powerpc: P1020RDB-PC: Separate from P1_P2_RDB_PC in Kconfig

[people/ms/u-boot.git] / include / configs / p1_p2_rdb_pc.h

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 596193d5c4cf41bcc803f4e1c7a02bbd315075b5..edb5395f28caddc5b14cee86ed73dc2c89b2ad77 100644 (file)
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -10,13 +10,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_DISPLAY_BOARDINFO
-
-#ifdef CONFIG_36BIT
-#define CONFIG_PHYS_64BIT
-#endif
-
-#if defined(CONFIG_P1020MBG)
+#if defined(CONFIG_TARGET_P1020MBG)
 #define CONFIG_BOARDNAME "P1020MBG-PC"
 #define CONFIG_P1020
 #define CONFIG_VSC7385_ENET
@@ -36,7 +30,7 @@
 #define CONFIG_SYS_L2_SIZE     (256 << 10)
 #endif
 
-#if defined(CONFIG_P1020RDB_PC)
+#if defined(CONFIG_TARGET_P1020RDB_PC)
 #define CONFIG_BOARDNAME "P1020RDB-PC"
 #define CONFIG_NAND_FSL_ELBC
 #define CONFIG_P1020
@@ -185,16 +179,9 @@
 #endif
 
 #ifdef CONFIG_SDCARD
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
 #define CONFIG_SPL_MMC_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
 #define CONFIG_SYS_TEXT_BASE           0x11001000
 #define CONFIG_SPL_TEXT_BASE           0xf8f81000
@@ -213,17 +200,9 @@
 #endif
 
 #ifdef CONFIG_SPIFLASH
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
 #define CONFIG_FSL_LAW         /* Use common FSL init code */
 #define CONFIG_SYS_TEXT_BASE           0x11001000
 #define CONFIG_SPL_TEXT_BASE           0xf8f81000
@@ -245,14 +224,7 @@
 #ifdef CONFIG_TPL_BUILD
 #define CONFIG_SPL_NAND_BOOT
 #define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_ENV_SUPPORT
 #define CONFIG_SPL_NAND_INIT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 #define CONFIG_SPL_COMMON_INIT_DDR
 #define CONFIG_SPL_MAX_SIZE            (128 << 10)
 #define CONFIG_SPL_TEXT_BASE           0xf8f81000
@@ -263,8 +235,6 @@
 #define CONFIG_SYS_NAND_U_BOOT_OFFS    ((128 + 128) << 10)
 #elif defined(CONFIG_SPL_BUILD)
 #define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
 #define CONFIG_SPL_TEXT_BASE           0xff800000
@@ -305,9 +275,8 @@
 #define CONFIG_MP
 
 #define CONFIG_FSL_ELBC
-#define CONFIG_PCI
-#define CONFIG_PCIE1   /* PCIE controler 1 (slot 1) */
-#define CONFIG_PCIE2   /* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE1   /* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2   /* PCIE controller 2 (slot 2) */
 #define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
 #define CONFIG_FSL_PCIE_RESET  /* need PCIe reset errata */
@@ -367,7 +336,7 @@
 #define SPD_EEPROM_ADDRESS 0x52
 #undef CONFIG_FSL_DDR_INTERACTIVE
 
-#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
+#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_P1020RDB_PD))
 #define CONFIG_SYS_SDRAM_SIZE_LAW      LAW_SIZE_2G
 #define CONFIG_CHIP_SELECTS_PER_CTRL   2
 #else
@@ -437,7 +406,7 @@
 /*
  * Local Bus Definitions
  */
-#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
+#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_P1020RDB_PD))
 #define CONFIG_SYS_MAX_FLASH_SECT      512     /* 64M */
 #define CONFIG_SYS_FLASH_BASE          0xec000000
 #elif defined(CONFIG_P1020UTM)
@@ -743,7 +712,6 @@
 #endif
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
 
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
 #define CONFIG_CMD_PCI
 
 #define CONFIG_PCI_SCAN_SHOW   /* show pci devices on startup */
@@ -882,7 +850,6 @@
 #ifdef CONFIG_USB_EHCI
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_USB_EHCI_FSL
-#define CONFIG_USB_STORAGE
 #endif
 #endif
 
@@ -944,7 +911,6 @@
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR        1000000
 
-#define CONFIG_BOOTDELAY 10    /* -1 disables auto-boot */
 #define CONFIG_BOOTARGS        /* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE        115200
@@ -990,7 +956,7 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset
 "consoledev=ttyS0\0"   \
 "ramdiskaddr=2000000\0"        \
 "ramdiskfile=rootfs.ext2.gz.uboot\0"   \
-"fdtaddr=c00000\0"     \
+"fdtaddr=1e00000\0"    \
 "bdev=sda1\0" \
 "jffs2nor=mtdblock3\0" \
 "norbootaddr=ef080000\0"       \