#ifndef __CONFIG_TI_OMAP5_COMMON_H
#define __CONFIG_TI_OMAP5_COMMON_H
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_798870
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/* Use General purpose timer 1 */
#define CONFIG_SYS_TIMERBASE GPT2_BASE
#define DFUARGS
#endif
-#ifndef CONFIG_SPL_BUILD
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
"setenv fdtfile omap5-uevm.dtb; fi; " \
"if test $board_name = dra7xx; then " \
"setenv fdtfile dra7-evm.dtb; fi;" \
+ "if test $board_name = dra72x-revc; then " \
+ "setenv fdtfile dra72-evm-revc.dtb; fi;" \
"if test $board_name = dra72x; then " \
"setenv fdtfile dra72-evm.dtb; fi;" \
"if test $board_name = beagle_x15; then " \
"setenv mmcroot /dev/mmcblk0p2 rw; " \
"run mmcboot;" \
""
-#endif
/*
* SPL related defines. The Public RAM memory map the ROM defines the
*/
#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ 0x1000
#define CONFIG_SPL_TEXT_BASE 0x40301350
+/* If no specific start address is specified then the secure EMIF
+ * region will be placed at the end of the DDR space. In order to prevent
+ * the main u-boot relocation from clobbering that memory and causing a
+ * firewall violation, we tell u-boot that memory is protected RAM (PRAM)
+ */
+#if (CONFIG_TI_SECURE_EMIF_REGION_START == 0)
+#define CONFIG_PRAM (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE) >> 10
+#endif
#else
/*
* For all booting on GP parts, the flash loader image is
#define CONFIG_SPL_TEXT_BASE 0x40300000
#endif
-/* DRA7xx/AM57xx have 512K of SRAM, OMAP5 only 128K */
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
-#define TI_ROM_BOOT_LOAD_END 0x4037E000
-#else
-#define TI_ROM_BOOT_LOAD_END 0x4031E000
-#endif
-#define CONFIG_SPL_MAX_SIZE (TI_ROM_BOOT_LOAD_END - CONFIG_SPL_TEXT_BASE)
-#define CONFIG_SPL_DISPLAY_PRINT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
(128 << 20))