#ifndef __FSL_ESDHC_H__
#define __FSL_ESDHC_H__
-#include <asm/errno.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
#include <asm/byteorder.h>
+/* needed for the mmc_cfg definition */
+#include <mmc.h>
+
+#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+#include "../board/freescale/common/qixis.h"
+#endif
+
/* FSL eSDHC-specific constants */
#define SYSCTL 0x0002e02c
#define SYSCTL_INITA 0x08000000
#define SYSCTL_TIMEOUT_MASK 0x000f0000
#define SYSCTL_CLOCK_MASK 0x0000fff0
+#if !defined(CONFIG_FSL_USDHC)
#define SYSCTL_CKEN 0x00000008
#define SYSCTL_PEREN 0x00000004
#define SYSCTL_HCKEN 0x00000002
#define SYSCTL_IPGEN 0x00000001
+#endif
#define SYSCTL_RSTA 0x01000000
#define SYSCTL_RSTC 0x02000000
#define SYSCTL_RSTD 0x04000000
+#define VENDORSPEC_CKEN 0x00004000
+#define VENDORSPEC_PEREN 0x00002000
+#define VENDORSPEC_HCKEN 0x00001000
+#define VENDORSPEC_IPGEN 0x00000800
+#define VENDORSPEC_INIT 0x20007809
+
#define IRQSTAT 0x0002e030
#define IRQSTAT_DMAE (0x10000000)
#define IRQSTAT_AC12E (0x01000000)
#define IRQSTATEN_TC (0x00000002)
#define IRQSTATEN_CC (0x00000001)
+#define ESDHCCTL 0x0002e40c
+#define ESDHCCTL_PCS (0x00080000)
+
#define PRSSTAT 0x0002e024
#define PRSSTAT_DAT0 (0x01000000)
#define PRSSTAT_CLSL (0x00800000)
#define PRSSTAT_CINS (0x00010000)
#define PRSSTAT_BREN (0x00000800)
#define PRSSTAT_BWEN (0x00000400)
+#define PRSSTAT_SDSTB (0X00000008)
#define PRSSTAT_DLA (0x00000004)
#define PRSSTAT_CICHB (0x00000002)
#define PRSSTAT_CIDHB (0x00000001)
#define XFERTYP_RSPTYP_48_BUSY 0x00030000
#define XFERTYP_MSBSEL 0x00000020
#define XFERTYP_DTDSEL 0x00000010
+#define XFERTYP_DDREN 0x00000008
#define XFERTYP_AC12EN 0x00000004
#define XFERTYP_BCEN 0x00000002
#define XFERTYP_DMAEN 0x00000001
#define CINS_TIMEOUT 1000
-#define PIO_TIMEOUT 100000
+#define PIO_TIMEOUT 500
#define DSADDR 0x2e004
#define ESDHC_HOSTCAPBLT_DMAS 0x00400000
#define ESDHC_HOSTCAPBLT_HSS 0x00200000
+#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
+
+/* Imported from Linux Kernel drivers/mmc/host/sdhci-esdhc-imx.c */
+#define MIX_CTRL_DDREN BIT(3)
+#define MIX_CTRL_DTDSEL_READ BIT(4)
+#define MIX_CTRL_AC23EN BIT(7)
+#define MIX_CTRL_EXE_TUNE BIT(22)
+#define MIX_CTRL_SMPCLK_SEL BIT(23)
+#define MIX_CTRL_AUTO_TUNE_EN BIT(24)
+#define MIX_CTRL_FBCLK_SEL BIT(25)
+#define MIX_CTRL_HS400_EN BIT(26)
+#define MIX_CTRL_HS400_ES BIT(27)
+/* Bits 3 and 6 are not SDHCI standard definitions */
+#define MIX_CTRL_SDHCI_MASK 0xb7
+/* Tuning bits */
+#define MIX_CTRL_TUNING_MASK 0x03c00000
+
+/* strobe dll register */
+#define ESDHC_STROBE_DLL_CTRL 0x70
+#define ESDHC_STROBE_DLL_CTRL_ENABLE BIT(0)
+#define ESDHC_STROBE_DLL_CTRL_RESET BIT(1)
+#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7
+#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
+
+#define ESDHC_STROBE_DLL_STATUS 0x74
+#define ESDHC_STROBE_DLL_STS_REF_LOCK BIT(1)
+#define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
+#define ESDHC_STROBE_DLL_CLK_FREQ 100000000
+
+#define ESDHC_STD_TUNING_EN BIT(24)
+/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
+#define ESDHC_TUNING_START_TAP_DEFAULT 0x1
+#define ESDHC_TUNING_START_TAP_MASK 0xff
+#define ESDHC_TUNING_STEP_MASK 0x00070000
+#define ESDHC_TUNING_STEP_SHIFT 16
+
+#define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
+#define ESDHC_FLAG_ENGCM07207 BIT(2)
+#define ESDHC_FLAG_USDHC BIT(3)
+#define ESDHC_FLAG_MAN_TUNING BIT(4)
+#define ESDHC_FLAG_STD_TUNING BIT(5)
+#define ESDHC_FLAG_HAVE_CAP1 BIT(6)
+#define ESDHC_FLAG_ERR004536 BIT(7)
+#define ESDHC_FLAG_HS200 BIT(8)
+#define ESDHC_FLAG_HS400 BIT(9)
+#define ESDHC_FLAG_ERR010450 BIT(10)
+#define ESDHC_FLAG_HS400_ES BIT(11)
+
struct fsl_esdhc_cfg {
- u32 esdhc_base;
+ phys_addr_t esdhc_base;
u32 sdhc_clk;
u8 max_bus_width;
+ int wp_enable;
+ int vs18_enable; /* Use 1.8V if set to 1 */
+ struct mmc_config cfg;
};
/* Select the correct accessors depending on endianess */
-#if __BYTE_ORDER == __LITTLE_ENDIAN
+#if defined CONFIG_SYS_FSL_ESDHC_LE
+#define esdhc_read32 in_le32
+#define esdhc_write32 out_le32
+#define esdhc_clrsetbits32 clrsetbits_le32
+#define esdhc_clrbits32 clrbits_le32
+#define esdhc_setbits32 setbits_le32
+#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
+#define esdhc_read32 in_be32
+#define esdhc_write32 out_be32
+#define esdhc_clrsetbits32 clrsetbits_be32
+#define esdhc_clrbits32 clrbits_be32
+#define esdhc_setbits32 setbits_be32
+#elif __BYTE_ORDER == __LITTLE_ENDIAN
#define esdhc_read32 in_le32
#define esdhc_write32 out_le32
#define esdhc_clrsetbits32 clrsetbits_le32
static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
#endif /* CONFIG_FSL_ESDHC */
void __noreturn mmc_boot(void);
+void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
#endif /* __FSL_ESDHC_H__ */
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