Convert CONFIG_BOOTCOUNT_ENV to Kconfig

[people/ms/u-boot.git] / include / fsl_immap.h

diff --git a/include/fsl_immap.h b/include/fsl_immap.h
index e4addada13045a714abe1de18643c1b02b183560..4f5a19cdc1abc835dbb88a61cb5a6aa8ce03354b 100644 (file)
--- a/include/fsl_immap.h
+++ b/include/fsl_immap.h
@@ -131,7 +131,57 @@ struct ccsr_ddr {
        u32     capture_ext_address;    /* Error Extended Addr Capture */
        u32     err_sbe;                /* Single-Bit ECC Error Management */
        u8      res_e5c[164];
-       u32     debug[32];              /* debug_1 to debug_32 */
-       u8      res_f80[128];
+       u32     debug[64];              /* debug_1 to debug_64 */
 };
+
+#ifdef CONFIG_SYS_FSL_HAS_CCI400
+#define CCI400_CTRLORD_TERM_BARRIER    0x00000008
+#define CCI400_CTRLORD_EN_BARRIER      0
+#define CCI400_SHAORD_NON_SHAREABLE    0x00000002
+#define CCI400_DVM_MESSAGE_REQ_EN      0x00000002
+#define CCI400_SNOOP_REQ_EN            0x00000001
+
+/* CCI-400 registers */
+struct ccsr_cci400 {
+       u32 ctrl_ord;                   /* Control Override */
+       u32 spec_ctrl;                  /* Speculation Control */
+       u32 secure_access;              /* Secure Access */
+       u32 status;                     /* Status */
+       u32 impr_err;                   /* Imprecise Error */
+       u8 res_14[0x100 - 0x14];
+       u32 pmcr;                       /* Performance Monitor Control */
+       u8 res_104[0xfd0 - 0x104];
+       u32 pid[8];                     /* Peripheral ID */
+       u32 cid[4];                     /* Component ID */
+       struct {
+               u32 snoop_ctrl;         /* Snoop Control */
+               u32 sha_ord;            /* Shareable Override */
+               u8 res_1008[0x1100 - 0x1008];
+               u32 rc_qos_ord;         /* read channel QoS Value Override */
+               u32 wc_qos_ord;         /* read channel QoS Value Override */
+               u8 res_1108[0x110c - 0x1108];
+               u32 qos_ctrl;           /* QoS Control */
+               u32 max_ot;             /* Max OT */
+               u8 res_1114[0x1130 - 0x1114];
+               u32 target_lat;         /* Target Latency */
+               u32 latency_regu;       /* Latency Regulation */
+               u32 qos_range;          /* QoS Range */
+               u8 res_113c[0x2000 - 0x113c];
+       } slave[5];                     /* Slave Interface */
+       u8 res_6000[0x9004 - 0x6000];
+       u32 cycle_counter;              /* Cycle counter */
+       u32 count_ctrl;                 /* Count Control */
+       u32 overflow_status;            /* Overflow Flag Status */
+       u8 res_9010[0xa000 - 0x9010];
+       struct {
+               u32 event_select;       /* Event Select */
+               u32 event_count;        /* Event Count */
+               u32 counter_ctrl;       /* Counter Control */
+               u32 overflow_status;    /* Overflow Flag Status */
+               u8 res_a010[0xb000 - 0xa010];
+       } pcounter[4];                  /* Performance Counter */
+       u8 res_e004[0x10000 - 0xe004];
+};
+#endif
+
 #endif /* __FSL_IMMAP_H */