NAND: Fix integer overflow in ONFI detection of chips >= 4GiB

[people/ms/u-boot.git] / include / mpc8xx.h

diff --git a/include/mpc8xx.h b/include/mpc8xx.h
index 29117589be9983db9d0114853d29d64fa6183c42..bef748f90039dd3d05759593cee88ffa3813fda4 100644 (file)
--- a/include/mpc8xx.h
+++ b/include/mpc8xx.h
@@ -35,7 +35,7 @@
  * Exception offsets (PowerPC standard)
  */
 #define EXC_OFF_SYS_RESET      0x0100  /* System reset                         */
-
+#define _START_OFFSET          EXC_OFF_SYS_RESET
 
 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control Register                          11-9
@@ -208,12 +208,12 @@
 #define SCCR_DFBRG10   0x00001000      /* BRGCLK division by 16                */
 #define SCCR_DFBRG11   0x00001800      /* BRGCLK division by 64                */
 #define SCCR_DFNL000   0x00000000      /* Division by 2 (default = minimum)    */
-#define SCCR_DFNL001   0x00000100      /* Division by 4                        */
-#define SCCR_DFNL010   0x00000200      /* Division by 8                        */
-#define SCCR_DFNL011   0x00000300      /* Division by 16                       */
-#define SCCR_DFNL100   0x00000400      /* Division by 32                       */
-#define SCCR_DFNL101   0x00000500      /* Division by 64                       */
-#define SCCR_DFNL110   0x00000600      /* Division by 128                      */
+#define SCCR_DFNL001   0x00000100      /* Division by 4                        */
+#define SCCR_DFNL010   0x00000200      /* Division by 8                        */
+#define SCCR_DFNL011   0x00000300      /* Division by 16                       */
+#define SCCR_DFNL100   0x00000400      /* Division by 32                       */
+#define SCCR_DFNL101   0x00000500      /* Division by 64                       */
+#define SCCR_DFNL110   0x00000600      /* Division by 128                      */
 #define SCCR_DFNL111   0x00000700      /* Division by 256 (maximum)            */
 #define SCCR_DFNH000   0x00000000      /* Division by 1 (default = minimum)    */
 #define SCCR_DFNH110   0x000000D0      /* Division by 64 (maximum)             */