NAND: Fix integer overflow in ONFI detection of chips >= 4GiB

[people/ms/u-boot.git] / include / mpc8xx.h

diff --git a/include/mpc8xx.h b/include/mpc8xx.h
index 847c2b4b6b9a97c4ab78688e6b522109fe720d30..bef748f90039dd3d05759593cee88ffa3813fda4 100644 (file)
--- a/include/mpc8xx.h
+++ b/include/mpc8xx.h
@@ -35,7 +35,7 @@
  * Exception offsets (PowerPC standard)
  */
 #define EXC_OFF_SYS_RESET      0x0100  /* System reset                         */
-
+#define _START_OFFSET          EXC_OFF_SYS_RESET
 
 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control Register                          11-9
@@ -131,11 +131,16 @@
 
 #define RSR_ALLBITS    (RSR_JTRS|RSR_DBSRS|RSR_DBHRS|RSR_CSRS|RSR_SWRS|RSR_LLRS|RSR_ESRS|RSR_EHRS)
 
+/*-----------------------------------------------------------------------
+ * Newer chips (MPC866 family and MPC87x/88x family) have different
+ * clock distribution system. Their IMMR lower half is >= 0x0800
+ */
+#define MPC8xx_NEW_CLK 0x0800
+
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register                 15-30
  */
-#ifdef CONFIG_MPC866_et_al
-#define PLPRCR_MF_MSK  0xFFFF001E      /* Multiplication factor + PDF bits     */
+/* Newer chips (MPC866/87x/88x et al) defines */
 #define PLPRCR_MFN_MSK 0xF8000000      /* Multiplication factor numerator bits */
 #define PLPRCR_MFN_SHIFT       27      /* Multiplication factor numerator shift*/
 #define PLPRCR_MFD_MSK 0x07C00000      /* Multiplication factor denominator bits */
@@ -144,32 +149,39 @@
 #define PLPRCR_S_SHIFT         20      /* Multiplication factor integer shift  */
 #define PLPRCR_MFI_MSK 0x000F0000      /* Multiplication factor integer bits   */
 #define PLPRCR_MFI_SHIFT       16      /* Multiplication factor integer shift  */
-#else
+
+#define PLPRCR_PDF_MSK 0x0000001E      /* Predivision Factor bits              */
+#define PLPRCR_PDF_SHIFT        1      /* Predivision Factor shift value       */
+#define PLPRCR_DBRMO   0x00000001      /* DPLL BRM Order bit                   */
+
+/* Multiplication factor + PDF bits */
+#define PLPRCR_MFACT_MSK (PLPRCR_MFN_MSK | \
+                         PLPRCR_MFD_MSK | \
+                         PLPRCR_S_MSK   | \
+                         PLPRCR_MFI_MSK | \
+                         PLPRCR_PDF_MSK)
+
+/* Older chips (MPC860/862 et al) defines */
 #define PLPRCR_MF_MSK  0xFFF00000      /* Multiplication factor bits           */
 #define PLPRCR_MF_SHIFT                20      /* Multiplication factor shift value    */
-#endif
+
 #define PLPRCR_SPLSS   0x00008000      /* SPLL Lock Status Sticky bit          */
-#define PLPRCR_TEXPS   0x00004000      /* TEXP Status                          */
-#ifndef CONFIG_MPC866_et_al
 #define PLPRCR_TMIST   0x00001000      /* Timers Interrupt Status              */
-#endif
-#define PLPRCR_CSRC    0x00000400      /* Clock Source                         */
-#ifndef CONFIG_MPC866_et_al
+
 #define PLPRCR_LPM_MSK 0x00000300      /* Low Power Mode mask                  */
 #define PLPRCR_LPM_NORMAL 0x00000000   /* normal power management mode         */
 #define PLPRCR_LPM_DOZE          0x00000100    /* doze power management mode           */
 #define PLPRCR_LPM_SLEEP  0x00000200   /* sleep power management mode          */
 #define PLPRCR_LPM_DEEP_SLEEP 0x00000300 /* deep sleep power mgt mode          */
 #define PLPRCR_LPM_DOWN          0x00000300    /* down power management mode           */
-#endif
+
+/* Common defines */
+#define PLPRCR_TEXPS   0x00004000      /* TEXP Status                          */
+#define PLPRCR_CSRC    0x00000400      /* Clock Source                         */
+
 #define PLPRCR_CSR     0x00000080      /* CheskStop Reset value                */
 #define PLPRCR_LOLRE   0x00000040      /* Loss Of Lock Reset Enable            */
 #define PLPRCR_FIOPD   0x00000020      /* Force I/O Pull Down                  */
-#ifdef CONFIG_MPC866_et_al
-#define PLPRCR_PDF_MSK 0x0000001E      /* Predivision Factor bits              */
-#define PLPRCR_PDF_SHIFT        1      /* Predivision Factor shift value       */
-#define PLPRCR_DBRMO   0x00000001      /* DPLL BRM Order bit                   */
-#endif
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register                      15-27
@@ -196,6 +208,12 @@
 #define SCCR_DFBRG10   0x00001000      /* BRGCLK division by 16                */
 #define SCCR_DFBRG11   0x00001800      /* BRGCLK division by 64                */
 #define SCCR_DFNL000   0x00000000      /* Division by 2 (default = minimum)    */
+#define SCCR_DFNL001   0x00000100      /* Division by 4                        */
+#define SCCR_DFNL010   0x00000200      /* Division by 8                        */
+#define SCCR_DFNL011   0x00000300      /* Division by 16                       */
+#define SCCR_DFNL100   0x00000400      /* Division by 32                       */
+#define SCCR_DFNL101   0x00000500      /* Division by 64                       */
+#define SCCR_DFNL110   0x00000600      /* Division by 128                      */
 #define SCCR_DFNL111   0x00000700      /* Division by 256 (maximum)            */
 #define SCCR_DFNH000   0x00000000      /* Division by 1 (default = minimum)    */
 #define SCCR_DFNH110   0x000000D0      /* Division by 64 (maximum)             */