extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
#endif
+#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
pci_addr_t addr, unsigned long flags);
extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
/* For driver model these are defined in macros in pci_compat.c */
-#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
extern int pci_hose_read_config_byte(struct pci_controller *hose,
pci_dev_t dev, int where, u8 *val);
extern int pci_hose_read_config_word(struct pci_controller *hose,
extern void pci_register_hose(struct pci_controller* hose);
extern struct pci_controller* pci_bus_to_hose(int bus);
extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
+extern struct pci_controller *pci_get_hose_head(void);
extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
extern int pci_hose_scan(struct pci_controller *hose);
/**
* pci_write_bar32() - Write the address of a BAR including control bits
*
- * This writes a raw address (with control bits) to a bar
+ * This writes a raw address (with control bits) to a bar. This can be used
+ * with devices which require hard-coded addresses, not part of the normal
+ * PCI enumeration process.
*
* @hose: PCI hose to use
* @dev: PCI device to update
* @addr: BAR address with control bits
*/
void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
- u32 addr_and_ctrl);
+ u32 addr);
/**
* pci_read_bar32() - read the address of a bar
*
* @bus: Bus to read from
* @bdf: PCI device address: bus, device and function -see PCI_BDF()
+ * @offset: Register offset to read
* @valuep: Place to put the returned value
* @size: Access size
* @return 0 if OK, -ve on error
*
* @bus: Bus to write from
* @bdf: PCI device address: bus, device and function -see PCI_BDF()
+ * @offset: Register offset to write
* @value: Value to write
* @size: Access size
* @return 0 if OK, -ve on error
int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
unsigned long value, enum pci_size_t size);
+/**
+ * pci_bus_clrset_config32() - Update a configuration value for a device
+ *
+ * The register at @offset is updated to (oldvalue & ~clr) | set.
+ *
+ * @bus: Bus to access
+ * @bdf: PCI device address: bus, device and function -see PCI_BDF()
+ * @offset: Register offset to update
+ * @clr: Bits to clear
+ * @set: Bits to set
+ * @return 0 if OK, -ve on error
+ */
+int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
+ u32 clr, u32 set);
+
/**
* Driver model PCI config access functions. Use these in preference to others
* when you have a valid device
int dm_pci_write_config16(struct udevice *dev, int offset, u16 value);
int dm_pci_write_config32(struct udevice *dev, int offset, u32 value);
+/**
+ * These permit convenient read/modify/write on PCI configuration. The
+ * register is updated to (oldvalue & ~clr) | set.
+ */
+int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set);
+int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set);
+int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set);
+
/*
* The following functions provide access to the above without needing the
* size parameter. We are trying to encourage the use of the 8/16/32-style
* functions, rather than byte/word/dword. But both are supported.
*/
int pci_write_config32(pci_dev_t pcidev, int offset, u32 value);
+int pci_write_config16(pci_dev_t pcidev, int offset, u16 value);
+int pci_write_config8(pci_dev_t pcidev, int offset, u8 value);
+int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep);
+int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);
+int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
#ifdef CONFIG_DM_PCI_COMPAT
/* Compatibility with old naming */
return pci_write_config32(pcidev, offset, value);
}
-int pci_write_config16(pci_dev_t pcidev, int offset, u16 value);
-
/* Compatibility with old naming */
static inline int pci_write_config_word(pci_dev_t pcidev, int offset,
u16 value)
return pci_write_config16(pcidev, offset, value);
}
-int pci_write_config8(pci_dev_t pcidev, int offset, u8 value);
-
/* Compatibility with old naming */
static inline int pci_write_config_byte(pci_dev_t pcidev, int offset,
u8 value)
return pci_write_config8(pcidev, offset, value);
}
-int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep);
-
/* Compatibility with old naming */
static inline int pci_read_config_dword(pci_dev_t pcidev, int offset,
u32 *valuep)
return pci_read_config32(pcidev, offset, valuep);
}
-int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);
-
/* Compatibility with old naming */
static inline int pci_read_config_word(pci_dev_t pcidev, int offset,
u16 *valuep)
return pci_read_config16(pcidev, offset, valuep);
}
-int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
-
/* Compatibility with old naming */
static inline int pci_read_config_byte(pci_dev_t pcidev, int offset,
u8 *valuep)
{
return pci_read_config8(pcidev, offset, valuep);
}
-
#endif /* CONFIG_DM_PCI_COMPAT */
/**
int pci_get_regions(struct udevice *dev, struct pci_region **iop,
struct pci_region **memp, struct pci_region **prefp);
+/**
+ * dm_pci_write_bar32() - Write the address of a BAR
+ *
+ * This writes a raw address to a bar
+ *
+ * @dev: PCI device to update
+ * @barnum: BAR number (0-5)
+ * @addr: BAR address
+ */
+void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr);
+
/**
* dm_pci_read_bar32() - read a base address register from a device
*
*/
u32 dm_pci_read_bar32(struct udevice *dev, int barnum);
+/**
+ * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address
+ *
+ * @dev: Device containing the PCI address
+ * @addr: PCI address to convert
+ * @flags: Flags for the region type (PCI_REGION_...)
+ * @return physical address corresponding to that PCI bus address
+ */
+phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr,
+ unsigned long flags);
+
+/**
+ * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address
+ *
+ * @dev: Device containing the bus address
+ * @addr: Physical address to convert
+ * @flags: Flags for the region type (PCI_REGION_...)
+ * @return PCI bus address corresponding to that physical address
+ */
+pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr,
+ unsigned long flags);
+
+/**
+ * dm_pci_map_bar() - get a virtual address associated with a BAR region
+ *
+ * Looks up a base address register and finds the physical memory address
+ * that corresponds to it
+ *
+ * @dev: Device to check
+ * @bar: Bar number to read (numbered from 0)
+ * @flags: Flags for the region type (PCI_REGION_...)
+ * @return: pointer to the virtual address to use
+ */
+void *dm_pci_map_bar(struct udevice *dev, int bar, int flags);
+
+#define dm_pci_virt_to_bus(dev, addr, flags) \
+ dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags))
+#define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \
+ map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \
+ (len), (map_flags))
+
+#define dm_pci_phys_to_mem(dev, addr) \
+ dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
+#define dm_pci_mem_to_phys(dev, addr) \
+ dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
+#define dm_pci_phys_to_io(dev, addr) \
+ dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
+#define dm_pci_io_to_phys(dev, addr) \
+ dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
+
+#define dm_pci_virt_to_mem(dev, addr) \
+ dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
+#define dm_pci_mem_to_virt(dev, addr, len, map_flags) \
+ dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
+#define dm_pci_virt_to_io(dev, addr) \
+ dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
+#define dm_pci_io_to_virt(dev, addr, len, map_flags) \
+ dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
+
/**
* dm_pci_find_device() - find a device by vendor/device ID
*
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