drivers, block: remove sil680 driver

[people/ms/u-boot.git] / post / cpu / ppc4xx / cache_4xx.S

diff --git a/post/cpu/ppc4xx/cache_4xx.S b/post/cpu/ppc4xx/cache_4xx.S
index 785b8d60b93a5422c63919539d4009fd375089ed..15a133cfa8e2b8ad3fbbb9aed33ac7a6fd9bad96 100644 (file)
--- a/post/cpu/ppc4xx/cache_4xx.S
+++ b/post/cpu/ppc4xx/cache_4xx.S
@@ -4,39 +4,28 @@
  *
  * Author: Igor Lisitsin <igor@emcraft.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <config.h>
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 #include <asm/cache.h>
 #include <asm/mmu.h>
 
-#if CONFIG_POST & CFG_POST_CACHE
+#if CONFIG_POST & CONFIG_SYS_POST_CACHE
 
        .text
 
+       /*
+        * All 44x variants deal with cache management differently
+        * because they have the address translation always enabled.
+        * The 40x ppc's don't use address translation in U-Boot at all,
+        * so we have to distinguish here between 40x and 44x.
+        */
+#ifdef CONFIG_440
 /* void cache_post_disable (int tlb)
  */
 cache_post_disable:
@@ -68,13 +57,50 @@ cache_post_wb:
        sync
        isync
        blr
+#else
+/* void cache_post_disable (int tlb)
+ */
+cache_post_disable:
+       lis     r0, 0x0000
+       ori     r0, r0, 0x0000
+       mtdccr  r0
+       sync
+       isync
+       blr
+
+/* void cache_post_wt (int tlb)
+ */
+cache_post_wt:
+       lis     r0, 0x8000
+       ori     r0, r0, 0x0000
+       mtdccr  r0
+       lis     r0, 0x8000
+       ori     r0, r0, 0x0000
+       mtdcwr  r0
+       sync
+       isync
+       blr
+
+/* void cache_post_wb (int tlb)
+ */
+cache_post_wb:
+       lis     r0, 0x8000
+       ori     r0, r0, 0x0000
+       mtdccr  r0
+       lis     r0, 0x0000
+       ori     r0, r0, 0x0000
+       mtdcwr  r0
+       sync
+       isync
+       blr
+#endif
 
 /* void cache_post_dinvalidate (void *p, int size)
  */
 cache_post_dinvalidate:
        dcbi    r0, r3
-       addi    r3, r3, CFG_CACHELINE_SIZE
-       subic.  r4, r4, CFG_CACHELINE_SIZE
+       addi    r3, r3, CONFIG_SYS_CACHELINE_SIZE
+       subic.  r4, r4, CONFIG_SYS_CACHELINE_SIZE
        bgt     cache_post_dinvalidate
        sync
        blr
@@ -83,8 +109,8 @@ cache_post_dinvalidate:
  */
 cache_post_dstore:
        dcbst   r0, r3
-       addi    r3, r3, CFG_CACHELINE_SIZE
-       subic.  r4, r4, CFG_CACHELINE_SIZE
+       addi    r3, r3, CONFIG_SYS_CACHELINE_SIZE
+       subic.  r4, r4, CONFIG_SYS_CACHELINE_SIZE
        bgt     cache_post_dstore
        sync
        blr
@@ -93,8 +119,8 @@ cache_post_dstore:
  */
 cache_post_dtouch:
        dcbt    r0, r3
-       addi    r3, r3, CFG_CACHELINE_SIZE
-       subic.  r4, r4, CFG_CACHELINE_SIZE
+       addi    r3, r3, CONFIG_SYS_CACHELINE_SIZE
+       subic.  r4, r4, CONFIG_SYS_CACHELINE_SIZE
        bgt     cache_post_dtouch
        sync
        blr
@@ -438,11 +464,10 @@ cache_post_test6_reloc:
        blr
 
 /* Test instructions.
- */    
+ */
 cache_post_test_inst:
        li      r3, 0
        li      r3, -1
        blr
 
-#endif /* CONFIG_POST & CFG_POST_CACHE */
-#endif /* CONFIG_POST */
+#endif /* CONFIG_POST & CONFIG_SYS_POST_CACHE */