X-Git-Url: http://git.ipfire.org/?p=people%2Fms%2Fu-boot.git;a=blobdiff_plain;f=README;h=2abba91b6475d0781e1791336f6e5a37d3966cbc;hp=075d919df3fee00e6c486e65344b1c1d61338422;hb=97a63144a906827ad7e3c4ef18d641c2765b1ebc;hpb=b07d044d5bfa8c440b172eb3f8a9d537f82e21b6 diff --git a/README b/README index 075d919df3..2abba91b64 100644 --- a/README +++ b/README @@ -328,34 +328,6 @@ The following options need to be configured: multiple fs option at one time for marvell soc family -- 8xx CPU Options: (if using an MPC8xx CPU) - CONFIG_8xx_GCLK_FREQ - deprecated: CPU clock if - get_gclk_freq() cannot work - e.g. if there is no 32KHz - reference PIT/RTC clock - CONFIG_8xx_OSCLK - PLL input clock (either EXTCLK - or XTAL/EXTAL) - -- 859/866/885 CPU options: (if using a MPC859 or MPC866 or MPC885 CPU): - CONFIG_SYS_8xx_CPUCLK_MIN - CONFIG_SYS_8xx_CPUCLK_MAX - CONFIG_8xx_CPUCLK_DEFAULT - See doc/README.MPC866 - - CONFIG_SYS_MEASURE_CPUCLK - - Define this to measure the actual CPU clock instead - of relying on the correctness of the configured - values. Mostly useful for board bringup to make sure - the PLL is locked at the intended frequency. Note - that this requires a (stable) reference clock (32 kHz - RTC clock or CONFIG_SYS_8XX_XIN) - - CONFIG_SYS_DELAYED_ICACHE - - Define this option if you want to enable the - ICache only when Code runs from RAM. - - 85xx CPU Options: CONFIG_SYS_PPC64 @@ -636,10 +608,6 @@ The following options need to be configured: * Adds the "fdt" command * The bootm command automatically updates the fdt - OF_CPU - The proper name of the cpus node (only required for - MPC512X and MPC5xxx based boards). - OF_SOC - The proper name of the soc node (only required for - MPC512X and MPC5xxx based boards). OF_TBCLK - The timebase frequency. OF_STDOUT_PATH - The path to the console device @@ -723,29 +691,10 @@ The following options need to be configured: Define this variable to enable hw flow control in serial driver. Current user of this option is drivers/serial/nsl16550.c driver -- Console Interface: - Depending on board, define exactly one serial port - (like CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2, - CONFIG_8xx_CONS_SCC1, ...), or switch off the serial - console by defining CONFIG_8xx_CONS_NONE - - Note: if CONFIG_8xx_CONS_NONE is defined, the serial - port routines must be defined elsewhere - (i.e. serial_init(), serial_getc(), ...) - - Console Baudrate: CONFIG_BAUDRATE - in bps Select one of the baudrates listed in CONFIG_SYS_BAUDRATE_TABLE, see below. - CONFIG_SYS_BRGCLK_PRESCALE, baudrate prescale - -- Console Rx buffer length - With CONFIG_SYS_SMC_RXBUFLEN it is possible to define - the maximum receive buffer length for the SMC. - This option is actual only for 82xx and 8xx possible. - If using CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE - must be defined, to setup the maximum idle timeout for - the SMC. - Autoboot Command: CONFIG_BOOTCOMMAND @@ -912,7 +861,7 @@ The following options need to be configured: Note: Don't enable the "icache" and "dcache" commands (configuration option CONFIG_CMD_CACHE) unless you know what you (and your U-Boot users) are doing. Data - cache cannot be enabled on systems like the 8xx or + cache cannot be enabled on systems like the 8260 (where accesses to the IMMR region must be uncached), and it cannot be disabled on all other systems where we (mis-) use the data cache to hold an @@ -976,11 +925,9 @@ The following options need to be configured: CONFIG_WATCHDOG If this variable is defined, it enables watchdog support for the SoC. There must be support in the SoC - specific code for a watchdog. For the 8xx and 8260 - CPUs, the SIU Watchdog feature is enabled in the SYPCR - register. When supported for a specific SoC is - available, then no further board specific code should - be needed to use it. + specific code for a watchdog. When supported for a + specific SoC is available, then no further board specific + code should be needed to use it. CONFIG_HW_WATCHDOG When using a watchdog circuitry external to the used @@ -1004,7 +951,6 @@ The following options need to be configured: has to be selected, too. Define exactly one of the following options: - CONFIG_RTC_MPC8xx - use internal RTC of MPC8xx CONFIG_RTC_PCF8563 - use Philips PCF8563 RTC CONFIG_RTC_MC13XXX - use MC13783 or MC13892 RTC CONFIG_RTC_MC146818 - use MC146818 RTC @@ -1015,7 +961,7 @@ The following options need to be configured: CONFIG_RTC_DS164x - use Dallas DS164x RTC CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC - CONFIG_SYS_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337 + CONFIG_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337 CONFIG_SYS_RV3029_TCR - enable trickle charger on RV3029 RTC. @@ -1282,7 +1228,7 @@ The following options need to be configured: - USB Support: At the moment only the UHCI host controller is - supported (PIP405, MIP405, MPC5200); define + supported (PIP405, MIP405); define CONFIG_USB_UHCI to enable it. define CONFIG_USB_KEYBOARD to enable the USB Keyboard and define CONFIG_USB_STORAGE to enable the USB @@ -1290,19 +1236,6 @@ The following options need to be configured: Note: Supported are USB Keyboards and USB Floppy drives (TEAC FD-05PUB). - MPC5200 USB requires additional defines: - CONFIG_USB_CLOCK - for 528 MHz Clock: 0x0001bbbb - CONFIG_PSC3_USB - for USB on PSC3 - CONFIG_USB_CONFIG - for differential drivers: 0x00001000 - for single ended drivers: 0x00005000 - for differential drivers on PSC3: 0x00000100 - for single ended drivers on PSC3: 0x00004100 - CONFIG_SYS_USB_EVENT_POLL - May be defined to allow interrupt polling - instead of using asynchronous interrupts CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the txfilltuning field in the EHCI controller on reset. @@ -1345,11 +1278,6 @@ The following options need to be configured: Define this if you want stdin, stdout &/or stderr to be set to usbtty. - mpc8xx: - CONFIG_SYS_USB_EXTC_CLK 0xBLAH - Derive USB clock from external clock "blah" - - CONFIG_SYS_USB_EXTC_CLK 0x02 - If you have a USB-IF assigned VendorID then you may wish to define your own vendor specific values either in BoardName.h or directly in usbd_vendor_info.h. If you don't define @@ -1949,12 +1877,6 @@ The following options need to be configured: In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined with a list of GPIO LEDs that have inverted polarity. -- CAN Support: CONFIG_CAN_DRIVER - - Defining CONFIG_CAN_DRIVER enables CAN driver support - on those systems that support this (optional) - feature, like the TQM8xxL modules. - - I2C Support: CONFIG_SYS_I2C This enable the NEW i2c subsystem, and will allow you to use @@ -2153,12 +2075,6 @@ The following options need to be configured: eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) - I2C_PORT - - (Only for MPC8260 CPU). The I/O port to use (the code - assumes both bits are on the same port). Valid values - are 0..3 for ports A..D. - I2C_ACTIVE The code necessary to make the I2C data line active @@ -2445,9 +2361,9 @@ The following options need to be configured: following board configurations are known to be "pRAM-clean": - IVMS8, IVML24, SPD8xx, TQM8xxL, + IVMS8, IVML24, SPD8xx, HERMES, IP860, RPXlite, LWMON, - FLAGADM, TQM8260 + FLAGADM - Access to physical memory region (> 4GB) Some basic support is provided for operations on memory not @@ -2618,12 +2534,6 @@ The following options need to be configured: Define this option to include a destructive SPI flash test ('sf test'). - CONFIG_SF_DUAL_FLASH Dual flash memories - - Define this option to use dual flash support where two flash - memories can be connected with a given cs line. - Currently Xilinx Zynq qspi supports these type of connections. - - SystemACE Support: CONFIG_SYSTEMACE @@ -3905,16 +3815,6 @@ but it can not erase, write this NOR flash by SRIO or PCIE interface. set. If this value is set, it must be set to the same value as CONFIG_ENV_SIZE. -- CONFIG_SYS_SPI_INIT_OFFSET - - Defines offset to the initial SPI buffer area in DPRAM. The - area is used at an early stage (ROM part) if the environment - is configured to reside in the SPI EEPROM: We need a 520 byte - scratch DPRAM area. It is used between the two initialization - calls (spi_init_f() and spi_init_r()). A value of 0xB00 seems - to be a good choice since it makes it far enough from the - start of the data area as well as from the stack pointer. - Please note that the environment is read-only until the monitor has been relocated to RAM and a RAM copy of the environment has been created; also, when using EEPROM you will have to use getenv_f() @@ -3968,13 +3868,6 @@ Low Level (hardware related) configuration options: - CONFIG_SYS_CACHELINE_SIZE: Cache Line Size of the CPU. -- CONFIG_SYS_DEFAULT_IMMR: - Default address of the IMMR after system reset. - - Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU, - and RPXsuper) to be able to adjust the position of - the IMMR register after a reset. - - CONFIG_SYS_CCSRBAR_DEFAULT: Default (power-on reset) physical address of CCSR on Freescale PowerPC SOCs. @@ -3983,9 +3876,6 @@ Low Level (hardware related) configuration options: Virtual address of CCSR. On a 32-bit build, this is typically the same value as CONFIG_SYS_CCSRBAR_DEFAULT. - CONFIG_SYS_DEFAULT_IMMR must also be set to this value, - for cross-platform code that uses that macro instead. - - CONFIG_SYS_CCSRBAR_PHYS: Physical address of CCSR. CCSR can be relocated to a new physical address, if desired. In this case, this macro should @@ -4048,7 +3938,7 @@ Low Level (hardware related) configuration options: - CONFIG_SYS_IMMR: Physical address of the Internal Memory. DO NOT CHANGE unless you know exactly what you're - doing! (11-4) [MPC8xx/82xx systems only] + doing! (11-4) [82xx systems only] - CONFIG_SYS_INIT_RAM_ADDR: @@ -4061,8 +3951,6 @@ Low Level (hardware related) configuration options: sequences. U-Boot uses the following memory types: - - MPC8xx and MPC8260: IMMR (internal memory of the CPU) - - MPC824X: data cache - PPC4xx: data cache - CONFIG_SYS_GBL_DATA_OFFSET: @@ -4083,16 +3971,6 @@ Low Level (hardware related) configuration options: point to an otherwise UNUSED address space between the top of RAM and the start of the PCI space. -- CONFIG_SYS_SIUMCR: SIU Module Configuration (11-6) - -- CONFIG_SYS_SYPCR: System Protection Control (11-9) - -- CONFIG_SYS_TBSCR: Time Base Status and Control (11-26) - -- CONFIG_SYS_PISCR: Periodic Interrupt Status and Control (11-31) - -- CONFIG_SYS_PLPRCR: PLL, Low-Power, and Reset Control Register (15-30) - - CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27) - CONFIG_SYS_OR_TIMING_SDRAM: @@ -4101,8 +3979,6 @@ Low Level (hardware related) configuration options: - CONFIG_SYS_MAMR_PTA: periodic timer for refresh -- CONFIG_SYS_DER: Debug Event Register (37-47) - - FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM, CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP, CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM, @@ -4114,39 +3990,6 @@ Low Level (hardware related) configuration options: CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM: Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM) -- CONFIG_SYS_MAMR_PTA, CONFIG_SYS_MPTPR_2BK_4K, CONFIG_SYS_MPTPR_1BK_4K, CONFIG_SYS_MPTPR_2BK_8K, - CONFIG_SYS_MPTPR_1BK_8K, CONFIG_SYS_MAMR_8COL, CONFIG_SYS_MAMR_9COL: - Machine Mode Register and Memory Periodic Timer - Prescaler definitions (SDRAM timing) - -- CONFIG_SYS_I2C_UCODE_PATCH, CONFIG_SYS_I2C_DPMEM_OFFSET [0x1FC0]: - enable I2C microcode relocation patch (MPC8xx); - define relocation offset in DPRAM [DSP2] - -- CONFIG_SYS_SMC_UCODE_PATCH, CONFIG_SYS_SMC_DPMEM_OFFSET [0x1FC0]: - enable SMC microcode relocation patch (MPC8xx); - define relocation offset in DPRAM [SMC1] - -- CONFIG_SYS_SPI_UCODE_PATCH, CONFIG_SYS_SPI_DPMEM_OFFSET [0x1FC0]: - enable SPI microcode relocation patch (MPC8xx); - define relocation offset in DPRAM [SCC4] - -- CONFIG_SYS_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only) - Offset of the bootmode word in DPRAM used by post - (Power On Self Tests). This definition overrides - #define'd default value in commproc.h resp. - cpm_8260.h. - -- CONFIG_SYS_PCI_SLV_MEM_LOCAL, CONFIG_SYS_PCI_SLV_MEM_BUS, CONFIG_SYS_PICMR0_MASK_ATTRIB, - CONFIG_SYS_PCI_MSTR0_LOCAL, CONFIG_SYS_PCIMSK0_MASK, CONFIG_SYS_PCI_MSTR1_LOCAL, - CONFIG_SYS_PCIMSK1_MASK, CONFIG_SYS_PCI_MSTR_MEM_LOCAL, CONFIG_SYS_PCI_MSTR_MEM_BUS, - CONFIG_SYS_CPU_PCI_MEM_START, CONFIG_SYS_PCI_MSTR_MEM_SIZE, CONFIG_SYS_POCMR0_MASK_ATTRIB, - CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL, CONFIG_SYS_PCI_MSTR_MEMIO_BUS, CPU_PCI_MEMIO_START, - CONFIG_SYS_PCI_MSTR_MEMIO_SIZE, CONFIG_SYS_POCMR1_MASK_ATTRIB, CONFIG_SYS_PCI_MSTR_IO_LOCAL, - CONFIG_SYS_PCI_MSTR_IO_BUS, CONFIG_SYS_CPU_PCI_IO_START, CONFIG_SYS_PCI_MSTR_IO_SIZE, - CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only) - Overrides the default PCI memory map in arch/powerpc/cpu/mpc8260/pci.c if set. - - CONFIG_PCI_DISABLE_PCIE: Disable PCI-Express on systems where it is supported but not required. @@ -4225,21 +4068,6 @@ Low Level (hardware related) configuration options: Only for 83xx systems. If specified, then DDR should be configured using CS0 and CS1 instead of CS2 and CS3. -- CONFIG_ETHER_ON_FEC[12] - Define to enable FEC[12] on a 8xx series processor. - -- CONFIG_FEC[12]_PHY - Define to the hardcoded PHY address which corresponds - to the given FEC; i. e. - #define CONFIG_FEC1_PHY 4 - means that the PHY with address 4 is connected to FEC1 - - When set to -1, means to probe for first available. - -- CONFIG_FEC[12]_PHY_NORXERR - The PHY does not have a RXERR line (RMII only). - (so program the FEC to ignore it). - - CONFIG_RMII Enable RMII mode for all FECs. Note that this is a global option, we can't @@ -5782,9 +5610,9 @@ configuration for CS0# this is a mirror of the on board Flash memory. To be able to re-map memory U-Boot then jumps to its link address. To be able to implement the initialization code in C, a (small!) initial stack is set up in the internal Dual Ported RAM (in case CPUs -which provide such a feature like MPC8xx or MPC8260), or in a locked -part of the data cache. After that, U-Boot initializes the CPU core, -the caches and the SIU. +which provide such a feature like), or in a locked part of the data +cache. After that, U-Boot initializes the CPU core, the caches and +the SIU. Next, all (potentially) available memory banks are mapped using a preliminary mapping. For example, we put them on 512 MB boundaries