X-Git-Url: http://git.ipfire.org/?p=people%2Fms%2Fu-boot.git;a=blobdiff_plain;f=board%2Fsynopsys%2Faxs101%2Faxs101.c;h=d4280f743ad0b46e4da1bf16e54930c4cceb9f89;hp=4dbeaea16158edc48eb50030166b6418fc43ef42;hb=8b2eb776b13055e71f94367c06a26c5e3a902f16;hpb=a87a0ce7028d5371c81d77ba72c1ba43a1ca77bc

diff --git a/board/synopsys/axs101/axs101.c b/board/synopsys/axs101/axs101.c
index 4dbeaea161..d4280f743a 100644
--- a/board/synopsys/axs101/axs101.c
+++ b/board/synopsys/axs101/axs101.c
@@ -9,6 +9,7 @@
 #include <malloc.h>
 #include <netdev.h>
 #include <phy.h>
+#include "axs10x.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -27,18 +28,61 @@ int board_mmc_init(bd_t *bis)
 	host->ioaddr = (void *)ARC_DWMMC_BASE;
 	host->buswidth = 4;
 	host->dev_index = 0;
-	host->bus_hz = 25000000;
+	host->bus_hz = 50000000;
 
-	add_dwmci(host, 52000000, 400000);
+	add_dwmci(host, host->bus_hz, 400000);
 
 	return 0;
 }
 
 int board_eth_init(bd_t *bis)
 {
-	if (designware_initialize(0, ARC_DWGMAC_BASE, 0,
+	if (designware_initialize(ARC_DWGMAC_BASE,
 				  PHY_INTERFACE_MODE_RGMII) >= 0)
 		return 1;
 
 	return 0;
 }
+
+
+#define AXS_MB_CREG	0xE0011000
+
+int board_early_init_f(void)
+{
+	if (readl((void __iomem *)AXS_MB_CREG + 0x234) & (1 << 28))
+		gd->board_type = AXS_MB_V3;
+	else
+		gd->board_type = AXS_MB_V2;
+
+	return 0;
+}
+
+#ifdef CONFIG_ISA_ARCV2
+#define RESET_VECTOR_ADDR	0x0
+
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+	/* All cores have reset vector pointing to 0 */
+	writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
+
+	/* Make sure other cores see written value in memory */
+	flush_dcache_range(RESET_VECTOR_ADDR, RESET_VECTOR_ADDR + sizeof(int));
+}
+
+void smp_kick_all_cpus(void)
+{
+/* CPU start CREG */
+#define AXC003_CREG_CPU_START	0xF0001400
+
+/* Bits positions in CPU start CREG */
+#define BITS_START	0
+#define BITS_POLARITY	8
+#define BITS_CORE_SEL	9
+#define BITS_MULTICORE	12
+
+#define CMD	(1 << BITS_MULTICORE) | (1 << BITS_CORE_SEL) | \
+		(1 << BITS_POLARITY) | (1 << BITS_START)
+
+	writel(CMD, (void __iomem *)AXC003_CREG_CPU_START);
+}
+#endif