X-Git-Url: http://git.ipfire.org/?p=people%2Fms%2Fu-boot.git;a=blobdiff_plain;f=include%2Fconfigs%2Fcalimain.h;h=854dc1ffedf019f83054120cb76b9ad50f008112;hp=7686592ee186e4b4a877ff116a342b009ff8205c;hb=d021e942107a1f7304a879cec99286ca462f7be3;hpb=2ff1da9453030e02c1e750bd847c9b4dffb8f4a8 diff --git a/include/configs/calimain.h b/include/configs/calimain.h index 7686592ee1..854dc1ffed 100644 --- a/include/configs/calimain.h +++ b/include/configs/calimain.h @@ -21,15 +21,11 @@ /* * SoC Configuration */ -#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ -#define CONFIG_SOC_DA850 /* TI DA850 SoC */ #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) #define CONFIG_SYS_OSCIN_FREQ calimain_get_osc_freq() #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) -#define CONFIG_SYS_TEXT_BASE 0x60000000 -#define CONFIG_DA850_LOWLEVEL #define CONFIG_ARCH_CPU_INIT #define CONFIG_DA8XX_GPIO #define CONFIG_HW_WATCHDOG @@ -42,20 +38,6 @@ /* * PLL configuration */ -#define CONFIG_SYS_DV_CLKMODE 0 -#define CONFIG_SYS_DA850_PLL0_POSTDIV 1 -#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 -#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 -#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 -#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 -#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 -#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 -#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 - -#define CONFIG_SYS_DA850_PLL1_POSTDIV 1 -#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 -#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 -#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 #define CONFIG_SYS_DA850_PLL0_PLLM \ ((calimain_get_osc_freq() == 25000000) ? 23 : 24) @@ -175,7 +157,6 @@ */ #ifdef CONFIG_DRIVER_TI_EMAC #define CONFIG_MII -#define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 @@ -189,9 +170,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) #define CONFIG_LOADADDR 0xc0700000 -#define CONFIG_AUTO_COMPLETE -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP #define CONFIG_MX_CYCLIC /* @@ -295,7 +273,6 @@ /* initial stack pointer in internal SRAM */ #define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00) -#define CONFIG_BOOTCOUNT_LIMIT #define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */ #define CONFIG_SYS_BOOTCOUNT_ADDR DAVINCI_RTC_BASE