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(parent: c253573) | patch
ARM: imx6: Adjust DDR DRAM settings on DHCOM i.MX6 PDK
authorMarek Vasut <marex@denx.de>
Thu, 9 Nov 2017 10:50:13 +0000 (11:50 +0100)
committerStefano Babic <sbabic@denx.de>
Thu, 16 Nov 2017 09:43:22 +0000 (10:43 +0100)
commitb979e35230042bfeadd5f4eddf66232f29e4bff4
tree5efda1c4b05b5273352f2d9ba8b201711241d880tree | snapshot
parentc253573f3e269fd9a24ee6684d87dd91106018a5commit | diff
ARM: imx6: Adjust DDR DRAM settings on DHCOM i.MX6 PDK

The board uses T-topology for the four x16 DRAM chips, so remove
the write-leveling from the SPL as that is only usefly on fly-by
topology and can be harmful on T-topology. Also update the DRAM
timing with values from calibration on multiple boards.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
board/dhelectronics/dh_imx6/dh_imx6_spl.c diff | blob | blame | history
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