]> git.ipfire.org Git - people/ms/u-boot.git/commitdiff
arc: dts: separate single axs10x.dts file
authorVlad Zakharov <vzakhar@synopsys.com>
Tue, 21 Mar 2017 11:49:48 +0000 (14:49 +0300)
committerAlexey Brodkin <abrodkin@synopsys.com>
Fri, 24 Mar 2017 11:47:52 +0000 (14:47 +0300)
We want to use the same device tree blobs in both Linux and U-Boot for
ARC boards.

Earlier device tree sources in U-Boot were very simplified and hadn't been
updated for quite a long period of time.

So this commit is the first step on the road to unified device tree blobs.

First of all we re-organize device tree sources for AXS10X boards.
As AXS101 and AXS103 boards consist of AXS10X motherboard and AXC001 and
AXC003 cpu tiles respectively we add corresponding device tree source
files: axs10x_mb.dtsi for motherboard, axc001.dtsi and axc003.dtsi for
cpu tiles and axs101.dts and axs103.dts to represent actual boards.

Also we delete axs10x.dts as it is no longer used.

One more important change - we add timer device to ARC skeleton device
tree sources as both ARC700 and ARCHS cores contain such timer.
We add core_clk nodes to abilis_tb100, nsim, axc001 and axc003 device tree
sources as it is referenced via phandle from timer node in common
skeleton.dtsi file.

Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
14 files changed:
arch/arc/Kconfig
arch/arc/dts/Makefile
arch/arc/dts/abilis_tb100.dts
arch/arc/dts/axc001.dtsi [new file with mode: 0644]
arch/arc/dts/axc003.dtsi [new file with mode: 0644]
arch/arc/dts/axs101.dts [new file with mode: 0644]
arch/arc/dts/axs103.dts [new file with mode: 0644]
arch/arc/dts/axs10x.dts [deleted file]
arch/arc/dts/axs10x_mb.dtsi [new file with mode: 0644]
arch/arc/dts/nsim.dts
arch/arc/dts/skeleton.dtsi
board/synopsys/axs10x/Kconfig
configs/axs101_defconfig
configs/axs103_defconfig

index 4c5696be1c3c834dcd8626aa412d9f878fbecd72..6e4b1d0e2290abeff0428a02f58063c263585e06 100644 (file)
@@ -118,7 +118,7 @@ config SYS_DCACHE_OFF
 
 choice
        prompt "Target select"
-       default TARGET_AXS10X
+       default TARGET_AXS103
 
 config TARGET_TB100
        bool "Support tb100"
@@ -126,8 +126,11 @@ config TARGET_TB100
 config TARGET_NSIM
        bool "Support standalone nSIM & Free nSIM"
 
-config TARGET_AXS10X
-       bool "Support Synopsys Designware SDP board (AXS101 & AXS103)"
+config TARGET_AXS101
+       bool "Support Synopsys Designware SDP board AXS101"
+
+config TARGET_AXS103
+       bool "Support Synopsys Designware SDP board AXS103"
 
 endchoice
 
index 1d94c082ab57d9a1adef739b4a5b4889b2aa119b..218a6475dd59043cadbe3c5c61d38a52aa8ff5ab 100644 (file)
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-dtb-$(CONFIG_TARGET_AXS10X) +=  axs10x.dtb
+dtb-$(CONFIG_TARGET_AXS101) +=  axs101.dtb
+dtb-$(CONFIG_TARGET_AXS103) +=  axs103.dtb
 dtb-$(CONFIG_TARGET_NSIM) +=  nsim.dtb
 dtb-$(CONFIG_TARGET_TB100) +=  abilis_tb100.dtb
 
index cf395c4011cdcf5279d5ede6a9a11adc560c6288..23329ec016c83ad7ba36b2be81d856ffe415b04c 100644 (file)
@@ -8,13 +8,19 @@
 #include "skeleton.dtsi"
 
 / {
-       #address-cells = <1>;
-       #size-cells = <1>;
-
        aliases {
                console = &uart0;
        };
 
+       cpu_card {
+               core_clk: core_clk {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <500000000>;
+                       u-boot,dm-pre-reloc;
+               };
+       };
+
        uart0: serial@ff100000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0xff100000 0x1000>;
diff --git a/arch/arc/dts/axc001.dtsi b/arch/arc/dts/axc001.dtsi
new file mode 100644 (file)
index 0000000..1cf630d
--- /dev/null
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+       cpu_card {
+               core_clk: core_clk {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <750000000>;
+                       u-boot,dm-pre-reloc;
+               };
+       };
+};
+
diff --git a/arch/arc/dts/axc003.dtsi b/arch/arc/dts/axc003.dtsi
new file mode 100644 (file)
index 0000000..5e9270a
--- /dev/null
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+       cpu_card {
+               core_clk: core_clk {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <100000000>;
+                       u-boot,dm-pre-reloc;
+               };
+       };
+};
+
diff --git a/arch/arc/dts/axs101.dts b/arch/arc/dts/axs101.dts
new file mode 100644 (file)
index 0000000..ec7b8b7
--- /dev/null
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+/dts-v1/;
+
+/include/ "axc001.dtsi"
+/include/ "axs10x_mb.dtsi"
+
+
+/ {
+       chosen {
+               stdout-path = &uart0;
+       };
+};
+
diff --git a/arch/arc/dts/axs103.dts b/arch/arc/dts/axs103.dts
new file mode 100644 (file)
index 0000000..8f7a76f
--- /dev/null
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+/dts-v1/;
+
+/include/ "axc003.dtsi"
+/include/ "axs10x_mb.dtsi"
+
+
+/ {
+       chosen {
+               stdout-path = &uart0;
+       };
+};
+
diff --git a/arch/arc/dts/axs10x.dts b/arch/arc/dts/axs10x.dts
deleted file mode 100644 (file)
index 391d067..0000000
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright (C) 2015 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-/dts-v1/;
-
-#include "skeleton.dtsi"
-
-/ {
-       #address-cells = <1>;
-       #size-cells = <1>;
-
-       aliases {
-               console = &uart0;
-       };
-
-       clocks {
-               apbclk: apbclk {
-                       compatible = "fixed-clock";
-                       clock-frequency = <50000000>;
-                       #clock-cells = <0>;
-               };
-       };
-
-       uart0: serial0@e0022000 {
-               compatible = "snps,dw-apb-uart";
-               reg = <0xe0022000 0x1000>;
-               reg-shift = <2>;
-               reg-io-width = <4>;
-       };
-
-       ethernet@e0018000 {
-               #interrupt-cells = <1>;
-               compatible = "altr,socfpga-stmmac";
-               reg = < 0xe0018000 0x2000 >;
-               interrupts = < 25 >;
-               interrupt-names = "macirq";
-               phy-mode = "gmii";
-               snps,pbl = < 32 >;
-               clocks = <&apbclk>;
-               clock-names = "stmmaceth";
-               max-speed = <100>;
-       };
-
-       ehci@0xe0040000 {
-               compatible = "generic-ehci";
-               reg = < 0xe0040000 0x100 >;
-               interrupts = < 8 >;
-       };
-
-       ohci@0xe0060000 {
-               compatible = "generic-ohci";
-               reg = < 0xe0060000 0x100 >;
-               interrupts = < 8 >;
-       };
-};
diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi
new file mode 100644 (file)
index 0000000..b74d3c8
--- /dev/null
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/ {
+       axs10x_mb@e0000000 {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0x00000000 0xe0000000 0x10000000>;
+               u-boot,dm-pre-reloc;
+
+               clocks {
+                       compatible = "simple-bus";
+                       u-boot,dm-pre-reloc;
+
+                       apbclk: apbclk {
+                               compatible = "fixed-clock";
+                               clock-frequency = <50000000>;
+                               #clock-cells = <0>;
+                       };
+
+                       uartclk: uartclk {
+                               compatible = "fixed-clock";
+                               clock-frequency = <33333333>;
+                               #clock-cells = <0>;
+                               u-boot,dm-pre-reloc;
+                       };
+               };
+
+               ethernet@18000 {
+                       #interrupt-cells = <1>;
+                       compatible = "altr,socfpga-stmmac";
+                       reg = < 0x18000 0x2000 >;
+                       interrupts = < 25 >;
+                       interrupt-names = "macirq";
+                       phy-mode = "gmii";
+                       snps,pbl = < 32 >;
+                       clocks = <&apbclk>;
+                       clock-names = "stmmaceth";
+                       max-speed = <100>;
+               };
+
+               ehci@0x40000 {
+                       compatible = "generic-ehci";
+                       reg = < 0x40000 0x100 >;
+                       interrupts = < 8 >;
+               };
+
+               ohci@0x60000 {
+                       compatible = "generic-ohci";
+                       reg = < 0x60000 0x100 >;
+                       interrupts = < 8 >;
+               };
+
+               uart0: serial0@22000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x22000 0x100>;
+                       clocks = <&uartclk>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+               };
+       };
+};
index 69e16c2a1b4a6a85ce22b8a0122ec34b5f00a8b2..491c46da56cc82120644fd11405c438c07564c16 100644 (file)
@@ -8,17 +8,23 @@
 #include "skeleton.dtsi"
 
 / {
-       #address-cells = <1>;
-       #size-cells = <1>;
-
        aliases {
                console = &arcuart0;
        };
 
+       cpu_card {
+               core_clk: core_clk {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <70000000>;
+                       u-boot,dm-pre-reloc;
+               };
+       };
+
        arcuart0: serial@0xc0fc1000 {
                compatible = "snps,arc-uart";
                reg = <0xc0fc1000 0x100>;
-               clock-frequency = <80000000>;
+               clock-frequency = <70000000>;
        };
 
 };
index b41d241de2cde0ccf022134519e9f9d3ae4261a4..279fc6cacfc0ecb0d8a143dfb3fa65e6e5168ddd 100644 (file)
@@ -9,5 +9,22 @@
        #size-cells = <1>;
        chosen { };
        aliases { };
-       memory { device_type = "memory"; reg = <0 0>; };
+
+       cpu_card {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               u-boot,dm-pre-reloc;
+
+               timer@0 {
+                       compatible = "snps,arc-timer";
+                       clocks = <&core_clk>;
+                       reg = <0 1>;
+               };
+       };
+
+       memory@80000000 {
+               device_type = "memory";
+               reg = <0x80000000 0x10000000>; /* 256M */
+       };
 };
index c60b6a20473e958ee98cb90da2deef98e2f97bdf..dd1305adc76da4706e62345415a06b8f993e8c5b 100644 (file)
@@ -1,4 +1,4 @@
-if TARGET_AXS10X
+if TARGET_AXS101 || TARGET_AXS103
 
 config SYS_BOARD
        default "axs10x"
index aed41aae56c547b62374271949267a7495bfe8d7..b2d4bcabdeacf5b994a16236b5f59aaa12d6118a 100644 (file)
@@ -1,8 +1,9 @@
 CONFIG_ARC=y
 CONFIG_SYS_DCACHE_OFF=y
+CONFIG_TARGET_AXS101=y
 CONFIG_SYS_TEXT_BASE=0x81000000
 CONFIG_SYS_CLK_FREQ=750000000
-CONFIG_DEFAULT_DEVICE_TREE="axs10x"
+CONFIG_DEFAULT_DEVICE_TREE="axs101"
 CONFIG_BOOTDELAY=3
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_PROMPT="AXS# "
index b62e0ad389c4fc30b89c382a603b8e40f212d54a..431eaa43c5452e9f073d6c04aa457a40128f9e25 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_ARC=y
 CONFIG_ISA_ARCV2=y
 CONFIG_SYS_TEXT_BASE=0x81000000
 CONFIG_SYS_CLK_FREQ=100000000
-CONFIG_DEFAULT_DEVICE_TREE="axs10x"
+CONFIG_DEFAULT_DEVICE_TREE="axs103"
 CONFIG_BOOTDELAY=3
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_PROMPT="AXS# "