--- /dev/null
+Broadcom STB wake-up Timer
+
+The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the
+ability to wake up the system from low-power suspend/standby modes.
+
+Required properties:
+- compatible : should contain "brcm,brcmstb-waketimer"
+- reg : the register start and length for the WKTMR block
+- interrupts : The TIMER interrupt
+- interrupt-parent: The phandle to the Always-On (AON) Power Management (PM) L2
+ interrupt controller node
+- clocks : The phandle to the UPG fixed clock (27Mhz domain)
+
+Example:
+
+waketimer@f0411580 {
+ compatible = "brcm,brcmstb-waketimer";
+ reg = <0xf0411580 0x14>;
+ interrupts = <0x3>;
+ interrupt-parent = <&aon_pm_l2_intc>;
+ clocks = <&upg_fixed>;
+};
F: arch/arm/cpu/arm926ejs/mx*/
F: arch/arm/cpu/armv7/mx*/
F: arch/arm/cpu/armv7/vf610/
-F: arch/arm/imx-common/
+F: arch/arm/mach-imx/
F: arch/arm/include/asm/arch-imx/
F: arch/arm/include/asm/arch-mx*/
F: arch/arm/include/asm/arch-vf610/
-F: arch/arm/include/asm/imx-common/
+F: arch/arm/include/asm/mach-imx/
F: board/freescale/*mx*/
ARM HISILICON
endif
%.imx: %.bin
- $(Q)$(MAKE) $(build)=arch/arm/imx-common $@
+ $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
%.vyb: %.imx
$(Q)$(MAKE) $(build)=arch/arm/cpu/armv7/vf610 $@
$(call if_changed,pad_cat)
SPL: spl/u-boot-spl.bin FORCE
- $(Q)$(MAKE) $(build)=arch/arm/imx-common $@
+ $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE
- $(Q)$(MAKE) $(build)=arch/arm/imx-common $@
+ $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
MKIMAGEFLAGS_u-boot.ubl = -n $(UBL_CONFIG) -T ublimage -e $(CONFIG_SYS_TEXT_BASE)
source "arch/arm/cpu/armv7/ls102xa/Kconfig"
-source "arch/arm/cpu/armv7/mx7ulp/Kconfig"
+source "arch/arm/mach-imx/mx7ulp/Kconfig"
-source "arch/arm/cpu/armv7/mx7/Kconfig"
+source "arch/arm/mach-imx/mx7/Kconfig"
-source "arch/arm/cpu/armv7/mx6/Kconfig"
+source "arch/arm/mach-imx/mx6/Kconfig"
-source "arch/arm/cpu/armv7/mx5/Kconfig"
+source "arch/arm/mach-imx/mx5/Kconfig"
source "arch/arm/mach-omap2/Kconfig"
source "arch/arm/cpu/armv8/Kconfig"
-source "arch/arm/imx-common/Kconfig"
+source "arch/arm/mach-imx/Kconfig"
source "board/aries/m28evk/Kconfig"
source "board/bosch/shc/Kconfig"
ifeq ($(CONFIG_SPL_BUILD),y)
ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35))
-libs-y += arch/arm/imx-common/
+libs-y += arch/arm/mach-imx/
endif
else
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs vf610))
-libs-y += arch/arm/imx-common/
+libs-y += arch/arm/mach-imx/
endif
endif
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/sys_proto.h>
#ifdef CONFIG_MMC_MXC
#include <asm/arch/mxcmmc.h>
#endif
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
-#include <asm/imx-common/dma.h>
+#include <asm/mach-imx/dma.h>
#include <asm/arch/gpio.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
-obj-$(if $(filter mx5,$(SOC)),y) += mx5/
-obj-$(CONFIG_MX6) += mx6/
-obj-$(CONFIG_MX7) += mx7/
-obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
obj-$(CONFIG_RMOBILE) += rmobile/
obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/sys_proto.h>
#include <netdev.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#ifndef __ASM_ARCH_MX25_GPIO_H
#define __ASM_ARCH_MX25_GPIO_H
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#endif
#ifndef __IOMUX_MX25_H__
#define __IOMUX_MX25_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
/* Pad control groupings */
#define MX25_KPP_ROW_PAD_CTRL PAD_CTL_PUS_100K_UP
#ifndef __ASM_ARCH_MX31_GPIO_H
#define __ASM_ARCH_MX31_GPIO_H
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#endif
#ifndef _MX31_SYS_PROTO_H_
#define _MX31_SYS_PROTO_H_
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/sys_proto.h>
struct mxc_weimcs {
u32 upper;
#ifndef __ASM_ARCH_MX35_GPIO_H
#define __ASM_ARCH_MX35_GPIO_H
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#endif
#ifndef __IOMUX_MX35_H__
#define __IOMUX_MX35_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
/*
* The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>
#ifndef _MX35_SYS_PROTO_H_
#define _MX35_SYS_PROTO_H_
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/sys_proto.h>
void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config, u32 row,
u32 col, u32 dsize, u32 refresh);
#ifndef __ASM_ARCH_MX5_GPIO_H
#define __ASM_ARCH_MX5_GPIO_H
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#endif
#ifndef __IOMUX_MX51_H__
#define __IOMUX_MX51_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
/* Pad control groupings */
#define MX51_UART_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \
#ifndef __IOMUX_MX53_H__
#define __IOMUX_MX53_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
/* Pad control groupings */
#define MX53_UART_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/sys_proto.h>
#ifndef __ASM_ARCH_MX6_GPIO_H
#define __ASM_ARCH_MX6_GPIO_H
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#endif /* __ASM_ARCH_MX6_GPIO_H */
#endif
#define FEC_QUIRK_ENET_MAC
-#include <asm/imx-common/regs-lcdif.h>
+#include <asm/mach-imx/regs-lcdif.h>
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
#ifndef __ASM_ARCH_MX6_PINS_H__
#define __ASM_ARCH_MX6_PINS_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#define MX6_PAD_DECLARE(prefix, name, pco, mc, mm, sio, si, pc) \
prefix##name = IOMUX_PAD(pco, mc, mm, sio, si, pc)
#ifndef __ASM_ARCH_MX6_MX6SL_PINS_H__
#define __ASM_ARCH_MX6_MX6SL_PINS_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
enum {
MX6_PAD_ECSPI1_MISO__ECSPI_MISO = IOMUX_PAD(0x0358, 0x0068, 0, 0x0684, 0, 0),
#ifndef __ASM_ARCH_IMX6SLL_PINS_H__
#define __ASM_ARCH_IMX6SLL_PINS_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
enum {
MX6_PAD_WDOG_B__WDOG1_B = IOMUX_PAD(0x02DC, 0x0014, 0, 0x0000, 0, 0),
#ifndef __ASM_ARCH_MX6_MX6_PINS_H__
#define __ASM_ARCH_MX6_MX6_PINS_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
enum {
MX6_PAD_GPIO1_IO00__I2C1_SCL = IOMUX_PAD(0x035C, 0x0014, IOMUX_CONFIG_SION | 0, 0x07A8, 1, 0),
#ifndef __ASM_ARCH_IMX6UL_PINS_H__
#define __ASM_ARCH_IMX6UL_PINS_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
enum {
#ifndef __ASM_ARCH_IMX6ULL_PINS_H__
#define __ASM_ARCH_IMX6ULL_PINS_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
enum {
MX6_PAD_BOOT_MODE0__GPIO5_IO10 = IOMUX_PAD(0x0044, 0x0000, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/sys_proto.h>
#ifndef __ASM_ARCH_MX7_GPIO_H
#define __ASM_ARCH_MX7_GPIO_H
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#endif /* __ASM_ARCH_MX7_GPIO_H */
CONFIG_SYS_FSL_JR0_OFFSET)
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/imx-common/regs-lcdif.h>
+#include <asm/mach-imx/regs-lcdif.h>
#include <asm/types.h>
extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
#ifndef __ASM_ARCH_MX7_PINS_H__
#define __ASM_ARCH_MX7_PINS_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#if defined(CONFIG_MX7D)
#include "mx7d_pins.h"
#ifndef __ASM_ARCH_IMX7D_PINS_H__
#define __ASM_ARCH_IMX7D_PINS_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
enum {
MX7D_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/sys_proto.h>
void set_wdog_reset(struct wdog_regs *wdog);
#ifndef _SYS_PROTO_MX7ULP_H_
#define _SYS_PROTO_MX7ULP_H_
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/sys_proto.h>
#define BT0CFG_LPBOOT_MASK 0x1
#define BT0CFG_DUALBOOT_MASK 0x2
#ifndef __IMX_REGS_H__
#define __IMX_REGS_H__
-#include <asm/imx-common/regs-apbh.h>
+#include <asm/mach-imx/regs-apbh.h>
#include <asm/arch/regs-base.h>
-#include <asm/imx-common/regs-bch.h>
+#include <asm/mach-imx/regs-bch.h>
#include <asm/arch/regs-digctl.h>
-#include <asm/imx-common/regs-gpmi.h>
-#include <asm/imx-common/regs-lcdif.h>
+#include <asm/mach-imx/regs-gpmi.h>
+#include <asm/mach-imx/regs-lcdif.h>
#include <asm/arch/regs-i2c.h>
#include <asm/arch/regs-lradc.h>
#include <asm/arch/regs-ocotp.h>
#ifndef __MX23_REGS_CLKCTRL_H__
#define __MX23_REGS_CLKCTRL_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_clkctrl_regs {
#ifndef __MX28_REGS_CLKCTRL_H__
#define __MX28_REGS_CLKCTRL_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_clkctrl_regs {
#ifndef __MX28_REGS_DIGCTL_H__
#define __MX28_REGS_DIGCTL_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_digctl_regs {
#ifndef __MX28_REGS_I2C_H__
#define __MX28_REGS_I2C_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_i2c_regs {
#ifndef __MX28_REGS_LRADC_H__
#define __MX28_REGS_LRADC_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_lradc_regs {
#ifndef __MX28_REGS_OCOTP_H__
#define __MX28_REGS_OCOTP_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_ocotp_regs {
#ifndef __MX28_REGS_PINCTRL_H__
#define __MX28_REGS_PINCTRL_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_pinctrl_regs {
#ifndef __MX23_REGS_POWER_H__
#define __MX23_REGS_POWER_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_power_regs {
#ifndef __MX28_REGS_POWER_H__
#define __MX28_REGS_POWER_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_power_regs {
#ifndef __MX28_REGS_RTC_H__
#define __MX28_REGS_RTC_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_rtc_regs {
#ifndef __MX28_REGS_SSP_H__
#define __MX28_REGS_SSP_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
#if defined(CONFIG_MX23)
#ifndef __MX28_REGS_TIMROT_H__
#define __MX28_REGS_TIMROT_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_timrot_regs {
#ifndef __ARCH_ARM___MXS_UARTAPP_H
#define __ARCH_ARM___MXS_UARTAPP_H
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_uartapp_regs {
#ifndef __MXS_SYS_PROTO_H__
#define __MXS_SYS_PROTO_H__
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/sys_proto.h>
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int));
#ifndef __IOMUX_VF610_H__
#define __IOMUX_VF610_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
/* Pad control groupings */
#define VF610_UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_25ohm | \
#ifndef __ASM_ARCH_MXC_MXC_I2C_H__
#define __ASM_ARCH_MXC_MXC_I2C_H__
#include <asm-generic/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
struct i2c_pin_ctrl {
iomux_v3_cfg_t i2c_mode;
#ifndef __REGS_APBH_H__
#define __REGS_APBH_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
#ifndef __MX28_REGS_BCH_H__
#define __MX28_REGS_BCH_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_bch_regs {
#ifndef __MX28_REGS_GPMI_H__
#define __MX28_REGS_GPMI_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_gpmi_regs {
#define __IMX_REGS_LCDIF_H__
#ifndef __ASSEMBLY__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */
#define _SYS_PROTO_H_
#include <asm/io.h>
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#include <common.h>
#include "../arch-imx/cpu.h"
$(call if_changed,u-boot-nand-spl_imx)
targets += $(addprefix ../../../,$(IMX_CONFIG) SPL u-boot.uim spl/u-boot-nand-spl.imx)
+
+obj-$(CONFIG_MX5) += mx5/
+obj-$(CONFIG_MX6) += mx6/
+obj-$(CONFIG_MX7) += mx7/
+obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
+
#include <asm/armv7.h>
#include <asm/pl310.h>
#include <asm/io.h>
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/sys_proto.h>
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
#include <common.h>
#include <linux/errno.h>
#include <asm/io.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/boot_mode.h>
#include <malloc.h>
#include <command.h>
#include <asm/system.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/hab.h>
+#include <asm/mach-imx/hab.h>
/* -------- start of HAB API updates ------------*/
#include <asm/arch/imx-regs.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <watchdog.h>
int force_idle_bus(void *priv)
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/crm_regs.h>
void init_aips(void)
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sys_proto.h>
static void *base = (void *)IOMUXC_BASE_ADDR;
#include <asm/arch/sys_proto.h>
#include <linux/errno.h>
#include <asm/io.h>
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
/* 1 second delay should be plenty of time for block reset. */
#define RESET_MAX_TIMEOUT 1000000
#include <linux/errno.h>
#include <asm/io.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/boot_mode.h>
#if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
#error "CPU_TYPE not defined"
select SUPPORT_SPL
select SPL_LOAD_FIT
-config TARGET_MX6QSABREAUTO
- bool "mx6qsabreauto"
+config TARGET_MX6SABREAUTO
+ bool "mx6sabreauto"
select BOARD_LATE_INIT
+ select SUPPORT_SPL
select DM
select DM_THERMAL
select BOARD_EARLY_INIT_F
source "board/engicam/icorem6_rqs/Kconfig"
source "board/engicam/isiotmx6ul/Kconfig"
source "board/freescale/mx6qarm2/Kconfig"
-source "board/freescale/mx6qsabreauto/Kconfig"
+source "board/freescale/mx6sabreauto/Kconfig"
source "board/freescale/mx6sabresd/Kconfig"
source "board/freescale/mx6slevk/Kconfig"
source "board/freescale/mx6sllevk/Kconfig"
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <asm/arch/mx6ul_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <common.h>
#include <environment.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/dma.h>
-#include <asm/imx-common/hab.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/dma.h>
+#include <asm/mach-imx/hab.h>
#include <stdbool.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
-#ifdef CONFIG_APBH_DMA
- /* Start APBH DMA */
- mxs_dma_init();
-#endif
-
init_src();
return 0;
const struct boot_mode soc_boot_modes[] = {
{"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
/* reserved value should start rom usb */
+#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
+ {"usb", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
+#else
{"usb", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
+#endif
{"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
{"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
{"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/dma.h>
-#include <asm/imx-common/hab.h>
-#include <asm/imx-common/rdc-sema.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/dma.h>
+#include <asm/mach-imx/hab.h>
+#include <asm/mach-imx/rdc-sema.h>
#include <asm/arch/imx-rdc.h>
#include <asm/arch/crm_regs.h>
#include <dm.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/hab.h>
+#include <asm/mach-imx/hab.h>
static char *get_reset_cause(char *);
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/rdc-sema.h>
+#include <asm/mach-imx/rdc-sema.h>
#include <asm/arch/imx-rdc.h>
#include <linux/errno.h>
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include <asm/arch/iomux.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/spl.h>
#include <spl.h>
-#include <asm/imx-common/hab.h>
+#include <asm/mach-imx/hab.h>
#if defined(CONFIG_MX6)
/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 register */
#include <div64.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/syscounter.h>
+#include <asm/mach-imx/syscounter.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <linux/errno.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/video.h>
int board_video_skip(void)
{
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
*
* The syntax is taken as close as possible with the kwbimage
*/
-#include <asm/imx-common/imximage.cfg>
+#include <asm/mach-imx/imximage.cfg>
/* image version */
IMAGE_VERSION 2
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
-#include <asm/imx-common/mx5_video.h>
+#include <asm/mach-imx/mx5_video.h>
#include <asm/spl.h>
#include <linux/errno.h>
#include <netdev.h>
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
default "opos6uldev"
config IMX_CONFIG
- default "arch/arm/imx-common/spl_sd.cfg"
+ default "arch/arm/mach-imx/spl_sd.cfg"
endif
#include <asm/arch/opos6ul.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <common.h>
#include <asm/arch/iomux.h>
#include <malloc.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <mmc.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
#include "platinum.h"
#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <i2c.h>
#include <miiphy.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <miiphy.h>
#include <micrel.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <spl.h>
#include "platinum.h"
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <spl.h>
#include "platinum.h"
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <micrel.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
#include <asm/arch/clock.h>
-#include <asm/imx-common/mx5_video.h>
+#include <asm/mach-imx/mx5_video.h>
#include <ACEX1K.h>
#include <netdev.h>
#include <i2c.h>
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/spi.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/spi.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <micrel.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mxc_hdmi.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/video.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <dm/platform_data/serial_mxc.h>
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/spi.h>
+#include <asm/mach-imx/spi.h>
#include <fsl_esdhc.h>
#include "common.h"
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include <fsl_esdhc.h>
#include "common.h"
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/spi.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/spi.h>
+#include <asm/mach-imx/video.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/video.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include "../common/board.h"
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/video.h>
#include "../common/board.h"
S: Maintained
F: board/engicam/icorem6_rqs
F: include/configs/imx6qdl_icore_rqs.h
-F: configs/imx6qdl_icore_rqs_mmc_defconfig
+F: configs/imx6qdl_icore_rqs_defconfig
F: arch/arm/dts/imx6qdl-icore-rqs.dtsi
F: arch/arm/dts/imx6q-icore-rqs.dts
F: arch/arm/dts/imx6dl-icore-rqs.dts
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include "../common/board.h"
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include "../common/board.h"
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
-#include <asm/imx-common/mx5_video.h>
+#include <asm/mach-imx/mx5_video.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
#include <linux/errno.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/boot_mode.h>
#include <netdev.h>
#include <i2c.h>
#include <mmc.h>
#include <asm/arch/iomux-mx53.h>
#include <asm/arch/clock.h>
#include <linux/errno.h>
-#include <asm/imx-common/mx5_video.h>
+#include <asm/mach-imx/mx5_video.h>
#include <netdev.h>
#include <i2c.h>
#include <mmc.h>
#include <asm/arch/clock.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
+++ /dev/null
-MX6QSABREAUTO BOARD
-M: Fabio Estevam <fabio.estevam@nxp.com>
-M: Peng Fan <peng.fan@nxp.com>
-S: Maintained
-F: board/freescale/mx6qsabreauto/
-F: include/configs/mx6qsabreauto.h
-F: configs/mx6dlsabreauto_defconfig
-F: configs/mx6qsabreauto_defconfig
-F: configs/mx6qpsabreauto_defconfig
+++ /dev/null
-/*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-/* image version */
-
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-DATA 4 0x020e0798 0x000C0000
-DATA 4 0x020e0758 0x00000000
-DATA 4 0x020e0588 0x00000030
-DATA 4 0x020e0594 0x00000030
-DATA 4 0x020e056c 0x00000030
-DATA 4 0x020e0578 0x00000030
-DATA 4 0x020e074c 0x00000030
-DATA 4 0x020e057c 0x00000030
-DATA 4 0x020e058c 0x00000000
-DATA 4 0x020e059c 0x00000030
-DATA 4 0x020e05a0 0x00000030
-DATA 4 0x020e078c 0x00000030
-DATA 4 0x020e0750 0x00020000
-DATA 4 0x020e05a8 0x00000028
-DATA 4 0x020e05b0 0x00000028
-DATA 4 0x020e0524 0x00000028
-DATA 4 0x020e051c 0x00000028
-DATA 4 0x020e0518 0x00000028
-DATA 4 0x020e050c 0x00000028
-DATA 4 0x020e05b8 0x00000028
-DATA 4 0x020e05c0 0x00000028
-DATA 4 0x020e0774 0x00020000
-DATA 4 0x020e0784 0x00000028
-DATA 4 0x020e0788 0x00000028
-DATA 4 0x020e0794 0x00000028
-DATA 4 0x020e079c 0x00000028
-DATA 4 0x020e07a0 0x00000028
-DATA 4 0x020e07a4 0x00000028
-DATA 4 0x020e07a8 0x00000028
-DATA 4 0x020e0748 0x00000028
-DATA 4 0x020e05ac 0x00000028
-DATA 4 0x020e05b4 0x00000028
-DATA 4 0x020e0528 0x00000028
-DATA 4 0x020e0520 0x00000028
-DATA 4 0x020e0514 0x00000028
-DATA 4 0x020e0510 0x00000028
-DATA 4 0x020e05bc 0x00000028
-DATA 4 0x020e05c4 0x00000028
-DATA 4 0x021b0800 0xa1390003
-DATA 4 0x021b080c 0x001F001F
-DATA 4 0x021b0810 0x001F001F
-DATA 4 0x021b480c 0x001F001F
-DATA 4 0x021b4810 0x001F001F
-DATA 4 0x021b083c 0x43260335
-DATA 4 0x021b0840 0x031A030B
-DATA 4 0x021b483c 0x4323033B
-DATA 4 0x021b4840 0x0323026F
-DATA 4 0x021b0848 0x483D4545
-DATA 4 0x021b4848 0x44433E48
-DATA 4 0x021b0850 0x41444840
-DATA 4 0x021b4850 0x4835483E
-DATA 4 0x021b081c 0x33333333
-DATA 4 0x021b0820 0x33333333
-DATA 4 0x021b0824 0x33333333
-DATA 4 0x021b0828 0x33333333
-DATA 4 0x021b481c 0x33333333
-DATA 4 0x021b4820 0x33333333
-DATA 4 0x021b4824 0x33333333
-DATA 4 0x021b4828 0x33333333
-DATA 4 0x021b08b8 0x00000800
-DATA 4 0x021b48b8 0x00000800
-DATA 4 0x021b0004 0x00020036
-DATA 4 0x021b0008 0x09444040
-DATA 4 0x021b000c 0x8A8F7955
-DATA 4 0x021b0010 0xFF328F64
-DATA 4 0x021b0014 0x01FF00DB
-DATA 4 0x021b0018 0x00001740
-DATA 4 0x021b001c 0x00008000
-DATA 4 0x021b002c 0x000026d2
-DATA 4 0x021b0030 0x008F1023
-DATA 4 0x021b0040 0x00000047
-DATA 4 0x021b0000 0x841A0000
-DATA 4 0x021b001c 0x04088032
-DATA 4 0x021b001c 0x00008033
-DATA 4 0x021b001c 0x00048031
-DATA 4 0x021b001c 0x09408030
-DATA 4 0x021b001c 0x04008040
-DATA 4 0x021b0020 0x00005800
-DATA 4 0x021b0818 0x00011117
-DATA 4 0x021b4818 0x00011117
-DATA 4 0x021b0004 0x00025576
-DATA 4 0x021b0404 0x00011006
-DATA 4 0x021b001c 0x00000000
-
-/* set the default clock gate to save power */
-DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC03
-DATA 4 0x020c4070 0x0FFFC000
-DATA 4 0x020c4074 0x3FF00000
-DATA 4 0x020c4078 0xFFFFF300
-DATA 4 0x020c407c 0x0F0000F3
-DATA 4 0x020c4080 0x00000FFF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4 0x020e0010 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4 0x020e0018 0x007F007F
-DATA 4 0x020e001c 0x007F007F
+++ /dev/null
-/*
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
- * Jason Liu <r64343@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-/* image version */
-
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-DATA 4 0x020e0774 0x000C0000
-DATA 4 0x020e0754 0x00000000
-DATA 4 0x020e04ac 0x00000030
-DATA 4 0x020e04b0 0x00000030
-DATA 4 0x020e0464 0x00000030
-DATA 4 0x020e0490 0x00000030
-DATA 4 0x020e074c 0x00000030
-DATA 4 0x020e0494 0x00000030
-DATA 4 0x020e04a0 0x00000000
-DATA 4 0x020e04b4 0x00000030
-DATA 4 0x020e04b8 0x00000030
-DATA 4 0x020e076c 0x00000030
-DATA 4 0x020e0750 0x00020000
-DATA 4 0x020e04bc 0x00000028
-DATA 4 0x020e04c0 0x00000028
-DATA 4 0x020e04c4 0x00000028
-DATA 4 0x020e04c8 0x00000028
-DATA 4 0x020e04cc 0x00000028
-DATA 4 0x020e04d0 0x00000028
-DATA 4 0x020e04d4 0x00000028
-DATA 4 0x020e04d8 0x00000028
-DATA 4 0x020e0760 0x00020000
-DATA 4 0x020e0764 0x00000028
-DATA 4 0x020e0770 0x00000028
-DATA 4 0x020e0778 0x00000028
-DATA 4 0x020e077c 0x00000028
-DATA 4 0x020e0780 0x00000028
-DATA 4 0x020e0784 0x00000028
-DATA 4 0x020e078c 0x00000028
-DATA 4 0x020e0748 0x00000028
-DATA 4 0x020e0470 0x00000028
-DATA 4 0x020e0474 0x00000028
-DATA 4 0x020e0478 0x00000028
-DATA 4 0x020e047c 0x00000028
-DATA 4 0x020e0480 0x00000028
-DATA 4 0x020e0484 0x00000028
-DATA 4 0x020e0488 0x00000028
-DATA 4 0x020e048c 0x00000028
-DATA 4 0x021b0800 0xa1390003
-DATA 4 0x021b080c 0x001F001F
-DATA 4 0x021b0810 0x001F001F
-DATA 4 0x021b480c 0x001F001F
-DATA 4 0x021b4810 0x001F001F
-DATA 4 0x021b083c 0x42190217
-DATA 4 0x021b0840 0x017B017B
-DATA 4 0x021b483c 0x4176017B
-DATA 4 0x021b4840 0x015F016C
-DATA 4 0x021b0848 0x4C4C4D4C
-DATA 4 0x021b4848 0x4A4D4C48
-DATA 4 0x021b0850 0x3F3F3F40
-DATA 4 0x021b4850 0x3538382E
-DATA 4 0x021b081c 0x33333333
-DATA 4 0x021b0820 0x33333333
-DATA 4 0x021b0824 0x33333333
-DATA 4 0x021b0828 0x33333333
-DATA 4 0x021b481c 0x33333333
-DATA 4 0x021b4820 0x33333333
-DATA 4 0x021b4824 0x33333333
-DATA 4 0x021b4828 0x33333333
-DATA 4 0x021b08b8 0x00000800
-DATA 4 0x021b48b8 0x00000800
-DATA 4 0x021b0004 0x00020025
-DATA 4 0x021b0008 0x00333030
-DATA 4 0x021b000c 0x676B5313
-DATA 4 0x021b0010 0xB66E8B63
-DATA 4 0x021b0014 0x01FF00DB
-DATA 4 0x021b0018 0x00001740
-DATA 4 0x021b001c 0x00008000
-DATA 4 0x021b002c 0x000026d2
-DATA 4 0x021b0030 0x006B1023
-DATA 4 0x021b0040 0x00000047
-DATA 4 0x021b0000 0x841A0000
-DATA 4 0x021b001c 0x04008032
-DATA 4 0x021b001c 0x00008033
-DATA 4 0x021b001c 0x00048031
-DATA 4 0x021b001c 0x05208030
-DATA 4 0x021b001c 0x04008040
-DATA 4 0x021b0020 0x00005800
-DATA 4 0x021b0818 0x00011117
-DATA 4 0x021b4818 0x00011117
-DATA 4 0x021b0004 0x00025565
-DATA 4 0x021b0404 0x00011006
-DATA 4 0x021b001c 0x00000000
-
-/* set the default clock gate to save power */
-DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC03
-DATA 4 0x020c4070 0x0FFFC000
-DATA 4 0x020c4074 0x3FF00000
-DATA 4 0x020c4078 0xFFFFF300
-DATA 4 0x020c407c 0x0F0000C3
-DATA 4 0x020c4080 0x00000FFF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4 0x020e0010 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4 0x020e0018 0x007F007F
-DATA 4 0x020e001c 0x007F007F
+++ /dev/null
-/*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-/* image version */
-
-#define __ASSEMBLY__
-#include <config.h>
-
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of spi, sd, eimnor, nand, sata:
- * spinor: flash_offset: 0x0400
- * nand: flash_offset: 0x0400
- * sata: flash_offset: 0x0400
- * sd/mmc: flash_offset: 0x0400
- * eimnor: flash_offset: 0x1000
- */
-BOOT_FROM sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-DATA 4 0x020e0798 0x000C0000
-DATA 4 0x020e0758 0x00000000
-DATA 4 0x020e0588 0x00000030
-DATA 4 0x020e0594 0x00000030
-DATA 4 0x020e056c 0x00000030
-DATA 4 0x020e0578 0x00000030
-DATA 4 0x020e074c 0x00000030
-DATA 4 0x020e057c 0x00000030
-DATA 4 0x020e058c 0x00000000
-DATA 4 0x020e059c 0x00000030
-DATA 4 0x020e05a0 0x00000030
-DATA 4 0x020e078c 0x00000030
-DATA 4 0x020e0750 0x00020000
-DATA 4 0x020e05a8 0x00000030
-DATA 4 0x020e05b0 0x00000030
-DATA 4 0x020e0524 0x00000030
-DATA 4 0x020e051c 0x00000030
-DATA 4 0x020e0518 0x00000030
-DATA 4 0x020e050c 0x00000030
-DATA 4 0x020e05b8 0x00000030
-DATA 4 0x020e05c0 0x00000030
-DATA 4 0x020e0774 0x00020000
-DATA 4 0x020e0784 0x00000030
-DATA 4 0x020e0788 0x00000030
-DATA 4 0x020e0794 0x00000030
-DATA 4 0x020e079c 0x00000030
-DATA 4 0x020e07a0 0x00000030
-DATA 4 0x020e07a4 0x00000030
-DATA 4 0x020e07a8 0x00000030
-DATA 4 0x020e0748 0x00000030
-DATA 4 0x020e05ac 0x00000030
-DATA 4 0x020e05b4 0x00000030
-DATA 4 0x020e0528 0x00000030
-DATA 4 0x020e0520 0x00000030
-DATA 4 0x020e0514 0x00000030
-DATA 4 0x020e0510 0x00000030
-DATA 4 0x020e05bc 0x00000030
-DATA 4 0x020e05c4 0x00000030
-DATA 4 0x021b0800 0xa1390003
-DATA 4 0x021b080c 0x001b001e
-DATA 4 0x021b0810 0x002e0029
-DATA 4 0x021b480c 0x001b002a
-DATA 4 0x021b4810 0x0019002c
-DATA 4 0x021b083c 0x43240334
-DATA 4 0x021b0840 0x0324031a
-DATA 4 0x021b483c 0x43340344
-DATA 4 0x021b4840 0x03280276
-DATA 4 0x021b0848 0x44383A3E
-DATA 4 0x021b4848 0x3C3C3846
-DATA 4 0x021b0850 0x2e303230
-DATA 4 0x021b4850 0x38283E34
-DATA 4 0x021b081c 0x33333333
-DATA 4 0x021b0820 0x33333333
-DATA 4 0x021b0824 0x33333333
-DATA 4 0x021b0828 0x33333333
-DATA 4 0x021b481c 0x33333333
-DATA 4 0x021b4820 0x33333333
-DATA 4 0x021b4824 0x33333333
-DATA 4 0x021b4828 0x33333333
-DATA 4 0x021b08c0 0x24912492
-DATA 4 0x021b48c0 0x24912492
-DATA 4 0x021b08b8 0x00000800
-DATA 4 0x021b48b8 0x00000800
-DATA 4 0x021b0004 0x00020036
-DATA 4 0x021b0008 0x09444040
-DATA 4 0x021b000c 0x898E7955
-DATA 4 0x021b0010 0xFF328F64
-DATA 4 0x021b0014 0x01FF00DB
-DATA 4 0x021b0018 0x00001740
-DATA 4 0x021b001c 0x00008000
-
-DATA 4 0x021b002c 0x000026d2
-DATA 4 0x021b0030 0x008E1023
-DATA 4 0x021b0040 0x00000047
-DATA 4 0x021b0400 0x14420000
-DATA 4 0x021b0000 0x841A0000
-DATA 4 0x00bb0008 0x00000004
-DATA 4 0x00bb000c 0x2891E41A
-DATA 4 0x00bb0038 0x00000564
-DATA 4 0x00bb0014 0x00000040
-DATA 4 0x00bb0028 0x00000020
-DATA 4 0x00bb002c 0x00000020
-DATA 4 0x021b001c 0x04088032
-DATA 4 0x021b001c 0x00008033
-DATA 4 0x021b001c 0x00048031
-DATA 4 0x021b001c 0x09408030
-DATA 4 0x021b001c 0x04008040
-DATA 4 0x021b0020 0x00005800
-DATA 4 0x021b0818 0x00011117
-DATA 4 0x021b4818 0x00011117
-DATA 4 0x021b0004 0x00025576
-DATA 4 0x021b0404 0x00011006
-DATA 4 0x021b001c 0x00000000
-/* set the default clock gate to save power */
-DATA 4, 0x020c4068, 0x00C03F3F
-DATA 4, 0x020c406c, 0x0030FC03
-DATA 4, 0x020c4070, 0x0FFFC000
-DATA 4, 0x020c4074, 0x3FF00000
-DATA 4, 0x020c4078, 0xFFFFF300
-DATA 4, 0x020c407c, 0x0F0000F3
-DATA 4, 0x020c4080, 0x00000FFF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4, 0x020e0010, 0xF00000CF
-/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
-DATA 4, 0x020e0018, 0x77177717
-DATA 4, 0x020e001c, 0x77177717
+++ /dev/null
-/*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- *
- * Author: Fabio Estevam <fabio.estevam@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/spi.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/arch/sys_proto.h>
-#include <i2c.h>
-#include <asm/arch/mxc_hdmi.h>
-#include <asm/imx-common/video.h>
-#include <asm/arch/crm_regs.h>
-#include <pca953x.h>
-#include <power/pmic.h>
-#include <power/pfuze100_pmic.h>
-#include "../common/pfuze.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
- PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
-#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
- PAD_CTL_SRE_FAST)
-#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define I2C_PMIC 1
-
-int dram_init(void)
-{
- gd->ram_size = imx_ddr_size();
-
- return 0;
-}
-
-static iomux_v3_cfg_t const uart4_pads[] = {
- MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const enet_pads[] = {
- MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
-static struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
- .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
- .gp = IMX_GPIO_NR(2, 30)
- },
- .sda = {
- .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-#ifndef CONFIG_SYS_FLASH_CFI
-/*
- * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
- * Compass Sensor, Accelerometer, Res Touch
- */
-static struct i2c_pads_info i2c_pad_info2 = {
- .scl = {
- .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
- .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
- .gp = IMX_GPIO_NR(1, 3)
- },
- .sda = {
- .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
- .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
- .gp = IMX_GPIO_NR(3, 18)
- }
-};
-#endif
-
-static iomux_v3_cfg_t const i2c3_pads[] = {
- MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const port_exp[] = {
- MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-/*Define for building port exp gpio, pin starts from 0*/
-#define PORTEXP_IO_NR(chip, pin) \
- ((chip << 5) + pin)
-
-/*Get the chip addr from a ioexp gpio*/
-#define PORTEXP_IO_TO_CHIP(gpio_nr) \
- (gpio_nr >> 5)
-
-/*Get the pin number from a ioexp gpio*/
-#define PORTEXP_IO_TO_PIN(gpio_nr) \
- (gpio_nr & 0x1f)
-
-static int port_exp_direction_output(unsigned gpio, int value)
-{
- int ret;
-
- i2c_set_bus_num(2);
- ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
- if (ret)
- return ret;
-
- ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
- (1 << PORTEXP_IO_TO_PIN(gpio)),
- (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
-
- if (ret)
- return ret;
-
- ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
- (1 << PORTEXP_IO_TO_PIN(gpio)),
- (value << PORTEXP_IO_TO_PIN(gpio)));
-
- if (ret)
- return ret;
-
- return 0;
-}
-
-static iomux_v3_cfg_t const eimnor_pads[] = {
- MX6_PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
- MX6_PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void eimnor_cs_setup(void)
-{
- struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
-
- writel(0x00020181, &weim_regs->cs0gcr1);
- writel(0x00000001, &weim_regs->cs0gcr2);
- writel(0x0a020000, &weim_regs->cs0rcr1);
- writel(0x0000c000, &weim_regs->cs0rcr2);
- writel(0x0804a240, &weim_regs->cs0wcr1);
- writel(0x00000120, &weim_regs->wcr);
-
- set_chipselect_size(CS0_128);
-}
-
-static void eim_clk_setup(void)
-{
- struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- int cscmr1, ccgr6;
-
-
- /* Turn off EIM clock */
- ccgr6 = readl(&imx_ccm->CCGR6);
- ccgr6 &= ~(0x3 << 10);
- writel(ccgr6, &imx_ccm->CCGR6);
-
- /*
- * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root
- * and aclk_eim_slow_podf = 01 --> divide by 2
- * so that we can have EIM at the maximum clock of 132MHz
- */
- cscmr1 = readl(&imx_ccm->cscmr1);
- cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK |
- MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK);
- cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET);
- writel(cscmr1, &imx_ccm->cscmr1);
-
- /* Turn on EIM clock */
- ccgr6 |= (0x3 << 10);
- writel(ccgr6, &imx_ccm->CCGR6);
-}
-
-static void setup_iomux_eimnor(void)
-{
- imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
-
- gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
-
- eimnor_cs_setup();
-}
-
-static void setup_iomux_enet(void)
-{
- imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
-}
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void setup_iomux_uart(void)
-{
- imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
-}
-
-#ifdef CONFIG_FSL_ESDHC
-static struct fsl_esdhc_cfg usdhc_cfg[1] = {
- {USDHC3_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- gpio_direction_input(IMX_GPIO_NR(6, 15));
- return !gpio_get_value(IMX_GPIO_NR(6, 15));
-}
-
-int board_mmc_init(bd_t *bis)
-{
- imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-}
-#endif
-
-#ifdef CONFIG_NAND_MXS
-static iomux_v3_cfg_t gpmi_pads[] = {
- MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
- MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1),
-};
-
-static void setup_gpmi_nand(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- /* config gpmi nand iomux */
- imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
-
- setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
- MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
- MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
-
- /* enable apbh clock gating */
- setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
-}
-#endif
-
-static void setup_fec(void)
-{
- if (is_mx6dqp()) {
- /*
- * select ENET MAC0 TX clock from PLL
- */
- imx_iomux_set_gpr_register(5, 9, 1, 1);
- enable_fec_anatop_clock(0, ENET_125MHZ);
- }
-
- setup_iomux_enet();
-}
-
-int board_eth_init(bd_t *bis)
-{
- setup_fec();
-
- return cpu_eth_init(bis);
-}
-
-#define BOARD_REV_B 0x200
-#define BOARD_REV_A 0x100
-
-static int mx6sabre_rev(void)
-{
- /*
- * Get Board ID information from OCOTP_GP1[15:8]
- * i.MX6Q ARD RevA: 0x01
- * i.MX6Q ARD RevB: 0x02
- */
- struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
- struct fuse_bank *bank = &ocotp->bank[4];
- struct fuse_bank4_regs *fuse =
- (struct fuse_bank4_regs *)bank->fuse_regs;
- int reg = readl(&fuse->gp1);
- int ret;
-
- switch (reg >> 8 & 0x0F) {
- case 0x02:
- ret = BOARD_REV_B;
- break;
- case 0x01:
- default:
- ret = BOARD_REV_A;
- break;
- }
-
- return ret;
-}
-
-u32 get_board_rev(void)
-{
- int rev = mx6sabre_rev();
-
- return (get_cpu_rev() & ~(0xF << 8)) | rev;
-}
-
-#if defined(CONFIG_VIDEO_IPUV3)
-static void disable_lvds(struct display_info_t const *dev)
-{
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
- clrbits_le32(&iomux->gpr[2],
- IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
- IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
-}
-
-static void do_enable_hdmi(struct display_info_t const *dev)
-{
- disable_lvds(dev);
- imx_enable_hdmi_phy();
-}
-
-struct display_info_t const displays[] = {{
- .bus = -1,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB666,
- .detect = NULL,
- .enable = NULL,
- .mode = {
- .name = "Hannstar-XGA",
- .refresh = 60,
- .xres = 1024,
- .yres = 768,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- .bus = -1,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB24,
- .detect = detect_hdmi,
- .enable = do_enable_hdmi,
- .mode = {
- .name = "HDMI",
- .refresh = 60,
- .xres = 1024,
- .yres = 768,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED,
-} } };
-size_t display_count = ARRAY_SIZE(displays);
-
-iomux_v3_cfg_t const backlight_pads[] = {
- MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-static void setup_iomux_backlight(void)
-{
- gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
- imx_iomux_v3_setup_multiple_pads(backlight_pads,
- ARRAY_SIZE(backlight_pads));
-}
-
-static void setup_display(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
- int reg;
-
- setup_iomux_backlight();
- enable_ipu_clock();
- imx_setup_hdmi();
-
- /* Turn on LDB_DI0 and LDB_DI1 clocks */
- reg = readl(&mxc_ccm->CCGR3);
- reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
- writel(reg, &mxc_ccm->CCGR3);
-
- /* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
- reg = readl(&mxc_ccm->cs2cdr);
- reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
- MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
- reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
- (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
- writel(reg, &mxc_ccm->cs2cdr);
-
- reg = readl(&mxc_ccm->cscmr2);
- reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
- writel(reg, &mxc_ccm->cscmr2);
-
- reg = readl(&mxc_ccm->chsccdr);
- reg |= (CHSCCDR_CLK_SEL_LDB_DI0
- << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
- reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
- MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
- writel(reg, &mxc_ccm->chsccdr);
-
- reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
- IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
- IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
- IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
- IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
- IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
- IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
- IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
- writel(reg, &iomux->gpr[2]);
-
- reg = readl(&iomux->gpr[3]);
- reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
- IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
- reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
- IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
- (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
- IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
- writel(reg, &iomux->gpr[3]);
-}
-#endif /* CONFIG_VIDEO_IPUV3 */
-
-/*
- * Do not overwrite the console
- * Use always serial for U-Boot console
- */
-int overwrite_console(void)
-{
- return 1;
-}
-
-int board_early_init_f(void)
-{
- setup_iomux_uart();
-
-#ifdef CONFIG_NAND_MXS
- setup_gpmi_nand();
-#endif
- eim_clk_setup();
-
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
- /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
- /* I2C 3 Steer */
- gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
- imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
-#ifndef CONFIG_SYS_FLASH_CFI
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-#endif
- gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
- imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
-
-#ifdef CONFIG_VIDEO_IPUV3
- setup_display();
-#endif
- setup_iomux_eimnor();
- return 0;
-}
-
-#ifdef CONFIG_MXC_SPI
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
- return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
-}
-#endif
-
-int power_init_board(void)
-{
- struct pmic *p;
- unsigned int value;
-
- p = pfuze_common_init(I2C_PMIC);
- if (!p)
- return -ENODEV;
-
- if (is_mx6dqp()) {
- /* set SW2 staby volatage 0.975V*/
- pmic_reg_read(p, PFUZE100_SW2STBY, &value);
- value &= ~0x3f;
- value |= 0x17;
- pmic_reg_write(p, PFUZE100_SW2STBY, value);
- }
-
- return pfuze_mode_init(p, APS_PFM);
-}
-
-#ifdef CONFIG_CMD_BMODE
-static const struct boot_mode board_boot_modes[] = {
- /* 4 bit bus width */
- {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
- {NULL, 0},
-};
-#endif
-
-int board_late_init(void)
-{
-#ifdef CONFIG_CMD_BMODE
- add_board_boot_modes(board_boot_modes);
-#endif
-
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- setenv("board_name", "SABREAUTO");
-
- if (is_mx6dqp())
- setenv("board_rev", "MX6QP");
- else if (is_mx6dq())
- setenv("board_rev", "MX6Q");
- else if (is_mx6sdl())
- setenv("board_rev", "MX6DL");
-#endif
-
- return 0;
-}
-
-int checkboard(void)
-{
- int rev = mx6sabre_rev();
- char *revname;
-
- switch (rev) {
- case BOARD_REV_B:
- revname = "B";
- break;
- case BOARD_REV_A:
- default:
- revname = "A";
- break;
- }
-
- printf("Board: MX6Q-Sabreauto rev%s\n", revname);
-
- return 0;
-}
-
-#ifdef CONFIG_USB_EHCI_MX6
-#define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7)
-#define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1)
-
-iomux_v3_cfg_t const usb_otg_pads[] = {
- MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-int board_ehci_hcd_init(int port)
-{
- switch (port) {
- case 0:
- imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
- ARRAY_SIZE(usb_otg_pads));
-
- /*
- * Set daisy chain for otg_pin_id on 6q.
- * For 6dl, this bit is reserved.
- */
- imx_iomux_set_gpr_register(1, 13, 1, 0);
- break;
- case 1:
- break;
- default:
- printf("MXC USB port %d not yet supported\n", port);
- return -EINVAL;
- }
- return 0;
-}
-
-int board_ehci_power(int port, int on)
-{
- switch (port) {
- case 0:
- if (on)
- port_exp_direction_output(USB_OTG_PWR, 1);
- else
- port_exp_direction_output(USB_OTG_PWR, 0);
- break;
- case 1:
- if (on)
- port_exp_direction_output(USB_HOST1_PWR, 1);
- else
- port_exp_direction_output(USB_HOST1_PWR, 0);
- break;
- default:
- printf("MXC USB port %d not yet supported\n", port);
- return -EINVAL;
- }
-
- return 0;
-}
-#endif
-if TARGET_MX6QSABREAUTO
+if TARGET_MX6SABREAUTO
config SYS_BOARD
- default "mx6qsabreauto"
+ default "mx6sabreauto"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
- default "mx6qsabreauto"
+ default "mx6sabreauto"
endif
--- /dev/null
+MX6SABREAUTO BOARD
+M: Fabio Estevam <fabio.estevam@nxp.com>
+M: Peng Fan <peng.fan@nxp.com>
+S: Maintained
+F: board/freescale/mx6sabreauto/
+F: include/configs/mx6sabreauto.h
+F: configs/mx6sabreauto_defconfig
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := mx6qsabreauto.o
+obj-y := mx6sabreauto.o
--- /dev/null
+How to use and build U-Boot on mx6sabreauto
+-------------------------------------------
+
+mx6sabreauto_defconfig target supports mx6q/mx6dl/mx6qp sabreauto variants.
+
+In order to build it:
+
+$ make mx6sabreauto_defconfig
+
+$ make
+
+This will generate the SPL and u-boot.img binaries.
+
+- Flash the SPL binary into the SD card:
+
+$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync
+
+- Flash the u-boot.img binary into the SD card:
+
+$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 && sync
+
+Booting via Falcon mode
+-----------------------
+
+Write in mx6sabreauto_defconfig the following define below:
+
+CONFIG_SPL_OS_BOOT=y
+
+In order to build it:
+
+$ make mx6sabreauto_defconfig
+
+$ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the SD card:
+
+$ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 && sync
+
+- Flash the u-boot.img image into the SD card:
+
+$ sudo dd if=u-boot.img of=/dev/sdb bs=1K seek=69 && sync
+
+Create a FAT16 boot partition to store uImage and the dtb file, then copy the files there:
+
+$ sudo cp uImage /media/boot
+
+$ sudo cp imx6dl-sabreauto.dtb /media/boot
+
+Create a partition for root file system and extract it there:
+
+$ sudo tar xvf rootfs.tar.gz -C /media/root
+
+The SD card must have enough space for raw "args" and "kernel".
+To configure Falcon mode for the first time, on U-Boot do the following commands:
+
+- Load dtb file from boot partition:
+
+# load mmc 0:1 ${fdt_addr} imx6dl-sabreauto.dtb
+
+- Load kernel image from boot partition:
+
+# load mmc 0:1 ${loadaddr} uImage
+
+- Write kernel at 2MB offset:
+
+# mmc write ${loadaddr} 0x1000 0x4000
+
+- Setup kernel bootargs:
+
+# setenv bootargs "console=ttymxc3,115200 root=/dev/mmcblk0p1 rootfstype=ext4 rootwait quiet rw"
+
+- Prepare args:
+
+# spl export fdt ${loadaddr} - ${fdt_addr}
+
+- Write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)
+
+# mmc write 18000000 0x800 0x800
+
+- Restart the board and then SPL binary will launch the kernel directly.
--- /dev/null
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/spi.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/mach-imx/video.h>
+#include <asm/arch/crm_regs.h>
+#include <pca953x.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+ PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PMIC 1
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+ IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const enet_pads[] = {
+ IOMUX_PADS(PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+};
+
+/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
+static struct i2c_pads_info mx6q_i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6Q_PAD_EIM_EB2__I2C2_SCL | PC,
+ .gpio_mode = MX6Q_PAD_EIM_EB2__GPIO2_IO30 | PC,
+ .gp = IMX_GPIO_NR(2, 30)
+ },
+ .sda = {
+ .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
+static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6DL_PAD_EIM_EB2__I2C2_SCL | PC,
+ .gpio_mode = MX6DL_PAD_EIM_EB2__GPIO2_IO30 | PC,
+ .gp = IMX_GPIO_NR(2, 30)
+ },
+ .sda = {
+ .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
+#ifndef CONFIG_SYS_FLASH_CFI
+/*
+ * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
+ * Compass Sensor, Accelerometer, Res Touch
+ */
+static struct i2c_pads_info mx6q_i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
+ .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
+ .gp = IMX_GPIO_NR(1, 3)
+ },
+ .sda = {
+ .i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA | PC,
+ .gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 | PC,
+ .gp = IMX_GPIO_NR(3, 18)
+ }
+};
+
+static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
+ .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
+ .gp = IMX_GPIO_NR(1, 3)
+ },
+ .sda = {
+ .i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA | PC,
+ .gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 | PC,
+ .gp = IMX_GPIO_NR(3, 18)
+ }
+};
+#endif
+
+static iomux_v3_cfg_t const i2c3_pads[] = {
+ IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const port_exp[] = {
+ IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+/*Define for building port exp gpio, pin starts from 0*/
+#define PORTEXP_IO_NR(chip, pin) \
+ ((chip << 5) + pin)
+
+/*Get the chip addr from a ioexp gpio*/
+#define PORTEXP_IO_TO_CHIP(gpio_nr) \
+ (gpio_nr >> 5)
+
+/*Get the pin number from a ioexp gpio*/
+#define PORTEXP_IO_TO_PIN(gpio_nr) \
+ (gpio_nr & 0x1f)
+
+static int port_exp_direction_output(unsigned gpio, int value)
+{
+ int ret;
+
+ i2c_set_bus_num(2);
+ ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
+ if (ret)
+ return ret;
+
+ ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
+ (1 << PORTEXP_IO_TO_PIN(gpio)),
+ (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
+
+ if (ret)
+ return ret;
+
+ ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
+ (1 << PORTEXP_IO_TO_PIN(gpio)),
+ (value << PORTEXP_IO_TO_PIN(gpio)));
+
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+#ifdef CONFIG_MTD_NOR_FLASH
+static iomux_v3_cfg_t const eimnor_pads[] = {
+ IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void eimnor_cs_setup(void)
+{
+ struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
+
+ writel(0x00020181, &weim_regs->cs0gcr1);
+ writel(0x00000001, &weim_regs->cs0gcr2);
+ writel(0x0a020000, &weim_regs->cs0rcr1);
+ writel(0x0000c000, &weim_regs->cs0rcr2);
+ writel(0x0804a240, &weim_regs->cs0wcr1);
+ writel(0x00000120, &weim_regs->wcr);
+
+ set_chipselect_size(CS0_128);
+}
+
+static void eim_clk_setup(void)
+{
+ struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ int cscmr1, ccgr6;
+
+
+ /* Turn off EIM clock */
+ ccgr6 = readl(&imx_ccm->CCGR6);
+ ccgr6 &= ~(0x3 << 10);
+ writel(ccgr6, &imx_ccm->CCGR6);
+
+ /*
+ * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root
+ * and aclk_eim_slow_podf = 01 --> divide by 2
+ * so that we can have EIM at the maximum clock of 132MHz
+ */
+ cscmr1 = readl(&imx_ccm->cscmr1);
+ cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK |
+ MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK);
+ cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET);
+ writel(cscmr1, &imx_ccm->cscmr1);
+
+ /* Turn on EIM clock */
+ ccgr6 |= (0x3 << 10);
+ writel(ccgr6, &imx_ccm->CCGR6);
+}
+
+static void setup_iomux_eimnor(void)
+{
+ SETUP_IOMUX_PADS(eimnor_pads);
+
+ gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
+
+ eimnor_cs_setup();
+}
+#endif
+
+static void setup_iomux_enet(void)
+{
+ SETUP_IOMUX_PADS(enet_pads);
+}
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void setup_iomux_uart(void)
+{
+ SETUP_IOMUX_PADS(uart4_pads);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC3_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ gpio_direction_input(IMX_GPIO_NR(6, 15));
+ return !gpio_get_value(IMX_GPIO_NR(6, 15));
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ SETUP_IOMUX_PADS(usdhc3_pads);
+
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t gpmi_pads[] = {
+ IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
+ IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1)),
+};
+
+static void setup_gpmi_nand(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* config gpmi nand iomux */
+ SETUP_IOMUX_PADS(gpmi_pads);
+
+ setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
+
+ /* enable apbh clock gating */
+ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
+static void setup_fec(void)
+{
+ if (is_mx6dqp()) {
+ /*
+ * select ENET MAC0 TX clock from PLL
+ */
+ imx_iomux_set_gpr_register(5, 9, 1, 1);
+ enable_fec_anatop_clock(0, ENET_125MHZ);
+ }
+
+ setup_iomux_enet();
+}
+
+int board_eth_init(bd_t *bis)
+{
+ setup_fec();
+
+ return cpu_eth_init(bis);
+}
+
+#define BOARD_REV_B 0x200
+#define BOARD_REV_A 0x100
+
+static int mx6sabre_rev(void)
+{
+ /*
+ * Get Board ID information from OCOTP_GP1[15:8]
+ * i.MX6Q ARD RevA: 0x01
+ * i.MX6Q ARD RevB: 0x02
+ */
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[4];
+ struct fuse_bank4_regs *fuse =
+ (struct fuse_bank4_regs *)bank->fuse_regs;
+ int reg = readl(&fuse->gp1);
+ int ret;
+
+ switch (reg >> 8 & 0x0F) {
+ case 0x02:
+ ret = BOARD_REV_B;
+ break;
+ case 0x01:
+ default:
+ ret = BOARD_REV_A;
+ break;
+ }
+
+ return ret;
+}
+
+u32 get_board_rev(void)
+{
+ int rev = mx6sabre_rev();
+
+ return (get_cpu_rev() & ~(0xF << 8)) | rev;
+}
+
+static int ar8031_phy_fixup(struct phy_device *phydev)
+{
+ unsigned short val;
+
+ /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+ val &= 0xffe3;
+ val |= 0x18;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+ /* introduce tx clock delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+ val |= 0x0100;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ ar8031_phy_fixup(phydev);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+#if defined(CONFIG_VIDEO_IPUV3)
+static void disable_lvds(struct display_info_t const *dev)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ clrbits_le32(&iomux->gpr[2],
+ IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
+ IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
+}
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+ disable_lvds(dev);
+ imx_enable_hdmi_phy();
+}
+
+struct display_info_t const displays[] = {{
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB666,
+ .detect = NULL,
+ .enable = NULL,
+ .mode = {
+ .name = "Hannstar-XGA",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = do_enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED,
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+iomux_v3_cfg_t const backlight_pads[] = {
+ IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+};
+
+static void setup_iomux_backlight(void)
+{
+ gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
+ SETUP_IOMUX_PADS(backlight_pads);
+}
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int reg;
+
+ setup_iomux_backlight();
+ enable_ipu_clock();
+ imx_setup_hdmi();
+
+ /* Turn on LDB_DI0 and LDB_DI1 clocks */
+ reg = readl(&mxc_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
+ writel(reg, &mxc_ccm->CCGR3);
+
+ /* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
+ reg = readl(&mxc_ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
+ MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+ reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
+ (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->cs2cdr);
+
+ reg = readl(&mxc_ccm->cscmr2);
+ reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
+ writel(reg, &mxc_ccm->cscmr2);
+
+ reg = readl(&mxc_ccm->chsccdr);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
+ MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->chsccdr);
+
+ reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
+ IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
+ IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
+ IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
+ IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+ IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
+ IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
+ IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
+ writel(reg, &iomux->gpr[2]);
+
+ reg = readl(&iomux->gpr[3]);
+ reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
+ IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
+ reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+ IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
+ (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+ IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
+ writel(reg, &iomux->gpr[3]);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+#ifdef CONFIG_NAND_MXS
+ setup_gpmi_nand();
+#endif
+
+#ifdef CONFIG_MTD_NOR_FLASH
+ eim_clk_setup();
+#endif
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
+ if (is_mx6dq() || is_mx6dqp())
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
+ else
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
+ /* I2C 3 Steer */
+ gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
+ SETUP_IOMUX_PADS(i2c3_pads);
+#ifndef CONFIG_SYS_FLASH_CFI
+ if (is_mx6dq() || is_mx6dqp())
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
+ else
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
+#endif
+ gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
+ SETUP_IOMUX_PADS(port_exp);
+
+#ifdef CONFIG_VIDEO_IPUV3
+ setup_display();
+#endif
+
+#ifdef CONFIG_MTD_NOR_FLASH
+ setup_iomux_eimnor();
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
+}
+#endif
+
+int power_init_board(void)
+{
+ struct pmic *p;
+ unsigned int value;
+
+ p = pfuze_common_init(I2C_PMIC);
+ if (!p)
+ return -ENODEV;
+
+ if (is_mx6dqp()) {
+ /* set SW2 staby volatage 0.975V*/
+ pmic_reg_read(p, PFUZE100_SW2STBY, &value);
+ value &= ~0x3f;
+ value |= 0x17;
+ pmic_reg_write(p, PFUZE100_SW2STBY, value);
+ }
+
+ return pfuze_mode_init(p, APS_PFM);
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ setenv("board_name", "SABREAUTO");
+
+ if (is_mx6dqp())
+ setenv("board_rev", "MX6QP");
+ else if (is_mx6dq())
+ setenv("board_rev", "MX6Q");
+ else if (is_mx6sdl())
+ setenv("board_rev", "MX6DL");
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ int rev = mx6sabre_rev();
+ char *revname;
+
+ switch (rev) {
+ case BOARD_REV_B:
+ revname = "B";
+ break;
+ case BOARD_REV_A:
+ default:
+ revname = "A";
+ break;
+ }
+
+ printf("Board: MX6Q-Sabreauto rev%s\n", revname);
+
+ return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7)
+#define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1)
+
+iomux_v3_cfg_t const usb_otg_pads[] = {
+ IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+int board_ehci_hcd_init(int port)
+{
+ switch (port) {
+ case 0:
+ SETUP_IOMUX_PADS(usb_otg_pads);
+
+ /*
+ * Set daisy chain for otg_pin_id on 6q.
+ * For 6dl, this bit is reserved.
+ */
+ imx_iomux_set_gpr_register(1, 13, 1, 0);
+ break;
+ case 1:
+ break;
+ default:
+ printf("MXC USB port %d not yet supported\n", port);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+ switch (port) {
+ case 0:
+ if (on)
+ port_exp_direction_output(USB_OTG_PWR, 1);
+ else
+ port_exp_direction_output(USB_OTG_PWR, 0);
+ break;
+ case 1:
+ if (on)
+ port_exp_direction_output(USB_HOST1_PWR, 1);
+ else
+ port_exp_direction_output(USB_HOST1_PWR, 0);
+ break;
+ default:
+ printf("MXC USB port %d not yet supported\n", port);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#include <asm/arch/mx6-ddr.h>
+#include <spl.h>
+#include <libfdt.h>
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ return 0;
+}
+#endif
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC03, &ccm->CCGR1);
+ writel(0x0FFFC000, &ccm->CCGR2);
+ writel(0x3FF00000, &ccm->CCGR3);
+ writel(0x00FFF300, &ccm->CCGR4);
+ writel(0x0F0000C3, &ccm->CCGR5);
+ writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* enable AXI cache for VDOA/VPU/IPU */
+ writel(0xF00000CF, &iomux->gpr[4]);
+ if (is_mx6dqp()) {
+ /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+ } else {
+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+ }
+}
+
+static int mx6q_dcd_table[] = {
+ 0x020e0798, 0x000C0000,
+ 0x020e0758, 0x00000000,
+ 0x020e0588, 0x00000030,
+ 0x020e0594, 0x00000030,
+ 0x020e056c, 0x00000030,
+ 0x020e0578, 0x00000030,
+ 0x020e074c, 0x00000030,
+ 0x020e057c, 0x00000030,
+ 0x020e058c, 0x00000000,
+ 0x020e059c, 0x00000030,
+ 0x020e05a0, 0x00000030,
+ 0x020e078c, 0x00000030,
+ 0x020e0750, 0x00020000,
+ 0x020e05a8, 0x00000028,
+ 0x020e05b0, 0x00000028,
+ 0x020e0524, 0x00000028,
+ 0x020e051c, 0x00000028,
+ 0x020e0518, 0x00000028,
+ 0x020e050c, 0x00000028,
+ 0x020e05b8, 0x00000028,
+ 0x020e05c0, 0x00000028,
+ 0x020e0774, 0x00020000,
+ 0x020e0784, 0x00000028,
+ 0x020e0788, 0x00000028,
+ 0x020e0794, 0x00000028,
+ 0x020e079c, 0x00000028,
+ 0x020e07a0, 0x00000028,
+ 0x020e07a4, 0x00000028,
+ 0x020e07a8, 0x00000028,
+ 0x020e0748, 0x00000028,
+ 0x020e05ac, 0x00000028,
+ 0x020e05b4, 0x00000028,
+ 0x020e0528, 0x00000028,
+ 0x020e0520, 0x00000028,
+ 0x020e0514, 0x00000028,
+ 0x020e0510, 0x00000028,
+ 0x020e05bc, 0x00000028,
+ 0x020e05c4, 0x00000028,
+ 0x021b0800, 0xa1390003,
+ 0x021b080c, 0x001F001F,
+ 0x021b0810, 0x001F001F,
+ 0x021b480c, 0x001F001F,
+ 0x021b4810, 0x001F001F,
+ 0x021b083c, 0x43260335,
+ 0x021b0840, 0x031A030B,
+ 0x021b483c, 0x4323033B,
+ 0x021b4840, 0x0323026F,
+ 0x021b0848, 0x483D4545,
+ 0x021b4848, 0x44433E48,
+ 0x021b0850, 0x41444840,
+ 0x021b4850, 0x4835483E,
+ 0x021b081c, 0x33333333,
+ 0x021b0820, 0x33333333,
+ 0x021b0824, 0x33333333,
+ 0x021b0828, 0x33333333,
+ 0x021b481c, 0x33333333,
+ 0x021b4820, 0x33333333,
+ 0x021b4824, 0x33333333,
+ 0x021b4828, 0x33333333,
+ 0x021b08b8, 0x00000800,
+ 0x021b48b8, 0x00000800,
+ 0x021b0004, 0x00020036,
+ 0x021b0008, 0x09444040,
+ 0x021b000c, 0x8A8F7955,
+ 0x021b0010, 0xFF328F64,
+ 0x021b0014, 0x01FF00DB,
+ 0x021b0018, 0x00001740,
+ 0x021b001c, 0x00008000,
+ 0x021b002c, 0x000026d2,
+ 0x021b0030, 0x008F1023,
+ 0x021b0040, 0x00000047,
+ 0x021b0000, 0x841A0000,
+ 0x021b001c, 0x04088032,
+ 0x021b001c, 0x00008033,
+ 0x021b001c, 0x00048031,
+ 0x021b001c, 0x09408030,
+ 0x021b001c, 0x04008040,
+ 0x021b0020, 0x00005800,
+ 0x021b0818, 0x00011117,
+ 0x021b4818, 0x00011117,
+ 0x021b0004, 0x00025576,
+ 0x021b0404, 0x00011006,
+ 0x021b001c, 0x00000000,
+ 0x020c4068, 0x00C03F3F,
+ 0x020c406c, 0x0030FC03,
+ 0x020c4070, 0x0FFFC000,
+ 0x020c4074, 0x3FF00000,
+ 0x020c4078, 0xFFFFF300,
+ 0x020c407c, 0x0F0000F3,
+ 0x020c4080, 0x00000FFF,
+ 0x020e0010, 0xF00000CF,
+ 0x020e0018, 0x007F007F,
+ 0x020e001c, 0x007F007F,
+};
+
+static int mx6qp_dcd_table[] = {
+ 0x020e0798, 0x000C0000,
+ 0x020e0758, 0x00000000,
+ 0x020e0588, 0x00000030,
+ 0x020e0594, 0x00000030,
+ 0x020e056c, 0x00000030,
+ 0x020e0578, 0x00000030,
+ 0x020e074c, 0x00000030,
+ 0x020e057c, 0x00000030,
+ 0x020e058c, 0x00000000,
+ 0x020e059c, 0x00000030,
+ 0x020e05a0, 0x00000030,
+ 0x020e078c, 0x00000030,
+ 0x020e0750, 0x00020000,
+ 0x020e05a8, 0x00000030,
+ 0x020e05b0, 0x00000030,
+ 0x020e0524, 0x00000030,
+ 0x020e051c, 0x00000030,
+ 0x020e0518, 0x00000030,
+ 0x020e050c, 0x00000030,
+ 0x020e05b8, 0x00000030,
+ 0x020e05c0, 0x00000030,
+ 0x020e0774, 0x00020000,
+ 0x020e0784, 0x00000030,
+ 0x020e0788, 0x00000030,
+ 0x020e0794, 0x00000030,
+ 0x020e079c, 0x00000030,
+ 0x020e07a0, 0x00000030,
+ 0x020e07a4, 0x00000030,
+ 0x020e07a8, 0x00000030,
+ 0x020e0748, 0x00000030,
+ 0x020e05ac, 0x00000030,
+ 0x020e05b4, 0x00000030,
+ 0x020e0528, 0x00000030,
+ 0x020e0520, 0x00000030,
+ 0x020e0514, 0x00000030,
+ 0x020e0510, 0x00000030,
+ 0x020e05bc, 0x00000030,
+ 0x020e05c4, 0x00000030,
+ 0x021b0800, 0xa1390003,
+ 0x021b080c, 0x001b001e,
+ 0x021b0810, 0x002e0029,
+ 0x021b480c, 0x001b002a,
+ 0x021b4810, 0x0019002c,
+ 0x021b083c, 0x43240334,
+ 0x021b0840, 0x0324031a,
+ 0x021b483c, 0x43340344,
+ 0x021b4840, 0x03280276,
+ 0x021b0848, 0x44383A3E,
+ 0x021b4848, 0x3C3C3846,
+ 0x021b0850, 0x2e303230,
+ 0x021b4850, 0x38283E34,
+ 0x021b081c, 0x33333333,
+ 0x021b0820, 0x33333333,
+ 0x021b0824, 0x33333333,
+ 0x021b0828, 0x33333333,
+ 0x021b481c, 0x33333333,
+ 0x021b4820, 0x33333333,
+ 0x021b4824, 0x33333333,
+ 0x021b4828, 0x33333333,
+ 0x021b08c0, 0x24912492,
+ 0x021b48c0, 0x24912492,
+ 0x021b08b8, 0x00000800,
+ 0x021b48b8, 0x00000800,
+ 0x021b0004, 0x00020036,
+ 0x021b0008, 0x09444040,
+ 0x021b000c, 0x898E7955,
+ 0x021b0010, 0xFF328F64,
+ 0x021b0014, 0x01FF00DB,
+ 0x021b0018, 0x00001740,
+ 0x021b001c, 0x00008000,
+ 0x021b002c, 0x000026d2,
+ 0x021b0030, 0x008E1023,
+ 0x021b0040, 0x00000047,
+ 0x021b0400, 0x14420000,
+ 0x021b0000, 0x841A0000,
+ 0x00bb0008, 0x00000004,
+ 0x00bb000c, 0x2891E41A,
+ 0x00bb0038, 0x00000564,
+ 0x00bb0014, 0x00000040,
+ 0x00bb0028, 0x00000020,
+ 0x00bb002c, 0x00000020,
+ 0x021b001c, 0x04088032,
+ 0x021b001c, 0x00008033,
+ 0x021b001c, 0x00048031,
+ 0x021b001c, 0x09408030,
+ 0x021b001c, 0x04008040,
+ 0x021b0020, 0x00005800,
+ 0x021b0818, 0x00011117,
+ 0x021b4818, 0x00011117,
+ 0x021b0004, 0x00025576,
+ 0x021b0404, 0x00011006,
+ 0x021b001c, 0x00000000,
+ 0x020c4068, 0x00C03F3F,
+ 0x020c406c, 0x0030FC03,
+ 0x020c4070, 0x0FFFC000,
+ 0x020c4074, 0x3FF00000,
+ 0x020c4078, 0xFFFFF300,
+ 0x020c407c, 0x0F0000F3,
+ 0x020c4080, 0x00000FFF,
+ 0x020e0010, 0xF00000CF,
+ 0x020e0018, 0x77177717,
+ 0x020e001c, 0x77177717,
+};
+
+static int mx6dl_dcd_table[] = {
+ 0x020e0774, 0x000C0000,
+ 0x020e0754, 0x00000000,
+ 0x020e04ac, 0x00000030,
+ 0x020e04b0, 0x00000030,
+ 0x020e0464, 0x00000030,
+ 0x020e0490, 0x00000030,
+ 0x020e074c, 0x00000030,
+ 0x020e0494, 0x00000030,
+ 0x020e04a0, 0x00000000,
+ 0x020e04b4, 0x00000030,
+ 0x020e04b8, 0x00000030,
+ 0x020e076c, 0x00000030,
+ 0x020e0750, 0x00020000,
+ 0x020e04bc, 0x00000028,
+ 0x020e04c0, 0x00000028,
+ 0x020e04c4, 0x00000028,
+ 0x020e04c8, 0x00000028,
+ 0x020e04cc, 0x00000028,
+ 0x020e04d0, 0x00000028,
+ 0x020e04d4, 0x00000028,
+ 0x020e04d8, 0x00000028,
+ 0x020e0760, 0x00020000,
+ 0x020e0764, 0x00000028,
+ 0x020e0770, 0x00000028,
+ 0x020e0778, 0x00000028,
+ 0x020e077c, 0x00000028,
+ 0x020e0780, 0x00000028,
+ 0x020e0784, 0x00000028,
+ 0x020e078c, 0x00000028,
+ 0x020e0748, 0x00000028,
+ 0x020e0470, 0x00000028,
+ 0x020e0474, 0x00000028,
+ 0x020e0478, 0x00000028,
+ 0x020e047c, 0x00000028,
+ 0x020e0480, 0x00000028,
+ 0x020e0484, 0x00000028,
+ 0x020e0488, 0x00000028,
+ 0x020e048c, 0x00000028,
+ 0x021b0800, 0xa1390003,
+ 0x021b080c, 0x001F001F,
+ 0x021b0810, 0x001F001F,
+ 0x021b480c, 0x001F001F,
+ 0x021b4810, 0x001F001F,
+ 0x021b083c, 0x42190217,
+ 0x021b0840, 0x017B017B,
+ 0x021b483c, 0x4176017B,
+ 0x021b4840, 0x015F016C,
+ 0x021b0848, 0x4C4C4D4C,
+ 0x021b4848, 0x4A4D4C48,
+ 0x021b0850, 0x3F3F3F40,
+ 0x021b4850, 0x3538382E,
+ 0x021b081c, 0x33333333,
+ 0x021b0820, 0x33333333,
+ 0x021b0824, 0x33333333,
+ 0x021b0828, 0x33333333,
+ 0x021b481c, 0x33333333,
+ 0x021b4820, 0x33333333,
+ 0x021b4824, 0x33333333,
+ 0x021b4828, 0x33333333,
+ 0x021b08b8, 0x00000800,
+ 0x021b48b8, 0x00000800,
+ 0x021b0004, 0x00020025,
+ 0x021b0008, 0x00333030,
+ 0x021b000c, 0x676B5313,
+ 0x021b0010, 0xB66E8B63,
+ 0x021b0014, 0x01FF00DB,
+ 0x021b0018, 0x00001740,
+ 0x021b001c, 0x00008000,
+ 0x021b002c, 0x000026d2,
+ 0x021b0030, 0x006B1023,
+ 0x021b0040, 0x00000047,
+ 0x021b0000, 0x841A0000,
+ 0x021b001c, 0x04008032,
+ 0x021b001c, 0x00008033,
+ 0x021b001c, 0x00048031,
+ 0x021b001c, 0x05208030,
+ 0x021b001c, 0x04008040,
+ 0x021b0020, 0x00005800,
+ 0x021b0818, 0x00011117,
+ 0x021b4818, 0x00011117,
+ 0x021b0004, 0x00025565,
+ 0x021b0404, 0x00011006,
+ 0x021b001c, 0x00000000,
+ 0x020c4068, 0x00C03F3F,
+ 0x020c406c, 0x0030FC03,
+ 0x020c4070, 0x0FFFC000,
+ 0x020c4074, 0x3FF00000,
+ 0x020c4078, 0xFFFFF300,
+ 0x020c407c, 0x0F0000C3,
+ 0x020c4080, 0x00000FFF,
+ 0x020e0010, 0xF00000CF,
+ 0x020e0018, 0x007F007F,
+ 0x020e001c, 0x007F007F,
+};
+
+static void ddr_init(int *table, int size)
+{
+ int i;
+
+ for (i = 0; i < size / 2 ; i++)
+ writel(table[2 * i + 1], table[2 * i]);
+}
+
+static void spl_dram_init(void)
+{
+ if (is_mx6dq())
+ ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
+ else if (is_mx6dqp())
+ ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
+ else if (is_mx6sdl())
+ ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
+}
+
+void board_init_f(ulong dummy)
+{
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ ccgr_init();
+ gpr_init();
+
+ /* iomux and setup of i2c */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+#endif
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/spi.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/spi.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <common.h>
#include <linux/sizes.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <linux/sizes.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <asm/arch/mx7-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
#include <power/pfuze3000_pmic.h>
#include "../common/pfuze.h"
#include <i2c.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/crm_regs.h>
DECLARE_GLOBAL_DATA_PTR;
pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1);
+ /*
+ * Set the voltage of VLDO4 output to 2.8V which feeds
+ * the MIPI DSI and MIPI CSI inputs.
+ */
+ pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA);
+
return 0;
}
#endif
*
* The syntax is taken as close as possible with the kwbimage
*/
-#include <asm/imx-common/imximage.cfg>
+#include <asm/mach-imx/imximage.cfg>
/* image version */
IMAGE_VERSION 2
*
* The syntax is taken as close as possible with the kwbimage
*/
-#include <asm/imx-common/imximage.cfg>
+#include <asm/mach-imx/imximage.cfg>
/* image version */
IMAGE_VERSION 2
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <fsl_esdhc.h>
#include <hwconfig.h>
#include <power/pmic.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/spi.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/spi.h>
+#include <asm/mach-imx/video.h>
#include <asm/io.h>
#include <asm/setup.h>
#include <dm.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <environment.h>
#include <i2c.h>
#include <spl.h>
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/video.h>
#include <fsl_esdhc.h>
#include <i2c.h>
#include <input.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/crm_regs.h>
#include <i2c.h>
#include <mmc.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/video.h>
#include <i2c.h>
#include <input.h>
#include <ipu_pixfmt.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/spi.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/spi.h>
+#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <fsl_esdhc.h>
#include <mmc.h>
#include <asm/arch/mx6-pins.h>
#include <errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
DECLARE_GLOBAL_DATA_PTR;
* The syntax is taken as close as possible with the kwbimage
*/
-#include <asm/imx-common/imximage.cfg>
+#include <asm/mach-imx/imximage.cfg>
/* image version */
IMAGE_VERSION 2
*
* The syntax is taken as close as possible with the kwbimage
*/
-#include <asm/imx-common/imximage.cfg>
+#include <asm/mach-imx/imximage.cfg>
/* image version */
IMAGE_VERSION 2
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/spi.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/spi.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <mmc.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <linux/sizes.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <micrel.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <i2c.h>
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
#include <malloc.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <micrel.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <i2c.h>
#include "../common/mx6.h"
#include <asm/arch/mxc_hdmi.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <malloc.h>
ret = setup_display();
#endif
+#ifdef CONFIG_CMD_SATA
+ setup_sata();
+#endif
+
#ifdef CONFIG_USB_EHCI_MX6
setup_usb();
#endif
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
#include <miiphy.h>
#include <asm/arch/mx7-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
-#include <asm/imx-common/mx5_video.h>
+#include <asm/mach-imx/mx5_video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <mc13892.h>
#include <asm/bootm.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
#include <dm/platform_data/serial_mxc.h>
#include <dm/platdata.h>
#include <fsl_esdhc.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include "pf0100_otp.inc"
#include "pf0100.h"
#include <asm/arch/sys_proto.h>
#include <asm/bootm.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
#include <asm/io.h>
#include <dm/platform_data/serial_mxc.h>
#include <dm/platdata.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include "pf0100_otp.inc"
#include "pf0100.h"
#include <asm/arch/mx7-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <common.h>
#include <dm.h>
*
* The syntax is taken as close as possible with the kwbimage
*/
-#include <asm/imx-common/imximage.cfg>
+#include <asm/mach-imx/imximage.cfg>
/* image version */
IMAGE_VERSION 2
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/spi.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/spi.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <libfdt.h>
#include <asm/arch/sys_proto.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <asm/arch/sys_proto.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/sys_proto.h>
#include <spl.h>
#include <linux/sizes.h>
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/sata.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sata.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/arch/crm_regs.h>
mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
}
-
- udelay(100);
}
void board_init_f(ulong dummy)
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
-#include <asm/imx-common/sata.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
+#include <asm/mach-imx/sata.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
}
static struct fsl_esdhc_cfg usdhc_cfg[1] = {
- {USDHC2_BASE_ADDR},
+ {USDHC2_BASE_ADDR, 0, 0, 0, 1},
};
int board_mmc_getcd(struct mmc *mmc)
#include <asm/arch/mx7-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
#include <fsl_esdhc.h>
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_CMD_HDMIDETECT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VIDEO=y
# CONFIG_CMD_BMODE is not set
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_CMD_HDMIDETECT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6DL"
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
CONFIG_BOOTDELAY=3
# CONFIG_SYS_STDIO_DEREGISTER is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
CONFIG_BOOTDELAY=3
# CONFIG_SYS_STDIO_DEREGISTER is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
CONFIG_BOOTDELAY=3
# CONFIG_SYS_STDIO_DEREGISTER is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,ENV_IS_IN_MMC"
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_VIDEO_IPUV3=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_MXC=y
+CONFIG_DEBUG_UART_BASE=0x021f0000
+CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,ENV_IS_IN_NAND"
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,ENV_IS_IN_MMC"
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,ENV_IS_IN_MMC"
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,ENV_IS_IN_NAND"
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,ENV_IS_IN_MMC"
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,ENV_IS_IN_MMC"
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,ENV_IS_IN_NAND"
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=1
CONFIG_DEFAULT_FDT_FILE="imx6ul-liteboard.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PXE=y
CONFIG_OF_CONTROL=y
CONFIG_FPGA_ALTERA=y
CONFIG_FPGA_CYCLON2=y
# CONFIG_CMD_BMODE is not set
CONFIG_CMD_HDMIDETECT=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
# CONFIG_SYS_STDIO_DEREGISTER is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
+CONFIG_CMD_SATA=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_PARTITION_UUIDS is not set
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_TARGET_MX6QSABREAUTO=y
-CONFIG_VIDEO=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6qp.cfg,MX6Q"
-CONFIG_BOOTDELAY=3
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_SF=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="FSL"
-CONFIG_G_DNL_VENDOR_NUM=0x0525
-CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
-# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_TARGET_MX6QSABREAUTO=y
-CONFIG_VIDEO=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q"
-CONFIG_BOOTDELAY=3
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_SF=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="FSL"
-CONFIG_G_DNL_VENDOR_NUM=0x0525
-CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
-# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TARGET_MX6QSABREAUTO=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_MX6SABREAUTO=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL,MX6QDL"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
-CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_DFU_MMC=y
CONFIG_DFU_SF=y
-CONFIG_MTD_NOR_FLASH=y
+# CONFIG_MTD_NOR_FLASH is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USB=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_BMODE is not set
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6SL,SYS_I2C"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6SL,SYS_I2C"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
# CONFIG_CMD_BMODE is not set
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM=y
+CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM=y
+CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6DL"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6q-zc5202.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6q-zc5601.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
- CONFIG_SYS_FSL_ESDHC_BE
ESDHC IP is in big-endian mode. Accessing ESDHC registers can be determined
by ESDHC IP's endian mode or processor's endian mode.
-
- - CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V.
value shall be set to one of the
values found in the file:
arch/arm/include/asm/\
- imx-common/imximage.cfg
+ mach-imx/imximage.cfg
Example:
BOOT_OFFSET FLASH_OFFSET_STANDARD
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/dma.h>
-#include <asm/imx-common/regs-apbh.h>
+#include <asm/mach-imx/dma.h>
+#include <asm/mach-imx/regs-apbh.h>
static struct mxs_dma_chan mxs_dma_channels[MXS_MAX_DMA_CHANNELS];
#include <errno.h>
#include <fdtdec.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <malloc.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <linux/errno.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <i2c.h>
#include <watchdog.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/sys_proto.h>
#define BO_CTRL_WR_UNLOCK 16
#define BM_CTRL_WR_UNLOCK 0xffff0000
#include <hwconfig.h>
#include <mmc.h>
#include <part.h>
+#include <power/regulator.h>
#include <malloc.h>
#include <fsl_esdhc.h>
#include <fdt_support.h>
* @dev: pointer for the device
* @non_removable: 0: removable; 1: non-removable
* @wp_enable: 1: enable checking wp; 0: no check
+ * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
* @cd_gpio: gpio for card detection
* @wp_gpio: gpio for write protection
*/
struct udevice *dev;
int non_removable;
int wp_enable;
+ int vs18_enable;
#ifdef CONFIG_DM_GPIO
struct gpio_desc cd_gpio;
struct gpio_desc wp_gpio;
/* Set timout to the maximum value */
esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
-#ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
- esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
-#endif
+ if (priv->vs18_enable)
+ esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
return 0;
}
VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
#endif
+ if (priv->vs18_enable)
+ esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+
writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
memset(&priv->cfg, 0, sizeof(priv->cfg));
priv->bus_width = cfg->max_bus_width;
priv->sdhc_clk = cfg->sdhc_clk;
priv->wp_enable = cfg->wp_enable;
+ priv->vs18_enable = cfg->vs18_enable;
return 0;
};
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
+ struct udevice *vqmmc_dev;
fdt_addr_t addr;
unsigned int val;
int ret;
if (ret)
priv->wp_enable = 0;
#endif
+
+ priv->vs18_enable = 0;
+
+#ifdef CONFIG_DM_REGULATOR
+ /*
+ * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
+ * otherwise, emmc will work abnormally.
+ */
+ ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
+ if (ret) {
+ dev_dbg(dev, "no vqmmc-supply\n");
+ } else {
+ ret = regulator_set_enable(vqmmc_dev, true);
+ if (ret) {
+ dev_err(dev, "fail to enable vqmmc-supply\n");
+ return ret;
+ }
+
+ if (regulator_get_value(vqmmc_dev) == 1800000)
+ priv->vs18_enable = 1;
+ }
+#endif
+
/*
* TODO:
* Because lack of clk driver, if SDHC clk is not enabled,
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/dma.h>
+#include <asm/mach-imx/dma.h>
#include <bouncebuf.h>
struct mxsmmc_priv {
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/regs-bch.h>
-#include <asm/imx-common/regs-gpmi.h>
+#include <asm/mach-imx/regs-bch.h>
+#include <asm/mach-imx/regs-gpmi.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/dma.h>
+#include <asm/mach-imx/dma.h>
#define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
}
/* Init the DMA controller. */
+ mxs_dma_init();
for (j = MXS_DMA_CHANNEL_AHB_APBH_GPMI0;
j <= MXS_DMA_CHANNEL_AHB_APBH_GPMI7; j++) {
ret = mxs_dma_init_channel(j);
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
if (ret)
return ret;
- bus = fec_get_miibus((uint32_t)priv->eth, dev_id);
- if (!bus)
- goto err_mii;
-
- priv->bus = bus;
- priv->xcv_type = CONFIG_FEC_XCV_TYPE;
- priv->interface = pdata->phy_interface;
- ret = fec_phy_init(priv, dev);
- if (ret)
- goto err_phy;
-
/* Reset chip. */
writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
&priv->eth->ecntrl);
fec_reg_setup(priv);
priv->dev_id = (dev_id == -1) ? 0 : dev_id;
+ bus = fec_get_miibus(dev, dev_id);
+ if (!bus) {
+ ret = -ENOMEM;
+ goto err_mii;
+ }
+
+ priv->bus = bus;
+ priv->xcv_type = CONFIG_FEC_XCV_TYPE;
+ priv->interface = pdata->phy_interface;
+ ret = fec_phy_init(priv, dev);
+ if (ret)
+ goto err_phy;
+
return 0;
err_timeout:
will need to provide parameters to make this work. The driver will
be available until the real driver model serial is running.
+config DEBUG_UART_MXC
+ bool "IMX Serial port"
+ depends on MXC_UART
+ help
+ Select this to enable a debug UART using the serial_mxc driver. You
+ will need to provide parameters to make this work. The driver will
+ be available until the real driver model serial is running.
+
config DEBUG_UART_UNIPHIER
bool "UniPhier on-chip UART"
depends on ARCH_UNIPHIER
#include <linux/compiler.h>
/* UART Control Register Bit Fields.*/
-#define URXD_CHARRDY (1<<15)
-#define URXD_ERR (1<<14)
-#define URXD_OVRRUN (1<<13)
-#define URXD_FRMERR (1<<12)
-#define URXD_BRK (1<<11)
-#define URXD_PRERR (1<<10)
-#define URXD_RX_DATA (0xFF)
-#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
-#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
-#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
-#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
-#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
-#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
-#define UCR1_IREN (1<<7) /* Infrared interface enable */
-#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
-#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
-#define UCR1_SNDBRK (1<<4) /* Send break */
-#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
-#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
-#define UCR1_DOZE (1<<1) /* Doze */
-#define UCR1_UARTEN (1<<0) /* UART enabled */
-#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
-#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
-#define UCR2_CTSC (1<<13) /* CTS pin control */
-#define UCR2_CTS (1<<12) /* Clear to send */
-#define UCR2_ESCEN (1<<11) /* Escape enable */
-#define UCR2_PREN (1<<8) /* Parity enable */
-#define UCR2_PROE (1<<7) /* Parity odd/even */
-#define UCR2_STPB (1<<6) /* Stop */
-#define UCR2_WS (1<<5) /* Word size */
-#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
-#define UCR2_TXEN (1<<2) /* Transmitter enabled */
-#define UCR2_RXEN (1<<1) /* Receiver enabled */
-#define UCR2_SRST (1<<0) /* SW reset */
-#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
-#define UCR3_PARERREN (1<<12) /* Parity enable */
-#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
-#define UCR3_DSR (1<<10) /* Data set ready */
-#define UCR3_DCD (1<<9) /* Data carrier detect */
-#define UCR3_RI (1<<8) /* Ring indicator */
-#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
-#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
-#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
-#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
-#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
-#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
-#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
-#define UCR3_BPEN (1<<0) /* Preset registers enable */
-#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
-#define UCR4_INVR (1<<9) /* Inverted infrared reception */
-#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
-#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
-#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
-#define UCR4_IRSC (1<<5) /* IR special case */
-#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
-#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
-#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
-#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
-#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
-#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
-#define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */
-#define UFCR_DCEDTE (1<<6) /* DTE mode select */
-#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
-#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
-#define USR1_RTSS (1<<14) /* RTS pin status */
-#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
-#define USR1_RTSD (1<<12) /* RTS delta */
-#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
-#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
-#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
-#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
-#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
-#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
-#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
-#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
-#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
-#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
-#define USR2_IDLE (1<<12) /* Idle condition */
-#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
-#define USR2_WAKE (1<<7) /* Wake */
-#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
-#define USR2_TXDC (1<<3) /* Transmitter complete */
-#define USR2_BRCD (1<<2) /* Break condition */
-#define USR2_ORE (1<<1) /* Overrun error */
-#define USR2_RDR (1<<0) /* Recv data ready */
-#define UTS_FRCPERR (1<<13) /* Force parity error */
-#define UTS_LOOP (1<<12) /* Loop tx and rx */
-#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
-#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
-#define UTS_TXFULL (1<<4) /* TxFIFO full */
-#define UTS_RXFULL (1<<3) /* RxFIFO full */
-#define UTS_SOFTRST (1<<0) /* Software reset */
+#define URXD_CHARRDY (1<<15)
+#define URXD_ERR (1<<14)
+#define URXD_OVRRUN (1<<13)
+#define URXD_FRMERR (1<<12)
+#define URXD_BRK (1<<11)
+#define URXD_PRERR (1<<10)
+#define URXD_RX_DATA (0xFF)
+#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
+#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
+#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
+#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
+#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
+#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
+#define UCR1_IREN (1<<7) /* Infrared interface enable */
+#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
+#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
+#define UCR1_SNDBRK (1<<4) /* Send break */
+#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
+#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
+#define UCR1_DOZE (1<<1) /* Doze */
+#define UCR1_UARTEN (1<<0) /* UART enabled */
+#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
+#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
+#define UCR2_CTSC (1<<13) /* CTS pin control */
+#define UCR2_CTS (1<<12) /* Clear to send */
+#define UCR2_ESCEN (1<<11) /* Escape enable */
+#define UCR2_PREN (1<<8) /* Parity enable */
+#define UCR2_PROE (1<<7) /* Parity odd/even */
+#define UCR2_STPB (1<<6) /* Stop */
+#define UCR2_WS (1<<5) /* Word size */
+#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
+#define UCR2_TXEN (1<<2) /* Transmitter enabled */
+#define UCR2_RXEN (1<<1) /* Receiver enabled */
+#define UCR2_SRST (1<<0) /* SW reset */
+#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
+#define UCR3_PARERREN (1<<12) /* Parity enable */
+#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
+#define UCR3_DSR (1<<10) /* Data set ready */
+#define UCR3_DCD (1<<9) /* Data carrier detect */
+#define UCR3_RI (1<<8) /* Ring indicator */
+#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
+#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
+#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
+#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
+#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
+#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
+#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
+#define UCR3_BPEN (1<<0) /* Preset registers enable */
+#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
+#define UCR4_INVR (1<<9) /* Inverted infrared reception */
+#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
+#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
+#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
+#define UCR4_IRSC (1<<5) /* IR special case */
+#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
+#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
+#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
+#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
+#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
+#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
+#define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */
+#define RFDIV 4 /* divide input clock by 2 */
+#define UFCR_DCEDTE (1<<6) /* DTE mode select */
+#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
+#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
+#define USR1_RTSS (1<<14) /* RTS pin status */
+#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
+#define USR1_RTSD (1<<12) /* RTS delta */
+#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
+#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
+#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
+#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
+#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
+#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
+#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
+#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
+#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
+#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
+#define USR2_IDLE (1<<12) /* Idle condition */
+#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
+#define USR2_WAKE (1<<7) /* Wake */
+#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
+#define USR2_TXDC (1<<3) /* Transmitter complete */
+#define USR2_BRCD (1<<2) /* Break condition */
+#define USR2_ORE (1<<1) /* Overrun error */
+#define USR2_RDR (1<<0) /* Recv data ready */
+#define UTS_FRCPERR (1<<13) /* Force parity error */
+#define UTS_LOOP (1<<12) /* Loop tx and rx */
+#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
+#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
+#define UTS_TXFULL (1<<4) /* TxFIFO full */
+#define UTS_RXFULL (1<<3) /* RxFIFO full */
+#define UTS_SOFTRS (1<<0) /* Software reset */
+#define TXTL 2 /* reset default */
+#define RXTL 1 /* reset default */
DECLARE_GLOBAL_DATA_PTR;
+struct mxc_uart {
+ u32 rxd;
+ u32 spare0[15];
+
+ u32 txd;
+ u32 spare1[15];
+
+ u32 cr1;
+ u32 cr2;
+ u32 cr3;
+ u32 cr4;
+
+ u32 fcr;
+ u32 sr1;
+ u32 sr2;
+ u32 esc;
+
+ u32 tim;
+ u32 bir;
+ u32 bmr;
+ u32 brc;
+
+ u32 onems;
+ u32 ts;
+};
+
+static void _mxc_serial_init(struct mxc_uart *base)
+{
+ writel(0, &base->cr1);
+ writel(0, &base->cr2);
+
+ while (!(readl(&base->cr2) & UCR2_SRST));
+
+ writel(0x704 | UCR3_ADNIMP, &base->cr3);
+ writel(0x8000, &base->cr4);
+ writel(0x2b, &base->esc);
+ writel(0, &base->tim);
+
+ writel(0, &base->ts);
+}
+
+static void _mxc_serial_setbrg(struct mxc_uart *base, unsigned long clk,
+ unsigned long baudrate, bool use_dte)
+{
+ u32 tmp;
+
+ tmp = RFDIV << UFCR_RFDIV_SHF;
+ if (use_dte)
+ tmp |= UFCR_DCEDTE;
+ else
+ tmp |= (TXTL << UFCR_TXTL_SHF) | (RXTL << UFCR_RXTL_SHF);
+ writel(tmp, &base->fcr);
+
+ writel(0xf, &base->bir);
+ writel(clk / (2 * baudrate), &base->bmr);
+
+ writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
+ &base->cr2);
+ writel(UCR1_UARTEN, &base->cr1);
+}
+
#ifndef CONFIG_DM_SERIAL
#ifndef CONFIG_MXC_UART_BASE
#error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
#endif
-#define UART_PHYS CONFIG_MXC_UART_BASE
-
-#define __REG(x) (*((volatile u32 *)(x)))
-
-/* Register definitions */
-#define URXD 0x0 /* Receiver Register */
-#define UTXD 0x40 /* Transmitter Register */
-#define UCR1 0x80 /* Control Register 1 */
-#define UCR2 0x84 /* Control Register 2 */
-#define UCR3 0x88 /* Control Register 3 */
-#define UCR4 0x8c /* Control Register 4 */
-#define UFCR 0x90 /* FIFO Control Register */
-#define USR1 0x94 /* Status Register 1 */
-#define USR2 0x98 /* Status Register 2 */
-#define UESC 0x9c /* Escape Character Register */
-#define UTIM 0xa0 /* Escape Timer Register */
-#define UBIR 0xa4 /* BRM Incremental Register */
-#define UBMR 0xa8 /* BRM Modulator Register */
-#define UBRC 0xac /* Baud Rate Count Register */
-#define UTS 0xb4 /* UART Test Register (mx31) */
-
-#define TXTL 2 /* reset default */
-#define RXTL 1 /* reset default */
-#define RFDIV 4 /* divide input clock by 2 */
+#define mxc_base ((struct mxc_uart *)CONFIG_MXC_UART_BASE)
static void mxc_serial_setbrg(void)
{
if (!gd->baudrate)
gd->baudrate = CONFIG_BAUDRATE;
- __REG(UART_PHYS + UFCR) = (RFDIV << UFCR_RFDIV_SHF)
- | (TXTL << UFCR_TXTL_SHF)
- | (RXTL << UFCR_RXTL_SHF);
- __REG(UART_PHYS + UBIR) = 0xf;
- __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
-
+ _mxc_serial_setbrg(mxc_base, clk, gd->baudrate, false);
}
static int mxc_serial_getc(void)
{
- while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
+ while (readl(&mxc_base->ts) & UTS_RXEMPTY)
WATCHDOG_RESET();
- return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */
+ return (readl(&mxc_base->rxd) & URXD_RX_DATA); /* mask out status from upper word */
}
static void mxc_serial_putc(const char c)
if (c == '\n')
serial_putc('\r');
- __REG(UART_PHYS + UTXD) = c;
+ writel(c, &mxc_base->txd);
/* wait for transmitter to be ready */
- while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY))
+ while (!(readl(&mxc_base->ts) & UTS_TXEMPTY))
WATCHDOG_RESET();
}
-/*
- * Test whether a character is in the RX buffer
- */
+/* Test whether a character is in the RX buffer */
static int mxc_serial_tstc(void)
{
/* If receive fifo is empty, return false */
- if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
+ if (readl(&mxc_base->ts) & UTS_RXEMPTY)
return 0;
return 1;
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
*/
static int mxc_serial_init(void)
{
- __REG(UART_PHYS + UCR1) = 0x0;
- __REG(UART_PHYS + UCR2) = 0x0;
-
- while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST));
-
- __REG(UART_PHYS + UCR3) = 0x0704 | UCR3_ADNIMP;
- __REG(UART_PHYS + UCR4) = 0x8000;
- __REG(UART_PHYS + UESC) = 0x002b;
- __REG(UART_PHYS + UTIM) = 0x0;
-
- __REG(UART_PHYS + UTS) = 0x0;
+ _mxc_serial_init(mxc_base);
serial_setbrg();
- __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST;
-
- __REG(UART_PHYS + UCR1) = UCR1_UARTEN;
-
return 0;
}
#ifdef CONFIG_DM_SERIAL
-struct mxc_uart {
- u32 rxd;
- u32 spare0[15];
-
- u32 txd;
- u32 spare1[15];
-
- u32 cr1;
- u32 cr2;
- u32 cr3;
- u32 cr4;
-
- u32 fcr;
- u32 sr1;
- u32 sr2;
- u32 esc;
-
- u32 tim;
- u32 bir;
- u32 bmr;
- u32 brc;
-
- u32 onems;
- u32 ts;
-};
-
int mxc_serial_setbrg(struct udevice *dev, int baudrate)
{
struct mxc_serial_platdata *plat = dev->platdata;
- struct mxc_uart *const uart = plat->reg;
u32 clk = imx_get_uartclk();
- u32 tmp;
-
- tmp = 4 << UFCR_RFDIV_SHF;
- if (plat->use_dte)
- tmp |= UFCR_DCEDTE;
- writel(tmp, &uart->fcr);
-
- writel(0xf, &uart->bir);
- writel(clk / (2 * baudrate), &uart->bmr);
- writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
- &uart->cr2);
- writel(UCR1_UARTEN, &uart->cr1);
+ _mxc_serial_setbrg(plat->reg, clk, baudrate, plat->use_dte);
return 0;
}
static int mxc_serial_probe(struct udevice *dev)
{
struct mxc_serial_platdata *plat = dev->platdata;
- struct mxc_uart *const uart = plat->reg;
- writel(0, &uart->cr1);
- writel(0, &uart->cr2);
- while (!(readl(&uart->cr2) & UCR2_SRST));
- writel(0x704 | UCR3_ADNIMP, &uart->cr3);
- writel(0x8000, &uart->cr4);
- writel(0x2b, &uart->esc);
- writel(0, &uart->tim);
- writel(0, &uart->ts);
+ _mxc_serial_init(plat->reg);
return 0;
}
.flags = DM_FLAG_PRE_RELOC,
};
#endif
+
+#ifdef CONFIG_DEBUG_UART_MXC
+#include <debug_uart.h>
+
+static inline void _debug_uart_init(void)
+{
+ struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
+
+ _mxc_serial_init(base);
+ _mxc_serial_setbrg(base, CONFIG_DEBUG_UART_CLOCK,
+ CONFIG_BAUDRATE, false);
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+ struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
+
+ while (!(readl(&base->ts) & UTS_TXEMPTY))
+ WATCHDOG_RESET();
+
+ writel(ch, &base->txd);
+}
+
+DEBUG_UART_FUNCS
+
+#endif
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
-#include <asm/imx-common/spi.h>
+#include <asm/mach-imx/spi.h>
#ifdef CONFIG_MX27
/* i.MX27 has a completely wrong register layout and register definitions in the
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/dma.h>
+#include <asm/mach-imx/dma.h>
#define MXS_SPI_MAX_TIMEOUT 1000000
#define MXS_SPI_PORT_OFFSET 0x2000
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sys_proto.h>
#include <dm.h>
#include <asm/mach-types.h>
#include <power/regulator.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/regs-usbphy.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/regs-usbphy.h>
#include <usb/ehci-ci.h>
#include <libfdt.h>
#include <fdtdec.h>
#include <linux/errno.h>
#include <asm/io.h>
-#include <asm/imx-common/dma.h>
+#include <asm/mach-imx/dma.h>
#include "videomodes.h"
#define __ADVANTECH_DMSBA16_CONFIG_H
#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#define CONFIG_BOARD_NAME "Advantech DMS-BA16"
#define CONFIG_SYS_GENERIC_BOARD
#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#ifdef CONFIG_SPL
#include "imx6_spl.h"
#define CONFIG_SYS_GENERIC_BOARD
#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#ifdef CONFIG_SPL
#include "imx6_spl.h"
#define CONFIG_MXC_UART_BASE UART2_BASE
#define CONSOLE_DEV "ttymxc1"
-#define CONFIG_MMCROOT "/dev/mmcblk1p2"
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
+#define CONFIG_BOOTCOMMAND \
+ "run finduuid; " \
+ "run distro_bootcmd"
+
#include <config_distro_bootcmd.h>
#define CONSOLE_STDIN_SETTINGS \
CONSOLE_ENV_SETTINGS \
MEM_LAYOUT_ENV_SETTINGS \
"fdtfile=" CONFIG_FDTFILE "\0" \
+ "finduuid=part uuid mmc 0:1 uuid\0" \
BOOTENV
#endif /* __RIOTBOARD_CONFIG_H */
#define __GE_BX50V3_CONFIG_H
#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#define BX50V3_BOOTARGS_EXTRA
#if defined(CONFIG_TARGET_GE_B450V3)
/* Define the payload for FAT/EXT support */
#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
+# ifdef CONFIG_OF_CONTROL
+# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
+# else
+# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
+# endif
#endif
#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6SL)
#define CONFIG_SYS_TEXT_BASE 0x77800000
#define CONFIG_EXTRA_ENV_SETTINGS \
- "fdt_addr=0x71ff0000\0" \
- "rdaddr=0x72000000\0" \
+ "fdt_addr_r=0x71ff0000\0" \
+ "pxefile_addr_r=0x73000000\0" \
+ "ramdisk_addr_r=0x72000000\0" \
"console=ttymxc1,115200\0" \
"uenv=/boot/uEnv.txt\0" \
"optargs=\0" \
"rootfstype=${mmcrootfstype} " \
"${cmdline}\0" \
"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
- "loadrd=load mmc ${bootpart} ${rdaddr} ${bootdir}/${rdfile};" \
+ "loadpxe=dhcp;setenv kernel_addr_r ${loadaddr};pxe get;pxe boot;\0" \
+ "loadrd=load mmc ${bootpart} ${ramdisk_addr_r} ${bootdir}/${rdfile};" \
"setenv rdsize ${filesize}\0" \
"loadfdt=echo loading ${fdt_path} ...;" \
- "load mmc ${bootpart} ${fdt_addr} ${fdt_path}\0" \
+ "load mmc ${bootpart} ${fdt_addr_r} ${fdt_path}\0" \
"mmcboot=mmc dev ${mmcdev}; " \
"if mmc rescan; then " \
"echo SD/MMC found on device ${mmcdev};" \
"fi;" \
"run mmcargs;" \
"echo debug: [${bootargs}] ... ;" \
- "echo debug: [bootz ${loadaddr} - ${fdt_addr}] ... ;" \
- "bootz ${loadaddr} - ${fdt_addr}; " \
+ "echo debug: [bootz ${loadaddr} - ${fdt_addr_r}];" \
+ "bootz ${loadaddr} - ${fdt_addr_r}; " \
+ "else " \
+ "echo loading from dhcp ...; " \
+ "run loadpxe; " \
"fi;\0"
#define CONFIG_BOOTCOMMAND \
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#ifndef CONFIG_MX6
#define CONFIG_MX6
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+/* SATA Configuration */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE 1
+#define CONFIG_DWC_AHSATA_PORT_ID 0
+#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
/* Ethernet Configuration */
#define CONFIG_FEC_MXC
#define CONFIG_MII
"console=" CONSOLE_DEV ",115200\0" \
"bootm_size=0x10000000\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+ "finduuid=part uuid mmc 0:1 uuid\0" \
"update_sd_firmware=" \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
#define CONFIG_BOOTCOMMAND \
"run findfdt; " \
+ "run finduuid; " \
"run distro_bootcmd"
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
+ func(SATA, sata, 0) \
func(USB, usb, 0) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
"initrd_high=0xffffffff\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
- "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
"update_sd_firmware=" \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"fi\0" \
EMMC_ENV \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
- "root=${mmcroot}\0" \
+ "root=PARTUUID=${uuid} rootwait rw\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
+ "run finduuid; " \
"run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __MX6QSABREAUTO_CONFIG_H
-#define __MX6QSABREAUTO_CONFIG_H
+#ifndef __MX6SABREAUTO_CONFIG_H
+#define __MX6SABREAUTO_CONFIG_H
+
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+#endif
#define CONFIG_MACH_TYPE 3529
#define CONFIG_MXC_UART_BASE UART4_BASE
#define CONSOLE_DEV "ttymxc3"
-#define CONFIG_MMCROOT "/dev/mmcblk0p2"
/* USB Configs */
#define CONFIG_USB_HOST_ETHER
#include "mx6sabre_common.h"
+/* Falcon Mode */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
+#define CONFIG_CMD_SPL
+#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
+#define CONFIG_CMD_SPL_WRITE_SIZE (128 * SZ_1K)
+
+/* Falcon Mode - MMC support: args@1MB kernel@2MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */
+#endif
+
+#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#endif
#define CONFIG_SYS_FSL_USDHC_NUM 2
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
-#endif /* __MX6QSABREAUTO_CONFIG_H */
+#endif /* __MX6SABREAUTO_CONFIG_H */
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __MX6QSABRESD_CONFIG_H
-#define __MX6QSABRESD_CONFIG_H
+#ifndef __MX6SABRESD_CONFIG_H
+#define __MX6SABRESD_CONFIG_H
#ifdef CONFIG_SPL
#include "imx6_spl.h"
#define CONFIG_MACH_TYPE 3980
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONSOLE_DEV "ttymxc0"
-#define CONFIG_MMCROOT "/dev/mmcblk1p2"
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */
#endif
-#endif /* __MX6QSABRESD_CONFIG_H */
+#endif /* __MX6SABRESD_CONFIG_H */
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
#include "mx6_common.h"
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#define is_mx6ul_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK)
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
#include "mx6_common.h"
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#ifdef CONFIG_SECURE_BOOT
#ifndef CONFIG_CSF_SIZE
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#ifndef CONFIG_MX7
#define CONFIG_MX7
#define CONFIG_PREBOOT ""
+/* Thermal support */
+#define CONFIG_IMX_THERMAL
+
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
#include "mx6_common.h"
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
/* Network support */
"fdt_addr=0x18000000\0" \
"ip_dyn=yes\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+ "finduuid=part uuid mmc 0:1 uuid\0" \
"update_sd_firmware_filename=u-boot.imx\0" \
"update_sd_firmware=" \
"if test ${ip_dyn} = yes; then " \
#define CONFIG_BOOTCOMMAND \
"run findfdt; " \
+ "run finduuid; " \
"run distro_bootcmd"
#include <config_distro_bootcmd.h>
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-#define CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
#define CONFIG_SUPPORT_EMMC_BOOT
"ip_dyn=yes\0" \
"mmcdev=0\0" \
"mmcpart=1\0" \
- "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+ "finduuid=part uuid mmc 0:2 uuid\0" \
"dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
- "root=${mmcroot}\0" \
+ "root=PARTUUID=${uuid} rootwait rw\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
+ "run finduuid; " \
"run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
#define __XPRESS_CONFIG_H
#include "mx6_common.h"
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
/* SPL options */
#include "imx6_spl.h"
phys_addr_t esdhc_base;
u32 sdhc_clk;
u8 max_bus_width;
- u8 wp_enable;
+ int wp_enable;
+ int vs18_enable; /* Use 1.8V if set to 1 */
struct mmc_config cfg;
};
CONFIG_SYS_FSL_ESDHC_ADDR
CONFIG_SYS_FSL_ESDHC_BE
CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
CONFIG_SYS_FSL_ESDHC_LE
CONFIG_SYS_FSL_ESDHC_NUM
/*
* NOTE: This file must be kept in sync with arch/arm/include/asm/\
- * imx-common/imximage.cfg because tools/imximage.c can not
+ * mach-imx/imximage.cfg because tools/imximage.c can not
* cross-include headers from arch/arm/ and vice-versa.
*/
#define CMD_DATA_STR "DATA"
projects / people / ms / u-boot.git / commitdiff
