Merge git://git.denx.de/u-boot-socfpga

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7b618d6881759697aaa9b24f3c3758d2fdae25df..77cb20090c4f6204736920e360581dae2e263137 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -698,16 +698,17 @@ config ARCH_SOCFPGA
        select OF_CONTROL
        select SPL_OF_CONTROL
        select DM
-       select DM_SPI_FLASH
-       select DM_SPI
        select ENABLE_ARM_SOC_BOOT0_HOOK
        select ARCH_EARLY_INIT_R
        select ARCH_MISC_INIT
-       select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
        select SYS_THUMB_BUILD
        imply CMD_MTDPARTS
        imply CRC32_VERIFY
+       imply DM_SPI
+       imply DM_SPI_FLASH
        imply FAT_WRITE
+       imply HW_WATCHDOG
+       imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
 
 config ARCH_SUNXI
        bool "Support sunxi (Allwinner) SoCs"

diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts
index 1e91a65af6b197ec331231c1eb80a9400d8a11f1..4e4b619f4f9cb071cbce21d11ee88028cb67233f 100644 (file)
--- a/arch/arm/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/dts/socfpga_arria5_socdk.dts
@@ -88,7 +88,7 @@
                u-boot,dm-pre-reloc;
                #address-cells = <1>;
                #size-cells = <1>;
-               compatible = "n25q00";
+               compatible = "n25q00", "spi-flash";
                reg = <0>;      /* chip select */
                spi-max-frequency = <50000000>;
                m25p,fast-read;

diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts
index 2e2b71fefb6c4771b0f4b98741f9eb4e2e541e74..ea323a16caac3ad80600bca185938f4b87eb2b78 100644 (file)
--- a/arch/arm/dts/socfpga_cyclone5_is1.dts
+++ b/arch/arm/dts/socfpga_cyclone5_is1.dts
@@ -87,7 +87,7 @@
                u-boot,dm-pre-reloc;
                #address-cells = <1>;
                #size-cells = <1>;
-               compatible = "n25q00";
+               compatible = "n25q00", "spi-flash";
                reg = <0>;      /* chip select */
                spi-max-frequency = <100000000>;
                m25p,fast-read;

diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index 95a8e653d7f51855db33407047394fe1f5b65835..3af51134bbec6c5e97951641cf005541cc1ca0ab 100644 (file)
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -98,7 +98,7 @@
                u-boot,dm-pre-reloc;
                #address-cells = <1>;
                #size-cells = <1>;
-               compatible = "n25q00";
+               compatible = "n25q00", "spi-flash";
                reg = <0>;      /* chip select */
                spi-max-frequency = <100000000>;
                m25p,fast-read;

diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index e3ae8a820795d17cbabdbf564ed95313fccd76df..e612eeed4ffc787246d4f676c5ac6c418395bd92 100644 (file)
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -68,7 +68,7 @@
        flash0: n25q00@0 {
                #address-cells = <1>;
                #size-cells = <1>;
-               compatible = "n25q00";
+               compatible = "n25q00", "spi-flash";
                reg = <0>;      /* chip select */
                spi-max-frequency = <50000000>;
                m25p,fast-read;

diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h
index 83718dd2c9cb9864e77079a859f7bc8890acc2f8..82bb48b2777022c92b0e197dab16c17459d80208 100644 (file)
--- a/include/configs/socfpga_arria10_socdk.h
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -9,8 +9,6 @@
 
 #include <asm/arch/base_addr_a10.h>
 
-#define CONFIG_HW_WATCHDOG
-
 /* Booting Linux */
 #define CONFIG_LOADADDR                0x01000000
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR

diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h
index 6b6d54b97b1a571e06391d3aeacf5736219fc683..cd5aac65e922115d186709bd0e18c19fa4122fef 100644 (file)
--- a/include/configs/socfpga_arria5_socdk.h
+++ b/include/configs/socfpga_arria5_socdk.h
@@ -8,8 +8,6 @@
 
 #include <asm/arch/base_addr_ac5.h>
 
-#define CONFIG_HW_WATCHDOG
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB on SoCDK */
 

diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h
index 018a0c3bb48a494de01937740f620f26fa30521b..9c5bd648e3d4d82d756519b2fc1adde8e2b70eda 100644 (file)
--- a/include/configs/socfpga_cyclone5_socdk.h
+++ b/include/configs/socfpga_cyclone5_socdk.h
@@ -8,8 +8,6 @@
 
 #include <asm/arch/base_addr_ac5.h>
 
-#define CONFIG_HW_WATCHDOG
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB on SoCDK */
 

diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h
index 275ed7ffebbdbbc8dafc14cc4e3e14e5bb918cc1..e5db00e36612a8accb51712f265764ecf987c22a 100644 (file)
--- a/include/configs/socfpga_de0_nano_soc.h
+++ b/include/configs/socfpga_de0_nano_soc.h
@@ -8,8 +8,6 @@
 
 #include <asm/arch/base_addr_ac5.h>
 
-#define CONFIG_HW_WATCHDOG
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB */
 

diff --git a/include/configs/socfpga_de10_nano.h b/include/configs/socfpga_de10_nano.h
index bb50fcf1ff02600d06404a7e9bfd9e9c30696aee..656af1104dd7e17a3c99a841434641cd2954c219 100644 (file)
--- a/include/configs/socfpga_de10_nano.h
+++ b/include/configs/socfpga_de10_nano.h
@@ -8,8 +8,6 @@
 
 #include <asm/arch/base_addr_ac5.h>
 
-#define CONFIG_HW_WATCHDOG
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB */
 

diff --git a/include/configs/socfpga_de1_soc.h b/include/configs/socfpga_de1_soc.h
index 05975c9bde4b458d877543dbdd8eb5c6b9953b2a..f57b9504259eccd7a2e9f2f84538b266f940fa7f 100644 (file)
--- a/include/configs/socfpga_de1_soc.h
+++ b/include/configs/socfpga_de1_soc.h
@@ -8,8 +8,6 @@
 
 #include <asm/arch/base_addr_ac5.h>
 
-#define CONFIG_HW_WATCHDOG
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB */
 

diff --git a/include/configs/socfpga_is1.h b/include/configs/socfpga_is1.h
index 883ffb76f3eccc5a0ecf63fbff4e6346493f3285..f2c3f405549ad5b3cb8532f0572a9d33c7bf6012 100644 (file)
--- a/include/configs/socfpga_is1.h
+++ b/include/configs/socfpga_is1.h
@@ -9,8 +9,6 @@
 
 #include <asm/arch/base_addr_ac5.h>
 
-#define CONFIG_HW_WATCHDOG
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x10000000
 

diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h
index 404f064e948a42918e35817446e3cc242f61c5d6..f13463b8b0681f814de946bfe900a2872e531669 100644 (file)
--- a/include/configs/socfpga_mcvevk.h
+++ b/include/configs/socfpga_mcvevk.h
@@ -8,8 +8,6 @@
 
 #include <asm/arch/base_addr_ac5.h>
 
-#define CONFIG_HW_WATCHDOG
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB on MCV */
 

diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h
index b4f31c42c5083fe20af894095e044d6d13e2cc5e..0bbc7e010541d1347d454d9037939b98df37d6a0 100644 (file)
--- a/include/configs/socfpga_sockit.h
+++ b/include/configs/socfpga_sockit.h
@@ -8,8 +8,6 @@
 
 #include <asm/arch/base_addr_ac5.h>
 
-#define CONFIG_HW_WATCHDOG
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB on SoCDK */
 

diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h
index ebb9ac588d7b270b158d2ba38ee24c4317b8ab1c..b66108d0ccd49f7fecfb1ef33dfaae0ee0ba17e0 100644 (file)
--- a/include/configs/socfpga_socrates.h
+++ b/include/configs/socfpga_socrates.h
@@ -8,8 +8,6 @@
 
 #include <asm/arch/base_addr_ac5.h>
 
-#define CONFIG_HW_WATCHDOG
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB on SoCrates */
 

diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h
index 8c9069c923ded146e344d20fb39a296ed8dc001a..8879817b3020ed503eac0f5ab4ee6d2d178b9524 100644 (file)
--- a/include/configs/socfpga_sr1500.h
+++ b/include/configs/socfpga_sr1500.h
@@ -8,8 +8,6 @@
 
 #include <asm/arch/base_addr_ac5.h>
 
-#define CONFIG_HW_WATCHDOG
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB on SR1500 */
 

diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h
index 0c76a775256de18e5446ac7bff9d78941d703bb6..1197b40b58b2286a09b07492fd10afdc063dc38b 100644 (file)
--- a/include/configs/socfpga_vining_fpga.h
+++ b/include/configs/socfpga_vining_fpga.h
@@ -8,8 +8,6 @@
 
 #include <asm/arch/base_addr_ac5.h>
 
-#define CONFIG_HW_WATCHDOG
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB on VINING_FPGA */