spl/u-boot-spl.ais: spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
-OBJCOPYFLAGS_u-boot.ais = -I binary -O binary --pad-to=$(CONFIG_SPL_MAX_SIZE)
+OBJCOPYFLAGS_u-boot.ais = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO)
u-boot.ais: spl/u-boot-spl.ais u-boot.img FORCE
$(call if_changed,pad_cat)
CONFIG_SH_MMCIF_CLK
Define the clock frequency for MMCIF
+ CONFIG_GENERIC_MMC
+ Enable the generic MMC driver
+
+ CONFIG_SUPPORT_EMMC_BOOT
+ Enable some additional features of the eMMC boot partitions.
+
+ CONFIG_SUPPORT_EMMC_RPMB
+ Enable the commands for reading, writing and programming the
+ key for the Replay Protection Memory Block partition in eMMC.
+
- USB Device Firmware Update (DFU) class support:
CONFIG_DFU_FUNCTION
This enables the USB portion of the DFU USB class
entering dfuMANIFEST state. Host waits this timeout, before
sending again an USB request to the device.
+- USB Device Android Fastboot support:
+ CONFIG_CMD_FASTBOOT
+ This enables the command "fastboot" which enables the Android
+ fastboot mode for the platform's USB device. Fastboot is a USB
+ protocol for downloading images, flashing and device control
+ used on Android devices.
+ See doc/README.android-fastboot for more information.
+
+ CONFIG_ANDROID_BOOT_IMAGE
+ This enables support for booting images which use the Android
+ image format header.
+
+ CONFIG_USB_FASTBOOT_BUF_ADDR
+ The fastboot protocol requires a large memory buffer for
+ downloads. Define this to the starting RAM address to use for
+ downloaded images.
+
+ CONFIG_USB_FASTBOOT_BUF_SIZE
+ The fastboot protocol requires a large memory buffer for
+ downloads. This buffer should be as large as possible for a
+ platform. Define this to the size available RAM for fastboot.
+
- Journaling Flash filesystem support:
CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
CONFIG_JFFS2_NAND_DEV
Specify the number of FPGA devices to support.
+ CONFIG_CMD_FPGA_LOADMK
+
+ Enable support for fpga loadmk command
+
+ CONFIG_CMD_FPGA_LOADP
+
+ Enable support for fpga loadp command - load partial bitstream
+
+ CONFIG_CMD_FPGA_LOADBP
+
+ Enable support for fpga loadbp command - load partial bitstream
+ (Xilinx only)
+
CONFIG_SYS_FPGA_PROG_FEEDBACK
Enable printing of hash marks during FPGA configuration.
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
-.globl _start
-_start: b reset
-#ifdef CONFIG_SPL_BUILD
- ldr pc, _hang
- ldr pc, _hang
- ldr pc, _hang
- ldr pc, _hang
- ldr pc, _hang
- ldr pc, _hang
- ldr pc, _hang
-_hang:
- .word do_hang
- .word 0x12345678
- .word 0x12345678
- .word 0x12345678
- .word 0x12345678
- .word 0x12345678
- .word 0x12345678
- .word 0x12345678 /* now 16*4=64 */
-#else
- ldr pc, _undefined_instruction
- ldr pc, _software_interrupt
- ldr pc, _prefetch_abort
- ldr pc, _data_abort
- ldr pc, _not_used
- ldr pc, _irq
- ldr pc, _fiq
-
-_undefined_instruction: .word undefined_instruction
-_software_interrupt: .word software_interrupt
-_prefetch_abort: .word prefetch_abort
-_data_abort: .word data_abort
-_not_used: .word not_used
-_irq: .word irq
-_fiq: .word fiq
-_pad: .word 0x12345678 /* now 16*4=64 */
-#endif /* CONFIG_SPL_BUILD */
-.global _end_vect
-_end_vect:
-
- .balignl 16,0xdeadbeef
/*
*************************************************************************
*
*************************************************************************
*/
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
- .word 0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
- .word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
- .word 0x0badc0de
-
-/*
- * the actual reset code
- */
+ .globl reset
reset:
/*
mov lr, ip /* restore link */
mov pc, lr /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-#ifndef CONFIG_SPL_BUILD
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE 72
-
-#define S_OLD_R0 68
-#define S_PSR 64
-#define S_PC 60
-#define S_LR 56
-#define S_SP 52
-
-#define S_IP 48
-#define S_FP 44
-#define S_R10 40
-#define S_R9 36
-#define S_R8 32
-#define S_R7 28
-#define S_R6 24
-#define S_R5 20
-#define S_R4 16
-#define S_R3 12
-#define S_R2 8
-#define S_R1 4
-#define S_R0 0
-
-#define MODE_SVC 0x13
-#define I_BIT 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
- .macro bad_save_user_regs
- sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
- stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
-
- ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
- ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
- add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
-
- add r5, sp, #S_SP
- mov r1, lr
- stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
- mov r0, sp @ save current stack into r0 (param register)
- .endm
-
- .macro irq_save_user_regs
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} @ Calling r0-r12
- add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
- stmdb r8, {sp, lr}^ @ Calling SP, LR
- str lr, [r8, #0] @ Save calling PC
- mrs r6, spsr
- str r6, [r8, #4] @ Save CPSR
- str r0, [r8, #8] @ Save OLD_R0
- mov r0, sp
- .endm
-
- .macro irq_restore_user_regs
- ldmia sp, {r0 - lr}^ @ Calling r0 - lr
- mov r0, r0
- ldr lr, [sp, #S_PC] @ Get PC
- add sp, sp, #S_FRAME_SIZE
- subs pc, lr, #4 @ return & move spsr_svc into cpsr
- .endm
-
- .macro get_bad_stack
- ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
-
- str lr, [r13] @ save caller lr in position 0 of saved stack
- mrs lr, spsr @ get the spsr
- str lr, [r13, #4] @ save spsr in position 1 of saved stack
-
- mov r13, #MODE_SVC @ prepare SVC-Mode
- @ msr spsr_c, r13
- msr spsr, r13 @ switch modes, make sure moves will execute
- mov lr, pc @ capture return pc
- movs pc, lr @ jump to next instruction & switch modes.
- .endm
-
- .macro get_bad_stack_swi
- sub r13, r13, #4 @ space on current stack for scratch reg.
- str r0, [r13] @ save R0's value.
- ldr r0, IRQ_STACK_START_IN @ get data regions start
- str lr, [r0] @ save caller lr in position 0 of saved stack
- mrs lr, spsr @ get the spsr
- str lr, [r0, #4] @ save spsr in position 1 of saved stack
- ldr lr, [r0] @ restore lr
- ldr r0, [r13] @ restore r0
- add r13, r13, #4 @ pop stack entry
- .endm
-
- .macro get_irq_stack @ setup IRQ stack
- ldr sp, IRQ_STACK_START
- .endm
-
- .macro get_fiq_stack @ setup FIQ stack
- ldr sp, FIQ_STACK_START
- .endm
-#endif /* CONFIG_SPL_BUILD */
-
-/*
- * exception handlers
- */
-#ifdef CONFIG_SPL_BUILD
- .align 5
-do_hang:
- bl hang /* hang and never return */
-#else /* !CONFIG_SPL_BUILD */
- .align 5
-undefined_instruction:
- get_bad_stack
- bad_save_user_regs
- bl do_undefined_instruction
-
- .align 5
-software_interrupt:
- get_bad_stack_swi
- bad_save_user_regs
- bl do_software_interrupt
-
- .align 5
-prefetch_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_prefetch_abort
-
- .align 5
-data_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_data_abort
-
- .align 5
-not_used:
- get_bad_stack
- bad_save_user_regs
- bl do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
- .align 5
-irq:
- get_irq_stack
- irq_save_user_regs
- bl do_irq
- irq_restore_user_regs
-
- .align 5
-fiq:
- get_fiq_stack
- /* someone ought to write a more effiction fiq_save_user_regs */
- irq_save_user_regs
- bl do_fiq
- irq_restore_user_regs
-
-#else
-
- .align 5
-irq:
- get_bad_stack
- bad_save_user_regs
- bl do_irq
-
- .align 5
-fiq:
- get_bad_stack
- bad_save_user_regs
- bl do_fiq
-
-#endif
- .align 5
-.global arm1136_cache_flush
-arm1136_cache_flush:
-#if !defined(CONFIG_SYS_ICACHE_OFF)
- mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
-#endif
-#if !defined(CONFIG_SYS_DCACHE_OFF)
- mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache
-#endif
- mov pc, lr @ back to caller
-#endif /* CONFIG_SPL_BUILD */
#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
#endif
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-.globl _start
-_start: b reset
-#ifndef CONFIG_SPL_BUILD
- ldr pc, _undefined_instruction
- ldr pc, _software_interrupt
- ldr pc, _prefetch_abort
- ldr pc, _data_abort
- ldr pc, _not_used
- ldr pc, _irq
- ldr pc, _fiq
-
-_undefined_instruction:
- .word undefined_instruction
-_software_interrupt:
- .word software_interrupt
-_prefetch_abort:
- .word prefetch_abort
-_data_abort:
- .word data_abort
-_not_used:
- .word not_used
-_irq:
- .word irq
-_fiq:
- .word fiq
-_pad:
- .word 0x12345678 /* now 16*4=64 */
-#else
- . = _start + 64
-#endif
-
-.global _end_vect
-_end_vect:
- .balignl 16,0xdeadbeef
/*
*************************************************************************
*
*************************************************************************
*/
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
- .word 0x0badc0de
-
-/*
- * the actual reset code
- */
+ .globl reset
reset:
/*
c_runtime_cpu_setup:
mov pc, lr
-
-#ifndef CONFIG_SPL_BUILD
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE 72
-
-#define S_OLD_R0 68
-#define S_PSR 64
-#define S_PC 60
-#define S_LR 56
-#define S_SP 52
-
-#define S_IP 48
-#define S_FP 44
-#define S_R10 40
-#define S_R9 36
-#define S_R8 32
-#define S_R7 28
-#define S_R6 24
-#define S_R5 20
-#define S_R4 16
-#define S_R3 12
-#define S_R2 8
-#define S_R1 4
-#define S_R0 0
-
-#define MODE_SVC 0x13
-#define I_BIT 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- */
-
- .macro bad_save_user_regs
- /* carve out a frame on current user stack */
- sub sp, sp, #S_FRAME_SIZE
- /* Save user registers (now in svc mode) r0-r12 */
- stmia sp, {r0 - r12}
-
- ldr r2, IRQ_STACK_START_IN
- /* get values for "aborted" pc and cpsr (into parm regs) */
- ldmia r2, {r2 - r3}
- /* grab pointer to old stack */
- add r0, sp, #S_FRAME_SIZE
-
- add r5, sp, #S_SP
- mov r1, lr
- /* save sp_SVC, lr_SVC, pc, cpsr */
- stmia r5, {r0 - r3}
- /* save current stack into r0 (param register) */
- mov r0, sp
- .endm
-
- .macro get_bad_stack
- ldr r13, IRQ_STACK_START_IN @ setup our mode stack
-
- /* save caller lr in position 0 of saved stack */
- str lr, [r13]
- /* get the spsr */
- mrs lr, spsr
- /* save spsr in position 1 of saved stack */
- str lr, [r13, #4]
-
- /* prepare SVC-Mode */
- mov r13, #MODE_SVC
- @ msr spsr_c, r13
- /* switch modes, make sure moves will execute */
- msr spsr, r13
- /* capture return pc */
- mov lr, pc
- /* jump to next instruction & switch modes. */
- movs pc, lr
- .endm
-
- .macro get_bad_stack_swi
- /* space on current stack for scratch reg. */
- sub r13, r13, #4
- /* save R0's value. */
- str r0, [r13]
- ldr r13, IRQ_STACK_START_IN @ setup our mode stack
- /* save caller lr in position 0 of saved stack */
- str lr, [r0]
- /* get the spsr */
- mrs lr, spsr
- /* save spsr in position 1 of saved stack */
- str lr, [r0, #4]
- /* restore lr */
- ldr lr, [r0]
- /* restore r0 */
- ldr r0, [r13]
- /* pop stack entry */
- add r13, r13, #4
- .endm
-
-/*
- * exception handlers
- */
- .align 5
-undefined_instruction:
- get_bad_stack
- bad_save_user_regs
- bl do_undefined_instruction
-
- .align 5
-software_interrupt:
- get_bad_stack_swi
- bad_save_user_regs
- bl do_software_interrupt
-
- .align 5
-prefetch_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_prefetch_abort
-
- .align 5
-data_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_data_abort
-
- .align 5
-not_used:
- get_bad_stack
- bad_save_user_regs
- bl do_not_used
-
- .align 5
-irq:
- get_bad_stack
- bad_save_user_regs
- bl do_irq
-
- .align 5
-fiq:
- get_bad_stack
- bad_save_user_regs
- bl do_fiq
-#endif /* CONFIG_SPL_BUILD */
#include <version.h>
#include <asm/hardware.h>
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-
-.globl _start
-_start: b reset
- ldr pc, _undefined_instruction
- ldr pc, _software_interrupt
- ldr pc, _prefetch_abort
- ldr pc, _data_abort
- ldr pc, _not_used
- ldr pc, _irq
- ldr pc, _fiq
-
-#ifdef CONFIG_SPL_BUILD
-_undefined_instruction: .word _undefined_instruction
-_software_interrupt: .word _software_interrupt
-_prefetch_abort: .word _prefetch_abort
-_data_abort: .word _data_abort
-_not_used: .word _not_used
-_irq: .word _irq
-_fiq: .word _fiq
-_pad: .word 0x12345678 /* now 16*4=64 */
-#else
-_undefined_instruction: .word undefined_instruction
-_software_interrupt: .word software_interrupt
-_prefetch_abort: .word prefetch_abort
-_data_abort: .word data_abort
-_not_used: .word not_used
-_irq: .word irq
-_fiq: .word fiq
-_pad: .word 0x12345678 /* now 16*4=64 */
-#endif /* CONFIG_SPL_BUILD */
-
- .balignl 16,0xdeadbeef
-
-
/*
*************************************************************************
*
*************************************************************************
*/
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
- .word 0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
- .word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
- .word 0x0badc0de
-
-/*
- * the actual reset code
- */
+ .globl reset
reset:
/*
mov pc, lr
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-
-#ifndef CONFIG_SPL_BUILD
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE 72
-
-#define S_OLD_R0 68
-#define S_PSR 64
-#define S_PC 60
-#define S_LR 56
-#define S_SP 52
-
-#define S_IP 48
-#define S_FP 44
-#define S_R10 40
-#define S_R9 36
-#define S_R8 32
-#define S_R7 28
-#define S_R6 24
-#define S_R5 20
-#define S_R4 16
-#define S_R3 12
-#define S_R2 8
-#define S_R1 4
-#define S_R0 0
-
-#define MODE_SVC 0x13
-#define I_BIT 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
- .macro bad_save_user_regs
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} @ Calling r0-r12
- add r8, sp, #S_PC
-
- ldr r2, IRQ_STACK_START_IN
- ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
- add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
-
- add r5, sp, #S_SP
- mov r1, lr
- stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
- mov r0, sp
- .endm
-
- .macro irq_save_user_regs
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} @ Calling r0-r12
- add r8, sp, #S_PC
- stmdb r8, {sp, lr}^ @ Calling SP, LR
- str lr, [r8, #0] @ Save calling PC
- mrs r6, spsr
- str r6, [r8, #4] @ Save CPSR
- str r0, [r8, #8] @ Save OLD_R0
- mov r0, sp
- .endm
-
- .macro irq_restore_user_regs
- ldmia sp, {r0 - lr}^ @ Calling r0 - lr
- mov r0, r0
- ldr lr, [sp, #S_PC] @ Get PC
- add sp, sp, #S_FRAME_SIZE
- subs pc, lr, #4 @ return & move spsr_svc into cpsr
- .endm
-
- .macro get_bad_stack
- ldr r13, IRQ_STACK_START_IN @ setup our mode stack
-
- str lr, [r13] @ save caller lr / spsr
- mrs lr, spsr
- str lr, [r13, #4]
-
- mov r13, #MODE_SVC @ prepare SVC-Mode
- msr spsr_c, r13
- mov lr, pc
- movs pc, lr
- .endm
-
- .macro get_irq_stack @ setup IRQ stack
- ldr sp, IRQ_STACK_START
- .endm
-
- .macro get_fiq_stack @ setup FIQ stack
- ldr sp, FIQ_STACK_START
- .endm
-
-/*
- * exception handlers
- */
- .align 5
-undefined_instruction:
- get_bad_stack
- bad_save_user_regs
- bl do_undefined_instruction
-
- .align 5
-software_interrupt:
- get_bad_stack
- bad_save_user_regs
- bl do_software_interrupt
-
- .align 5
-prefetch_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_prefetch_abort
-
- .align 5
-data_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_data_abort
-
- .align 5
-not_used:
- get_bad_stack
- bad_save_user_regs
- bl do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
- .align 5
-irq:
- get_irq_stack
- irq_save_user_regs
- bl do_irq
- irq_restore_user_regs
-
- .align 5
-fiq:
- get_fiq_stack
- /* someone ought to write a more effiction fiq_save_user_regs */
- irq_save_user_regs
- bl do_fiq
- irq_restore_user_regs
-
-#else
-
- .align 5
-irq:
- get_bad_stack
- bad_save_user_regs
- bl do_irq
-
- .align 5
-fiq:
- get_bad_stack
- bad_save_user_regs
- bl do_fiq
-
-#endif
-#endif /* CONFIG_SPL_BUILD */
{ .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
},
/*
- * T30: 1.4 GHz
+ * T30: 600 MHz
*
* Register Field Bits Width
* ------------------------------
* PLLX_MISC cpcon 11: 8 4
*/
{
- { .n = 862, .m = 8, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
- { .n = 583, .m = 8, .p = 0, .cpcon = 4 }, /* OSC: 19.2 MHz */
- { .n = 700, .m = 6, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
- { .n = 700, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
+ { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
+ { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
+ { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
+ { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
},
/*
* T114: 700 MHz
writel(config, ®->cnfg);
}
+#define TPS62366A_I2C_ADDR 0xC0
+#define TPS62366A_SET1_REG 0x01
+#define TPS62366A_SET1_DATA (0x4600 | TPS62366A_SET1_REG)
+
+#define TPS62361B_I2C_ADDR 0xC0
+#define TPS62361B_SET3_REG 0x03
+#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG)
+
#define TPS65911_I2C_ADDR 0x5A
#define TPS65911_VDDCTRL_OP_REG 0x28
#define TPS65911_VDDCTRL_SR_REG 0x27
-#define TPS65911_VDDCTRL_OP_DATA (0x2300 | TPS65911_VDDCTRL_OP_REG)
+#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG)
#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
#define I2C_SEND_2_BYTES 0x0A02
reg |= CPUPWRREQ_OE;
writel(reg, &pmc->pmc_cntrl);
+ /* Set VDD_CORE to 1.200V. */
+#ifdef CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
+ tegra_i2c_ll_write_addr(TPS62366A_I2C_ADDR, 2);
+ tegra_i2c_ll_write_data(TPS62366A_SET1_DATA, I2C_SEND_2_BYTES);
+#endif
+#ifdef CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
+ tegra_i2c_ll_write_addr(TPS62361B_I2C_ADDR, 2);
+ tegra_i2c_ll_write_data(TPS62361B_SET3_DATA, I2C_SEND_2_BYTES);
+#endif
+ udelay(1000);
+
/*
* Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
- * First set VDD to 1.4V, then enable the VDD regulator.
+ * First set VDD to 1.0125V, then enable the VDD regulator.
*/
tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2);
tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES);
.text :
{
*(.__image_copy_start)
- arch/arm/cpu/arm920t/start.o (.text*)
+ *(.vectors)
+ arch/arm/cpu/arm920t/start.o (.text*)
/* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
. = 0x1000;
LONG(0x53555243)
#include <common.h>
#include <config.h>
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-
-.globl _start
-_start: b start_code
- ldr pc, _undefined_instruction
- ldr pc, _software_interrupt
- ldr pc, _prefetch_abort
- ldr pc, _data_abort
- ldr pc, _not_used
- ldr pc, _irq
- ldr pc, _fiq
-
-_undefined_instruction: .word undefined_instruction
-_software_interrupt: .word software_interrupt
-_prefetch_abort: .word prefetch_abort
-_data_abort: .word data_abort
-_not_used: .word not_used
-_irq: .word irq
-_fiq: .word fiq
-
- .balignl 16,0xdeadbeef
-
-
/*
*************************************************************************
*
*************************************************************************
*/
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
- .word 0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
- .word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
- .word 0x0badc0de
+ .globl reset
-/*
- * the actual start code
- */
-
-start_code:
+reset:
/*
* set the cpu to SVC32 mode
*/
mov lr, ip
mov pc, lr
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE 72
-
-#define S_OLD_R0 68
-#define S_PSR 64
-#define S_PC 60
-#define S_LR 56
-#define S_SP 52
-
-#define S_IP 48
-#define S_FP 44
-#define S_R10 40
-#define S_R9 36
-#define S_R8 32
-#define S_R7 28
-#define S_R6 24
-#define S_R5 20
-#define S_R4 16
-#define S_R3 12
-#define S_R2 8
-#define S_R1 4
-#define S_R0 0
-
-#define MODE_SVC 0x13
-#define I_BIT 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
- .macro bad_save_user_regs
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} @ Calling r0-r12
- ldr r2, IRQ_STACK_START_IN
- ldmia r2, {r2 - r3} @ get pc, cpsr
- add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
-
- add r5, sp, #S_SP
- mov r1, lr
- stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
- mov r0, sp
- .endm
-
- .macro irq_save_user_regs
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} @ Calling r0-r12
- add r7, sp, #S_PC
- stmdb r7, {sp, lr}^ @ Calling SP, LR
- str lr, [r7, #0] @ Save calling PC
- mrs r6, spsr
- str r6, [r7, #4] @ Save CPSR
- str r0, [r7, #8] @ Save OLD_R0
- mov r0, sp
- .endm
-
- .macro irq_restore_user_regs
- ldmia sp, {r0 - lr}^ @ Calling r0 - lr
- mov r0, r0
- ldr lr, [sp, #S_PC] @ Get PC
- add sp, sp, #S_FRAME_SIZE
- /* return & move spsr_svc into cpsr */
- subs pc, lr, #4
- .endm
-
- .macro get_bad_stack
- ldr r13, IRQ_STACK_START_IN @ setup our mode stack
-
- str lr, [r13] @ save caller lr / spsr
- mrs lr, spsr
- str lr, [r13, #4]
-
- mov r13, #MODE_SVC @ prepare SVC-Mode
- @ msr spsr_c, r13
- msr spsr, r13
- mov lr, pc
- movs pc, lr
- .endm
-
- .macro get_irq_stack @ setup IRQ stack
- ldr sp, IRQ_STACK_START
- .endm
-
- .macro get_fiq_stack @ setup FIQ stack
- ldr sp, FIQ_STACK_START
- .endm
-
-/*
- * exception handlers
- */
- .align 5
-undefined_instruction:
- get_bad_stack
- bad_save_user_regs
- bl do_undefined_instruction
-
- .align 5
-software_interrupt:
- get_bad_stack
- bad_save_user_regs
- bl do_software_interrupt
-
- .align 5
-prefetch_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_prefetch_abort
-
- .align 5
-data_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_data_abort
-
- .align 5
-not_used:
- get_bad_stack
- bad_save_user_regs
- bl do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
- .align 5
-irq:
- get_irq_stack
- irq_save_user_regs
- bl do_irq
- irq_restore_user_regs
-
- .align 5
-fiq:
- get_fiq_stack
- /* someone ought to write a more effiction fiq_save_user_regs */
- irq_save_user_regs
- bl do_fiq
- irq_restore_user_regs
-
-#else
-
- .align 5
-irq:
- get_bad_stack
- bad_save_user_regs
- bl do_irq
-
- .align 5
-fiq:
- get_bad_stack
- bad_save_user_regs
- bl do_fiq
-
-#endif
#include <common.h>
#include <version.h>
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-
-.globl _start
-_start:
- b reset
- b undefined_instruction
- b software_interrupt
- b prefetch_abort
- b data_abort
- b not_used
- b irq
- b fiq
-
-/*
- * Vector table, located at address 0x20.
- * This table allows the code running AFTER SPL, the U-Boot, to install it's
- * interrupt handlers here. The problem is that the U-Boot is loaded into RAM,
- * including it's interrupt vectoring table and the table at 0x0 is still the
- * SPLs. So if interrupt happens in U-Boot, the SPLs interrupt vectoring table
- * is still used.
- */
-_vt_reset:
- .word _reset
-_vt_undefined_instruction:
- .word _hang
-_vt_software_interrupt:
- .word _hang
-_vt_prefetch_abort:
- .word _hang
-_vt_data_abort:
- .word _hang
-_vt_not_used:
- .word _reset
-_vt_irq:
- .word _hang
-_vt_fiq:
- .word _hang
-
-reset:
- ldr pc, _vt_reset
-undefined_instruction:
- ldr pc, _vt_undefined_instruction
-software_interrupt:
- ldr pc, _vt_software_interrupt
-prefetch_abort:
- ldr pc, _vt_prefetch_abort
-data_abort:
- ldr pc, _vt_data_abort
-not_used:
- ldr pc, _vt_not_used
-irq:
- ldr pc, _vt_irq
-fiq:
- ldr pc, _vt_fiq
-
- .balignl 16,0xdeadbeef
-
/*
*************************************************************************
*
*************************************************************************
*/
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
- .word 0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
- .word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
- .word 0x0badc0de
-
-/*
- * the actual reset code
- */
-
-_reset:
+ .globl reset
+reset:
/*
* If the CPU is configured in "Wait JTAG connection mode", the stack
* pointer is not configured and is zero. This will cause crash when
mov r0, #0
bx lr
-
-_hang:
-1:
- bl 1b /* hang and never return */
#include <config.h>
-.globl _start
-_start:
- b reset
- ldr pc, _undefined_instruction
- ldr pc, _software_interrupt
- ldr pc, _prefetch_abort
- ldr pc, _data_abort
- ldr pc, _not_used
- ldr pc, _irq
- ldr pc, _fiq
-
-_undefined_instruction:
-_software_interrupt:
-_prefetch_abort:
-_data_abort:
-_not_used:
-_irq:
-_fiq:
- .word infinite_loop
-
-infinite_loop:
- b infinite_loop
-
/*
*************************************************************************
*
*************************************************************************
*/
-/*
- * the actual reset code
- */
+ .globl reset
reset:
/*
. = ALIGN(4);
.text :
{
+ *(.vectors)
arch/arm/cpu/arm926ejs/spear/start.o (.text*)
*(.text*)
}
#include <common.h>
#include <version.h>
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-
-#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
-.globl _start
-_start:
-.globl _NOR_BOOT_CFG
-_NOR_BOOT_CFG:
- .word CONFIG_SYS_DV_NOR_BOOT_CFG
- b reset
-#else
-.globl _start
-_start:
- b reset
-#endif
-#ifdef CONFIG_SPL_BUILD
-/* No exception handlers in preloader */
- ldr pc, _hang
- ldr pc, _hang
- ldr pc, _hang
- ldr pc, _hang
- ldr pc, _hang
- ldr pc, _hang
- ldr pc, _hang
-
-_hang:
- .word do_hang
-/* pad to 64 byte boundary */
- .word 0x12345678
- .word 0x12345678
- .word 0x12345678
- .word 0x12345678
- .word 0x12345678
- .word 0x12345678
- .word 0x12345678
-#else
- ldr pc, _undefined_instruction
- ldr pc, _software_interrupt
- ldr pc, _prefetch_abort
- ldr pc, _data_abort
- ldr pc, _not_used
- ldr pc, _irq
- ldr pc, _fiq
-
-_undefined_instruction:
- .word undefined_instruction
-_software_interrupt:
- .word software_interrupt
-_prefetch_abort:
- .word prefetch_abort
-_data_abort:
- .word data_abort
-_not_used:
- .word not_used
-_irq:
- .word irq
-_fiq:
- .word fiq
-
-#endif /* CONFIG_SPL_BUILD */
- .balignl 16,0xdeadbeef
-
-
/*
*************************************************************************
*
*************************************************************************
*/
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
- .word 0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
- .word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
- .word 0x0badc0de
-
-/*
- * the actual reset code
- */
+ .globl reset
reset:
/*
mov lr, ip /* restore link */
mov pc, lr /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-#ifndef CONFIG_SPL_BUILD
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE 72
-
-#define S_OLD_R0 68
-#define S_PSR 64
-#define S_PC 60
-#define S_LR 56
-#define S_SP 52
-
-#define S_IP 48
-#define S_FP 44
-#define S_R10 40
-#define S_R9 36
-#define S_R8 32
-#define S_R7 28
-#define S_R6 24
-#define S_R5 20
-#define S_R4 16
-#define S_R3 12
-#define S_R2 8
-#define S_R1 4
-#define S_R0 0
-
-#define MODE_SVC 0x13
-#define I_BIT 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
- .macro bad_save_user_regs
- @ carve out a frame on current user stack
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
- ldr r2, IRQ_STACK_START_IN
- @ get values for "aborted" pc and cpsr (into parm regs)
- ldmia r2, {r2 - r3}
- add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
- add r5, sp, #S_SP
- mov r1, lr
- stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
- mov r0, sp @ save current stack into r0 (param register)
- .endm
-
- .macro irq_save_user_regs
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} @ Calling r0-r12
- @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
- add r8, sp, #S_PC
- stmdb r8, {sp, lr}^ @ Calling SP, LR
- str lr, [r8, #0] @ Save calling PC
- mrs r6, spsr
- str r6, [r8, #4] @ Save CPSR
- str r0, [r8, #8] @ Save OLD_R0
- mov r0, sp
- .endm
-
- .macro irq_restore_user_regs
- ldmia sp, {r0 - lr}^ @ Calling r0 - lr
- mov r0, r0
- ldr lr, [sp, #S_PC] @ Get PC
- add sp, sp, #S_FRAME_SIZE
- subs pc, lr, #4 @ return & move spsr_svc into cpsr
- .endm
-
- .macro get_bad_stack
- ldr r13, IRQ_STACK_START_IN @ setup our mode stack
-
- str lr, [r13] @ save caller lr in position 0 of saved stack
- mrs lr, spsr @ get the spsr
- str lr, [r13, #4] @ save spsr in position 1 of saved stack
- mov r13, #MODE_SVC @ prepare SVC-Mode
- @ msr spsr_c, r13
- msr spsr, r13 @ switch modes, make sure moves will execute
- mov lr, pc @ capture return pc
- movs pc, lr @ jump to next instruction & switch modes.
- .endm
-
- .macro get_irq_stack @ setup IRQ stack
- ldr sp, IRQ_STACK_START
- .endm
-
- .macro get_fiq_stack @ setup FIQ stack
- ldr sp, FIQ_STACK_START
- .endm
-#endif /* CONFIG_SPL_BUILD */
-
-/*
- * exception handlers
- */
-#ifdef CONFIG_SPL_BUILD
- .align 5
-do_hang:
-1:
- bl 1b /* hang and never return */
-#else /* !CONFIG_SPL_BUILD */
- .align 5
-undefined_instruction:
- get_bad_stack
- bad_save_user_regs
- bl do_undefined_instruction
-
- .align 5
-software_interrupt:
- get_bad_stack
- bad_save_user_regs
- bl do_software_interrupt
-
- .align 5
-prefetch_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_prefetch_abort
-
- .align 5
-data_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_data_abort
-
- .align 5
-not_used:
- get_bad_stack
- bad_save_user_regs
- bl do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
- .align 5
-irq:
- get_irq_stack
- irq_save_user_regs
- bl do_irq
- irq_restore_user_regs
-
- .align 5
-fiq:
- get_fiq_stack
- /* someone ought to write a more effiction fiq_save_user_regs */
- irq_save_user_regs
- bl do_fiq
- irq_restore_user_regs
-
-#else
-
- .align 5
-irq:
- get_bad_stack
- bad_save_user_regs
- bl do_irq
-
- .align 5
-fiq:
- get_bad_stack
- bad_save_user_regs
- bl do_fiq
-
-#endif
-#endif /* CONFIG_SPL_BUILD */
#include <common.h>
#include <command.h>
#include <asm/system.h>
+#include <asm/io.h>
static void cache_flush(void);
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i));
}
+
+#ifndef CONFIG_INTEGRATOR
+
+__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused)))
+{
+ writew(0x0, 0xfffece10);
+ writew(0x8, 0xfffece10);
+ for (;;)
+ ;
+}
+
+#endif /* #ifdef CONFIG_INTEGRATOR */
#include <config.h>
#include <version.h>
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-
-.globl _start
-_start:
- b reset
- ldr pc, _undefined_instruction
- ldr pc, _software_interrupt
- ldr pc, _prefetch_abort
- ldr pc, _data_abort
- ldr pc, _not_used
- ldr pc, _irq
- ldr pc, _fiq
-
-_undefined_instruction:
- .word undefined_instruction
-_software_interrupt:
- .word software_interrupt
-_prefetch_abort:
- .word prefetch_abort
-_data_abort:
- .word data_abort
-_not_used:
- .word not_used
-_irq:
- .word irq
-_fiq:
- .word fiq
-
- .balignl 16,0xdeadbeef
-
-_vectors_end:
-
/*
*************************************************************************
*
*************************************************************************
*/
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
- .word 0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
- .word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
- .word 0x0badc0de
-
-/*
- * the actual reset code
- */
+ .globl reset
reset:
/*
mov lr, ip /* restore link */
mov pc, lr /* back to my caller */
#endif
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE 72
-
-#define S_OLD_R0 68
-#define S_PSR 64
-#define S_PC 60
-#define S_LR 56
-#define S_SP 52
-
-#define S_IP 48
-#define S_FP 44
-#define S_R10 40
-#define S_R9 36
-#define S_R8 32
-#define S_R7 28
-#define S_R6 24
-#define S_R5 20
-#define S_R4 16
-#define S_R3 12
-#define S_R2 8
-#define S_R1 4
-#define S_R0 0
-
-#define MODE_SVC 0x13
-#define I_BIT 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
- .macro bad_save_user_regs
- @ carve out a frame on current user stack
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
-
- ldr r2, IRQ_STACK_START_IN
- @ get values for "aborted" pc and cpsr (into parm regs)
- ldmia r2, {r2 - r3}
- add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
- add r5, sp, #S_SP
- mov r1, lr
- stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
- mov r0, sp @ save current stack into r0 (param register)
- .endm
-
- .macro irq_save_user_regs
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} @ Calling r0-r12
- @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
- add r8, sp, #S_PC
- stmdb r8, {sp, lr}^ @ Calling SP, LR
- str lr, [r8, #0] @ Save calling PC
- mrs r6, spsr
- str r6, [r8, #4] @ Save CPSR
- str r0, [r8, #8] @ Save OLD_R0
- mov r0, sp
- .endm
-
- .macro irq_restore_user_regs
- ldmia sp, {r0 - lr}^ @ Calling r0 - lr
- mov r0, r0
- ldr lr, [sp, #S_PC] @ Get PC
- add sp, sp, #S_FRAME_SIZE
- subs pc, lr, #4 @ return & move spsr_svc into cpsr
- .endm
-
- .macro get_bad_stack
- ldr r13, IRQ_STACK_START_IN @ setup our mode stack
-
- str lr, [r13] @ save caller lr in position 0 of saved stack
- mrs lr, spsr @ get the spsr
- str lr, [r13, #4] @ save spsr in position 1 of saved stack
- mov r13, #MODE_SVC @ prepare SVC-Mode
- @ msr spsr_c, r13
- msr spsr, r13 @ switch modes, make sure moves will execute
- mov lr, pc @ capture return pc
- movs pc, lr @ jump to next instruction & switch modes.
- .endm
-
- .macro get_irq_stack @ setup IRQ stack
- ldr sp, IRQ_STACK_START
- .endm
-
- .macro get_fiq_stack @ setup FIQ stack
- ldr sp, FIQ_STACK_START
- .endm
-
-/*
- * exception handlers
- */
- .align 5
-undefined_instruction:
- get_bad_stack
- bad_save_user_regs
- bl do_undefined_instruction
-
- .align 5
-software_interrupt:
- get_bad_stack
- bad_save_user_regs
- bl do_software_interrupt
-
- .align 5
-prefetch_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_prefetch_abort
-
- .align 5
-data_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_data_abort
-
- .align 5
-not_used:
- get_bad_stack
- bad_save_user_regs
- bl do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
- .align 5
-irq:
- get_irq_stack
- irq_save_user_regs
- bl do_irq
- irq_restore_user_regs
-
- .align 5
-fiq:
- get_fiq_stack
- /* someone ought to write a more effiction fiq_save_user_regs */
- irq_save_user_regs
- bl do_fiq
- irq_restore_user_regs
-
-#else
-
- .align 5
-irq:
- get_bad_stack
- bad_save_user_regs
- bl do_irq
-
- .align 5
-fiq:
- get_bad_stack
- bad_save_user_regs
- bl do_fiq
-
-#endif
-
-# ifdef CONFIG_INTEGRATOR
-
- /* Satisfied by general board level routine */
-
-#else
-
- .align 5
-.globl reset_cpu
-reset_cpu:
-
- ldr r1, rstctl1 /* get clkm1 reset ctl */
- mov r3, #0x0
- strh r3, [r1] /* clear it */
- mov r3, #0x8
- strh r3, [r1] /* force dsp+arm reset */
-_loop_forever:
- b _loop_forever
-
-rstctl1:
- .word 0xfffece10
-
-#endif /* #ifdef CONFIG_INTEGRATOR */
#include <config.h>
#include <version.h>
-/*
- *************************************************************************
- *
- * Jump vector table
- *
- *************************************************************************
- */
-
-.globl _start
-_start:
- b reset
- ldr pc, _undefined_instruction
- ldr pc, _software_interrupt
- ldr pc, _prefetch_abort
- ldr pc, _data_abort
- ldr pc, _not_used
- ldr pc, _irq
- ldr pc, _fiq
-
-_undefined_instruction:
- .word undefined_instruction
-_software_interrupt:
- .word software_interrupt
-_prefetch_abort:
- .word prefetch_abort
-_data_abort:
- .word data_abort
-_not_used:
- .word not_used
-_irq:
- .word irq
-_fiq:
- .word fiq
-
- .balignl 16,0xdeadbeef
-
/*
*************************************************************************
*
*************************************************************************
*/
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
- .word 0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
- .word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
- .word 0x0badc0de
-
-/*
- * the actual reset code
- */
+ .globl reset
reset:
/*
*/
mov pc, lr /* back to my caller */
#endif
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE 72
-
-#define S_OLD_R0 68
-#define S_PSR 64
-#define S_PC 60
-#define S_LR 56
-#define S_SP 52
-
-#define S_IP 48
-#define S_FP 44
-#define S_R10 40
-#define S_R9 36
-#define S_R8 32
-#define S_R7 28
-#define S_R6 24
-#define S_R5 20
-#define S_R4 16
-#define S_R3 12
-#define S_R2 8
-#define S_R1 4
-#define S_R0 0
-
-#define MODE_SVC 0x13
-#define I_BIT 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
- .macro bad_save_user_regs
- @ carve out a frame on current user stack
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
-
- ldr r2, IRQ_STACK_START_IN
- @ get values for "aborted" pc and cpsr (into parm regs)
- ldmia r2, {r2 - r3}
- add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
- add r5, sp, #S_SP
- mov r1, lr
- stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
- mov r0, sp @ save current stack into r0 (param register)
- .endm
-
- .macro irq_save_user_regs
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} @ Calling r0-r12
- @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
- add r8, sp, #S_PC
- stmdb r8, {sp, lr}^ @ Calling SP, LR
- str lr, [r8, #0] @ Save calling PC
- mrs r6, spsr
- str r6, [r8, #4] @ Save CPSR
- str r0, [r8, #8] @ Save OLD_R0
- mov r0, sp
- .endm
-
- .macro irq_restore_user_regs
- ldmia sp, {r0 - lr}^ @ Calling r0 - lr
- mov r0, r0
- ldr lr, [sp, #S_PC] @ Get PC
- add sp, sp, #S_FRAME_SIZE
- subs pc, lr, #4 @ return & move spsr_svc into cpsr
- .endm
-
- .macro get_bad_stack
- ldr r13, IRQ_STACK_START_IN @ setup our mode stack
-
- str lr, [r13] @ save caller lr in position 0 of saved stack
- mrs lr, spsr @ get the spsr
- str lr, [r13, #4] @ save spsr in position 1 of saved stack
- mov r13, #MODE_SVC @ prepare SVC-Mode
- @ msr spsr_c, r13
- msr spsr, r13 @ switch modes, make sure moves will execute
- mov lr, pc @ capture return pc
- movs pc, lr @ jump to next instruction & switch modes.
- .endm
-
- .macro get_irq_stack @ setup IRQ stack
- ldr sp, IRQ_STACK_START
- .endm
-
- .macro get_fiq_stack @ setup FIQ stack
- ldr sp, FIQ_STACK_START
- .endm
-
-/*
- * exception handlers
- */
- .align 5
-.globl undefined_instruction
-undefined_instruction:
- get_bad_stack
- bad_save_user_regs
- bl do_undefined_instruction
-
- .align 5
-.globl software_interrupt
-software_interrupt:
- get_bad_stack
- bad_save_user_regs
- bl do_software_interrupt
-
- .align 5
-.globl prefetch_abort
-prefetch_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_prefetch_abort
-
- .align 5
-.globl data_abort
-data_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_data_abort
-
- .align 5
-.globl not_used
-not_used:
- get_bad_stack
- bad_save_user_regs
- bl do_not_used
-
-#ifdef CONFIG_USE_IRQ
- .align 5
-.globl irq
-irq:
- get_irq_stack
- irq_save_user_regs
- bl do_irq
- irq_restore_user_regs
-
- .align 5
-.globl fiq
-fiq:
- get_fiq_stack
- /* someone ought to write a more effiction fiq_save_user_regs */
- irq_save_user_regs
- bl do_fiq
- irq_restore_user_regs
-
-#else
-
- .align 5
-.globl irq
-irq:
- get_bad_stack
- bad_save_user_regs
- bl do_irq
-
- .align 5
-.globl fiq
-fiq:
- get_bad_stack
- bad_save_user_regs
- bl do_fiq
-
-#endif
static void exynos5_uart_config(int peripheral)
{
- struct exynos5_gpio_part1 *gpio1 =
- (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
- struct s5p_gpio_bank *bank;
int i, start, count;
switch (peripheral) {
case PERIPH_ID_UART0:
- bank = &gpio1->a0;
- start = 0;
+ start = EXYNOS5_GPIO_A00;
count = 4;
break;
case PERIPH_ID_UART1:
- bank = &gpio1->d0;
- start = 0;
+ start = EXYNOS5_GPIO_D00;
count = 4;
break;
case PERIPH_ID_UART2:
- bank = &gpio1->a1;
- start = 0;
+ start = EXYNOS5_GPIO_A10;
count = 4;
break;
case PERIPH_ID_UART3:
- bank = &gpio1->a1;
- start = 4;
+ start = EXYNOS5_GPIO_A14;
count = 2;
break;
default:
return;
}
for (i = start; i < start + count; i++) {
- s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
- s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
}
}
static void exynos5420_uart_config(int peripheral)
{
- struct exynos5420_gpio_part1 *gpio1 =
- (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
- struct s5p_gpio_bank *bank;
int i, start, count;
switch (peripheral) {
case PERIPH_ID_UART0:
- bank = &gpio1->a0;
- start = 0;
+ start = EXYNOS5420_GPIO_A00;
count = 4;
break;
case PERIPH_ID_UART1:
- bank = &gpio1->a0;
- start = 4;
+ start = EXYNOS5420_GPIO_A04;
count = 4;
break;
case PERIPH_ID_UART2:
- bank = &gpio1->a1;
- start = 0;
+ start = EXYNOS5420_GPIO_A10;
count = 4;
break;
case PERIPH_ID_UART3:
- bank = &gpio1->a1;
- start = 4;
+ start = EXYNOS5420_GPIO_A14;
count = 2;
break;
default:
}
for (i = start; i < start + count; i++) {
- s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
- s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
}
}
static int exynos5_mmc_config(int peripheral, int flags)
{
- struct exynos5_gpio_part1 *gpio1 =
- (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
- struct s5p_gpio_bank *bank, *bank_ext;
- int i, start = 0, gpio_func = 0;
+ int i, start, start_ext, gpio_func = 0;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
- bank = &gpio1->c0;
- bank_ext = &gpio1->c1;
- start = 0;
- gpio_func = GPIO_FUNC(0x2);
+ start = EXYNOS5_GPIO_C00;
+ start_ext = EXYNOS5_GPIO_C10;
+ gpio_func = S5P_GPIO_FUNC(0x2);
break;
case PERIPH_ID_SDMMC1:
- bank = &gpio1->c2;
- bank_ext = NULL;
+ start = EXYNOS5_GPIO_C20;
+ start_ext = 0;
break;
case PERIPH_ID_SDMMC2:
- bank = &gpio1->c3;
- bank_ext = &gpio1->c4;
- start = 3;
- gpio_func = GPIO_FUNC(0x3);
+ start = EXYNOS5_GPIO_C30;
+ start_ext = EXYNOS5_GPIO_C43;
+ gpio_func = S5P_GPIO_FUNC(0x3);
break;
case PERIPH_ID_SDMMC3:
- bank = &gpio1->c4;
- bank_ext = NULL;
+ start = EXYNOS5_GPIO_C40;
+ start_ext = 0;
break;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
}
- if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
+ if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
debug("SDMMC device %d does not support 8bit mode",
peripheral);
return -1;
}
if (flags & PINMUX_FLAG_8BIT_MODE) {
- for (i = start; i <= (start + 3); i++) {
- s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
- s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
- s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+ for (i = start_ext; i <= (start_ext + 3); i++) {
+ gpio_cfg_pin(i, gpio_func);
+ gpio_set_pull(i, S5P_GPIO_PULL_UP);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
}
- for (i = 0; i < 2; i++) {
- s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
- s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
- s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+ for (i = start; i < (start + 2); i++) {
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
- for (i = 3; i <= 6; i++) {
- s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
- s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
- s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+ for (i = (start + 3); i <= (start + 6); i++) {
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+ gpio_set_pull(i, S5P_GPIO_PULL_UP);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
return 0;
static int exynos5420_mmc_config(int peripheral, int flags)
{
- struct exynos5420_gpio_part3 *gpio3 =
- (struct exynos5420_gpio_part3 *)samsung_get_base_gpio_part3();
- struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL;
- int i, start;
+ int i, start = 0, start_ext = 0;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
- bank = &gpio3->c0;
- bank_ext = &gpio3->c3;
- start = 0;
+ start = EXYNOS5420_GPIO_C00;
+ start_ext = EXYNOS5420_GPIO_C30;
break;
case PERIPH_ID_SDMMC1:
- bank = &gpio3->c1;
- bank_ext = &gpio3->d1;
- start = 4;
+ start = EXYNOS5420_GPIO_C10;
+ start_ext = EXYNOS5420_GPIO_D14;
break;
case PERIPH_ID_SDMMC2:
- bank = &gpio3->c2;
- bank_ext = NULL;
- start = 0;
+ start = EXYNOS5420_GPIO_C20;
+ start_ext = 0;
break;
default:
start = 0;
return -1;
}
- if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
+ if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
debug("SDMMC device %d does not support 8bit mode",
peripheral);
return -1;
}
if (flags & PINMUX_FLAG_8BIT_MODE) {
- for (i = start; i <= (start + 3); i++) {
- s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x2));
- s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
- s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+ for (i = start_ext; i <= (start_ext + 3); i++) {
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+ gpio_set_pull(i, S5P_GPIO_PULL_UP);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
}
- for (i = 0; i < 3; i++) {
+ for (i = start; i < (start + 3); i++) {
/*
* MMC0 is intended to be used for eMMC. The
* card detect pin is used as a VDDEN signal to
* power on the eMMC. The 5420 iROM makes
* this same assumption.
*/
- if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) {
- s5p_gpio_set_value(bank, i, 1);
- s5p_gpio_cfg_pin(bank, i, GPIO_OUTPUT);
+ if ((peripheral == PERIPH_ID_SDMMC0) && (i == (start + 2))) {
+ gpio_set_value(i, 1);
+ gpio_cfg_pin(i, S5P_GPIO_OUTPUT);
} else {
- s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
}
- s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
- s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
- for (i = 3; i <= 6; i++) {
- s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
- s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
- s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+ for (i = (start + 3); i <= (start + 6); i++) {
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+ gpio_set_pull(i, S5P_GPIO_PULL_UP);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
return 0;
static void exynos5_sromc_config(int flags)
{
- struct exynos5_gpio_part1 *gpio1 =
- (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
int i;
/*
* GPY1[2] SROM_WAIT(2)
* GPY1[3] EBI_DATA_RDn(2)
*/
- s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK),
- GPIO_FUNC(2));
- s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2));
- s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2));
+ gpio_cfg_pin(EXYNOS5_GPIO_Y00 + (flags & PINMUX_FLAG_BANK),
+ S5P_GPIO_FUNC(2));
+ gpio_cfg_pin(EXYNOS5_GPIO_Y04, S5P_GPIO_FUNC(2));
+ gpio_cfg_pin(EXYNOS5_GPIO_Y05, S5P_GPIO_FUNC(2));
for (i = 0; i < 4; i++)
- s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2));
+ gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, S5P_GPIO_FUNC(2));
/*
* EBI: 8 Addrss Lines
* GPY6[7] EBI_DATA[15](2)
*/
for (i = 0; i < 8; i++) {
- s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2));
- s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP);
+ gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_FUNC(2));
+ gpio_set_pull(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_PULL_UP);
- s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2));
- s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP);
+ gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_FUNC(2));
+ gpio_set_pull(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_PULL_UP);
- s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2));
- s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP);
+ gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_FUNC(2));
+ gpio_set_pull(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_PULL_UP);
}
}
static void exynos5_i2c_config(int peripheral, int flags)
{
-
- struct exynos5_gpio_part1 *gpio1 =
- (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
-
switch (peripheral) {
case PERIPH_ID_I2C0:
- s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
- s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C1:
- s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
- s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C2:
- s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C3:
- s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C4:
- s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A21, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C5:
- s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A22, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A23, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C6:
- s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
- s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5_GPIO_B13, S5P_GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5_GPIO_B14, S5P_GPIO_FUNC(0x4));
break;
case PERIPH_ID_I2C7:
- s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_B22, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_B23, S5P_GPIO_FUNC(0x3));
break;
}
}
static void exynos5420_i2c_config(int peripheral)
{
- struct exynos5420_gpio_part1 *gpio1 =
- (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
-
switch (peripheral) {
case PERIPH_ID_I2C0:
- s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
- s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B30, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B31, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C1:
- s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
- s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B32, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B33, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C2:
- s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A06, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A07, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C3:
- s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A12, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A13, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C4:
- s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A20, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A21, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C5:
- s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A22, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A23, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C6:
- s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
- s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B13, S5P_GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B14, S5P_GPIO_FUNC(0x4));
break;
case PERIPH_ID_I2C7:
- s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B22, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B23, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C8:
- s5p_gpio_cfg_pin(&gpio1->b3, 4, GPIO_FUNC(0x2));
- s5p_gpio_cfg_pin(&gpio1->b3, 5, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B34, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B35, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C9:
- s5p_gpio_cfg_pin(&gpio1->b3, 6, GPIO_FUNC(0x2));
- s5p_gpio_cfg_pin(&gpio1->b3, 7, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B36, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B37, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C10:
- s5p_gpio_cfg_pin(&gpio1->b4, 0, GPIO_FUNC(0x2));
- s5p_gpio_cfg_pin(&gpio1->b4, 1, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B40, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B41, S5P_GPIO_FUNC(0x2));
break;
}
}
static void exynos5_i2s_config(int peripheral)
{
int i;
- struct exynos5_gpio_part1 *gpio1 =
- (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
- struct exynos5_gpio_part4 *gpio4 =
- (struct exynos5_gpio_part4 *)samsung_get_base_gpio_part4();
switch (peripheral) {
case PERIPH_ID_I2S0:
for (i = 0; i < 5; i++)
- s5p_gpio_cfg_pin(&gpio4->z, i, GPIO_FUNC(0x02));
+ gpio_cfg_pin(EXYNOS5_GPIO_Z0 + i, S5P_GPIO_FUNC(0x02));
break;
case PERIPH_ID_I2S1:
for (i = 0; i < 5; i++)
- s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
+ gpio_cfg_pin(EXYNOS5_GPIO_B00 + i, S5P_GPIO_FUNC(0x02));
break;
}
}
void exynos5_spi_config(int peripheral)
{
int cfg = 0, pin = 0, i;
- struct s5p_gpio_bank *bank = NULL;
- struct exynos5_gpio_part1 *gpio1 =
- (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
- struct exynos5_gpio_part2 *gpio2 =
- (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2();
switch (peripheral) {
case PERIPH_ID_SPI0:
- bank = &gpio1->a2;
- cfg = GPIO_FUNC(0x2);
- pin = 0;
+ cfg = S5P_GPIO_FUNC(0x2);
+ pin = EXYNOS5_GPIO_A20;
break;
case PERIPH_ID_SPI1:
- bank = &gpio1->a2;
- cfg = GPIO_FUNC(0x2);
- pin = 4;
+ cfg = S5P_GPIO_FUNC(0x2);
+ pin = EXYNOS5_GPIO_A24;
break;
case PERIPH_ID_SPI2:
- bank = &gpio1->b1;
- cfg = GPIO_FUNC(0x5);
- pin = 1;
+ cfg = S5P_GPIO_FUNC(0x5);
+ pin = EXYNOS5_GPIO_B11;
break;
case PERIPH_ID_SPI3:
- bank = &gpio2->f1;
- cfg = GPIO_FUNC(0x2);
- pin = 0;
+ cfg = S5P_GPIO_FUNC(0x2);
+ pin = EXYNOS5_GPIO_F10;
break;
case PERIPH_ID_SPI4:
for (i = 0; i < 2; i++) {
- s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4));
- s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, S5P_GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, S5P_GPIO_FUNC(0x4));
}
break;
}
if (peripheral != PERIPH_ID_SPI4) {
for (i = pin; i < pin + 4; i++)
- s5p_gpio_cfg_pin(bank, i, cfg);
+ gpio_cfg_pin(i, cfg);
}
}
void exynos5420_spi_config(int peripheral)
{
int cfg, pin, i;
- struct s5p_gpio_bank *bank = NULL;
- struct exynos5420_gpio_part1 *gpio1 =
- (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
- struct exynos5420_gpio_part4 *gpio4 =
- (struct exynos5420_gpio_part4 *)samsung_get_base_gpio_part4();
switch (peripheral) {
case PERIPH_ID_SPI0:
- bank = &gpio1->a2;
- cfg = GPIO_FUNC(0x2);
- pin = 0;
+ pin = EXYNOS5420_GPIO_A20;
+ cfg = S5P_GPIO_FUNC(0x2);
break;
case PERIPH_ID_SPI1:
- bank = &gpio1->a2;
- cfg = GPIO_FUNC(0x2);
- pin = 4;
+ pin = EXYNOS5420_GPIO_A24;
+ cfg = S5P_GPIO_FUNC(0x2);
break;
case PERIPH_ID_SPI2:
- bank = &gpio1->b1;
- cfg = GPIO_FUNC(0x5);
- pin = 1;
+ pin = EXYNOS5420_GPIO_B11;
+ cfg = S5P_GPIO_FUNC(0x5);
break;
case PERIPH_ID_SPI3:
- bank = &gpio4->f1;
- cfg = GPIO_FUNC(0x2);
- pin = 0;
+ pin = EXYNOS5420_GPIO_F10;
+ cfg = S5P_GPIO_FUNC(0x2);
break;
case PERIPH_ID_SPI4:
cfg = 0;
if (peripheral != PERIPH_ID_SPI4) {
for (i = pin; i < pin + 4; i++)
- s5p_gpio_cfg_pin(bank, i, cfg);
+ gpio_cfg_pin(i, cfg);
} else {
for (i = 0; i < 2; i++) {
- s5p_gpio_cfg_pin(&gpio4->f0, i + 2, GPIO_FUNC(0x4));
- s5p_gpio_cfg_pin(&gpio4->e0, i + 4, GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5420_GPIO_F02 + i,
+ S5P_GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5420_GPIO_E04 + i,
+ S5P_GPIO_FUNC(0x4));
}
}
}
static void exynos4_i2c_config(int peripheral, int flags)
{
- struct exynos4_gpio_part1 *gpio1 =
- (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
-
switch (peripheral) {
case PERIPH_ID_I2C0:
- s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2));
- s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS4_GPIO_D10, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS4_GPIO_D11, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C1:
- s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2));
- s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS4_GPIO_D12, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS4_GPIO_D13, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C2:
- s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS4_GPIO_A06, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS4_GPIO_A07, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C3:
- s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS4_GPIO_A12, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS4_GPIO_A13, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C4:
- s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS4_GPIO_B2, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS4_GPIO_B3, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C5:
- s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS4_GPIO_B6, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS4_GPIO_B7, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C6:
- s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4));
- s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS4_GPIO_C13, S5P_GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS4_GPIO_C14, S5P_GPIO_FUNC(0x4));
break;
case PERIPH_ID_I2C7:
- s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS4_GPIO_D02, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS4_GPIO_D03, S5P_GPIO_FUNC(0x3));
break;
}
}
static int exynos4_mmc_config(int peripheral, int flags)
{
- struct exynos4_gpio_part2 *gpio2 =
- (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
- struct s5p_gpio_bank *bank, *bank_ext;
- int i;
+ int i, start = 0, start_ext = 0;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
- bank = &gpio2->k0;
- bank_ext = &gpio2->k1;
+ start = EXYNOS4_GPIO_K00;
+ start_ext = EXYNOS4_GPIO_K13;
break;
case PERIPH_ID_SDMMC2:
- bank = &gpio2->k2;
- bank_ext = &gpio2->k3;
+ start = EXYNOS4_GPIO_K20;
+ start_ext = EXYNOS4_GPIO_K33;
break;
default:
return -1;
}
- for (i = 0; i < 7; i++) {
- if (i == 2)
+ for (i = start; i < (start + 7); i++) {
+ if (i == (start + 2))
continue;
- s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
- s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
- s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
if (flags & PINMUX_FLAG_8BIT_MODE) {
- for (i = 3; i < 7; i++) {
- s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
- s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE);
- s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+ for (i = start_ext; i < (start_ext + 4); i++) {
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x3));
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
}
static void exynos4_uart_config(int peripheral)
{
- struct exynos4_gpio_part1 *gpio1 =
- (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
- struct s5p_gpio_bank *bank;
int i, start, count;
switch (peripheral) {
case PERIPH_ID_UART0:
- bank = &gpio1->a0;
- start = 0;
+ start = EXYNOS4_GPIO_A00;
count = 4;
break;
case PERIPH_ID_UART1:
- bank = &gpio1->a0;
- start = 4;
+ start = EXYNOS4_GPIO_A04;
count = 4;
break;
case PERIPH_ID_UART2:
- bank = &gpio1->a1;
- start = 0;
+ start = EXYNOS4_GPIO_A10;
count = 4;
break;
case PERIPH_ID_UART3:
- bank = &gpio1->a1;
- start = 4;
+ start = EXYNOS4_GPIO_A14;
count = 2;
break;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return;
}
- for (i = start; i < start + count; i++) {
- s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
- s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ for (i = start; i < (start + count); i++) {
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+ }
+}
+
+static void exynos4x12_i2c_config(int peripheral, int flags)
+{
+ switch (peripheral) {
+ case PERIPH_ID_I2C0:
+ gpio_cfg_pin(EXYNOS4X12_GPIO_D10, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS4X12_GPIO_D11, S5P_GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C1:
+ gpio_cfg_pin(EXYNOS4X12_GPIO_D12, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS4X12_GPIO_D13, S5P_GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C2:
+ gpio_cfg_pin(EXYNOS4X12_GPIO_A06, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS4X12_GPIO_A07, S5P_GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C3:
+ gpio_cfg_pin(EXYNOS4X12_GPIO_A12, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS4X12_GPIO_A13, S5P_GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C4:
+ gpio_cfg_pin(EXYNOS4X12_GPIO_B2, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS4X12_GPIO_B3, S5P_GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C5:
+ gpio_cfg_pin(EXYNOS4X12_GPIO_B6, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS4X12_GPIO_B7, S5P_GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C6:
+ gpio_cfg_pin(EXYNOS4X12_GPIO_C13, S5P_GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS4X12_GPIO_C14, S5P_GPIO_FUNC(0x4));
+ break;
+ case PERIPH_ID_I2C7:
+ gpio_cfg_pin(EXYNOS4X12_GPIO_D02, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS4X12_GPIO_D03, S5P_GPIO_FUNC(0x3));
+ break;
+ }
+}
+
+static int exynos4x12_mmc_config(int peripheral, int flags)
+{
+ int i, start = 0, start_ext = 0;
+
+ switch (peripheral) {
+ case PERIPH_ID_SDMMC0:
+ start = EXYNOS4X12_GPIO_K00;
+ start_ext = EXYNOS4X12_GPIO_K13;
+ break;
+ case PERIPH_ID_SDMMC2:
+ start = EXYNOS4X12_GPIO_K20;
+ start_ext = EXYNOS4X12_GPIO_K33;
+ break;
+ default:
+ return -1;
}
+ for (i = start; i < (start + 7); i++) {
+ if (i == (start + 2))
+ continue;
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
+ }
+ if (flags & PINMUX_FLAG_8BIT_MODE) {
+ for (i = start_ext; i < (start_ext + 4); i++) {
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x3));
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
+ }
+ }
+
+ return 0;
}
+
+static void exynos4x12_uart_config(int peripheral)
+{
+ int i, start, count;
+
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ start = EXYNOS4X12_GPIO_A00;
+ count = 4;
+ break;
+ case PERIPH_ID_UART1:
+ start = EXYNOS4X12_GPIO_A04;
+ count = 4;
+ break;
+ case PERIPH_ID_UART2:
+ start = EXYNOS4X12_GPIO_A10;
+ count = 4;
+ break;
+ case PERIPH_ID_UART3:
+ start = EXYNOS4X12_GPIO_A14;
+ count = 2;
+ break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return;
+ }
+ for (i = start; i < (start + count); i++) {
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+ }
+}
+
static int exynos4_pinmux_config(int peripheral, int flags)
{
switch (peripheral) {
return 0;
}
+static int exynos4x12_pinmux_config(int peripheral, int flags)
+{
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART2:
+ case PERIPH_ID_UART3:
+ exynos4x12_uart_config(peripheral);
+ break;
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ case PERIPH_ID_I2C4:
+ case PERIPH_ID_I2C5:
+ case PERIPH_ID_I2C6:
+ case PERIPH_ID_I2C7:
+ exynos4x12_i2c_config(peripheral, flags);
+ break;
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC2:
+ return exynos4x12_mmc_config(peripheral, flags);
+ case PERIPH_ID_SDMMC1:
+ case PERIPH_ID_SDMMC3:
+ case PERIPH_ID_SDMMC4:
+ debug("SDMMC device %d not implemented\n", peripheral);
+ return -1;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return -1;
+ }
+
+ return 0;
+}
+
int exynos_pinmux_config(int peripheral, int flags)
{
if (cpu_is_exynos5()) {
else if (proid_is_exynos5250())
return exynos5_pinmux_config(peripheral, flags);
} else if (cpu_is_exynos4()) {
- return exynos4_pinmux_config(peripheral, flags);
- } else {
- debug("pinmux functionality not supported\n");
+ if (proid_is_exynos4412())
+ return exynos4x12_pinmux_config(peripheral, flags);
+ else
+ return exynos4_pinmux_config(peripheral, flags);
}
+ debug("pinmux functionality not supported\n");
+
return -1;
}
return exynos5_pinmux_decode_periph_id(blob, node);
else if (cpu_is_exynos4())
return exynos4_pinmux_decode_periph_id(blob, node);
- else
- return PERIPH_ID_NONE;
+
+ return PERIPH_ID_NONE;
}
#endif
obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
obj-$(CONFIG_GLOBAL_TIMER) += timer.o
obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
-obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-r8a7790.o pfc-r8a7790.o
-obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-r8a7791.o pfc-r8a7791.o
+obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7790.o
+obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o
obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o
+++ /dev/null
-/*
- * arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c
- *
- * Copyright (C) 2013 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-#include <common.h>
-#include <asm/io.h>
-
-#define PRR 0xFF000044
-
-u32 rmobile_get_cpu_type(void)
-{
- u32 product;
-
- product = readl(PRR);
-
- return (u32)((product & 0x00007F00) >> 8);
-}
-
-u32 rmobile_get_cpu_rev_integer(void)
-{
- u32 product;
-
- product = readl(PRR);
-
- return (u32)((product & 0x000000F0) >> 4);
-}
/*
- * arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c
- * This file is r8a7790 processor support.
+ * arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c
*
- * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
u32 rmobile_get_cpu_rev_integer(void)
{
- return (readl(PRR) & 0x000000F0) >> 4;
+ return ((readl(PRR) & 0x000000F0) >> 4) + 1;
+}
+
+u32 rmobile_get_cpu_rev_fraction(void)
+{
+ return readl(PRR) & 0x0000000F;
}
u32 rmobile_get_cpu_rev_fraction(void)
__attribute__((weak, alias("__rmobile_get_cpu_rev_fraction")));
+/* CPU infomation table */
+static const struct {
+ u16 cpu_type;
+ u8 cpu_name[10];
+} rmobile_cpuinfo[] = {
+ { 0x37, "SH73A0" },
+ { 0x40, "R8A7740" },
+ { 0x45, "R8A7790" },
+ { 0x47, "R8A7791" },
+ { 0x0, "CPU" },
+};
+
int print_cpuinfo(void)
{
- switch (rmobile_get_cpu_type()) {
- case 0x37:
- printf("CPU: Renesas Electronics SH73A0 rev %d.%d\n",
- rmobile_get_cpu_rev_integer(),
- rmobile_get_cpu_rev_fraction());
- break;
- case 0x40:
- printf("CPU: Renesas Electronics R8A7740 rev %d.%d\n",
- rmobile_get_cpu_rev_integer(),
- rmobile_get_cpu_rev_fraction());
- break;
-
- case 0x45:
- printf("CPU: Renesas Electronics R8A7790 rev %d\n",
- rmobile_get_cpu_rev_integer());
- break;
-
- case 0x47:
- printf("CPU: Renesas Electronics R8A7791 rev %d\n",
- rmobile_get_cpu_rev_integer());
- break;
-
- default:
- printf("CPU: Renesas Electronics CPU rev %d.%d\n",
- rmobile_get_cpu_rev_integer(),
- rmobile_get_cpu_rev_fraction());
- break;
+ int i = 0;
+ u32 cpu_type = rmobile_get_cpu_type();
+ for (; i < ARRAY_SIZE(rmobile_cpuinfo); i++) {
+ if (rmobile_cpuinfo[i].cpu_type == cpu_type) {
+ printf("CPU: Renesas Electronics %s rev %d.%d\n",
+ rmobile_cpuinfo[i].cpu_name,
+ rmobile_get_cpu_rev_integer(),
+ rmobile_get_cpu_rev_fraction());
+ break;
+ }
}
return 0;
}
* arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
* This file is lager low level initialize.
*
- * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013, 2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
.align 4
do_lowlevel_init:
/* surpress wfe if ca15 */
- tst r4, #4
+ tst r4, #4
mrceq p15, 0, r0, c1, c0, 1 /* actlr */
orreq r0, r0, #(1<<7)
mcreq p15, 0, r0, c1, c0, 1
+
/* and set l2 latency */
mrceq p15, 1, r0, c9, c0, 2 /* l2ctlr */
orreq r0, r0, #0x00000800
orreq r0, r0, #0x00000003
mcreq p15, 1, r0, c9, c0, 2
+ mrc p15, 0, r0, c0, c0, 5 /* r0 = MPIDR */
+ and r0, r0, #0xf00
+ lsr r0, r0, #8
+ tst r0, #1 /* only need for cluster 0 */
+ bne _exit_init_l2_a15
+
+ mrc p15, 1, r0, c9, c0, 2 /* r0 = L2CTLR */
+ and r1, r0, #7
+ cmp r1, #3 /* has already been set up */
+ bicne r0, r0, #0xe7
+ orrne r0, r0, #0x83 /* L2CTLR[7:6] + L2CTLR[2:0] */
+ orrne r0, r0, #0x20 /* L2CTLR[5] */
+ mcrne p15, 1, r0, c9, c0, 2
+
+_exit_init_l2_a15:
ldr r3, =(CONFIG_SYS_INIT_SP_ADDR)
sub sp, r3, #4
str lr, [sp]
/* Save the parameter pass in by previous boot loader */
.global save_boot_params
save_boot_params:
- /* save the parameter here */
-
- /*
- * Setup stack for exception, which is located
- * at the end of on-chip RAM. We don't expect exception prior to
- * relocation and if that happens, we won't worry -- it will overide
- * global data region as the code will goto reset. After relocation,
- * this region won't be used by other part of program.
- * Hence it is safe.
- */
- ldr r0, =(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
- ldr r1, =IRQ_STACK_START_IN
- str r0, [r1]
-
+ /* no parameter to save */
bx lr
#include <asm/system.h>
#include <linux/linkage.h>
-.globl _start
-_start: b reset
- ldr pc, _undefined_instruction
- ldr pc, _software_interrupt
- ldr pc, _prefetch_abort
- ldr pc, _data_abort
- ldr pc, _not_used
- ldr pc, _irq
- ldr pc, _fiq
-#ifdef CONFIG_SPL_BUILD
-_undefined_instruction: .word _undefined_instruction
-_software_interrupt: .word _software_interrupt
-_prefetch_abort: .word _prefetch_abort
-_data_abort: .word _data_abort
-_not_used: .word _not_used
-_irq: .word _irq
-_fiq: .word _fiq
-_pad: .word 0x12345678 /* now 16*4=64 */
-#else
-.globl _undefined_instruction
-_undefined_instruction: .word undefined_instruction
-.globl _software_interrupt
-_software_interrupt: .word software_interrupt
-.globl _prefetch_abort
-_prefetch_abort: .word prefetch_abort
-.globl _data_abort
-_data_abort: .word data_abort
-.globl _not_used
-_not_used: .word not_used
-.globl _irq
-_irq: .word irq
-.globl _fiq
-_fiq: .word fiq
-_pad: .word 0x12345678 /* now 16*4=64 */
-#endif /* CONFIG_SPL_BUILD */
-
-.global _end_vect
-_end_vect:
-
- .balignl 16,0xdeadbeef
/*************************************************************************
*
* Startup Code (reset vector)
*
*************************************************************************/
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
- .word 0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
- .word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
- .word 0x0badc0de
-
-/*
- * the actual reset code
- */
+ .globl reset
reset:
bl save_boot_params
b lowlevel_init @ go setup pll,mux,memory
ENDPROC(cpu_init_crit)
#endif
-
-#ifndef CONFIG_SPL_BUILD
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE 72
-
-#define S_OLD_R0 68
-#define S_PSR 64
-#define S_PC 60
-#define S_LR 56
-#define S_SP 52
-
-#define S_IP 48
-#define S_FP 44
-#define S_R10 40
-#define S_R9 36
-#define S_R8 32
-#define S_R7 28
-#define S_R6 24
-#define S_R5 20
-#define S_R4 16
-#define S_R3 12
-#define S_R2 8
-#define S_R1 4
-#define S_R0 0
-
-#define MODE_SVC 0x13
-#define I_BIT 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
- .macro bad_save_user_regs
- sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
- @ user stack
- stmia sp, {r0 - r12} @ Save user registers (now in
- @ svc mode) r0-r12
- ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
- @ stack
- ldmia r2, {r2 - r3} @ get values for "aborted" pc
- @ and cpsr (into parm regs)
- add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
-
- add r5, sp, #S_SP
- mov r1, lr
- stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
- mov r0, sp @ save current stack into r0
- @ (param register)
- .endm
-
- .macro irq_save_user_regs
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} @ Calling r0-r12
- add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
- @ a reserved stack spot would
- @ be good.
- stmdb r8, {sp, lr}^ @ Calling SP, LR
- str lr, [r8, #0] @ Save calling PC
- mrs r6, spsr
- str r6, [r8, #4] @ Save CPSR
- str r0, [r8, #8] @ Save OLD_R0
- mov r0, sp
- .endm
-
- .macro irq_restore_user_regs
- ldmia sp, {r0 - lr}^ @ Calling r0 - lr
- mov r0, r0
- ldr lr, [sp, #S_PC] @ Get PC
- add sp, sp, #S_FRAME_SIZE
- subs pc, lr, #4 @ return & move spsr_svc into
- @ cpsr
- .endm
-
- .macro get_bad_stack
- ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
- @ in banked mode)
-
- str lr, [r13] @ save caller lr in position 0
- @ of saved stack
- mrs lr, spsr @ get the spsr
- str lr, [r13, #4] @ save spsr in position 1 of
- @ saved stack
-
- mov r13, #MODE_SVC @ prepare SVC-Mode
- @ msr spsr_c, r13
- msr spsr, r13 @ switch modes, make sure
- @ moves will execute
- mov lr, pc @ capture return pc
- movs pc, lr @ jump to next instruction &
- @ switch modes.
- .endm
-
- .macro get_bad_stack_swi
- sub r13, r13, #4 @ space on current stack for
- @ scratch reg.
- str r0, [r13] @ save R0's value.
- ldr r0, IRQ_STACK_START_IN @ get data regions start
- @ spots for abort stack
- str lr, [r0] @ save caller lr in position 0
- @ of saved stack
- mrs lr, spsr @ get the spsr
- str lr, [r0, #4] @ save spsr in position 1 of
- @ saved stack
- ldr lr, [r0] @ restore lr
- ldr r0, [r13] @ restore r0
- add r13, r13, #4 @ pop stack entry
- .endm
-
- .macro get_irq_stack @ setup IRQ stack
- ldr sp, IRQ_STACK_START
- .endm
-
- .macro get_fiq_stack @ setup FIQ stack
- ldr sp, FIQ_STACK_START
- .endm
-
-/*
- * exception handlers
- */
- .align 5
-undefined_instruction:
- get_bad_stack
- bad_save_user_regs
- bl do_undefined_instruction
-
- .align 5
-software_interrupt:
- get_bad_stack_swi
- bad_save_user_regs
- bl do_software_interrupt
-
- .align 5
-prefetch_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_prefetch_abort
-
- .align 5
-data_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_data_abort
-
- .align 5
-not_used:
- get_bad_stack
- bad_save_user_regs
- bl do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
- .align 5
-irq:
- get_irq_stack
- irq_save_user_regs
- bl do_irq
- irq_restore_user_regs
-
- .align 5
-fiq:
- get_fiq_stack
- /* someone ought to write a more effective fiq_save_user_regs */
- irq_save_user_regs
- bl do_fiq
- irq_restore_user_regs
-
-#else
-
- .align 5
-irq:
- get_bad_stack
- bad_save_user_regs
- bl do_irq
-
- .align 5
-fiq:
- get_bad_stack
- bad_save_user_regs
- bl do_fiq
-
-#endif /* CONFIG_USE_IRQ */
-#endif /* CONFIG_SPL_BUILD */
}
/*
- * Zynq needs to discard more sections because the user
+ * Zynq needs to discard these sections because the user
* is expected to pass this image on to tools for boot.bin
* generation that require them to be dropped.
*/
#include <errno.h>
#include <linux/compiler.h>
+#ifdef CONFIG_CPU_PXA25X
+#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
+#error "Init SP address must be set to 0xfffff800 for PXA250"
+#endif
+#endif
+
#define CPU_MASK_PXA_PRODID 0x000003f0
#define CPU_MASK_PXA_REVID 0x0000000f
#include <config.h>
#include <version.h>
-#ifdef CONFIG_CPU_PXA25X
-#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
-#error "Init SP address must be set to 0xfffff800 for PXA250"
-#endif
-#endif
-
-.globl _start
-_start: b reset
-#ifdef CONFIG_SPL_BUILD
- ldr pc, _hang
- ldr pc, _hang
- ldr pc, _hang
- ldr pc, _hang
- ldr pc, _hang
- ldr pc, _hang
- ldr pc, _hang
-
-_hang:
- .word do_hang
- .word 0x12345678
- .word 0x12345678
- .word 0x12345678
- .word 0x12345678
- .word 0x12345678
- .word 0x12345678
- .word 0x12345678 /* now 16*4=64 */
-#else
- ldr pc, _undefined_instruction
- ldr pc, _software_interrupt
- ldr pc, _prefetch_abort
- ldr pc, _data_abort
- ldr pc, _not_used
- ldr pc, _irq
- ldr pc, _fiq
-
-_undefined_instruction: .word undefined_instruction
-_software_interrupt: .word software_interrupt
-_prefetch_abort: .word prefetch_abort
-_data_abort: .word data_abort
-_not_used: .word not_used
-_irq: .word irq
-_fiq: .word fiq
-_pad: .word 0x12345678 /* now 16*4=64 */
-#endif /* CONFIG_SPL_BUILD */
-.global _end_vect
-_end_vect:
-
- .balignl 16,0xdeadbeef
/*
*************************************************************************
*
*************************************************************************
*/
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
- .word 0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
- .word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
- .word 0x0badc0de
-
-/*
- * the actual reset code
- */
+ .globl reset
reset:
/*
mov pc, lr /* back to my caller */
#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
-#ifndef CONFIG_SPL_BUILD
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE 72
-
-#define S_OLD_R0 68
-#define S_PSR 64
-#define S_PC 60
-#define S_LR 56
-#define S_SP 52
-
-#define S_IP 48
-#define S_FP 44
-#define S_R10 40
-#define S_R9 36
-#define S_R8 32
-#define S_R7 28
-#define S_R6 24
-#define S_R5 20
-#define S_R4 16
-#define S_R3 12
-#define S_R2 8
-#define S_R1 4
-#define S_R0 0
-
-#define MODE_SVC 0x13
-#define I_BIT 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
- .macro bad_save_user_regs
- sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
- stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
-
- ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
- ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
- add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
-
- add r5, sp, #S_SP
- mov r1, lr
- stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
- mov r0, sp @ save current stack into r0 (param register)
- .endm
-
- .macro irq_save_user_regs
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} @ Calling r0-r12
- add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
- stmdb r8, {sp, lr}^ @ Calling SP, LR
- str lr, [r8, #0] @ Save calling PC
- mrs r6, spsr
- str r6, [r8, #4] @ Save CPSR
- str r0, [r8, #8] @ Save OLD_R0
- mov r0, sp
- .endm
-
- .macro irq_restore_user_regs
- ldmia sp, {r0 - lr}^ @ Calling r0 - lr
- mov r0, r0
- ldr lr, [sp, #S_PC] @ Get PC
- add sp, sp, #S_FRAME_SIZE
- subs pc, lr, #4 @ return & move spsr_svc into cpsr
- .endm
-
- .macro get_bad_stack
- ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
-
- str lr, [r13] @ save caller lr in position 0 of saved stack
- mrs lr, spsr @ get the spsr
- str lr, [r13, #4] @ save spsr in position 1 of saved stack
-
- mov r13, #MODE_SVC @ prepare SVC-Mode
- @ msr spsr_c, r13
- msr spsr, r13 @ switch modes, make sure moves will execute
- mov lr, pc @ capture return pc
- movs pc, lr @ jump to next instruction & switch modes.
- .endm
-
- .macro get_bad_stack_swi
- sub r13, r13, #4 @ space on current stack for scratch reg.
- str r0, [r13] @ save R0's value.
- ldr r0, IRQ_STACK_START_IN @ get data regions start
- str lr, [r0] @ save caller lr in position 0 of saved stack
- mrs lr, spsr @ get the spsr
- str lr, [r0, #4] @ save spsr in position 1 of saved stack
- ldr lr, [r0] @ restore lr
- ldr r0, [r13] @ restore r0
- add r13, r13, #4 @ pop stack entry
- .endm
-
- .macro get_irq_stack @ setup IRQ stack
- ldr sp, IRQ_STACK_START
- .endm
-
- .macro get_fiq_stack @ setup FIQ stack
- ldr sp, FIQ_STACK_START
- .endm
-#endif /* CONFIG_SPL_BUILD */
-
-/*
- * exception handlers
- */
-#ifdef CONFIG_SPL_BUILD
- .align 5
-do_hang:
- bl hang /* hang and never return */
-#else /* !CONFIG_SPL_BUILD */
- .align 5
-undefined_instruction:
- get_bad_stack
- bad_save_user_regs
- bl do_undefined_instruction
-
- .align 5
-software_interrupt:
- get_bad_stack_swi
- bad_save_user_regs
- bl do_software_interrupt
-
- .align 5
-prefetch_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_prefetch_abort
-
- .align 5
-data_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_data_abort
-
- .align 5
-not_used:
- get_bad_stack
- bad_save_user_regs
- bl do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
- .align 5
-irq:
- get_irq_stack
- irq_save_user_regs
- bl do_irq
- irq_restore_user_regs
-
- .align 5
-fiq:
- get_fiq_stack
- /* someone ought to write a more effiction fiq_save_user_regs */
- irq_save_user_regs
- bl do_fiq
- irq_restore_user_regs
-
-#else
-
- .align 5
-irq:
- get_bad_stack
- bad_save_user_regs
- bl do_irq
-
- .align 5
-fiq:
- get_bad_stack
- bad_save_user_regs
- bl do_fiq
-
-#endif
- .align 5
-#endif /* CONFIG_SPL_BUILD */
-
-
/*
* Enable MMU to use DCache as DRAM.
*
#include <common.h>
#include <command.h>
#include <asm/system.h>
+#include <asm/io.h>
#ifdef CONFIG_USE_IRQ
DECLARE_GLOBAL_DATA_PTR;
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
}
+
+#define RST_BASE 0x90030000
+#define RSRR 0x00
+#define RCSR 0x04
+
+__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused)))
+{
+ /* repeat endlessly */
+ while (1) {
+ writel(0, RST_BASE + RCSR);
+ writel(1, RST_BASE + RSRR);
+ }
+}
#include <config.h>
#include <version.h>
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-
-.globl _start
-_start: b reset
- ldr pc, _undefined_instruction
- ldr pc, _software_interrupt
- ldr pc, _prefetch_abort
- ldr pc, _data_abort
- ldr pc, _not_used
- ldr pc, _irq
- ldr pc, _fiq
-
-_undefined_instruction: .word undefined_instruction
-_software_interrupt: .word software_interrupt
-_prefetch_abort: .word prefetch_abort
-_data_abort: .word data_abort
-_not_used: .word not_used
-_irq: .word irq
-_fiq: .word fiq
-
- .balignl 16,0xdeadbeef
-
-
/*
*************************************************************************
*
*************************************************************************
*/
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
- .word 0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
- .word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
- .word 0x0badc0de
-
-/*
- * the actual reset code
- */
+ .globl reset
reset:
/*
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
mov pc, lr
-
-
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE 72
-
-#define S_OLD_R0 68
-#define S_PSR 64
-#define S_PC 60
-#define S_LR 56
-#define S_SP 52
-
-#define S_IP 48
-#define S_FP 44
-#define S_R10 40
-#define S_R9 36
-#define S_R8 32
-#define S_R7 28
-#define S_R6 24
-#define S_R5 20
-#define S_R4 16
-#define S_R3 12
-#define S_R2 8
-#define S_R1 4
-#define S_R0 0
-
-#define MODE_SVC 0x13
-#define I_BIT 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
- .macro bad_save_user_regs
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} @ Calling r0-r12
- add r8, sp, #S_PC
-
- ldr r2, IRQ_STACK_START_IN
- ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
- add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
-
- add r5, sp, #S_SP
- mov r1, lr
- stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
- mov r0, sp
- .endm
-
- .macro irq_save_user_regs
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} @ Calling r0-r12
- add r8, sp, #S_PC
- stmdb r8, {sp, lr}^ @ Calling SP, LR
- str lr, [r8, #0] @ Save calling PC
- mrs r6, spsr
- str r6, [r8, #4] @ Save CPSR
- str r0, [r8, #8] @ Save OLD_R0
- mov r0, sp
- .endm
-
- .macro irq_restore_user_regs
- ldmia sp, {r0 - lr}^ @ Calling r0 - lr
- mov r0, r0
- ldr lr, [sp, #S_PC] @ Get PC
- add sp, sp, #S_FRAME_SIZE
- subs pc, lr, #4 @ return & move spsr_svc into cpsr
- .endm
-
- .macro get_bad_stack
- ldr r13, IRQ_STACK_START_IN @ setup our mode stack
-
- str lr, [r13] @ save caller lr / spsr
- mrs lr, spsr
- str lr, [r13, #4]
-
- mov r13, #MODE_SVC @ prepare SVC-Mode
- msr spsr_c, r13
- mov lr, pc
- movs pc, lr
- .endm
-
- .macro get_irq_stack @ setup IRQ stack
- ldr sp, IRQ_STACK_START
- .endm
-
- .macro get_fiq_stack @ setup FIQ stack
- ldr sp, FIQ_STACK_START
- .endm
-
-/*
- * exception handlers
- */
- .align 5
-undefined_instruction:
- get_bad_stack
- bad_save_user_regs
- bl do_undefined_instruction
-
- .align 5
-software_interrupt:
- get_bad_stack
- bad_save_user_regs
- bl do_software_interrupt
-
- .align 5
-prefetch_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_prefetch_abort
-
- .align 5
-data_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_data_abort
-
- .align 5
-not_used:
- get_bad_stack
- bad_save_user_regs
- bl do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
- .align 5
-irq:
- get_irq_stack
- irq_save_user_regs
- bl do_irq
- irq_restore_user_regs
-
- .align 5
-fiq:
- get_fiq_stack
- /* someone ought to write a more effiction fiq_save_user_regs */
- irq_save_user_regs
- bl do_fiq
- irq_restore_user_regs
-
-#else
-
- .align 5
-irq:
- get_bad_stack
- bad_save_user_regs
- bl do_irq
-
- .align 5
-fiq:
- get_bad_stack
- bad_save_user_regs
- bl do_fiq
-
-#endif
-
- .align 5
-.globl reset_cpu
-reset_cpu:
- ldr r0, RST_BASE
- mov r1, #0x0 @ set bit 3-0 ...
- str r1, [r0, #RCSR] @ ... to clear in RCSR
- mov r1, #0x1
- str r1, [r0, #RSRR] @ and perform reset
- b reset_cpu @ silly, but repeat endlessly
#define IO_RESET_SHIFT 8
#define RCV_SEL_SHIFT 9
+#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30)
+/* This register/field only exists on Tegra114 and later */
+#define APB_MISC_PP_PINMUX_GLOBAL_0 0x40
+#define CLAMP_INPUTS_WHEN_TRISTATED 1
+
+void pinmux_set_tristate_input_clamping(void)
+{
+ u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
+ u32 val;
+
+ val = readl(reg);
+ val |= CLAMP_INPUTS_WHEN_TRISTATED;
+ writel(val, reg);
+}
+#endif
+
void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
{
u32 *reg = MUX_REG(pin);
int i, mux = -1;
u32 val;
+ if (func == PMUX_FUNC_DEFAULT)
+ return;
+
/* Error check on pin and func */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_func_isvalid(func));
.text :
{
__image_copy_start = .;
+ *(.vectors)
CPUDIR/start.o (.text*)
*(.text*)
}
.text :
{
*(.__image_copy_start)
+ *(.vectors)
CPUDIR/start.o (.text*)
*(.text*)
}
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
- cd-gpios = <&gpio 0x2008002 0>;
+ cd-gpios = <&gpio 0xA2 0>;
};
sdhci@12540000 {
status = "disabled";
};
-};
\ No newline at end of file
+};
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
- pwr-gpios = <&gpio 0x2008002 0>;
+ pwr-gpios = <&gpio 0xA2 0>;
};
sdhci@12520000 {
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
- cd-gpios = <&gpio 0x20c6004 0>;
+ cd-gpios = <&gpio 0x39C 0>;
};
sdhci@12540000 {
status = "disabled";
};
-};
\ No newline at end of file
+};
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
- pwr-gpios = <&gpio 0x2008002 0>;
+ pwr-gpios = <&gpio 0xA2 0>;
};
sdhci@12520000 {
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
- cd-gpios = <&gpio 0x20c6004 0>;
+ cd-gpios = <&gpio 0x39C 0>;
};
sdhci@12540000 {
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
- pwr-gpios = <&gpio 0x2004002 0>;
+ pwr-gpios = <&gpio 0xB2 0>;
};
sdhci@12520000 {
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
- cd-gpios = <&gpio 0x20C6004 0>;
+ cd-gpios = <&gpio 0x3BC 0>;
};
sdhci@12540000 {
/*
- + * Copyright 2012 Freescale Semiconductor, Inc.
- + * Copyright 2011 Linaro Ltd.
- + *
- + * SPDX-License-Identifier: GPL-2.0+
- + */
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
/dts-v1/;
endif
ifeq ($(SOC),$(filter $(SOC),mx6))
obj-$(CONFIG_CMD_SATA) += sata.o
+obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
endif
obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
(pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
+#if defined CONFIG_MX6SL
+ /* Check whether LVE bit needs to be set */
+ if (pad_ctrl & PAD_CTL_LVE) {
+ pad_ctrl &= ~PAD_CTL_LVE;
+ pad_ctrl |= PAD_CTL_LVE_BIT;
+ }
+#endif
+
if (mux_ctrl_ofs)
__raw_writel(mux_mode, base + mux_ctrl_ofs);
--- /dev/null
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/imx-common/video.h>
+
+extern struct display_info_t const displays[];
+extern size_t display_count;
+
+int board_video_skip(void)
+{
+ int i;
+ int ret;
+ char const *panel = getenv("panel");
+ if (!panel) {
+ for (i = 0; i < display_count; i++) {
+ struct display_info_t const *dev = displays+i;
+ if (dev->detect && dev->detect(dev)) {
+ panel = dev->mode.name;
+ printf("auto-detected panel %s\n", panel);
+ break;
+ }
+ }
+ if (!panel) {
+ panel = displays[0].mode.name;
+ printf("No panel detected: default to %s\n", panel);
+ i = 0;
+ }
+ } else {
+ for (i = 0; i < display_count; i++) {
+ if (!strcmp(panel, displays[i].mode.name))
+ break;
+ }
+ }
+ if (i < display_count) {
+ ret = ipuv3_fb_init(&displays[i].mode, 0,
+ displays[i].pixfmt);
+ if (!ret) {
+ displays[i].enable(displays+i);
+ printf("Display: %s (%ux%u)\n",
+ displays[i].mode.name,
+ displays[i].mode.xres,
+ displays[i].mode.yres);
+ } else
+ printf("LCD %s cannot be configured: %d\n",
+ displays[i].mode.name, ret);
+ } else {
+ printf("unsupported panel %s\n", panel);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_IMX_HDMI
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/io.h>
+int detect_hdmi(struct display_info_t const *dev)
+{
+ struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+ return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
+}
+#endif
#define MODULE_CLKCTRL_IDLEST_DISABLED 3
/* CM_CLKMODE_DPLL */
+#define CM_CLKMODE_DPLL_SSC_EN_SHIFT 12
+#define CM_CLKMODE_DPLL_SSC_EN_MASK (1 << 12)
#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
#define EXYNOS5_I2C_SPACING 0x10000
#define EXYNOS5_AUDIOSS_BASE 0x03810000
-#define EXYNOS5_GPIO_PART4_BASE 0x03860000
+#define EXYNOS5_GPIO_PART8_BASE 0x03860000
#define EXYNOS5_PRO_ID 0x10000000
#define EXYNOS5_CLOCK_BASE 0x10010000
#define EXYNOS5_POWER_BASE 0x10040000
#define EXYNOS5_WATCHDOG_BASE 0x101D0000
#define EXYNOS5_ACE_SFR_BASE 0x10830000
#define EXYNOS5_DMC_PHY_BASE 0x10C00000
-#define EXYNOS5_GPIO_PART3_BASE 0x10D10000
+#define EXYNOS5_GPIO_PART5_BASE 0x10D10000
+#define EXYNOS5_GPIO_PART6_BASE 0x10D10060
+#define EXYNOS5_GPIO_PART7_BASE 0x10D100C0
#define EXYNOS5_DMC_CTRL_BASE 0x10DD0000
#define EXYNOS5_GPIO_PART1_BASE 0x11400000
+#define EXYNOS5_GPIO_PART2_BASE 0x114002E0
+#define EXYNOS5_GPIO_PART3_BASE 0x11400C00
#define EXYNOS5_MIPI_DSIM_BASE 0x11D00000
#define EXYNOS5_USB_HOST_XHCI_BASE 0x12000000
#define EXYNOS5_USB3PHY_BASE 0x12100000
#define EXYNOS5_I2S_BASE 0x12D60000
#define EXYNOS5_PWMTIMER_BASE 0x12DD0000
#define EXYNOS5_SPI_ISP_BASE 0x131A0000
-#define EXYNOS5_GPIO_PART2_BASE 0x13400000
+#define EXYNOS5_GPIO_PART4_BASE 0x13400000
#define EXYNOS5_FIMD_BASE 0x14400000
#define EXYNOS5_DP_BASE 0x145B0000
/* EXYNOS5420 */
#define EXYNOS5420_AUDIOSS_BASE 0x03810000
-#define EXYNOS5420_GPIO_PART5_BASE 0x03860000
+#define EXYNOS5420_GPIO_PART6_BASE 0x03860000
#define EXYNOS5420_PRO_ID 0x10000000
#define EXYNOS5420_CLOCK_BASE 0x10010000
#define EXYNOS5420_POWER_BASE 0x10040000
#define EXYNOS5420_PWMTIMER_BASE 0x12DD0000
#define EXYNOS5420_SPI_ISP_BASE 0x131A0000
#define EXYNOS5420_GPIO_PART2_BASE 0x13400000
-#define EXYNOS5420_GPIO_PART3_BASE 0x13410000
-#define EXYNOS5420_GPIO_PART4_BASE 0x14000000
+#define EXYNOS5420_GPIO_PART3_BASE 0x13400C00
+#define EXYNOS5420_GPIO_PART4_BASE 0x13410000
+#define EXYNOS5420_GPIO_PART5_BASE 0x14000000
#define EXYNOS5420_GPIO_PART1_BASE 0x14010000
#define EXYNOS5420_MIPI_DSIM_BASE 0x14500000
#define EXYNOS5420_DP_BASE 0x145B0000
unsigned char res1[8];
};
-struct exynos4_gpio_part1 {
- struct s5p_gpio_bank a0;
- struct s5p_gpio_bank a1;
- struct s5p_gpio_bank b;
- struct s5p_gpio_bank c0;
- struct s5p_gpio_bank c1;
- struct s5p_gpio_bank d0;
- struct s5p_gpio_bank d1;
- struct s5p_gpio_bank e0;
- struct s5p_gpio_bank e1;
- struct s5p_gpio_bank e2;
- struct s5p_gpio_bank e3;
- struct s5p_gpio_bank e4;
- struct s5p_gpio_bank f0;
- struct s5p_gpio_bank f1;
- struct s5p_gpio_bank f2;
- struct s5p_gpio_bank f3;
-};
+/* GPIO pins per bank */
+#define GPIO_PER_BANK 8
-struct exynos4_gpio_part2 {
- struct s5p_gpio_bank j0;
- struct s5p_gpio_bank j1;
- struct s5p_gpio_bank k0;
- struct s5p_gpio_bank k1;
- struct s5p_gpio_bank k2;
- struct s5p_gpio_bank k3;
- struct s5p_gpio_bank l0;
- struct s5p_gpio_bank l1;
- struct s5p_gpio_bank l2;
- struct s5p_gpio_bank y0;
- struct s5p_gpio_bank y1;
- struct s5p_gpio_bank y2;
- struct s5p_gpio_bank y3;
- struct s5p_gpio_bank y4;
- struct s5p_gpio_bank y5;
- struct s5p_gpio_bank y6;
- struct s5p_gpio_bank res1[80];
- struct s5p_gpio_bank x0;
- struct s5p_gpio_bank x1;
- struct s5p_gpio_bank x2;
- struct s5p_gpio_bank x3;
-};
+/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */
+enum exynos4_gpio_pin {
+ /* GPIO_PART1_STARTS */
+ EXYNOS4_GPIO_A00, /* 0 */
+ EXYNOS4_GPIO_A01,
+ EXYNOS4_GPIO_A02,
+ EXYNOS4_GPIO_A03,
+ EXYNOS4_GPIO_A04,
+ EXYNOS4_GPIO_A05,
+ EXYNOS4_GPIO_A06,
+ EXYNOS4_GPIO_A07,
+ EXYNOS4_GPIO_A10, /* 8 */
+ EXYNOS4_GPIO_A11,
+ EXYNOS4_GPIO_A12,
+ EXYNOS4_GPIO_A13,
+ EXYNOS4_GPIO_A14,
+ EXYNOS4_GPIO_A15,
+ EXYNOS4_GPIO_A16,
+ EXYNOS4_GPIO_A17,
+ EXYNOS4_GPIO_B0, /* 16 0x10 */
+ EXYNOS4_GPIO_B1,
+ EXYNOS4_GPIO_B2,
+ EXYNOS4_GPIO_B3,
+ EXYNOS4_GPIO_B4,
+ EXYNOS4_GPIO_B5,
+ EXYNOS4_GPIO_B6,
+ EXYNOS4_GPIO_B7,
+ EXYNOS4_GPIO_C00, /* 24 0x18 */
+ EXYNOS4_GPIO_C01,
+ EXYNOS4_GPIO_C02,
+ EXYNOS4_GPIO_C03,
+ EXYNOS4_GPIO_C04,
+ EXYNOS4_GPIO_C05,
+ EXYNOS4_GPIO_C06,
+ EXYNOS4_GPIO_C07,
+ EXYNOS4_GPIO_C10, /* 32 0x20*/
+ EXYNOS4_GPIO_C11,
+ EXYNOS4_GPIO_C12,
+ EXYNOS4_GPIO_C13,
+ EXYNOS4_GPIO_C14,
+ EXYNOS4_GPIO_C15,
+ EXYNOS4_GPIO_C16,
+ EXYNOS4_GPIO_C17,
+ EXYNOS4_GPIO_D00, /* 40 0x28 */
+ EXYNOS4_GPIO_D01,
+ EXYNOS4_GPIO_D02,
+ EXYNOS4_GPIO_D03,
+ EXYNOS4_GPIO_D04,
+ EXYNOS4_GPIO_D05,
+ EXYNOS4_GPIO_D06,
+ EXYNOS4_GPIO_D07,
+ EXYNOS4_GPIO_D10, /* 48 0x30 */
+ EXYNOS4_GPIO_D11,
+ EXYNOS4_GPIO_D12,
+ EXYNOS4_GPIO_D13,
+ EXYNOS4_GPIO_D14,
+ EXYNOS4_GPIO_D15,
+ EXYNOS4_GPIO_D16,
+ EXYNOS4_GPIO_D17,
+ EXYNOS4_GPIO_E00, /* 56 0x38 */
+ EXYNOS4_GPIO_E01,
+ EXYNOS4_GPIO_E02,
+ EXYNOS4_GPIO_E03,
+ EXYNOS4_GPIO_E04,
+ EXYNOS4_GPIO_E05,
+ EXYNOS4_GPIO_E06,
+ EXYNOS4_GPIO_E07,
+ EXYNOS4_GPIO_E10, /* 64 0x40 */
+ EXYNOS4_GPIO_E11,
+ EXYNOS4_GPIO_E12,
+ EXYNOS4_GPIO_E13,
+ EXYNOS4_GPIO_E14,
+ EXYNOS4_GPIO_E15,
+ EXYNOS4_GPIO_E16,
+ EXYNOS4_GPIO_E17,
+ EXYNOS4_GPIO_E20, /* 72 0x48 */
+ EXYNOS4_GPIO_E21,
+ EXYNOS4_GPIO_E22,
+ EXYNOS4_GPIO_E23,
+ EXYNOS4_GPIO_E24,
+ EXYNOS4_GPIO_E25,
+ EXYNOS4_GPIO_E26,
+ EXYNOS4_GPIO_E27,
+ EXYNOS4_GPIO_E30, /* 80 0x50 */
+ EXYNOS4_GPIO_E31,
+ EXYNOS4_GPIO_E32,
+ EXYNOS4_GPIO_E33,
+ EXYNOS4_GPIO_E34,
+ EXYNOS4_GPIO_E35,
+ EXYNOS4_GPIO_E36,
+ EXYNOS4_GPIO_E37,
+ EXYNOS4_GPIO_E40, /* 88 0x58 */
+ EXYNOS4_GPIO_E41,
+ EXYNOS4_GPIO_E42,
+ EXYNOS4_GPIO_E43,
+ EXYNOS4_GPIO_E44,
+ EXYNOS4_GPIO_E45,
+ EXYNOS4_GPIO_E46,
+ EXYNOS4_GPIO_E47,
+ EXYNOS4_GPIO_F00, /* 96 0x60 */
+ EXYNOS4_GPIO_F01,
+ EXYNOS4_GPIO_F02,
+ EXYNOS4_GPIO_F03,
+ EXYNOS4_GPIO_F04,
+ EXYNOS4_GPIO_F05,
+ EXYNOS4_GPIO_F06,
+ EXYNOS4_GPIO_F07,
+ EXYNOS4_GPIO_F10, /* 104 0x68 */
+ EXYNOS4_GPIO_F11,
+ EXYNOS4_GPIO_F12,
+ EXYNOS4_GPIO_F13,
+ EXYNOS4_GPIO_F14,
+ EXYNOS4_GPIO_F15,
+ EXYNOS4_GPIO_F16,
+ EXYNOS4_GPIO_F17,
+ EXYNOS4_GPIO_F20, /* 112 0x70 */
+ EXYNOS4_GPIO_F21,
+ EXYNOS4_GPIO_F22,
+ EXYNOS4_GPIO_F23,
+ EXYNOS4_GPIO_F24,
+ EXYNOS4_GPIO_F25,
+ EXYNOS4_GPIO_F26,
+ EXYNOS4_GPIO_F27,
+ EXYNOS4_GPIO_F30, /* 120 0x78 */
+ EXYNOS4_GPIO_F31,
+ EXYNOS4_GPIO_F32,
+ EXYNOS4_GPIO_F33,
+ EXYNOS4_GPIO_F34,
+ EXYNOS4_GPIO_F35,
+ EXYNOS4_GPIO_F36,
+ EXYNOS4_GPIO_F37,
-struct exynos4_gpio_part3 {
- struct s5p_gpio_bank z;
-};
+ /* GPIO_PART2_STARTS */
+ EXYNOS4_GPIO_MAX_PORT_PART_1, /* 128 0x80 */
+ EXYNOS4_GPIO_J00 = EXYNOS4_GPIO_MAX_PORT_PART_1,
+ EXYNOS4_GPIO_J01,
+ EXYNOS4_GPIO_J02,
+ EXYNOS4_GPIO_J03,
+ EXYNOS4_GPIO_J04,
+ EXYNOS4_GPIO_J05,
+ EXYNOS4_GPIO_J06,
+ EXYNOS4_GPIO_J07,
+ EXYNOS4_GPIO_J10, /* 136 0x88 */
+ EXYNOS4_GPIO_J11,
+ EXYNOS4_GPIO_J12,
+ EXYNOS4_GPIO_J13,
+ EXYNOS4_GPIO_J14,
+ EXYNOS4_GPIO_J15,
+ EXYNOS4_GPIO_J16,
+ EXYNOS4_GPIO_J17,
+ EXYNOS4_GPIO_K00, /* 144 0x90 */
+ EXYNOS4_GPIO_K01,
+ EXYNOS4_GPIO_K02,
+ EXYNOS4_GPIO_K03,
+ EXYNOS4_GPIO_K04,
+ EXYNOS4_GPIO_K05,
+ EXYNOS4_GPIO_K06,
+ EXYNOS4_GPIO_K07,
+ EXYNOS4_GPIO_K10, /* 152 0x98 */
+ EXYNOS4_GPIO_K11,
+ EXYNOS4_GPIO_K12,
+ EXYNOS4_GPIO_K13,
+ EXYNOS4_GPIO_K14,
+ EXYNOS4_GPIO_K15,
+ EXYNOS4_GPIO_K16,
+ EXYNOS4_GPIO_K17,
+ EXYNOS4_GPIO_K20, /* 160 0xA0 */
+ EXYNOS4_GPIO_K21,
+ EXYNOS4_GPIO_K22,
+ EXYNOS4_GPIO_K23,
+ EXYNOS4_GPIO_K24,
+ EXYNOS4_GPIO_K25,
+ EXYNOS4_GPIO_K26,
+ EXYNOS4_GPIO_K27,
+ EXYNOS4_GPIO_K30, /* 168 0xA8 */
+ EXYNOS4_GPIO_K31,
+ EXYNOS4_GPIO_K32,
+ EXYNOS4_GPIO_K33,
+ EXYNOS4_GPIO_K34,
+ EXYNOS4_GPIO_K35,
+ EXYNOS4_GPIO_K36,
+ EXYNOS4_GPIO_K37,
+ EXYNOS4_GPIO_L00, /* 176 0xB0 */
+ EXYNOS4_GPIO_L01,
+ EXYNOS4_GPIO_L02,
+ EXYNOS4_GPIO_L03,
+ EXYNOS4_GPIO_L04,
+ EXYNOS4_GPIO_L05,
+ EXYNOS4_GPIO_L06,
+ EXYNOS4_GPIO_L07,
+ EXYNOS4_GPIO_L10, /* 184 0xB8 */
+ EXYNOS4_GPIO_L11,
+ EXYNOS4_GPIO_L12,
+ EXYNOS4_GPIO_L13,
+ EXYNOS4_GPIO_L14,
+ EXYNOS4_GPIO_L15,
+ EXYNOS4_GPIO_L16,
+ EXYNOS4_GPIO_L17,
+ EXYNOS4_GPIO_L20, /* 192 0xC0 */
+ EXYNOS4_GPIO_L21,
+ EXYNOS4_GPIO_L22,
+ EXYNOS4_GPIO_L23,
+ EXYNOS4_GPIO_L24,
+ EXYNOS4_GPIO_L25,
+ EXYNOS4_GPIO_L26,
+ EXYNOS4_GPIO_L27,
+ EXYNOS4_GPIO_Y00, /* 200 0xC8 */
+ EXYNOS4_GPIO_Y01,
+ EXYNOS4_GPIO_Y02,
+ EXYNOS4_GPIO_Y03,
+ EXYNOS4_GPIO_Y04,
+ EXYNOS4_GPIO_Y05,
+ EXYNOS4_GPIO_Y06,
+ EXYNOS4_GPIO_Y07,
+ EXYNOS4_GPIO_Y10, /* 208 0xD0 */
+ EXYNOS4_GPIO_Y11,
+ EXYNOS4_GPIO_Y12,
+ EXYNOS4_GPIO_Y13,
+ EXYNOS4_GPIO_Y14,
+ EXYNOS4_GPIO_Y15,
+ EXYNOS4_GPIO_Y16,
+ EXYNOS4_GPIO_Y17,
+ EXYNOS4_GPIO_Y20, /* 216 0xD8 */
+ EXYNOS4_GPIO_Y21,
+ EXYNOS4_GPIO_Y22,
+ EXYNOS4_GPIO_Y23,
+ EXYNOS4_GPIO_Y24,
+ EXYNOS4_GPIO_Y25,
+ EXYNOS4_GPIO_Y26,
+ EXYNOS4_GPIO_Y27,
+ EXYNOS4_GPIO_Y30, /* 224 0xE0 */
+ EXYNOS4_GPIO_Y31,
+ EXYNOS4_GPIO_Y32,
+ EXYNOS4_GPIO_Y33,
+ EXYNOS4_GPIO_Y34,
+ EXYNOS4_GPIO_Y35,
+ EXYNOS4_GPIO_Y36,
+ EXYNOS4_GPIO_Y37,
+ EXYNOS4_GPIO_Y40, /* 232 0xE8 */
+ EXYNOS4_GPIO_Y41,
+ EXYNOS4_GPIO_Y42,
+ EXYNOS4_GPIO_Y43,
+ EXYNOS4_GPIO_Y44,
+ EXYNOS4_GPIO_Y45,
+ EXYNOS4_GPIO_Y46,
+ EXYNOS4_GPIO_Y47,
+ EXYNOS4_GPIO_Y50, /* 240 0xF0 */
+ EXYNOS4_GPIO_Y51,
+ EXYNOS4_GPIO_Y52,
+ EXYNOS4_GPIO_Y53,
+ EXYNOS4_GPIO_Y54,
+ EXYNOS4_GPIO_Y55,
+ EXYNOS4_GPIO_Y56,
+ EXYNOS4_GPIO_Y57,
+ EXYNOS4_GPIO_Y60, /* 248 0xF8 */
+ EXYNOS4_GPIO_Y61,
+ EXYNOS4_GPIO_Y62,
+ EXYNOS4_GPIO_Y63,
+ EXYNOS4_GPIO_Y64,
+ EXYNOS4_GPIO_Y65,
+ EXYNOS4_GPIO_Y66,
+ EXYNOS4_GPIO_Y67,
+ EXYNOS4_GPIO_X00 = 896, /* 896 0x380 */
+ EXYNOS4_GPIO_X01,
+ EXYNOS4_GPIO_X02,
+ EXYNOS4_GPIO_X03,
+ EXYNOS4_GPIO_X04,
+ EXYNOS4_GPIO_X05,
+ EXYNOS4_GPIO_X06,
+ EXYNOS4_GPIO_X07,
+ EXYNOS4_GPIO_X10, /* 904 0x388 */
+ EXYNOS4_GPIO_X11,
+ EXYNOS4_GPIO_X12,
+ EXYNOS4_GPIO_X13,
+ EXYNOS4_GPIO_X14,
+ EXYNOS4_GPIO_X15,
+ EXYNOS4_GPIO_X16,
+ EXYNOS4_GPIO_X17,
+ EXYNOS4_GPIO_X20, /* 912 0x390 */
+ EXYNOS4_GPIO_X21,
+ EXYNOS4_GPIO_X22,
+ EXYNOS4_GPIO_X23,
+ EXYNOS4_GPIO_X24,
+ EXYNOS4_GPIO_X25,
+ EXYNOS4_GPIO_X26,
+ EXYNOS4_GPIO_X27,
+ EXYNOS4_GPIO_X30, /* 920 0x398 */
+ EXYNOS4_GPIO_X31,
+ EXYNOS4_GPIO_X32,
+ EXYNOS4_GPIO_X33,
+ EXYNOS4_GPIO_X34,
+ EXYNOS4_GPIO_X35,
+ EXYNOS4_GPIO_X36,
+ EXYNOS4_GPIO_X37,
+
+ /* GPIO_PART3_STARTS */
+ EXYNOS4_GPIO_MAX_PORT_PART_2, /* 928 0x3A0 */
+ EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2,
+ EXYNOS4_GPIO_Z1,
+ EXYNOS4_GPIO_Z2,
+ EXYNOS4_GPIO_Z3,
+ EXYNOS4_GPIO_Z4,
+ EXYNOS4_GPIO_Z5,
+ EXYNOS4_GPIO_Z6,
+ EXYNOS4_GPIO_Z7,
-struct exynos4x12_gpio_part1 {
- struct s5p_gpio_bank a0;
- struct s5p_gpio_bank a1;
- struct s5p_gpio_bank b;
- struct s5p_gpio_bank c0;
- struct s5p_gpio_bank c1;
- struct s5p_gpio_bank d0;
- struct s5p_gpio_bank d1;
- struct s5p_gpio_bank res1[0x5];
- struct s5p_gpio_bank f0;
- struct s5p_gpio_bank f1;
- struct s5p_gpio_bank f2;
- struct s5p_gpio_bank f3;
- struct s5p_gpio_bank res2[0x2];
- struct s5p_gpio_bank j0;
- struct s5p_gpio_bank j1;
+ EXYNOS4_GPIO_MAX_PORT
};
-struct exynos4x12_gpio_part2 {
- struct s5p_gpio_bank res1[0x2];
- struct s5p_gpio_bank k0;
- struct s5p_gpio_bank k1;
- struct s5p_gpio_bank k2;
- struct s5p_gpio_bank k3;
- struct s5p_gpio_bank l0;
- struct s5p_gpio_bank l1;
- struct s5p_gpio_bank l2;
- struct s5p_gpio_bank y0;
- struct s5p_gpio_bank y1;
- struct s5p_gpio_bank y2;
- struct s5p_gpio_bank y3;
- struct s5p_gpio_bank y4;
- struct s5p_gpio_bank y5;
- struct s5p_gpio_bank y6;
- struct s5p_gpio_bank res2[0x3];
- struct s5p_gpio_bank m0;
- struct s5p_gpio_bank m1;
- struct s5p_gpio_bank m2;
- struct s5p_gpio_bank m3;
- struct s5p_gpio_bank m4;
- struct s5p_gpio_bank res3[0x48];
- struct s5p_gpio_bank x0;
- struct s5p_gpio_bank x1;
- struct s5p_gpio_bank x2;
- struct s5p_gpio_bank x3;
+enum exynos4X12_gpio_pin {
+ /* GPIO_PART1_STARTS */
+ EXYNOS4X12_GPIO_A00, /* 0 */
+ EXYNOS4X12_GPIO_A01,
+ EXYNOS4X12_GPIO_A02,
+ EXYNOS4X12_GPIO_A03,
+ EXYNOS4X12_GPIO_A04,
+ EXYNOS4X12_GPIO_A05,
+ EXYNOS4X12_GPIO_A06,
+ EXYNOS4X12_GPIO_A07,
+ EXYNOS4X12_GPIO_A10, /* 8 */
+ EXYNOS4X12_GPIO_A11,
+ EXYNOS4X12_GPIO_A12,
+ EXYNOS4X12_GPIO_A13,
+ EXYNOS4X12_GPIO_A14,
+ EXYNOS4X12_GPIO_A15,
+ EXYNOS4X12_GPIO_A16,
+ EXYNOS4X12_GPIO_A17,
+ EXYNOS4X12_GPIO_B0, /* 16 0x10 */
+ EXYNOS4X12_GPIO_B1,
+ EXYNOS4X12_GPIO_B2,
+ EXYNOS4X12_GPIO_B3,
+ EXYNOS4X12_GPIO_B4,
+ EXYNOS4X12_GPIO_B5,
+ EXYNOS4X12_GPIO_B6,
+ EXYNOS4X12_GPIO_B7,
+ EXYNOS4X12_GPIO_C00, /* 24 0x18 */
+ EXYNOS4X12_GPIO_C01,
+ EXYNOS4X12_GPIO_C02,
+ EXYNOS4X12_GPIO_C03,
+ EXYNOS4X12_GPIO_C04,
+ EXYNOS4X12_GPIO_C05,
+ EXYNOS4X12_GPIO_C06,
+ EXYNOS4X12_GPIO_C07,
+ EXYNOS4X12_GPIO_C10, /* 32 0x20 */
+ EXYNOS4X12_GPIO_C11,
+ EXYNOS4X12_GPIO_C12,
+ EXYNOS4X12_GPIO_C13,
+ EXYNOS4X12_GPIO_C14,
+ EXYNOS4X12_GPIO_C15,
+ EXYNOS4X12_GPIO_C16,
+ EXYNOS4X12_GPIO_C17,
+ EXYNOS4X12_GPIO_D00, /* 40 0x28 */
+ EXYNOS4X12_GPIO_D01,
+ EXYNOS4X12_GPIO_D02,
+ EXYNOS4X12_GPIO_D03,
+ EXYNOS4X12_GPIO_D04,
+ EXYNOS4X12_GPIO_D05,
+ EXYNOS4X12_GPIO_D06,
+ EXYNOS4X12_GPIO_D07,
+ EXYNOS4X12_GPIO_D10, /* 48 0x30 */
+ EXYNOS4X12_GPIO_D11,
+ EXYNOS4X12_GPIO_D12,
+ EXYNOS4X12_GPIO_D13,
+ EXYNOS4X12_GPIO_D14,
+ EXYNOS4X12_GPIO_D15,
+ EXYNOS4X12_GPIO_D16,
+ EXYNOS4X12_GPIO_D17,
+ EXYNOS4X12_GPIO_F00 = 96, /* 96 0x60 */
+ EXYNOS4X12_GPIO_F01,
+ EXYNOS4X12_GPIO_F02,
+ EXYNOS4X12_GPIO_F03,
+ EXYNOS4X12_GPIO_F04,
+ EXYNOS4X12_GPIO_F05,
+ EXYNOS4X12_GPIO_F06,
+ EXYNOS4X12_GPIO_F07,
+ EXYNOS4X12_GPIO_F10, /* 104 0x68 */
+ EXYNOS4X12_GPIO_F11,
+ EXYNOS4X12_GPIO_F12,
+ EXYNOS4X12_GPIO_F13,
+ EXYNOS4X12_GPIO_F14,
+ EXYNOS4X12_GPIO_F15,
+ EXYNOS4X12_GPIO_F16,
+ EXYNOS4X12_GPIO_F17,
+ EXYNOS4X12_GPIO_F20, /* 112 0x70 */
+ EXYNOS4X12_GPIO_F21,
+ EXYNOS4X12_GPIO_F22,
+ EXYNOS4X12_GPIO_F23,
+ EXYNOS4X12_GPIO_F24,
+ EXYNOS4X12_GPIO_F25,
+ EXYNOS4X12_GPIO_F26,
+ EXYNOS4X12_GPIO_F27,
+ EXYNOS4X12_GPIO_F30, /* 120 0x78 */
+ EXYNOS4X12_GPIO_F31,
+ EXYNOS4X12_GPIO_F32,
+ EXYNOS4X12_GPIO_F33,
+ EXYNOS4X12_GPIO_F34,
+ EXYNOS4X12_GPIO_F35,
+ EXYNOS4X12_GPIO_F36,
+ EXYNOS4X12_GPIO_F37,
+ EXYNOS4X12_GPIO_J00 = 144, /* 144 0x90 */
+ EXYNOS4X12_GPIO_J01,
+ EXYNOS4X12_GPIO_J02,
+ EXYNOS4X12_GPIO_J03,
+ EXYNOS4X12_GPIO_J04,
+ EXYNOS4X12_GPIO_J05,
+ EXYNOS4X12_GPIO_J06,
+ EXYNOS4X12_GPIO_J07,
+ EXYNOS4X12_GPIO_J10, /* 152 0x98 */
+ EXYNOS4X12_GPIO_J11,
+ EXYNOS4X12_GPIO_J12,
+ EXYNOS4X12_GPIO_J13,
+ EXYNOS4X12_GPIO_J14,
+ EXYNOS4X12_GPIO_J15,
+ EXYNOS4X12_GPIO_J16,
+ EXYNOS4X12_GPIO_J17,
+
+ /* GPIO_PART2_STARTS */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 160 0xA0 */
+ EXYNOS4X12_GPIO_K00 = 176, /* 176 0xB0 */
+ EXYNOS4X12_GPIO_K01,
+ EXYNOS4X12_GPIO_K02,
+ EXYNOS4X12_GPIO_K03,
+ EXYNOS4X12_GPIO_K04,
+ EXYNOS4X12_GPIO_K05,
+ EXYNOS4X12_GPIO_K06,
+ EXYNOS4X12_GPIO_K07,
+ EXYNOS4X12_GPIO_K10, /* 184 0xB8 */
+ EXYNOS4X12_GPIO_K11,
+ EXYNOS4X12_GPIO_K12,
+ EXYNOS4X12_GPIO_K13,
+ EXYNOS4X12_GPIO_K14,
+ EXYNOS4X12_GPIO_K15,
+ EXYNOS4X12_GPIO_K16,
+ EXYNOS4X12_GPIO_K17,
+ EXYNOS4X12_GPIO_K20, /* 192 0xC0 */
+ EXYNOS4X12_GPIO_K21,
+ EXYNOS4X12_GPIO_K22,
+ EXYNOS4X12_GPIO_K23,
+ EXYNOS4X12_GPIO_K24,
+ EXYNOS4X12_GPIO_K25,
+ EXYNOS4X12_GPIO_K26,
+ EXYNOS4X12_GPIO_K27,
+ EXYNOS4X12_GPIO_K30, /* 200 0xC8 */
+ EXYNOS4X12_GPIO_K31,
+ EXYNOS4X12_GPIO_K32,
+ EXYNOS4X12_GPIO_K33,
+ EXYNOS4X12_GPIO_K34,
+ EXYNOS4X12_GPIO_K35,
+ EXYNOS4X12_GPIO_K36,
+ EXYNOS4X12_GPIO_K37,
+ EXYNOS4X12_GPIO_L00, /* 208 0xD0 */
+ EXYNOS4X12_GPIO_L01,
+ EXYNOS4X12_GPIO_L02,
+ EXYNOS4X12_GPIO_L03,
+ EXYNOS4X12_GPIO_L04,
+ EXYNOS4X12_GPIO_L05,
+ EXYNOS4X12_GPIO_L06,
+ EXYNOS4X12_GPIO_L07,
+ EXYNOS4X12_GPIO_L10, /* 216 0xD8 */
+ EXYNOS4X12_GPIO_L11,
+ EXYNOS4X12_GPIO_L12,
+ EXYNOS4X12_GPIO_L13,
+ EXYNOS4X12_GPIO_L14,
+ EXYNOS4X12_GPIO_L15,
+ EXYNOS4X12_GPIO_L16,
+ EXYNOS4X12_GPIO_L17,
+ EXYNOS4X12_GPIO_L20, /* 224 0xE0 */
+ EXYNOS4X12_GPIO_L21,
+ EXYNOS4X12_GPIO_L22,
+ EXYNOS4X12_GPIO_L23,
+ EXYNOS4X12_GPIO_L24,
+ EXYNOS4X12_GPIO_L25,
+ EXYNOS4X12_GPIO_L26,
+ EXYNOS4X12_GPIO_L27,
+ EXYNOS4X12_GPIO_Y00, /* 232 0xE8 */
+ EXYNOS4X12_GPIO_Y01,
+ EXYNOS4X12_GPIO_Y02,
+ EXYNOS4X12_GPIO_Y03,
+ EXYNOS4X12_GPIO_Y04,
+ EXYNOS4X12_GPIO_Y05,
+ EXYNOS4X12_GPIO_Y06,
+ EXYNOS4X12_GPIO_Y07,
+ EXYNOS4X12_GPIO_Y10, /* 240 0xF0 */
+ EXYNOS4X12_GPIO_Y11,
+ EXYNOS4X12_GPIO_Y12,
+ EXYNOS4X12_GPIO_Y13,
+ EXYNOS4X12_GPIO_Y14,
+ EXYNOS4X12_GPIO_Y15,
+ EXYNOS4X12_GPIO_Y16,
+ EXYNOS4X12_GPIO_Y17,
+ EXYNOS4X12_GPIO_Y20, /* 248 0xF8 */
+ EXYNOS4X12_GPIO_Y21,
+ EXYNOS4X12_GPIO_Y22,
+ EXYNOS4X12_GPIO_Y23,
+ EXYNOS4X12_GPIO_Y24,
+ EXYNOS4X12_GPIO_Y25,
+ EXYNOS4X12_GPIO_Y26,
+ EXYNOS4X12_GPIO_Y27,
+ EXYNOS4X12_GPIO_Y30, /* 256 0x100 */
+ EXYNOS4X12_GPIO_Y31,
+ EXYNOS4X12_GPIO_Y32,
+ EXYNOS4X12_GPIO_Y33,
+ EXYNOS4X12_GPIO_Y34,
+ EXYNOS4X12_GPIO_Y35,
+ EXYNOS4X12_GPIO_Y36,
+ EXYNOS4X12_GPIO_Y37,
+ EXYNOS4X12_GPIO_Y40, /* 264 0x108 */
+ EXYNOS4X12_GPIO_Y41,
+ EXYNOS4X12_GPIO_Y42,
+ EXYNOS4X12_GPIO_Y43,
+ EXYNOS4X12_GPIO_Y44,
+ EXYNOS4X12_GPIO_Y45,
+ EXYNOS4X12_GPIO_Y46,
+ EXYNOS4X12_GPIO_Y47,
+ EXYNOS4X12_GPIO_Y50, /* 272 0x110 */
+ EXYNOS4X12_GPIO_Y51,
+ EXYNOS4X12_GPIO_Y52,
+ EXYNOS4X12_GPIO_Y53,
+ EXYNOS4X12_GPIO_Y54,
+ EXYNOS4X12_GPIO_Y55,
+ EXYNOS4X12_GPIO_Y56,
+ EXYNOS4X12_GPIO_Y57,
+ EXYNOS4X12_GPIO_Y60, /* 280 0x118 */
+ EXYNOS4X12_GPIO_Y61,
+ EXYNOS4X12_GPIO_Y62,
+ EXYNOS4X12_GPIO_Y63,
+ EXYNOS4X12_GPIO_Y64,
+ EXYNOS4X12_GPIO_Y65,
+ EXYNOS4X12_GPIO_Y66,
+ EXYNOS4X12_GPIO_Y67,
+ EXYNOS4X12_GPIO_M00 = 312, /* 312 0xF0 */
+ EXYNOS4X12_GPIO_M01,
+ EXYNOS4X12_GPIO_M02,
+ EXYNOS4X12_GPIO_M03,
+ EXYNOS4X12_GPIO_M04,
+ EXYNOS4X12_GPIO_M05,
+ EXYNOS4X12_GPIO_M06,
+ EXYNOS4X12_GPIO_M07,
+ EXYNOS4X12_GPIO_M10, /* 320 0xF8 */
+ EXYNOS4X12_GPIO_M11,
+ EXYNOS4X12_GPIO_M12,
+ EXYNOS4X12_GPIO_M13,
+ EXYNOS4X12_GPIO_M14,
+ EXYNOS4X12_GPIO_M15,
+ EXYNOS4X12_GPIO_M16,
+ EXYNOS4X12_GPIO_M17,
+ EXYNOS4X12_GPIO_M20, /* 328 0x100 */
+ EXYNOS4X12_GPIO_M21,
+ EXYNOS4X12_GPIO_M22,
+ EXYNOS4X12_GPIO_M23,
+ EXYNOS4X12_GPIO_M24,
+ EXYNOS4X12_GPIO_M25,
+ EXYNOS4X12_GPIO_M26,
+ EXYNOS4X12_GPIO_M27,
+ EXYNOS4X12_GPIO_M30, /* 336 0x108 */
+ EXYNOS4X12_GPIO_M31,
+ EXYNOS4X12_GPIO_M32,
+ EXYNOS4X12_GPIO_M33,
+ EXYNOS4X12_GPIO_M34,
+ EXYNOS4X12_GPIO_M35,
+ EXYNOS4X12_GPIO_M36,
+ EXYNOS4X12_GPIO_M37,
+ EXYNOS4X12_GPIO_M40, /* 344 0x110 */
+ EXYNOS4X12_GPIO_M41,
+ EXYNOS4X12_GPIO_M42,
+ EXYNOS4X12_GPIO_M43,
+ EXYNOS4X12_GPIO_M44,
+ EXYNOS4X12_GPIO_M45,
+ EXYNOS4X12_GPIO_M46,
+ EXYNOS4X12_GPIO_M47,
+ EXYNOS4X12_GPIO_X00 = 928, /* 928 0x3A0 */
+ EXYNOS4X12_GPIO_X01,
+ EXYNOS4X12_GPIO_X02,
+ EXYNOS4X12_GPIO_X03,
+ EXYNOS4X12_GPIO_X04,
+ EXYNOS4X12_GPIO_X05,
+ EXYNOS4X12_GPIO_X06,
+ EXYNOS4X12_GPIO_X07,
+ EXYNOS4X12_GPIO_X10, /* 936 0x3A8 */
+ EXYNOS4X12_GPIO_X11,
+ EXYNOS4X12_GPIO_X12,
+ EXYNOS4X12_GPIO_X13,
+ EXYNOS4X12_GPIO_X14,
+ EXYNOS4X12_GPIO_X15,
+ EXYNOS4X12_GPIO_X16,
+ EXYNOS4X12_GPIO_X17,
+ EXYNOS4X12_GPIO_X20, /* 944 0x3B0 */
+ EXYNOS4X12_GPIO_X21,
+ EXYNOS4X12_GPIO_X22,
+ EXYNOS4X12_GPIO_X23,
+ EXYNOS4X12_GPIO_X24,
+ EXYNOS4X12_GPIO_X25,
+ EXYNOS4X12_GPIO_X26,
+ EXYNOS4X12_GPIO_X27,
+ EXYNOS4X12_GPIO_X30, /* 952 0x3B8 */
+ EXYNOS4X12_GPIO_X31,
+ EXYNOS4X12_GPIO_X32,
+ EXYNOS4X12_GPIO_X33,
+ EXYNOS4X12_GPIO_X34,
+ EXYNOS4X12_GPIO_X35,
+ EXYNOS4X12_GPIO_X36,
+ EXYNOS4X12_GPIO_X37,
+
+ /* GPIO_PART3_STARTS */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 960 0x3C0 */
+ EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2,
+ EXYNOS4X12_GPIO_Z1,
+ EXYNOS4X12_GPIO_Z2,
+ EXYNOS4X12_GPIO_Z3,
+ EXYNOS4X12_GPIO_Z4,
+ EXYNOS4X12_GPIO_Z5,
+ EXYNOS4X12_GPIO_Z6,
+ EXYNOS4X12_GPIO_Z7,
+
+ /* GPIO_PART4_STARTS */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 968 0x3C8 */
+ EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3,
+ EXYNOS4X12_GPIO_V01,
+ EXYNOS4X12_GPIO_V02,
+ EXYNOS4X12_GPIO_V03,
+ EXYNOS4X12_GPIO_V04,
+ EXYNOS4X12_GPIO_V05,
+ EXYNOS4X12_GPIO_V06,
+ EXYNOS4X12_GPIO_V07,
+ EXYNOS4X12_GPIO_V10, /* 976 0x3D0 */
+ EXYNOS4X12_GPIO_V11,
+ EXYNOS4X12_GPIO_V12,
+ EXYNOS4X12_GPIO_V13,
+ EXYNOS4X12_GPIO_V14,
+ EXYNOS4X12_GPIO_V15,
+ EXYNOS4X12_GPIO_V16,
+ EXYNOS4X12_GPIO_V17,
+ EXYNOS4X12_GPIO_V20 = 992, /* 992 0x3E0 */
+ EXYNOS4X12_GPIO_V21,
+ EXYNOS4X12_GPIO_V22,
+ EXYNOS4X12_GPIO_V23,
+ EXYNOS4X12_GPIO_V24,
+ EXYNOS4X12_GPIO_V25,
+ EXYNOS4X12_GPIO_V26,
+ EXYNOS4X12_GPIO_V27,
+ EXYNOS4X12_GPIO_V30 = 1000, /* 1000 0x3E8 */
+ EXYNOS4X12_GPIO_V31,
+ EXYNOS4X12_GPIO_V32,
+ EXYNOS4X12_GPIO_V33,
+ EXYNOS4X12_GPIO_V34,
+ EXYNOS4X12_GPIO_V35,
+ EXYNOS4X12_GPIO_V36,
+ EXYNOS4X12_GPIO_V37,
+ EXYNOS4X12_GPIO_V40 = 1016, /* 1016 0x3F8 */
+ EXYNOS4X12_GPIO_V41,
+ EXYNOS4X12_GPIO_V42,
+ EXYNOS4X12_GPIO_V43,
+ EXYNOS4X12_GPIO_V44,
+ EXYNOS4X12_GPIO_V45,
+ EXYNOS4X12_GPIO_V46,
+ EXYNOS4X12_GPIO_V47,
+
+ EXYNOS4X12_GPIO_MAX_PORT
};
-struct exynos4x12_gpio_part3 {
- struct s5p_gpio_bank z;
+enum exynos5_gpio_pin {
+ /* GPIO_PART1_STARTS */
+ EXYNOS5_GPIO_A00, /* 0 */
+ EXYNOS5_GPIO_A01,
+ EXYNOS5_GPIO_A02,
+ EXYNOS5_GPIO_A03,
+ EXYNOS5_GPIO_A04,
+ EXYNOS5_GPIO_A05,
+ EXYNOS5_GPIO_A06,
+ EXYNOS5_GPIO_A07,
+ EXYNOS5_GPIO_A10, /* 8 */
+ EXYNOS5_GPIO_A11,
+ EXYNOS5_GPIO_A12,
+ EXYNOS5_GPIO_A13,
+ EXYNOS5_GPIO_A14,
+ EXYNOS5_GPIO_A15,
+ EXYNOS5_GPIO_A16,
+ EXYNOS5_GPIO_A17,
+ EXYNOS5_GPIO_A20, /* 16 0x10 */
+ EXYNOS5_GPIO_A21,
+ EXYNOS5_GPIO_A22,
+ EXYNOS5_GPIO_A23,
+ EXYNOS5_GPIO_A24,
+ EXYNOS5_GPIO_A25,
+ EXYNOS5_GPIO_A26,
+ EXYNOS5_GPIO_A27,
+ EXYNOS5_GPIO_B00, /* 24 0x18 */
+ EXYNOS5_GPIO_B01,
+ EXYNOS5_GPIO_B02,
+ EXYNOS5_GPIO_B03,
+ EXYNOS5_GPIO_B04,
+ EXYNOS5_GPIO_B05,
+ EXYNOS5_GPIO_B06,
+ EXYNOS5_GPIO_B07,
+ EXYNOS5_GPIO_B10, /* 32 0x20 */
+ EXYNOS5_GPIO_B11,
+ EXYNOS5_GPIO_B12,
+ EXYNOS5_GPIO_B13,
+ EXYNOS5_GPIO_B14,
+ EXYNOS5_GPIO_B15,
+ EXYNOS5_GPIO_B16,
+ EXYNOS5_GPIO_B17,
+ EXYNOS5_GPIO_B20, /* 40 0x28 */
+ EXYNOS5_GPIO_B21,
+ EXYNOS5_GPIO_B22,
+ EXYNOS5_GPIO_B23,
+ EXYNOS5_GPIO_B24,
+ EXYNOS5_GPIO_B25,
+ EXYNOS5_GPIO_B26,
+ EXYNOS5_GPIO_B27,
+ EXYNOS5_GPIO_B30, /* 48 0x39 */
+ EXYNOS5_GPIO_B31,
+ EXYNOS5_GPIO_B32,
+ EXYNOS5_GPIO_B33,
+ EXYNOS5_GPIO_B34,
+ EXYNOS5_GPIO_B35,
+ EXYNOS5_GPIO_B36,
+ EXYNOS5_GPIO_B37,
+ EXYNOS5_GPIO_C00, /* 56 0x38 */
+ EXYNOS5_GPIO_C01,
+ EXYNOS5_GPIO_C02,
+ EXYNOS5_GPIO_C03,
+ EXYNOS5_GPIO_C04,
+ EXYNOS5_GPIO_C05,
+ EXYNOS5_GPIO_C06,
+ EXYNOS5_GPIO_C07,
+ EXYNOS5_GPIO_C10, /* 64 0x40 */
+ EXYNOS5_GPIO_C11,
+ EXYNOS5_GPIO_C12,
+ EXYNOS5_GPIO_C13,
+ EXYNOS5_GPIO_C14,
+ EXYNOS5_GPIO_C15,
+ EXYNOS5_GPIO_C16,
+ EXYNOS5_GPIO_C17,
+ EXYNOS5_GPIO_C20, /* 72 0x48 */
+ EXYNOS5_GPIO_C21,
+ EXYNOS5_GPIO_C22,
+ EXYNOS5_GPIO_C23,
+ EXYNOS5_GPIO_C24,
+ EXYNOS5_GPIO_C25,
+ EXYNOS5_GPIO_C26,
+ EXYNOS5_GPIO_C27,
+ EXYNOS5_GPIO_C30, /* 80 0x50 */
+ EXYNOS5_GPIO_C31,
+ EXYNOS5_GPIO_C32,
+ EXYNOS5_GPIO_C33,
+ EXYNOS5_GPIO_C34,
+ EXYNOS5_GPIO_C35,
+ EXYNOS5_GPIO_C36,
+ EXYNOS5_GPIO_C37,
+ EXYNOS5_GPIO_D00, /* 88 0x58 */
+ EXYNOS5_GPIO_D01,
+ EXYNOS5_GPIO_D02,
+ EXYNOS5_GPIO_D03,
+ EXYNOS5_GPIO_D04,
+ EXYNOS5_GPIO_D05,
+ EXYNOS5_GPIO_D06,
+ EXYNOS5_GPIO_D07,
+ EXYNOS5_GPIO_D10, /* 96 0x60 */
+ EXYNOS5_GPIO_D11,
+ EXYNOS5_GPIO_D12,
+ EXYNOS5_GPIO_D13,
+ EXYNOS5_GPIO_D14,
+ EXYNOS5_GPIO_D15,
+ EXYNOS5_GPIO_D16,
+ EXYNOS5_GPIO_D17,
+ EXYNOS5_GPIO_Y00, /* 104 0x68 */
+ EXYNOS5_GPIO_Y01,
+ EXYNOS5_GPIO_Y02,
+ EXYNOS5_GPIO_Y03,
+ EXYNOS5_GPIO_Y04,
+ EXYNOS5_GPIO_Y05,
+ EXYNOS5_GPIO_Y06,
+ EXYNOS5_GPIO_Y07,
+ EXYNOS5_GPIO_Y10, /* 112 0x70 */
+ EXYNOS5_GPIO_Y11,
+ EXYNOS5_GPIO_Y12,
+ EXYNOS5_GPIO_Y13,
+ EXYNOS5_GPIO_Y14,
+ EXYNOS5_GPIO_Y15,
+ EXYNOS5_GPIO_Y16,
+ EXYNOS5_GPIO_Y17,
+ EXYNOS5_GPIO_Y20, /* 120 0x78 */
+ EXYNOS5_GPIO_Y21,
+ EXYNOS5_GPIO_Y22,
+ EXYNOS5_GPIO_Y23,
+ EXYNOS5_GPIO_Y24,
+ EXYNOS5_GPIO_Y25,
+ EXYNOS5_GPIO_Y26,
+ EXYNOS5_GPIO_Y27,
+ EXYNOS5_GPIO_Y30, /* 128 0x80 */
+ EXYNOS5_GPIO_Y31,
+ EXYNOS5_GPIO_Y32,
+ EXYNOS5_GPIO_Y33,
+ EXYNOS5_GPIO_Y34,
+ EXYNOS5_GPIO_Y35,
+ EXYNOS5_GPIO_Y36,
+ EXYNOS5_GPIO_Y37,
+ EXYNOS5_GPIO_Y40, /* 136 0x88 */
+ EXYNOS5_GPIO_Y41,
+ EXYNOS5_GPIO_Y42,
+ EXYNOS5_GPIO_Y43,
+ EXYNOS5_GPIO_Y44,
+ EXYNOS5_GPIO_Y45,
+ EXYNOS5_GPIO_Y46,
+ EXYNOS5_GPIO_Y47,
+ EXYNOS5_GPIO_Y50, /* 144 0x90 */
+ EXYNOS5_GPIO_Y51,
+ EXYNOS5_GPIO_Y52,
+ EXYNOS5_GPIO_Y53,
+ EXYNOS5_GPIO_Y54,
+ EXYNOS5_GPIO_Y55,
+ EXYNOS5_GPIO_Y56,
+ EXYNOS5_GPIO_Y57,
+ EXYNOS5_GPIO_Y60, /* 152 0x98 */
+ EXYNOS5_GPIO_Y61,
+ EXYNOS5_GPIO_Y62,
+ EXYNOS5_GPIO_Y63,
+ EXYNOS5_GPIO_Y64,
+ EXYNOS5_GPIO_Y65,
+ EXYNOS5_GPIO_Y66,
+ EXYNOS5_GPIO_Y67,
+
+ /* GPIO_PART2_STARTS */
+ EXYNOS5_GPIO_MAX_PORT_PART_1, /* 160 0xa0 */
+ EXYNOS5_GPIO_C40 = EXYNOS5_GPIO_MAX_PORT_PART_1,
+ EXYNOS5_GPIO_C41,
+ EXYNOS5_GPIO_C42,
+ EXYNOS5_GPIO_C43,
+ EXYNOS5_GPIO_C44,
+ EXYNOS5_GPIO_C45,
+ EXYNOS5_GPIO_C46,
+ EXYNOS5_GPIO_C47,
+
+ /* GPIO_PART3_STARTS */
+ EXYNOS5_GPIO_MAX_PORT_PART_2, /* 168 0xa8 */
+ EXYNOS5_GPIO_X00 = EXYNOS5_GPIO_MAX_PORT_PART_2,
+ EXYNOS5_GPIO_X01,
+ EXYNOS5_GPIO_X02,
+ EXYNOS5_GPIO_X03,
+ EXYNOS5_GPIO_X04,
+ EXYNOS5_GPIO_X05,
+ EXYNOS5_GPIO_X06,
+ EXYNOS5_GPIO_X07,
+ EXYNOS5_GPIO_X10, /* 176 0xb0 */
+ EXYNOS5_GPIO_X11,
+ EXYNOS5_GPIO_X12,
+ EXYNOS5_GPIO_X13,
+ EXYNOS5_GPIO_X14,
+ EXYNOS5_GPIO_X15,
+ EXYNOS5_GPIO_X16,
+ EXYNOS5_GPIO_X17,
+ EXYNOS5_GPIO_X20, /* 184 0xb8 */
+ EXYNOS5_GPIO_X21,
+ EXYNOS5_GPIO_X22,
+ EXYNOS5_GPIO_X23,
+ EXYNOS5_GPIO_X24,
+ EXYNOS5_GPIO_X25,
+ EXYNOS5_GPIO_X26,
+ EXYNOS5_GPIO_X27,
+ EXYNOS5_GPIO_X30, /* 192 0xc0 */
+ EXYNOS5_GPIO_X31,
+ EXYNOS5_GPIO_X32,
+ EXYNOS5_GPIO_X33,
+ EXYNOS5_GPIO_X34,
+ EXYNOS5_GPIO_X35,
+ EXYNOS5_GPIO_X36,
+ EXYNOS5_GPIO_X37,
+
+ /* GPIO_PART4_STARTS */
+ EXYNOS5_GPIO_MAX_PORT_PART_3, /* 200 0xc8 */
+ EXYNOS5_GPIO_E00 = EXYNOS5_GPIO_MAX_PORT_PART_3,
+ EXYNOS5_GPIO_E01,
+ EXYNOS5_GPIO_E02,
+ EXYNOS5_GPIO_E03,
+ EXYNOS5_GPIO_E04,
+ EXYNOS5_GPIO_E05,
+ EXYNOS5_GPIO_E06,
+ EXYNOS5_GPIO_E07,
+ EXYNOS5_GPIO_E10, /* 208 0xd0 */
+ EXYNOS5_GPIO_E11,
+ EXYNOS5_GPIO_E12,
+ EXYNOS5_GPIO_E13,
+ EXYNOS5_GPIO_E14,
+ EXYNOS5_GPIO_E15,
+ EXYNOS5_GPIO_E16,
+ EXYNOS5_GPIO_E17,
+ EXYNOS5_GPIO_F00, /* 216 0xd8 */
+ EXYNOS5_GPIO_F01,
+ EXYNOS5_GPIO_F02,
+ EXYNOS5_GPIO_F03,
+ EXYNOS5_GPIO_F04,
+ EXYNOS5_GPIO_F05,
+ EXYNOS5_GPIO_F06,
+ EXYNOS5_GPIO_F07,
+ EXYNOS5_GPIO_F10, /* 224 0xe0 */
+ EXYNOS5_GPIO_F11,
+ EXYNOS5_GPIO_F12,
+ EXYNOS5_GPIO_F13,
+ EXYNOS5_GPIO_F14,
+ EXYNOS5_GPIO_F15,
+ EXYNOS5_GPIO_F16,
+ EXYNOS5_GPIO_F17,
+ EXYNOS5_GPIO_G00, /* 232 0xe8 */
+ EXYNOS5_GPIO_G01,
+ EXYNOS5_GPIO_G02,
+ EXYNOS5_GPIO_G03,
+ EXYNOS5_GPIO_G04,
+ EXYNOS5_GPIO_G05,
+ EXYNOS5_GPIO_G06,
+ EXYNOS5_GPIO_G07,
+ EXYNOS5_GPIO_G10, /* 240 0xf0 */
+ EXYNOS5_GPIO_G11,
+ EXYNOS5_GPIO_G12,
+ EXYNOS5_GPIO_G13,
+ EXYNOS5_GPIO_G14,
+ EXYNOS5_GPIO_G15,
+ EXYNOS5_GPIO_G16,
+ EXYNOS5_GPIO_G17,
+ EXYNOS5_GPIO_G20, /* 248 0xf8 */
+ EXYNOS5_GPIO_G21,
+ EXYNOS5_GPIO_G22,
+ EXYNOS5_GPIO_G23,
+ EXYNOS5_GPIO_G24,
+ EXYNOS5_GPIO_G25,
+ EXYNOS5_GPIO_G26,
+ EXYNOS5_GPIO_G27,
+ EXYNOS5_GPIO_H00, /* 256 0x100 */
+ EXYNOS5_GPIO_H01,
+ EXYNOS5_GPIO_H02,
+ EXYNOS5_GPIO_H03,
+ EXYNOS5_GPIO_H04,
+ EXYNOS5_GPIO_H05,
+ EXYNOS5_GPIO_H06,
+ EXYNOS5_GPIO_H07,
+ EXYNOS5_GPIO_H10, /* 264 0x108 */
+ EXYNOS5_GPIO_H11,
+ EXYNOS5_GPIO_H12,
+ EXYNOS5_GPIO_H13,
+ EXYNOS5_GPIO_H14,
+ EXYNOS5_GPIO_H15,
+ EXYNOS5_GPIO_H16,
+ EXYNOS5_GPIO_H17,
+
+ /* GPIO_PART4_STARTS */
+ EXYNOS5_GPIO_MAX_PORT_PART_4, /* 272 0x110 */
+ EXYNOS5_GPIO_V00 = EXYNOS5_GPIO_MAX_PORT_PART_4,
+ EXYNOS5_GPIO_V01,
+ EXYNOS5_GPIO_V02,
+ EXYNOS5_GPIO_V03,
+ EXYNOS5_GPIO_V04,
+ EXYNOS5_GPIO_V05,
+ EXYNOS5_GPIO_V06,
+ EXYNOS5_GPIO_V07,
+ EXYNOS5_GPIO_V10, /* 280 0x118 */
+ EXYNOS5_GPIO_V11,
+ EXYNOS5_GPIO_V12,
+ EXYNOS5_GPIO_V13,
+ EXYNOS5_GPIO_V14,
+ EXYNOS5_GPIO_V15,
+ EXYNOS5_GPIO_V16,
+ EXYNOS5_GPIO_V17,
+
+ /* GPIO_PART5_STARTS */
+ EXYNOS5_GPIO_MAX_PORT_PART_5, /* 288 0x120 */
+ EXYNOS5_GPIO_V20 = EXYNOS5_GPIO_MAX_PORT_PART_5,
+ EXYNOS5_GPIO_V21,
+ EXYNOS5_GPIO_V22,
+ EXYNOS5_GPIO_V23,
+ EXYNOS5_GPIO_V24,
+ EXYNOS5_GPIO_V25,
+ EXYNOS5_GPIO_V26,
+ EXYNOS5_GPIO_V27,
+ EXYNOS5_GPIO_V30, /* 296 0x128 */
+ EXYNOS5_GPIO_V31,
+ EXYNOS5_GPIO_V32,
+ EXYNOS5_GPIO_V33,
+ EXYNOS5_GPIO_V34,
+ EXYNOS5_GPIO_V35,
+ EXYNOS5_GPIO_V36,
+ EXYNOS5_GPIO_V37,
+
+ /* GPIO_PART6_STARTS */
+ EXYNOS5_GPIO_MAX_PORT_PART_6, /* 304 0x130 */
+ EXYNOS5_GPIO_V40 = EXYNOS5_GPIO_MAX_PORT_PART_6,
+ EXYNOS5_GPIO_V41,
+ EXYNOS5_GPIO_V42,
+ EXYNOS5_GPIO_V43,
+ EXYNOS5_GPIO_V44,
+ EXYNOS5_GPIO_V45,
+ EXYNOS5_GPIO_V46,
+ EXYNOS5_GPIO_V47,
+
+ /* GPIO_PART7_STARTS */ /* 312 0x138 */
+ EXYNOS5_GPIO_MAX_PORT_PART_7,
+ EXYNOS5_GPIO_Z0 = EXYNOS5_GPIO_MAX_PORT_PART_7,
+ EXYNOS5_GPIO_Z1,
+ EXYNOS5_GPIO_Z2,
+ EXYNOS5_GPIO_Z3,
+ EXYNOS5_GPIO_Z4,
+ EXYNOS5_GPIO_Z5,
+ EXYNOS5_GPIO_Z6,
+ EXYNOS5_GPIO_MAX_PORT
};
-struct exynos4x12_gpio_part4 {
- struct s5p_gpio_bank v0;
- struct s5p_gpio_bank v1;
- struct s5p_gpio_bank res1[0x1];
- struct s5p_gpio_bank v2;
- struct s5p_gpio_bank v3;
- struct s5p_gpio_bank res2[0x1];
- struct s5p_gpio_bank v4;
+enum exynos5420_gpio_pin {
+ /* GPIO_PART1_STARTS */
+ EXYNOS5420_GPIO_A00, /* 0 */
+ EXYNOS5420_GPIO_A01,
+ EXYNOS5420_GPIO_A02,
+ EXYNOS5420_GPIO_A03,
+ EXYNOS5420_GPIO_A04,
+ EXYNOS5420_GPIO_A05,
+ EXYNOS5420_GPIO_A06,
+ EXYNOS5420_GPIO_A07,
+ EXYNOS5420_GPIO_A10, /* 8 */
+ EXYNOS5420_GPIO_A11,
+ EXYNOS5420_GPIO_A12,
+ EXYNOS5420_GPIO_A13,
+ EXYNOS5420_GPIO_A14,
+ EXYNOS5420_GPIO_A15,
+ EXYNOS5420_GPIO_A16,
+ EXYNOS5420_GPIO_A17,
+ EXYNOS5420_GPIO_A20, /* 16 0x10 */
+ EXYNOS5420_GPIO_A21,
+ EXYNOS5420_GPIO_A22,
+ EXYNOS5420_GPIO_A23,
+ EXYNOS5420_GPIO_A24,
+ EXYNOS5420_GPIO_A25,
+ EXYNOS5420_GPIO_A26,
+ EXYNOS5420_GPIO_A27,
+ EXYNOS5420_GPIO_B00, /* 24 0x18 */
+ EXYNOS5420_GPIO_B01,
+ EXYNOS5420_GPIO_B02,
+ EXYNOS5420_GPIO_B03,
+ EXYNOS5420_GPIO_B04,
+ EXYNOS5420_GPIO_B05,
+ EXYNOS5420_GPIO_B06,
+ EXYNOS5420_GPIO_B07,
+ EXYNOS5420_GPIO_B10, /* 32 0x20 */
+ EXYNOS5420_GPIO_B11,
+ EXYNOS5420_GPIO_B12,
+ EXYNOS5420_GPIO_B13,
+ EXYNOS5420_GPIO_B14,
+ EXYNOS5420_GPIO_B15,
+ EXYNOS5420_GPIO_B16,
+ EXYNOS5420_GPIO_B17,
+ EXYNOS5420_GPIO_B20, /* 40 0x28 */
+ EXYNOS5420_GPIO_B21,
+ EXYNOS5420_GPIO_B22,
+ EXYNOS5420_GPIO_B23,
+ EXYNOS5420_GPIO_B24,
+ EXYNOS5420_GPIO_B25,
+ EXYNOS5420_GPIO_B26,
+ EXYNOS5420_GPIO_B27,
+ EXYNOS5420_GPIO_B30, /* 48 0x30 */
+ EXYNOS5420_GPIO_B31,
+ EXYNOS5420_GPIO_B32,
+ EXYNOS5420_GPIO_B33,
+ EXYNOS5420_GPIO_B34,
+ EXYNOS5420_GPIO_B35,
+ EXYNOS5420_GPIO_B36,
+ EXYNOS5420_GPIO_B37,
+ EXYNOS5420_GPIO_B40, /* 56 0x38 */
+ EXYNOS5420_GPIO_B41,
+ EXYNOS5420_GPIO_B42,
+ EXYNOS5420_GPIO_B43,
+ EXYNOS5420_GPIO_B44,
+ EXYNOS5420_GPIO_B45,
+ EXYNOS5420_GPIO_B46,
+ EXYNOS5420_GPIO_B47,
+ EXYNOS5420_GPIO_H00, /* 64 0x40 */
+ EXYNOS5420_GPIO_H01,
+ EXYNOS5420_GPIO_H02,
+ EXYNOS5420_GPIO_H03,
+ EXYNOS5420_GPIO_H04,
+ EXYNOS5420_GPIO_H05,
+ EXYNOS5420_GPIO_H06,
+ EXYNOS5420_GPIO_H07,
+
+ /* GPIO PART 2 STARTS*/
+ EXYNOS5420_GPIO_MAX_PORT_PART_1,/* 72 0x48 */
+ EXYNOS5420_GPIO_Y70 = EXYNOS5420_GPIO_MAX_PORT_PART_1,
+ EXYNOS5420_GPIO_Y71,
+ EXYNOS5420_GPIO_Y72,
+ EXYNOS5420_GPIO_Y73,
+ EXYNOS5420_GPIO_Y74,
+ EXYNOS5420_GPIO_Y75,
+ EXYNOS5420_GPIO_Y76,
+ EXYNOS5420_GPIO_Y77,
+
+ /* GPIO PART 3 STARTS*/
+ EXYNOS5420_GPIO_MAX_PORT_PART_2,/* 80 0x50 */
+ EXYNOS5420_GPIO_X00 = EXYNOS5420_GPIO_MAX_PORT_PART_2,
+ EXYNOS5420_GPIO_X01,
+ EXYNOS5420_GPIO_X02,
+ EXYNOS5420_GPIO_X03,
+ EXYNOS5420_GPIO_X04,
+ EXYNOS5420_GPIO_X05,
+ EXYNOS5420_GPIO_X06,
+ EXYNOS5420_GPIO_X07,
+ EXYNOS5420_GPIO_X10, /* 88 0x58 */
+ EXYNOS5420_GPIO_X11,
+ EXYNOS5420_GPIO_X12,
+ EXYNOS5420_GPIO_X13,
+ EXYNOS5420_GPIO_X14,
+ EXYNOS5420_GPIO_X15,
+ EXYNOS5420_GPIO_X16,
+ EXYNOS5420_GPIO_X17,
+ EXYNOS5420_GPIO_X20, /* 96 0x60 */
+ EXYNOS5420_GPIO_X21,
+ EXYNOS5420_GPIO_X22,
+ EXYNOS5420_GPIO_X23,
+ EXYNOS5420_GPIO_X24,
+ EXYNOS5420_GPIO_X25,
+ EXYNOS5420_GPIO_X26,
+ EXYNOS5420_GPIO_X27,
+ EXYNOS5420_GPIO_X30, /* 104 0x68 */
+ EXYNOS5420_GPIO_X31,
+ EXYNOS5420_GPIO_X32,
+ EXYNOS5420_GPIO_X33,
+ EXYNOS5420_GPIO_X34,
+ EXYNOS5420_GPIO_X35,
+ EXYNOS5420_GPIO_X36,
+ EXYNOS5420_GPIO_X37,
+
+ /* GPIO PART 4 STARTS*/
+ EXYNOS5420_GPIO_MAX_PORT_PART_3,/* 112 0x70 */
+ EXYNOS5420_GPIO_C00 = EXYNOS5420_GPIO_MAX_PORT_PART_3,
+ EXYNOS5420_GPIO_C01,
+ EXYNOS5420_GPIO_C02,
+ EXYNOS5420_GPIO_C03,
+ EXYNOS5420_GPIO_C04,
+ EXYNOS5420_GPIO_C05,
+ EXYNOS5420_GPIO_C06,
+ EXYNOS5420_GPIO_C07,
+ EXYNOS5420_GPIO_C10, /* 120 0x78 */
+ EXYNOS5420_GPIO_C11,
+ EXYNOS5420_GPIO_C12,
+ EXYNOS5420_GPIO_C13,
+ EXYNOS5420_GPIO_C14,
+ EXYNOS5420_GPIO_C15,
+ EXYNOS5420_GPIO_C16,
+ EXYNOS5420_GPIO_C17,
+ EXYNOS5420_GPIO_C20, /* 128 0x80 */
+ EXYNOS5420_GPIO_C21,
+ EXYNOS5420_GPIO_C22,
+ EXYNOS5420_GPIO_C23,
+ EXYNOS5420_GPIO_C24,
+ EXYNOS5420_GPIO_C25,
+ EXYNOS5420_GPIO_C26,
+ EXYNOS5420_GPIO_C27,
+ EXYNOS5420_GPIO_C30, /* 136 0x88 */
+ EXYNOS5420_GPIO_C31,
+ EXYNOS5420_GPIO_C32,
+ EXYNOS5420_GPIO_C33,
+ EXYNOS5420_GPIO_C34,
+ EXYNOS5420_GPIO_C35,
+ EXYNOS5420_GPIO_C36,
+ EXYNOS5420_GPIO_C37,
+ EXYNOS5420_GPIO_C40, /* 144 0x90 */
+ EXYNOS5420_GPIO_C41,
+ EXYNOS5420_GPIO_C42,
+ EXYNOS5420_GPIO_C43,
+ EXYNOS5420_GPIO_C44,
+ EXYNOS5420_GPIO_C45,
+ EXYNOS5420_GPIO_C46,
+ EXYNOS5420_GPIO_C47,
+ EXYNOS5420_GPIO_D10, /* 152 0x98 */
+ EXYNOS5420_GPIO_D11,
+ EXYNOS5420_GPIO_D12,
+ EXYNOS5420_GPIO_D13,
+ EXYNOS5420_GPIO_D14,
+ EXYNOS5420_GPIO_D15,
+ EXYNOS5420_GPIO_D16,
+ EXYNOS5420_GPIO_D17,
+ EXYNOS5420_GPIO_Y00, /* 160 0xa0 */
+ EXYNOS5420_GPIO_Y01,
+ EXYNOS5420_GPIO_Y02,
+ EXYNOS5420_GPIO_Y03,
+ EXYNOS5420_GPIO_Y04,
+ EXYNOS5420_GPIO_Y05,
+ EXYNOS5420_GPIO_Y06,
+ EXYNOS5420_GPIO_Y07,
+ EXYNOS5420_GPIO_Y10, /* 168 0xa8 */
+ EXYNOS5420_GPIO_Y11,
+ EXYNOS5420_GPIO_Y12,
+ EXYNOS5420_GPIO_Y13,
+ EXYNOS5420_GPIO_Y14,
+ EXYNOS5420_GPIO_Y15,
+ EXYNOS5420_GPIO_Y16,
+ EXYNOS5420_GPIO_Y17,
+ EXYNOS5420_GPIO_Y20, /* 176 0xb0 */
+ EXYNOS5420_GPIO_Y21,
+ EXYNOS5420_GPIO_Y22,
+ EXYNOS5420_GPIO_Y23,
+ EXYNOS5420_GPIO_Y24,
+ EXYNOS5420_GPIO_Y25,
+ EXYNOS5420_GPIO_Y26,
+ EXYNOS5420_GPIO_Y27,
+ EXYNOS5420_GPIO_Y30, /* 184 0xb8 */
+ EXYNOS5420_GPIO_Y31,
+ EXYNOS5420_GPIO_Y32,
+ EXYNOS5420_GPIO_Y33,
+ EXYNOS5420_GPIO_Y34,
+ EXYNOS5420_GPIO_Y35,
+ EXYNOS5420_GPIO_Y36,
+ EXYNOS5420_GPIO_Y37,
+ EXYNOS5420_GPIO_Y40, /* 192 0xc0 */
+ EXYNOS5420_GPIO_Y41,
+ EXYNOS5420_GPIO_Y42,
+ EXYNOS5420_GPIO_Y43,
+ EXYNOS5420_GPIO_Y44,
+ EXYNOS5420_GPIO_Y45,
+ EXYNOS5420_GPIO_Y46,
+ EXYNOS5420_GPIO_Y47,
+ EXYNOS5420_GPIO_Y50, /* 200 0xc8 */
+ EXYNOS5420_GPIO_Y51,
+ EXYNOS5420_GPIO_Y52,
+ EXYNOS5420_GPIO_Y53,
+ EXYNOS5420_GPIO_Y54,
+ EXYNOS5420_GPIO_Y55,
+ EXYNOS5420_GPIO_Y56,
+ EXYNOS5420_GPIO_Y57,
+ EXYNOS5420_GPIO_Y60, /* 208 0xd0 */
+ EXYNOS5420_GPIO_Y61,
+ EXYNOS5420_GPIO_Y62,
+ EXYNOS5420_GPIO_Y63,
+ EXYNOS5420_GPIO_Y64,
+ EXYNOS5420_GPIO_Y65,
+ EXYNOS5420_GPIO_Y66,
+ EXYNOS5420_GPIO_Y67,
+
+ /* GPIO_PART5_STARTS */
+ EXYNOS5420_GPIO_MAX_PORT_PART_4,/* 216 0xd8 */
+ EXYNOS5420_GPIO_E00 = EXYNOS5420_GPIO_MAX_PORT_PART_4,
+ EXYNOS5420_GPIO_E01,
+ EXYNOS5420_GPIO_E02,
+ EXYNOS5420_GPIO_E03,
+ EXYNOS5420_GPIO_E04,
+ EXYNOS5420_GPIO_E05,
+ EXYNOS5420_GPIO_E06,
+ EXYNOS5420_GPIO_E07,
+ EXYNOS5420_GPIO_E10, /* 224 0xe0 */
+ EXYNOS5420_GPIO_E11,
+ EXYNOS5420_GPIO_E12,
+ EXYNOS5420_GPIO_E13,
+ EXYNOS5420_GPIO_E14,
+ EXYNOS5420_GPIO_E15,
+ EXYNOS5420_GPIO_E16,
+ EXYNOS5420_GPIO_E17,
+ EXYNOS5420_GPIO_F00, /* 232 0xe8 */
+ EXYNOS5420_GPIO_F01,
+ EXYNOS5420_GPIO_F02,
+ EXYNOS5420_GPIO_F03,
+ EXYNOS5420_GPIO_F04,
+ EXYNOS5420_GPIO_F05,
+ EXYNOS5420_GPIO_F06,
+ EXYNOS5420_GPIO_F07,
+ EXYNOS5420_GPIO_F10, /* 240 0xf0 */
+ EXYNOS5420_GPIO_F11,
+ EXYNOS5420_GPIO_F12,
+ EXYNOS5420_GPIO_F13,
+ EXYNOS5420_GPIO_F14,
+ EXYNOS5420_GPIO_F15,
+ EXYNOS5420_GPIO_F16,
+ EXYNOS5420_GPIO_F17,
+ EXYNOS5420_GPIO_G00, /* 248 0xf8 */
+ EXYNOS5420_GPIO_G01,
+ EXYNOS5420_GPIO_G02,
+ EXYNOS5420_GPIO_G03,
+ EXYNOS5420_GPIO_G04,
+ EXYNOS5420_GPIO_G05,
+ EXYNOS5420_GPIO_G06,
+ EXYNOS5420_GPIO_G07,
+ EXYNOS5420_GPIO_G10, /* 256 0x100 */
+ EXYNOS5420_GPIO_G11,
+ EXYNOS5420_GPIO_G12,
+ EXYNOS5420_GPIO_G13,
+ EXYNOS5420_GPIO_G14,
+ EXYNOS5420_GPIO_G15,
+ EXYNOS5420_GPIO_G16,
+ EXYNOS5420_GPIO_G17,
+ EXYNOS5420_GPIO_G20, /* 264 0x108 */
+ EXYNOS5420_GPIO_G21,
+ EXYNOS5420_GPIO_G22,
+ EXYNOS5420_GPIO_G23,
+ EXYNOS5420_GPIO_G24,
+ EXYNOS5420_GPIO_G25,
+ EXYNOS5420_GPIO_G26,
+ EXYNOS5420_GPIO_G27,
+ EXYNOS5420_GPIO_J40, /* 272 0x110 */
+ EXYNOS5420_GPIO_J41,
+ EXYNOS5420_GPIO_J42,
+ EXYNOS5420_GPIO_J43,
+ EXYNOS5420_GPIO_J44,
+ EXYNOS5420_GPIO_J45,
+ EXYNOS5420_GPIO_J46,
+ EXYNOS5420_GPIO_J47,
+
+ /* GPIO_PART6_STARTS */
+ EXYNOS5420_GPIO_MAX_PORT_PART_5,/* 280 0x118 */
+ EXYNOS5420_GPIO_Z0 = EXYNOS5420_GPIO_MAX_PORT_PART_5,
+ EXYNOS5420_GPIO_Z1,
+ EXYNOS5420_GPIO_Z2,
+ EXYNOS5420_GPIO_Z3,
+ EXYNOS5420_GPIO_Z4,
+ EXYNOS5420_GPIO_Z5,
+ EXYNOS5420_GPIO_Z6,
+ EXYNOS5420_GPIO_MAX_PORT
};
-struct exynos5420_gpio_part1 {
- struct s5p_gpio_bank a0;
- struct s5p_gpio_bank a1;
- struct s5p_gpio_bank a2;
- struct s5p_gpio_bank b0;
- struct s5p_gpio_bank b1;
- struct s5p_gpio_bank b2;
- struct s5p_gpio_bank b3;
- struct s5p_gpio_bank b4;
- struct s5p_gpio_bank h0;
+struct gpio_info {
+ unsigned int reg_addr; /* Address of register for this part */
+ unsigned int max_gpio; /* Maximum GPIO in this part */
};
-struct exynos5420_gpio_part2 {
- struct s5p_gpio_bank y7; /* 0x1340_0000 */
- struct s5p_gpio_bank res[0x5f]; /* */
- struct s5p_gpio_bank x0; /* 0x1340_0C00 */
- struct s5p_gpio_bank x1; /* 0x1340_0C20 */
- struct s5p_gpio_bank x2; /* 0x1340_0C40 */
- struct s5p_gpio_bank x3; /* 0x1340_0C60 */
+#define EXYNOS4_GPIO_NUM_PARTS 3
+static struct gpio_info exynos4_gpio_data[EXYNOS4_GPIO_NUM_PARTS] = {
+ { EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 },
+ { EXYNOS4_GPIO_PART2_BASE, EXYNOS4_GPIO_MAX_PORT_PART_2 },
+ { EXYNOS4_GPIO_PART3_BASE, EXYNOS4_GPIO_MAX_PORT },
};
-struct exynos5420_gpio_part3 {
- struct s5p_gpio_bank c0;
- struct s5p_gpio_bank c1;
- struct s5p_gpio_bank c2;
- struct s5p_gpio_bank c3;
- struct s5p_gpio_bank c4;
- struct s5p_gpio_bank d1;
- struct s5p_gpio_bank y0;
- struct s5p_gpio_bank y1;
- struct s5p_gpio_bank y2;
- struct s5p_gpio_bank y3;
- struct s5p_gpio_bank y4;
- struct s5p_gpio_bank y5;
- struct s5p_gpio_bank y6;
+#define EXYNOS4X12_GPIO_NUM_PARTS 4
+static struct gpio_info exynos4x12_gpio_data[EXYNOS4X12_GPIO_NUM_PARTS] = {
+ { EXYNOS4X12_GPIO_PART1_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_1 },
+ { EXYNOS4X12_GPIO_PART2_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_2 },
+ { EXYNOS4X12_GPIO_PART3_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_3 },
+ { EXYNOS4X12_GPIO_PART4_BASE, EXYNOS4X12_GPIO_MAX_PORT },
};
-struct exynos5420_gpio_part4 {
- struct s5p_gpio_bank e0; /* 0x1400_0000 */
- struct s5p_gpio_bank e1; /* 0x1400_0020 */
- struct s5p_gpio_bank f0; /* 0x1400_0040 */
- struct s5p_gpio_bank f1; /* 0x1400_0060 */
- struct s5p_gpio_bank g0; /* 0x1400_0080 */
- struct s5p_gpio_bank g1; /* 0x1400_00A0 */
- struct s5p_gpio_bank g2; /* 0x1400_00C0 */
- struct s5p_gpio_bank j4; /* 0x1400_00E0 */
+#define EXYNOS5_GPIO_NUM_PARTS 8
+static struct gpio_info exynos5_gpio_data[EXYNOS5_GPIO_NUM_PARTS] = {
+ { EXYNOS5_GPIO_PART1_BASE, EXYNOS5_GPIO_MAX_PORT_PART_1 },
+ { EXYNOS5_GPIO_PART2_BASE, EXYNOS5_GPIO_MAX_PORT_PART_2 },
+ { EXYNOS5_GPIO_PART3_BASE, EXYNOS5_GPIO_MAX_PORT_PART_3 },
+ { EXYNOS5_GPIO_PART4_BASE, EXYNOS5_GPIO_MAX_PORT_PART_4 },
+ { EXYNOS5_GPIO_PART5_BASE, EXYNOS5_GPIO_MAX_PORT_PART_5 },
+ { EXYNOS5_GPIO_PART6_BASE, EXYNOS5_GPIO_MAX_PORT_PART_6 },
+ { EXYNOS5_GPIO_PART7_BASE, EXYNOS5_GPIO_MAX_PORT_PART_7 },
+ { EXYNOS5_GPIO_PART8_BASE, EXYNOS5_GPIO_MAX_PORT },
};
-struct exynos5420_gpio_part5 {
- struct s5p_gpio_bank z0; /* 0x0386_0000 */
+#define EXYNOS5420_GPIO_NUM_PARTS 6
+static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = {
+ { EXYNOS5420_GPIO_PART1_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_1 },
+ { EXYNOS5420_GPIO_PART2_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_2 },
+ { EXYNOS5420_GPIO_PART3_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_3 },
+ { EXYNOS5420_GPIO_PART4_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_4 },
+ { EXYNOS5420_GPIO_PART5_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_5 },
+ { EXYNOS5420_GPIO_PART6_BASE, EXYNOS5420_GPIO_MAX_PORT },
};
-struct exynos5_gpio_part1 {
- struct s5p_gpio_bank a0;
- struct s5p_gpio_bank a1;
- struct s5p_gpio_bank a2;
- struct s5p_gpio_bank b0;
- struct s5p_gpio_bank b1;
- struct s5p_gpio_bank b2;
- struct s5p_gpio_bank b3;
- struct s5p_gpio_bank c0;
- struct s5p_gpio_bank c1;
- struct s5p_gpio_bank c2;
- struct s5p_gpio_bank c3;
- struct s5p_gpio_bank d0;
- struct s5p_gpio_bank d1;
- struct s5p_gpio_bank y0;
- struct s5p_gpio_bank y1;
- struct s5p_gpio_bank y2;
- struct s5p_gpio_bank y3;
- struct s5p_gpio_bank y4;
- struct s5p_gpio_bank y5;
- struct s5p_gpio_bank y6;
- struct s5p_gpio_bank res1[0x3];
- struct s5p_gpio_bank c4;
- struct s5p_gpio_bank res2[0x48];
- struct s5p_gpio_bank x0;
- struct s5p_gpio_bank x1;
- struct s5p_gpio_bank x2;
- struct s5p_gpio_bank x3;
+static inline struct gpio_info *get_gpio_data(void)
+{
+ if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420())
+ return exynos5420_gpio_data;
+ else
+ return exynos5_gpio_data;
+ } else if (cpu_is_exynos4()) {
+ if (proid_is_exynos4412())
+ return exynos4x12_gpio_data;
+ else
+ return exynos4_gpio_data;
+ }
+
+ return NULL;
+}
+
+static inline unsigned int get_bank_num(void)
+{
+ if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420())
+ return EXYNOS5420_GPIO_NUM_PARTS;
+ else
+ return EXYNOS5_GPIO_NUM_PARTS;
+ } else if (cpu_is_exynos4()) {
+ if (proid_is_exynos4412())
+ return EXYNOS4X12_GPIO_NUM_PARTS;
+ else
+ return EXYNOS4_GPIO_NUM_PARTS;
+ }
+
+ return 0;
+}
+
+/*
+ * This structure helps mapping symbolic GPIO names into indices from
+ * exynos5_gpio_pin/exynos5420_gpio_pin enums.
+ *
+ * By convention, symbolic GPIO name is defined as follows:
+ *
+ * g[p]<bank><set><bit>, where
+ * p is optional
+ * <bank> - a single character bank name, as defined by the SOC
+ * <set> - a single digit set number
+ * <bit> - bit number within the set (in 0..7 range).
+ *
+ * <set><bit> essentially form an octal number of the GPIO pin within the bank
+ * space. On the 5420 architecture some banks' sets do not start not from zero
+ * ('d' starts from 1 and 'j' starts from 4). To compensate for that and
+ * maintain flat number space withoout holes, those banks use offsets to be
+ * deducted from the pin number.
+ */
+struct gpio_name_num_table {
+ char bank; /* bank name symbol */
+ unsigned int bank_size; /* total number of pins in the bank */
+ char bank_offset; /* offset of the first bank's pin */
+ unsigned int base; /* index of the first bank's pin in the enum */
};
-struct exynos5_gpio_part2 {
- struct s5p_gpio_bank e0;
- struct s5p_gpio_bank e1;
- struct s5p_gpio_bank f0;
- struct s5p_gpio_bank f1;
- struct s5p_gpio_bank g0;
- struct s5p_gpio_bank g1;
- struct s5p_gpio_bank g2;
- struct s5p_gpio_bank h0;
- struct s5p_gpio_bank h1;
+#define GPIO_ENTRY(name, base, top, offset) { name, top - base, offset, base }
+static const struct gpio_name_num_table exynos4_gpio_table[] = {
+ GPIO_ENTRY('a', EXYNOS4_GPIO_A00, EXYNOS4_GPIO_B0, 0),
+ GPIO_ENTRY('b', EXYNOS4_GPIO_B0, EXYNOS4_GPIO_C00, 0),
+ GPIO_ENTRY('c', EXYNOS4_GPIO_C00, EXYNOS4_GPIO_D00, 0),
+ GPIO_ENTRY('d', EXYNOS4_GPIO_D00, EXYNOS4_GPIO_E00, 0),
+ GPIO_ENTRY('e', EXYNOS4_GPIO_E00, EXYNOS4_GPIO_F00, 0),
+ GPIO_ENTRY('f', EXYNOS4_GPIO_F00, EXYNOS4_GPIO_J00, 0),
+ GPIO_ENTRY('j', EXYNOS4_GPIO_J00, EXYNOS4_GPIO_K00, 0),
+ GPIO_ENTRY('k', EXYNOS4_GPIO_K00, EXYNOS4_GPIO_L00, 0),
+ GPIO_ENTRY('l', EXYNOS4_GPIO_L00, EXYNOS4_GPIO_Y00, 0),
+ GPIO_ENTRY('y', EXYNOS4_GPIO_Y00, EXYNOS4_GPIO_X00, 0),
+ GPIO_ENTRY('x', EXYNOS4_GPIO_X00, EXYNOS4_GPIO_Z0, 0),
+ GPIO_ENTRY('z', EXYNOS4_GPIO_Z0, EXYNOS4_GPIO_MAX_PORT, 0),
+ { 0 }
};
-struct exynos5_gpio_part3 {
- struct s5p_gpio_bank v0;
- struct s5p_gpio_bank v1;
- struct s5p_gpio_bank res1[0x1];
- struct s5p_gpio_bank v2;
- struct s5p_gpio_bank v3;
- struct s5p_gpio_bank res2[0x1];
- struct s5p_gpio_bank v4;
+static const struct gpio_name_num_table exynos4x12_gpio_table[] = {
+ GPIO_ENTRY('a', EXYNOS4X12_GPIO_A00, EXYNOS4X12_GPIO_B0, 0),
+ GPIO_ENTRY('b', EXYNOS4X12_GPIO_B0, EXYNOS4X12_GPIO_C00, 0),
+ GPIO_ENTRY('c', EXYNOS4X12_GPIO_C00, EXYNOS4X12_GPIO_D00, 0),
+ GPIO_ENTRY('d', EXYNOS4X12_GPIO_D00, EXYNOS4X12_GPIO_F00, 0),
+ GPIO_ENTRY('f', EXYNOS4X12_GPIO_F00, EXYNOS4X12_GPIO_J00, 0),
+ GPIO_ENTRY('j', EXYNOS4X12_GPIO_J00, EXYNOS4X12_GPIO_K00, 0),
+ GPIO_ENTRY('k', EXYNOS4X12_GPIO_K00, EXYNOS4X12_GPIO_L00, 0),
+ GPIO_ENTRY('l', EXYNOS4X12_GPIO_L00, EXYNOS4X12_GPIO_Y00, 0),
+ GPIO_ENTRY('y', EXYNOS4X12_GPIO_Y00, EXYNOS4X12_GPIO_M00, 0),
+ GPIO_ENTRY('m', EXYNOS4X12_GPIO_M00, EXYNOS4X12_GPIO_X00, 0),
+ GPIO_ENTRY('x', EXYNOS4X12_GPIO_X00, EXYNOS4X12_GPIO_Z0, 0),
+ GPIO_ENTRY('z', EXYNOS4X12_GPIO_Z0, EXYNOS4X12_GPIO_V00, 0),
+ GPIO_ENTRY('v', EXYNOS4X12_GPIO_V00, EXYNOS4X12_GPIO_MAX_PORT, 0),
+ { 0 }
};
-struct exynos5_gpio_part4 {
- struct s5p_gpio_bank z;
+static const struct gpio_name_num_table exynos5_gpio_table[] = {
+ GPIO_ENTRY('a', EXYNOS5_GPIO_A00, EXYNOS5_GPIO_B00, 0),
+ GPIO_ENTRY('b', EXYNOS5_GPIO_B00, EXYNOS5_GPIO_C00, 0),
+ GPIO_ENTRY('c', EXYNOS5_GPIO_C00, EXYNOS5_GPIO_D00, 0),
+ GPIO_ENTRY('d', EXYNOS5_GPIO_D00, EXYNOS5_GPIO_Y00, 0),
+ GPIO_ENTRY('y', EXYNOS5_GPIO_Y00, EXYNOS5_GPIO_C40, 0),
+ GPIO_ENTRY('x', EXYNOS5_GPIO_X00, EXYNOS5_GPIO_E00, 0),
+ GPIO_ENTRY('e', EXYNOS5_GPIO_E00, EXYNOS5_GPIO_F00, 0),
+ GPIO_ENTRY('f', EXYNOS5_GPIO_F00, EXYNOS5_GPIO_G00, 0),
+ GPIO_ENTRY('g', EXYNOS5_GPIO_G00, EXYNOS5_GPIO_H00, 0),
+ GPIO_ENTRY('h', EXYNOS5_GPIO_H00, EXYNOS5_GPIO_V00, 0),
+ GPIO_ENTRY('v', EXYNOS5_GPIO_V00, EXYNOS5_GPIO_Z0, 0),
+ GPIO_ENTRY('z', EXYNOS5_GPIO_Z0, EXYNOS5_GPIO_MAX_PORT, 0),
+ { 0 }
};
-/* functions */
-void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
-void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
-void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
-void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
-unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
-void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
-void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
-void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
+static const struct gpio_name_num_table exynos5420_gpio_table[] = {
+ GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00, 0),
+ GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00, 0),
+ GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Y70, 0),
+ GPIO_ENTRY('x', EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_C00, 0),
+ GPIO_ENTRY('c', EXYNOS5420_GPIO_C00, EXYNOS5420_GPIO_D10, 0),
+ GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00, 010),
+ GPIO_ENTRY('y', EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_E00, 0),
+ GPIO_ENTRY('e', EXYNOS5420_GPIO_E00, EXYNOS5420_GPIO_F00, 0),
+ GPIO_ENTRY('f', EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_G00, 0),
+ GPIO_ENTRY('g', EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_J40, 0),
+ GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_Z0, 040),
+ GPIO_ENTRY('z', EXYNOS5420_GPIO_Z0, EXYNOS5420_GPIO_MAX_PORT, 0),
+ { 0 }
+};
-/* GPIO pins per bank */
-#define GPIO_PER_BANK 8
-#define S5P_GPIO_PART_SHIFT (24)
-#define S5P_GPIO_PART_MASK (0xff)
-#define S5P_GPIO_BANK_SHIFT (8)
-#define S5P_GPIO_BANK_MASK (0xffff)
-#define S5P_GPIO_PIN_MASK (0xff)
-
-#define S5P_GPIO_SET_PART(x) \
- (((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT)
-
-#define S5P_GPIO_GET_PART(x) \
- (((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK)
-
-#define S5P_GPIO_SET_PIN(x) \
- ((x) & S5P_GPIO_PIN_MASK)
-
-#define EXYNOS4_GPIO_SET_BANK(part, bank) \
- ((((unsigned)&(((struct exynos4_gpio_part##part *) \
- EXYNOS4_GPIO_PART##part##_BASE)->bank) \
- - EXYNOS4_GPIO_PART##part##_BASE) \
- & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
-
-#define EXYNOS4X12_GPIO_SET_BANK(part, bank) \
- ((((unsigned)&(((struct exynos4x12_gpio_part##part *) \
- EXYNOS4X12_GPIO_PART##part##_BASE)->bank) \
- - EXYNOS4X12_GPIO_PART##part##_BASE) \
- & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
-
-#define EXYNOS5_GPIO_SET_BANK(part, bank) \
- ((((unsigned)&(((struct exynos5420_gpio_part##part *) \
- EXYNOS5420_GPIO_PART##part##_BASE)->bank) \
- - EXYNOS5_GPIO_PART##part##_BASE) \
- & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
-
-#define EXYNOS5420_GPIO_SET_BANK(part, bank) \
- ((((unsigned)&(((struct exynos5420_gpio_part##part *) \
- EXYNOS5420_GPIO_PART##part##_BASE)->bank) \
- - EXYNOS5420_GPIO_PART##part##_BASE) \
- & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
-
-#define exynos4_gpio_get(part, bank, pin) \
- (S5P_GPIO_SET_PART(part) | \
- EXYNOS4_GPIO_SET_BANK(part, bank) | \
- S5P_GPIO_SET_PIN(pin))
-
-#define exynos4x12_gpio_get(part, bank, pin) \
- (S5P_GPIO_SET_PART(part) | \
- EXYNOS4X12_GPIO_SET_BANK(part, bank) | \
- S5P_GPIO_SET_PIN(pin))
-
-#define exynos5420_gpio_get(part, bank, pin) \
- (S5P_GPIO_SET_PART(part) | \
- EXYNOS5420_GPIO_SET_BANK(part, bank) | \
- S5P_GPIO_SET_PIN(pin))
-
-#define exynos5_gpio_get(part, bank, pin) \
- (S5P_GPIO_SET_PART(part) | \
- EXYNOS5_GPIO_SET_BANK(part, bank) | \
- S5P_GPIO_SET_PIN(pin))
-
-static inline unsigned int s5p_gpio_base(int gpio)
-{
- unsigned gpio_part = S5P_GPIO_GET_PART(gpio);
-
- switch (gpio_part) {
- case 1:
- return samsung_get_base_gpio_part1();
- case 2:
- return samsung_get_base_gpio_part2();
- case 3:
- return samsung_get_base_gpio_part3();
- case 4:
- return samsung_get_base_gpio_part4();
- default:
- return 0;
- }
-}
+void gpio_cfg_pin(int gpio, int cfg);
+void gpio_set_pull(int gpio, int mode);
+void gpio_set_drv(int gpio, int mode);
+int gpio_direction_output(unsigned gpio, int value);
+int gpio_set_value(unsigned gpio, int value);
+int gpio_get_value(unsigned gpio);
+void gpio_set_rate(int gpio, int mode);
+struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio);
+int s5p_gpio_get_pin(unsigned gpio);
#endif
/* Pin configurations */
-#define GPIO_INPUT 0x0
-#define GPIO_OUTPUT 0x1
-#define GPIO_IRQ 0xf
-#define GPIO_FUNC(x) (x)
+#define S5P_GPIO_INPUT 0x0
+#define S5P_GPIO_OUTPUT 0x1
+#define S5P_GPIO_IRQ 0xf
+#define S5P_GPIO_FUNC(x) (x)
/* Pull mode */
-#define GPIO_PULL_NONE 0x0
-#define GPIO_PULL_DOWN 0x1
-#define GPIO_PULL_UP 0x3
+#define S5P_GPIO_PULL_NONE 0x0
+#define S5P_GPIO_PULL_DOWN 0x1
+#define S5P_GPIO_PULL_UP 0x3
/* Drive Strength level */
-#define GPIO_DRV_1X 0x0
-#define GPIO_DRV_3X 0x1
-#define GPIO_DRV_2X 0x2
-#define GPIO_DRV_4X 0x3
-#define GPIO_DRV_FAST 0x0
-#define GPIO_DRV_SLOW 0x1
+#define S5P_GPIO_DRV_1X 0x0
+#define S5P_GPIO_DRV_3X 0x1
+#define S5P_GPIO_DRV_2X 0x2
+#define S5P_GPIO_DRV_4X 0x3
+#define S5P_GPIO_DRV_FAST 0x0
+#define S5P_GPIO_DRV_SLOW 0x1
#endif
u32 mpr_0_7;
u32 mpr_8_15;
};
+/* LCD controller registers */
+struct lcdc_regs {
+ u32 lssar; /* Screen Start Address */
+ u32 lsr; /* Size */
+ u32 lvpwr; /* Virtual Page Width */
+ u32 lcpr; /* Cursor Position */
+ u32 lcwhb; /* Cursor Width Height and Blink */
+ u32 lccmr; /* Color Cursor Mapping */
+ u32 lpcr; /* Panel Configuration */
+ u32 lhcr; /* Horizontal Configuration */
+ u32 lvcr; /* Vertical Configuration */
+ u32 lpor; /* Panning Offset */
+ u32 lscr; /* Sharp Configuration */
+ u32 lpccr; /* PWM Contrast Control */
+ u32 ldcr; /* DMA Control */
+ u32 lrmcr; /* Refresh Mode Control */
+ u32 licr; /* Interrupt Configuration */
+ u32 lier; /* Interrupt Enable */
+ u32 lisr; /* Interrupt Status */
+ u32 res0[3];
+ u32 lgwsar; /* Graphic Window Start Address */
+ u32 lgwsr; /* Graphic Window Size */
+ u32 lgwvpwr; /* Graphic Window Virtual Page Width Regist */
+ u32 lgwpor; /* Graphic Window Panning Offset */
+ u32 lgwpr; /* Graphic Window Position */
+ u32 lgwcr; /* Graphic Window Control */
+ u32 lgwdcr; /* Graphic Window DMA Control */
+ u32 res1[5];
+ u32 lauscr; /* AUS Mode Control */
+ u32 lausccr; /* AUS mode Cursor Control */
+ u32 res2[31 + 64*7];
+ u32 bglut; /* Background Lookup Table */
+ u32 gwlut; /* Graphic Window Lookup Table */
+};
+
+/* Wireless External Interface Module Registers */
+struct weim_regs {
+ u32 cscr0u; /* Chip Select 0 Upper Register */
+ u32 cscr0l; /* Chip Select 0 Lower Register */
+ u32 cscr0a; /* Chip Select 0 Addition Register */
+ u32 pad0;
+ u32 cscr1u; /* Chip Select 1 Upper Register */
+ u32 cscr1l; /* Chip Select 1 Lower Register */
+ u32 cscr1a; /* Chip Select 1 Addition Register */
+ u32 pad1;
+ u32 cscr2u; /* Chip Select 2 Upper Register */
+ u32 cscr2l; /* Chip Select 2 Lower Register */
+ u32 cscr2a; /* Chip Select 2 Addition Register */
+ u32 pad2;
+ u32 cscr3u; /* Chip Select 3 Upper Register */
+ u32 cscr3l; /* Chip Select 3 Lower Register */
+ u32 cscr3a; /* Chip Select 3 Addition Register */
+ u32 pad3;
+ u32 cscr4u; /* Chip Select 4 Upper Register */
+ u32 cscr4l; /* Chip Select 4 Lower Register */
+ u32 cscr4a; /* Chip Select 4 Addition Register */
+ u32 pad4;
+ u32 cscr5u; /* Chip Select 5 Upper Register */
+ u32 cscr5l; /* Chip Select 5 Lower Register */
+ u32 cscr5a; /* Chip Select 5 Addition Register */
+ u32 pad5;
+ u32 wcr; /* WEIM Configuration Register */
+};
+
+/* Multi-Master Memory Interface */
+struct m3if_regs {
+ u32 ctl; /* Control Register */
+ u32 wcfg0; /* Watermark Configuration Register 0 */
+ u32 wcfg1; /* Watermark Configuration Register1 */
+ u32 wcfg2; /* Watermark Configuration Register2 */
+ u32 wcfg3; /* Watermark Configuration Register 3 */
+ u32 wcfg4; /* Watermark Configuration Register 4 */
+ u32 wcfg5; /* Watermark Configuration Register 5 */
+ u32 wcfg6; /* Watermark Configuration Register 6 */
+ u32 wcfg7; /* Watermark Configuration Register 7 */
+ u32 wcsr; /* Watermark Control and Status Register */
+ u32 scfg0; /* Snooping Configuration Register 0 */
+ u32 scfg1; /* Snooping Configuration Register 1 */
+ u32 scfg2; /* Snooping Configuration Register 2 */
+ u32 ssr0; /* Snooping Status Register 0 */
+ u32 ssr1; /* Snooping Status Register 1 */
+ u32 res0;
+ u32 mlwe0; /* Master Lock WEIM CS0 Register */
+ u32 mlwe1; /* Master Lock WEIM CS1 Register */
+ u32 mlwe2; /* Master Lock WEIM CS2 Register */
+ u32 mlwe3; /* Master Lock WEIM CS3 Register */
+ u32 mlwe4; /* Master Lock WEIM CS4 Register */
+ u32 mlwe5; /* Master Lock WEIM CS5 Register */
+};
+
+/* Pulse width modulation */
+struct pwm_regs {
+ u32 cr; /* Control Register */
+ u32 sr; /* Status Register */
+ u32 ir; /* Interrupt Register */
+ u32 sar; /* Sample Register */
+ u32 pr; /* Period Register */
+ u32 cnr; /* Counter Register */
+};
+
+/* Enhanced Periodic Interrupt Timer */
+struct epit_regs {
+ u32 cr; /* Control register */
+ u32 sr; /* Status register */
+ u32 lr; /* Load register */
+ u32 cmpr; /* Compare register */
+ u32 cnr; /* Counter register */
+};
+
+/* CSPI registers */
+struct cspi_regs {
+ u32 rxdata;
+ u32 txdata;
+ u32 ctrl;
+ u32 intr;
+ u32 dma;
+ u32 stat;
+ u32 period;
+ u32 test;
+};
#endif
#define CCM_PERCLK_MASK 0x3f
#define CCM_RCSR_NF_16BIT_SEL (1 << 14)
#define CCM_RCSR_NF_PS(v) ((v >> 26) & 3)
+#define CCM_CRDR_BT_UART_SRC_SHIFT 29
+#define CCM_CRDR_BT_UART_SRC_MASK 7
/* ESDRAM Controller register bitfields */
#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0)
#define WSR_UNLOCK1 0x5555
#define WSR_UNLOCK2 0xAAAA
+/* MAX bits */
+#define MAX_MGPCR_AULB(x) (((x) & 0x7) << 0)
+
+/* M3IF bits */
+#define M3IF_CTL_MRRP(x) (((x) & 0xff) << 0)
+
+/* WEIM bits */
+/* 13 fields of the upper CS control register */
+#define WEIM_CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
+ cnc, wsc, ew, wws, edc) \
+ ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (bcs) << 24 | \
+ (psz) << 22 | (pme) << 21 | (sync) << 20 | (dol) << 16 | \
+ (cnc) << 14 | (wsc) << 8 | (ew) << 7 | (wws) << 4 | (edc) << 0)
+/* 12 fields of the lower CS control register */
+#define WEIM_CSCR_L(oea, oen, ebwa, ebwn, \
+ csa, ebc, dsz, csn, psr, cre, wrap, csen) \
+ ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\
+ (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\
+ (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
+/* 14 fields of the additional CS control register */
+#define WEIM_CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \
+ wwu, age, cnc2, fce) \
+ ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\
+ (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\
+ (dww) << 6 | (dct) << 4 | (wwu) << 3 |\
+ (age) << 2 | (cnc2) << 1 | (fce) << 0)
+
/* Names used in GPIO driver */
#define GPIO1_BASE_ADDR IMX_GPIO1_BASE
#define GPIO2_BASE_ADDR IMX_GPIO2_BASE
#define GPIO3_BASE_ADDR IMX_GPIO3_BASE
#define GPIO4_BASE_ADDR IMX_GPIO4_BASE
+/*
+ * CSPI register definitions
+ */
+#define MXC_CSPI
+#define MXC_CSPICTRL_EN (1 << 0)
+#define MXC_CSPICTRL_MODE (1 << 1)
+#define MXC_CSPICTRL_XCH (1 << 2)
+#define MXC_CSPICTRL_SMC (1 << 3)
+#define MXC_CSPICTRL_POL (1 << 4)
+#define MXC_CSPICTRL_PHA (1 << 5)
+#define MXC_CSPICTRL_SSCTL (1 << 6)
+#define MXC_CSPICTRL_SSPOL (1 << 7)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC (1 << 7)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPICTRL_MAXBITS 0xfff
+#define MXC_CSPIPERIOD_32KHZ (1 << 15)
+#define MAX_SPI_BYTES 4
+
+#define MXC_SPI_BASE_ADDRESSES \
+ IMX_CSPI1_BASE, \
+ IMX_CSPI2_BASE, \
+ IMX_CSPI3_BASE
+
#define CHIP_REV_1_0 0x10
#define CHIP_REV_1_1 0x11
#define CHIP_REV_1_2 0x12
#include <asm/imx-common/iomux-v3.h>
enum {
+ MX6_PAD_ECSPI1_MISO__ECSPI_MISO = IOMUX_PAD(0x0358, 0x0068, 0, 0x0684, 0, 0),
+ MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI = IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, 0),
+ MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK = IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, 0),
+ MX6_PAD_ECSPI1_SS0__GPIO4_IO11 = IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, 0),
MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0),
MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0),
#define V_SCLK V_OSCK
+/* CKO buffer control */
+#define CKOBUFFER_CLK_ENABLE_MASK (1 << 28)
+
/* AUXCLKx reg fields */
#define AUXCLK_ENABLE_MASK (1 << 8)
#define AUXCLK_SRCSELECT_SHIFT 1
#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
#define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000)
#define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000)
+#define UART4_BASE (OMAP54XX_L4_PER_BASE + 0x6e000)
/* General Purpose Timers */
#define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000)
/*
* arch/arm/include/asm/arch-rmobile/r8a7790.h
*
- * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
- */
+*/
#ifndef __ASM_ARCH_R8A7790_H
#define __ASM_ARCH_R8A7790_H
-/*
- * R8A7790 I/O Addresses
- */
-#define RWDT_BASE 0xE6020000
-#define SWDT_BASE 0xE6030000
-#define LBSC_BASE 0xFEC00200
-#define DBSC3_0_BASE 0xE6790000
-#define DBSC3_1_BASE 0xE67A0000
-#define TMU_BASE 0xE61E0000
-#define GPIO5_BASE 0xE6055000
-#define SH_QSPI_BASE 0xE6B10000
-
-#define S3C_BASE 0xE6784000
-#define S3C_INT_BASE 0xE6784A00
-#define S3C_MEDIA_BASE 0xE6784B00
-
-#define S3C_QOS_DCACHE_BASE 0xE6784BDC
-#define S3C_QOS_CCI0_BASE 0xE6784C00
-#define S3C_QOS_CCI1_BASE 0xE6784C24
-#define S3C_QOS_MXI_BASE 0xE6784C48
-#define S3C_QOS_AXI_BASE 0xE6784C6C
-
-#define DBSC3_0_QOS_R0_BASE 0xE6791000
-#define DBSC3_0_QOS_R1_BASE 0xE6791100
-#define DBSC3_0_QOS_R2_BASE 0xE6791200
-#define DBSC3_0_QOS_R3_BASE 0xE6791300
-#define DBSC3_0_QOS_R4_BASE 0xE6791400
-#define DBSC3_0_QOS_R5_BASE 0xE6791500
-#define DBSC3_0_QOS_R6_BASE 0xE6791600
-#define DBSC3_0_QOS_R7_BASE 0xE6791700
-#define DBSC3_0_QOS_R8_BASE 0xE6791800
-#define DBSC3_0_QOS_R9_BASE 0xE6791900
-#define DBSC3_0_QOS_R10_BASE 0xE6791A00
-#define DBSC3_0_QOS_R11_BASE 0xE6791B00
-#define DBSC3_0_QOS_R12_BASE 0xE6791C00
-#define DBSC3_0_QOS_R13_BASE 0xE6791D00
-#define DBSC3_0_QOS_R14_BASE 0xE6791E00
-#define DBSC3_0_QOS_R15_BASE 0xE6791F00
-#define DBSC3_0_QOS_W0_BASE 0xE6792000
-#define DBSC3_0_QOS_W1_BASE 0xE6792100
-#define DBSC3_0_QOS_W2_BASE 0xE6792200
-#define DBSC3_0_QOS_W3_BASE 0xE6792300
-#define DBSC3_0_QOS_W4_BASE 0xE6792400
-#define DBSC3_0_QOS_W5_BASE 0xE6792500
-#define DBSC3_0_QOS_W6_BASE 0xE6792600
-#define DBSC3_0_QOS_W7_BASE 0xE6792700
-#define DBSC3_0_QOS_W8_BASE 0xE6792800
-#define DBSC3_0_QOS_W9_BASE 0xE6792900
-#define DBSC3_0_QOS_W10_BASE 0xE6792A00
-#define DBSC3_0_QOS_W11_BASE 0xE6792B00
-#define DBSC3_0_QOS_W12_BASE 0xE6792C00
-#define DBSC3_0_QOS_W13_BASE 0xE6792D00
-#define DBSC3_0_QOS_W14_BASE 0xE6792E00
-#define DBSC3_0_QOS_W15_BASE 0xE6792F00
-
-#define DBSC3_0_DBADJ2 0xE67900C8
-
-#define CCI_400_MAXOT_1 0xF0091110
-#define CCI_400_MAXOT_2 0xF0092110
-#define CCI_400_QOSCNTL_1 0xF009110C
-#define CCI_400_QOSCNTL_2 0xF009210C
-
-#define MXI_BASE 0xFE960000
-#define MXI_QOS_BASE 0xFE960300
-
-#define SYS_AXI_SYX64TO128_BASE 0xFF800300
-#define SYS_AXI_AVB_BASE 0xFF800340
-#define SYS_AXI_G2D_BASE 0xFF800540
-#define SYS_AXI_IMP0_BASE 0xFF800580
-#define SYS_AXI_IMP1_BASE 0xFF8005C0
-#define SYS_AXI_IMUX0_BASE 0xFF800600
-#define SYS_AXI_IMUX1_BASE 0xFF800640
-#define SYS_AXI_IMUX2_BASE 0xFF800680
-#define SYS_AXI_LBS_BASE 0xFF8006C0
-#define SYS_AXI_MMUDS_BASE 0xFF800700
-#define SYS_AXI_MMUM_BASE 0xFF800740
-#define SYS_AXI_MMUR_BASE 0xFF800780
-#define SYS_AXI_MMUS0_BASE 0xFF8007C0
-#define SYS_AXI_MMUS1_BASE 0xFF800800
-#define SYS_AXI_MTSB0_BASE 0xFF800880
-#define SYS_AXI_MTSB1_BASE 0xFF8008C0
-#define SYS_AXI_PCI_BASE 0xFF800900
-#define SYS_AXI_RTX_BASE 0xFF800940
-#define SYS_AXI_SDS0_BASE 0xFF800A80
-#define SYS_AXI_SDS1_BASE 0xFF800AC0
-#define SYS_AXI_USB20_BASE 0xFF800C00
-#define SYS_AXI_USB21_BASE 0xFF800C40
-#define SYS_AXI_USB22_BASE 0xFF800C80
-#define SYS_AXI_USB30_BASE 0xFF800CC0
-
-#define RT_AXI_SHX_BASE 0xFF810100
-#define RT_AXI_RDS_BASE 0xFF8101C0
-#define RT_AXI_RTX64TO128_BASE 0xFF810200
-#define RT_AXI_STPRO_BASE 0xFF810240
-
-#define MP_AXI_ADSP_BASE 0xFF820100
-#define MP_AXI_ASDS0_BASE 0xFF8201C0
-#define MP_AXI_ASDS1_BASE 0xFF820200
-#define MP_AXI_MLP_BASE 0xFF820240
-#define MP_AXI_MMUMP_BASE 0xFF820280
-#define MP_AXI_SPU_BASE 0xFF8202C0
-#define MP_AXI_SPUC_BASE 0xFF820300
-
-#define SYS_AXI256_AXI128TO256_BASE 0xFF860100
-#define SYS_AXI256_SYX_BASE 0xFF860140
-#define SYS_AXI256_MPX_BASE 0xFF860180
-#define SYS_AXI256_MXI_BASE 0xFF8601C0
-
-#define CCI_AXI_MMUS0_BASE 0xFF880100
-#define CCI_AXI_SYX2_BASE 0xFF880140
-#define CCI_AXI_MMUR_BASE 0xFF880180
-#define CCI_AXI_MMUDS_BASE 0xFF8801C0
-#define CCI_AXI_MMUM_BASE 0xFF880200
-#define CCI_AXI_MXI_BASE 0xFF880240
-#define CCI_AXI_MMUS1_BASE 0xFF880280
-#define CCI_AXI_MMUMP_BASE 0xFF8802C0
-
-#define MEDIA_AXI_JPR_BASE 0xFE964100
-#define MEDIA_AXI_JPW_BASE 0xFE966100
-#define MEDIA_AXI_GCU0R_BASE 0xFE964140
-#define MEDIA_AXI_GCU0W_BASE 0xFE966140
-#define MEDIA_AXI_GCU1R_BASE 0xFE964180
-#define MEDIA_AXI_GCU1W_BASE 0xFE966180
-#define MEDIA_AXI_TDMR_BASE 0xFE964500
-#define MEDIA_AXI_TDMW_BASE 0xFE966500
-#define MEDIA_AXI_VSP0CR_BASE 0xFE964540
-#define MEDIA_AXI_VSP0CW_BASE 0xFE966540
-#define MEDIA_AXI_VSP1CR_BASE 0xFE964580
-#define MEDIA_AXI_VSP1CW_BASE 0xFE966580
-#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0
-#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0
-#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600
-#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600
-#define MEDIA_AXI_VIN0W_BASE 0xFE966900
-#define MEDIA_AXI_VSP0R_BASE 0xFE964D00
-#define MEDIA_AXI_VSP0W_BASE 0xFE966D00
-#define MEDIA_AXI_FDP0R_BASE 0xFE964D40
-#define MEDIA_AXI_FDP0W_BASE 0xFE966D40
-#define MEDIA_AXI_IMSR_BASE 0xFE964D80
-#define MEDIA_AXI_IMSW_BASE 0xFE966D80
-#define MEDIA_AXI_VSP1R_BASE 0xFE965100
-#define MEDIA_AXI_VSP1W_BASE 0xFE967100
-#define MEDIA_AXI_FDP1R_BASE 0xFE965140
-#define MEDIA_AXI_FDP1W_BASE 0xFE967140
-#define MEDIA_AXI_IMRR_BASE 0xFE965180
-#define MEDIA_AXI_IMRW_BASE 0xFE967180
-#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0
-#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0
-#define MEDIA_AXI_VSPD0R_BASE 0xFE965500
-#define MEDIA_AXI_VSPD0W_BASE 0xFE967500
-#define MEDIA_AXI_VSPD1R_BASE 0xFE965540
-#define MEDIA_AXI_VSPD1W_BASE 0xFE967540
-#define MEDIA_AXI_DU0R_BASE 0xFE965580
-#define MEDIA_AXI_DU0W_BASE 0xFE967580
-#define MEDIA_AXI_DU1R_BASE 0xFE9655C0
-#define MEDIA_AXI_DU1W_BASE 0xFE9675C0
-#define MEDIA_AXI_VCP0CR_BASE 0xFE965900
-#define MEDIA_AXI_VCP0CW_BASE 0xFE967900
-#define MEDIA_AXI_VCP0VR_BASE 0xFE965940
-#define MEDIA_AXI_VCP0VW_BASE 0xFE967940
-#define MEDIA_AXI_VPC0R_BASE 0xFE965980
-#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00
-#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00
-#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40
-#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40
-#define MEDIA_AXI_VPC1R_BASE 0xFE965D80
-
-#define SYS_AXI_AVBDMSCR 0xFF802000
-#define SYS_AXI_SYX2DMSCR 0xFF802004
-#define SYS_AXI_CC50DMSCR 0xFF802008
-#define SYS_AXI_CC51DMSCR 0xFF80200C
-#define SYS_AXI_CCIDMSCR 0xFF802010
-#define SYS_AXI_CSDMSCR 0xFF802014
-#define SYS_AXI_DDMDMSCR 0xFF802018
-#define SYS_AXI_ETHDMSCR 0xFF80201C
-#define SYS_AXI_G2DDMSCR 0xFF802020
-#define SYS_AXI_IMP0DMSCR 0xFF802024
-#define SYS_AXI_IMP1DMSCR 0xFF802028
-#define SYS_AXI_LBSDMSCR 0xFF80202C
-#define SYS_AXI_MMUDSDMSCR 0xFF802030
-#define SYS_AXI_MMUMXDMSCR 0xFF802034
-#define SYS_AXI_MMURDDMSCR 0xFF802038
-#define SYS_AXI_MMUS0DMSCR 0xFF80203C
-#define SYS_AXI_MMUS1DMSCR 0xFF802040
-#define SYS_AXI_MPXDMSCR 0xFF802044
-#define SYS_AXI_MTSB0DMSCR 0xFF802048
-#define SYS_AXI_MTSB1DMSCR 0xFF80204C
-#define SYS_AXI_PCIDMSCR 0xFF802050
-#define SYS_AXI_RTXDMSCR 0xFF802054
-#define SYS_AXI_SAT0DMSCR 0xFF802058
-#define SYS_AXI_SAT1DMSCR 0xFF80205C
-#define SYS_AXI_SDM0DMSCR 0xFF802060
-#define SYS_AXI_SDM1DMSCR 0xFF802064
-#define SYS_AXI_SDS0DMSCR 0xFF802068
-#define SYS_AXI_SDS1DMSCR 0xFF80206C
-#define SYS_AXI_ETRABDMSCR 0xFF802070
-#define SYS_AXI_ETRKFDMSCR 0xFF802074
-#define SYS_AXI_UDM0DMSCR 0xFF802078
-#define SYS_AXI_UDM1DMSCR 0xFF80207C
-#define SYS_AXI_USB20DMSCR 0xFF802080
-#define SYS_AXI_USB21DMSCR 0xFF802084
-#define SYS_AXI_USB22DMSCR 0xFF802088
-#define SYS_AXI_USB30DMSCR 0xFF80208C
-#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100
-#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104
-#define SYS_AXI_AVBSLVDMSCR 0xFF802108
-#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C
-#define SYS_AXI_ETHSLVDMSCR 0xFF802110
-#define SYS_AXI_GICSLVDMSCR 0xFF802114
-#define SYS_AXI_IMPSLVDMSCR 0xFF802118
-#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C
-#define SYS_AXI_IMX1SLVDMSCR 0xFF802120
-#define SYS_AXI_IMX2SLVDMSCR 0xFF802124
-#define SYS_AXI_LBSSLVDMSCR 0xFF802128
-#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C
-#define SYS_AXI_MMC1SLVDMSCR 0xFF802130
-#define SYS_AXI_MPXSLVDMSCR 0xFF802134
-#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138
-#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C
-#define SYS_AXI_MXTSLVDMSCR 0xFF802140
-#define SYS_AXI_PCISLVDMSCR 0xFF802144
-#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148
-#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C
-#define SYS_AXI_RTXSLVDMSCR 0xFF802150
-#define SYS_AXI_SAT0SLVDMSCR 0xFF802168
-#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C
-#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170
-#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174
-#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178
-#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C
-#define SYS_AXI_SGXSLVDMSCR 0xFF802180
-#define SYS_AXI_STBSLVDMSCR 0xFF802188
-#define SYS_AXI_STMSLVDMSCR 0xFF80218C
-#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194
-#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198
-#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C
-#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0
-#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4
-#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8
-#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC
-
-#define RT_AXI_CBMDMSCR 0xFF812000
-#define RT_AXI_DBDMSCR 0xFF812004
-#define RT_AXI_RDMDMSCR 0xFF812008
-#define RT_AXI_RDSDMSCR 0xFF81200C
-#define RT_AXI_STRDMSCR 0xFF812010
-#define RT_AXI_SY2RTDMSCR 0xFF812014
-#define RT_AXI_CBSSLVDMSCR 0xFF812100
-#define RT_AXI_DBSSLVDMSCR 0xFF812104
-#define RT_AXI_RTAP1SLVDMSCR 0xFF812108
-#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C
-#define RT_AXI_RTAP3SLVDMSCR 0xFF812110
-#define RT_AXI_RT2SYSLVDMSCR 0xFF812114
-#define RT_AXI_A128TO64SLVDMSCR 0xFF812118
-#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C
-#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120
-#define RT_AXI_UTLBRSLVDMSCR 0xFF812128
-
-#define MP_AXI_ADSPDMSCR 0xFF822000
-#define MP_AXI_ASDM0DMSCR 0xFF822004
-#define MP_AXI_ASDM1DMSCR 0xFF822008
-#define MP_AXI_ASDS0DMSCR 0xFF82200C
-#define MP_AXI_ASDS1DMSCR 0xFF822010
-#define MP_AXI_MLPDMSCR 0xFF822014
-#define MP_AXI_MMUMPDMSCR 0xFF822018
-#define MP_AXI_SPUDMSCR 0xFF82201C
-#define MP_AXI_SPUCDMSCR 0xFF822020
-#define MP_AXI_SY2MPDMSCR 0xFF822024
-#define MP_AXI_ADSPSLVDMSCR 0xFF822100
-#define MP_AXI_MLMSLVDMSCR 0xFF822104
-#define MP_AXI_MPAP4SLVDMSCR 0xFF822108
-#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C
-#define MP_AXI_MPAP6SLVDMSCR 0xFF822110
-#define MP_AXI_MPAP7SLVDMSCR 0xFF822114
-#define MP_AXI_MP2SYSLVDMSCR 0xFF822118
-#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C
-#define MP_AXI_MPXAPSLVDMSCR 0xFF822124
-#define MP_AXI_SPUSLVDMSCR 0xFF822128
-#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C
-
-#define ADM_AXI_ASDM0DMSCR 0xFF842000
-#define ADM_AXI_ASDM1DMSCR 0xFF842004
-#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104
-#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108
-#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C
-
-#define DM_AXI_RDMDMSCR 0xFF852000
-#define DM_AXI_SDM0DMSCR 0xFF852004
-#define DM_AXI_SDM1DMSCR 0xFF852008
-#define DM_AXI_MMAP0SLVDMSCR 0xFF852100
-#define DM_AXI_MMAP1SLVDMSCR 0xFF852104
-#define DM_AXI_QSPAPSLVDMSCR 0xFF852108
-#define DM_AXI_RAP4SLVDMSCR 0xFF85210C
-#define DM_AXI_RAP5SLVDMSCR 0xFF852110
-#define DM_AXI_SAP4SLVDMSCR 0xFF852114
-#define DM_AXI_SAP5SLVDMSCR 0xFF852118
-#define DM_AXI_SAP6SLVDMSCR 0xFF85211C
-#define DM_AXI_SAP65SLVDMSCR 0xFF852120
-#define DM_AXI_SDAP0SLVDMSCR 0xFF852124
-#define DM_AXI_SDAP1SLVDMSCR 0xFF852128
-#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C
-#define DM_AXI_SDAP3SLVDMSCR 0xFF852130
-
-#define SYS_AXI256_SYXDMSCR 0xFF862000
-#define SYS_AXI256_MPXDMSCR 0xFF862004
-#define SYS_AXI256_MXIDMSCR 0xFF862008
-#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100
-#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104
-#define SYS_AXI256_SYXSLVDMSCR 0xFF862108
-#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C
-#define SYS_AXI256_S3CSLVDMSCR 0xFF862110
-
-#define MXT_SYXDMSCR 0xFF872000
-#define MXT_CMM0SLVDMSCR 0xFF872100
-#define MXT_CMM1SLVDMSCR 0xFF872104
-#define MXT_CMM2SLVDMSCR 0xFF872108
-#define MXT_FDPSLVDMSCR 0xFF87210C
-#define MXT_IMRSLVDMSCR 0xFF872110
-#define MXT_VINSLVDMSCR 0xFF872114
-#define MXT_VPC0SLVDMSCR 0xFF872118
-#define MXT_VPC1SLVDMSCR 0xFF87211C
-#define MXT_VSP0SLVDMSCR 0xFF872120
-#define MXT_VSP1SLVDMSCR 0xFF872124
-#define MXT_VSPD0SLVDMSCR 0xFF872128
-#define MXT_VSPD1SLVDMSCR 0xFF87212C
-#define MXT_MAP1SLVDMSCR 0xFF872130
-#define MXT_MAP2SLVDMSCR 0xFF872134
-
-#define CCI_AXI_MMUS0DMSCR 0xFF882000
-#define CCI_AXI_SYX2DMSCR 0xFF882004
-#define CCI_AXI_MMURDMSCR 0xFF882008
-#define CCI_AXI_MMUDSDMSCR 0xFF88200C
-#define CCI_AXI_MMUMDMSCR 0xFF882010
-#define CCI_AXI_MXIDMSCR 0xFF882014
-#define CCI_AXI_MMUS1DMSCR 0xFF882018
-#define CCI_AXI_MMUMPDMSCR 0xFF88201C
-#define CCI_AXI_DVMDMSCR 0xFF882020
-#define CCI_AXI_CCISLVDMSCR 0xFF882100
-
-#define CCI_AXI_IPMMUIDVMCR 0xFF880400
-#define CCI_AXI_IPMMURDVMCR 0xFF880404
-#define CCI_AXI_IPMMUS0DVMCR 0xFF880408
-#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C
-#define CCI_AXI_IPMMUMPDVMCR 0xFF880410
-#define CCI_AXI_IPMMUDSDVMCR 0xFF880414
-#define CCI_AXI_AX2ADDRMASK 0xFF88041C
-
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-
-/* RWDT */
-struct r8a7790_rwdt {
- u32 rwtcnt; /* 0x00 */
- u32 rwtcsra; /* 0x04 */
- u16 rwtcsrb; /* 0x08 */
-};
-
-/* SWDT */
-struct r8a7790_swdt {
- u32 swtcnt; /* 0x00 */
- u32 swtcsra; /* 0x04 */
- u16 swtcsrb; /* 0x08 */
-};
-
-/* LBSC */
-struct r8a7790_lbsc {
- u32 cs0ctrl;
- u32 cs1ctrl;
- u32 ecs0ctrl;
- u32 ecs1ctrl;
- u32 ecs2ctrl;
- u32 ecs3ctrl;
- u32 ecs4ctrl;
- u32 ecs5ctrl;
- u32 dummy0[4]; /* 0x20 .. 0x2C */
- u32 cswcr0;
- u32 cswcr1;
- u32 ecswcr0;
- u32 ecswcr1;
- u32 ecswcr2;
- u32 ecswcr3;
- u32 ecswcr4;
- u32 ecswcr5;
- u32 exdmawcr0;
- u32 exdmawcr1;
- u32 exdmawcr2;
- u32 dummy1[9]; /* 0x5C .. 0x7C */
- u32 cspwcr0;
- u32 cspwcr1;
- u32 ecspwcr0;
- u32 ecspwcr1;
- u32 ecspwcr2;
- u32 ecspwcr3;
- u32 ecspwcr4;
- u32 ecspwcr5;
- u32 exwtsync;
- u32 dummy2[3]; /* 0xA4 .. 0xAC */
- u32 cs0bstctl;
- u32 cs0btph;
- u32 dummy3[2]; /* 0xB8 .. 0xBC */
- u32 cs1gdst;
- u32 ecs0gdst;
- u32 ecs1gdst;
- u32 ecs2gdst;
- u32 ecs3gdst;
- u32 ecs4gdst;
- u32 ecs5gdst;
- u32 dummy4[5]; /* 0xDC .. 0xEC */
- u32 exdmaset0;
- u32 exdmaset1;
- u32 exdmaset2;
- u32 dummy5[5]; /* 0xFC .. 0x10C */
- u32 exdmcr0;
- u32 exdmcr1;
- u32 exdmcr2;
- u32 dummy6[5]; /* 0x11C .. 0x12C */
- u32 bcintsr;
- u32 bcintcr;
- u32 bcintmr;
- u32 dummy7; /* 0x13C */
- u32 exbatlv;
- u32 exwtsts;
- u32 dummy8[14]; /* 0x148 .. 0x17C */
- u32 atacsctrl;
- u32 dummy9[15]; /* 0x184 .. 0x1BC */
- u32 exbct;
- u32 extct;
-};
-
-/* DBSC3 */
-struct r8a7790_dbsc3 {
- u32 dummy0[3]; /* 0x00 .. 0x08 */
- u32 dbstate1;
- u32 dbacen;
- u32 dbrfen;
- u32 dbcmd;
- u32 dbwait;
- u32 dbkind;
- u32 dbconf0;
- u32 dummy1[2]; /* 0x28 .. 0x2C */
- u32 dbphytype;
- u32 dummy2[3]; /* 0x34 .. 0x3C */
- u32 dbtr0;
- u32 dbtr1;
- u32 dbtr2;
- u32 dummy3; /* 0x4C */
- u32 dbtr3;
- u32 dbtr4;
- u32 dbtr5;
- u32 dbtr6;
- u32 dbtr7;
- u32 dbtr8;
- u32 dbtr9;
- u32 dbtr10;
- u32 dbtr11;
- u32 dbtr12;
- u32 dbtr13;
- u32 dbtr14;
- u32 dbtr15;
- u32 dbtr16;
- u32 dbtr17;
- u32 dbtr18;
- u32 dbtr19;
- u32 dummy4[7]; /* 0x94 .. 0xAC */
- u32 dbbl;
- u32 dummy5[3]; /* 0xB4 .. 0xBC */
- u32 dbadj0;
- u32 dummy6; /* 0xC4 */
- u32 dbadj2;
- u32 dummy7[5]; /* 0xCC .. 0xDC */
- u32 dbrfcnf0;
- u32 dbrfcnf1;
- u32 dbrfcnf2;
- u32 dummy8[2]; /* 0xEC .. 0xF0 */
- u32 dbcalcnf;
- u32 dbcaltr;
- u32 dummy9; /* 0xFC */
- u32 dbrnk0;
- u32 dummy10[31]; /* 0x104 .. 0x17C */
- u32 dbpdncnf;
- u32 dummy11[47]; /* 0x184 ..0x23C */
- u32 dbdfistat;
- u32 dbdficnt;
- u32 dummy12[14]; /* 0x248 .. 0x27C */
- u32 dbpdlck;
- u32 dummy13[3]; /* 0x284 .. 0x28C */
- u32 dbpdrga;
- u32 dummy14[3]; /* 0x294 .. 0x29C */
- u32 dbpdrgd;
- u32 dummy15[24]; /* 0x2A4 .. 0x300 */
- u32 dbbs0cnt1;
- u32 dummy16[30]; /* 0x308 .. 0x37C */
- u32 dbwt0cnf0;
- u32 dbwt0cnf1;
- u32 dbwt0cnf2;
- u32 dbwt0cnf3;
- u32 dbwt0cnf4;
-};
-
-/* GPIO */
-struct r8a7790_gpio {
- u32 iointsel;
- u32 inoutsel;
- u32 outdt;
- u32 indt;
- u32 intdt;
- u32 intclr;
- u32 intmsk;
- u32 posneg;
- u32 edglevel;
- u32 filonoff;
- u32 intmsks;
- u32 mskclrs;
- u32 outdtsel;
- u32 outdth;
- u32 outdtl;
- u32 bothedge;
-};
-
-/* S3C(QoS) */
-struct r8a7790_s3c {
- u32 s3cexcladdmsk;
- u32 s3cexclidmsk;
- u32 s3cadsplcr;
- u32 s3cmaar;
- u32 s3carcr11;
- u32 s3crorr;
- u32 s3cworr;
- u32 s3carcr22;
- u32 dummy1[2]; /* 0x20 .. 0x24 */
- u32 s3cmctr;
- u32 dummy2; /* 0x2C */
- u32 cconf0;
- u32 cconf1;
- u32 cconf2;
- u32 cconf3;
-};
-
-struct r8a7790_s3c_qos {
- u32 s3cqos0;
- u32 s3cqos1;
- u32 s3cqos2;
- u32 s3cqos3;
- u32 s3cqos4;
- u32 s3cqos5;
- u32 s3cqos6;
- u32 s3cqos7;
- u32 s3cqos8;
-};
-
-/* DBSC(QoS) */
-struct r8a7790_dbsc3_qos {
- u32 dblgcnt;
- u32 dbtmval0;
- u32 dbtmval1;
- u32 dbtmval2;
- u32 dbtmval3;
- u32 dbrqctr;
- u32 dbthres0;
- u32 dbthres1;
- u32 dbthres2;
- u32 dummy0; /* 0x24 */
- u32 dblgqon;
-};
-
-/* MXI(QoS) */
-struct r8a7790_mxi {
- u32 mxsaar0;
- u32 mxsaar1;
- u32 dummy0[7]; /* 0x08 .. 0x20 */
- u32 mxaxiracr;
- u32 mxs3cracr;
- u32 dummy1[2]; /* 0x2C .. 0x30 */
- u32 mxaxiwacr;
- u32 mxs3cwacr;
- u32 dummy2; /* 0x3C */
- u32 mxrtcr;
- u32 mxwtcr;
-};
-
-struct r8a7790_mxi_qos {
- u32 vspdu0;
- u32 vspdu1;
- u32 du0;
- u32 du1;
-};
-
-/* AXI(QoS) */
-struct r8a7790_axi_qos {
- u32 qosconf;
- u32 qosctset0;
- u32 qosctset1;
- u32 qosctset2;
- u32 qosctset3;
- u32 qosreqctr;
- u32 qosthres0;
- u32 qosthres1;
- u32 qosthres2;
- u32 qosqon;
-};
+#include "rcar-base.h"
-#endif
+#define R8A7790_CUT_ES2X 2
+#define IS_R8A7790_ES2() \
+ (rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X)
#endif /* __ASM_ARCH_R8A7790_H */
/*
* arch/arm/include/asm/arch-rmobile/r8a7791.h
*
- * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
- */
+*/
#ifndef __ASM_ARCH_R8A7791_H
#define __ASM_ARCH_R8A7791_H
+#include "rcar-base.h"
/*
- * R8A7791 I/O Addresses
+ * R-Car (R8A7791) I/O Addresses
*/
-#define RWDT_BASE 0xE6020000
-#define SWDT_BASE 0xE6030000
-#define LBSC_BASE 0xFEC00200
-#define DBSC3_0_BASE 0xE6790000
-#define DBSC3_1_BASE 0xE67A0000
-#define TMU_BASE 0xE61E0000
-#define GPIO5_BASE 0xE6055000
-#define SH_QSPI_BASE 0xE6B10000
-
-#define S3C_BASE 0xE6784000
-#define S3C_INT_BASE 0xE6784A00
-#define S3C_MEDIA_BASE 0xE6784B00
-
-#define S3C_QOS_DCACHE_BASE 0xE6784BDC
-#define S3C_QOS_CCI0_BASE 0xE6784C00
-#define S3C_QOS_CCI1_BASE 0xE6784C24
-#define S3C_QOS_MXI_BASE 0xE6784C48
-#define S3C_QOS_AXI_BASE 0xE6784C6C
-
-#define DBSC3_0_QOS_R0_BASE 0xE6791000
-#define DBSC3_0_QOS_R1_BASE 0xE6791100
-#define DBSC3_0_QOS_R2_BASE 0xE6791200
-#define DBSC3_0_QOS_R3_BASE 0xE6791300
-#define DBSC3_0_QOS_R4_BASE 0xE6791400
-#define DBSC3_0_QOS_R5_BASE 0xE6791500
-#define DBSC3_0_QOS_R6_BASE 0xE6791600
-#define DBSC3_0_QOS_R7_BASE 0xE6791700
-#define DBSC3_0_QOS_R8_BASE 0xE6791800
-#define DBSC3_0_QOS_R9_BASE 0xE6791900
-#define DBSC3_0_QOS_R10_BASE 0xE6791A00
-#define DBSC3_0_QOS_R11_BASE 0xE6791B00
-#define DBSC3_0_QOS_R12_BASE 0xE6791C00
-#define DBSC3_0_QOS_R13_BASE 0xE6791D00
-#define DBSC3_0_QOS_R14_BASE 0xE6791E00
-#define DBSC3_0_QOS_R15_BASE 0xE6791F00
-#define DBSC3_0_QOS_W0_BASE 0xE6792000
-#define DBSC3_0_QOS_W1_BASE 0xE6792100
-#define DBSC3_0_QOS_W2_BASE 0xE6792200
-#define DBSC3_0_QOS_W3_BASE 0xE6792300
-#define DBSC3_0_QOS_W4_BASE 0xE6792400
-#define DBSC3_0_QOS_W5_BASE 0xE6792500
-#define DBSC3_0_QOS_W6_BASE 0xE6792600
-#define DBSC3_0_QOS_W7_BASE 0xE6792700
-#define DBSC3_0_QOS_W8_BASE 0xE6792800
-#define DBSC3_0_QOS_W9_BASE 0xE6792900
-#define DBSC3_0_QOS_W10_BASE 0xE6792A00
-#define DBSC3_0_QOS_W11_BASE 0xE6792B00
-#define DBSC3_0_QOS_W12_BASE 0xE6792C00
-#define DBSC3_0_QOS_W13_BASE 0xE6792D00
-#define DBSC3_0_QOS_W14_BASE 0xE6792E00
-#define DBSC3_0_QOS_W15_BASE 0xE6792F00
-
#define DBSC3_1_QOS_R0_BASE 0xE67A1000
#define DBSC3_1_QOS_R1_BASE 0xE67A1100
#define DBSC3_1_QOS_R2_BASE 0xE67A1200
#define DBSC3_1_QOS_W14_BASE 0xE67A2E00
#define DBSC3_1_QOS_W15_BASE 0xE67A2F00
-#define DBSC3_0_DBADJ2 0xE67900C8
-
-#define CCI_400_MAXOT_1 0xF0091110
-#define CCI_400_MAXOT_2 0xF0092110
-#define CCI_400_QOSCNTL_1 0xF009110C
-#define CCI_400_QOSCNTL_2 0xF009210C
-
-#define MXI_BASE 0xFE960000
-#define MXI_QOS_BASE 0xFE960300
-
-#define SYS_AXI_SYX64TO128_BASE 0xFF800300
-#define SYS_AXI_AVB_BASE 0xFF800340
-#define SYS_AXI_G2D_BASE 0xFF800540
-#define SYS_AXI_IMP0_BASE 0xFF800580
-#define SYS_AXI_IMP1_BASE 0xFF8005C0
-#define SYS_AXI_IMUX0_BASE 0xFF800600
-#define SYS_AXI_IMUX1_BASE 0xFF800640
-#define SYS_AXI_IMUX2_BASE 0xFF800680
-#define SYS_AXI_LBS_BASE 0xFF8006C0
-#define SYS_AXI_MMUDS_BASE 0xFF800700
-#define SYS_AXI_MMUM_BASE 0xFF800740
-#define SYS_AXI_MMUR_BASE 0xFF800780
-#define SYS_AXI_MMUS0_BASE 0xFF8007C0
-#define SYS_AXI_MMUS1_BASE 0xFF800800
-#define SYS_AXI_MTSB0_BASE 0xFF800880
-#define SYS_AXI_MTSB1_BASE 0xFF8008C0
-#define SYS_AXI_PCI_BASE 0xFF800900
-#define SYS_AXI_RTX_BASE 0xFF800940
-#define SYS_AXI_SDS0_BASE 0xFF800A80
-#define SYS_AXI_SDS1_BASE 0xFF800AC0
-#define SYS_AXI_USB20_BASE 0xFF800C00
-#define SYS_AXI_USB21_BASE 0xFF800C40
-#define SYS_AXI_USB22_BASE 0xFF800C80
-#define SYS_AXI_USB30_BASE 0xFF800CC0
-#define SYS_AXI_AX2M_BASE 0xFF800380
-#define SYS_AXI_CC50_BASE 0xFF8003C0
-#define SYS_AXI_CCI_BASE 0xFF800440
-#define SYS_AXI_CS_BASE 0xFF800480
-#define SYS_AXI_DDM_BASE 0xFF8004C0
-#define SYS_AXI_ETH_BASE 0xFF800500
-#define SYS_AXI_MPXM_BASE 0xFF800840
-#define SYS_AXI_SAT0_BASE 0xFF800980
-#define SYS_AXI_SAT1_BASE 0xFF8009C0
-#define SYS_AXI_SDM0_BASE 0xFF800A00
-#define SYS_AXI_SDM1_BASE 0xFF800A40
-#define SYS_AXI_TRAB_BASE 0xFF800B00
-#define SYS_AXI_UDM0_BASE 0xFF800B80
-#define SYS_AXI_UDM1_BASE 0xFF800BC0
-
-#define RT_AXI_SHX_BASE 0xFF810100
-#define RT_AXI_DBG_BASE 0xFF810140
-#define RT_AXI_RDM_BASE 0xFF810180
-#define RT_AXI_RDS_BASE 0xFF8101C0
-#define RT_AXI_RTX64TO128_BASE 0xFF810200
-#define RT_AXI_STPRO_BASE 0xFF810240
-#define RT_AXI_SY2RT_BASE 0xFF810280
-
-#define MP_AXI_ADSP_BASE 0xFF820100
-#define MP_AXI_ASDS0_BASE 0xFF8201C0
-#define MP_AXI_ASDS1_BASE 0xFF820200
-#define MP_AXI_MLP_BASE 0xFF820240
-#define MP_AXI_MMUMP_BASE 0xFF820280
-#define MP_AXI_SPU_BASE 0xFF8202C0
-#define MP_AXI_SPUC_BASE 0xFF820300
-
-#define SYS_AXI256_AXI128TO256_BASE 0xFF860100
-#define SYS_AXI256_SYX_BASE 0xFF860140
-#define SYS_AXI256_MPX_BASE 0xFF860180
-#define SYS_AXI256_MXI_BASE 0xFF8601C0
-
-#define CCI_AXI_MMUS0_BASE 0xFF880100
-#define CCI_AXI_SYX2_BASE 0xFF880140
-#define CCI_AXI_MMUR_BASE 0xFF880180
-#define CCI_AXI_MMUDS_BASE 0xFF8801C0
-#define CCI_AXI_MMUM_BASE 0xFF880200
-#define CCI_AXI_MXI_BASE 0xFF880240
-#define CCI_AXI_MMUS1_BASE 0xFF880280
-#define CCI_AXI_MMUMP_BASE 0xFF8802C0
-
-#define MEDIA_AXI_MXR_BASE 0xFE960080
-#define MEDIA_AXI_MXW_BASE 0xFE9600C0
-#define MEDIA_AXI_JPR_BASE 0xFE964100
-#define MEDIA_AXI_JPW_BASE 0xFE966100
-#define MEDIA_AXI_GCU0R_BASE 0xFE964140
-#define MEDIA_AXI_GCU0W_BASE 0xFE966140
-#define MEDIA_AXI_GCU1R_BASE 0xFE964180
-#define MEDIA_AXI_GCU1W_BASE 0xFE966180
-#define MEDIA_AXI_TDMR_BASE 0xFE964500
-#define MEDIA_AXI_TDMW_BASE 0xFE966500
-#define MEDIA_AXI_VSP0CR_BASE 0xFE964540
-#define MEDIA_AXI_VSP0CW_BASE 0xFE966540
-#define MEDIA_AXI_VSP1CR_BASE 0xFE964580
-#define MEDIA_AXI_VSP1CW_BASE 0xFE966580
-#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0
-#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0
-#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600
-#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600
-#define MEDIA_AXI_VIN0W_BASE 0xFE966900
-#define MEDIA_AXI_VSP0R_BASE 0xFE964D00
-#define MEDIA_AXI_VSP0W_BASE 0xFE966D00
-#define MEDIA_AXI_FDP0R_BASE 0xFE964D40
-#define MEDIA_AXI_FDP0W_BASE 0xFE966D40
-#define MEDIA_AXI_IMSR_BASE 0xFE964D80
-#define MEDIA_AXI_IMSW_BASE 0xFE966D80
-#define MEDIA_AXI_VSP1R_BASE 0xFE965100
-#define MEDIA_AXI_VSP1W_BASE 0xFE967100
-#define MEDIA_AXI_FDP1R_BASE 0xFE965140
-#define MEDIA_AXI_FDP1W_BASE 0xFE967140
-#define MEDIA_AXI_IMRR_BASE 0xFE965180
-#define MEDIA_AXI_IMRW_BASE 0xFE967180
-#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0
-#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0
-#define MEDIA_AXI_VSPD0R_BASE 0xFE965500
-#define MEDIA_AXI_VSPD0W_BASE 0xFE967500
-#define MEDIA_AXI_VSPD1R_BASE 0xFE965540
-#define MEDIA_AXI_VSPD1W_BASE 0xFE967540
-#define MEDIA_AXI_DU0R_BASE 0xFE965580
-#define MEDIA_AXI_DU0W_BASE 0xFE967580
-#define MEDIA_AXI_DU1R_BASE 0xFE9655C0
-#define MEDIA_AXI_DU1W_BASE 0xFE9675C0
-#define MEDIA_AXI_VCP0CR_BASE 0xFE965900
-#define MEDIA_AXI_VCP0CW_BASE 0xFE967900
-#define MEDIA_AXI_VCP0VR_BASE 0xFE965940
-#define MEDIA_AXI_VCP0VW_BASE 0xFE967940
-#define MEDIA_AXI_VPC0R_BASE 0xFE965980
-#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00
-#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00
-#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40
-#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40
-#define MEDIA_AXI_VPC1R_BASE 0xFE965D80
-
-#define SYS_AXI_AVBDMSCR 0xFF802000
-#define SYS_AXI_SYX2DMSCR 0xFF802004
-#define SYS_AXI_CC50DMSCR 0xFF802008
-#define SYS_AXI_CC51DMSCR 0xFF80200C
-#define SYS_AXI_CCIDMSCR 0xFF802010
-#define SYS_AXI_CSDMSCR 0xFF802014
-#define SYS_AXI_DDMDMSCR 0xFF802018
-#define SYS_AXI_ETHDMSCR 0xFF80201C
-#define SYS_AXI_G2DDMSCR 0xFF802020
-#define SYS_AXI_IMP0DMSCR 0xFF802024
-#define SYS_AXI_IMP1DMSCR 0xFF802028
-#define SYS_AXI_LBSDMSCR 0xFF80202C
-#define SYS_AXI_MMUDSDMSCR 0xFF802030
-#define SYS_AXI_MMUMXDMSCR 0xFF802034
-#define SYS_AXI_MMURDDMSCR 0xFF802038
-#define SYS_AXI_MMUS0DMSCR 0xFF80203C
-#define SYS_AXI_MMUS1DMSCR 0xFF802040
-#define SYS_AXI_MPXDMSCR 0xFF802044
-#define SYS_AXI_MTSB0DMSCR 0xFF802048
-#define SYS_AXI_MTSB1DMSCR 0xFF80204C
-#define SYS_AXI_PCIDMSCR 0xFF802050
-#define SYS_AXI_RTXDMSCR 0xFF802054
-#define SYS_AXI_SAT0DMSCR 0xFF802058
-#define SYS_AXI_SAT1DMSCR 0xFF80205C
-#define SYS_AXI_SDM0DMSCR 0xFF802060
-#define SYS_AXI_SDM1DMSCR 0xFF802064
-#define SYS_AXI_SDS0DMSCR 0xFF802068
-#define SYS_AXI_SDS1DMSCR 0xFF80206C
-#define SYS_AXI_ETRABDMSCR 0xFF802070
-#define SYS_AXI_ETRKFDMSCR 0xFF802074
-#define SYS_AXI_UDM0DMSCR 0xFF802078
-#define SYS_AXI_UDM1DMSCR 0xFF80207C
-#define SYS_AXI_USB20DMSCR 0xFF802080
-#define SYS_AXI_USB21DMSCR 0xFF802084
-#define SYS_AXI_USB22DMSCR 0xFF802088
-#define SYS_AXI_USB30DMSCR 0xFF80208C
-#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100
-#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104
-#define SYS_AXI_AVBSLVDMSCR 0xFF802108
-#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C
-#define SYS_AXI_ETHSLVDMSCR 0xFF802110
-#define SYS_AXI_GICSLVDMSCR 0xFF802114
-#define SYS_AXI_IMPSLVDMSCR 0xFF802118
-#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C
-#define SYS_AXI_IMX1SLVDMSCR 0xFF802120
-#define SYS_AXI_IMX2SLVDMSCR 0xFF802124
-#define SYS_AXI_LBSSLVDMSCR 0xFF802128
-#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C
-#define SYS_AXI_MMC1SLVDMSCR 0xFF802130
-#define SYS_AXI_MPXSLVDMSCR 0xFF802134
-#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138
-#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C
-#define SYS_AXI_MXTSLVDMSCR 0xFF802140
-#define SYS_AXI_PCISLVDMSCR 0xFF802144
-#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148
-#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C
-#define SYS_AXI_RTXSLVDMSCR 0xFF802150
-#define SYS_AXI_SAT0SLVDMSCR 0xFF802168
-#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C
-#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170
-#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174
-#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178
-#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C
-#define SYS_AXI_SGXSLVDMSCR 0xFF802180
-#define SYS_AXI_STBSLVDMSCR 0xFF802188
-#define SYS_AXI_STMSLVDMSCR 0xFF80218C
-#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194
-#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198
-#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C
-#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0
-#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4
-#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8
-#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC
-
-#define RT_AXI_CBMDMSCR 0xFF812000
-#define RT_AXI_DBDMSCR 0xFF812004
-#define RT_AXI_RDMDMSCR 0xFF812008
-#define RT_AXI_RDSDMSCR 0xFF81200C
-#define RT_AXI_STRDMSCR 0xFF812010
-#define RT_AXI_SY2RTDMSCR 0xFF812014
-#define RT_AXI_CBSSLVDMSCR 0xFF812100
-#define RT_AXI_DBSSLVDMSCR 0xFF812104
-#define RT_AXI_RTAP1SLVDMSCR 0xFF812108
-#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C
-#define RT_AXI_RTAP3SLVDMSCR 0xFF812110
-#define RT_AXI_RT2SYSLVDMSCR 0xFF812114
-#define RT_AXI_A128TO64SLVDMSCR 0xFF812118
-#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C
-#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120
-#define RT_AXI_UTLBRSLVDMSCR 0xFF812128
-
-#define MP_AXI_ADSPDMSCR 0xFF822000
-#define MP_AXI_ASDM0DMSCR 0xFF822004
-#define MP_AXI_ASDM1DMSCR 0xFF822008
-#define MP_AXI_ASDS0DMSCR 0xFF82200C
-#define MP_AXI_ASDS1DMSCR 0xFF822010
-#define MP_AXI_MLPDMSCR 0xFF822014
-#define MP_AXI_MMUMPDMSCR 0xFF822018
-#define MP_AXI_SPUDMSCR 0xFF82201C
-#define MP_AXI_SPUCDMSCR 0xFF822020
-#define MP_AXI_SY2MPDMSCR 0xFF822024
-#define MP_AXI_ADSPSLVDMSCR 0xFF822100
-#define MP_AXI_MLMSLVDMSCR 0xFF822104
-#define MP_AXI_MPAP4SLVDMSCR 0xFF822108
-#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C
-#define MP_AXI_MPAP6SLVDMSCR 0xFF822110
-#define MP_AXI_MPAP7SLVDMSCR 0xFF822114
-#define MP_AXI_MP2SYSLVDMSCR 0xFF822118
-#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C
-#define MP_AXI_MPXAPSLVDMSCR 0xFF822124
-#define MP_AXI_SPUSLVDMSCR 0xFF822128
-#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C
-
-#define ADM_AXI_ASDM0DMSCR 0xFF842000
-#define ADM_AXI_ASDM1DMSCR 0xFF842004
-#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104
-#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108
-#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C
-
-#define DM_AXI_RDMDMSCR 0xFF852000
-#define DM_AXI_SDM0DMSCR 0xFF852004
-#define DM_AXI_SDM1DMSCR 0xFF852008
-#define DM_AXI_MMAP0SLVDMSCR 0xFF852100
-#define DM_AXI_MMAP1SLVDMSCR 0xFF852104
-#define DM_AXI_QSPAPSLVDMSCR 0xFF852108
-#define DM_AXI_RAP4SLVDMSCR 0xFF85210C
-#define DM_AXI_RAP5SLVDMSCR 0xFF852110
-#define DM_AXI_SAP4SLVDMSCR 0xFF852114
-#define DM_AXI_SAP5SLVDMSCR 0xFF852118
-#define DM_AXI_SAP6SLVDMSCR 0xFF85211C
-#define DM_AXI_SAP65SLVDMSCR 0xFF852120
-#define DM_AXI_SDAP0SLVDMSCR 0xFF852124
-#define DM_AXI_SDAP1SLVDMSCR 0xFF852128
-#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C
-#define DM_AXI_SDAP3SLVDMSCR 0xFF852130
-
-#define SYS_AXI256_SYXDMSCR 0xFF862000
-#define SYS_AXI256_MPXDMSCR 0xFF862004
-#define SYS_AXI256_MXIDMSCR 0xFF862008
-#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100
-#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104
-#define SYS_AXI256_SYXSLVDMSCR 0xFF862108
-#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C
-#define SYS_AXI256_S3CSLVDMSCR 0xFF862110
-
-#define MXT_SYXDMSCR 0xFF872000
-#define MXT_CMM0SLVDMSCR 0xFF872100
-#define MXT_CMM1SLVDMSCR 0xFF872104
-#define MXT_CMM2SLVDMSCR 0xFF872108
-#define MXT_FDPSLVDMSCR 0xFF87210C
-#define MXT_IMRSLVDMSCR 0xFF872110
-#define MXT_VINSLVDMSCR 0xFF872114
-#define MXT_VPC0SLVDMSCR 0xFF872118
-#define MXT_VPC1SLVDMSCR 0xFF87211C
-#define MXT_VSP0SLVDMSCR 0xFF872120
-#define MXT_VSP1SLVDMSCR 0xFF872124
-#define MXT_VSPD0SLVDMSCR 0xFF872128
-#define MXT_VSPD1SLVDMSCR 0xFF87212C
-#define MXT_MAP1SLVDMSCR 0xFF872130
-#define MXT_MAP2SLVDMSCR 0xFF872134
-
-#define CCI_AXI_MMUS0DMSCR 0xFF882000
-#define CCI_AXI_SYX2DMSCR 0xFF882004
-#define CCI_AXI_MMURDMSCR 0xFF882008
-#define CCI_AXI_MMUDSDMSCR 0xFF88200C
-#define CCI_AXI_MMUMDMSCR 0xFF882010
-#define CCI_AXI_MXIDMSCR 0xFF882014
-#define CCI_AXI_MMUS1DMSCR 0xFF882018
-#define CCI_AXI_MMUMPDMSCR 0xFF88201C
-#define CCI_AXI_DVMDMSCR 0xFF882020
-#define CCI_AXI_CCISLVDMSCR 0xFF882100
-
-#define CCI_AXI_IPMMUIDVMCR 0xFF880400
-#define CCI_AXI_IPMMURDVMCR 0xFF880404
-#define CCI_AXI_IPMMUS0DVMCR 0xFF880408
-#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C
-#define CCI_AXI_IPMMUMPDVMCR 0xFF880410
-#define CCI_AXI_IPMMUDSDVMCR 0xFF880414
-#define CCI_AXI_AX2ADDRMASK 0xFF88041C
-
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-
-/* RWDT */
-struct r8a7791_rwdt {
- u32 rwtcnt; /* 0x00 */
- u32 rwtcsra; /* 0x04 */
- u16 rwtcsrb; /* 0x08 */
-};
-
-/* SWDT */
-struct r8a7791_swdt {
- u32 swtcnt; /* 0x00 */
- u32 swtcsra; /* 0x04 */
- u16 swtcsrb; /* 0x08 */
-};
-
-/* LBSC */
-struct r8a7791_lbsc {
- u32 cs0ctrl;
- u32 cs1ctrl;
- u32 ecs0ctrl;
- u32 ecs1ctrl;
- u32 ecs2ctrl;
- u32 ecs3ctrl;
- u32 ecs4ctrl;
- u32 ecs5ctrl;
- u32 dummy0[4]; /* 0x20 .. 0x2C */
- u32 cswcr0;
- u32 cswcr1;
- u32 ecswcr0;
- u32 ecswcr1;
- u32 ecswcr2;
- u32 ecswcr3;
- u32 ecswcr4;
- u32 ecswcr5;
- u32 exdmawcr0;
- u32 exdmawcr1;
- u32 exdmawcr2;
- u32 dummy1[9]; /* 0x5C .. 0x7C */
- u32 cspwcr0;
- u32 cspwcr1;
- u32 ecspwcr0;
- u32 ecspwcr1;
- u32 ecspwcr2;
- u32 ecspwcr3;
- u32 ecspwcr4;
- u32 ecspwcr5;
- u32 exwtsync;
- u32 dummy2[3]; /* 0xA4 .. 0xAC */
- u32 cs0bstctl;
- u32 cs0btph;
- u32 dummy3[2]; /* 0xB8 .. 0xBC */
- u32 cs1gdst;
- u32 ecs0gdst;
- u32 ecs1gdst;
- u32 ecs2gdst;
- u32 ecs3gdst;
- u32 ecs4gdst;
- u32 ecs5gdst;
- u32 dummy4[5]; /* 0xDC .. 0xEC */
- u32 exdmaset0;
- u32 exdmaset1;
- u32 exdmaset2;
- u32 dummy5[5]; /* 0xFC .. 0x10C */
- u32 exdmcr0;
- u32 exdmcr1;
- u32 exdmcr2;
- u32 dummy6[5]; /* 0x11C .. 0x12C */
- u32 bcintsr;
- u32 bcintcr;
- u32 bcintmr;
- u32 dummy7; /* 0x13C */
- u32 exbatlv;
- u32 exwtsts;
- u32 dummy8[14]; /* 0x148 .. 0x17C */
- u32 atacsctrl;
- u32 dummy9[15]; /* 0x184 .. 0x1BC */
- u32 exbct;
- u32 extct;
-};
-
-/* DBSC3 */
-struct r8a7791_dbsc3 {
- u32 dummy0[3]; /* 0x00 .. 0x08 */
- u32 dbstate1;
- u32 dbacen;
- u32 dbrfen;
- u32 dbcmd;
- u32 dbwait;
- u32 dbkind;
- u32 dbconf0;
- u32 dummy1[2]; /* 0x28 .. 0x2C */
- u32 dbphytype;
- u32 dummy2[3]; /* 0x34 .. 0x3C */
- u32 dbtr0;
- u32 dbtr1;
- u32 dbtr2;
- u32 dummy3; /* 0x4C */
- u32 dbtr3;
- u32 dbtr4;
- u32 dbtr5;
- u32 dbtr6;
- u32 dbtr7;
- u32 dbtr8;
- u32 dbtr9;
- u32 dbtr10;
- u32 dbtr11;
- u32 dbtr12;
- u32 dbtr13;
- u32 dbtr14;
- u32 dbtr15;
- u32 dbtr16;
- u32 dbtr17;
- u32 dbtr18;
- u32 dbtr19;
- u32 dummy4[7]; /* 0x94 .. 0xAC */
- u32 dbbl;
- u32 dummy5[3]; /* 0xB4 .. 0xBC */
- u32 dbadj0;
- u32 dummy6; /* 0xC4 */
- u32 dbadj2;
- u32 dummy7[5]; /* 0xCC .. 0xDC */
- u32 dbrfcnf0;
- u32 dbrfcnf1;
- u32 dbrfcnf2;
- u32 dummy8[2]; /* 0xEC .. 0xF0 */
- u32 dbcalcnf;
- u32 dbcaltr;
- u32 dummy9; /* 0xFC */
- u32 dbrnk0;
- u32 dummy10[31]; /* 0x104 .. 0x17C */
- u32 dbpdncnf;
- u32 dummy11[47]; /* 0x184 ..0x23C */
- u32 dbdfistat;
- u32 dbdficnt;
- u32 dummy12[14]; /* 0x248 .. 0x27C */
- u32 dbpdlck;
- u32 dummy13[3]; /* 0x284 .. 0x28C */
- u32 dbpdrga;
- u32 dummy14[3]; /* 0x294 .. 0x29C */
- u32 dbpdrgd;
- u32 dummy15[24]; /* 0x2A4 .. 0x300 */
- u32 dbbs0cnt1;
- u32 dummy16[30]; /* 0x308 .. 0x37C */
- u32 dbwt0cnf0;
- u32 dbwt0cnf1;
- u32 dbwt0cnf2;
- u32 dbwt0cnf3;
- u32 dbwt0cnf4;
-};
-
-/* GPIO */
-struct r8a7791_gpio {
- u32 iointsel;
- u32 inoutsel;
- u32 outdt;
- u32 indt;
- u32 intdt;
- u32 intclr;
- u32 intmsk;
- u32 posneg;
- u32 edglevel;
- u32 filonoff;
- u32 intmsks;
- u32 mskclrs;
- u32 outdtsel;
- u32 outdth;
- u32 outdtl;
- u32 bothedge;
-};
-
-/* S3C(QoS) */
-struct r8a7791_s3c {
- u32 s3cexcladdmsk;
- u32 s3cexclidmsk;
- u32 s3cadsplcr;
- u32 s3cmaar;
- u32 dummy0; /* 0x10 */
- u32 s3crorr;
- u32 s3cworr;
- u32 s3carcr22;
- u32 dummy1[2]; /* 0x20 .. 0x24 */
- u32 s3cmctr;
- u32 dummy2; /* 0x2C */
- u32 cconf0;
- u32 cconf1;
- u32 cconf2;
- u32 cconf3;
-};
-
-struct r8a7791_s3c_qos {
- u32 s3cqos0;
- u32 s3cqos1;
- u32 s3cqos2;
- u32 s3cqos3;
- u32 s3cqos4;
- u32 s3cqos5;
- u32 s3cqos6;
- u32 s3cqos7;
- u32 s3cqos8;
-};
-
-/* DBSC(QoS) */
-struct r8a7791_dbsc3_qos {
- u32 dblgcnt;
- u32 dbtmval0;
- u32 dbtmval1;
- u32 dbtmval2;
- u32 dbtmval3;
- u32 dbrqctr;
- u32 dbthres0;
- u32 dbthres1;
- u32 dbthres2;
- u32 dummy0; /* 0x24 */
- u32 dblgqon;
-};
-
-/* MXI(QoS) */
-struct r8a7791_mxi {
- u32 mxsaar0;
- u32 mxsaar1;
- u32 dummy0[8]; /* 0x08 .. 0x24 */
- u32 mxs3cracr;
- u32 dummy1[3]; /* 0x2C .. 0x34 */
- u32 mxs3cwacr;
- u32 dummy2; /* 0x3C */
- u32 mxrtcr;
- u32 mxwtcr;
-};
-
-struct r8a7791_mxi_qos {
- u32 vspdu0;
- u32 vspdu1;
- u32 du0;
- u32 du1;
-};
-
-/* AXI(QoS) */
-struct r8a7791_axi_qos {
- u32 qosconf;
- u32 qosctset0;
- u32 qosctset1;
- u32 qosctset2;
- u32 qosctset3;
- u32 qosreqctr;
- u32 qosthres0;
- u32 qosthres1;
- u32 qosthres2;
- u32 qosqon;
-};
-
-#endif
+#define R8A7791_CUT_ES2X 2
+#define IS_R8A7791_ES2() \
+ (rmobile_get_cpu_rev_integer() == R8A7791_CUT_ES2X)
#endif /* __ASM_ARCH_R8A7791_H */
--- /dev/null
+/*
+ * arch/arm/include/asm/arch-rmobile/rcar-base.h
+ *
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+*/
+
+#ifndef __ASM_ARCH_RCAR_BASE_H
+#define __ASM_ARCH_RCAR_BASE_H
+
+/*
+ * R-Car (R8A7790/R8A7791) I/O Addresses
+ */
+#define RWDT_BASE 0xE6020000
+#define SWDT_BASE 0xE6030000
+#define LBSC_BASE 0xFEC00200
+#define DBSC3_0_BASE 0xE6790000
+#define DBSC3_1_BASE 0xE67A0000
+#define TMU_BASE 0xE61E0000
+#define GPIO5_BASE 0xE6055000
+#define SH_QSPI_BASE 0xE6B10000
+
+#define S3C_BASE 0xE6784000
+#define S3C_INT_BASE 0xE6784A00
+#define S3C_MEDIA_BASE 0xE6784B00
+
+#define S3C_QOS_DCACHE_BASE 0xE6784BDC
+#define S3C_QOS_CCI0_BASE 0xE6784C00
+#define S3C_QOS_CCI1_BASE 0xE6784C24
+#define S3C_QOS_MXI_BASE 0xE6784C48
+#define S3C_QOS_AXI_BASE 0xE6784C6C
+
+#define DBSC3_0_QOS_R0_BASE 0xE6791000
+#define DBSC3_0_QOS_R1_BASE 0xE6791100
+#define DBSC3_0_QOS_R2_BASE 0xE6791200
+#define DBSC3_0_QOS_R3_BASE 0xE6791300
+#define DBSC3_0_QOS_R4_BASE 0xE6791400
+#define DBSC3_0_QOS_R5_BASE 0xE6791500
+#define DBSC3_0_QOS_R6_BASE 0xE6791600
+#define DBSC3_0_QOS_R7_BASE 0xE6791700
+#define DBSC3_0_QOS_R8_BASE 0xE6791800
+#define DBSC3_0_QOS_R9_BASE 0xE6791900
+#define DBSC3_0_QOS_R10_BASE 0xE6791A00
+#define DBSC3_0_QOS_R11_BASE 0xE6791B00
+#define DBSC3_0_QOS_R12_BASE 0xE6791C00
+#define DBSC3_0_QOS_R13_BASE 0xE6791D00
+#define DBSC3_0_QOS_R14_BASE 0xE6791E00
+#define DBSC3_0_QOS_R15_BASE 0xE6791F00
+#define DBSC3_0_QOS_W0_BASE 0xE6792000
+#define DBSC3_0_QOS_W1_BASE 0xE6792100
+#define DBSC3_0_QOS_W2_BASE 0xE6792200
+#define DBSC3_0_QOS_W3_BASE 0xE6792300
+#define DBSC3_0_QOS_W4_BASE 0xE6792400
+#define DBSC3_0_QOS_W5_BASE 0xE6792500
+#define DBSC3_0_QOS_W6_BASE 0xE6792600
+#define DBSC3_0_QOS_W7_BASE 0xE6792700
+#define DBSC3_0_QOS_W8_BASE 0xE6792800
+#define DBSC3_0_QOS_W9_BASE 0xE6792900
+#define DBSC3_0_QOS_W10_BASE 0xE6792A00
+#define DBSC3_0_QOS_W11_BASE 0xE6792B00
+#define DBSC3_0_QOS_W12_BASE 0xE6792C00
+#define DBSC3_0_QOS_W13_BASE 0xE6792D00
+#define DBSC3_0_QOS_W14_BASE 0xE6792E00
+#define DBSC3_0_QOS_W15_BASE 0xE6792F00
+#define DBSC3_0_DBADJ2 0xE67900C8
+
+#define CCI_400_MAXOT_1 0xF0091110
+#define CCI_400_MAXOT_2 0xF0092110
+#define CCI_400_QOSCNTL_1 0xF009110C
+#define CCI_400_QOSCNTL_2 0xF009210C
+
+#define MXI_BASE 0xFE960000
+#define MXI_QOS_BASE 0xFE960300
+
+#define SYS_AXI_SYX64TO128_BASE 0xFF800300
+#define SYS_AXI_AVB_BASE 0xFF800340
+#define SYS_AXI_G2D_BASE 0xFF800540
+#define SYS_AXI_IMP0_BASE 0xFF800580
+#define SYS_AXI_IMP1_BASE 0xFF8005C0
+#define SYS_AXI_IMUX0_BASE 0xFF800600
+#define SYS_AXI_IMUX1_BASE 0xFF800640
+#define SYS_AXI_IMUX2_BASE 0xFF800680
+#define SYS_AXI_LBS_BASE 0xFF8006C0
+#define SYS_AXI_MMUDS_BASE 0xFF800700
+#define SYS_AXI_MMUM_BASE 0xFF800740
+#define SYS_AXI_MMUR_BASE 0xFF800780
+#define SYS_AXI_MMUS0_BASE 0xFF8007C0
+#define SYS_AXI_MMUS1_BASE 0xFF800800
+#define SYS_AXI_MTSB0_BASE 0xFF800880
+#define SYS_AXI_MTSB1_BASE 0xFF8008C0
+#define SYS_AXI_PCI_BASE 0xFF800900
+#define SYS_AXI_RTX_BASE 0xFF800940
+#define SYS_AXI_SDS0_BASE 0xFF800A80
+#define SYS_AXI_SDS1_BASE 0xFF800AC0
+#define SYS_AXI_USB20_BASE 0xFF800C00
+#define SYS_AXI_USB21_BASE 0xFF800C40
+#define SYS_AXI_USB22_BASE 0xFF800C80
+#define SYS_AXI_USB30_BASE 0xFF800CC0
+#define SYS_AXI_AX2M_BASE 0xFF800380
+#define SYS_AXI_CC50_BASE 0xFF8003C0
+#define SYS_AXI_CCI_BASE 0xFF800440
+#define SYS_AXI_CS_BASE 0xFF800480
+#define SYS_AXI_DDM_BASE 0xFF8004C0
+#define SYS_AXI_ETH_BASE 0xFF800500
+#define SYS_AXI_MPXM_BASE 0xFF800840
+#define SYS_AXI_SAT0_BASE 0xFF800980
+#define SYS_AXI_SAT1_BASE 0xFF8009C0
+#define SYS_AXI_SDM0_BASE 0xFF800A00
+#define SYS_AXI_SDM1_BASE 0xFF800A40
+#define SYS_AXI_TRAB_BASE 0xFF800B00
+#define SYS_AXI_UDM0_BASE 0xFF800B80
+#define SYS_AXI_UDM1_BASE 0xFF800BC0
+
+#define RT_AXI_SHX_BASE 0xFF810100
+#define RT_AXI_DBG_BASE 0xFF810140 /* R8A7791 only */
+#define RT_AXI_RDM_BASE 0xFF810180 /* R8A7791 only */
+#define RT_AXI_RDS_BASE 0xFF8101C0
+#define RT_AXI_RTX64TO128_BASE 0xFF810200
+#define RT_AXI_STPRO_BASE 0xFF810240
+#define RT_AXI_SY2RT_BASE 0xFF810280 /* R8A7791 only */
+
+#define MP_AXI_ADSP_BASE 0xFF820100
+#define MP_AXI_ASDS0_BASE 0xFF8201C0
+#define MP_AXI_ASDS1_BASE 0xFF820200
+#define MP_AXI_MLP_BASE 0xFF820240
+#define MP_AXI_MMUMP_BASE 0xFF820280
+#define MP_AXI_SPU_BASE 0xFF8202C0
+#define MP_AXI_SPUC_BASE 0xFF820300
+
+#define SYS_AXI256_AXI128TO256_BASE 0xFF860100
+#define SYS_AXI256_SYX_BASE 0xFF860140
+#define SYS_AXI256_MPX_BASE 0xFF860180
+#define SYS_AXI256_MXI_BASE 0xFF8601C0
+
+#define CCI_AXI_MMUS0_BASE 0xFF880100
+#define CCI_AXI_SYX2_BASE 0xFF880140
+#define CCI_AXI_MMUR_BASE 0xFF880180
+#define CCI_AXI_MMUDS_BASE 0xFF8801C0
+#define CCI_AXI_MMUM_BASE 0xFF880200
+#define CCI_AXI_MXI_BASE 0xFF880240
+#define CCI_AXI_MMUS1_BASE 0xFF880280
+#define CCI_AXI_MMUMP_BASE 0xFF8802C0
+
+#define MEDIA_AXI_MXR_BASE 0xFE960080 /* R8A7791 only */
+#define MEDIA_AXI_MXW_BASE 0xFE9600C0 /* R8A7791 only */
+#define MEDIA_AXI_JPR_BASE 0xFE964100
+#define MEDIA_AXI_JPW_BASE 0xFE966100
+#define MEDIA_AXI_GCU0R_BASE 0xFE964140
+#define MEDIA_AXI_GCU0W_BASE 0xFE966140
+#define MEDIA_AXI_GCU1R_BASE 0xFE964180
+#define MEDIA_AXI_GCU1W_BASE 0xFE966180
+#define MEDIA_AXI_TDMR_BASE 0xFE964500
+#define MEDIA_AXI_TDMW_BASE 0xFE966500
+#define MEDIA_AXI_VSP0CR_BASE 0xFE964540
+#define MEDIA_AXI_VSP0CW_BASE 0xFE966540
+#define MEDIA_AXI_VSP1CR_BASE 0xFE964580
+#define MEDIA_AXI_VSP1CW_BASE 0xFE966580
+#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0
+#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0
+#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600
+#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600
+#define MEDIA_AXI_VIN0W_BASE 0xFE966900
+#define MEDIA_AXI_VSP0R_BASE 0xFE964D00
+#define MEDIA_AXI_VSP0W_BASE 0xFE966D00
+#define MEDIA_AXI_FDP0R_BASE 0xFE964D40
+#define MEDIA_AXI_FDP0W_BASE 0xFE966D40
+#define MEDIA_AXI_IMSR_BASE 0xFE964D80
+#define MEDIA_AXI_IMSW_BASE 0xFE966D80
+#define MEDIA_AXI_VSP1R_BASE 0xFE965100
+#define MEDIA_AXI_VSP1W_BASE 0xFE967100
+#define MEDIA_AXI_FDP1R_BASE 0xFE965140
+#define MEDIA_AXI_FDP1W_BASE 0xFE967140
+#define MEDIA_AXI_IMRR_BASE 0xFE965180
+#define MEDIA_AXI_IMRW_BASE 0xFE967180
+#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0
+#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0
+#define MEDIA_AXI_VSPD0R_BASE 0xFE965500
+#define MEDIA_AXI_VSPD0W_BASE 0xFE967500
+#define MEDIA_AXI_VSPD1R_BASE 0xFE965540
+#define MEDIA_AXI_VSPD1W_BASE 0xFE967540
+#define MEDIA_AXI_DU0R_BASE 0xFE965580
+#define MEDIA_AXI_DU0W_BASE 0xFE967580
+#define MEDIA_AXI_DU1R_BASE 0xFE9655C0
+#define MEDIA_AXI_DU1W_BASE 0xFE9675C0
+#define MEDIA_AXI_VCP0CR_BASE 0xFE965900
+#define MEDIA_AXI_VCP0CW_BASE 0xFE967900
+#define MEDIA_AXI_VCP0VR_BASE 0xFE965940
+#define MEDIA_AXI_VCP0VW_BASE 0xFE967940
+#define MEDIA_AXI_VPC0R_BASE 0xFE965980
+#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00
+#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00
+#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40
+#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40
+#define MEDIA_AXI_VPC1R_BASE 0xFE965D80
+
+#define SYS_AXI_AVBDMSCR 0xFF802000
+#define SYS_AXI_SYX2DMSCR 0xFF802004
+#define SYS_AXI_CC50DMSCR 0xFF802008
+#define SYS_AXI_CC51DMSCR 0xFF80200C
+#define SYS_AXI_CCIDMSCR 0xFF802010
+#define SYS_AXI_CSDMSCR 0xFF802014
+#define SYS_AXI_DDMDMSCR 0xFF802018
+#define SYS_AXI_ETHDMSCR 0xFF80201C
+#define SYS_AXI_G2DDMSCR 0xFF802020
+#define SYS_AXI_IMP0DMSCR 0xFF802024
+#define SYS_AXI_IMP1DMSCR 0xFF802028
+#define SYS_AXI_LBSDMSCR 0xFF80202C
+#define SYS_AXI_MMUDSDMSCR 0xFF802030
+#define SYS_AXI_MMUMXDMSCR 0xFF802034
+#define SYS_AXI_MMURDDMSCR 0xFF802038
+#define SYS_AXI_MMUS0DMSCR 0xFF80203C
+#define SYS_AXI_MMUS1DMSCR 0xFF802040
+#define SYS_AXI_MPXDMSCR 0xFF802044
+#define SYS_AXI_MTSB0DMSCR 0xFF802048
+#define SYS_AXI_MTSB1DMSCR 0xFF80204C
+#define SYS_AXI_PCIDMSCR 0xFF802050
+#define SYS_AXI_RTXDMSCR 0xFF802054
+#define SYS_AXI_SAT0DMSCR 0xFF802058
+#define SYS_AXI_SAT1DMSCR 0xFF80205C
+#define SYS_AXI_SDM0DMSCR 0xFF802060
+#define SYS_AXI_SDM1DMSCR 0xFF802064
+#define SYS_AXI_SDS0DMSCR 0xFF802068
+#define SYS_AXI_SDS1DMSCR 0xFF80206C
+#define SYS_AXI_ETRABDMSCR 0xFF802070
+#define SYS_AXI_ETRKFDMSCR 0xFF802074
+#define SYS_AXI_UDM0DMSCR 0xFF802078
+#define SYS_AXI_UDM1DMSCR 0xFF80207C
+#define SYS_AXI_USB20DMSCR 0xFF802080
+#define SYS_AXI_USB21DMSCR 0xFF802084
+#define SYS_AXI_USB22DMSCR 0xFF802088
+#define SYS_AXI_USB30DMSCR 0xFF80208C
+#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100
+#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104
+#define SYS_AXI_AVBSLVDMSCR 0xFF802108
+#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C
+#define SYS_AXI_ETHSLVDMSCR 0xFF802110
+#define SYS_AXI_GICSLVDMSCR 0xFF802114
+#define SYS_AXI_IMPSLVDMSCR 0xFF802118
+#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C
+#define SYS_AXI_IMX1SLVDMSCR 0xFF802120
+#define SYS_AXI_IMX2SLVDMSCR 0xFF802124
+#define SYS_AXI_LBSSLVDMSCR 0xFF802128
+#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C
+#define SYS_AXI_MMC1SLVDMSCR 0xFF802130
+#define SYS_AXI_MPXSLVDMSCR 0xFF802134
+#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138
+#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C
+#define SYS_AXI_MXTSLVDMSCR 0xFF802140
+#define SYS_AXI_PCISLVDMSCR 0xFF802144
+#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148
+#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C
+#define SYS_AXI_RTXSLVDMSCR 0xFF802150
+#define SYS_AXI_SAT0SLVDMSCR 0xFF802168
+#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C
+#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170
+#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174
+#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178
+#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C
+#define SYS_AXI_SGXSLVDMSCR 0xFF802180
+#define SYS_AXI_STBSLVDMSCR 0xFF802188
+#define SYS_AXI_STMSLVDMSCR 0xFF80218C
+#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194
+#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198
+#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C
+#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0
+#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4
+#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8
+#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC
+
+#define RT_AXI_CBMDMSCR 0xFF812000
+#define RT_AXI_DBDMSCR 0xFF812004
+#define RT_AXI_RDMDMSCR 0xFF812008
+#define RT_AXI_RDSDMSCR 0xFF81200C
+#define RT_AXI_STRDMSCR 0xFF812010
+#define RT_AXI_SY2RTDMSCR 0xFF812014
+#define RT_AXI_CBSSLVDMSCR 0xFF812100
+#define RT_AXI_DBSSLVDMSCR 0xFF812104
+#define RT_AXI_RTAP1SLVDMSCR 0xFF812108
+#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C
+#define RT_AXI_RTAP3SLVDMSCR 0xFF812110
+#define RT_AXI_RT2SYSLVDMSCR 0xFF812114
+#define RT_AXI_A128TO64SLVDMSCR 0xFF812118
+#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C
+#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120
+#define RT_AXI_UTLBRSLVDMSCR 0xFF812128
+
+#define MP_AXI_ADSPDMSCR 0xFF822000
+#define MP_AXI_ASDM0DMSCR 0xFF822004
+#define MP_AXI_ASDM1DMSCR 0xFF822008
+#define MP_AXI_ASDS0DMSCR 0xFF82200C
+#define MP_AXI_ASDS1DMSCR 0xFF822010
+#define MP_AXI_MLPDMSCR 0xFF822014
+#define MP_AXI_MMUMPDMSCR 0xFF822018
+#define MP_AXI_SPUDMSCR 0xFF82201C
+#define MP_AXI_SPUCDMSCR 0xFF822020
+#define MP_AXI_SY2MPDMSCR 0xFF822024
+#define MP_AXI_ADSPSLVDMSCR 0xFF822100
+#define MP_AXI_MLMSLVDMSCR 0xFF822104
+#define MP_AXI_MPAP4SLVDMSCR 0xFF822108
+#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C
+#define MP_AXI_MPAP6SLVDMSCR 0xFF822110
+#define MP_AXI_MPAP7SLVDMSCR 0xFF822114
+#define MP_AXI_MP2SYSLVDMSCR 0xFF822118
+#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C
+#define MP_AXI_MPXAPSLVDMSCR 0xFF822124
+#define MP_AXI_SPUSLVDMSCR 0xFF822128
+#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C
+
+#define ADM_AXI_ASDM0DMSCR 0xFF842000
+#define ADM_AXI_ASDM1DMSCR 0xFF842004
+#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104
+#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108
+#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C
+
+#define DM_AXI_RDMDMSCR 0xFF852000
+#define DM_AXI_SDM0DMSCR 0xFF852004
+#define DM_AXI_SDM1DMSCR 0xFF852008
+#define DM_AXI_MMAP0SLVDMSCR 0xFF852100
+#define DM_AXI_MMAP1SLVDMSCR 0xFF852104
+#define DM_AXI_QSPAPSLVDMSCR 0xFF852108
+#define DM_AXI_RAP4SLVDMSCR 0xFF85210C
+#define DM_AXI_RAP5SLVDMSCR 0xFF852110
+#define DM_AXI_SAP4SLVDMSCR 0xFF852114
+#define DM_AXI_SAP5SLVDMSCR 0xFF852118
+#define DM_AXI_SAP6SLVDMSCR 0xFF85211C
+#define DM_AXI_SAP65SLVDMSCR 0xFF852120
+#define DM_AXI_SDAP0SLVDMSCR 0xFF852124
+#define DM_AXI_SDAP1SLVDMSCR 0xFF852128
+#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C
+#define DM_AXI_SDAP3SLVDMSCR 0xFF852130
+
+#define SYS_AXI256_SYXDMSCR 0xFF862000
+#define SYS_AXI256_MPXDMSCR 0xFF862004
+#define SYS_AXI256_MXIDMSCR 0xFF862008
+#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100
+#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104
+#define SYS_AXI256_SYXSLVDMSCR 0xFF862108
+#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C
+#define SYS_AXI256_S3CSLVDMSCR 0xFF862110
+
+#define MXT_SYXDMSCR 0xFF872000
+#define MXT_CMM0SLVDMSCR 0xFF872100
+#define MXT_CMM1SLVDMSCR 0xFF872104
+#define MXT_CMM2SLVDMSCR 0xFF872108
+#define MXT_FDPSLVDMSCR 0xFF87210C
+#define MXT_IMRSLVDMSCR 0xFF872110
+#define MXT_VINSLVDMSCR 0xFF872114
+#define MXT_VPC0SLVDMSCR 0xFF872118
+#define MXT_VPC1SLVDMSCR 0xFF87211C
+#define MXT_VSP0SLVDMSCR 0xFF872120
+#define MXT_VSP1SLVDMSCR 0xFF872124
+#define MXT_VSPD0SLVDMSCR 0xFF872128
+#define MXT_VSPD1SLVDMSCR 0xFF87212C
+#define MXT_MAP1SLVDMSCR 0xFF872130
+#define MXT_MAP2SLVDMSCR 0xFF872134
+
+#define CCI_AXI_MMUS0DMSCR 0xFF882000
+#define CCI_AXI_SYX2DMSCR 0xFF882004
+#define CCI_AXI_MMURDMSCR 0xFF882008
+#define CCI_AXI_MMUDSDMSCR 0xFF88200C
+#define CCI_AXI_MMUMDMSCR 0xFF882010
+#define CCI_AXI_MXIDMSCR 0xFF882014
+#define CCI_AXI_MMUS1DMSCR 0xFF882018
+#define CCI_AXI_MMUMPDMSCR 0xFF88201C
+#define CCI_AXI_DVMDMSCR 0xFF882020
+#define CCI_AXI_CCISLVDMSCR 0xFF882100
+
+#define CCI_AXI_IPMMUIDVMCR 0xFF880400
+#define CCI_AXI_IPMMURDVMCR 0xFF880404
+#define CCI_AXI_IPMMUS0DVMCR 0xFF880408
+#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C
+#define CCI_AXI_IPMMUMPDVMCR 0xFF880410
+#define CCI_AXI_IPMMUDSDVMCR 0xFF880414
+#define CCI_AXI_AX2ADDRMASK 0xFF88041C
+
+#define PLL0CR 0xE61500D8
+#define PLL0_STC_MASK 0x7F000000
+#define PLL0_STC_BIT 24
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+/* RWDT */
+struct rcar_rwdt {
+ u32 rwtcnt; /* 0x00 */
+ u32 rwtcsra; /* 0x04 */
+ u16 rwtcsrb; /* 0x08 */
+};
+
+/* SWDT */
+struct rcar_swdt {
+ u32 swtcnt; /* 0x00 */
+ u32 swtcsra; /* 0x04 */
+ u16 swtcsrb; /* 0x08 */
+};
+
+/* LBSC */
+struct rcar_lbsc {
+ u32 cs0ctrl;
+ u32 cs1ctrl;
+ u32 ecs0ctrl;
+ u32 ecs1ctrl;
+ u32 ecs2ctrl;
+ u32 ecs3ctrl;
+ u32 ecs4ctrl;
+ u32 ecs5ctrl;
+ u32 dummy0[4]; /* 0x20 .. 0x2C */
+ u32 cswcr0;
+ u32 cswcr1;
+ u32 ecswcr0;
+ u32 ecswcr1;
+ u32 ecswcr2;
+ u32 ecswcr3;
+ u32 ecswcr4;
+ u32 ecswcr5;
+ u32 exdmawcr0;
+ u32 exdmawcr1;
+ u32 exdmawcr2;
+ u32 dummy1[9]; /* 0x5C .. 0x7C */
+ u32 cspwcr0;
+ u32 cspwcr1;
+ u32 ecspwcr0;
+ u32 ecspwcr1;
+ u32 ecspwcr2;
+ u32 ecspwcr3;
+ u32 ecspwcr4;
+ u32 ecspwcr5;
+ u32 exwtsync;
+ u32 dummy2[3]; /* 0xA4 .. 0xAC */
+ u32 cs0bstctl;
+ u32 cs0btph;
+ u32 dummy3[2]; /* 0xB8 .. 0xBC */
+ u32 cs1gdst;
+ u32 ecs0gdst;
+ u32 ecs1gdst;
+ u32 ecs2gdst;
+ u32 ecs3gdst;
+ u32 ecs4gdst;
+ u32 ecs5gdst;
+ u32 dummy4[5]; /* 0xDC .. 0xEC */
+ u32 exdmaset0;
+ u32 exdmaset1;
+ u32 exdmaset2;
+ u32 dummy5[5]; /* 0xFC .. 0x10C */
+ u32 exdmcr0;
+ u32 exdmcr1;
+ u32 exdmcr2;
+ u32 dummy6[5]; /* 0x11C .. 0x12C */
+ u32 bcintsr;
+ u32 bcintcr;
+ u32 bcintmr;
+ u32 dummy7; /* 0x13C */
+ u32 exbatlv;
+ u32 exwtsts;
+ u32 dummy8[14]; /* 0x148 .. 0x17C */
+ u32 atacsctrl;
+ u32 dummy9[15]; /* 0x184 .. 0x1BC */
+ u32 exbct;
+ u32 extct;
+};
+
+/* DBSC3 */
+struct rcar_dbsc3 {
+ u32 dummy0[3]; /* 0x00 .. 0x08 */
+ u32 dbstate1;
+ u32 dbacen;
+ u32 dbrfen;
+ u32 dbcmd;
+ u32 dbwait;
+ u32 dbkind;
+ u32 dbconf0;
+ u32 dummy1[2]; /* 0x28 .. 0x2C */
+ u32 dbphytype;
+ u32 dummy2[3]; /* 0x34 .. 0x3C */
+ u32 dbtr0;
+ u32 dbtr1;
+ u32 dbtr2;
+ u32 dummy3; /* 0x4C */
+ u32 dbtr3;
+ u32 dbtr4;
+ u32 dbtr5;
+ u32 dbtr6;
+ u32 dbtr7;
+ u32 dbtr8;
+ u32 dbtr9;
+ u32 dbtr10;
+ u32 dbtr11;
+ u32 dbtr12;
+ u32 dbtr13;
+ u32 dbtr14;
+ u32 dbtr15;
+ u32 dbtr16;
+ u32 dbtr17;
+ u32 dbtr18;
+ u32 dbtr19;
+ u32 dummy4[7]; /* 0x94 .. 0xAC */
+ u32 dbbl;
+ u32 dummy5[3]; /* 0xB4 .. 0xBC */
+ u32 dbadj0;
+ u32 dummy6; /* 0xC4 */
+ u32 dbadj2;
+ u32 dummy7[5]; /* 0xCC .. 0xDC */
+ u32 dbrfcnf0;
+ u32 dbrfcnf1;
+ u32 dbrfcnf2;
+ u32 dummy8[2]; /* 0xEC .. 0xF0 */
+ u32 dbcalcnf;
+ u32 dbcaltr;
+ u32 dummy9; /* 0xFC */
+ u32 dbrnk0;
+ u32 dummy10[31]; /* 0x104 .. 0x17C */
+ u32 dbpdncnf;
+ u32 dummy11[47]; /* 0x184 ..0x23C */
+ u32 dbdfistat;
+ u32 dbdficnt;
+ u32 dummy12[14]; /* 0x248 .. 0x27C */
+ u32 dbpdlck;
+ u32 dummy13[3]; /* 0x284 .. 0x28C */
+ u32 dbpdrga;
+ u32 dummy14[3]; /* 0x294 .. 0x29C */
+ u32 dbpdrgd;
+ u32 dummy15[24]; /* 0x2A4 .. 0x300 */
+ u32 dbbs0cnt1;
+ u32 dummy16[30]; /* 0x308 .. 0x37C */
+ u32 dbwt0cnf0;
+ u32 dbwt0cnf1;
+ u32 dbwt0cnf2;
+ u32 dbwt0cnf3;
+ u32 dbwt0cnf4;
+};
+
+/* GPIO */
+struct rcar_gpio {
+ u32 iointsel;
+ u32 inoutsel;
+ u32 outdt;
+ u32 indt;
+ u32 intdt;
+ u32 intclr;
+ u32 intmsk;
+ u32 posneg;
+ u32 edglevel;
+ u32 filonoff;
+ u32 intmsks;
+ u32 mskclrs;
+ u32 outdtsel;
+ u32 outdth;
+ u32 outdtl;
+ u32 bothedge;
+};
+
+/* S3C(QoS) */
+struct rcar_s3c {
+ u32 s3cexcladdmsk;
+ u32 s3cexclidmsk;
+ u32 s3cadsplcr;
+ u32 s3cmaar;
+ u32 s3carcr11;
+ u32 s3crorr;
+ u32 s3cworr;
+ u32 s3carcr22;
+ u32 dummy1[2]; /* 0x20 .. 0x24 */
+ u32 s3cmctr;
+ u32 dummy2; /* 0x2C */
+ u32 cconf0;
+ u32 cconf1;
+ u32 cconf2;
+ u32 cconf3;
+};
+
+struct rcar_s3c_qos {
+ u32 s3cqos0;
+ u32 s3cqos1;
+ u32 s3cqos2;
+ u32 s3cqos3;
+ u32 s3cqos4;
+ u32 s3cqos5;
+ u32 s3cqos6;
+ u32 s3cqos7;
+ u32 s3cqos8;
+};
+
+/* DBSC(QoS) */
+struct rcar_dbsc3_qos {
+ u32 dblgcnt;
+ u32 dbtmval0;
+ u32 dbtmval1;
+ u32 dbtmval2;
+ u32 dbtmval3;
+ u32 dbrqctr;
+ u32 dbthres0;
+ u32 dbthres1;
+ u32 dbthres2;
+ u32 dummy0; /* 0x24 */
+ u32 dblgqon;
+};
+
+/* MXI(QoS) */
+struct rcar_mxi {
+ u32 mxsaar0;
+ u32 mxsaar1;
+ u32 dummy0[7]; /* 0x08 .. 0x20 */
+ u32 mxaxiracr; /* R8a7790 only */
+ u32 mxs3cracr;
+ u32 dummy1[2]; /* 0x2C .. 0x30 */
+ u32 mxaxiwacr; /* R8a7790 only */
+ u32 mxs3cwacr;
+ u32 dummy2; /* 0x3C */
+ u32 mxrtcr;
+ u32 mxwtcr;
+};
+
+struct rcar_mxi_qos {
+ u32 vspdu0;
+ u32 vspdu1;
+ u32 du0;
+ u32 du1;
+};
+
+/* AXI(QoS) */
+struct rcar_axi_qos {
+ u32 qosconf;
+ u32 qosctset0;
+ u32 qosctset1;
+ u32 qosctset2;
+ u32 qosctset3;
+ u32 qosreqctr;
+ u32 qosthres0;
+ u32 qosthres1;
+ u32 qosthres2;
+ u32 qosqon;
+};
+
+#endif
+
+#endif /* __ASM_ARCH_RCAR_BASE_H */
#endif
#endif /* CONFIG_RMOBILE */
+#ifndef __ASSEMBLY__
+u32 rmobile_get_cpu_type(void);
+u32 rmobile_get_cpu_rev_integer(void);
+u32 rmobile_get_cpu_rev_fraction(void);
+#endif /* __ASSEMBLY__ */
+
#endif /* __ASM_ARCH_RMOBILE_H */
unsigned char res1[8];
};
-struct s5pc100_gpio {
- struct s5p_gpio_bank a0;
- struct s5p_gpio_bank a1;
- struct s5p_gpio_bank b;
- struct s5p_gpio_bank c;
- struct s5p_gpio_bank d;
- struct s5p_gpio_bank e0;
- struct s5p_gpio_bank e1;
- struct s5p_gpio_bank f0;
- struct s5p_gpio_bank f1;
- struct s5p_gpio_bank f2;
- struct s5p_gpio_bank f3;
- struct s5p_gpio_bank g0;
- struct s5p_gpio_bank g1;
- struct s5p_gpio_bank g2;
- struct s5p_gpio_bank g3;
- struct s5p_gpio_bank i;
- struct s5p_gpio_bank j0;
- struct s5p_gpio_bank j1;
- struct s5p_gpio_bank j2;
- struct s5p_gpio_bank j3;
- struct s5p_gpio_bank j4;
- struct s5p_gpio_bank k0;
- struct s5p_gpio_bank k1;
- struct s5p_gpio_bank k2;
- struct s5p_gpio_bank k3;
- struct s5p_gpio_bank l0;
- struct s5p_gpio_bank l1;
- struct s5p_gpio_bank l2;
- struct s5p_gpio_bank l3;
- struct s5p_gpio_bank l4;
- struct s5p_gpio_bank h0;
- struct s5p_gpio_bank h1;
- struct s5p_gpio_bank h2;
- struct s5p_gpio_bank h3;
+/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */
+enum s5pc100_gpio_pin {
+ S5PC100_GPIO_A00,
+ S5PC100_GPIO_A01,
+ S5PC100_GPIO_A02,
+ S5PC100_GPIO_A03,
+ S5PC100_GPIO_A04,
+ S5PC100_GPIO_A05,
+ S5PC100_GPIO_A06,
+ S5PC100_GPIO_A07,
+ S5PC100_GPIO_A10,
+ S5PC100_GPIO_A11,
+ S5PC100_GPIO_A12,
+ S5PC100_GPIO_A13,
+ S5PC100_GPIO_A14,
+ S5PC100_GPIO_A15,
+ S5PC100_GPIO_A16,
+ S5PC100_GPIO_A17,
+ S5PC100_GPIO_B0,
+ S5PC100_GPIO_B1,
+ S5PC100_GPIO_B2,
+ S5PC100_GPIO_B3,
+ S5PC100_GPIO_B4,
+ S5PC100_GPIO_B5,
+ S5PC100_GPIO_B6,
+ S5PC100_GPIO_B7,
+ S5PC100_GPIO_C0,
+ S5PC100_GPIO_C1,
+ S5PC100_GPIO_C2,
+ S5PC100_GPIO_C3,
+ S5PC100_GPIO_C4,
+ S5PC100_GPIO_C5,
+ S5PC100_GPIO_C6,
+ S5PC100_GPIO_C7,
+ S5PC100_GPIO_D0,
+ S5PC100_GPIO_D1,
+ S5PC100_GPIO_D2,
+ S5PC100_GPIO_D3,
+ S5PC100_GPIO_D4,
+ S5PC100_GPIO_D5,
+ S5PC100_GPIO_D6,
+ S5PC100_GPIO_D7,
+ S5PC100_GPIO_E00,
+ S5PC100_GPIO_E01,
+ S5PC100_GPIO_E02,
+ S5PC100_GPIO_E03,
+ S5PC100_GPIO_E04,
+ S5PC100_GPIO_E05,
+ S5PC100_GPIO_E06,
+ S5PC100_GPIO_E07,
+ S5PC100_GPIO_E10,
+ S5PC100_GPIO_E11,
+ S5PC100_GPIO_E12,
+ S5PC100_GPIO_E13,
+ S5PC100_GPIO_E14,
+ S5PC100_GPIO_E15,
+ S5PC100_GPIO_E16,
+ S5PC100_GPIO_E17,
+ S5PC100_GPIO_F00,
+ S5PC100_GPIO_F01,
+ S5PC100_GPIO_F02,
+ S5PC100_GPIO_F03,
+ S5PC100_GPIO_F04,
+ S5PC100_GPIO_F05,
+ S5PC100_GPIO_F06,
+ S5PC100_GPIO_F07,
+ S5PC100_GPIO_F10,
+ S5PC100_GPIO_F11,
+ S5PC100_GPIO_F12,
+ S5PC100_GPIO_F13,
+ S5PC100_GPIO_F14,
+ S5PC100_GPIO_F15,
+ S5PC100_GPIO_F16,
+ S5PC100_GPIO_F17,
+ S5PC100_GPIO_F20,
+ S5PC100_GPIO_F21,
+ S5PC100_GPIO_F22,
+ S5PC100_GPIO_F23,
+ S5PC100_GPIO_F24,
+ S5PC100_GPIO_F25,
+ S5PC100_GPIO_F26,
+ S5PC100_GPIO_F27,
+ S5PC100_GPIO_F30,
+ S5PC100_GPIO_F31,
+ S5PC100_GPIO_F32,
+ S5PC100_GPIO_F33,
+ S5PC100_GPIO_F34,
+ S5PC100_GPIO_F35,
+ S5PC100_GPIO_F36,
+ S5PC100_GPIO_F37,
+ S5PC100_GPIO_G00,
+ S5PC100_GPIO_G01,
+ S5PC100_GPIO_G02,
+ S5PC100_GPIO_G03,
+ S5PC100_GPIO_G04,
+ S5PC100_GPIO_G05,
+ S5PC100_GPIO_G06,
+ S5PC100_GPIO_G07,
+ S5PC100_GPIO_G10,
+ S5PC100_GPIO_G11,
+ S5PC100_GPIO_G12,
+ S5PC100_GPIO_G13,
+ S5PC100_GPIO_G14,
+ S5PC100_GPIO_G15,
+ S5PC100_GPIO_G16,
+ S5PC100_GPIO_G17,
+ S5PC100_GPIO_G20,
+ S5PC100_GPIO_G21,
+ S5PC100_GPIO_G22,
+ S5PC100_GPIO_G23,
+ S5PC100_GPIO_G24,
+ S5PC100_GPIO_G25,
+ S5PC100_GPIO_G26,
+ S5PC100_GPIO_G27,
+ S5PC100_GPIO_G30,
+ S5PC100_GPIO_G31,
+ S5PC100_GPIO_G32,
+ S5PC100_GPIO_G33,
+ S5PC100_GPIO_G34,
+ S5PC100_GPIO_G35,
+ S5PC100_GPIO_G36,
+ S5PC100_GPIO_G37,
+ S5PC100_GPIO_I0,
+ S5PC100_GPIO_I1,
+ S5PC100_GPIO_I2,
+ S5PC100_GPIO_I3,
+ S5PC100_GPIO_I4,
+ S5PC100_GPIO_I5,
+ S5PC100_GPIO_I6,
+ S5PC100_GPIO_I7,
+ S5PC100_GPIO_J00,
+ S5PC100_GPIO_J01,
+ S5PC100_GPIO_J02,
+ S5PC100_GPIO_J03,
+ S5PC100_GPIO_J04,
+ S5PC100_GPIO_J05,
+ S5PC100_GPIO_J06,
+ S5PC100_GPIO_J07,
+ S5PC100_GPIO_J10,
+ S5PC100_GPIO_J11,
+ S5PC100_GPIO_J12,
+ S5PC100_GPIO_J13,
+ S5PC100_GPIO_J14,
+ S5PC100_GPIO_J15,
+ S5PC100_GPIO_J16,
+ S5PC100_GPIO_J17,
+ S5PC100_GPIO_J20,
+ S5PC100_GPIO_J21,
+ S5PC100_GPIO_J22,
+ S5PC100_GPIO_J23,
+ S5PC100_GPIO_J24,
+ S5PC100_GPIO_J25,
+ S5PC100_GPIO_J26,
+ S5PC100_GPIO_J27,
+ S5PC100_GPIO_J30,
+ S5PC100_GPIO_J31,
+ S5PC100_GPIO_J32,
+ S5PC100_GPIO_J33,
+ S5PC100_GPIO_J34,
+ S5PC100_GPIO_J35,
+ S5PC100_GPIO_J36,
+ S5PC100_GPIO_J37,
+ S5PC100_GPIO_J40,
+ S5PC100_GPIO_J41,
+ S5PC100_GPIO_J42,
+ S5PC100_GPIO_J43,
+ S5PC100_GPIO_J44,
+ S5PC100_GPIO_J45,
+ S5PC100_GPIO_J46,
+ S5PC100_GPIO_J47,
+ S5PC100_GPIO_K00,
+ S5PC100_GPIO_K01,
+ S5PC100_GPIO_K02,
+ S5PC100_GPIO_K03,
+ S5PC100_GPIO_K04,
+ S5PC100_GPIO_K05,
+ S5PC100_GPIO_K06,
+ S5PC100_GPIO_K07,
+ S5PC100_GPIO_K10,
+ S5PC100_GPIO_K11,
+ S5PC100_GPIO_K12,
+ S5PC100_GPIO_K13,
+ S5PC100_GPIO_K14,
+ S5PC100_GPIO_K15,
+ S5PC100_GPIO_K16,
+ S5PC100_GPIO_K17,
+ S5PC100_GPIO_K20,
+ S5PC100_GPIO_K21,
+ S5PC100_GPIO_K22,
+ S5PC100_GPIO_K23,
+ S5PC100_GPIO_K24,
+ S5PC100_GPIO_K25,
+ S5PC100_GPIO_K26,
+ S5PC100_GPIO_K27,
+ S5PC100_GPIO_K30,
+ S5PC100_GPIO_K31,
+ S5PC100_GPIO_K32,
+ S5PC100_GPIO_K33,
+ S5PC100_GPIO_K34,
+ S5PC100_GPIO_K35,
+ S5PC100_GPIO_K36,
+ S5PC100_GPIO_K37,
+ S5PC100_GPIO_L00,
+ S5PC100_GPIO_L01,
+ S5PC100_GPIO_L02,
+ S5PC100_GPIO_L03,
+ S5PC100_GPIO_L04,
+ S5PC100_GPIO_L05,
+ S5PC100_GPIO_L06,
+ S5PC100_GPIO_L07,
+ S5PC100_GPIO_L10,
+ S5PC100_GPIO_L11,
+ S5PC100_GPIO_L12,
+ S5PC100_GPIO_L13,
+ S5PC100_GPIO_L14,
+ S5PC100_GPIO_L15,
+ S5PC100_GPIO_L16,
+ S5PC100_GPIO_L17,
+ S5PC100_GPIO_L20,
+ S5PC100_GPIO_L21,
+ S5PC100_GPIO_L22,
+ S5PC100_GPIO_L23,
+ S5PC100_GPIO_L24,
+ S5PC100_GPIO_L25,
+ S5PC100_GPIO_L26,
+ S5PC100_GPIO_L27,
+ S5PC100_GPIO_L30,
+ S5PC100_GPIO_L31,
+ S5PC100_GPIO_L32,
+ S5PC100_GPIO_L33,
+ S5PC100_GPIO_L34,
+ S5PC100_GPIO_L35,
+ S5PC100_GPIO_L36,
+ S5PC100_GPIO_L37,
+ S5PC100_GPIO_L40,
+ S5PC100_GPIO_L41,
+ S5PC100_GPIO_L42,
+ S5PC100_GPIO_L43,
+ S5PC100_GPIO_L44,
+ S5PC100_GPIO_L45,
+ S5PC100_GPIO_L46,
+ S5PC100_GPIO_L47,
+ S5PC100_GPIO_H00,
+ S5PC100_GPIO_H01,
+ S5PC100_GPIO_H02,
+ S5PC100_GPIO_H03,
+ S5PC100_GPIO_H04,
+ S5PC100_GPIO_H05,
+ S5PC100_GPIO_H06,
+ S5PC100_GPIO_H07,
+ S5PC100_GPIO_H10,
+ S5PC100_GPIO_H11,
+ S5PC100_GPIO_H12,
+ S5PC100_GPIO_H13,
+ S5PC100_GPIO_H14,
+ S5PC100_GPIO_H15,
+ S5PC100_GPIO_H16,
+ S5PC100_GPIO_H17,
+ S5PC100_GPIO_H20,
+ S5PC100_GPIO_H21,
+ S5PC100_GPIO_H22,
+ S5PC100_GPIO_H23,
+ S5PC100_GPIO_H24,
+ S5PC100_GPIO_H25,
+ S5PC100_GPIO_H26,
+ S5PC100_GPIO_H27,
+ S5PC100_GPIO_H30,
+ S5PC100_GPIO_H31,
+ S5PC100_GPIO_H32,
+ S5PC100_GPIO_H33,
+ S5PC100_GPIO_H34,
+ S5PC100_GPIO_H35,
+ S5PC100_GPIO_H36,
+ S5PC100_GPIO_H37,
+
+ S5PC100_GPIO_MAX_PORT
};
-struct s5pc110_gpio {
- struct s5p_gpio_bank a0;
- struct s5p_gpio_bank a1;
- struct s5p_gpio_bank b;
- struct s5p_gpio_bank c0;
- struct s5p_gpio_bank c1;
- struct s5p_gpio_bank d0;
- struct s5p_gpio_bank d1;
- struct s5p_gpio_bank e0;
- struct s5p_gpio_bank e1;
- struct s5p_gpio_bank f0;
- struct s5p_gpio_bank f1;
- struct s5p_gpio_bank f2;
- struct s5p_gpio_bank f3;
- struct s5p_gpio_bank g0;
- struct s5p_gpio_bank g1;
- struct s5p_gpio_bank g2;
- struct s5p_gpio_bank g3;
- struct s5p_gpio_bank i;
- struct s5p_gpio_bank j0;
- struct s5p_gpio_bank j1;
- struct s5p_gpio_bank j2;
- struct s5p_gpio_bank j3;
- struct s5p_gpio_bank j4;
- struct s5p_gpio_bank mp0_1;
- struct s5p_gpio_bank mp0_2;
- struct s5p_gpio_bank mp0_3;
- struct s5p_gpio_bank mp0_4;
- struct s5p_gpio_bank mp0_5;
- struct s5p_gpio_bank mp0_6;
- struct s5p_gpio_bank mp0_7;
- struct s5p_gpio_bank mp1_0;
- struct s5p_gpio_bank mp1_1;
- struct s5p_gpio_bank mp1_2;
- struct s5p_gpio_bank mp1_3;
- struct s5p_gpio_bank mp1_4;
- struct s5p_gpio_bank mp1_5;
- struct s5p_gpio_bank mp1_6;
- struct s5p_gpio_bank mp1_7;
- struct s5p_gpio_bank mp1_8;
- struct s5p_gpio_bank mp2_0;
- struct s5p_gpio_bank mp2_1;
- struct s5p_gpio_bank mp2_2;
- struct s5p_gpio_bank mp2_3;
- struct s5p_gpio_bank mp2_4;
- struct s5p_gpio_bank mp2_5;
- struct s5p_gpio_bank mp2_6;
- struct s5p_gpio_bank mp2_7;
- struct s5p_gpio_bank mp2_8;
- struct s5p_gpio_bank res1[48];
- struct s5p_gpio_bank h0;
- struct s5p_gpio_bank h1;
- struct s5p_gpio_bank h2;
- struct s5p_gpio_bank h3;
+enum s5pc110_gpio_pin {
+ S5PC110_GPIO_A00,
+ S5PC110_GPIO_A01,
+ S5PC110_GPIO_A02,
+ S5PC110_GPIO_A03,
+ S5PC110_GPIO_A04,
+ S5PC110_GPIO_A05,
+ S5PC110_GPIO_A06,
+ S5PC110_GPIO_A07,
+ S5PC110_GPIO_A10,
+ S5PC110_GPIO_A11,
+ S5PC110_GPIO_A12,
+ S5PC110_GPIO_A13,
+ S5PC110_GPIO_A14,
+ S5PC110_GPIO_A15,
+ S5PC110_GPIO_A16,
+ S5PC110_GPIO_A17,
+ S5PC110_GPIO_B0,
+ S5PC110_GPIO_B1,
+ S5PC110_GPIO_B2,
+ S5PC110_GPIO_B3,
+ S5PC110_GPIO_B4,
+ S5PC110_GPIO_B5,
+ S5PC110_GPIO_B6,
+ S5PC110_GPIO_B7,
+ S5PC110_GPIO_C00,
+ S5PC110_GPIO_C01,
+ S5PC110_GPIO_C02,
+ S5PC110_GPIO_C03,
+ S5PC110_GPIO_C04,
+ S5PC110_GPIO_C05,
+ S5PC110_GPIO_C06,
+ S5PC110_GPIO_C07,
+ S5PC110_GPIO_C10,
+ S5PC110_GPIO_C11,
+ S5PC110_GPIO_C12,
+ S5PC110_GPIO_C13,
+ S5PC110_GPIO_C14,
+ S5PC110_GPIO_C15,
+ S5PC110_GPIO_C16,
+ S5PC110_GPIO_C17,
+ S5PC110_GPIO_D00,
+ S5PC110_GPIO_D01,
+ S5PC110_GPIO_D02,
+ S5PC110_GPIO_D03,
+ S5PC110_GPIO_D04,
+ S5PC110_GPIO_D05,
+ S5PC110_GPIO_D06,
+ S5PC110_GPIO_D07,
+ S5PC110_GPIO_D10,
+ S5PC110_GPIO_D11,
+ S5PC110_GPIO_D12,
+ S5PC110_GPIO_D13,
+ S5PC110_GPIO_D14,
+ S5PC110_GPIO_D15,
+ S5PC110_GPIO_D16,
+ S5PC110_GPIO_D17,
+ S5PC110_GPIO_E00,
+ S5PC110_GPIO_E01,
+ S5PC110_GPIO_E02,
+ S5PC110_GPIO_E03,
+ S5PC110_GPIO_E04,
+ S5PC110_GPIO_E05,
+ S5PC110_GPIO_E06,
+ S5PC110_GPIO_E07,
+ S5PC110_GPIO_E10,
+ S5PC110_GPIO_E11,
+ S5PC110_GPIO_E12,
+ S5PC110_GPIO_E13,
+ S5PC110_GPIO_E14,
+ S5PC110_GPIO_E15,
+ S5PC110_GPIO_E16,
+ S5PC110_GPIO_E17,
+ S5PC110_GPIO_F00,
+ S5PC110_GPIO_F01,
+ S5PC110_GPIO_F02,
+ S5PC110_GPIO_F03,
+ S5PC110_GPIO_F04,
+ S5PC110_GPIO_F05,
+ S5PC110_GPIO_F06,
+ S5PC110_GPIO_F07,
+ S5PC110_GPIO_F10,
+ S5PC110_GPIO_F11,
+ S5PC110_GPIO_F12,
+ S5PC110_GPIO_F13,
+ S5PC110_GPIO_F14,
+ S5PC110_GPIO_F15,
+ S5PC110_GPIO_F16,
+ S5PC110_GPIO_F17,
+ S5PC110_GPIO_F20,
+ S5PC110_GPIO_F21,
+ S5PC110_GPIO_F22,
+ S5PC110_GPIO_F23,
+ S5PC110_GPIO_F24,
+ S5PC110_GPIO_F25,
+ S5PC110_GPIO_F26,
+ S5PC110_GPIO_F27,
+ S5PC110_GPIO_F30,
+ S5PC110_GPIO_F31,
+ S5PC110_GPIO_F32,
+ S5PC110_GPIO_F33,
+ S5PC110_GPIO_F34,
+ S5PC110_GPIO_F35,
+ S5PC110_GPIO_F36,
+ S5PC110_GPIO_F37,
+ S5PC110_GPIO_G00,
+ S5PC110_GPIO_G01,
+ S5PC110_GPIO_G02,
+ S5PC110_GPIO_G03,
+ S5PC110_GPIO_G04,
+ S5PC110_GPIO_G05,
+ S5PC110_GPIO_G06,
+ S5PC110_GPIO_G07,
+ S5PC110_GPIO_G10,
+ S5PC110_GPIO_G11,
+ S5PC110_GPIO_G12,
+ S5PC110_GPIO_G13,
+ S5PC110_GPIO_G14,
+ S5PC110_GPIO_G15,
+ S5PC110_GPIO_G16,
+ S5PC110_GPIO_G17,
+ S5PC110_GPIO_G20,
+ S5PC110_GPIO_G21,
+ S5PC110_GPIO_G22,
+ S5PC110_GPIO_G23,
+ S5PC110_GPIO_G24,
+ S5PC110_GPIO_G25,
+ S5PC110_GPIO_G26,
+ S5PC110_GPIO_G27,
+ S5PC110_GPIO_G30,
+ S5PC110_GPIO_G31,
+ S5PC110_GPIO_G32,
+ S5PC110_GPIO_G33,
+ S5PC110_GPIO_G34,
+ S5PC110_GPIO_G35,
+ S5PC110_GPIO_G36,
+ S5PC110_GPIO_G37,
+ S5PC110_GPIO_I0,
+ S5PC110_GPIO_I1,
+ S5PC110_GPIO_I2,
+ S5PC110_GPIO_I3,
+ S5PC110_GPIO_I4,
+ S5PC110_GPIO_I5,
+ S5PC110_GPIO_I6,
+ S5PC110_GPIO_I7,
+ S5PC110_GPIO_J00,
+ S5PC110_GPIO_J01,
+ S5PC110_GPIO_J02,
+ S5PC110_GPIO_J03,
+ S5PC110_GPIO_J04,
+ S5PC110_GPIO_J05,
+ S5PC110_GPIO_J06,
+ S5PC110_GPIO_J07,
+ S5PC110_GPIO_J10,
+ S5PC110_GPIO_J11,
+ S5PC110_GPIO_J12,
+ S5PC110_GPIO_J13,
+ S5PC110_GPIO_J14,
+ S5PC110_GPIO_J15,
+ S5PC110_GPIO_J16,
+ S5PC110_GPIO_J17,
+ S5PC110_GPIO_J20,
+ S5PC110_GPIO_J21,
+ S5PC110_GPIO_J22,
+ S5PC110_GPIO_J23,
+ S5PC110_GPIO_J24,
+ S5PC110_GPIO_J25,
+ S5PC110_GPIO_J26,
+ S5PC110_GPIO_J27,
+ S5PC110_GPIO_J30,
+ S5PC110_GPIO_J31,
+ S5PC110_GPIO_J32,
+ S5PC110_GPIO_J33,
+ S5PC110_GPIO_J34,
+ S5PC110_GPIO_J35,
+ S5PC110_GPIO_J36,
+ S5PC110_GPIO_J37,
+ S5PC110_GPIO_J40,
+ S5PC110_GPIO_J41,
+ S5PC110_GPIO_J42,
+ S5PC110_GPIO_J43,
+ S5PC110_GPIO_J44,
+ S5PC110_GPIO_J45,
+ S5PC110_GPIO_J46,
+ S5PC110_GPIO_J47,
+ S5PC110_GPIO_MP010,
+ S5PC110_GPIO_MP011,
+ S5PC110_GPIO_MP012,
+ S5PC110_GPIO_MP013,
+ S5PC110_GPIO_MP014,
+ S5PC110_GPIO_MP015,
+ S5PC110_GPIO_MP016,
+ S5PC110_GPIO_MP017,
+ S5PC110_GPIO_MP020,
+ S5PC110_GPIO_MP021,
+ S5PC110_GPIO_MP022,
+ S5PC110_GPIO_MP023,
+ S5PC110_GPIO_MP024,
+ S5PC110_GPIO_MP025,
+ S5PC110_GPIO_MP026,
+ S5PC110_GPIO_MP027,
+ S5PC110_GPIO_MP030,
+ S5PC110_GPIO_MP031,
+ S5PC110_GPIO_MP032,
+ S5PC110_GPIO_MP033,
+ S5PC110_GPIO_MP034,
+ S5PC110_GPIO_MP035,
+ S5PC110_GPIO_MP036,
+ S5PC110_GPIO_MP037,
+ S5PC110_GPIO_MP040,
+ S5PC110_GPIO_MP041,
+ S5PC110_GPIO_MP042,
+ S5PC110_GPIO_MP043,
+ S5PC110_GPIO_MP044,
+ S5PC110_GPIO_MP045,
+ S5PC110_GPIO_MP046,
+ S5PC110_GPIO_MP047,
+ S5PC110_GPIO_MP050,
+ S5PC110_GPIO_MP051,
+ S5PC110_GPIO_MP052,
+ S5PC110_GPIO_MP053,
+ S5PC110_GPIO_MP054,
+ S5PC110_GPIO_MP055,
+ S5PC110_GPIO_MP056,
+ S5PC110_GPIO_MP057,
+ S5PC110_GPIO_MP060,
+ S5PC110_GPIO_MP061,
+ S5PC110_GPIO_MP062,
+ S5PC110_GPIO_MP063,
+ S5PC110_GPIO_MP064,
+ S5PC110_GPIO_MP065,
+ S5PC110_GPIO_MP066,
+ S5PC110_GPIO_MP067,
+ S5PC110_GPIO_MP070,
+ S5PC110_GPIO_MP071,
+ S5PC110_GPIO_MP072,
+ S5PC110_GPIO_MP073,
+ S5PC110_GPIO_MP074,
+ S5PC110_GPIO_MP075,
+ S5PC110_GPIO_MP076,
+ S5PC110_GPIO_MP077,
+ S5PC110_GPIO_MP100,
+ S5PC110_GPIO_MP101,
+ S5PC110_GPIO_MP102,
+ S5PC110_GPIO_MP103,
+ S5PC110_GPIO_MP104,
+ S5PC110_GPIO_MP105,
+ S5PC110_GPIO_MP106,
+ S5PC110_GPIO_MP107,
+ S5PC110_GPIO_MP110,
+ S5PC110_GPIO_MP111,
+ S5PC110_GPIO_MP112,
+ S5PC110_GPIO_MP113,
+ S5PC110_GPIO_MP114,
+ S5PC110_GPIO_MP115,
+ S5PC110_GPIO_MP116,
+ S5PC110_GPIO_MP117,
+ S5PC110_GPIO_MP120,
+ S5PC110_GPIO_MP121,
+ S5PC110_GPIO_MP122,
+ S5PC110_GPIO_MP123,
+ S5PC110_GPIO_MP124,
+ S5PC110_GPIO_MP125,
+ S5PC110_GPIO_MP126,
+ S5PC110_GPIO_MP127,
+ S5PC110_GPIO_MP130,
+ S5PC110_GPIO_MP131,
+ S5PC110_GPIO_MP132,
+ S5PC110_GPIO_MP133,
+ S5PC110_GPIO_MP134,
+ S5PC110_GPIO_MP135,
+ S5PC110_GPIO_MP136,
+ S5PC110_GPIO_MP137,
+ S5PC110_GPIO_MP140,
+ S5PC110_GPIO_MP141,
+ S5PC110_GPIO_MP142,
+ S5PC110_GPIO_MP143,
+ S5PC110_GPIO_MP144,
+ S5PC110_GPIO_MP145,
+ S5PC110_GPIO_MP146,
+ S5PC110_GPIO_MP147,
+ S5PC110_GPIO_MP150,
+ S5PC110_GPIO_MP151,
+ S5PC110_GPIO_MP152,
+ S5PC110_GPIO_MP153,
+ S5PC110_GPIO_MP154,
+ S5PC110_GPIO_MP155,
+ S5PC110_GPIO_MP156,
+ S5PC110_GPIO_MP157,
+ S5PC110_GPIO_MP160,
+ S5PC110_GPIO_MP161,
+ S5PC110_GPIO_MP162,
+ S5PC110_GPIO_MP163,
+ S5PC110_GPIO_MP164,
+ S5PC110_GPIO_MP165,
+ S5PC110_GPIO_MP166,
+ S5PC110_GPIO_MP167,
+ S5PC110_GPIO_MP170,
+ S5PC110_GPIO_MP171,
+ S5PC110_GPIO_MP172,
+ S5PC110_GPIO_MP173,
+ S5PC110_GPIO_MP174,
+ S5PC110_GPIO_MP175,
+ S5PC110_GPIO_MP176,
+ S5PC110_GPIO_MP177,
+ S5PC110_GPIO_MP180,
+ S5PC110_GPIO_MP181,
+ S5PC110_GPIO_MP182,
+ S5PC110_GPIO_MP183,
+ S5PC110_GPIO_MP184,
+ S5PC110_GPIO_MP185,
+ S5PC110_GPIO_MP186,
+ S5PC110_GPIO_MP187,
+ S5PC110_GPIO_MP200,
+ S5PC110_GPIO_MP201,
+ S5PC110_GPIO_MP202,
+ S5PC110_GPIO_MP203,
+ S5PC110_GPIO_MP204,
+ S5PC110_GPIO_MP205,
+ S5PC110_GPIO_MP206,
+ S5PC110_GPIO_MP207,
+ S5PC110_GPIO_MP210,
+ S5PC110_GPIO_MP211,
+ S5PC110_GPIO_MP212,
+ S5PC110_GPIO_MP213,
+ S5PC110_GPIO_MP214,
+ S5PC110_GPIO_MP215,
+ S5PC110_GPIO_MP216,
+ S5PC110_GPIO_MP217,
+ S5PC110_GPIO_MP220,
+ S5PC110_GPIO_MP221,
+ S5PC110_GPIO_MP222,
+ S5PC110_GPIO_MP223,
+ S5PC110_GPIO_MP224,
+ S5PC110_GPIO_MP225,
+ S5PC110_GPIO_MP226,
+ S5PC110_GPIO_MP227,
+ S5PC110_GPIO_MP230,
+ S5PC110_GPIO_MP231,
+ S5PC110_GPIO_MP232,
+ S5PC110_GPIO_MP233,
+ S5PC110_GPIO_MP234,
+ S5PC110_GPIO_MP235,
+ S5PC110_GPIO_MP236,
+ S5PC110_GPIO_MP237,
+ S5PC110_GPIO_MP240,
+ S5PC110_GPIO_MP241,
+ S5PC110_GPIO_MP242,
+ S5PC110_GPIO_MP243,
+ S5PC110_GPIO_MP244,
+ S5PC110_GPIO_MP245,
+ S5PC110_GPIO_MP246,
+ S5PC110_GPIO_MP247,
+ S5PC110_GPIO_MP250,
+ S5PC110_GPIO_MP251,
+ S5PC110_GPIO_MP252,
+ S5PC110_GPIO_MP253,
+ S5PC110_GPIO_MP254,
+ S5PC110_GPIO_MP255,
+ S5PC110_GPIO_MP256,
+ S5PC110_GPIO_MP257,
+ S5PC110_GPIO_MP260,
+ S5PC110_GPIO_MP261,
+ S5PC110_GPIO_MP262,
+ S5PC110_GPIO_MP263,
+ S5PC110_GPIO_MP264,
+ S5PC110_GPIO_MP265,
+ S5PC110_GPIO_MP266,
+ S5PC110_GPIO_MP267,
+ S5PC110_GPIO_MP270,
+ S5PC110_GPIO_MP271,
+ S5PC110_GPIO_MP272,
+ S5PC110_GPIO_MP273,
+ S5PC110_GPIO_MP274,
+ S5PC110_GPIO_MP275,
+ S5PC110_GPIO_MP276,
+ S5PC110_GPIO_MP277,
+ S5PC110_GPIO_MP280,
+ S5PC110_GPIO_MP281,
+ S5PC110_GPIO_MP282,
+ S5PC110_GPIO_MP283,
+ S5PC110_GPIO_MP284,
+ S5PC110_GPIO_MP285,
+ S5PC110_GPIO_MP286,
+ S5PC110_GPIO_MP287,
+ S5PC110_GPIO_RES,
+ S5PC110_GPIO_H00 = (S5PC110_GPIO_RES + (48 * 8)),
+ S5PC110_GPIO_H01,
+ S5PC110_GPIO_H02,
+ S5PC110_GPIO_H03,
+ S5PC110_GPIO_H04,
+ S5PC110_GPIO_H05,
+ S5PC110_GPIO_H06,
+ S5PC110_GPIO_H07,
+ S5PC110_GPIO_H10,
+ S5PC110_GPIO_H11,
+ S5PC110_GPIO_H12,
+ S5PC110_GPIO_H13,
+ S5PC110_GPIO_H14,
+ S5PC110_GPIO_H15,
+ S5PC110_GPIO_H16,
+ S5PC110_GPIO_H17,
+ S5PC110_GPIO_H20,
+ S5PC110_GPIO_H21,
+ S5PC110_GPIO_H22,
+ S5PC110_GPIO_H23,
+ S5PC110_GPIO_H24,
+ S5PC110_GPIO_H25,
+ S5PC110_GPIO_H26,
+ S5PC110_GPIO_H27,
+ S5PC110_GPIO_H30,
+ S5PC110_GPIO_H31,
+ S5PC110_GPIO_H32,
+ S5PC110_GPIO_H33,
+ S5PC110_GPIO_H34,
+ S5PC110_GPIO_H35,
+ S5PC110_GPIO_H36,
+ S5PC110_GPIO_H37,
+
+ S5PC110_GPIO_MAX_PORT
};
-/* functions */
-void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
-void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
-void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
-void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
-unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
-void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
-void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
-void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
+struct gpio_info {
+ unsigned int reg_addr; /* Address of register for this part */
+ unsigned int max_gpio; /* Maximum GPIO in this part */
+};
-/* GPIO pins per bank */
-#define GPIO_PER_BANK 8
+#define S5PC100_GPIO_NUM_PARTS 1
+static struct gpio_info s5pc100_gpio_data[S5PC100_GPIO_NUM_PARTS] = {
+ { S5PC100_GPIO_BASE, S5PC100_GPIO_MAX_PORT },
+};
-#define S5P_GPIO_PART_SHIFT (24)
-#define S5P_GPIO_PART_MASK (0xff)
-#define S5P_GPIO_BANK_SHIFT (8)
-#define S5P_GPIO_BANK_MASK (0xffff)
-#define S5P_GPIO_PIN_MASK (0xff)
+#define S5PC110_GPIO_NUM_PARTS 1
+static struct gpio_info s5pc110_gpio_data[S5PC110_GPIO_NUM_PARTS] = {
+ { S5PC110_GPIO_BASE, S5PC110_GPIO_MAX_PORT },
+};
-#define S5P_GPIO_SET_PART(x) \
- (((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT)
+static inline struct gpio_info *get_gpio_data(void)
+{
+ if (cpu_is_s5pc100())
+ return s5pc100_gpio_data;
+ else if (cpu_is_s5pc110())
+ return s5pc110_gpio_data;
-#define S5P_GPIO_GET_PART(x) \
- (((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK)
+ return NULL;
+}
-#define S5P_GPIO_SET_PIN(x) \
- ((x) & S5P_GPIO_PIN_MASK)
+static inline unsigned int get_bank_num(void)
+{
+ if (cpu_is_s5pc100())
+ return S5PC100_GPIO_NUM_PARTS;
+ else if (cpu_is_s5pc110())
+ return S5PC110_GPIO_NUM_PARTS;
-#define S5PC100_SET_BANK(bank) \
- (((unsigned)&(((struct s5pc100_gpio *) \
- S5PC100_GPIO_BASE)->bank) - S5PC100_GPIO_BASE) \
- & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+ return 0;
+}
-#define S5PC110_SET_BANK(bank) \
- ((((unsigned)&(((struct s5pc110_gpio *) \
- S5PC110_GPIO_BASE)->bank) - S5PC110_GPIO_BASE) \
- & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+/*
+ * This structure helps mapping symbolic GPIO names into indices from
+ * exynos5_gpio_pin/exynos5420_gpio_pin enums.
+ *
+ * By convention, symbolic GPIO name is defined as follows:
+ *
+ * g[p]<bank><set><bit>, where
+ * p is optional
+ * <bank> - a single character bank name, as defined by the SOC
+ * <set> - a single digit set number
+ * <bit> - bit number within the set (in 0..7 range).
+ *
+ * <set><bit> essentially form an octal number of the GPIO pin within the bank
+ * space. On the 5420 architecture some banks' sets do not start not from zero
+ * ('d' starts from 1 and 'j' starts from 4). To compensate for that and
+ * maintain flat number space withoout holes, those banks use offsets to be
+ * deducted from the pin number.
+ */
+struct gpio_name_num_table {
+ char bank; /* bank name symbol */
+ u8 bank_size; /* total number of pins in the bank */
+ char bank_offset; /* offset of the first bank's pin */
+ unsigned int base; /* index of the first bank's pin in the enum */
+};
-#define s5pc100_gpio_get(bank, pin) \
- (S5P_GPIO_SET_PART(0) | \
- S5PC100_SET_BANK(bank) | \
- S5P_GPIO_SET_PIN(pin))
+#define GPIO_PER_BANK 8
+#define GPIO_ENTRY(name, base, top, offset) { name, top - base, offset, base }
+static const struct gpio_name_num_table s5pc100_gpio_table[] = {
+ GPIO_ENTRY('a', S5PC100_GPIO_A00, S5PC100_GPIO_B0, 0),
+ GPIO_ENTRY('b', S5PC100_GPIO_B0, S5PC100_GPIO_C0, 0),
+ GPIO_ENTRY('c', S5PC100_GPIO_C0, S5PC100_GPIO_D0, 0),
+ GPIO_ENTRY('d', S5PC100_GPIO_D0, S5PC100_GPIO_E00, 0),
+ GPIO_ENTRY('e', S5PC100_GPIO_E00, S5PC100_GPIO_F00, 0),
+ GPIO_ENTRY('f', S5PC100_GPIO_F00, S5PC100_GPIO_G00, 0),
+ GPIO_ENTRY('g', S5PC100_GPIO_G00, S5PC100_GPIO_I0, 0),
+ GPIO_ENTRY('i', S5PC100_GPIO_I0, S5PC100_GPIO_J00, 0),
+ GPIO_ENTRY('j', S5PC100_GPIO_J00, S5PC100_GPIO_K00, 0),
+ GPIO_ENTRY('k', S5PC100_GPIO_K00, S5PC100_GPIO_L00, 0),
+ GPIO_ENTRY('l', S5PC100_GPIO_L00, S5PC100_GPIO_H00, 0),
+ GPIO_ENTRY('h', S5PC100_GPIO_H00, S5PC100_GPIO_MAX_PORT, 0),
+ { 0 }
+};
-#define s5pc110_gpio_get(bank, pin) \
- (S5P_GPIO_SET_PART(0) | \
- S5PC110_SET_BANK(bank) | \
- S5P_GPIO_SET_PIN(pin))
+static const struct gpio_name_num_table s5pc110_gpio_table[] = {
+ GPIO_ENTRY('a', S5PC110_GPIO_A00, S5PC110_GPIO_B0, 0),
+ GPIO_ENTRY('b', S5PC110_GPIO_B0, S5PC110_GPIO_C00, 0),
+ GPIO_ENTRY('c', S5PC110_GPIO_C00, S5PC110_GPIO_D00, 0),
+ GPIO_ENTRY('d', S5PC110_GPIO_D00, S5PC110_GPIO_E00, 0),
+ GPIO_ENTRY('e', S5PC110_GPIO_E00, S5PC110_GPIO_F00, 0),
+ GPIO_ENTRY('f', S5PC110_GPIO_F00, S5PC110_GPIO_G00, 0),
+ GPIO_ENTRY('g', S5PC110_GPIO_G00, S5PC110_GPIO_I0, 0),
+ GPIO_ENTRY('i', S5PC110_GPIO_I0, S5PC110_GPIO_J00, 0),
+ GPIO_ENTRY('j', S5PC110_GPIO_J00, S5PC110_GPIO_MP010, 0),
+ GPIO_ENTRY('h', S5PC110_GPIO_H00, S5PC110_GPIO_MAX_PORT, 0),
+ { 0 }
+};
-static inline unsigned int s5p_gpio_base(int nr)
-{
- return samsung_get_base_gpio();
-}
+/* functions */
+void gpio_cfg_pin(int gpio, int cfg);
+void gpio_set_pull(int gpio, int mode);
+void gpio_set_drv(int gpio, int mode);
+int gpio_direction_output(unsigned gpio, int value);
+int gpio_set_value(unsigned gpio, int value);
+int gpio_get_value(unsigned gpio);
+void gpio_set_rate(int gpio, int mode);
+struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio);
+int s5p_gpio_get_pin(unsigned gpio);
+
+/* GPIO pins per bank */
+#define GPIO_PER_BANK 8
#endif
/* Pin configurations */
-#define GPIO_INPUT 0x0
-#define GPIO_OUTPUT 0x1
-#define GPIO_IRQ 0xf
-#define GPIO_FUNC(x) (x)
+#define S5P_GPIO_INPUT 0x0
+#define S5P_GPIO_OUTPUT 0x1
+#define S5P_GPIO_IRQ 0xf
+#define S5P_GPIO_FUNC(x) (x)
/* Pull mode */
-#define GPIO_PULL_NONE 0x0
-#define GPIO_PULL_DOWN 0x1
-#define GPIO_PULL_UP 0x2
+#define S5P_GPIO_PULL_NONE 0x0
+#define S5P_GPIO_PULL_DOWN 0x1
+#define S5P_GPIO_PULL_UP 0x2
/* Drive Strength level */
-#define GPIO_DRV_1X 0x0
-#define GPIO_DRV_3X 0x1
-#define GPIO_DRV_2X 0x2
-#define GPIO_DRV_4X 0x3
-#define GPIO_DRV_FAST 0x0
-#define GPIO_DRV_SLOW 0x1
+#define S5P_GPIO_DRV_1X 0x0
+#define S5P_GPIO_DRV_3X 0x1
+#define S5P_GPIO_DRV_2X 0x2
+#define S5P_GPIO_DRV_4X 0x3
+#define S5P_GPIO_DRV_FAST 0x0
+#define S5P_GPIO_DRV_SLOW 0x1
#endif
#define GPIO_FULLPORT(x) ((x) >> 3)
#define GPIO_BIT(x) ((x) & 0x7)
+enum tegra_gpio_init {
+ TEGRA_GPIO_INIT_IN,
+ TEGRA_GPIO_INIT_OUT0,
+ TEGRA_GPIO_INIT_OUT1,
+};
+
+struct tegra_gpio_config {
+ u32 gpio:16;
+ u32 init:2;
+};
+
/*
* Tegra-specific GPIO API
*/
+/**
+ * Configure a list of GPIOs
+ *
+ * @param config List of GPIO configurations
+ * @param len Number of config items in list
+ */
+void gpio_config_table(const struct tegra_gpio_config *config, int len);
+
void gpio_info(void);
#define gpio_status() gpio_info()
+
#endif /* TEGRA_GPIO_H_ */
#endif
};
+#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30)
+/* Set the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */
+void pinmux_set_tristate_input_clamping(void);
+#endif
+
/* Set the mux function for a pin group */
void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
/* for mmc_config definition */
#include <mmc.h>
-#define MAX_HOSTS 4 /* Max number of 'hosts'/controllers */
-
#ifndef __ASSEMBLY__
struct tegra_mmc {
unsigned int sysad; /* _SYSTEM_ADDRESS_0 */
/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
#define VBUS_VLD_STS (1 << 26)
+#define VBUS_B_SESS_VLD_SW_VALUE (1 << 12)
+#define VBUS_B_SESS_VLD_SW_EN (1 << 11)
/* Setup USB on the board */
int usb_process_devicetree(const void *blob);
};
enum pmux_func {
+ PMUX_FUNC_DEFAULT,
PMUX_FUNC_BLINK,
PMUX_FUNC_CEC,
PMUX_FUNC_CLDVFS,
};
enum pmux_func {
+ PMUX_FUNC_DEFAULT,
PMUX_FUNC_BLINK,
PMUX_FUNC_CCLA,
PMUX_FUNC_CEC,
* purely a convenience. The translation is done through a table search.
*/
enum pmux_func {
+ PMUX_FUNC_DEFAULT,
PMUX_FUNC_AHB_CLK,
PMUX_FUNC_APB_CLK,
PMUX_FUNC_AUDIO_SYNC,
};
enum pmux_func {
+ PMUX_FUNC_DEFAULT,
PMUX_FUNC_BLINK,
PMUX_FUNC_CEC,
PMUX_FUNC_CLK_12M_OUT,
#define PAD_CTL_DSE_40ohm (6 << 3)
#define PAD_CTL_DSE_34ohm (7 << 3)
+#if defined CONFIG_MX6SL
+#define PAD_CTL_LVE (1 << 1)
+#define PAD_CTL_LVE_BIT (1 << 22)
+#endif
+
#elif defined(CONFIG_VF610)
#define PAD_MUX_MODE_SHIFT 20
--- /dev/null
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __IMX_VIDEO_H_
+#define __IMX_VIDEO_H_
+
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+
+struct display_info_t {
+ int bus;
+ int addr;
+ int pixfmt;
+ int (*detect)(struct display_info_t const *dev);
+ void (*enable)(struct display_info_t const *dev);
+ struct fb_videomode mode;
+};
+
+#ifdef CONFIG_IMX_HDMI
+extern int detect_hdmi(struct display_info_t const *dev);
+#endif
+
+#endif
ifdef CONFIG_ARM64
obj-y += crt0_64.o
else
-obj-y += crt0.o
+obj-y += vectors.o crt0.o
endif
ifndef CONFIG_SPL_BUILD
void __flush_cache(unsigned long start, unsigned long size)
{
#if defined(CONFIG_ARM1136)
- void arm1136_cache_flush(void);
- arm1136_cache_flush();
+#if !defined(CONFIG_SYS_ICACHE_OFF)
+ asm("mcr p15, 0, r1, c7, c5, 0"); /* invalidate I cache */
#endif
+
+#if !defined(CONFIG_SYS_DCACHE_OFF)
+ asm("mcr p15, 0, r1, c7, c14, 0"); /* Clean+invalidate D cache */
+#endif
+
+#endif /* CONFIG_ARM1136 */
+
#ifdef CONFIG_ARM926EJS
/* test and clean, page 2-23 of arm926ejs manual */
asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
/* disable write buffer as well (page 2-22) */
asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
-#endif
+#endif /* CONFIG_ARM926EJS */
return;
}
void flush_cache(unsigned long start, unsigned long size)
--- /dev/null
+/*
+ * vectors - Generic ARM exception table code
+ *
+ * Copyright (c) 1998 Dan Malek <dmalek@jlc.net>
+ * Copyright (c) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
+ * Copyright (c) 2000 Wolfgang Denk <wd@denx.de>
+ * Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
+ * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
+ * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
+ * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
+ * Copyright (c) 2002 Kyle Harris <kharris@nexus-tech.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ *************************************************************************
+ *
+ * Symbol _start is referenced elsewhere, so make it global
+ *
+ *************************************************************************
+ */
+
+.globl _start
+
+/*
+ *************************************************************************
+ *
+ * Vectors have their own section so linker script can map them easily
+ *
+ *************************************************************************
+ */
+
+ .section ".vectors", "x"
+
+/*
+ *************************************************************************
+ *
+ * Exception vectors as described in ARM reference manuals
+ *
+ * Uses indirect branch to allow reaching handlers anywhere in memory.
+ *
+ *************************************************************************
+ */
+
+_start:
+
+#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
+ .word CONFIG_SYS_DV_NOR_BOOT_CFG
+#endif
+
+_start:
+ ldr pc, _reset
+ ldr pc, _undefined_instruction
+ ldr pc, _software_interrupt
+ ldr pc, _prefetch_abort
+ ldr pc, _data_abort
+ ldr pc, _not_used
+ ldr pc, _irq
+ ldr pc, _fiq
+
+/*
+ *************************************************************************
+ *
+ * Indirect vectors table
+ *
+ * Symbols referenced here must be defined somewhere else
+ *
+ *************************************************************************
+ */
+
+ .globl _undefined_instruction
+ .globl _software_interrupt
+ .globl _prefetch_abort
+ .globl _data_abort
+ .globl _not_used
+ .globl _irq
+ .globl _fiq
+
+_reset: .word reset
+_undefined_instruction: .word undefined_instruction
+_software_interrupt: .word software_interrupt
+_prefetch_abort: .word prefetch_abort
+_data_abort: .word data_abort
+_not_used: .word not_used
+_irq: .word irq
+_fiq: .word fiq
+
+ .balignl 16,0xdeadbeef
+
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+
+/* SPL interrupt handling: just hang */
+
+#ifdef CONFIG_SPL_BUILD
+
+ .align 5
+undefined_instruction:
+software_interrupt:
+prefetch_abort:
+data_abort:
+not_used:
+irq:
+fiq:
+
+1:
+ bl 1b /* hang and never return */
+
+#else /* !CONFIG_SPL_BUILD */
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+ .word 0x0badc0de
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+ .word 0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+ .word 0x0badc0de
+
+#endif /* CONFIG_USE_IRQ */
+
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE 72
+
+#define S_OLD_R0 68
+#define S_PSR 64
+#define S_PC 60
+#define S_LR 56
+#define S_SP 52
+
+#define S_IP 48
+#define S_FP 44
+#define S_R10 40
+#define S_R9 36
+#define S_R8 32
+#define S_R7 28
+#define S_R6 24
+#define S_R5 20
+#define S_R4 16
+#define S_R3 12
+#define S_R2 8
+#define S_R1 4
+#define S_R0 0
+
+#define MODE_SVC 0x13
+#define I_BIT 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+ .macro bad_save_user_regs
+ @ carve out a frame on current user stack
+ sub sp, sp, #S_FRAME_SIZE
+ stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
+ ldr r2, IRQ_STACK_START_IN
+ @ get values for "aborted" pc and cpsr (into parm regs)
+ ldmia r2, {r2 - r3}
+ add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
+ add r5, sp, #S_SP
+ mov r1, lr
+ stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
+ mov r0, sp @ save current stack into r0 (param register)
+ .endm
+
+ .macro irq_save_user_regs
+ sub sp, sp, #S_FRAME_SIZE
+ stmia sp, {r0 - r12} @ Calling r0-r12
+ @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
+ add r8, sp, #S_PC
+ stmdb r8, {sp, lr}^ @ Calling SP, LR
+ str lr, [r8, #0] @ Save calling PC
+ mrs r6, spsr
+ str r6, [r8, #4] @ Save CPSR
+ str r0, [r8, #8] @ Save OLD_R0
+ mov r0, sp
+ .endm
+
+ .macro irq_restore_user_regs
+ ldmia sp, {r0 - lr}^ @ Calling r0 - lr
+ mov r0, r0
+ ldr lr, [sp, #S_PC] @ Get PC
+ add sp, sp, #S_FRAME_SIZE
+ subs pc, lr, #4 @ return & move spsr_svc into cpsr
+ .endm
+
+ .macro get_bad_stack
+ ldr r13, IRQ_STACK_START_IN @ setup our mode stack
+
+ str lr, [r13] @ save caller lr in position 0 of saved stack
+ mrs lr, spsr @ get the spsr
+ str lr, [r13, #4] @ save spsr in position 1 of saved stack
+ mov r13, #MODE_SVC @ prepare SVC-Mode
+ @ msr spsr_c, r13
+ msr spsr, r13 @ switch modes, make sure moves will execute
+ mov lr, pc @ capture return pc
+ movs pc, lr @ jump to next instruction & switch modes.
+ .endm
+
+ .macro get_irq_stack @ setup IRQ stack
+ ldr sp, IRQ_STACK_START
+ .endm
+
+ .macro get_fiq_stack @ setup FIQ stack
+ ldr sp, FIQ_STACK_START
+ .endm
+
+/*
+ * exception handlers
+ */
+
+ .align 5
+undefined_instruction:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_undefined_instruction
+
+ .align 5
+software_interrupt:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_software_interrupt
+
+ .align 5
+prefetch_abort:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_prefetch_abort
+
+ .align 5
+data_abort:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_data_abort
+
+ .align 5
+not_used:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+ .align 5
+irq:
+ get_irq_stack
+ irq_save_user_regs
+ bl do_irq
+ irq_restore_user_regs
+
+ .align 5
+fiq:
+ get_fiq_stack
+ /* someone ought to write a more effiction fiq_save_user_regs */
+ irq_save_user_regs
+ bl do_fiq
+ irq_restore_user_regs
+
+#else
+
+ .align 5
+irq:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_irq
+
+ .align 5
+fiq:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_fiq
+
+#endif /* CONFIG_USE_IRQ */
+
+#endif /* CONFIG_SPL_BUILD */
obj-$(CONFIG_PPC_P5040) += p5040_ids.o
obj-$(CONFIG_PPC_T4240) += t4240_ids.o
obj-$(CONFIG_PPC_T4160) += t4240_ids.o
+obj-$(CONFIG_PPC_T4080) += t4240_ids.o
obj-$(CONFIG_PPC_B4420) += b4860_ids.o
obj-$(CONFIG_PPC_B4860) += b4860_ids.o
obj-$(CONFIG_PPC_T1040) += t1040_ids.o
obj-$(CONFIG_PPC_P5040) += p5040_serdes.o
obj-$(CONFIG_PPC_T4240) += t4240_serdes.o
obj-$(CONFIG_PPC_T4160) += t4240_serdes.o
+obj-$(CONFIG_PPC_T4080) += t4240_serdes.o
obj-$(CONFIG_PPC_B4420) += b4860_serdes.o
obj-$(CONFIG_PPC_B4860) += b4860_serdes.o
obj-$(CONFIG_BSC9132) += bsc9132_serdes.o
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
check_erratum_a007212();
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
+ puts("Work-around for Erratum A-005434 enabled\n");
+#endif
return 0;
}
major = SVR_MAJ(svr);
minor = SVR_MIN(svr);
+#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
+ if (SVR_SOC_VER(svr) == SVR_T4080) {
+ ccsr_rcpm_t *rcpm =
+ (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+
+ setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
+ FSL_CORENET_DEVDISR2_DTSEC1_9);
+ setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
+ setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
+
+ /* It needs SW to disable core4~7 as HW design sake on T4080 */
+ for (i = 4; i < 8; i++)
+ cpu_disable(i);
+
+ /* request core4~7 into PH20 state, prior to entering PCL10
+ * state, all cores in cluster should be placed in PH20 state.
+ */
+ setbits_be32(&rcpm->pcph20setr, 0xf0);
+
+ /* put the 2nd cluster into PCL10 state */
+ setbits_be32(&rcpm->clpcl10setr, 1 << 1);
+ }
+#endif
+
if (cpu_numcores() > 1) {
#ifndef CONFIG_MP
puts("Unicore software on multiprocessor system!!\n"
}
#endif
-void cpu_init_f (void)
+ulong cpu_init_f(void)
{
+ ulong flag = 0;
extern void m8560_cpm_reset (void);
#ifdef CONFIG_SYS_DCSRBAR_PHYS
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
#endif
#if defined(CONFIG_SECURE_BOOT)
struct law_entry law;
#ifdef CONFIG_DEEP_SLEEP
/* disable the console if boot from deep sleep */
if (in_be32(&gur->scrtsr[0]) & (1 << 3))
- gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+ flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
#endif
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
fsl_erratum_a007212_workaround();
#endif
+ return flag;
}
/* Implement a dummy function for those platforms w/o SERDES */
int enable_cluster_l2(void)
{
int i = 0;
- u32 cluster;
+ u32 cluster, svr = get_svr();
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
struct ccsr_cluster_l2 __iomem *l2cache;
+ /* only the L2 of first cluster should be enabled as expected on T4080,
+ * but there is no EOC in the first cluster as HW sake, so return here
+ * to skip enabling L2 cache of the 2nd cluster.
+ */
+ if (SVR_SOC_VER(svr) == SVR_T4080)
+ return 0;
+
cluster = in_be32(&gur->tp_cluster[i].lower);
if (cluster & TP_CLUSTER_EOC)
return 0;
}
#endif
+ init_used_tlb_cams();
return 0;
}
for (i = 0; i < sizeof(gd_t); i++)
((char *)gd)[i] = 0;
+#ifdef CONFIG_QEMU_E500
/*
* CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
* so we need to populate it before it accesses it.
*/
gd->fdt_blob = fdt;
+#endif
mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
* T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
* it uses 6.
*/
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+ defined(CONFIG_PPC_T4080)
if (SVR_MAJ(get_svr()) >= 2)
mem_pll_rat *= 2;
#endif
DECLARE_GLOBAL_DATA_PTR;
-void cpu_init_f(void)
+ulong cpu_init_f(void)
{
#ifdef CONFIG_SYS_INIT_L2_ADDR
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
out_be32(&l2cache->l2ctl,
(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
#endif
+
+ return 0;
}
#ifndef CONFIG_SYS_FSL_TBCLK_DIV
#endif
mtspr HID0,r0
-#ifndef CONFIG_E500MC
+#if !defined(CONFIG_E500MC) && !defined(CONFIG_QEMU_E500)
li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mfspr r3,PVR
andi. r3,r3, 0xff
mtmsr r3
isync
- bl cpu_init_f
+ bl cpu_init_f /* return boot_flag for calling board_init_f */
bl board_init_f
isync
};
#endif
+#ifdef CONFIG_SYS_SRIO
struct srio_liodn_id_table srio_liodn_tbl[] = {
SET_SRIO_LIODN_BASE(1, 307),
SET_SRIO_LIODN_BASE(2, 387),
};
int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
+#endif
struct liodn_id_table liodn_tbl[] = {
#ifdef CONFIG_SYS_DPAA_QBMAN
{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
{}
};
-#elif defined(CONFIG_PPC_T4160)
+#elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
static const struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
{1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
/* bl l2cache_enable */
/* run 1st part of board init code (from Flash) */
+ li r3, 0 /* clear boot_flag for calling board_init_f */
bl board_init_f
sync
CPU_TYPE_ENTRY(T4240, T4240, 0),
CPU_TYPE_ENTRY(T4120, T4120, 0),
CPU_TYPE_ENTRY(T4160, T4160, 0),
+ CPU_TYPE_ENTRY(T4080, T4080, 4),
CPU_TYPE_ENTRY(B4860, B4860, 0),
CPU_TYPE_ENTRY(G4860, G4860, 0),
CPU_TYPE_ENTRY(G4060, G4060, 0),
CPU_TYPE_ENTRY(B4440, B4440, 0),
+ CPU_TYPE_ENTRY(B4460, B4460, 0),
CPU_TYPE_ENTRY(G4440, G4440, 0),
CPU_TYPE_ENTRY(B4420, B4420, 0),
CPU_TYPE_ENTRY(B4220, B4220, 0),
/*
* Return a 32-bit mask indicating which cores are present on this SOC.
*/
-u32 cpu_mask(void)
+__weak u32 cpu_mask(void)
{
ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
struct cpu_type *cpu = gd->arch.cpu;
/*
* Return the number of cores on this SOC.
*/
-int cpu_numcores(void)
+__weak int cpu_numcores(void)
{
struct cpu_type *cpu = gd->arch.cpu;
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
#elif defined(CONFIG_P1021)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_ERRATUM_A005434
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
#define CONFIG_ESDHC_HC_BLK_ADDR
-#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+ defined(CONFIG_PPC_T4080)
#define CONFIG_E6500
#define CONFIG_SYS_PPC64 /* 64-bit core */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_NUM_FM2_10GEC 2
#define CONFIG_NUM_DDR_CONTROLLERS 3
#else
-#define CONFIG_MAX_CPUS 8
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
-#define CONFIG_SYS_NUM_FM1_DTSEC 7
+#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_SYS_NUM_FM2_DTSEC 7
+#define CONFIG_SYS_NUM_FM2_DTSEC 8
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 2
+#if defined(CONFIG_PPC_T4160)
+#define CONFIG_MAX_CPUS 8
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
+#elif defined(CONFIG_PPC_T4080)
+#define CONFIG_MAX_CPUS 4
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 }
+#endif
#endif
#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_ISBC_VER 2
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_A006261
+#define CONFIG_SYS_FSL_ERRATUM_A006593
+#define CONFIG_SYS_FSL_ERRATUM_A006379
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
u32 svr = get_svr();
if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) ||
((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) ||
+ ((SVR_SOC_VER(svr) == SVR_T4080) && SVR_MAJ(svr) <= 1) ||
((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) ||
((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) ||
((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) ||
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
case SVR_T4240:
case SVR_T4160:
+ case SVR_T4080:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
case SVR_T1040:
return IS_SVR_REV(svr, 1, 0);
+ case SVR_T2080:
+ case SVR_T2081:
+ return IS_SVR_REV(svr, 1, 0);
case SVR_P5040:
return IS_SVR_REV(svr, 1, 0);
}
#if defined(CONFIG_B4860QDS) || \
defined(CONFIG_T4240QDS) || \
defined(CONFIG_T2080QDS) || \
+ defined(CONFIG_T2080RDB) || \
defined(CONFIG_T1040QDS) || \
- defined(CONFIG_T1040RDB)
+ defined(CONFIG_T104xRDB)
#define CONFIG_SYS_CPC_REINIT_F
#undef CONFIG_SYS_INIT_L3_ADDR
#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
/* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+ defined(CONFIG_PPC_T4080)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
#endif
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+ defined(CONFIG_PPC_T4080)
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
#define SVR_T4240 0x824000
#define SVR_T4120 0x824001
#define SVR_T4160 0x824100
+#define SVR_T4080 0x824102
#define SVR_C291 0x850000
#define SVR_C292 0x850020
#define SVR_C293 0x850030
#define SVR_B4860 0X868000
#define SVR_G4860 0x868001
+#define SVR_B4460 0x868003
#define SVR_G4060 0x868003
#define SVR_B4440 0x868100
#define SVR_G4440 0x868101
#
-obj-y += interrupts.o sandbox.o
+obj-y += interrupts.o
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <i2c.h>
return rv;
}
#endif /* CONFIG_DRIVER_TI_CPSW */
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(1, 0, 0, -1, -1);
+}
+#endif
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/sata.h>
#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <micrel.h>
#include <miiphy.h>
#include <netdev.h>
-#include <linux/fb.h>
-#include <ipu_pixfmt.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mxc_hdmi.h>
#include <i2c.h>
#ifdef CONFIG_MXC_SPI
iomux_v3_cfg_t const ecspi1_pads[] = {
/* SS1 */
- MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
};
-struct display_info_t {
- int bus;
- int addr;
- int pixfmt;
- int (*detect)(struct display_info_t const *dev);
- void (*enable)(struct display_info_t const *dev);
- struct fb_videomode mode;
-};
-
-
-static int detect_hdmi(struct display_info_t const *dev)
-{
- struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
- return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
-}
-
static void do_enable_hdmi(struct display_info_t const *dev)
{
imx_enable_hdmi_phy();
gpio_direction_output(RGB_BACKLIGHT_GP, 1);
}
-static struct display_info_t const displays[] = {{
+struct display_info_t const displays[] = {{
.bus = -1,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB24,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
} } };
-
-int board_video_skip(void)
-{
- int i;
- int ret;
- char const *panel = getenv("panel");
- if (!panel) {
- for (i = 0; i < ARRAY_SIZE(displays); i++) {
- struct display_info_t const *dev = displays+i;
- if (dev->detect(dev)) {
- panel = dev->mode.name;
- printf("auto-detected panel %s\n", panel);
- break;
- }
- }
- if (!panel) {
- panel = displays[0].mode.name;
- printf("No panel detected: default to %s\n", panel);
- i = 0;
- }
- } else {
- for (i = 0; i < ARRAY_SIZE(displays); i++) {
- if (!strcmp(panel, displays[i].mode.name))
- break;
- }
- }
- if (i < ARRAY_SIZE(displays)) {
- ret = ipuv3_fb_init(&displays[i].mode, 0,
- displays[i].pixfmt);
- if (!ret) {
- displays[i].enable(displays+i);
- printf("Display: %s (%ux%u)\n",
- displays[i].mode.name,
- displays[i].mode.xres,
- displays[i].mode.yres);
- } else {
- printf("LCD %s cannot be configured: %d\n",
- displays[i].mode.name, ret);
- }
- } else {
- printf("unsupported panel %s\n", panel);
- ret = -EINVAL;
- }
- return (0 != ret);
-}
+size_t display_count = ARRAY_SIZE(displays);
static void setup_display(void)
{
.text :
{
*(.__image_copy_start)
+ *(.vectors)
CPUDIR/start.o (.text*)
board/compulab/cm_t335/built-in.o (.text*)
*(.text*)
--- /dev/null
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx6boards.o
--- /dev/null
+/*
+ * Copyright (C) 2014 Eukréa Electromatique
+ * Author: Eric Bénard <eric@eukrea.com>
+ * Fabio Estevam <fabio.estevam@freescale.com>
+ * Jon Nettleton <jon.nettleton@gmail.com>
+ *
+ * based on sabresd.c which is :
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * and on hummingboard.c which is :
+ * Copyright (C) 2013 SolidRun ltd.
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/video.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
+ PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+static int board_type = -1;
+#define BOARD_IS_MARSBOARD 0
+#define BOARD_IS_RIOTBOARD 1
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart2_pads[] = {
+ MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+iomux_v3_cfg_t const enet_pads[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* GPIO16 -> AR8035 25MHz */
+ MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+ /* AR8035 PHY Reset */
+ MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+ /* AR8035 PHY Interrupt */
+ MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+ /* Reset AR8035 PHY */
+ gpio_direction_output(IMX_GPIO_NR(3, 31) , 0);
+ mdelay(2);
+ gpio_set_value(IMX_GPIO_NR(3, 31), 1);
+}
+
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+ /* from linux/arch/arm/mach-imx/mach-imx6q.c :
+ * Ar803x phy SmartEEE feature cause link status generates glitch,
+ * which cause ethernet link down/up issue, so disable SmartEEE
+ */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ mx6_rgmii_rework(phydev);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
+ MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
+ MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const riotboard_usdhc3_pads[] = {
+ MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
+ MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
+ MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ /* eMMC RST */
+ MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[3] = {
+ {USDHC2_BASE_ADDR},
+ {USDHC3_BASE_ADDR},
+ {USDHC4_BASE_ADDR},
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
+#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 0)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC2_BASE_ADDR:
+ ret = !gpio_get_value(USDHC2_CD_GPIO);
+ break;
+ case USDHC3_BASE_ADDR:
+ if (board_type == BOARD_IS_RIOTBOARD)
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ else if (board_type == BOARD_IS_MARSBOARD)
+ ret = 1; /* eMMC/uSDHC3 is always present */
+ break;
+ case USDHC4_BASE_ADDR:
+ ret = 1; /* eMMC/uSDHC4 is always present */
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ s32 status = 0;
+ int i;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * ** RiOTboard :
+ * mmc0 SDCard slot (bottom)
+ * mmc1 uSDCard slot (top)
+ * mmc2 eMMC
+ * ** MarSBoard :
+ * mmc0 uSDCard slot (bottom)
+ * mmc1 eMMC
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ gpio_direction_input(USDHC2_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ usdhc_cfg[0].max_bus_width = 4;
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ if (board_type == BOARD_IS_RIOTBOARD) {
+ imx_iomux_v3_setup_multiple_pads(
+ riotboard_usdhc3_pads,
+ ARRAY_SIZE(riotboard_usdhc3_pads));
+ gpio_direction_input(USDHC3_CD_GPIO);
+ gpio_direction_output(IMX_GPIO_NR(7, 8) , 0);
+ udelay(250);
+ gpio_set_value(IMX_GPIO_NR(7, 8), 1);
+ }
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[1].max_bus_width = 4;
+ break;
+ case 2:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ usdhc_cfg[2].max_bus_width = 4;
+ gpio_direction_output(IMX_GPIO_NR(6, 8) , 0);
+ udelay(250);
+ gpio_set_value(IMX_GPIO_NR(6, 8), 1);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) then supported by the board (%d)\n",
+ i + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ return status;
+ }
+
+ status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ }
+
+ return status;
+}
+#endif
+
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t const ecspi1_pads[] = {
+ MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_spi(void)
+{
+ imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+}
+#endif
+
+struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(5, 27)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(5, 26)
+ }
+};
+
+struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
+struct i2c_pads_info i2c_pad_info3 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(1, 5)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(1, 6)
+ }
+};
+
+iomux_v3_cfg_t const tft_pads_riot[] = {
+ /* LCD_PWR_EN */
+ MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* TOUCH_INT */
+ MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* LED_PWR_EN */
+ MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* BL LEVEL */
+ MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const tft_pads_mars[] = {
+ /* LCD_PWR_EN */
+ MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* TOUCH_INT */
+ MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* LED_PWR_EN */
+ MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* BL LEVEL (PWM4) */
+ MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#if defined(CONFIG_VIDEO_IPUV3)
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+ struct iomuxc *iomux = (struct iomuxc *)
+ IOMUXC_BASE_ADDR;
+ setbits_le32(&iomux->gpr[2],
+ IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT);
+ /* set backlight level to ON */
+ if (board_type == BOARD_IS_RIOTBOARD)
+ gpio_direction_output(IMX_GPIO_NR(1, 18) , 1);
+ else if (board_type == BOARD_IS_MARSBOARD)
+ gpio_direction_output(IMX_GPIO_NR(2, 10) , 1);
+}
+
+static void disable_lvds(struct display_info_t const *dev)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* set backlight level to OFF */
+ if (board_type == BOARD_IS_RIOTBOARD)
+ gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
+ else if (board_type == BOARD_IS_MARSBOARD)
+ gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
+
+ clrbits_le32(&iomux->gpr[2],
+ IOMUXC_GPR2_LVDS_CH0_MODE_MASK);
+}
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+ disable_lvds(dev);
+ imx_enable_hdmi_phy();
+}
+
+static int detect_i2c(struct display_info_t const *dev)
+{
+ return (0 == i2c_set_bus_num(dev->bus)) &&
+ (0 == i2c_probe(dev->addr));
+}
+
+struct display_info_t const displays[] = {{
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = do_enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = 2,
+ .addr = 0x1,
+ .pixfmt = IPU_PIX_FMT_LVDS666,
+ .detect = detect_i2c,
+ .enable = enable_lvds,
+ .mode = {
+ .name = "LCD8000-97C",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 100,
+ .right_margin = 200,
+ .upper_margin = 10,
+ .lower_margin = 20,
+ .hsync_len = 20,
+ .vsync_len = 8,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int reg;
+
+ enable_ipu_clock();
+ imx_setup_hdmi();
+
+ /* Turn on LDB0, IPU,IPU DI0 clocks */
+ setbits_le32(&mxc_ccm->CCGR3,
+ MXC_CCM_CCGR3_LDB_DI0_MASK);
+
+ /* set LDB0 clk select to 011/011 */
+ clrsetbits_le32(&mxc_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
+ (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
+
+ setbits_le32(&mxc_ccm->cscmr2,
+ MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+
+ setbits_le32(&mxc_ccm->chsccdr,
+ (CHSCCDR_CLK_SEL_LDB_DI0
+ << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
+
+ reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+ | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+ | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+ | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+ | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+ | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+ | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
+ | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+ writel(reg, &iomux->gpr[2]);
+
+ clrsetbits_le32(&iomux->gpr[3],
+ IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
+ IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
+ IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+ << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ setup_iomux_enet();
+
+ return cpu_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+ u32 cputype = cpu_type(get_cpu_rev());
+
+ switch (cputype) {
+ case MXC_CPU_MX6SOLO:
+ board_type = BOARD_IS_RIOTBOARD;
+ break;
+ case MXC_CPU_MX6D:
+ board_type = BOARD_IS_MARSBOARD;
+ break;
+ }
+
+ setup_iomux_uart();
+
+ if (board_type == BOARD_IS_RIOTBOARD)
+ imx_iomux_v3_setup_multiple_pads(
+ tft_pads_riot, ARRAY_SIZE(tft_pads_riot));
+ else if (board_type == BOARD_IS_MARSBOARD)
+ imx_iomux_v3_setup_multiple_pads(
+ tft_pads_mars, ARRAY_SIZE(tft_pads_mars));
+#if defined(CONFIG_VIDEO_IPUV3)
+ /* power ON LCD */
+ gpio_direction_output(IMX_GPIO_NR(1, 29) , 1);
+ /* touch interrupt is an input */
+ gpio_direction_input(IMX_GPIO_NR(6, 14));
+ /* power ON backlight */
+ gpio_direction_output(IMX_GPIO_NR(6, 15) , 1);
+ /* set backlight level to off */
+ if (board_type == BOARD_IS_RIOTBOARD)
+ gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
+ else if (board_type == BOARD_IS_MARSBOARD)
+ gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
+ setup_display();
+#endif
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+ /* i2c1 : PMIC, Audio codec on RiOT, Expansion connector on MarS */
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+ /* i2c2 : HDMI EDID */
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+ /* i2c3 : LVDS, Expansion connector */
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
+#ifdef CONFIG_MXC_SPI
+ setup_spi();
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode riotboard_boot_modes[] = {
+ {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+ {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+ {NULL, 0},
+};
+static const struct boot_mode marsboard_boot_modes[] = {
+ {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+ {"emmc", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ if (board_type == BOARD_IS_RIOTBOARD)
+ add_board_boot_modes(riotboard_boot_modes);
+ else if (board_type == BOARD_IS_RIOTBOARD)
+ add_board_boot_modes(marsboard_boot_modes);
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: ");
+ if (board_type == BOARD_IS_MARSBOARD)
+ puts("MarSBoard\n");
+ else if (board_type == BOARD_IS_RIOTBOARD)
+ puts("RIoTboard\n");
+ else
+ printf("unknown - cputype : %02x\n", cpu_type(get_cpu_rev()));
+
+ return 0;
+}
#include "../common/qixis.h"
#include "../common/vsc3316_3308.h"
#include "../common/idt8t49n222a_serdes_clk.h"
+#include "../common/zm7300.h"
#include "b4860qds.h"
#include "b4860qds_qixis.h"
#include "b4860qds_crossbar_con.h"
return 0;
}
+/*
+ * read_voltage from sensor on I2C bus
+ * We use average of 4 readings, waiting for 532us befor another reading
+ */
+#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
+#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
+
+static inline int read_voltage(void)
+{
+ int i, ret, voltage_read = 0;
+ u16 vol_mon;
+
+ for (i = 0; i < NUM_READINGS; i++) {
+ ret = i2c_read(I2C_VOL_MONITOR_ADDR,
+ I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
+ if (ret) {
+ printf("VID: failed to read core voltage\n");
+ return ret;
+ }
+ if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
+ printf("VID: Core voltage sensor error\n");
+ return -1;
+ }
+ debug("VID: bus voltage reads 0x%04x\n", vol_mon);
+ /* LSB = 4mv */
+ voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
+ udelay(WAIT_FOR_ADC);
+ }
+ /* calculate the average */
+ voltage_read /= NUM_READINGS;
+
+ return voltage_read;
+}
+
+static int adjust_vdd(ulong vdd_override)
+{
+ int re_enable = disable_interrupts();
+ ccsr_gur_t __iomem *gur =
+ (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 fusesr;
+ u8 vid;
+ int vdd_target, vdd_last;
+ int existing_voltage, temp_voltage, voltage; /* all in 1/10 mV */
+ int ret;
+ unsigned int orig_i2c_speed;
+ unsigned long vdd_string_override;
+ char *vdd_string;
+ static const uint16_t vdd[32] = {
+ 0, /* unused */
+ 9875, /* 0.9875V */
+ 9750,
+ 9625,
+ 9500,
+ 9375,
+ 9250,
+ 9125,
+ 9000,
+ 8875,
+ 8750,
+ 8625,
+ 8500,
+ 8375,
+ 8250,
+ 8125,
+ 10000, /* 1.0000V */
+ 10125,
+ 10250,
+ 10375,
+ 10500,
+ 10625,
+ 10750,
+ 10875,
+ 11000,
+ 0, /* reserved */
+ };
+ struct vdd_drive {
+ u8 vid;
+ unsigned voltage;
+ };
+
+ ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
+ if (ret) {
+ printf("VID: I2c failed to switch channel\n");
+ ret = -1;
+ goto exit;
+ }
+
+ /* get the voltage ID from fuse status register */
+ fusesr = in_be32(&gur->dcfg_fusesr);
+ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
+ FSL_CORENET_DCFG_FUSESR_VID_MASK;
+ if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
+ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
+ FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
+ }
+ vdd_target = vdd[vid];
+ debug("VID:Reading from from fuse,vid=%x vdd is %dmV\n",
+ vid, vdd_target/10);
+
+ /* check override variable for overriding VDD */
+ vdd_string = getenv("b4qds_vdd_mv");
+ if (vdd_override == 0 && vdd_string &&
+ !strict_strtoul(vdd_string, 10, &vdd_string_override))
+ vdd_override = vdd_string_override;
+ if (vdd_override >= 819 && vdd_override <= 1212) {
+ vdd_target = vdd_override * 10; /* convert to 1/10 mV */
+ debug("VDD override is %lu\n", vdd_override);
+ } else if (vdd_override != 0) {
+ printf("Invalid value.\n");
+ }
+
+ if (vdd_target == 0) {
+ printf("VID: VID not used\n");
+ ret = 0;
+ goto exit;
+ }
+
+ /*
+ * Read voltage monitor to check real voltage.
+ * Voltage monitor LSB is 4mv.
+ */
+ vdd_last = read_voltage();
+ if (vdd_last < 0) {
+ printf("VID: abort VID adjustment\n");
+ ret = -1;
+ goto exit;
+ }
+
+ debug("VID: Core voltage is at %d mV\n", vdd_last);
+ ret = select_i2c_ch_pca(I2C_MUX_CH_DPM);
+ if (ret) {
+ printf("VID: I2c failed to switch channel to DPM\n");
+ ret = -1;
+ goto exit;
+ }
+
+ /* Round up to the value of step of Voltage regulator */
+ voltage = roundup(vdd_target, ZM_STEP);
+ debug("VID: rounded up voltage = %d\n", voltage);
+
+ /* lower the speed to 100kHz to access ZM7300 device */
+ debug("VID: Setting bus speed to 100KHz if not already set\n");
+ orig_i2c_speed = i2c_get_bus_speed();
+ if (orig_i2c_speed != 100000)
+ i2c_set_bus_speed(100000);
+
+ /* Read the existing level on board, if equal to requsted one,
+ no need to re-set */
+ existing_voltage = zm_read_voltage();
+
+ /* allowing the voltage difference of one step 0.0125V acceptable */
+ if ((existing_voltage >= voltage) &&
+ (existing_voltage < (voltage + ZM_STEP))) {
+ debug("VID: voltage already set as requested,returning\n");
+ ret = existing_voltage;
+ goto out;
+ }
+ debug("VID: Changing voltage for board from %dmV to %dmV\n",
+ existing_voltage/10, voltage/10);
+
+ if (zm_disable_wp() < 0) {
+ ret = -1;
+ goto out;
+ }
+ /* Change Voltage: the change is done through all the steps in the
+ way, to avoid reset to the board due to power good signal fail
+ in big voltage change gap jump.
+ */
+ if (existing_voltage > voltage) {
+ temp_voltage = existing_voltage - ZM_STEP;
+ while (temp_voltage >= voltage) {
+ ret = zm_write_voltage(temp_voltage);
+ if (ret == temp_voltage) {
+ temp_voltage -= ZM_STEP;
+ } else {
+ /* ZM7300 device failed to set
+ * the voltage */
+ printf
+ ("VID:Stepping down vol failed:%dmV\n",
+ temp_voltage/10);
+ ret = -1;
+ goto out;
+ }
+ }
+ } else {
+ temp_voltage = existing_voltage + ZM_STEP;
+ while (temp_voltage < (voltage + ZM_STEP)) {
+ ret = zm_write_voltage(temp_voltage);
+ if (ret == temp_voltage) {
+ temp_voltage += ZM_STEP;
+ } else {
+ /* ZM7300 device failed to set
+ * the voltage */
+ printf
+ ("VID:Stepping up vol failed:%dmV\n",
+ temp_voltage/10);
+ ret = -1;
+ goto out;
+ }
+ }
+ }
+
+ if (zm_enable_wp() < 0)
+ ret = -1;
+
+ /* restore the speed to 400kHz */
+out: debug("VID: Restore the I2C bus speed to %dKHz\n",
+ orig_i2c_speed/1000);
+ i2c_set_bus_speed(orig_i2c_speed);
+ if (ret < 0)
+ goto exit;
+
+ ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
+ if (ret) {
+ printf("VID: I2c failed to switch channel\n");
+ ret = -1;
+ goto exit;
+ }
+ vdd_last = read_voltage();
+ select_i2c_ch_pca(I2C_CH_DEFAULT);
+
+ if (vdd_last > 0)
+ printf("VID: Core voltage %d mV\n", vdd_last);
+ else
+ ret = -1;
+
+exit:
+ if (re_enable)
+ enable_interrupts();
+ return ret;
+}
+
int configure_vsc3316_3308(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals();
#endif
+ /*
+ * Adjust core voltage according to voltage ID
+ * This function changes I2C mux to channel 2.
+ */
+ if (adjust_vdd(0) < 0)
+ printf("Warning: Adjusting core voltage failed\n");
+
/* SerDes1 refclks need to be set again, as default clks
* are not suitable for CPRI and onboard SGMIIs to work
* simultaneously.
obj-$(CONFIG_P5040DS) += ics307_clk.o
obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o
obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o
+obj-$(CONFIG_ZM7300) += zm7300.o
# deal with common files for P-series corenet based devices
obj-$(CONFIG_P2041RDB) += p_corenet/
/* some boards with non-256-bytes EEPROM have special define */
/* for MAX_NUM_PORTS in board-specific file */
#ifndef MAX_NUM_PORTS
-#define MAX_NUM_PORTS 23
+#define MAX_NUM_PORTS 16
#endif
#define NXID_VERSION 1
#endif
u8 res_1[21]; /* 0x2b - 0x3f Reserved */
u8 mac_count; /* 0x40 Number of MAC addresses */
u8 mac_flag; /* 0x41 MAC table flags */
- u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - x MAC addresses */
- u32 crc; /* x+1 CRC32 checksum */
+ u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0xa1 MAC addresses */
+ u8 res_2[90]; /* 0xa2 - 0xfb Reserved */
+ u32 crc; /* 0xfc - 0xff CRC32 checksum */
#endif
} e;
if (read_eeprom()) {
printf("Read failed.\n");
- return -1;
+ return 0;
}
if (!is_valid) {
printf("Invalid ID (%02x %02x %02x %02x)\n",
e.id[0], e.id[1], e.id[2], e.id[3]);
- return -1;
+ return 0;
}
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
crcp = (void *)&e + crc_offset;
if (crc != be32_to_cpu(*crcp)) {
printf("CRC mismatch (%08x != %08x)\n", crc, be32_to_cpu(e.crc));
- return -1;
+ return 0;
}
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
--- /dev/null
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Power-One ZM7300 DPM */
+#include "zm7300.h"
+
+#define DPM_WP 0x96
+#define WRP_OPCODE 0x01
+#define WRM_OPCODE 0x02
+#define RRP_OPCODE 0x11
+
+#define DPM_SUCCESS 0x01
+#define DPM_EXEC_FAIL 0x00
+
+static const uint16_t hex_to_1_10mv[] = {
+ 5000,
+ 5125,
+ 5250,
+ 5375,
+ 5500,
+ 5625,
+ 5750,
+ 5875,
+ 6000,
+ 6125,
+ 6250,
+ 6375,
+ 6500,
+ 6625,
+ 6750,
+ 6875,
+ 7000,
+ 7125,
+ 7250,
+ 7375,
+ 7500,
+ 7625,
+ 7750,
+ 7875,
+ 8000,
+ 8125,
+ 8250,
+ 8375,
+ 8500,
+ 8625,
+ 8750,
+ 8875,
+ 9000,
+ 9125,
+ 9250,
+ 9375,
+ 9500, /* 0.95mV */
+ 9625,
+ 9750,
+ 9875,
+ 10000, /* 1.0V */
+ 10125,
+ 10250,
+ 10375,
+ 10500,
+ 10625,
+ 10750,
+ 10875,
+ 11000,
+ 11125,
+ 11250,
+ 11375,
+ 11500,
+ 11625,
+ 11750,
+ 11875,
+ 12000,
+ 12125,
+ 12250,
+ 12375,
+ 0, /* reserved */
+};
+
+
+/* Read Data d from Register r of POL p */
+u8 dpm_rrp(uchar r)
+{
+ u8 ret[5];
+
+ ret[0] = RRP_OPCODE;
+ /* POL is 0 */
+ ret[1] = 0;
+ ret[2] = r;
+ i2c_read(I2C_DPM_ADDR, 0, -3, ret, 2);
+ if (ret[1] == DPM_SUCCESS) { /* the DPM returned success as status */
+ debug("RRP_OPCODE returned success data is %x\n", ret[0]);
+ return ret[0];
+ } else {
+ return -1;
+ }
+}
+
+/* Write Data d into DPM register r (RAM) */
+int dpm_wrm(u8 r, u8 d)
+{
+ u8 ret[5];
+
+ ret[0] = WRM_OPCODE;
+ ret[1] = r;
+ ret[2] = d;
+ i2c_read(I2C_DPM_ADDR, 0, -3, ret, 1);
+ if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */
+ debug("WRM_OPCODE returned success data is %x\n", ret[0]);
+ return ret[0];
+ } else {
+ return -1;
+ }
+}
+
+/* Write Data d into Register r of POL(s) a */
+int dpm_wrp(u8 r, u8 d)
+{
+ u8 ret[7];
+
+ ret[0] = WRP_OPCODE;
+ /* only POL0 is present */
+ ret[1] = 0x01;
+ ret[2] = 0x00;
+ ret[3] = 0x00;
+ ret[4] = 0x00;
+ ret[5] = r;
+ ret[6] = d;
+ i2c_read(I2C_DPM_ADDR, 0, -7, ret, 1);
+ if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */
+ debug("WRP_OPCODE returned success data is %x\n", ret[0]);
+ return 0;
+ } else {
+ return -1;
+ }
+}
+
+/* Uses the DPM command RRP */
+u8 zm_read(uchar reg)
+{
+ u8 d;
+ d = dpm_rrp(reg);
+ return d;
+}
+
+/* ZM_write --
+ Steps:
+ a. Write data to the register
+ b. Read data from register and compare to written value
+ c. Return return_code & voltage_read
+*/
+u8 zm_write(u8 reg, u8 data)
+{
+ u8 d;
+
+ /* write data to register */
+ dpm_wrp(reg, data);
+
+ /* read register and compare to written value */
+ d = dpm_rrp(reg);
+ if (d != data) {
+ printf("zm_write : Comparison register data failed\n");
+ return -1;
+ }
+
+ return d;
+}
+
+/* zm_write_out_voltage
+ * voltage in 1/10 mV
+ */
+int zm_write_voltage(int voltage)
+{
+ u8 reg = 0x7, vid;
+ uint16_t voltage_read;
+ u8 ret;
+
+ vid = (voltage - 5000) / ZM_STEP;
+
+ ret = zm_write(reg, vid);
+ if (ret != -1) {
+ voltage_read = hex_to_1_10mv[ret];
+ debug("voltage set to %dmV\n", voltage_read/10);
+ return voltage_read;
+ }
+ return -1;
+}
+
+/* zm_read_out_voltage
+ * voltage in 1/10 mV
+ */
+int zm_read_voltage(void)
+{
+ u8 reg = 0x7;
+ u8 ret;
+ int voltage;
+
+ ret = zm_read(reg);
+ if (ret != -1) {
+ voltage = hex_to_1_10mv[ret];
+ debug("Voltage read is %dmV\n", voltage/10);
+ return voltage;
+ } else {
+ return -1;
+ }
+}
+
+int zm_disable_wp()
+{
+ u8 new_wp_value;
+
+ /* Disable using Write-Protect register 0x96 */
+ new_wp_value = 0x8;
+ if ((dpm_wrm(DPM_WP, new_wp_value)) < 0) {
+ printf("Disable Write-Protect register failed\n");
+ return -1;
+ }
+ return 0;
+}
+
+int zm_enable_wp()
+{
+ u8 orig_wp_value;
+ orig_wp_value = 0x0;
+
+ /* Enable using Write-Protect register 0x96 */
+ if ((dpm_wrm(DPM_WP, orig_wp_value)) < 0) {
+ printf("Enable Write-Protect register failed\n");
+ return -1;
+ }
+ return 0;
+}
+
--- /dev/null
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ZM7300_H_
+#define __ZM7300_H 1_
+
+#include <common.h>
+#include <i2c.h>
+#include <errno.h>
+#include <asm/io.h>
+
+#define ZM_STEP 125
+int zm7300_set_voltage(int voltage_1_10mv);
+int zm_write_voltage(int voltage);
+int zm_read_voltage(void);
+int zm_disable_wp(void);
+int zm_enable_wp(void);
+
+#endif /* __ZM7300_H_ */
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
+ * (.vectors)
arch/arm/cpu/arm1136/start.o (.text*)
board/freescale/mx31ads/built-in.o (.text*)
arch/arm/lib/built-in.o (.text*)
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
-#include <linux/fb.h>
-#include <ipu_pixfmt.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
}
#if defined(CONFIG_VIDEO_IPUV3)
-struct display_info_t {
- int bus;
- int addr;
- int pixfmt;
- int (*detect)(struct display_info_t const *dev);
- void (*enable)(struct display_info_t const *dev);
- struct fb_videomode mode;
-};
-
-static int detect_hdmi(struct display_info_t const *dev)
-{
- struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
- return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
-}
-
-
static void disable_lvds(struct display_info_t const *dev)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
writel(reg, &iomux->gpr[2]);
}
-static struct display_info_t const displays[] = {{
+struct display_info_t const displays[] = {{
.bus = -1,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB666,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} } };
-
-int board_video_skip(void)
-{
- int i;
- int ret;
- char const *panel = getenv("panel");
- if (!panel) {
- for (i = 0; i < ARRAY_SIZE(displays); i++) {
- struct display_info_t const *dev = displays+i;
- if (dev->detect && dev->detect(dev)) {
- panel = dev->mode.name;
- printf("auto-detected panel %s\n", panel);
- break;
- }
- }
- if (!panel) {
- panel = displays[0].mode.name;
- printf("No panel detected: default to %s\n", panel);
- i = 0;
- }
- } else {
- for (i = 0; i < ARRAY_SIZE(displays); i++) {
- if (!strcmp(panel, displays[i].mode.name))
- break;
- }
- }
- if (i < ARRAY_SIZE(displays)) {
- ret = ipuv3_fb_init(&displays[i].mode, 0,
- displays[i].pixfmt);
- if (!ret) {
- displays[i].enable(displays+i);
- printf("Display: %s (%ux%u)\n",
- displays[i].mode.name,
- displays[i].mode.xres,
- displays[i].mode.yres);
- } else
- printf("LCD %s cannot be configured: %d\n",
- displays[i].mode.name, ret);
- } else {
- printf("unsupported panel %s\n", panel);
- return -EINVAL;
- }
-
- return 0;
-}
+size_t display_count = ARRAY_SIZE(displays);
static void setup_display(void)
{
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
#define ETH_PHY_RESET IMX_GPIO_NR(4, 21)
int dram_init(void)
MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
+#ifdef CONFIG_MXC_SPI
+static iomux_v3_cfg_t ecspi1_pads[] = {
+ MX6_PAD_ECSPI1_MISO__ECSPI_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_ECSPI1_SS0__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_spi(void)
+{
+ imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+}
+#endif
+
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
int board_early_init_f(void)
{
setup_iomux_uart();
+#ifdef CONFIG_MXC_SPI
+ setup_spi();
+#endif
return 0;
}
# SPDX-License-Identifier: GPL-2.0+
#
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+obj-y += spl_minimal.o tlb.o law.o
+
+else
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
obj-y += p1_p2_rdb.o
+obj-$(CONFIG_PCI) += pci.o
+endif
obj-y += ddr.o
obj-y += law.o
-obj-$(CONFIG_PCI) += pci.o
obj-y += tlb.o
+
+endif
phys_size_t fixed_sdram (void)
{
- char buf[32];
fsl_ddr_cfg_regs_t ddr_cfg_regs;
size_t ddr_size;
struct cpu_type *cpu;
ulong ddr_freq, ddr_freq_mhz;
cpu = gd->arch.cpu;
- /* P1020 and it's derivatives support max 32bit DDR width */
- if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
- ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
- } else {
- ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
- }
+
+ ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
#if defined(CONFIG_SYS_RAMBOOT)
return ddr_size;
#endif
ddr_freq = get_ddr_freq(0);
ddr_freq_mhz = ddr_freq / 1000000;
- printf("Configuring DDR for %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
+ printf("Configuring DDR for %ld T/s data rate\n", ddr_freq);
if(ddr_freq_mhz <= 400)
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
else if(ddr_freq_mhz <= 800)
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
else
- panic("Unsupported DDR data rate %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
+ panic("Unsupported DDR data rate %ld T/s\n", ddr_freq);
/* P1020 and it's derivatives support max 32bit DDR width */
if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
--- /dev/null
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SYSCLK_MASK 0x00200000
+#define BOARDREV_MASK 0x10100000
+
+#define SYSCLK_66 66666666
+#define SYSCLK_100 100000000
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ u32 val_gpdat, sysclk_gpio;
+
+ val_gpdat = in_be32(&pgpio->gpdat);
+ sysclk_gpio = val_gpdat & SYSCLK_MASK;
+
+ if (sysclk_gpio == 0)
+ return SYSCLK_66;
+ else
+ return SYSCLK_100;
+
+ return 0;
+}
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, bus_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ console_init_f();
+
+ /* Set pmuxcr to allow both i2c1 and i2c2 */
+ setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
+ setbits_be32(&gur->pmuxcr,
+ in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+
+ /* Read back the register to synchronize the write. */
+ in_be32(&gur->pmuxcr);
+
+#ifdef CONFIG_SPL_SPI_BOOT
+ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+ gd->bus_clk = bus_clk;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ bus_clk / 16 / CONFIG_BAUDRATE);
+#ifdef CONFIG_SPL_MMC_BOOT
+ puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ puts("\nSPI Flash boot...\n");
+#endif
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+ bd_t *bd;
+
+ memset(gd, 0, sizeof(gd_t));
+ bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_initialize(bd);
+#endif
+ /* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_SPI_BOOT
+ spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ gd->ram_size = initdram(0);
+#ifdef CONFIG_SPL_NAND_BOOT
+ puts("Tertiary program loader running in sram...");
+#else
+ puts("Second program loader running in sram...\n");
+#endif
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
+#endif
+}
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <linux/compiler.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+#define SYSCLK_MASK 0x00200000
+#define BOARDREV_MASK 0x10100000
+
+#define SYSCLK_66 66666666
+#define SYSCLK_100 100000000
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ u32 val_gpdat, sysclk_gpio;
+
+ val_gpdat = in_be32(&pgpio->gpdat);
+ sysclk_gpio = val_gpdat & SYSCLK_MASK;
+
+ if (sysclk_gpio == 0)
+ return SYSCLK_66;
+ else
+ return SYSCLK_100;
+
+ return 0;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+ set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot... ");
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ puts("\nSecond program loader running in sram...");
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
+#ifndef CONFIG_SPL_BUILD
/* W**G* - Flash/promjet, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
0, 4, BOOKE_PAGESZ_256K, 1),
#endif /* #if defined(CONFIG_PCI) */
+#endif
/* *I*G - NAND */
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_1M, 1),
-#if defined(CONFIG_SYS_RAMBOOT)
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+ /* *I*G - L2SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 11, BOOKE_PAGESZ_256K, 1),
+#if CONFIG_SYS_L2_SIZE >= (256 << 10)
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+ CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_256K, 1),
+#endif
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_1G, 1)
get_sys_info(&sys_info);
return sys_info.freq_systembus;
}
+
+/*
+ * Return the number of cores on this SOC.
+ */
+int cpu_numcores(void)
+{
+ /*
+ * The QEMU u-boot target only needs to drive the first core,
+ * spinning and device tree nodes get driven by QEMU itself
+ */
+ return 1;
+}
+
+/*
+ * Return a 32-bit mask indicating which cores are present on this SOC.
+ */
+u32 cpu_mask(void)
+{
+ return (1 << cpu_numcores()) - 1;
+}
#ifdef CONFIG_DEEP_SLEEP
void board_mem_sleep_setup(void)
{
+ /* does not provide HW signals for power management */
+ CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40));
/* Disable MCKE isolation */
gpio_set_value(2, 0);
udelay(1);
--- /dev/null
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_T4240RDB) += t4240rdb.o
+obj-y += ddr.o
+obj-y += eth.o
+obj-$(CONFIG_PCI) += pci.o
+obj-y += law.o
+obj-y += tlb.o
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 2) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ /*
+ * we use identical timing for all slots. If needed, change the code
+ * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+ */
+ if (popts->registered_dimm_en)
+ pbsp = rdimms[0];
+ else
+ pbsp = udimms[0];
+
+
+ /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks &&
+ (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found for data\n"
+ "rate %lu MT/s\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+ "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x,\n"
+ "wrlvl_ctrl_3 0x%x\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+ pbsp->wrlvl_ctl_3);
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+ puts("Initializing....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ puts(" DDR: ");
+ return dram_size;
+}
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a},
+ {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09},
+ {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b},
+ {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a},
+ {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c},
+ {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c},
+ {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a},
+ {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a},
+ {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a},
+ {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b},
+ {}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {4, 1350, 0, 5, 9, 0x08070605, 0x06070806},
+ {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906},
+ {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
+ {2, 1350, 0, 5, 9, 0x08070605, 0x06070806},
+ {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
+ {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
+ {1, 1350, 0, 5, 9, 0x08070605, 0x06070806},
+ {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
+ {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07},
+ {}
+};
+
+/*
+ * The three slots have slightly different timing. The center values are good
+ * for all slots. We use identical speed tables for them. In future use, if
+ * DIMMs require separated tables, make more entries as needed.
+ */
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+/*
+ * The three slots have slightly different timing. See comments above.
+ */
+static const struct board_specific_parameters *rdimms[] = {
+ rdimm0,
+};
+
+
+#endif
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * Chunhe Lan <Chunhe.Lan@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+#include <hwconfig.h>
+
+#include "../common/fman.h"
+#include "t4rdb.h"
+
+void fdt_fixup_board_enet(void *fdt)
+{
+ return;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FMAN_ENET)
+ int i, interface;
+ struct memac_mdio_info dtsec_mdio_info;
+ struct memac_mdio_info tgec_mdio_info;
+ struct mii_dev *dev;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_prtcl_s1, srds_prtcl_s2;
+
+ srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+ srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+ srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+
+ dtsec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
+
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the 1G MDIO bus */
+ fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+ tgec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
+ tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the 10G MDIO bus */
+ fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+ if (srds_prtcl_s1 == 28) {
+ /* SGMII */
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
+ fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3);
+ fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4);
+ } else {
+ puts("Invalid SerDes1 protocol for T4240RDB\n");
+ }
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ interface = fm_info_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+ for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+ if (srds_prtcl_s2 == 56) {
+ /* SGMII && XFI */
+ fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
+ fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
+ fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7);
+ fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8);
+ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
+ fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR);
+ fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR);
+ } else {
+ puts("Invalid SerDes2 protocol for T4240RDB\n");
+ }
+
+ for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
+ interface = fm_info_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+ for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+#endif /* CONFIG_SYS_NUM_FMAN */
+
+ cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+ return pci_eth_init(bis);
+}
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ /* Limit DCSR to 32M to access NPC Trace Buffer */
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "t4rdb.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ struct cpu_type *cpu = gd->arch.cpu;
+
+ printf("Board: %sRDB, ", cpu->name);
+
+ puts("SERDES Reference Clocks:\n");
+ printf(" SERDES1=100MHz SERDES2=156.25MHz\n"
+ " SERDES3=100MHz SERDES4=100MHz\n");
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+ fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+}
+
+/*
+ * This function is called by bdinfo to print detail board information.
+ * As an exmaple for future board, we organize the messages into
+ * several sections. If applicable, the message is in the format of
+ * <name> = <value>
+ * It should aligned with normal output of bdinfo command.
+ *
+ * Voltage: Core, DDR and another configurable voltages
+ * Clock : Critical clocks which are not printed already
+ * RCW : RCW source if not printed already
+ * Misc : Other important information not in above catagories
+ */
+void board_detail(void)
+{
+ int rcwsrc;
+
+ /* RCW section SW3[4] */
+ rcwsrc = 0x0;
+ puts("RCW source = ");
+ switch (rcwsrc & 0x1) {
+ case 0x1:
+ puts("SDHC/eMMC\n");
+ break;
+ default:
+ puts("I2C normal addressing\n");
+ break;
+ }
+}
--- /dev/null
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fff80009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff80000
+09000d08 81000012
+#slow mdio clock
+095fc030 00008148
+095fd030 00808148
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
--- /dev/null
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#serdes protocol 28_56_2_10
+16070019 18101916 00000000 00000000
+70701050 00448c00 6c020000 f5000000
+00000000 ee0000ee 00000000 000287fc
+00000000 50000000 00000000 00000028
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __T4RDB_H__
+#define __T4RDB_H__
+
+#undef CONFIG_SYS_NUM_FM1_DTSEC
+#undef CONFIG_SYS_NUM_FM2_DTSEC
+#define CONFIG_SYS_NUM_FM1_DTSEC 4
+#define CONFIG_SYS_NUM_FM2_DTSEC 4
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 512K SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_512K, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
+ CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
+ CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 9, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 11, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 13, BOOKE_PAGESZ_32M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ /*
+ * *I*G - NAND
+ * entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so we use entry 16 for nand.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 16, BOOKE_PAGESZ_64K, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
+#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/sata.h>
+#include <asm/imx-common/video.h>
#include <jffs2/load_kernel.h>
#include <hwconfig.h>
#include <i2c.h>
#include <mtd_node.h>
#include <netdev.h>
#include <power/pmic.h>
+#include <power/ltc3676_pmic.h>
#include <power/pfuze100_pmic.h>
-#include <i2c.h>
#include <fdt_support.h>
#include <jffs2/load_kernel.h>
#include <spi_flash.h>
return 0;
}
+#if defined(CONFIG_VIDEO_IPUV3)
+
+static void enable_hdmi(struct display_info_t const *dev)
+{
+ imx_enable_hdmi_phy();
+}
+
+static int detect_i2c(struct display_info_t const *dev)
+{
+ return i2c_set_bus_num(dev->bus) == 0 &&
+ i2c_probe(dev->addr) == 0;
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+ struct iomuxc *iomux = (struct iomuxc *)
+ IOMUXC_BASE_ADDR;
+
+ /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
+ u32 reg = readl(&iomux->gpr[2]);
+ reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
+ writel(reg, &iomux->gpr[2]);
+
+ /* Enable Backlight */
+ imx_iomux_v3_setup_pad(MX6_PAD_SD1_CMD__GPIO1_IO18 |
+ MUX_PAD_CTRL(NO_PAD_CTRL));
+ gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
+}
+
+struct display_info_t const displays[] = {{
+ /* HDMI Output */
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
+ .bus = 2,
+ .addr = 0x4,
+ .pixfmt = IPU_PIX_FMT_LVDS666,
+ .detect = detect_i2c,
+ .enable = enable_lvds,
+ .mode = {
+ .name = "Hannstar-XGA",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int reg;
+
+ enable_ipu_clock();
+ imx_setup_hdmi();
+ /* Turn on LDB0,IPU,IPU DI0 clocks */
+ reg = __raw_readl(&mxc_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
+ writel(reg, &mxc_ccm->CCGR3);
+
+ /* set LDB0, LDB1 clk select to 011/011 */
+ reg = readl(&mxc_ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+ |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+ reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+ |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->cs2cdr);
+
+ reg = readl(&mxc_ccm->cscmr2);
+ reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+ writel(reg, &mxc_ccm->cscmr2);
+
+ reg = readl(&mxc_ccm->chsccdr);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->chsccdr);
+
+ reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+ |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
+ |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+ |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+ |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+ |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+ |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+ |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
+ |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+ writel(reg, &iomux->gpr[2]);
+
+ reg = readl(&iomux->gpr[3]);
+ reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
+ | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+ <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+ writel(reg, &iomux->gpr[3]);
+
+ /* Backlight CABEN on LVDS connector */
+ imx_iomux_v3_setup_pad(MX6_PAD_SD2_CLK__GPIO1_IO10 |
+ MUX_PAD_CTRL(NO_PAD_CTRL));
+ gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
/* read ventana EEPROM, check for validity, and return baseboard type */
static int
read_eeprom(void)
},
};
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+ struct pmic *p;
+ u32 reg;
+
+ /* configure PFUZE100 PMIC */
+ if (board_type == GW54xx || board_type == GW54proto) {
+ power_pfuze100_init(I2C_PMIC);
+ p = pmic_get("PFUZE100_PMIC");
+ if (p && !pmic_probe(p)) {
+ pmic_reg_read(p, PFUZE100_DEVICEID, ®);
+ printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
+
+ /* Set VGEN1 to 1.5V and enable */
+ pmic_reg_read(p, PFUZE100_VGEN1VOL, ®);
+ reg &= ~(LDO_VOL_MASK);
+ reg |= (LDOA_1_50V | LDO_EN);
+ pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
+
+ /* Set SWBST to 5.0V and enable */
+ pmic_reg_read(p, PFUZE100_SWBSTCON1, ®);
+ reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
+ reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
+ pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
+ }
+ }
+
+ /* configure LTC3676 PMIC */
+ else {
+ power_ltc3676_init(I2C_PMIC);
+ p = pmic_get("LTC3676_PMIC");
+ if (p && !pmic_probe(p)) {
+ puts("PMIC: LTC3676\n");
+ /* set board-specific scalar to 1225mV for IMX6Q@1GHz */
+ if (is_cpu_type(MXC_CPU_MX6Q)) {
+ /* mask PGOOD during SW1 transition */
+ reg = 0x1d | LTC3676_PGOOD_MASK;
+ pmic_reg_write(p, LTC3676_DVB1B, reg);
+ /* set SW1 (VDD_SOC) to 1259mV */
+ reg = 0x1d;
+ pmic_reg_write(p, LTC3676_DVB1A, reg);
+
+ /* mask PGOOD during SW3 transition */
+ reg = 0x1d | LTC3676_PGOOD_MASK;
+ pmic_reg_write(p, LTC3676_DVB3B, reg);
+ /*set SW3 (VDD_ARM) to 1259mV */
+ reg = 0x1d;
+ pmic_reg_write(p, LTC3676_DVB3A, reg);
+ }
+ }
+ }
+
+ return 0;
+}
+
/* setup GPIO pinmux and default configuration per baseboard */
static void setup_board_gpio(int board)
{
setup_iomux_uart();
gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
+#if defined(CONFIG_VIDEO_IPUV3)
+ setup_display();
+#endif
return 0;
}
setenv("serial#", str);
}
- /* configure PFUZE100 PMIC (not used on all Ventana baseboards) */
- if ((board_type == GW54xx || board_type == GW54proto) &&
- !pmic_init(I2C_PMIC)) {
- struct pmic *p = pmic_get("PFUZE100_PMIC");
- u32 reg;
- if (p && !pmic_probe(p)) {
- pmic_reg_read(p, PFUZE100_DEVICEID, ®);
- printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
-
- /* Set VGEN1 to 1.5V and enable */
- pmic_reg_read(p, PFUZE100_VGEN1VOL, ®);
- reg &= ~(LDO_VOL_MASK);
- reg |= (LDOA_1_50V | LDO_EN);
- pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
-
- /* Set SWBST to 5.0V and enable */
- pmic_reg_read(p, PFUZE100_SWBSTCON1, ®);
- reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
- reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
- pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
- }
- }
/* setup baseboard specific GPIO pinmux and config */
setup_board_gpio(board_type);
/* board serial number */
fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
- strlen(getenv("serial#") + 1));
+ strlen(getenv("serial#")) + 1);
/* board (model contains model from device-tree) */
fdt_setprop(blob, 0, "board", info->model,
u8 mfgdate[4]; /* 0x20: MFG date (read only) */
u8 res2[7]; /* 0x24 */
/* sdram config */
- u8 sdram_size; /* 0x2B: enum (512,1024,2048) MB */
- u8 sdram_speed; /* 0x2C: enum (100,133,166,200,267,333,400) MHz */
- u8 sdram_width; /* 0x2D: enum (32,64) bit */
+ u8 sdram_size; /* 0x2B: (16 << n) MB */
+ u8 sdram_speed; /* 0x2C: (33.333 * n) MHz */
+ u8 sdram_width; /* 0x2D: (8 << n) bit */
/* cpu config */
- u8 cpu_speed; /* 0x2E: enum (800,1000,1200) MHz */
- u8 cpu_type; /* 0x2F: enum (imx6q,imx6d,imx6dl,imx6s) */
+ u8 cpu_speed; /* 0x2E: (33.333 * n) MHz */
+ u8 cpu_type; /* 0x2F: 7=imx6q, 8=imx6dl */
u8 model[16]; /* 0x30: model string */
/* FLASH config */
- u8 nand_flash_size; /* 0x40: enum (4,8,16,32,64,128) MB */
- u8 spi_flash_size; /* 0x41: enum (4,8,16,32,64,128) MB */
+ u8 nand_flash_size; /* 0x40: (8 << (n-1)) MB */
+ u8 spi_flash_size; /* 0x41: (4 << (n-1)) MB */
/* Config1: SoC Peripherals */
u8 config[8]; /* 0x42: loading options */
--- /dev/null
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += mux.o
+endif
+
+obj-y += board.o
--- /dev/null
+/*
+ * Board functions for Gumstix Pepper and AM335x-based boards
+ *
+ * Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
+ * Based on board/ti/am335x/board.c from Texas Instruments, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <power/tps65217.h>
+#include <environment.h>
+#include <watchdog.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+static const struct ddr_data ddr2_data = {
+ .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
+ (MT47H128M16RT25E_RD_DQS<<20) |
+ (MT47H128M16RT25E_RD_DQS<<10) |
+ (MT47H128M16RT25E_RD_DQS<<0)),
+ .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
+ (MT47H128M16RT25E_WR_DQS<<20) |
+ (MT47H128M16RT25E_WR_DQS<<10) |
+ (MT47H128M16RT25E_WR_DQS<<0)),
+ .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
+ (MT47H128M16RT25E_PHY_WRLVL<<20) |
+ (MT47H128M16RT25E_PHY_WRLVL<<10) |
+ (MT47H128M16RT25E_PHY_WRLVL<<0)),
+ .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
+ (MT47H128M16RT25E_PHY_GATELVL<<20) |
+ (MT47H128M16RT25E_PHY_GATELVL<<10) |
+ (MT47H128M16RT25E_PHY_GATELVL<<0)),
+ .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
+ (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
+ (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
+ (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
+ .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
+ (MT47H128M16RT25E_PHY_WR_DATA<<20) |
+ (MT47H128M16RT25E_PHY_WR_DATA<<10) |
+ (MT47H128M16RT25E_PHY_WR_DATA<<0)),
+};
+
+static const struct cmd_control ddr2_cmd_ctrl_data = {
+ .cmd0csratio = MT47H128M16RT25E_RATIO,
+ .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
+
+ .cmd1csratio = MT47H128M16RT25E_RATIO,
+ .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
+
+ .cmd2csratio = MT47H128M16RT25E_RATIO,
+ .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
+};
+
+static const struct emif_regs ddr2_emif_reg_data = {
+ .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
+ .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
+ .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
+ .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
+ .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
+ .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+
+#define OSC (V_OSCK/1000000)
+const struct dpll_params dpll_ddr = {266, OSC-1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ return &dpll_ddr;
+}
+
+void set_uart_mux_conf(void)
+{
+ enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+ enable_board_pin_mux();
+}
+
+const struct ctrl_ioregs ioregs = {
+ .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+};
+
+void sdram_init(void)
+{
+ config_ddr(266, &ioregs, &ddr2_data,
+ &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
+}
+#endif
+
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+ hw_watchdog_init();
+#endif
+
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gpmc_init();
+
+ return 0;
+}
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 0,
+ .phy_if = PHY_INTERFACE_MODE_RGMII,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+ int rv, n = 0;
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+ const char *devname;
+
+ if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+ /* try reading mac address from efuse */
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+
+ writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ n += rv;
+
+ /*
+ *
+ * CPSW RGMII Internal Delay Mode is not supported in all PVT
+ * operating points. So we must set the TX clock delay feature
+ * in the KSZ9021 PHY. Since we only support a single ethernet
+ * device in U-Boot, we only do this for the current instance.
+ */
+ devname = miiphy_get_current_dev();
+ /* max rx/tx clock delay, min rx/tx control delay */
+ miiphy_write(devname, 0x0, 0x0b, 0x8104);
+ miiphy_write(devname, 0x0, 0xc, 0xa0a0);
+
+ /* min rx data delay */
+ miiphy_write(devname, 0x0, 0x0b, 0x8105);
+ miiphy_write(devname, 0x0, 0x0c, 0x0000);
+
+ /* min tx data delay */
+ miiphy_write(devname, 0x0, 0x0b, 0x8106);
+ miiphy_write(devname, 0x0, 0x0c, 0x0000);
+
+ return n;
+}
+#endif
--- /dev/null
+/*
+ * Gumstix Pepper and AM335x-based boards information header
+ *
+ * Copyright (C) 2014, Gumstix, Inc. - http://www.gumstix.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * We must be able to enable uart0, for initial output. We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
--- /dev/null
+/*
+ * Muxing for Gumstix Pepper and AM335x-based boards
+ *
+ * Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
+ {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
+ {-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ /* I2C_DATA */
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ /* I2C_SCLK */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ {-1},
+};
+
+static struct module_pin_mux rgmii1_pin_mux[] = {
+ {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
+ {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
+ {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
+ {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
+ {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
+ {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
+ {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
+ {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
+ {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
+ {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
+ {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
+ {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {OFFSET(rmii1_refclk), MODE(7) | RXACTIVE}, /* ETH_INT */
+ {OFFSET(mii1_col), MODE(7) | PULLUP_EN}, /* PHY_NRESET */
+ {OFFSET(xdma_event_intr1), MODE(3)},
+ {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+/*
+ * Do board-specific muxes.
+ */
+void enable_board_pin_mux(void)
+{
+ /* I2C0 */
+ configure_module_pin_mux(i2c0_pin_mux);
+ /* SD Card */
+ configure_module_pin_mux(mmc0_pin_mux);
+ /* Ethernet pinmux. */
+ configure_module_pin_mux(rgmii1_pin_mux);
+}
#define ZL30158_RST 8
-#define ZL30343_RST 9
+#define BFTIC4_RST 0
int board_early_init_f(void)
{
/* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
setbits_be32(&gur->ddrclkdr, 0x001f000f);
- /* take the Zarlinks out of reset as soon as possible */
- qrio_prst(ZL30158_RST, false, false);
- qrio_prst(ZL30343_RST, false, false);
+ /* set the BFTIC's prstcfg to reset at power-up and unit reset only */
+ qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
+ /* and enable WD on it */
+ qrio_wdmask(BFTIC4_RST, true);
- /* and set their reset to power-up only */
- qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
- qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
+ /* set the ZL30138's prstcfg to reset at power-up and unit reset only */
+ qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_UNIT_RST);
+ /* and take it out of reset as soon as possible (needed for Hooper) */
+ qrio_prst(ZL30158_RST, false, false);
return 0;
}
if (ret)
printf("error triggering PCIe FPGA config\n");
+ /* enable the Unit LED (red) & Boot LED (on) */
+ qrio_set_leds();
+
+ /* enable Application Buffer */
+ qrio_enable_app_buffer();
+
return ret;
}
return 66666666;
}
+#define ETH_FRONT_PHY_RST 15
+#define QSFP2_RST 11
+#define QSFP1_RST 10
+#define ZL30343_RST 9
+
int misc_init_f(void)
{
/* configure QRIO pis for i2c deblocking */
i2c_deblock_gpio_cfg();
+ /* configure the front phy's prstcfg and take it out of reset */
+ qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+ qrio_prst(ETH_FRONT_PHY_RST, false, false);
+
+ /* set the ZL30343 prstcfg to reset at power-up and unit reset only */
+ qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_UNIT_RST);
+ /* and enable the WD on it */
+ qrio_wdmask(ZL30343_RST, true);
+
+ /* set the QSFPs' prstcfg to reset at power-up and unit rst only */
+ qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST);
+
+ /* and enable the WD on them */
+ qrio_wdmask(QSFP1_RST, true);
+ qrio_wdmask(QSFP2_RST, true);
+
return 0;
}
#define NUM_SRDS_BANKS 2
-#define PHY_RST 15
int misc_init_r(void)
{
}
}
- /* take the mgmt eth phy out of reset */
- qrio_prst(PHY_RST, false, false);
-
return 0;
}
#endif
#if defined(CONFIG_LAST_STAGE_INIT)
+
int last_stage_init(void)
{
+#if defined(CONFIG_KMCOGE4)
+ /* on KMCOGE4, the BFTIC4 is on the LBAPP2 */
+ struct bfticu_iomap *bftic4 =
+ (struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE;
+ u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK;
+
+ if (dip_switch != 0) {
+ /* start bootloader */
+ puts("DIP: Enabled\n");
+ setenv("actual_bank", "0");
+ }
+#endif
set_km_env();
+
return 0;
}
#endif
fdt_fixup_fman_mac_addresses(blob);
#endif
}
+
+#if defined(CONFIG_POST)
+
+/* DIC26_SELFTEST GPIO used to start factory test sw */
+#define SELFTEST_PORT GPIO_A
+#define SELFTEST_PIN 31
+
+int post_hotkeys_pressed(void)
+{
+ qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
+ return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
+}
+#endif
#define PRSTCFG_POWUP_RST 0x3
void qrio_prst(u8 bit, bool en, bool wden);
+void qrio_wdmask(u8 bit, bool wden);
void qrio_prstcfg(u8 bit, u8 mode);
+void qrio_set_leds(void);
+void qrio_enable_app_buffer(void);
void pci_of_setup(void *blob, bd_t *bd);
#
#PBI commands
-#Workaround for A-006559 needed for rev 2.0 of P2041 silicon
-#Freescale's errarta sheet suggests it may be done with PBI
+#Configure ALTCBAR for DCSR -> DCSR@89000000
+091380c0 000009C4
09000010 00000000
+091380c0 000009C4
09000014 00000000
+091380c0 000009C4
09000018 81d00000
-09021008 0000f000
-09021028 0000f000
-09021048 0000f000
-09021068 0000f000
+#Workaround for A-004849
+091380c0 000009C4
+890B0050 00000002
+091380c0 000009C4
+890B0054 00000002
+091380c0 000009C4
+890B0058 00000002
+091380c0 000009C4
+890B005C 00000002
+091380c0 000009C4
+890B0090 00000002
+091380c0 000009C4
+890B0094 00000002
+091380c0 000009C4
+890B0098 00000002
+091380c0 000009C4
+890B009C 00000002
+091380c0 000009C4
+890B0108 00000012
+091380c0 000009C4
+#Workaround for A-006559 needed for rev 2.0 of P2041 silicon
+89021008 0000f000
+091380c0 000009C4
+89021028 0000f000
+091380c0 000009C4
+89021048 0000f000
+091380c0 000009C4
+89021068 0000f000
+091380c0 000009C4
+#Flush PBL data
+09138000 00000000
+#Disable ALTCBAR
09000018 00000000
+091380c0 000009C4
#Initialize CPC1 as 1MB SRAM
09010000 00200400
09138000 00000000
}
#define PCIE_SW_RST 14
-#define PEXHC_SW_RST 13
-#define HOOPER_SW_RST 12
+#define PEXHC_RST 13
+#define HOOPER_RST 12
void pci_init_board(void)
{
- /* first wait for the PCIe FPGA to be configured
+ qrio_prstcfg(PCIE_SW_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+ qrio_prstcfg(PEXHC_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+ qrio_prstcfg(HOOPER_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+
+ /* wait for the PCIe FPGA to be configured
* it has been triggered earlier in board_early_init_r */
- int ret = wait_for_fpga_config();
- if (ret)
+ if (wait_for_fpga_config())
printf("error finishing PCIe FPGA config\n");
qrio_prst(PCIE_SW_RST, false, false);
- qrio_prst(PEXHC_SW_RST, false, false);
- qrio_prst(HOOPER_SW_RST, false, false);
+ qrio_prst(PEXHC_RST, false, false);
+ qrio_prst(HOOPER_RST, false, false);
/* Hooper is not direcly PCIe capable */
mdelay(50);
#define WDMASK_OFF 0x16
-static void qrio_wdmask(u8 bit, bool wden)
+void qrio_wdmask(u8 bit, bool wden)
{
u16 wdmask;
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
out_be32(qrio_base + PRSTCFG_OFF, prstcfg);
}
+
+#define CTRLH_OFF 0x02
+#define CTRLH_WRL_BOOT 0x01
+#define CTRLH_WRL_UNITRUN 0x02
+
+void qrio_set_leds(void)
+{
+ u8 ctrlh;
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ /* set UNIT LED to RED and BOOT LED to ON */
+ ctrlh = in_8(qrio_base + CTRLH_OFF);
+ ctrlh |= (CTRLH_WRL_BOOT | CTRLH_WRL_UNITRUN);
+ out_8(qrio_base + CTRLH_OFF, ctrlh);
+}
+
+#define CTRLL_OFF 0x03
+#define CTRLL_WRB_BUFENA 0x20
+
+void qrio_enable_app_buffer(void)
+{
+ u8 ctrll;
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ /* enable application buffer */
+ ctrll = in_8(qrio_base + CTRLL_OFF);
+ ctrll |= (CTRLL_WRB_BUFENA);
+ out_8(qrio_base + CTRLL_OFF, ctrll);
+}
#64 bytes RCW data
14600000 00000000 28200000 00000000
148E70CF CFC02000 58000000 41000000
-00000000 00000000 00000000 F0428002
+00000000 00000000 00000000 F0428816
00000000 00000000 00000000 00000000
return -1;
}
- result = fpga_load(0, fpga_data, data_size);
+ result = fpga_load(0, fpga_data, data_size, BIT_FULL);
if (!result)
bootstage_mark(BOOTSTAGE_ID_START);
*/
#include <common.h>
+#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
#include "pinmux-config-jetson-tk1.h"
*/
void pinmux_init(void)
{
+ pinmux_set_tristate_input_clamping();
+
+ gpio_config_table(jetson_tk1_gpio_inits,
+ ARRAY_SIZE(jetson_tk1_gpio_inits));
+
pinmux_config_pingrp_table(jetson_tk1_pingrps,
ARRAY_SIZE(jetson_tk1_pingrps));
#ifndef _PINMUX_CONFIG_JETSON_TK1_H_
#define _PINMUX_CONFIG_JETSON_TK1_H_
+#define GPIO_INIT(_gpio, _init) \
+ { \
+ .gpio = GPIO_P##_gpio, \
+ .init = TEGRA_GPIO_INIT_##_init, \
+ }
+
+static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = {
+ /* gpio, init_val */
+ GPIO_INIT(C7, IN),
+ GPIO_INIT(G0, OUT0),
+ GPIO_INIT(G1, OUT0),
+ GPIO_INIT(G2, IN),
+ GPIO_INIT(G3, IN),
+ GPIO_INIT(H2, OUT0),
+ GPIO_INIT(H3, OUT0),
+ GPIO_INIT(H4, IN),
+ GPIO_INIT(H5, OUT0),
+ GPIO_INIT(H6, IN),
+ GPIO_INIT(H7, OUT0),
+ GPIO_INIT(I0, OUT0),
+ GPIO_INIT(I2, OUT0),
+ GPIO_INIT(I4, OUT0),
+ GPIO_INIT(I5, IN),
+ GPIO_INIT(I6, IN),
+ GPIO_INIT(J0, IN),
+ GPIO_INIT(J2, IN),
+ GPIO_INIT(K1, OUT0),
+ GPIO_INIT(K2, IN),
+ GPIO_INIT(K3, IN),
+ GPIO_INIT(K4, OUT0),
+ GPIO_INIT(K5, OUT0),
+ GPIO_INIT(K6, OUT0),
+ GPIO_INIT(N7, IN),
+ GPIO_INIT(O0, IN),
+ GPIO_INIT(O1, IN),
+ GPIO_INIT(O2, IN),
+ GPIO_INIT(O3, IN),
+ GPIO_INIT(O4, IN),
+ GPIO_INIT(O5, IN),
+ GPIO_INIT(O6, OUT0),
+ GPIO_INIT(O7, IN),
+ GPIO_INIT(P0, OUT0),
+ GPIO_INIT(P1, OUT0),
+ GPIO_INIT(P2, OUT0),
+ GPIO_INIT(Q0, IN),
+ GPIO_INIT(Q1, IN),
+ GPIO_INIT(Q2, IN),
+ GPIO_INIT(Q5, IN),
+ GPIO_INIT(Q6, IN),
+ GPIO_INIT(Q7, IN),
+ GPIO_INIT(R0, OUT0),
+ GPIO_INIT(R1, OUT0),
+ GPIO_INIT(R2, OUT0),
+ GPIO_INIT(R4, IN),
+ GPIO_INIT(R5, OUT0),
+ GPIO_INIT(R7, IN),
+ GPIO_INIT(S0, IN),
+ GPIO_INIT(S3, OUT0),
+ GPIO_INIT(S4, OUT0),
+ GPIO_INIT(S5, IN),
+ GPIO_INIT(S6, OUT0),
+ GPIO_INIT(T0, OUT0),
+ GPIO_INIT(T1, OUT0),
+ GPIO_INIT(U0, OUT0),
+ GPIO_INIT(U1, IN),
+ GPIO_INIT(U2, IN),
+ GPIO_INIT(U3, OUT0),
+ GPIO_INIT(U4, OUT0),
+ GPIO_INIT(U5, IN),
+ GPIO_INIT(U6, IN),
+ GPIO_INIT(V0, IN),
+ GPIO_INIT(V1, IN),
+ GPIO_INIT(W2, IN),
+ GPIO_INIT(W3, IN),
+ GPIO_INIT(X1, OUT0),
+ GPIO_INIT(X3, IN),
+ GPIO_INIT(X4, OUT0),
+ GPIO_INIT(X5, IN),
+ GPIO_INIT(X6, IN),
+ GPIO_INIT(X7, OUT0),
+ GPIO_INIT(BB3, OUT0),
+ GPIO_INIT(BB5, OUT0),
+ GPIO_INIT(BB6, OUT0),
+ GPIO_INIT(BB7, OUT0),
+ GPIO_INIT(CC1, IN),
+ GPIO_INIT(CC2, IN),
+ GPIO_INIT(CC5, OUT0),
+ GPIO_INIT(EE1, OUT0),
+ GPIO_INIT(FF1, OUT0),
+ GPIO_INIT(FF2, IN),
+};
+
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
{ \
.pingrp = PMUX_PINGRP_##_pingrp, \
PINCFG(UART2_RXD_PC3, IRDA, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
- PINCFG(PC7, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PG0, RSVD1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PG1, RSVD1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PG2, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PG3, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PC7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PG1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PG2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG3, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PH2, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PH3, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PH4, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PH5, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PH6, GMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PH7, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PI0, RSVD1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PH5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PI2, RSVD4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PI4, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PI5, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PI6, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PI4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PI6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PJ0, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PJ2, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PJ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(UART2_CTS_N_PJ5, UARTB, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PJ7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PK0, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PK1, RSVD4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PK2, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PK3, GMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PK4, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(SPDIF_OUT_PK5, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(SPDIF_IN_PK6, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PK2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PK3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PK4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SPDIF_OUT_PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SPDIF_IN_PK6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PK7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP1_FS_PN0, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP1_DIN_PN1, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP1_SCLK_PN3, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(USB_VBUS_EN0_PN4, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(USB_VBUS_EN1_PN5, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT),
- PINCFG(HDMI_INT_PN7, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, NORMAL),
- PINCFG(ULPI_DATA7_PO0, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(ULPI_DATA0_PO1, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(ULPI_DATA1_PO2, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(ULPI_DATA2_PO3, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(ULPI_DATA3_PO4, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(ULPI_DATA4_PO5, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(ULPI_DATA5_PO6, ULPI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(ULPI_DATA6_PO7, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(DAP3_DOUT_PP2, RSVD4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL),
+ PINCFG(ULPI_DATA7_PO0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA0_PO1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA1_PO2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA2_PO3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA3_PO4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA4_PO5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA5_PO6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA6_PO7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_FS_PP0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_DIN_PP1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP4_FS_PP4, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP4_DIN_PP5, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP4_DOUT_PP6, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP4_SCLK_PP7, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_COL0_PQ0, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_COL1_PQ1, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_COL2_PQ2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL0_PQ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL1_PQ1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL2_PQ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL3_PQ3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_COL5_PQ5, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_COL6_PQ6, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_COL7_PQ7, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW0_PR0, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW1_PR1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW2_PR2, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL5_PQ5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL6_PQ6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL7_PQ7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW2_PR2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW3_PR3, SYS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW4_PR4, RSVD3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW5_PR5, RSVD3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW4_PR4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW5_PR5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW6_PR6, DISPLAYA_ALT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW7_PR7, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW8_PS0, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW7_PR7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW8_PS0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW9_PS1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW10_PS2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW11_PS3, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW12_PS4, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW13_PS5, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW14_PS6, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW13_PS5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW14_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW15_PS7, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW16_PT0, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW17_PT1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW16_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PU0, RSVD4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PU1, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PU2, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PU3, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PU4, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PU5, GMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PU6, RSVD3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PV0, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PV1, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PU1, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PU4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PV0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PV1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
- PINCFG(GPIO_W2_AUD_PW2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(GPIO_W3_AUD_PW3, SPI6, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_W2_AUD_PW2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_W3_AUD_PW3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(UART3_RXD_PW7, UARTC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(GPIO_X1_AUD_PX1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(GPIO_X3_AUD_PX3, RSVD4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(GPIO_X4_AUD_PX4, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(GPIO_X5_AUD_PX5, RSVD4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(GPIO_X6_AUD_PX6, GMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(GPIO_X7_AUD_PX7, RSVD1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X3_AUD_PX3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X5_AUD_PX5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X6_AUD_PX6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DIR_PY1, SPI1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PBB0, VIMCLK2_ALT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
- PINCFG(PBB3, VGP3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PBB5, RSVD3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PBB6, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PBB7, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PCC1, RSVD2, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PCC2, RSVD2, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PCC1, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PCC2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(CLK2_REQ_PCC5, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK2_REQ_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(CLK3_REQ_PEE1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK3_REQ_PEE1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP_MCLK1_REQ_PEE2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(USB_VBUS_EN2_PFF1, RSVD2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PFF2, RSVD2, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(USB_VBUS_EN2_PFF1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PFF2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CPU_PWR_REQ, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
/*
- * (C) Copyright 2013
- * NVIDIA Corporation <www.nvidia.com>
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _PINMUX_CONFIG_VENICE2_H_
#define _PINMUX_CONFIG_VENICE2_H_
-#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
- { \
- .pingrp = PMUX_PINGRP_##_pingrp, \
- .func = PMUX_FUNC_##_mux, \
- .pull = PMUX_PULL_##_pull, \
- .tristate = PMUX_TRI_##_tri, \
- .io = PMUX_PIN_##_io, \
- .lock = PMUX_PIN_LOCK_DEFAULT, \
- .od = PMUX_PIN_OD_DEFAULT, \
- .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+#define GPIO_INIT(_gpio, _init) \
+ { \
+ .gpio = GPIO_P##_gpio, \
+ .init = TEGRA_GPIO_INIT_##_init, \
}
-#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
- { \
- .pingrp = PMUX_PINGRP_##_pingrp, \
- .func = PMUX_FUNC_##_mux, \
- .pull = PMUX_PULL_##_pull, \
- .tristate = PMUX_TRI_##_tri, \
- .io = PMUX_PIN_##_io, \
- .lock = PMUX_PIN_LOCK_##_lock, \
- .od = PMUX_PIN_OD_##_od, \
- .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
- }
+static const struct tegra_gpio_config venice2_gpio_inits[] = {
+ /* gpio, init_val */
+ GPIO_INIT(A0, IN),
+ GPIO_INIT(C7, IN),
+ GPIO_INIT(G0, IN),
+ GPIO_INIT(G1, IN),
+ GPIO_INIT(G2, IN),
+ GPIO_INIT(G3, IN),
+ GPIO_INIT(H2, IN),
+ GPIO_INIT(H4, IN),
+ GPIO_INIT(H5, OUT0),
+ GPIO_INIT(H6, IN),
+ GPIO_INIT(H7, OUT1),
+ GPIO_INIT(I0, IN),
+ GPIO_INIT(I1, IN),
+ GPIO_INIT(I2, OUT0),
+ GPIO_INIT(I4, OUT0),
+ GPIO_INIT(I5, OUT1),
+ GPIO_INIT(I6, IN),
+ GPIO_INIT(J0, IN),
+ GPIO_INIT(J7, IN),
+ GPIO_INIT(K0, IN),
+ GPIO_INIT(K1, OUT0),
+ GPIO_INIT(K2, IN),
+ GPIO_INIT(K3, IN),
+ GPIO_INIT(K4, OUT0),
+ GPIO_INIT(K6, OUT0),
+ GPIO_INIT(K7, IN),
+ GPIO_INIT(N7, IN),
+ GPIO_INIT(O2, IN),
+ GPIO_INIT(O5, IN),
+ GPIO_INIT(O6, OUT0),
+ GPIO_INIT(O7, IN),
+ GPIO_INIT(P2, OUT0),
+ GPIO_INIT(Q0, IN),
+ GPIO_INIT(Q2, IN),
+ GPIO_INIT(Q3, IN),
+ GPIO_INIT(Q6, IN),
+ GPIO_INIT(Q7, IN),
+ GPIO_INIT(R0, OUT0),
+ GPIO_INIT(R1, IN),
+ GPIO_INIT(R4, IN),
+ GPIO_INIT(S0, IN),
+ GPIO_INIT(S3, OUT0),
+ GPIO_INIT(S4, OUT0),
+ GPIO_INIT(S7, IN),
+ GPIO_INIT(T1, IN),
+ GPIO_INIT(U4, IN),
+ GPIO_INIT(U5, IN),
+ GPIO_INIT(U6, IN),
+ GPIO_INIT(V0, IN),
+ GPIO_INIT(V1, IN),
+ GPIO_INIT(W3, IN),
+ GPIO_INIT(X1, IN),
+ GPIO_INIT(X3, IN),
+ GPIO_INIT(X4, IN),
+ GPIO_INIT(X7, OUT0),
+ GPIO_INIT(CC5, OUT0),
+};
-#define DDC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
+#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
{ \
.pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.io = PMUX_PIN_##_io, \
- .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_##_od, \
.rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
-#define VI_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
- { \
- .pingrp = PMUX_PINGRP_##_pingrp, \
- .func = PMUX_FUNC_##_mux, \
- .pull = PMUX_PULL_##_pull, \
- .tristate = PMUX_TRI_##_tri, \
- .io = PMUX_PIN_##_io, \
- .lock = PMUX_PIN_LOCK_##_lock, \
- .od = PMUX_PIN_OD_DEFAULT, \
- .ioreset = PMUX_PIN_IO_RESET_##_ioreset \
- }
-
-#define CEC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
- { \
- .pingrp = PMUX_PINGRP_##_pingrp, \
- .func = PMUX_FUNC_##_mux, \
- .pull = PMUX_PULL_##_pull, \
- .tristate = PMUX_TRI_##_tri, \
- .io = PMUX_PIN_##_io, \
- .lock = PMUX_PIN_LOCK_##_lock, \
- .od = PMUX_PIN_OD_##_od, \
- .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
- }
-
-#define USB_PINMUX CEC_PINMUX
+static const struct pmux_pingrp_config venice2_pingrps[] = {
+ /* pingrp, mux, pull, tri, e_input, od, rcv_sel */
+ PINCFG(CLK_32K_OUT_PA0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PB0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PB1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_RXD_PC3, IRDA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(PC7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PH0, PWM0, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PH3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PH5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PI1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PJ2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PJ7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PK0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PK2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PK3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PK4, DEFAULT, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SPDIF_OUT_PK5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SPDIF_IN_PK6, DEFAULT, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PK7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL),
+ PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA0_PO1, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA1_PO2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA3_PO4, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA4_PO5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA5_PO6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA6_PO7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_FS_PP0, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_DIN_PP1, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL0_PQ0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL1_PQ1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL2_PQ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL3_PQ3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL5_PQ5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL6_PQ6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL7_PQ7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW2_PR2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW4_PR4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW6_PR6, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW7_PR7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW8_PS0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW9_PS1, UARTA, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW10_PS2, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW15_PS7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW16_PT0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU0, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PU1, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU2, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU3, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PU4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PV0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PV1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
+ PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
+ PINCFG(GPIO_W2_AUD_PW2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_W3_AUD_PW3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK2_OUT_PW5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X3_AUD_PX3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X5_AUD_PX5, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X6_AUD_PX6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB0, VGP6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(PBB3, VGP3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB4, VGP4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CAM_MCLK_PCC0, VI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PCC1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PCC2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK2_REQ_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_L0_RST_N_PDD1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_L0_CLKREQ_N_PDD2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_WAKE_N_PDD3, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_L1_RST_N_PDD5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_L1_CLKREQ_N_PDD6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP_MCLK1_REQ_PEE2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PWR_INT_N, PMI, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL),
+ PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+};
-#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
{ \
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
.slwf = _slwf, \
.hsm = PMUX_HSM_##_hsm, \
}
-static struct pmux_pingrp_config tegra124_pinmux_common[] = {
- /* EXTPERIPH1 pinmux */
- DEFAULT_PINMUX(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
-
- /* I2S0 pinmux */
- DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
-
- /* I2S1 pinmux */
- DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
-
- /* I2S3 pinmux */
- DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
-
- /* CLDVFS pinmux */
- DEFAULT_PINMUX(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT),
-
- /* ULPI pinmux */
- DEFAULT_PINMUX(ULPI_DATA0_PO1, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA1_PO2, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA2_PO3, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA3_PO4, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA4_PO5, ULPI, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA5_PO6, ULPI, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA6_PO7, ULPI, NORMAL, NORMAL, INPUT),
-
- /* EC KBC/SPI */
- DEFAULT_PINMUX(ULPI_CLK_PY0, SPI1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DIR_PY1, SPI1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, INPUT),
-
- /* I2C3 (TPM) pinmux */
- I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
- I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
-
- /* I2C2 pinmux */
- I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
- I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
-
- /* UARTD pinmux (UART4 on Servo board, unused) */
- DEFAULT_PINMUX(PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PB0, UARTD, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PB1, UARTD, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PK7, UARTD, NORMAL, NORMAL, OUTPUT),
-
- /* SPI4 (Winbond 'boot ROM') */
- DEFAULT_PINMUX(PG5, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PG6, SPI4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(PG7, SPI4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(PI3, SPI4, NORMAL, NORMAL, INPUT),
-
- /* Touch IRQ */
- DEFAULT_PINMUX(GPIO_W3_AUD_PW3, RSVD1, NORMAL, NORMAL, INPUT),
-
- /* PWM1 pinmux */
- DEFAULT_PINMUX(PH1, PWM1, NORMAL, NORMAL, OUTPUT),
-
- /* SDMMC1 pinmux */
- DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
-
- /* SDMMC3 pinmux */
- DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, TRISTATE, INPUT),
- DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, DOWN, NORMAL, INPUT),
-
- /* SDMMC4 pinmux */
- DEFAULT_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT),
-
- /* BLINK pinmux */
- DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
-
- /* KBC pinmux */
- DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT),
-
- /* Misc */
- DEFAULT_PINMUX(PV0, RSVD1, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(KB_ROW7_PR7, RSVD1, UP, NORMAL, INPUT),
-
- /* UARTA pinmux (BR_UART_TXD/RXD on Servo board) */
- DEFAULT_PINMUX(KB_ROW9_PS1, UARTA, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_ROW10_PS2, UARTA, UP, TRISTATE, INPUT),
-
- /* I2CPWR pinmux (I2C5) */
- I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
- I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
-
- /* RTCK pinmux */
- DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT),
-
- /* CLK pinmux */
- DEFAULT_PINMUX(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT),
-
- /* PWRON pinmux */
- DEFAULT_PINMUX(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT),
-
- /* CPU pinmux */
- DEFAULT_PINMUX(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT),
-
- /* PMI pinmux */
- DEFAULT_PINMUX(PWR_INT_N, PMI, NORMAL, TRISTATE, INPUT),
-
- /* RESET_OUT_N pinmux */
- DEFAULT_PINMUX(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT),
-
- /* EXTPERIPH3 pinmux */
- DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
-
- /* I2C1 pinmux */
- I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
- I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
-
- /* UARTB, GPS */
- DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(UART2_RXD_PC3, IRDA, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT),
-
- /* UARTC (WIFI/BT) */
- DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
-
- /* CEC pinmux */
- CEC_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
-
- /* I2C4 (HDMI_DDC) pinmux */
- DDC_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
- DDC_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
-
- /* USB pinmux */
- USB_PINMUX(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
- USB_PINMUX(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
-
- /* Unused, marked SNN_ on schematic, TRISTATE 'em */
- DEFAULT_PINMUX(PBB0, RSVD3, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PBB3, RSVD3, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PBB4, RSVD3, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PBB5, RSVD2, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PBB6, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PBB7, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PCC2, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PH3, GMI, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PI7, GMI, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PJ2, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_X5_AUD_PX5, RSVD3, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_X6_AUD_PX6, GMI, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GPIO_W2_AUD_PW2, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PFF2, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(USB_VBUS_EN2_PFF1, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_COL5_PQ5, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW2_PR2, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW3_PR3, KBC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW5_PR5, RSVD2, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW13_PS5, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW14_PS6, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW16_PT0, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(OWR, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(ULPI_DATA7_PO0, ULPI, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(DAP3_DIN_PP1, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(DAP3_FS_PP0, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(DAP3_SCLK_PP3, RSVD2, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(CLK2_OUT_PW5, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(SDMMC1_WP_N_PV3, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(CAM_MCLK_PCC0, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(SPDIF_OUT_PK5, RSVD1, NORMAL, TRISTATE, INPUT),
-};
-
-static struct pmux_pingrp_config unused_pins_lowpower[] = {
- DEFAULT_PINMUX(DAP_MCLK1_REQ_PEE2, RSVD3, DOWN, TRISTATE, OUTPUT),
-};
-
-/* Initially setting all used GPIO's to non-TRISTATE */
-static struct pmux_pingrp_config tegra124_pinmux_set_nontristate[] = {
- DEFAULT_PINMUX(GPIO_X4_AUD_PX4, RSVD1, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_X7_AUD_PX7, RSVD1, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GPIO_W2_AUD_PW2, RSVD1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GPIO_X3_AUD_PX3, RSVD3, UP, NORMAL, INPUT),
-
- /* EN_VDD_BL */
- DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, DOWN, NORMAL, OUTPUT),
-
- /* MODEM */
- DEFAULT_PINMUX(PV0, RSVD3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT),
-
- /* BOOT_SEL0-3 */
- DEFAULT_PINMUX(PG0, GMI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PG1, GMI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PG2, GMI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PG3, GMI, NORMAL, NORMAL, INPUT),
-
- DEFAULT_PINMUX(CLK2_REQ_PCC5, RSVD3, NORMAL, NORMAL, OUTPUT),
-
- DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_ROW4_PR4, KBC, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
-
- DEFAULT_PINMUX(PU4, RSVD3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PU5, RSVD3, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PU6, RSVD3, NORMAL, NORMAL, INPUT),
-
- DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(SPDIF_IN_PK6, RSVD2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT),
-
- /* TS_SHDN_L */
- DEFAULT_PINMUX(PK1, GMI, NORMAL, NORMAL, OUTPUT),
+static const struct pmux_drvgrp_config venice2_drvgrps[] = {
};
-static struct pmux_drvgrp_config venice2_padctrl[] = {
- /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
- DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR,
- SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE),
-};
#endif /* PINMUX_CONFIG_VENICE2_H */
*/
#include <common.h>
-#include <asm-generic/gpio.h>
#include <asm/arch/gpio.h>
-#include <asm/arch/gp_padctrl.h>
#include <asm/arch/pinmux.h>
#include "pinmux-config-venice2.h"
-#include <i2c.h>
/*
* Routine: pinmux_init
*/
void pinmux_init(void)
{
- pinmux_config_pingrp_table(tegra124_pinmux_set_nontristate,
- ARRAY_SIZE(tegra124_pinmux_set_nontristate));
+ pinmux_set_tristate_input_clamping();
- pinmux_config_pingrp_table(tegra124_pinmux_common,
- ARRAY_SIZE(tegra124_pinmux_common));
+ gpio_config_table(venice2_gpio_inits,
+ ARRAY_SIZE(venice2_gpio_inits));
- pinmux_config_pingrp_table(unused_pins_lowpower,
- ARRAY_SIZE(unused_pins_lowpower));
+ pinmux_config_pingrp_table(venice2_pingrps,
+ ARRAY_SIZE(venice2_pingrps));
- /* Initialize any non-default pad configs (APB_MISC_GP regs) */
- pinmux_config_drvgrp_table(venice2_padctrl,
- ARRAY_SIZE(venice2_padctrl));
+ pinmux_config_drvgrp_table(venice2_drvgrps,
+ ARRAY_SIZE(venice2_drvgrps));
}
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
+#include <div64.h>
#include "qos.h"
DECLARE_GLOBAL_DATA_PTR;
-#define s_init_wait(cnt) \
- ({ \
- u32 i = 0x10000 * cnt; \
- while (i > 0) \
- i--; \
- })
-
-
-#define dbpdrgd_check(bsc) \
- ({ \
- while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1) \
- ; \
- })
-
-#if defined(CONFIG_NORFLASH)
-static void bsc_init(void)
-{
- struct r8a7791_lbsc *lbsc = (struct r8a7791_lbsc *)LBSC_BASE;
- struct r8a7791_dbsc3 *dbsc3_0 = (struct r8a7791_dbsc3 *)DBSC3_0_BASE;
-
- /* LBSC */
- writel(0x00000020, &lbsc->cs0ctrl);
- writel(0x00000020, &lbsc->cs1ctrl);
- writel(0x00002020, &lbsc->ecs0ctrl);
- writel(0x00002020, &lbsc->ecs1ctrl);
-
- writel(0x077F077F, &lbsc->cswcr0);
- writel(0x077F077F, &lbsc->cswcr1);
- writel(0x077F077F, &lbsc->ecswcr0);
- writel(0x077F077F, &lbsc->ecswcr1);
-
- /* DBSC3 */
- s_init_wait(10);
-
- writel(0x0000A55A, &dbsc3_0->dbpdlck);
- writel(0x00000001, &dbsc3_0->dbpdrga);
- writel(0x80000000, &dbsc3_0->dbpdrgd);
- writel(0x00000004, &dbsc3_0->dbpdrga);
- dbpdrgd_check(dbsc3_0);
-
- writel(0x00000006, &dbsc3_0->dbpdrga);
- writel(0x0001C000, &dbsc3_0->dbpdrgd);
-
- writel(0x00000023, &dbsc3_0->dbpdrga);
- writel(0x00FD2480, &dbsc3_0->dbpdrgd);
-
- writel(0x00000010, &dbsc3_0->dbpdrga);
- writel(0xF004649B, &dbsc3_0->dbpdrgd);
-
- writel(0x0000000F, &dbsc3_0->dbpdrga);
- writel(0x00181EE4, &dbsc3_0->dbpdrgd);
-
- writel(0x0000000E, &dbsc3_0->dbpdrga);
- writel(0x33C03812, &dbsc3_0->dbpdrgd);
-
- writel(0x00000003, &dbsc3_0->dbpdrga);
- writel(0x0300C481, &dbsc3_0->dbpdrgd);
-
- writel(0x00000007, &dbsc3_0->dbkind);
- writel(0x10030A02, &dbsc3_0->dbconf0);
- writel(0x00000001, &dbsc3_0->dbphytype);
- writel(0x00000000, &dbsc3_0->dbbl);
- writel(0x0000000B, &dbsc3_0->dbtr0);
- writel(0x00000008, &dbsc3_0->dbtr1);
- writel(0x00000000, &dbsc3_0->dbtr2);
- writel(0x0000000B, &dbsc3_0->dbtr3);
- writel(0x000C000B, &dbsc3_0->dbtr4);
- writel(0x00000027, &dbsc3_0->dbtr5);
- writel(0x0000001C, &dbsc3_0->dbtr6);
- writel(0x00000005, &dbsc3_0->dbtr7);
- writel(0x00000018, &dbsc3_0->dbtr8);
- writel(0x00000008, &dbsc3_0->dbtr9);
- writel(0x0000000C, &dbsc3_0->dbtr10);
- writel(0x00000009, &dbsc3_0->dbtr11);
- writel(0x00000012, &dbsc3_0->dbtr12);
- writel(0x000000D0, &dbsc3_0->dbtr13);
- writel(0x00140005, &dbsc3_0->dbtr14);
- writel(0x00050004, &dbsc3_0->dbtr15);
- writel(0x70233005, &dbsc3_0->dbtr16);
- writel(0x000C0000, &dbsc3_0->dbtr17);
- writel(0x00000300, &dbsc3_0->dbtr18);
- writel(0x00000040, &dbsc3_0->dbtr19);
- writel(0x00000001, &dbsc3_0->dbrnk0);
- writel(0x00020001, &dbsc3_0->dbadj0);
- writel(0x20082008, &dbsc3_0->dbadj2);
- writel(0x00020002, &dbsc3_0->dbwt0cnf0);
- writel(0x0000000F, &dbsc3_0->dbwt0cnf4);
-
- writel(0x00000015, &dbsc3_0->dbpdrga);
- writel(0x00000D70, &dbsc3_0->dbpdrgd);
-
- writel(0x00000016, &dbsc3_0->dbpdrga);
- writel(0x00000006, &dbsc3_0->dbpdrgd);
-
- writel(0x00000017, &dbsc3_0->dbpdrga);
- writel(0x00000018, &dbsc3_0->dbpdrgd);
-
- writel(0x00000012, &dbsc3_0->dbpdrga);
- writel(0x9D5CBB66, &dbsc3_0->dbpdrgd);
-
- writel(0x00000013, &dbsc3_0->dbpdrga);
- writel(0x1A868300, &dbsc3_0->dbpdrgd);
-
- writel(0x00000023, &dbsc3_0->dbpdrga);
- writel(0x00FDB6C0, &dbsc3_0->dbpdrgd);
-
- writel(0x00000014, &dbsc3_0->dbpdrga);
- writel(0x300214D8, &dbsc3_0->dbpdrgd);
-
- writel(0x0000001A, &dbsc3_0->dbpdrga);
- writel(0x930035C7, &dbsc3_0->dbpdrgd);
-
- writel(0x00000060, &dbsc3_0->dbpdrga);
- writel(0x330657B2, &dbsc3_0->dbpdrgd);
-
- writel(0x00000011, &dbsc3_0->dbpdrga);
- writel(0x1000040B, &dbsc3_0->dbpdrgd);
-
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x00000001, &dbsc3_0->dbpdrga);
- writel(0x00000071, &dbsc3_0->dbpdrgd);
-
- writel(0x00000004, &dbsc3_0->dbpdrga);
- dbpdrgd_check(dbsc3_0);
-
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x2100FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
-
- writel(0x110000DB, &dbsc3_0->dbcmd);
-
- writel(0x00000001, &dbsc3_0->dbpdrga);
- writel(0x00000181, &dbsc3_0->dbpdrgd);
-
- writel(0x00000004, &dbsc3_0->dbpdrga);
- dbpdrgd_check(dbsc3_0);
-
- writel(0x00000001, &dbsc3_0->dbpdrga);
- writel(0x0000FE01, &dbsc3_0->dbpdrgd);
-
- writel(0x00000004, &dbsc3_0->dbpdrga);
- dbpdrgd_check(dbsc3_0);
-
- writel(0x00000000, &dbsc3_0->dbbs0cnt1);
- writel(0x01004C20, &dbsc3_0->dbcalcnf);
- writel(0x014000AA, &dbsc3_0->dbcaltr);
- writel(0x00000140, &dbsc3_0->dbrfcnf0);
- writel(0x00081860, &dbsc3_0->dbrfcnf1);
- writel(0x00010000, &dbsc3_0->dbrfcnf2);
- writel(0x00000001, &dbsc3_0->dbrfen);
- writel(0x00000001, &dbsc3_0->dbacen);
-}
-#else
-#define bsc_init() do {} while (0)
-#endif /* CONFIG_NORFLASH */
-
+#define CLK2MHZ(clk) (clk / 1000 / 1000)
void s_init(void)
{
- struct r8a7791_rwdt *rwdt = (struct r8a7791_rwdt *)RWDT_BASE;
- struct r8a7791_swdt *swdt = (struct r8a7791_swdt *)SWDT_BASE;
+ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+ u32 stc;
/* Watchdog init */
writel(0xA5A5A500, &rwdt->rwtcsra);
writel(0xA5A5A500, &swdt->swtcsra);
+ /* CPU frequency setting. Set to 1.5GHz */
+ stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
+ clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+
/* QoS */
qos_init();
-
- /* BSC */
- bsc_init();
}
#define MSTPSR1 0xE6150038
#define SMSTPCR8 0xE6150990
#define ETHER_MSTP813 (1 << 13)
-#define PMMR 0xE6060000
-#define GPSR4 0xE6060014
-#define IPSR14 0xE6060058
-
-#define set_guard_reg(addr, mask, value) \
-{ \
- u32 val; \
- val = (readl(addr) & ~(mask)) | (value); \
- writel(~val, PMMR); \
- writel(val, addr); \
-}
-
#define mstp_setbits(type, addr, saddr, set) \
out_##type((saddr), in_##type(addr) | (set))
#define mstp_clrbits(type, addr, saddr, clear) \
{
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
-#if defined(CONFIG_NORFLASH)
/* SCIF0 */
- set_guard_reg(GPSR4, 0x34000000, 0x00000000);
- set_guard_reg(IPSR14, 0x00000FC7, 0x00000481);
- set_guard_reg(GPSR4, 0x00000000, 0x34000000);
-#endif
-
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
/* ETHER */
/*
* board/renesas/koelsch/qos.c
*
- * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*
#include <asm/io.h>
#include <asm/arch/rmobile.h>
-/* QoS version 0.23 */
+/* QoS version 0.240 for ES1 and version 0.310 for ES2 */
enum {
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
void qos_init(void)
{
int i;
- struct r8a7791_s3c *s3c;
- struct r8a7791_s3c_qos *s3c_qos;
- struct r8a7791_dbsc3_qos *qos_addr;
- struct r8a7791_mxi *mxi;
- struct r8a7791_mxi_qos *mxi_qos;
- struct r8a7791_axi_qos *axi_qos;
+ struct rcar_s3c *s3c;
+ struct rcar_s3c_qos *s3c_qos;
+ struct rcar_dbsc3_qos *qos_addr;
+ struct rcar_mxi *mxi;
+ struct rcar_mxi_qos *mxi_qos;
+ struct rcar_axi_qos *axi_qos;
/* DBSC DBADJ2 */
writel(0x20042004, DBSC3_0_DBADJ2);
/* S3C -QoS */
- s3c = (struct r8a7791_s3c *)S3C_BASE;
- writel(0x00FF1B1D, &s3c->s3cadsplcr);
- writel(0x1F0D0C0C, &s3c->s3crorr);
- writel(0x1F0D0C0A, &s3c->s3cworr);
-
+ s3c = (struct rcar_s3c *)S3C_BASE;
+ if (IS_R8A7791_ES2()) {
+ writel(0x00FF1B0D, &s3c->s3cadsplcr);
+ writel(0x1F0D0B0A, &s3c->s3crorr);
+ writel(0x1F0D0B09, &s3c->s3cworr);
+ writel(0x00200808, &s3c->s3carcr11);
+ } else {
+ writel(0x00FF1B1D, &s3c->s3cadsplcr);
+ writel(0x1F0D0C0C, &s3c->s3crorr);
+ writel(0x1F0D0C0A, &s3c->s3cworr);
+ }
/* QoS Control Registers */
- s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_CCI0_BASE;
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
writel(0x00890089, &s3c_qos->s3cqos0);
writel(0x20960010, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
writel(0x20AA2200, &s3c_qos->s3cqos7);
writel(0x00002032, &s3c_qos->s3cqos8);
- s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_CCI1_BASE;
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
writel(0x00890089, &s3c_qos->s3cqos0);
writel(0x20960010, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
writel(0x20AA2200, &s3c_qos->s3cqos7);
writel(0x00002032, &s3c_qos->s3cqos8);
- s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_MXI_BASE;
- writel(0x00820082, &s3c_qos->s3cqos0);
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x80928092, &s3c_qos->s3cqos0);
+ else
+ writel(0x00820082, &s3c_qos->s3cqos0);
writel(0x20960020, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
writel(0x20AA20DC, &s3c_qos->s3cqos3);
writel(0x20AA20DC, &s3c_qos->s3cqos7);
writel(0x00002032, &s3c_qos->s3cqos8);
- s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_AXI_BASE;
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
writel(0x00820082, &s3c_qos->s3cqos0);
writel(0x20960020, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
/* DBSC -QoS */
/* DBSC0 - Read */
for (i = DBSC3_00; i < DBSC3_NR; i++) {
- qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
writel(0x00000002, &qos_addr->dblgcnt);
writel(0x00002096, &qos_addr->dbtmval0);
writel(0x00002064, &qos_addr->dbtmval1);
/* DBSC0 - Write */
for (i = DBSC3_00; i < DBSC3_NR; i++) {
- qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
writel(0x00000002, &qos_addr->dblgcnt);
writel(0x000020EB, &qos_addr->dbtmval0);
writel(0x0000206E, &qos_addr->dbtmval1);
/* DBSC1 - Read */
for (i = DBSC3_00; i < DBSC3_NR; i++) {
- qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_1_r_qos_addr[i];
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_r_qos_addr[i];
writel(0x00000002, &qos_addr->dblgcnt);
writel(0x00002096, &qos_addr->dbtmval0);
writel(0x00002064, &qos_addr->dbtmval1);
/* DBSC1 - Write */
for (i = DBSC3_00; i < DBSC3_NR; i++) {
- qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_1_w_qos_addr[i];
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_w_qos_addr[i];
writel(0x00000002, &qos_addr->dblgcnt);
writel(0x000020EB, &qos_addr->dbtmval0);
writel(0x0000206E, &qos_addr->dbtmval1);
/* MXI -QoS */
/* Transaction Control (MXI) */
- mxi = (struct r8a7791_mxi *)MXI_BASE;
+ mxi = (struct rcar_mxi *)MXI_BASE;
writel(0x00000013, &mxi->mxrtcr);
writel(0x00000013, &mxi->mxwtcr);
writel(0x00780080, &mxi->mxsaar0);
writel(0x02000800, &mxi->mxsaar1);
/* QoS Control (MXI) */
- mxi_qos = (struct r8a7791_mxi_qos *)MXI_QOS_BASE;
+ mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
writel(0x0000000C, &mxi_qos->vspdu0);
writel(0x0000000C, &mxi_qos->vspdu1);
writel(0x0000000D, &mxi_qos->du0);
/* AXI -QoS */
/* Transaction Control (MXI) */
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_AVB_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x000020A6, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_G2D_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x000020A6, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMP0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002021, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMP1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002037, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMUX0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMUX1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMUX2_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_LBS_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000214C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUDS_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUM_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUR_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUS0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUS1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MTSB0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002021, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MTSB1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002021, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_PCI_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000214C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_RTX_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDS0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x000020A6, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDS1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x000020A6, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB20_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB21_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB22_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB30_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000214C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_AX2M_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_CC50_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002029, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_CCI_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_CS_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_DDM_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x000020A6, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_ETH_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MPXM_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SAT0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SAT1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDM0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000214C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDM1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000214C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_TRAB_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x000020A6, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_UDM0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_UDM1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (RT-AXI) */
- axi_qos = (struct r8a7791_axi_qos *)RT_AXI_SHX_BASE;
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)RT_AXI_DBG_BASE;
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)RT_AXI_RDM_BASE;
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002299, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)RT_AXI_RDS_BASE;
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002029, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)RT_AXI_RTX64TO128_BASE;
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)RT_AXI_STPRO_BASE;
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002029, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)RT_AXI_SY2RT_BASE;
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
- writel(0x00002096, &axi_qos->qosctset1);
- writel(0x00002030, &axi_qos->qosctset2);
- writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (MP-AXI) */
- axi_qos = (struct r8a7791_axi_qos *)MP_AXI_ADSP_BASE;
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002037, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MP_AXI_ASDS0_BASE;
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002014, &axi_qos->qosctset0);
- writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00000040, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MP_AXI_ASDS1_BASE;
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002014, &axi_qos->qosctset0);
- writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00000040, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MP_AXI_MLP_BASE;
- writel(0x00000000, &axi_qos->qosconf);
- writel(0x00002014, &axi_qos->qosctset0);
- writel(0x00000001, &axi_qos->qosreqctr);
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00001FF0, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
- writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00002001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MP_AXI_MMUMP_BASE;
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MP_AXI_SPU_BASE;
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MP_AXI_SPUC_BASE;
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000206E, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (SYS-AXI256) */
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
writel(0x00000002, &axi_qos->qosconf);
- writel(0x00002245, &axi_qos->qosctset0);
+ if (IS_R8A7791_ES2())
+ writel(0x000020EB, &axi_qos->qosctset0);
+ else
+ writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_SYX_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
writel(0x00000002, &axi_qos->qosconf);
- writel(0x00002245, &axi_qos->qosctset0);
+ if (IS_R8A7791_ES2())
+ writel(0x000020EB, &axi_qos->qosctset0);
+ else
+ writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_MPX_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
writel(0x00000002, &axi_qos->qosconf);
- writel(0x00002245, &axi_qos->qosctset0);
+ if (IS_R8A7791_ES2())
+ writel(0x000020EB, &axi_qos->qosctset0);
+ else
+ writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_MXI_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (CCI-AXI) */
- axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUS0_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_SYX2_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUR_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUDS_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUM_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MXI_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUS1_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUMP_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (Media-AXI) */
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_MXR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x000020DC, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002032, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_MXW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x000020DC, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002032, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_JPR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002190, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_JPW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002190, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
- writel(0x00002064, &axi_qos->qosthres0);
- writel(0x00002004, &axi_qos->qosthres1);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_TDMR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002190, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_TDMW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002190, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002190, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002190, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
- writel(0x00002064, &axi_qos->qosthres0);
- writel(0x00002004, &axi_qos->qosthres1);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002190, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002190, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
- writel(0x00002064, &axi_qos->qosthres0);
- writel(0x00002004, &axi_qos->qosthres1);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002190, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002190, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
- writel(0x00002064, &axi_qos->qosthres0);
- writel(0x00002004, &axi_qos->qosthres1);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
writel(0x00000001, &axi_qos->qosconf);
- writel(0x000020C8, &axi_qos->qosctset0);
+ if (IS_R8A7791_ES2())
+ writel(0x00001FF0, &axi_qos->qosctset0);
+ else
+ writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
- writel(0x00000001, &axi_qos->qosthres2);
+ if (IS_R8A7791_ES2())
+ writel(0x00002001, &axi_qos->qosthres2);
+ else
+ writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
- writel(0x00002064, &axi_qos->qosthres0);
- writel(0x00002004, &axi_qos->qosthres1);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMSR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMSW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
- writel(0x00002064, &axi_qos->qosthres0);
- writel(0x00002004, &axi_qos->qosthres1);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
- writel(0x00002064, &axi_qos->qosthres0);
- writel(0x00002004, &axi_qos->qosthres1);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMRR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMRW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
- writel(0x00000000, &axi_qos->qosconf);
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x00000003, &axi_qos->qosconf);
+ else
+ writel(0x00000000, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
- writel(0x00000000, &axi_qos->qosconf);
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x00000003, &axi_qos->qosconf);
+ else
+ writel(0x00000000, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
- writel(0x00000000, &axi_qos->qosconf);
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x00000003, &axi_qos->qosconf);
+ else
+ writel(0x00000000, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
- writel(0x00000000, &axi_qos->qosconf);
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x00000003, &axi_qos->qosconf);
+ else
+ writel(0x00000000, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_DU0R_BASE;
- writel(0x00000000, &axi_qos->qosconf);
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x00000003, &axi_qos->qosconf);
+ else
+ writel(0x00000000, &axi_qos->qosconf);
writel(0x00002063, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_DU0W_BASE;
- writel(0x00000000, &axi_qos->qosconf);
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x00000000, &axi_qos->qosconf);
+ else
+ writel(0x00000000, &axi_qos->qosconf);
writel(0x00002063, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002073, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002073, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
- writel(0x00002064, &axi_qos->qosthres0);
- writel(0x00002004, &axi_qos->qosthres1);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002073, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002073, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
- writel(0x00002064, &axi_qos->qosthres0);
- writel(0x00002004, &axi_qos->qosthres1);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002073, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
DECLARE_GLOBAL_DATA_PTR;
-#define s_init_wait(cnt) \
- ({ \
- u32 i = 0x10000 * cnt; \
- while (i > 0) \
- i--; \
- })
-
-#define dbpdrgd_check(bsc) \
- ({ \
- while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1) \
- ; \
- })
-
-#if defined(CONFIG_NORFLASH)
-static void bsc_init(void)
-{
- struct r8a7790_lbsc *lbsc = (struct r8a7790_lbsc *)LBSC_BASE;
- struct r8a7790_dbsc3 *dbsc3_0 = (struct r8a7790_dbsc3 *)DBSC3_0_BASE;
-
- /* LBSC */
- writel(0x00000020, &lbsc->cs0ctrl);
- writel(0x00000020, &lbsc->cs1ctrl);
- writel(0x00002020, &lbsc->ecs0ctrl);
- writel(0x00002020, &lbsc->ecs1ctrl);
-
- writel(0x077F077F, &lbsc->cswcr0);
- writel(0x077F077F, &lbsc->cswcr1);
- writel(0x077F077F, &lbsc->ecswcr0);
- writel(0x077F077F, &lbsc->ecswcr1);
-
- /* DBSC3 */
- s_init_wait(10);
-
- writel(0x0000A55A, &dbsc3_0->dbpdlck);
- writel(0x00000001, &dbsc3_0->dbpdrga);
- writel(0x80000000, &dbsc3_0->dbpdrgd);
- writel(0x00000004, &dbsc3_0->dbpdrga);
- dbpdrgd_check(dbsc3_0);
-
- writel(0x00000006, &dbsc3_0->dbpdrga);
- writel(0x0001C000, &dbsc3_0->dbpdrgd);
-
- writel(0x00000023, &dbsc3_0->dbpdrga);
- writel(0x00FD2480, &dbsc3_0->dbpdrgd);
-
- writel(0x00000010, &dbsc3_0->dbpdrga);
- writel(0xF004649B, &dbsc3_0->dbpdrgd);
-
- writel(0x0000000F, &dbsc3_0->dbpdrga);
- writel(0x00181EE4, &dbsc3_0->dbpdrgd);
-
- writel(0x0000000E, &dbsc3_0->dbpdrga);
- writel(0x33C03812, &dbsc3_0->dbpdrgd);
-
- writel(0x00000003, &dbsc3_0->dbpdrga);
- writel(0x0300C481, &dbsc3_0->dbpdrgd);
-
- writel(0x00000007, &dbsc3_0->dbkind);
- writel(0x10030A02, &dbsc3_0->dbconf0);
- writel(0x00000001, &dbsc3_0->dbphytype);
- writel(0x00000000, &dbsc3_0->dbbl);
- writel(0x0000000B, &dbsc3_0->dbtr0);
- writel(0x00000008, &dbsc3_0->dbtr1);
- writel(0x00000000, &dbsc3_0->dbtr2);
- writel(0x0000000B, &dbsc3_0->dbtr3);
- writel(0x000C000B, &dbsc3_0->dbtr4);
- writel(0x00000027, &dbsc3_0->dbtr5);
- writel(0x0000001C, &dbsc3_0->dbtr6);
- writel(0x00000005, &dbsc3_0->dbtr7);
- writel(0x00000018, &dbsc3_0->dbtr8);
- writel(0x00000008, &dbsc3_0->dbtr9);
- writel(0x0000000C, &dbsc3_0->dbtr10);
- writel(0x00000009, &dbsc3_0->dbtr11);
- writel(0x00000012, &dbsc3_0->dbtr12);
- writel(0x000000D0, &dbsc3_0->dbtr13);
- writel(0x00140005, &dbsc3_0->dbtr14);
- writel(0x00050004, &dbsc3_0->dbtr15);
- writel(0x70233005, &dbsc3_0->dbtr16);
- writel(0x000C0000, &dbsc3_0->dbtr17);
- writel(0x00000300, &dbsc3_0->dbtr18);
- writel(0x00000040, &dbsc3_0->dbtr19);
- writel(0x00000001, &dbsc3_0->dbrnk0);
- writel(0x00020001, &dbsc3_0->dbadj0);
- writel(0x20082008, &dbsc3_0->dbadj2);
- writel(0x00020002, &dbsc3_0->dbwt0cnf0);
- writel(0x0000000F, &dbsc3_0->dbwt0cnf4);
-
- writel(0x00000015, &dbsc3_0->dbpdrga);
- writel(0x00000D70, &dbsc3_0->dbpdrgd);
-
- writel(0x00000016, &dbsc3_0->dbpdrga);
- writel(0x00000006, &dbsc3_0->dbpdrgd);
-
- writel(0x00000017, &dbsc3_0->dbpdrga);
- writel(0x00000018, &dbsc3_0->dbpdrgd);
-
- writel(0x00000012, &dbsc3_0->dbpdrga);
- writel(0x9D5CBB66, &dbsc3_0->dbpdrgd);
-
- writel(0x00000013, &dbsc3_0->dbpdrga);
- writel(0x1A868300, &dbsc3_0->dbpdrgd);
-
- writel(0x00000023, &dbsc3_0->dbpdrga);
- writel(0x00FDB6C0, &dbsc3_0->dbpdrgd);
-
- writel(0x00000014, &dbsc3_0->dbpdrga);
- writel(0x300214D8, &dbsc3_0->dbpdrgd);
-
- writel(0x0000001A, &dbsc3_0->dbpdrga);
- writel(0x930035C7, &dbsc3_0->dbpdrgd);
-
- writel(0x00000060, &dbsc3_0->dbpdrga);
- writel(0x330657B2, &dbsc3_0->dbpdrgd);
-
- writel(0x00000011, &dbsc3_0->dbpdrga);
- writel(0x1000040B, &dbsc3_0->dbpdrgd);
-
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x00000001, &dbsc3_0->dbpdrga);
- writel(0x00000071, &dbsc3_0->dbpdrgd);
-
- writel(0x00000004, &dbsc3_0->dbpdrga);
- dbpdrgd_check(dbsc3_0);
-
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x2100FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
-
- writel(0x110000DB, &dbsc3_0->dbcmd);
-
- writel(0x00000001, &dbsc3_0->dbpdrga);
- writel(0x00000181, &dbsc3_0->dbpdrgd);
-
- writel(0x00000004, &dbsc3_0->dbpdrga);
- dbpdrgd_check(dbsc3_0);
-
- writel(0x00000001, &dbsc3_0->dbpdrga);
- writel(0x0000FE01, &dbsc3_0->dbpdrgd);
-
- writel(0x00000004, &dbsc3_0->dbpdrga);
- dbpdrgd_check(dbsc3_0);
-
- writel(0x00000000, &dbsc3_0->dbbs0cnt1);
- writel(0x01004C20, &dbsc3_0->dbcalcnf);
- writel(0x014000AA, &dbsc3_0->dbcaltr);
- writel(0x00000140, &dbsc3_0->dbrfcnf0);
- writel(0x00081860, &dbsc3_0->dbrfcnf1);
- writel(0x00010000, &dbsc3_0->dbrfcnf2);
- writel(0x00000001, &dbsc3_0->dbrfen);
- writel(0x00000001, &dbsc3_0->dbacen);
-}
-#else
-#define bsc_init() do {} while (0)
-#endif /* CONFIG_NORFLASH */
-
+#define CLK2MHZ(clk) (clk / 1000 / 1000)
void s_init(void)
{
- struct r8a7790_rwdt *rwdt = (struct r8a7790_rwdt *)RWDT_BASE;
- struct r8a7790_swdt *swdt = (struct r8a7790_swdt *)SWDT_BASE;
+ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+ u32 stc;
/* Watchdog init */
writel(0xA5A5A500, &rwdt->rwtcsra);
writel(0xA5A5A500, &swdt->swtcsra);
+ /* CPU frequency setting. Set to 1.4GHz */
+ stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
+ clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+
/* QoS(Quality-of-Service) Init */
qos_init();
-
- /* BSC init */
- bsc_init();
}
#define MSTPSR1 0xE6150038
#define SMSTPCR8 0xE6150990
#define ETHER_MSTP813 (1 << 13)
-#define PMMR 0xE6060000
-#define GPSR4 0xE6060014
-#define IPSR14 0xE6060058
-
-#define set_guard_reg(addr, mask, value) \
-{ \
- u32 val; \
- val = (readl(addr) & ~(mask)) | (value); \
- writel(~val, PMMR); \
- writel(val, addr); \
-}
-
#define mstp_setbits(type, addr, saddr, set) \
out_##type((saddr), in_##type(addr) | (set))
#define mstp_clrbits(type, addr, saddr, clear) \
{
/* TMU0 */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
-
-#if defined(CONFIG_NORFLASH)
/* SCIF0 */
- set_guard_reg(GPSR4, 0x34000000, 0x00000000);
- set_guard_reg(IPSR14, 0x00000FC7, 0x00000481);
- set_guard_reg(GPSR4, 0x00000000, 0x34000000);
-#endif
-
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
-
/* ETHER */
mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
- /* board id for linux */
- gd->bd->bi_arch_number = MACH_TYPE_LAGER;
/* adress of boot parameters */
gd->bd->bi_boot_params = LAGER_SDRAM_BASE + 0x100;
/*
* board/renesas/lager/qos.c
*
- * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <asm/io.h>
#include <asm/arch/rmobile.h>
-/* QoS version 0.954 */
+/* QoS version 0.955 */
enum {
DBSC3_R00, DBSC3_R01, DBSC3_R02, DBSC3_R03, DBSC3_R04,
void qos_init(void)
{
int i;
- struct r8a7790_s3c *s3c;
- struct r8a7790_s3c_qos *s3c_qos;
- struct r8a7790_dbsc3_qos *qos_addr;
- struct r8a7790_mxi *mxi;
- struct r8a7790_mxi_qos *mxi_qos;
- struct r8a7790_axi_qos *axi_qos;
+ struct rcar_s3c *s3c;
+ struct rcar_s3c_qos *s3c_qos;
+ struct rcar_dbsc3_qos *qos_addr;
+ struct rcar_mxi *mxi;
+ struct rcar_mxi_qos *mxi_qos;
+ struct rcar_axi_qos *axi_qos;
/* DBSC DBADJ2 */
writel(0x20042004, DBSC3_0_DBADJ2);
/* S3C -QoS */
- s3c = (struct r8a7790_s3c *)S3C_BASE;
+ s3c = (struct rcar_s3c *)S3C_BASE;
writel(0x80FF1C1E, &s3c->s3cadsplcr);
writel(0x1F060505, &s3c->s3crorr);
writel(0x1F020100, &s3c->s3cworr);
/* QoS Control Registers */
- s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_CCI0_BASE;
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
writel(0x00800080, &s3c_qos->s3cqos0);
writel(0x22000010, &s3c_qos->s3cqos1);
writel(0x22002200, &s3c_qos->s3cqos2);
writel(0x2F002200, &s3c_qos->s3cqos7);
writel(0x2F002F00, &s3c_qos->s3cqos8);
- s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_CCI1_BASE;
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
writel(0x00800080, &s3c_qos->s3cqos0);
writel(0x22000010, &s3c_qos->s3cqos1);
writel(0x22002200, &s3c_qos->s3cqos2);
writel(0x2F002200, &s3c_qos->s3cqos7);
writel(0x2F002F00, &s3c_qos->s3cqos8);
- s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_MXI_BASE;
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
writel(0x80918099, &s3c_qos->s3cqos0);
writel(0x20410010, &s3c_qos->s3cqos1);
writel(0x200A2023, &s3c_qos->s3cqos2);
writel(0x20502001, &s3c_qos->s3cqos7);
writel(0x20142032, &s3c_qos->s3cqos8);
- s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_AXI_BASE;
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
writel(0x00810089, &s3c_qos->s3cqos0);
writel(0x20410001, &s3c_qos->s3cqos1);
/* DBSC -QoS */
/* DBSC0 - Read/Write */
for (i = DBSC3_R00; i < DBSC3_NR; i++) {
- qos_addr = (struct r8a7790_dbsc3_qos *)dbsc3_qos_addr[i];
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_qos_addr[i];
writel(0x00000203, &qos_addr->dblgcnt);
writel(0x00002064, &qos_addr->dbtmval0);
writel(0x00002048, &qos_addr->dbtmval1);
/* MXI -QoS */
/* Transaction Control (MXI) */
- mxi = (struct r8a7790_mxi *)MXI_BASE;
+ mxi = (struct rcar_mxi *)MXI_BASE;
writel(0x00000013, &mxi->mxrtcr);
writel(0x00000013, &mxi->mxwtcr);
writel(0x00B800C0, &mxi->mxsaar0);
writel(0x00200000, &mxi->mxaxiwacr);
/* QoS Control (MXI) */
- mxi_qos = (struct r8a7790_mxi_qos *)MXI_QOS_BASE;
+ mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
writel(0x0000000C, &mxi_qos->vspdu0);
writel(0x0000000C, &mxi_qos->vspdu1);
writel(0x0000000D, &mxi_qos->du0);
/* AXI -QoS */
/* Transaction Control (MXI) */
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_AVB_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200A, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_G2D_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200A, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMP0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002002, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMP1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX2_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_LBS_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002014, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUDS_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUM_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUR_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUS0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUS1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MTSB0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002002, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MTSB1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002002, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_PCI_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002014, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_RTX_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SDS0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200A, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SDS1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200A, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB20_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002005, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB21_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002005, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB22_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002005, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB30_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002014, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (RT-AXI) */
- axi_qos = (struct r8a7790_axi_qos *)RT_AXI_SHX_BASE;
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002005, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)RT_AXI_RDS_BASE;
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)RT_AXI_RTX64TO128_BASE;
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)RT_AXI_STPRO_BASE;
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002003, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (MP-AXI) */
- axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ADSP_BASE;
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ASDS0_BASE;
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002014, &axi_qos->qosctset0);
- writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00000040, &axi_qos->qosreqctr);
writel(0x00002006, &axi_qos->qosthres0);
writel(0x00002001, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ASDS1_BASE;
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002014, &axi_qos->qosctset0);
- writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00000040, &axi_qos->qosreqctr);
writel(0x00002006, &axi_qos->qosthres0);
writel(0x00002001, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MP_AXI_MLP_BASE;
- writel(0x00000000, &axi_qos->qosconf);
- writel(0x00002002, &axi_qos->qosctset0);
- writel(0x00000001, &axi_qos->qosreqctr);
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00001FF0, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00002006, &axi_qos->qosthres0);
writel(0x00002001, &axi_qos->qosthres1);
- writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00002001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MP_AXI_MMUMP_BASE;
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MP_AXI_SPU_BASE;
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MP_AXI_SPUC_BASE;
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200D, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (SYS-AXI256) */
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_SYX_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_MPX_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_MXI_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (CCI-AXI) */
- axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUS0_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_SYX2_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUR_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUDS_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUM_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MXI_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUS1_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUMP_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (Media-AXI) */
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_JPR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_JPW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU0R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU0W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU1R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU1W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_TDMR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_TDMW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0CR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0CW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMSR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMSW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMRR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMRW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP2R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP2W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU0R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU0W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU1R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1R_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU1W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1W_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1CR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1CW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1VR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1VW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VPC1R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC1R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
#ifdef CONFIG_USB_EHCI_EXYNOS
int board_usb_init(int index, enum usb_init_type init)
{
- struct exynos5_gpio_part1 *gpio = (struct exynos5_gpio_part1 *)
- samsung_get_base_gpio_part1();
-
/* Configure gpios for usb 3503 hub:
* disconnect, toggle reset and connect
*/
- s5p_gpio_direction_output(&gpio->d1, 7, 0);
- s5p_gpio_direction_output(&gpio->x3, 5, 0);
+ gpio_direction_output(EXYNOS5_GPIO_D17, 0);
+ gpio_direction_output(EXYNOS5_GPIO_X35, 0);
- s5p_gpio_direction_output(&gpio->x3, 5, 1);
- s5p_gpio_direction_output(&gpio->d1, 7, 1);
+ gpio_direction_output(EXYNOS5_GPIO_X35, 1);
+ gpio_direction_output(EXYNOS5_GPIO_D17, 1);
return 0;
}
obj-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o
obj-$(CONFIG_THOR_FUNCTION) += thor.o
-obj-$(CONFIG_CMD_USB_MASS_STORAGE) += ums.o
obj-$(CONFIG_MISC_COMMON) += misc.o
ifndef CONFIG_SPL_BUILD
* 4 BOOT_MODE_EXIT
*/
static char *
-mode_name[BOOT_MODE_EXIT + 1] = {
- "DEVICE",
- "THOR",
- "UMS",
- "DFU",
- "EXIT"
+mode_name[BOOT_MODE_EXIT + 1][2] = {
+ {"DEVICE", ""},
+ {"THOR", "thor"},
+ {"UMS", "ums"},
+ {"DFU", "dfu"},
+ {"GPT", "gpt"},
+ {"ENV", "env"},
+ {"EXIT", ""},
};
static char *
"downloader",
"mass storage",
"firmware update",
+ "restore",
+ "default",
"and run normal boot"
};
-#define MODE_CMD_ARGC 4
-
static char *
-mode_cmd[BOOT_MODE_EXIT + 1][MODE_CMD_ARGC] = {
- {"", "", "", ""},
- {"thor", "0", "mmc", "0"},
- {"ums", "0", "mmc", "0"},
- {"dfu", "0", "mmc", "0"},
- {"", "", "", ""},
+mode_cmd[BOOT_MODE_EXIT + 1] = {
+ "",
+ "thor 0 mmc 0",
+ "ums 0 mmc 0",
+ "dfu 0 mmc 0",
+ "gpt write mmc 0 $partitions",
+ "env default -a; saveenv",
+ "",
};
static void display_board_info(void)
static int mode_leave_menu(int mode)
{
char *exit_option;
- char *exit_boot = "boot";
+ char *exit_reset = "reset";
char *exit_back = "back";
cmd_tbl_t *cmd;
int cmd_result;
- int cmd_repeatable;
int leave;
lcd_clear();
leave = 0;
break;
default:
- cmd = find_cmd(mode_cmd[mode][0]);
+ cmd = find_cmd(mode_name[mode][1]);
if (cmd) {
- printf("Enter: %s %s\n", mode_name[mode],
+ printf("Enter: %s %s\n", mode_name[mode][0],
mode_info[mode]);
- lcd_printf("\n\n\t%s %s\n", mode_name[mode],
+ lcd_printf("\n\n\t%s %s\n", mode_name[mode][0],
mode_info[mode]);
lcd_puts("\n\tDo not turn off device before finish!\n");
- cmd_result = cmd_process(0, MODE_CMD_ARGC,
- *(mode_cmd + mode),
- &cmd_repeatable, NULL);
+ cmd_result = run_command(mode_cmd[mode], 0);
if (cmd_result == CMD_RET_SUCCESS) {
printf("Command finished\n");
lcd_clear();
lcd_printf("\n\n\t%s finished\n",
- mode_name[mode]);
+ mode_name[mode][0]);
- exit_option = exit_boot;
+ exit_option = exit_reset;
leave = 1;
} else {
printf("Command error\n");
lcd_clear();
lcd_printf("\n\n\t%s command error\n",
- mode_name[mode]);
+ mode_name[mode][0]);
exit_option = exit_back;
leave = 0;
selection[mode] = "[=>]";
lcd_clear();
- lcd_printf("\n\t\tDownload Mode Menu\n");
+ lcd_printf("\n\n\t\tDownload Mode Menu\n\n");
for (i = 0; i <= BOOT_MODE_EXIT; i++)
lcd_printf("\t%s %s - %s\n\n", selection[i],
- mode_name[i],
+ mode_name[i][0],
mode_info[i]);
}
int mode = 0;
int last_mode = 0;
int run;
- int key;
+ int key = 0;
+ int timeout = 15; /* sec */
+ int i;
display_download_menu(mode);
+ lcd_puts("\n");
+
+ /* Start count if no key is pressed */
+ while (check_keys())
+ continue;
+
+ while (timeout--) {
+ lcd_printf("\r\tNormal boot will start in: %2.d seconds.",
+ timeout);
+
+ /* about 1000 ms in for loop */
+ for (i = 0; i < 10; i++) {
+ mdelay(100);
+ key = check_keys();
+ if (key)
+ break;
+ }
+ if (key)
+ break;
+ }
+
+ if (!key) {
+ lcd_clear();
+ return;
+ }
+
while (1) {
run = 0;
display_download_menu(mode);
last_mode = mode;
- mdelay(100);
+ mdelay(200);
key = check_keys();
switch (key) {
if (run) {
if (mode_leave_menu(mode))
- break;
+ run_command("reset", 0);
display_download_menu(mode);
}
lcd_clear();
}
-static void display_mode_info(void)
-{
- lcd_position_cursor(4, 4);
- lcd_printf("%s\n", U_BOOT_VERSION);
- lcd_puts("\nDownload Mode Menu\n");
-#ifdef CONFIG_SYS_BOARD
- lcd_printf("Board name: %s\n", CONFIG_SYS_BOARD);
-#endif
- lcd_printf("Press POWER KEY to display MENU options.");
-}
-
-static int boot_menu(void)
-{
- int key = 0;
- int timeout = 10;
-
- display_mode_info();
-
- while (timeout--) {
- lcd_printf("\rNormal boot will start in: %d seconds.", timeout);
- mdelay(1000);
-
- key = key_pressed(KEY_POWER);
- if (key)
- break;
- }
-
- lcd_clear();
-
- /* If PWR pressed - show download menu */
- if (key) {
- printf("Power pressed - go to download menu\n");
- download_menu();
- printf("Download mode exit.\n");
- }
-
- return 0;
-}
-
void check_boot_mode(void)
{
int pwr_key;
power_key_pressed(KEY_PWR_INTERRUPT_REG);
if (key_pressed(KEY_VOLUMEUP))
- boot_menu();
+ download_menu();
else if (key_pressed(KEY_VOLUMEDOWN))
mode_leave_menu(BOOT_MODE_THOR);
}
+++ /dev/null
-/*
- * Copyright (C) 2013 Samsung Electronics
- * Lukasz Majewski <l.majewski@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <usb_mass_storage.h>
-#include <part.h>
-
-static int ums_read_sector(struct ums *ums_dev,
- ulong start, lbaint_t blkcnt, void *buf)
-{
- block_dev_desc_t *block_dev = &ums_dev->mmc->block_dev;
- lbaint_t blkstart = start + ums_dev->start_sector;
- int dev_num = block_dev->dev;
-
- return block_dev->block_read(dev_num, blkstart, blkcnt, buf);
-}
-
-static int ums_write_sector(struct ums *ums_dev,
- ulong start, lbaint_t blkcnt, const void *buf)
-{
- block_dev_desc_t *block_dev = &ums_dev->mmc->block_dev;
- lbaint_t blkstart = start + ums_dev->start_sector;
- int dev_num = block_dev->dev;
-
- return block_dev->block_write(dev_num, blkstart, blkcnt, buf);
-}
-
-static struct ums ums_dev = {
- .read_sector = ums_read_sector,
- .write_sector = ums_write_sector,
- .name = "UMS disk",
-};
-
-static struct ums *ums_disk_init(struct mmc *mmc)
-{
- uint64_t mmc_end_sector = mmc->capacity / SECTOR_SIZE;
- uint64_t ums_end_sector = UMS_NUM_SECTORS + UMS_START_SECTOR;
-
- if (!mmc_end_sector) {
- error("MMC capacity is not valid");
- return NULL;
- }
-
- ums_dev.mmc = mmc;
-
- if (ums_end_sector <= mmc_end_sector) {
- ums_dev.start_sector = UMS_START_SECTOR;
- if (UMS_NUM_SECTORS)
- ums_dev.num_sectors = UMS_NUM_SECTORS;
- else
- ums_dev.num_sectors = mmc_end_sector - UMS_START_SECTOR;
- } else {
- ums_dev.num_sectors = mmc_end_sector;
- puts("UMS: defined bad disk parameters. Using default.\n");
- }
-
- printf("UMS: disk start sector: %#x, count: %#x\n",
- ums_dev.start_sector, ums_dev.num_sectors);
-
- return &ums_dev;
-}
-
-struct ums *ums_init(unsigned int dev_num)
-{
- struct mmc *mmc = find_mmc_device(dev_num);
-
- if (!mmc || mmc_init(mmc))
- return NULL;
- return ums_disk_init(mmc);
-}
DECLARE_GLOBAL_DATA_PTR;
-static struct s5pc110_gpio *s5pc110_gpio;
-
u32 get_board_rev(void)
{
return 0;
int board_init(void)
{
/* Set Initial global variables */
- s5pc110_gpio = (struct s5pc110_gpio *)S5PC110_GPIO_BASE;
-
gd->bd->bi_arch_number = MACH_TYPE_GONI;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
int i, ret, ret_sd = 0;
/* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */
- s5p_gpio_direction_output(&s5pc110_gpio->j2, 7, 1);
+ gpio_direction_output(S5PC110_GPIO_J27, 1);
/*
* MMC0 GPIO
* GPG0[2] SD_0_CDn -> Not used
* GPG0[3:6] SD_0_DATA[0:3]
*/
- for (i = 0; i < 7; i++) {
- if (i == 2)
+ for (i = S5PC110_GPIO_G00; i < S5PC110_GPIO_G07; i++) {
+ if (i == S5PC110_GPIO_G02)
continue;
/* GPG0[0:6] special function 2 */
- s5p_gpio_cfg_pin(&s5pc110_gpio->g0, i, 0x2);
+ gpio_cfg_pin(i, 0x2);
/* GPG0[0:6] pull disable */
- s5p_gpio_set_pull(&s5pc110_gpio->g0, i, GPIO_PULL_NONE);
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
/* GPG0[0:6] drv 4x */
- s5p_gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
ret = s5p_mmc_init(0, 4);
* SD card (T_FLASH) detect and init
* T_FLASH_DETECT: EINT28: GPH3[4] input mode
*/
- s5p_gpio_cfg_pin(&s5pc110_gpio->h3, 4, GPIO_INPUT);
- s5p_gpio_set_pull(&s5pc110_gpio->h3, 4, GPIO_PULL_UP);
+ gpio_cfg_pin(S5PC110_GPIO_H34, S5P_GPIO_INPUT);
+ gpio_set_pull(S5PC110_GPIO_H34, S5P_GPIO_PULL_UP);
- if (!s5p_gpio_get_value(&s5pc110_gpio->h3, 4)) {
- for (i = 0; i < 7; i++) {
- if (i == 2)
+ if (!gpio_get_value(S5PC110_GPIO_H34)) {
+ for (i = S5PC110_GPIO_G20; i < S5PC110_GPIO_G27; i++) {
+ if (i == S5PC110_GPIO_G22)
continue;
/* GPG2[0:6] special function 2 */
- s5p_gpio_cfg_pin(&s5pc110_gpio->g2, i, 0x2);
+ gpio_cfg_pin(i, 0x2);
/* GPG2[0:6] pull disable */
- s5p_gpio_set_pull(&s5pc110_gpio->g2, i, GPIO_PULL_NONE);
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
/* GPG2[0:6] drv 4x */
- s5p_gpio_set_drv(&s5pc110_gpio->g2, i, GPIO_DRV_4X);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
ret_sd = s5p_mmc_init(2, 4);
#ifdef CONFIG_SOUND_MAX98095
static void board_enable_audio_codec(void)
{
- struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
- samsung_get_base_gpio_part1();
-
/* Enable MAX98095 Codec */
- s5p_gpio_direction_output(&gpio1->x1, 7, 1);
- s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
+ gpio_direction_output(EXYNOS5_GPIO_X17, 1);
+ gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE);
}
#endif
#ifdef CONFIG_LCD
void exynos_cfg_lcd_gpio(void)
{
- struct exynos5_gpio_part1 *gpio1 =
- (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
-
/* For Backlight */
- s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
- s5p_gpio_set_value(&gpio1->b2, 0, 1);
+ gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT);
+ gpio_set_value(EXYNOS5_GPIO_B20, 1);
/* LCD power on */
- s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
- s5p_gpio_set_value(&gpio1->x1, 5, 1);
+ gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT);
+ gpio_set_value(EXYNOS5_GPIO_X15, 1);
/* Set Hotplug detect for DP */
- s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3));
}
void exynos_set_dp_phy(unsigned int onoff)
#ifdef CONFIG_SOUND_MAX98095
static void board_enable_audio_codec(void)
{
- struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
- samsung_get_base_gpio_part1();
-
/* Enable MAX98095 Codec */
- s5p_gpio_direction_output(&gpio1->x1, 7, 1);
- s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
+ gpio_direction_output(EXYNOS5_GPIO_X17, 1);
+ gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE);
}
#endif
#ifdef CONFIG_LCD
void exynos_cfg_lcd_gpio(void)
{
- struct exynos5_gpio_part1 *gpio1 =
- (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
/* For Backlight */
- s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
- s5p_gpio_set_value(&gpio1->b2, 0, 1);
+ gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT);
+ gpio_set_value(EXYNOS5_GPIO_B20, 1);
/* LCD power on */
- s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
- s5p_gpio_set_value(&gpio1->x1, 5, 1);
+ gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT);
+ gpio_set_value(EXYNOS5_GPIO_X15, 1);
/* Set Hotplug detect for DP */
- s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3));
}
void exynos_set_dp_phy(unsigned int onoff)
#ifdef CONFIG_USB_EHCI_EXYNOS
static int board_usb_vbus_init(void)
{
- struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
- samsung_get_base_gpio_part1();
-
/* Enable VBUS power switch */
- s5p_gpio_direction_output(&gpio1->x2, 6, 1);
+ gpio_direction_output(EXYNOS5420_GPIO_X26, 1);
/* VBUS turn ON time */
mdelay(3);
(struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
/* For Backlight */
- s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
- s5p_gpio_set_value(&gpio1->b2, 0, 1);
+ gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_OUTPUT);
+ gpio_set_value(EXYNOS5420_GPIO_B20, 1);
/* LCD power on */
- s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
- s5p_gpio_set_value(&gpio1->x1, 5, 1);
+ gpio_cfg_pin(EXYNOS5420_GPIO_X15, S5P_GPIO_OUTPUT);
+ gpio_set_value(EXYNOS5420_GPIO_X15, 1);
/* Set Hotplug detect for DP */
- s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_X07, S5P_GPIO_FUNC(0x3));
}
vidinfo_t panel_info = {
{
u32 smc_bw_conf, smc_bc_conf;
- struct s5pc100_gpio *const gpio =
- (struct s5pc100_gpio *)samsung_get_base_gpio();
-
/* gpio configuration GPK0CON */
- s5p_gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
+ gpio_cfg_pin(S5PC100_GPIO_K00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));
/* Ethernet needs bus width of 16 bits */
smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
#include <asm/arch/sromc.h>
DECLARE_GLOBAL_DATA_PTR;
-struct exynos4_gpio_part1 *gpio1;
-struct exynos4_gpio_part2 *gpio2;
static void smc9115_pre_init(void)
{
u32 smc_bw_conf, smc_bc_conf;
/* gpio configuration GPK0CON */
- s5p_gpio_cfg_pin(&gpio2->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
+ gpio_cfg_pin(EXYNOS4_GPIO_Y00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));
/* Ethernet needs bus width of 16 bits */
smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
int board_init(void)
{
- gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
- gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
-
smc9115_pre_init();
gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
* GPK2[2] SD_2_CDn
* GPK2[3:6] SD_2_DATA[0:3](2)
*/
- for (i = 0; i < 7; i++) {
+ for (i = EXYNOS4_GPIO_K20; i < EXYNOS4_GPIO_K27; i++) {
/* GPK2[0:6] special function 2 */
- s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2));
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
/* GPK2[0:6] drv 4x */
- s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
/* GPK2[0:1] pull disable */
- if (i == 0 || i == 1) {
- s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
+ if (i == EXYNOS4_GPIO_K20 || i == EXYNOS4_GPIO_K21) {
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
continue;
}
/* GPK2[2:6] pull up */
- s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP);
+ gpio_set_pull(i, S5P_GPIO_PULL_UP);
}
err = s5p_mmc_init(2, 4);
return err;
void i2c_init_board(void)
{
int err;
- struct exynos4_gpio_part2 *gpio2 =
- (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
/* I2C_5 -> PMIC */
err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE);
}
/* I2C_8 -> FG */
- s5p_gpio_direction_output(&gpio2->y4, 0, 1);
- s5p_gpio_direction_output(&gpio2->y4, 1, 1);
+ gpio_direction_output(EXYNOS4_GPIO_Y40, 1);
+ gpio_direction_output(EXYNOS4_GPIO_Y41, 1);
}
static void trats_low_power_mode(void)
static unsigned int get_hw_revision(void)
{
- struct exynos4_gpio_part1 *gpio =
- (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
int hwrev = 0;
int i;
/* hw_rev[3:0] == GPE1[3:0] */
- for (i = 0; i < 4; i++) {
- s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
- s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
+ for (i = EXYNOS4_GPIO_E10; i < EXYNOS4_GPIO_E14; i++) {
+ gpio_cfg_pin(i, S5P_GPIO_INPUT);
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
}
udelay(1);
for (i = 0; i < 4; i++)
- hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
+ hwrev |= (gpio_get_value(EXYNOS4_GPIO_E10 + i) << i);
debug("hwrev 0x%x\n", hwrev);
static void pmic_reset(void)
{
- struct exynos4_gpio_part2 *gpio =
- (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
-
- s5p_gpio_direction_output(&gpio->x0, 7, 1);
- s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
+ gpio_direction_output(EXYNOS4_GPIO_X07, 1);
+ gpio_set_pull(EXYNOS4_GPIO_X27, S5P_GPIO_PULL_NONE);
}
static void board_clock_init(void)
static void exynos_uart_init(void)
{
- struct exynos4_gpio_part2 *gpio2 =
- (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
-
/* UART_SEL GPY4[7] (part2) at EXYNOS4 */
- s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
- s5p_gpio_direction_output(&gpio2->y4, 7, 1);
+ gpio_set_pull(EXYNOS4_GPIO_Y47, S5P_GPIO_PULL_UP);
+ gpio_direction_output(EXYNOS4_GPIO_Y47, 1);
}
int exynos_early_init_f(void)
void exynos_reset_lcd(void)
{
- struct exynos4_gpio_part2 *gpio2 =
- (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
-
- s5p_gpio_direction_output(&gpio2->y4, 5, 1);
+ gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
udelay(10000);
- s5p_gpio_direction_output(&gpio2->y4, 5, 0);
+ gpio_direction_output(EXYNOS4_GPIO_Y45, 0);
udelay(10000);
- s5p_gpio_direction_output(&gpio2->y4, 5, 1);
+ gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
}
int lcd_power(void)
DECLARE_GLOBAL_DATA_PTR;
-static struct exynos4x12_gpio_part1 *gpio1;
-static struct exynos4x12_gpio_part2 *gpio2;
-
static unsigned int board_rev = -1;
static inline u32 get_model_rev(void);
int modelrev = 0;
int i;
- gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
-
/*
* GPM1[1:0]: MODEL_REV[1:0]
* Don't set as pull-none for these N/C pin.
* TRM say that it may cause unexcepted state and leakage current.
* and pull-none is only for output function.
*/
- for (i = 0; i < 2; i++)
- s5p_gpio_cfg_pin(&gpio2->m1, i, GPIO_INPUT);
+ for (i = EXYNOS4X12_GPIO_M10; i < EXYNOS4X12_GPIO_M12; i++)
+ gpio_cfg_pin(i, S5P_GPIO_INPUT);
/* GPM1[5:2]: HW_REV[3:0] */
- for (i = 2; i < 6; i++) {
- s5p_gpio_cfg_pin(&gpio2->m1, i, GPIO_INPUT);
- s5p_gpio_set_pull(&gpio2->m1, i, GPIO_PULL_NONE);
+ for (i = EXYNOS4X12_GPIO_M12; i < EXYNOS4X12_GPIO_M16; i++) {
+ gpio_cfg_pin(i, S5P_GPIO_INPUT);
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
}
/* GPM1[1:0]: MODEL_REV[1:0] */
for (i = 0; i < 2; i++)
- modelrev |= (s5p_gpio_get_value(&gpio2->m1, i) << i);
+ modelrev |= (gpio_get_value(EXYNOS4X12_GPIO_M10 + i) << i);
/* board_rev[15:8] = model */
board_rev = modelrev << 8;
static void board_external_gpio_init(void)
{
- gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
-
/*
* some pins which in alive block are connected with external pull-up
* but it's default setting is pull-down.
* if that pin set as input then that floated
*/
- s5p_gpio_set_pull(&gpio2->x0, 2, GPIO_PULL_NONE); /* PS_ALS_INT */
- s5p_gpio_set_pull(&gpio2->x0, 4, GPIO_PULL_NONE); /* TSP_nINT */
- s5p_gpio_set_pull(&gpio2->x0, 7, GPIO_PULL_NONE); /* AP_PMIC_IRQ*/
- s5p_gpio_set_pull(&gpio2->x1, 5, GPIO_PULL_NONE); /* IF_PMIC_IRQ*/
- s5p_gpio_set_pull(&gpio2->x2, 0, GPIO_PULL_NONE); /* VOL_UP */
- s5p_gpio_set_pull(&gpio2->x2, 1, GPIO_PULL_NONE); /* VOL_DOWN */
- s5p_gpio_set_pull(&gpio2->x2, 3, GPIO_PULL_NONE); /* FUEL_ALERT */
- s5p_gpio_set_pull(&gpio2->x2, 4, GPIO_PULL_NONE); /* ADC_INT */
- s5p_gpio_set_pull(&gpio2->x2, 7, GPIO_PULL_NONE); /* nPOWER */
- s5p_gpio_set_pull(&gpio2->x3, 0, GPIO_PULL_NONE); /* WPC_INT */
- s5p_gpio_set_pull(&gpio2->x3, 5, GPIO_PULL_NONE); /* OK_KEY */
- s5p_gpio_set_pull(&gpio2->x3, 7, GPIO_PULL_NONE); /* HDMI_HPD */
+ gpio_set_pull(EXYNOS4X12_GPIO_X02, S5P_GPIO_PULL_NONE); /* PS_ALS_INT */
+ gpio_set_pull(EXYNOS4X12_GPIO_X04, S5P_GPIO_PULL_NONE); /* TSP_nINT */
+ gpio_set_pull(EXYNOS4X12_GPIO_X07, S5P_GPIO_PULL_NONE); /* AP_PMIC_IRQ*/
+ gpio_set_pull(EXYNOS4X12_GPIO_X15, S5P_GPIO_PULL_NONE); /* IF_PMIC_IRQ*/
+ gpio_set_pull(EXYNOS4X12_GPIO_X20, S5P_GPIO_PULL_NONE); /* VOL_UP */
+ gpio_set_pull(EXYNOS4X12_GPIO_X21, S5P_GPIO_PULL_NONE); /* VOL_DOWN */
+ gpio_set_pull(EXYNOS4X12_GPIO_X23, S5P_GPIO_PULL_NONE); /* FUEL_ALERT */
+ gpio_set_pull(EXYNOS4X12_GPIO_X24, S5P_GPIO_PULL_NONE); /* ADC_INT */
+ gpio_set_pull(EXYNOS4X12_GPIO_X27, S5P_GPIO_PULL_NONE); /* nPOWER */
+ gpio_set_pull(EXYNOS4X12_GPIO_X30, S5P_GPIO_PULL_NONE); /* WPC_INT */
+ gpio_set_pull(EXYNOS4X12_GPIO_X35, S5P_GPIO_PULL_NONE); /* OK_KEY */
+ gpio_set_pull(EXYNOS4X12_GPIO_X37, S5P_GPIO_PULL_NONE); /* HDMI_HPD */
}
#ifdef CONFIG_SYS_I2C_INIT_BOARD
{
int err;
- gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1();
- gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
-
/* I2C_7 */
err = exynos_pinmux_config(PERIPH_ID_I2C7, PINMUX_FLAG_NONE);
if (err) {
}
/* I2C_8 */
- s5p_gpio_direction_output(&gpio1->f1, 4, 1);
- s5p_gpio_direction_output(&gpio1->f1, 5, 1);
+ gpio_direction_output(EXYNOS4X12_GPIO_F14, 1);
+ gpio_direction_output(EXYNOS4X12_GPIO_F15, 1);
/* I2C_9 */
- s5p_gpio_direction_output(&gpio2->m2, 1, 1);
- s5p_gpio_direction_output(&gpio2->m2, 0, 1);
+ gpio_direction_output(EXYNOS4X12_GPIO_M21, 1);
+ gpio_direction_output(EXYNOS4X12_GPIO_M20, 1);
}
#endif
int get_soft_i2c_scl_pin(void)
{
if (I2C_ADAP_HWNR)
- return exynos4x12_gpio_get(2, m2, 1); /* I2C9 */
+ return EXYNOS4X12_GPIO_M21; /* I2C9 */
else
- return exynos4x12_gpio_get(1, f1, 4); /* I2C8 */
+ return EXYNOS4X12_GPIO_F14; /* I2C8 */
}
int get_soft_i2c_sda_pin(void)
{
if (I2C_ADAP_HWNR)
- return exynos4x12_gpio_get(2, m2, 0); /* I2C9 */
+ return EXYNOS4X12_GPIO_M20; /* I2C9 */
else
- return exynos4x12_gpio_get(1, f1, 5); /* I2C8 */
+ return EXYNOS4X12_GPIO_F15; /* I2C8 */
}
#endif
{
struct pmic *p = pmic_get("MAX77686_PMIC");
- gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1();
-
/* LCD_2.2V_EN: GPC0[1] */
- s5p_gpio_set_pull(&gpio1->c0, 1, GPIO_PULL_UP);
- s5p_gpio_direction_output(&gpio1->c0, 1, 1);
+ gpio_set_pull(EXYNOS4X12_GPIO_C01, S5P_GPIO_PULL_UP);
+ gpio_direction_output(EXYNOS4X12_GPIO_C01, 1);
/* LDO25 VCC_3.1V_LCD */
pmic_probe(p);
void exynos_reset_lcd(void)
{
- gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1();
-
/* reset lcd */
- s5p_gpio_direction_output(&gpio1->f2, 1, 0);
+ gpio_direction_output(EXYNOS4X12_GPIO_F21, 0);
udelay(10);
- s5p_gpio_set_value(&gpio1->f2, 1, 1);
+ gpio_set_value(EXYNOS4X12_GPIO_F21, 1);
}
void exynos_lcd_misc_init(vidinfo_t *vid)
DECLARE_GLOBAL_DATA_PTR;
-struct exynos4_gpio_part1 *gpio1;
-struct exynos4_gpio_part2 *gpio2;
unsigned int board_rev;
u32 get_board_rev(void)
for (i = 0; i < 8; i++) {
/* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
- s5p_gpio_cfg_pin(&gpio1->f0, i, GPIO_FUNC(2));
- s5p_gpio_cfg_pin(&gpio1->f1, i, GPIO_FUNC(2));
- s5p_gpio_cfg_pin(&gpio1->f2, i, GPIO_FUNC(2));
+ gpio_cfg_pin(EXYNOS4_GPIO_F00 + i, S5P_GPIO_FUNC(2));
+ gpio_cfg_pin(EXYNOS4_GPIO_F10 + i, S5P_GPIO_FUNC(2));
+ gpio_cfg_pin(EXYNOS4_GPIO_F20 + i, S5P_GPIO_FUNC(2));
/* pull-up/down disable */
- s5p_gpio_set_pull(&gpio1->f0, i, GPIO_PULL_NONE);
- s5p_gpio_set_pull(&gpio1->f1, i, GPIO_PULL_NONE);
- s5p_gpio_set_pull(&gpio1->f2, i, GPIO_PULL_NONE);
+ gpio_set_pull(EXYNOS4_GPIO_F00 + i, S5P_GPIO_PULL_NONE);
+ gpio_set_pull(EXYNOS4_GPIO_F10 + i, S5P_GPIO_PULL_NONE);
+ gpio_set_pull(EXYNOS4_GPIO_F20 + i, S5P_GPIO_PULL_NONE);
/* drive strength to max (24bit) */
- s5p_gpio_set_drv(&gpio1->f0, i, GPIO_DRV_4X);
- s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
- s5p_gpio_set_drv(&gpio1->f1, i, GPIO_DRV_4X);
- s5p_gpio_set_rate(&gpio1->f1, i, GPIO_DRV_SLOW);
- s5p_gpio_set_drv(&gpio1->f2, i, GPIO_DRV_4X);
- s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
+ gpio_set_drv(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_4X);
+ gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW);
+ gpio_set_drv(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_4X);
+ gpio_set_rate(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_SLOW);
+ gpio_set_drv(EXYNOS4_GPIO_F20 + i, S5P_GPIO_DRV_4X);
+ gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW);
}
- for (i = 0; i < f3_end; i++) {
+ for (i = EXYNOS4_GPIO_F30; i < (EXYNOS4_GPIO_F30 + f3_end); i++) {
/* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
- s5p_gpio_cfg_pin(&gpio1->f3, i, GPIO_FUNC(2));
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(2));
/* pull-up/down disable */
- s5p_gpio_set_pull(&gpio1->f3, i, GPIO_PULL_NONE);
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
/* drive strength to max (24bit) */
- s5p_gpio_set_drv(&gpio1->f3, i, GPIO_DRV_4X);
- s5p_gpio_set_rate(&gpio1->f3, i, GPIO_DRV_SLOW);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
+ gpio_set_rate(i, S5P_GPIO_DRV_SLOW);
}
/* gpio pad configuration for LCD reset. */
- s5p_gpio_cfg_pin(&gpio2->y4, 5, GPIO_OUTPUT);
+ gpio_cfg_pin(EXYNOS4_GPIO_Y45, S5P_GPIO_OUTPUT);
spi_init();
}
void exynos_reset_lcd(void)
{
- s5p_gpio_set_value(&gpio2->y4, 5, 1);
+ gpio_set_value(EXYNOS4_GPIO_Y45, 1);
udelay(10000);
- s5p_gpio_set_value(&gpio2->y4, 5, 0);
+ gpio_set_value(EXYNOS4_GPIO_Y45, 0);
udelay(10000);
- s5p_gpio_set_value(&gpio2->y4, 5, 1);
+ gpio_set_value(EXYNOS4_GPIO_Y45, 1);
udelay(100);
}
int exynos_init(void)
{
- gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
- gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
-
gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
switch (get_hwrev()) {
* you should set it HIGH since it removes the inverter
*/
/* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */
- s5p_gpio_direction_output(&gpio1->e3, 6, 0);
+ gpio_direction_output(EXYNOS4_GPIO_E36, 0);
break;
default:
/*
* But set it as HIGH to ensure
*/
/* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */
- s5p_gpio_direction_output(&gpio1->e1, 3, 1);
+ gpio_direction_output(EXYNOS4_GPIO_E13, 1);
break;
}
--- /dev/null
+#
+# Copyright (c) 2011 The Chromium OS Authors.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := sandbox.o
button = 0;
gpio_free(gpio);
- if (!button) {
- /* LED0 - RED=1: GPIO2_0 2*32 = 64 */
- gpio_request(BOARD_DFU_BUTTON_LED, "");
- gpio_direction_output(BOARD_DFU_BUTTON_LED, 1);
- gpio_set_value(BOARD_DFU_BUTTON_LED, 1);
- }
return button;
}
""
);
#endif
+/*
+ * This command sets led
+ * Input - name of led
+ * value of led
+ * Returns - 1 if input does not match
+ * 0 if led was set
+ */
+static int
+do_setled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int gpio = 0;
+ if (argc != 3)
+ goto exit;
+#if defined(BOARD_STATUS_LED)
+ if (!strcmp(argv[1], "stat"))
+ gpio = BOARD_STATUS_LED;
+#endif
+#if defined(BOARD_DFU_BUTTON_LED)
+ if (!strcmp(argv[1], "dfu"))
+ gpio = BOARD_DFU_BUTTON_LED;
+#endif
+ /* If argument does not mach exit */
+ if (gpio == 0)
+ goto exit;
+ gpio_request(gpio, "");
+ gpio_direction_output(gpio, 1);
+ if (!strcmp(argv[2], "1"))
+ gpio_set_value(gpio, 1);
+ else
+ gpio_set_value(gpio, 0);
+ return 0;
+exit:
+ return 1;
+}
+
+U_BOOT_CMD(
+ led, CONFIG_SYS_MAXARGS, 2, do_setled,
+ "Set led on or off",
+ "dfu val - set dfu led\nled stat val - set status led"
+);
static int
do_usertestwdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
/*
- * Board functions for TI AM335X based dxr2 board
+ * Board functions for TI AM335X based draco board
* (C) Copyright 2013 Siemens Schweiz AG
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SPL_BUILD
-static struct dxr2_baseboard_id __attribute__((section(".data"))) settings;
-/* @303MHz-i0 */
+static struct draco_baseboard_id __attribute__((section(".data"))) settings;
+
+#if DDR_PLL_FREQ == 303
+/* Default@303MHz-i0 */
+const struct ddr3_data ddr3_default = {
+ 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
+ 0x0079, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32,
+ 0x0000093B, 0x0000014A,
+ "default name @303MHz \0",
+ "default marking \0",
+};
+#elif DDR_PLL_FREQ == 400
+/* Default@400MHz-i0 */
const struct ddr3_data ddr3_default = {
- 0x33524444, 0x56312e34, 0x0080, 0x0000, 0x0038, 0x003E, 0x00A4,
- 0x0075, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32,
+ 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab,
+ 0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232,
0x00000618, 0x0000014A,
+ "default name @400MHz \0",
+ "default marking \0",
};
+#endif
static void set_default_ddr3_timings(void)
{
static void print_ddr3_timings(void)
{
- printf("\n\nDDR3 Timing parameters:\n");
- printf("Diff Eeprom Default\n");
+ printf("\nDDR3\n");
+ printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
+ printf("device:\t\t%s\n", settings.ddr3.manu_name);
+ printf("marking:\t%s\n", settings.ddr3.manu_marking);
+ printf("timing parameters\n");
+ printf("diff\teeprom\tdefault\n");
PRINTARGS(magic);
PRINTARGS(version);
PRINTARGS(ddr3_sratio);
static void print_chip_data(void)
{
- printf("\n");
- printf("Device: '%s'\n", settings.chip.sdevname);
- printf("HW version: '%s'\n", settings.chip.shwver);
+ printf("\nCPU BOARD\n");
+ printf("device: \t'%s'\n", settings.chip.sdevname);
+ printf("hw version: \t'%s'\n", settings.chip.shwver);
}
#endif /* CONFIG_SPL_BUILD */
printf("Using DDR3 settings from EEPROM\n");
} else {
if (ddr3_default.magic != settings.ddr3.magic)
- printf("Error: No valid DDR3 data in eeprom.\n");
+ printf("Warning: No valid DDR3 data in eeprom.\n");
if (ddr3_default.version != settings.ddr3.version)
- printf("Error: DDR3 data version does not match.\n");
+ printf("Warning: DDR3 data version does not match.\n");
printf("Using default settings\n");
set_default_ddr3_timings();
}
- if (MAGIC_CHIP == settings.chip.magic) {
- printf("Valid chip data in eeprom\n");
+ if (MAGIC_CHIP == settings.chip.magic)
print_chip_data();
- } else {
- printf("Error: No chip data in eeprom\n");
- }
+ else
+ printf("Warning: No chip data in eeprom\n");
print_ddr3_timings();
#endif
#ifdef CONFIG_SPL_BUILD
static void board_init_ddr(void)
{
-struct emif_regs dxr2_ddr3_emif_reg_data = {
+struct emif_regs draco_ddr3_emif_reg_data = {
.zq_config = 0x50074BE4,
};
-struct ddr_data dxr2_ddr3_data = {
+struct ddr_data draco_ddr3_data = {
};
-struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
+struct cmd_control draco_ddr3_cmd_ctrl_data = {
};
-struct ctrl_ioregs dxr2_ddr3_ioregs = {
+struct ctrl_ioregs draco_ddr3_ioregs = {
};
/* pass values from eeprom */
- dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
- dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
- dxr2_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
- dxr2_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
+ draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
+ draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
+ draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
+ draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
settings.ddr3.emif_ddr_phy_ctlr_1;
- dxr2_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
- dxr2_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
-
- dxr2_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
- dxr2_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
- dxr2_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
- dxr2_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
-
- dxr2_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
- dxr2_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
- dxr2_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
- dxr2_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
- dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
- dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
-
- dxr2_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
- dxr2_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
- dxr2_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
- dxr2_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
- dxr2_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
-
- config_ddr(DDR_PLL_FREQ, &dxr2_ddr3_ioregs, &dxr2_ddr3_data,
- &dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0);
+ draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
+ draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
+
+ draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
+ draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
+ draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
+ draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
+
+ draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
+ draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
+ draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
+ draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
+ draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
+ draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
+
+ draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
+ draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
+ draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
+ draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
+ draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
+
+ config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
+ &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
}
static void spl_siemens_board_init(void)
#define MAGIC_CHIP 0x50494843
/* Automatic generated definition */
-/* Wed, 18 Sep 2013 18:58:27 +0200 */
-/* From file: draco/ddr3-data-micron-v2.txt */
+/* Wed, 16 Apr 2014 16:50:41 +0200 */
+/* From file: draco/ddr3-data-universal-default@303MHz-i0-ES3.txt */
struct ddr3_data {
unsigned int magic; /* 0x33524444 */
- unsigned int version; /* 0x56312e34 */
- unsigned short int ddr3_sratio; /* 0x0100 */
- unsigned short int iclkout; /* 0x0001 */
+ unsigned int version; /* 0x56312e35 */
+ unsigned short int ddr3_sratio; /* 0x0080 */
+ unsigned short int iclkout; /* 0x0000 */
unsigned short int dt0rdsratio0; /* 0x003A */
- unsigned short int dt0wdsratio0; /* 0x008A */
- unsigned short int dt0fwsratio0; /* 0x010B */
- unsigned short int dt0wrsratio0; /* 0x00C4 */
+ unsigned short int dt0wdsratio0; /* 0x003F */
+ unsigned short int dt0fwsratio0; /* 0x009F */
+ unsigned short int dt0wrsratio0; /* 0x0079 */
unsigned int sdram_tim1; /* 0x0888A39B */
unsigned int sdram_tim2; /* 0x26247FDA */
unsigned int sdram_tim3; /* 0x501F821F */
unsigned int emif_ddr_phy_ctlr_1; /* 0x00100206 */
- unsigned int sdram_config; /* 0x61C04AB2 */
- unsigned int ref_ctrl; /* 0x00000618 */
- unsigned int ioctr_val; /* 0x0000018B */
+ unsigned int sdram_config; /* 0x61A44A32 */
+ unsigned int ref_ctrl; /* 0x0000093B */
+ unsigned int ioctr_val; /* 0x0000014A */
+ char manu_name[32]; /* "default@303MHz \0" */
+ char manu_marking[32]; /* "default \0" */
};
struct chip_data {
char shwver[7];
};
-struct dxr2_baseboard_id {
+struct draco_baseboard_id {
struct ddr3_data ddr3;
struct chip_data chip;
};
/*
- * pinmux setup for siemens dxr2 board
+ * pinmux setup for siemens draco board
*
* (C) Copyright 2013 Siemens Schweiz AG
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
};
const struct ctrl_ioregs ioregs = {
- .cm0ioctl = DXR2_IOCTRL_VAL,
- .cm1ioctl = DXR2_IOCTRL_VAL,
- .cm2ioctl = DXR2_IOCTRL_VAL,
- .dt0ioctl = DXR2_IOCTRL_VAL,
- .dt1ioctl = DXR2_IOCTRL_VAL,
+ .cm0ioctl = DDR_IOCTRL_VAL,
+ .cm1ioctl = DDR_IOCTRL_VAL,
+ .cm2ioctl = DDR_IOCTRL_VAL,
+ .dt0ioctl = DDR_IOCTRL_VAL,
+ .dt1ioctl = DDR_IOCTRL_VAL,
};
config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data,
#if defined(DISPL_PLL_SPREAD_SPECTRUM)
writel(0x64, &cmwkup->resv6[3]); /* 0x50 */
writel(0x800, &cmwkup->resv6[2]); /* 0x4c */
- writel(readl(&cmwkup->clkmoddplldisp) | (1 << 12),
+ writel(readl(&cmwkup->clkmoddplldisp) | CM_CLKMODE_DPLL_SSC_EN_MASK,
&cmwkup->clkmoddplldisp); /* 0x98 */
#endif
return 0;
.text :
{
*(.__image_copy_start)
+ *(.vectors)
CPUDIR/start.o (.text*)
board/ti/am335x/built-in.o (.text*)
*(.text*)
/*
* Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2014 O.S. Systems Software LTDA.
*
* Author: Fabio Estevam <fabio.estevam@freescale.com>
*
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/video.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
#include <fsl_esdhc.h>
-#include <ipu_pixfmt.h>
#include <mmc.h>
#include <miiphy.h>
#include <netdev.h>
-#include <linux/fb.h>
#include <phy.h>
#include <input.h>
+#include <i2c.h>
DECLARE_GLOBAL_DATA_PTR;
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2)
#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9)
#define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
}
#if defined(CONFIG_VIDEO_IPUV3)
-static struct fb_videomode const hdmi = {
- .name = "HDMI",
- .refresh = 60,
- .xres = 1024,
- .yres = 768,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
+struct i2c_pads_info i2c2_pad_info = {
+ .scl = {
+ .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(4, 13)
+ }
};
-int board_video_skip(void)
-{
- int ret;
+static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSync */
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSync */
+ MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04
+ | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm), /* Contrast */
+ MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* DISP0_DRDY */
+
+ MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
+ MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
+ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
+ MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
+ MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
+ MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
+ MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
+ MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
+ MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
+ MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
+ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
+ MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
+ MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
+ MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
+ MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
+ MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
+ MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
+ MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
+
+ MX6_PAD_SD4_DAT2__GPIO2_IO10
+ | MUX_PAD_CTRL(NO_PAD_CTRL), /* DISP0_BKLEN */
+ MX6_PAD_SD4_DAT3__GPIO2_IO11
+ | MUX_PAD_CTRL(NO_PAD_CTRL), /* DISP0_VDDEN */
+};
- ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24);
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+ imx_enable_hdmi_phy();
+}
- if (ret) {
- printf("HDMI cannot be configured: %d\n", ret);
- return ret;
- }
+static int detect_i2c(struct display_info_t const *dev)
+{
+ return (0 == i2c_set_bus_num(dev->bus)) &&
+ (0 == i2c_probe(dev->addr));
+}
- imx_enable_hdmi_phy();
+static void enable_fwadapt_7wvga(struct display_info_t const *dev)
+{
+ imx_iomux_v3_setup_multiple_pads(
+ fwadapt_7wvga_pads,
+ ARRAY_SIZE(fwadapt_7wvga_pads));
- return ret;
+ gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
+ gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
}
+struct display_info_t const displays[] = {{
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = do_enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = 1,
+ .addr = 0x10,
+ .pixfmt = IPU_PIX_FMT_RGB666,
+ .detect = detect_i2c,
+ .enable = enable_fwadapt_7wvga,
+ .mode = {
+ .name = "FWBADAPT-LCD-F07A-0102",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 33260,
+ .left_margin = 128,
+ .right_margin = 128,
+ .upper_margin = 22,
+ .lower_margin = 22,
+ .hsync_len = 1,
+ .vsync_len = 1,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
static void setup_display(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->chsccdr);
+
+ /* Disable LCD backlight */
+ imx_iomux_v3_setup_pad(MX6_PAD_DI0_PIN4__GPIO4_IO20);
+ gpio_direction_input(IMX_GPIO_NR(4, 20));
}
#endif /* CONFIG_VIDEO_IPUV3 */
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c2_pad_info);
+
return 0;
}
Active arm armv7 am33xx BuR tseries tseries_nand tseries:SERIAL1,CONS_INDEX=1,NAND Hannes Petermaier <hannes.petermaier@br-automation.com>
Active arm armv7 am33xx BuR tseries tseries_spi tseries:SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT Hannes Petermaier <hannes.petermaier@br-automation.com>
Active arm armv7 am33xx compulab cm_t335 cm_t335 - Igor Grinberg <grinberg@compulab.co.il>
+Active arm armv7 am33xx gumstix pepper pepper - Ash Charles <ash@gumstix.com>
Active arm armv7 am33xx isee igep0033 am335x_igep0033 - Enric Balletbo i Serra <eballetbo@iseebcn.com>
Active arm armv7 am33xx phytec pcm051 pcm051_rev1 pcm051:REV1 Lars Poeschel <poeschel@lemonage.de>
Active arm armv7 am33xx phytec pcm051 pcm051_rev3 pcm051:REV3 Lars Poeschel <poeschel@lemonage.de>
-Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier <r.meier@siemens.com>
+Active arm armv7 am33xx siemens draco draco - Roger Meier <r.meier@siemens.com>
+Active arm armv7 am33xx siemens draco dxr2 - Roger Meier <r.meier@siemens.com>
Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier <r.meier@siemens.com>
Active arm armv7 am33xx siemens rut rut - Roger Meier <r.meier@siemens.com>
Active arm armv7 am33xx silica pengwyn pengwyn - Lothar Felten <lothar.felten@gmail.com>
Active arm armv7 mx6 boundary nitrogen6x nitrogen6s nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Eric Nelson <eric.nelson@boundarydevices.com>
Active arm armv7 mx6 boundary nitrogen6x nitrogen6s1g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com>
Active arm armv7 mx6 congatec cgtqmx6eval cgtqmx6qeval cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Leo Sartre <lsartre@adeneo-embedded.com>
+Active arm armv7 mx6 embest mx6boards marsboard embestmx6boards:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,ENV_IS_IN_SPI_FLASH Eric Bénard <eric@eukrea.com>
+Active arm armv7 mx6 embest mx6boards riotboard embestmx6boards:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024,ENV_IS_IN_MMC Eric Bénard <eric@eukrea.com>
Active arm armv7 mx6 freescale mx6qarm2 mx6qarm2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg Jason Liu <r64343@freescale.com>
Active arm armv7 mx6 freescale mx6qsabreauto mx6qsabreauto mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 rmobile renesas koelsch koelsch_nor koelsch:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
-Active arm armv7 s5pc1xx samsung goni s5p_goni - Mateusz Zalega <m.zalega@samsung.com>
+Active arm armv7 s5pc1xx samsung goni s5p_goni - Przemyslaw Marczak <p.marczak@samsung.com>
Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com>
Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - -
Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier@linaro.org>
Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS - -
Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_ATM MPC8569MDS:ATM -
Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_NAND MPC8569MDS:NAND -
-Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS - -
-Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_36BIT MPC8572DS:36BIT -
+Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS - York Sun <yorksun@freescale.com>
+Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_36BIT MPC8572DS:36BIT York Sun <yorksun@freescale.com>
Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_NAND MPC8572DS:NAND -
Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND P1010RDB:P1010RDB_PA,36BIT,NAND -
Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB:P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT -
Active powerpc mpc85xx - freescale t208xrdb T2080RDB T208xRDB:PPC_T2080 -
Active powerpc mpc85xx - freescale t208xrdb T2080RDB_NAND T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND -
Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SDCARD T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD -
+Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SECURE_BOOT T208xRDB:PPC_T2080,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SPIFLASH T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH -
Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SRIO_PCIE_BOOT T208xRDB:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 -
Active powerpc mpc85xx - freescale t4qds T4240QDS_SECURE_BOOT T4240QDS:PPC_T4240,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t4rdb T4160RDB T4240RDB:PPC_T4160 Chunhe Lan <Chunhe.Lan@freescale.com>
+Active powerpc mpc85xx - freescale t4rdb T4240RDB T4240RDB:PPC_T4240 Chunhe Lan <Chunhe.Lan@freescale.com>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach <eibach@gdsys.de>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach <eibach@gdsys.de>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach <eibach@gdsys.de>
Active powerpc ppc4xx - xilinx ppc405-generic xilinx-ppc405-generic_flash xilinx-ppc405-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda <ricardo.ribalda@uam.es>
Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1 Ricardo Ribalda <ricardo.ribalda@uam.es>
Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic_flash xilinx-ppc440-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda <ricardo.ribalda@uam.es>
-Active sandbox sandbox - - <none> sandbox - Simon Glass <sjg@chromium.org>
+Active sandbox sandbox - - sandbox sandbox - Simon Glass <sjg@chromium.org>
Active sh sh2 - renesas rsk7203 rsk7203 - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Active sh sh2 - renesas rsk7264 rsk7264 - Phil Edworthy <phil.edworthy@renesas.com>
Active sh sh2 - renesas rsk7269 rsk7269 - -
obj-y += usb.o usb_hub.o
obj-$(CONFIG_USB_STORAGE) += usb_storage.o
endif
+obj-$(CONFIG_CMD_FASTBOOT) += cmd_fastboot.o
+
obj-$(CONFIG_CMD_USB_MASS_STORAGE) += cmd_usb_mass_storage.o
obj-$(CONFIG_CMD_THOR_DOWNLOAD) += cmd_thordown.o
obj-$(CONFIG_CMD_XIMG) += cmd_ximg.o
obj-$(CONFIG_CROS_EC) += cros_ec.o
obj-y += dlmalloc.o
obj-y += image.o
+obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o
obj-$(CONFIG_OF_LIBFDT) += image-fdt.o
obj-$(CONFIG_FIT) += image-fit.o
obj-$(CONFIG_FIT_SIGNATURE) += image-sig.o
char * const argv[])
{
const void *os_hdr;
+ bool ep_found = false;
/* get kernel image header, start address and length */
os_hdr = boot_get_kernel(cmdtp, flag, argc, argv,
return 1;
}
break;
+#endif
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+ case IMAGE_FORMAT_ANDROID:
+ images.os.type = IH_TYPE_KERNEL;
+ images.os.comp = IH_COMP_NONE;
+ images.os.os = IH_OS_LINUX;
+ images.ep = images.os.load;
+ ep_found = true;
+
+ images.os.end = android_image_get_end(os_hdr);
+ images.os.load = android_image_get_kload(os_hdr);
+ break;
#endif
default:
puts("ERROR: unknown image format type!\n");
return 1;
}
#endif
- } else {
+ } else if (!ep_found) {
puts("Could not find kernel entry point!\n");
return 1;
}
images->fit_uname_cfg = fit_uname_config;
images->fit_noffset_os = os_noffset;
break;
+#endif
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+ case IMAGE_FORMAT_ANDROID:
+ printf("## Booting Android Image at 0x%08lx ...\n", img_addr);
+ if (android_image_get_kernel((void *)img_addr, images->verify,
+ os_data, os_len))
+ return NULL;
+ break;
#endif
default:
printf("Wrong Image Format for %s command\n", cmdtp->name);
--- /dev/null
+/*
+ * Copyright 2008 - 2009 Windriver, <www.windriver.com>
+ * Author: Tom Rix <Tom.Rix@windriver.com>
+ *
+ * (C) Copyright 2014 Linaro, Ltd.
+ * Rob Herring <robh@kernel.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <command.h>
+#include <g_dnl.h>
+
+static int do_fastboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ int ret;
+
+ ret = g_dnl_register("usb_dnl_fastboot");
+ if (ret)
+ return ret;
+
+ while (1) {
+ if (ctrlc())
+ break;
+ usb_gadget_handle_interrupts();
+ }
+
+ g_dnl_unregister();
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+ fastboot, 1, 1, do_fastboot,
+ "fastboot - enter USB Fastboot protocol",
+ ""
+);
#include <common.h>
#include <command.h>
#include <fpga.h>
+#include <fs.h>
#include <malloc.h>
/* Local functions */
#define FPGA_LOADB 2
#define FPGA_DUMP 3
#define FPGA_LOADMK 4
+#define FPGA_LOADP 5
+#define FPGA_LOADBP 6
+#define FPGA_LOADFS 7
/* ------------------------------------------------------------------------- */
/* command form:
const char *fit_uname = NULL;
ulong fit_addr;
#endif
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+ fpga_fs_info fpga_fsinfo;
+ fpga_fsinfo.fstype = FS_TYPE_ANY;
+#endif
if (devstr)
dev = (int) simple_strtoul(devstr, NULL, 16);
fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
switch (argc) {
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+ case 9:
+ fpga_fsinfo.blocksize = (unsigned int)
+ simple_strtoul(argv[5], NULL, 16);
+ fpga_fsinfo.interface = argv[6];
+ fpga_fsinfo.dev_part = argv[7];
+ fpga_fsinfo.filename = argv[8];
+#endif
case 5: /* fpga <op> <dev> <data> <datasize> */
data_size = simple_strtoul(argv[4], NULL, 16);
case FPGA_NONE:
case FPGA_INFO:
break;
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+ case FPGA_LOADFS:
+ /* Blocksize can be zero */
+ if (!fpga_fsinfo.interface || !fpga_fsinfo.dev_part ||
+ !fpga_fsinfo.filename)
+ wrong_parms = 1;
+#endif
case FPGA_LOAD:
+ case FPGA_LOADP:
case FPGA_LOADB:
+ case FPGA_LOADBP:
case FPGA_DUMP:
if (!fpga_data || !data_size)
wrong_parms = 1;
break;
+#if defined(CONFIG_CMD_FPGA_LOADMK)
case FPGA_LOADMK:
if (!fpga_data)
wrong_parms = 1;
break;
+#endif
}
if (wrong_parms) {
break;
case FPGA_LOAD:
- rc = fpga_load(dev, fpga_data, data_size);
+ rc = fpga_load(dev, fpga_data, data_size, BIT_FULL);
+ break;
+
+#if defined(CONFIG_CMD_FPGA_LOADP)
+ case FPGA_LOADP:
+ rc = fpga_load(dev, fpga_data, data_size, BIT_PARTIAL);
break;
+#endif
case FPGA_LOADB:
- rc = fpga_loadbitstream(dev, fpga_data, data_size);
+ rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_FULL);
+ break;
+
+#if defined(CONFIG_CMD_FPGA_LOADBP)
+ case FPGA_LOADBP:
+ rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_PARTIAL);
+ break;
+#endif
+
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+ case FPGA_LOADFS:
+ rc = fpga_fsload(dev, fpga_data, data_size, &fpga_fsinfo);
break;
+#endif
+#if defined(CONFIG_CMD_FPGA_LOADMK)
case FPGA_LOADMK:
switch (genimg_get_format(fpga_data)) {
case IMAGE_FORMAT_LEGACY:
data = (ulong)image_get_data(hdr);
data_size = image_get_data_size(hdr);
}
- rc = fpga_load(dev, (void *)data, data_size);
+ rc = fpga_load(dev, (void *)data, data_size,
+ BIT_FULL);
}
break;
#if defined(CONFIG_FIT)
return 1;
}
- rc = fpga_load(dev, fit_data, data_size);
+ rc = fpga_load(dev, fit_data, data_size,
+ BIT_FULL);
}
break;
#endif
break;
}
break;
+#endif
case FPGA_DUMP:
rc = fpga_dump(dev, fpga_data, data_size);
op = FPGA_LOADB;
else if (!strcmp("load", opstr))
op = FPGA_LOAD;
+#if defined(CONFIG_CMD_FPGA_LOADP)
+ else if (!strcmp("loadp", opstr))
+ op = FPGA_LOADP;
+#endif
+#if defined(CONFIG_CMD_FPGA_LOADBP)
+ else if (!strcmp("loadbp", opstr))
+ op = FPGA_LOADBP;
+#endif
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+ else if (!strcmp("loadfs", opstr))
+ op = FPGA_LOADFS;
+#endif
+#if defined(CONFIG_CMD_FPGA_LOADMK)
else if (!strcmp("loadmk", opstr))
op = FPGA_LOADMK;
+#endif
else if (!strcmp("dump", opstr))
op = FPGA_DUMP;
return op;
}
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+U_BOOT_CMD(fpga, 9, 1, do_fpga,
+#else
U_BOOT_CMD(fpga, 6, 1, do_fpga,
+#endif
"loadable FPGA image support",
"[operation type] [device number] [image address] [image size]\n"
"fpga operations:\n"
" dump\t[dev]\t\t\tLoad device to memory buffer\n"
" info\t[dev]\t\t\tlist known device information\n"
" load\t[dev] [address] [size]\tLoad device from memory buffer\n"
+#if defined(CONFIG_CMD_FPGA_LOADP)
+ " loadp\t[dev] [address] [size]\t"
+ "Load device from memory buffer with partial bitstream\n"
+#endif
" loadb\t[dev] [address] [size]\t"
"Load device from bitstream buffer (Xilinx only)\n"
+#if defined(CONFIG_CMD_FPGA_LOADBP)
+ " loadbp\t[dev] [address] [size]\t"
+ "Load device from bitstream buffer with partial bitstream"
+ "(Xilinx only)\n"
+#endif
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+ "Load device from filesystem (FAT by default) (Xilinx only)\n"
+ " loadfs [dev] [address] [image size] [blocksize] <interface>\n"
+ " [<dev[:part]>] <filename>\n"
+#endif
+#if defined(CONFIG_CMD_FPGA_LOADMK)
" loadmk [dev] [address]\tLoad device generated with mkimage"
#if defined(CONFIG_FIT)
"\n"
"\tFor loadmk operating on FIT format uImage address must include\n"
"\tsubimage unit name in the form of addr:<subimg_uname>"
#endif
+#endif
);
"what you are doing!\n"
"\nReally perform this fuse programming? <y/N>\n");
- if (getc() == 'y') {
- int c;
-
- putc('y');
- c = getc();
- putc('\n');
- if (c == '\r')
- return 1;
- }
+ if (confirm_yesno())
+ return 1;
puts("Fuse programming aborted\n");
return 0;
);
#else /* !CONFIG_GENERIC_MMC */
-enum mmc_state {
- MMC_INVALID,
- MMC_READ,
- MMC_WRITE,
- MMC_ERASE,
-};
static void print_mmcinfo(struct mmc *mmc)
{
printf("Device: %s\n", mmc->cfg->name);
printf("Bus Width: %d-bit\n", mmc->bus_width);
}
-
+static struct mmc *init_mmc_device(int dev)
+{
+ struct mmc *mmc;
+ mmc = find_mmc_device(dev);
+ if (!mmc) {
+ printf("no mmc device at slot %x\n", dev);
+ return NULL;
+ }
+ if (mmc_init(mmc))
+ return NULL;
+ return mmc;
+}
static int do_mmcinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct mmc *mmc;
}
}
- mmc = find_mmc_device(curr_device);
+ mmc = init_mmc_device(curr_device);
+ if (!mmc)
+ return CMD_RET_FAILURE;
- if (mmc) {
- mmc_init(mmc);
+ print_mmcinfo(mmc);
+ return CMD_RET_SUCCESS;
+}
- print_mmcinfo(mmc);
- return 0;
- } else {
- printf("no mmc device at slot %x\n", curr_device);
+#ifdef CONFIG_SUPPORT_EMMC_RPMB
+static int confirm_key_prog(void)
+{
+ puts("Warning: Programming authentication key can be done only once !\n"
+ " Use this command only if you are sure of what you are doing,\n"
+ "Really perform the key programming? <y/N> ");
+ if (confirm_yesno())
return 1;
+
+ puts("Authentication key programming aborted\n");
+ return 0;
+}
+static int do_mmcrpmb_key(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ void *key_addr;
+ struct mmc *mmc = find_mmc_device(curr_device);
+
+ if (argc != 2)
+ return CMD_RET_USAGE;
+
+ key_addr = (void *)simple_strtoul(argv[1], NULL, 16);
+ if (!confirm_key_prog())
+ return CMD_RET_FAILURE;
+ if (mmc_rpmb_set_key(mmc, key_addr)) {
+ printf("ERROR - Key already programmed ?\n");
+ return CMD_RET_FAILURE;
}
+ return CMD_RET_SUCCESS;
}
+static int do_mmcrpmb_read(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ u16 blk, cnt;
+ void *addr;
+ int n;
+ void *key_addr = NULL;
+ struct mmc *mmc = find_mmc_device(curr_device);
-U_BOOT_CMD(
- mmcinfo, 1, 0, do_mmcinfo,
- "display MMC info",
- "- display info of the current MMC device"
-);
+ if (argc < 4)
+ return CMD_RET_USAGE;
-static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+ addr = (void *)simple_strtoul(argv[1], NULL, 16);
+ blk = simple_strtoul(argv[2], NULL, 16);
+ cnt = simple_strtoul(argv[3], NULL, 16);
+
+ if (argc == 5)
+ key_addr = (void *)simple_strtoul(argv[4], NULL, 16);
+
+ printf("\nMMC RPMB read: dev # %d, block # %d, count %d ... ",
+ curr_device, blk, cnt);
+ n = mmc_rpmb_read(mmc, addr, blk, cnt, key_addr);
+
+ printf("%d RPMB blocks read: %s\n", n, (n == cnt) ? "OK" : "ERROR");
+ if (n != cnt)
+ return CMD_RET_FAILURE;
+ return CMD_RET_SUCCESS;
+}
+static int do_mmcrpmb_write(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
{
- enum mmc_state state;
+ u16 blk, cnt;
+ void *addr;
+ int n;
+ void *key_addr;
+ struct mmc *mmc = find_mmc_device(curr_device);
- if (argc < 2)
+ if (argc != 5)
return CMD_RET_USAGE;
- if (curr_device < 0) {
- if (get_mmc_num() > 0)
- curr_device = 0;
- else {
- puts("No MMC device available\n");
- return 1;
- }
+ addr = (void *)simple_strtoul(argv[1], NULL, 16);
+ blk = simple_strtoul(argv[2], NULL, 16);
+ cnt = simple_strtoul(argv[3], NULL, 16);
+ key_addr = (void *)simple_strtoul(argv[4], NULL, 16);
+
+ printf("\nMMC RPMB write: dev # %d, block # %d, count %d ... ",
+ curr_device, blk, cnt);
+ n = mmc_rpmb_write(mmc, addr, blk, cnt, key_addr);
+
+ printf("%d RPMB blocks written: %s\n", n, (n == cnt) ? "OK" : "ERROR");
+ if (n != cnt)
+ return CMD_RET_FAILURE;
+ return CMD_RET_SUCCESS;
+}
+static int do_mmcrpmb_counter(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ unsigned long counter;
+ struct mmc *mmc = find_mmc_device(curr_device);
+
+ if (mmc_rpmb_get_counter(mmc, &counter))
+ return CMD_RET_FAILURE;
+ printf("RPMB Write counter= %lx\n", counter);
+ return CMD_RET_SUCCESS;
+}
+
+static cmd_tbl_t cmd_rpmb[] = {
+ U_BOOT_CMD_MKENT(key, 2, 0, do_mmcrpmb_key, "", ""),
+ U_BOOT_CMD_MKENT(read, 5, 1, do_mmcrpmb_read, "", ""),
+ U_BOOT_CMD_MKENT(write, 5, 0, do_mmcrpmb_write, "", ""),
+ U_BOOT_CMD_MKENT(counter, 1, 1, do_mmcrpmb_counter, "", ""),
+};
+
+static int do_mmcrpmb(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ cmd_tbl_t *cp;
+ struct mmc *mmc;
+ char original_part;
+ int ret;
+
+ cp = find_cmd_tbl(argv[1], cmd_rpmb, ARRAY_SIZE(cmd_rpmb));
+
+ /* Drop the rpmb subcommand */
+ argc--;
+ argv++;
+
+ if (cp == NULL || argc > cp->maxargs)
+ return CMD_RET_USAGE;
+ if (flag == CMD_FLAG_REPEAT && !cp->repeatable)
+ return CMD_RET_SUCCESS;
+
+ mmc = init_mmc_device(curr_device);
+ if (!mmc)
+ return CMD_RET_FAILURE;
+
+ if (!(mmc->version & MMC_VERSION_MMC)) {
+ printf("It is not a EMMC device\n");
+ return CMD_RET_FAILURE;
+ }
+ if (mmc->version < MMC_VERSION_4_41) {
+ printf("RPMB not supported before version 4.41\n");
+ return CMD_RET_FAILURE;
+ }
+ /* Switch to the RPMB partition */
+ original_part = mmc->part_num;
+ if (mmc->part_num != MMC_PART_RPMB) {
+ if (mmc_switch_part(curr_device, MMC_PART_RPMB) != 0)
+ return CMD_RET_FAILURE;
+ mmc->part_num = MMC_PART_RPMB;
}
+ ret = cp->cmd(cmdtp, flag, argc, argv);
- if (strcmp(argv[1], "rescan") == 0) {
- struct mmc *mmc;
+ /* Return to original partition */
+ if (mmc->part_num != original_part) {
+ if (mmc_switch_part(curr_device, original_part) != 0)
+ return CMD_RET_FAILURE;
+ mmc->part_num = original_part;
+ }
+ return ret;
+}
+#endif
- if (argc != 2)
- return CMD_RET_USAGE;
+static int do_mmc_read(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ struct mmc *mmc;
+ u32 blk, cnt, n;
+ void *addr;
- mmc = find_mmc_device(curr_device);
- if (!mmc) {
- printf("no mmc device at slot %x\n", curr_device);
- return 1;
- }
+ if (argc != 4)
+ return CMD_RET_USAGE;
- mmc->has_init = 0;
+ addr = (void *)simple_strtoul(argv[1], NULL, 16);
+ blk = simple_strtoul(argv[2], NULL, 16);
+ cnt = simple_strtoul(argv[3], NULL, 16);
- if (mmc_init(mmc))
- return 1;
- else
- return 0;
- } else if (strcmp(argv[1], "part") == 0) {
- block_dev_desc_t *mmc_dev;
- struct mmc *mmc;
+ mmc = init_mmc_device(curr_device);
+ if (!mmc)
+ return CMD_RET_FAILURE;
- if (argc != 2)
- return CMD_RET_USAGE;
+ printf("\nMMC read: dev # %d, block # %d, count %d ... ",
+ curr_device, blk, cnt);
- mmc = find_mmc_device(curr_device);
- if (!mmc) {
- printf("no mmc device at slot %x\n", curr_device);
- return 1;
- }
- mmc_init(mmc);
- mmc_dev = mmc_get_dev(curr_device);
- if (mmc_dev != NULL &&
- mmc_dev->type != DEV_TYPE_UNKNOWN) {
- print_part(mmc_dev);
- return 0;
- }
+ n = mmc->block_dev.block_read(curr_device, blk, cnt, addr);
+ /* flush cache after read */
+ flush_cache((ulong)addr, cnt * 512); /* FIXME */
+ printf("%d blocks read: %s\n", n, (n == cnt) ? "OK" : "ERROR");
- puts("get mmc type error!\n");
- return 1;
- } else if (strcmp(argv[1], "list") == 0) {
- if (argc != 2)
- return CMD_RET_USAGE;
- print_mmc_devices('\n');
- return 0;
- } else if (strcmp(argv[1], "dev") == 0) {
- int dev, part = -1;
- struct mmc *mmc;
-
- if (argc == 2)
- dev = curr_device;
- else if (argc == 3)
- dev = simple_strtoul(argv[2], NULL, 10);
- else if (argc == 4) {
- dev = (int)simple_strtoul(argv[2], NULL, 10);
- part = (int)simple_strtoul(argv[3], NULL, 10);
- if (part > PART_ACCESS_MASK) {
- printf("#part_num shouldn't be larger"
- " than %d\n", PART_ACCESS_MASK);
- return 1;
- }
- } else
- return CMD_RET_USAGE;
+ return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
+}
+static int do_mmc_write(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ struct mmc *mmc;
+ u32 blk, cnt, n;
+ void *addr;
- mmc = find_mmc_device(dev);
- if (!mmc) {
- printf("no mmc device at slot %x\n", dev);
- return 1;
- }
+ if (argc != 4)
+ return CMD_RET_USAGE;
- mmc_init(mmc);
- if (part != -1) {
- int ret;
- if (mmc->part_config == MMCPART_NOAVAILABLE) {
- printf("Card doesn't support part_switch\n");
- return 1;
- }
+ addr = (void *)simple_strtoul(argv[1], NULL, 16);
+ blk = simple_strtoul(argv[2], NULL, 16);
+ cnt = simple_strtoul(argv[3], NULL, 16);
- if (part != mmc->part_num) {
- ret = mmc_switch_part(dev, part);
- if (!ret)
- mmc->part_num = part;
+ mmc = init_mmc_device(curr_device);
+ if (!mmc)
+ return CMD_RET_FAILURE;
- printf("switch to partitions #%d, %s\n",
- part, (!ret) ? "OK" : "ERROR");
- }
- }
- curr_device = dev;
- if (mmc->part_config == MMCPART_NOAVAILABLE)
- printf("mmc%d is current device\n", curr_device);
- else
- printf("mmc%d(part %d) is current device\n",
- curr_device, mmc->part_num);
+ printf("\nMMC write: dev # %d, block # %d, count %d ... ",
+ curr_device, blk, cnt);
- return 0;
-#ifdef CONFIG_SUPPORT_EMMC_BOOT
- } else if (strcmp(argv[1], "partconf") == 0) {
- int dev;
- struct mmc *mmc;
- u8 ack, part_num, access;
-
- if (argc == 6) {
- dev = simple_strtoul(argv[2], NULL, 10);
- ack = simple_strtoul(argv[3], NULL, 10);
- part_num = simple_strtoul(argv[4], NULL, 10);
- access = simple_strtoul(argv[5], NULL, 10);
- } else {
- return CMD_RET_USAGE;
- }
+ if (mmc_getwp(mmc) == 1) {
+ printf("Error: card is write protected!\n");
+ return CMD_RET_FAILURE;
+ }
+ n = mmc->block_dev.block_write(curr_device, blk, cnt, addr);
+ printf("%d blocks written: %s\n", n, (n == cnt) ? "OK" : "ERROR");
- mmc = find_mmc_device(dev);
- if (!mmc) {
- printf("no mmc device at slot %x\n", dev);
- return 1;
- }
+ return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
+}
+static int do_mmc_erase(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ struct mmc *mmc;
+ u32 blk, cnt, n;
- if (IS_SD(mmc)) {
- puts("PARTITION_CONFIG only exists on eMMC\n");
- return 1;
- }
+ if (argc != 3)
+ return CMD_RET_USAGE;
- /* acknowledge to be sent during boot operation */
- return mmc_set_part_conf(mmc, ack, part_num, access);
- } else if (strcmp(argv[1], "bootbus") == 0) {
- int dev;
- struct mmc *mmc;
- u8 width, reset, mode;
-
- if (argc == 6) {
- dev = simple_strtoul(argv[2], NULL, 10);
- width = simple_strtoul(argv[3], NULL, 10);
- reset = simple_strtoul(argv[4], NULL, 10);
- mode = simple_strtoul(argv[5], NULL, 10);
- } else {
- return CMD_RET_USAGE;
- }
+ blk = simple_strtoul(argv[1], NULL, 16);
+ cnt = simple_strtoul(argv[2], NULL, 16);
- mmc = find_mmc_device(dev);
- if (!mmc) {
- printf("no mmc device at slot %x\n", dev);
- return 1;
- }
+ mmc = init_mmc_device(curr_device);
+ if (!mmc)
+ return CMD_RET_FAILURE;
- if (IS_SD(mmc)) {
- puts("BOOT_BUS_WIDTH only exists on eMMC\n");
- return 1;
- }
+ printf("\nMMC erase: dev # %d, block # %d, count %d ... ",
+ curr_device, blk, cnt);
- /* acknowledge to be sent during boot operation */
- return mmc_set_boot_bus_width(mmc, width, reset, mode);
- } else if (strcmp(argv[1], "bootpart-resize") == 0) {
- int dev;
- struct mmc *mmc;
- u32 bootsize, rpmbsize;
-
- if (argc == 5) {
- dev = simple_strtoul(argv[2], NULL, 10);
- bootsize = simple_strtoul(argv[3], NULL, 10);
- rpmbsize = simple_strtoul(argv[4], NULL, 10);
- } else {
- return CMD_RET_USAGE;
- }
+ if (mmc_getwp(mmc) == 1) {
+ printf("Error: card is write protected!\n");
+ return CMD_RET_FAILURE;
+ }
+ n = mmc->block_dev.block_erase(curr_device, blk, cnt);
+ printf("%d blocks erased: %s\n", n, (n == cnt) ? "OK" : "ERROR");
- mmc = find_mmc_device(dev);
- if (!mmc) {
- printf("no mmc device at slot %x\n", dev);
- return 1;
- }
+ return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
+}
+static int do_mmc_rescan(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ struct mmc *mmc;
- if (IS_SD(mmc)) {
- printf("It is not a EMMC device\n");
- return 1;
- }
+ mmc = find_mmc_device(curr_device);
+ if (!mmc) {
+ printf("no mmc device at slot %x\n", curr_device);
+ return CMD_RET_FAILURE;
+ }
- if (0 == mmc_boot_partition_size_change(mmc,
- bootsize, rpmbsize)) {
- printf("EMMC boot partition Size %d MB\n", bootsize);
- printf("EMMC RPMB partition Size %d MB\n", rpmbsize);
- return 0;
- } else {
- printf("EMMC boot partition Size change Failed.\n");
- return 1;
- }
- } else if (strcmp(argv[1], "rst-function") == 0) {
- /*
- * Set the RST_n_ENABLE bit of RST_n_FUNCTION
- * The only valid values are 0x0, 0x1 and 0x2 and writing
- * a value of 0x1 or 0x2 sets the value permanently.
- */
- int dev;
- struct mmc *mmc;
- u8 enable;
-
- if (argc == 4) {
- dev = simple_strtoul(argv[2], NULL, 10);
- enable = simple_strtoul(argv[3], NULL, 10);
- } else {
- return CMD_RET_USAGE;
- }
+ mmc->has_init = 0;
- if (enable > 2 || enable < 0) {
- puts("Invalid RST_n_ENABLE value\n");
- return CMD_RET_USAGE;
- }
+ if (mmc_init(mmc))
+ return CMD_RET_FAILURE;
+ return CMD_RET_SUCCESS;
+}
+static int do_mmc_part(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ block_dev_desc_t *mmc_dev;
+ struct mmc *mmc;
- mmc = find_mmc_device(dev);
- if (!mmc) {
- printf("no mmc device at slot %x\n", dev);
- return 1;
+ mmc = init_mmc_device(curr_device);
+ if (!mmc)
+ return CMD_RET_FAILURE;
+
+ mmc_dev = mmc_get_dev(curr_device);
+ if (mmc_dev != NULL && mmc_dev->type != DEV_TYPE_UNKNOWN) {
+ print_part(mmc_dev);
+ return CMD_RET_SUCCESS;
+ }
+
+ puts("get mmc type error!\n");
+ return CMD_RET_FAILURE;
+}
+static int do_mmc_dev(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ int dev, part = -1, ret;
+ struct mmc *mmc;
+
+ if (argc == 1) {
+ dev = curr_device;
+ } else if (argc == 2) {
+ dev = simple_strtoul(argv[1], NULL, 10);
+ } else if (argc == 3) {
+ dev = (int)simple_strtoul(argv[1], NULL, 10);
+ part = (int)simple_strtoul(argv[2], NULL, 10);
+ if (part > PART_ACCESS_MASK) {
+ printf("#part_num shouldn't be larger than %d\n",
+ PART_ACCESS_MASK);
+ return CMD_RET_FAILURE;
}
+ } else {
+ return CMD_RET_USAGE;
+ }
+
+ mmc = init_mmc_device(dev);
+ if (!mmc)
+ return CMD_RET_FAILURE;
- if (IS_SD(mmc)) {
- puts("RST_n_FUNCTION only exists on eMMC\n");
+ if (part != -1) {
+ ret = mmc_select_hwpart(dev, part);
+ printf("switch to partitions #%d, %s\n",
+ part, (!ret) ? "OK" : "ERROR");
+ if (ret)
return 1;
- }
+ }
+ curr_device = dev;
+ if (mmc->part_config == MMCPART_NOAVAILABLE)
+ printf("mmc%d is current device\n", curr_device);
+ else
+ printf("mmc%d(part %d) is current device\n",
+ curr_device, mmc->part_num);
- return mmc_set_rst_n_function(mmc, enable);
-#endif /* CONFIG_SUPPORT_EMMC_BOOT */
+ return CMD_RET_SUCCESS;
+}
+static int do_mmc_list(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ print_mmc_devices('\n');
+ return CMD_RET_SUCCESS;
+}
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+static int do_mmc_bootbus(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ int dev;
+ struct mmc *mmc;
+ u8 width, reset, mode;
+
+ if (argc != 5)
+ return CMD_RET_USAGE;
+ dev = simple_strtoul(argv[1], NULL, 10);
+ width = simple_strtoul(argv[2], NULL, 10);
+ reset = simple_strtoul(argv[3], NULL, 10);
+ mode = simple_strtoul(argv[4], NULL, 10);
+
+ mmc = init_mmc_device(dev);
+ if (!mmc)
+ return CMD_RET_FAILURE;
+
+ if (IS_SD(mmc)) {
+ puts("BOOT_BUS_WIDTH only exists on eMMC\n");
+ return CMD_RET_FAILURE;
}
- else if (argc == 3 && strcmp(argv[1], "setdsr") == 0) {
- struct mmc *mmc = find_mmc_device(curr_device);
- u32 val = simple_strtoul(argv[2], NULL, 16);
- int ret;
+ /* acknowledge to be sent during boot operation */
+ return mmc_set_boot_bus_width(mmc, width, reset, mode);
+}
+static int do_mmc_boot_resize(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ int dev;
+ struct mmc *mmc;
+ u32 bootsize, rpmbsize;
+
+ if (argc != 4)
+ return CMD_RET_USAGE;
+ dev = simple_strtoul(argv[1], NULL, 10);
+ bootsize = simple_strtoul(argv[2], NULL, 10);
+ rpmbsize = simple_strtoul(argv[3], NULL, 10);
- if (!mmc) {
- printf("no mmc device at slot %x\n", curr_device);
- return 1;
- }
- ret = mmc_set_dsr(mmc, val);
- printf("set dsr %s\n", (!ret) ? "OK, force rescan" : "ERROR");
- if (!ret) {
- mmc->has_init = 0;
- if (mmc_init(mmc))
- return 1;
- else
- return 0;
- }
- return ret;
+ mmc = init_mmc_device(dev);
+ if (!mmc)
+ return CMD_RET_FAILURE;
+
+ if (IS_SD(mmc)) {
+ printf("It is not a EMMC device\n");
+ return CMD_RET_FAILURE;
}
- state = MMC_INVALID;
- if (argc == 5 && strcmp(argv[1], "read") == 0)
- state = MMC_READ;
- else if (argc == 5 && strcmp(argv[1], "write") == 0)
- state = MMC_WRITE;
- else if (argc == 4 && strcmp(argv[1], "erase") == 0)
- state = MMC_ERASE;
-
- if (state != MMC_INVALID) {
- struct mmc *mmc = find_mmc_device(curr_device);
- int idx = 2;
- u32 blk, cnt, n;
- void *addr;
-
- if (state != MMC_ERASE) {
- addr = (void *)simple_strtoul(argv[idx], NULL, 16);
- ++idx;
- } else
- addr = NULL;
- blk = simple_strtoul(argv[idx], NULL, 16);
- cnt = simple_strtoul(argv[idx + 1], NULL, 16);
-
- if (!mmc) {
- printf("no mmc device at slot %x\n", curr_device);
- return 1;
- }
+ if (mmc_boot_partition_size_change(mmc, bootsize, rpmbsize)) {
+ printf("EMMC boot partition Size change Failed.\n");
+ return CMD_RET_FAILURE;
+ }
+
+ printf("EMMC boot partition Size %d MB\n", bootsize);
+ printf("EMMC RPMB partition Size %d MB\n", rpmbsize);
+ return CMD_RET_SUCCESS;
+}
+static int do_mmc_partconf(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ int dev;
+ struct mmc *mmc;
+ u8 ack, part_num, access;
- printf("\nMMC %s: dev # %d, block # %d, count %d ... ",
- argv[1], curr_device, blk, cnt);
+ if (argc != 5)
+ return CMD_RET_USAGE;
- mmc_init(mmc);
+ dev = simple_strtoul(argv[1], NULL, 10);
+ ack = simple_strtoul(argv[2], NULL, 10);
+ part_num = simple_strtoul(argv[3], NULL, 10);
+ access = simple_strtoul(argv[4], NULL, 10);
- if ((state == MMC_WRITE || state == MMC_ERASE)) {
- if (mmc_getwp(mmc) == 1) {
- printf("Error: card is write protected!\n");
- return 1;
- }
- }
+ mmc = init_mmc_device(dev);
+ if (!mmc)
+ return CMD_RET_FAILURE;
- switch (state) {
- case MMC_READ:
- n = mmc->block_dev.block_read(curr_device, blk,
- cnt, addr);
- /* flush cache after read */
- flush_cache((ulong)addr, cnt * 512); /* FIXME */
- break;
- case MMC_WRITE:
- n = mmc->block_dev.block_write(curr_device, blk,
- cnt, addr);
- break;
- case MMC_ERASE:
- n = mmc->block_dev.block_erase(curr_device, blk, cnt);
- break;
- default:
- BUG();
- }
+ if (IS_SD(mmc)) {
+ puts("PARTITION_CONFIG only exists on eMMC\n");
+ return CMD_RET_FAILURE;
+ }
+
+ /* acknowledge to be sent during boot operation */
+ return mmc_set_part_conf(mmc, ack, part_num, access);
+}
+static int do_mmc_rst_func(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ int dev;
+ struct mmc *mmc;
+ u8 enable;
+
+ /*
+ * Set the RST_n_ENABLE bit of RST_n_FUNCTION
+ * The only valid values are 0x0, 0x1 and 0x2 and writing
+ * a value of 0x1 or 0x2 sets the value permanently.
+ */
+ if (argc != 3)
+ return CMD_RET_USAGE;
+
+ dev = simple_strtoul(argv[1], NULL, 10);
+ enable = simple_strtoul(argv[2], NULL, 10);
+
+ if (enable > 2 || enable < 0) {
+ puts("Invalid RST_n_ENABLE value\n");
+ return CMD_RET_USAGE;
+ }
+
+ mmc = init_mmc_device(dev);
+ if (!mmc)
+ return CMD_RET_FAILURE;
+
+ if (IS_SD(mmc)) {
+ puts("RST_n_FUNCTION only exists on eMMC\n");
+ return CMD_RET_FAILURE;
+ }
- printf("%d blocks %s: %s\n",
- n, argv[1], (n == cnt) ? "OK" : "ERROR");
- return (n == cnt) ? 0 : 1;
+ return mmc_set_rst_n_function(mmc, enable);
+}
+#endif
+static int do_mmc_setdsr(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ struct mmc *mmc;
+ u32 val;
+ int ret;
+
+ if (argc != 2)
+ return CMD_RET_USAGE;
+ val = simple_strtoul(argv[2], NULL, 16);
+
+ mmc = find_mmc_device(curr_device);
+ if (!mmc) {
+ printf("no mmc device at slot %x\n", curr_device);
+ return CMD_RET_FAILURE;
+ }
+ ret = mmc_set_dsr(mmc, val);
+ printf("set dsr %s\n", (!ret) ? "OK, force rescan" : "ERROR");
+ if (!ret) {
+ mmc->has_init = 0;
+ if (mmc_init(mmc))
+ return CMD_RET_FAILURE;
+ else
+ return CMD_RET_SUCCESS;
}
+ return ret;
+}
+
+static cmd_tbl_t cmd_mmc[] = {
+ U_BOOT_CMD_MKENT(info, 1, 0, do_mmcinfo, "", ""),
+ U_BOOT_CMD_MKENT(read, 4, 1, do_mmc_read, "", ""),
+ U_BOOT_CMD_MKENT(write, 4, 0, do_mmc_write, "", ""),
+ U_BOOT_CMD_MKENT(erase, 3, 0, do_mmc_erase, "", ""),
+ U_BOOT_CMD_MKENT(rescan, 1, 1, do_mmc_rescan, "", ""),
+ U_BOOT_CMD_MKENT(part, 1, 1, do_mmc_part, "", ""),
+ U_BOOT_CMD_MKENT(dev, 3, 0, do_mmc_dev, "", ""),
+ U_BOOT_CMD_MKENT(list, 1, 1, do_mmc_list, "", ""),
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+ U_BOOT_CMD_MKENT(bootbus, 5, 0, do_mmc_bootbus, "", ""),
+ U_BOOT_CMD_MKENT(bootpart-resize, 3, 0, do_mmc_boot_resize, "", ""),
+ U_BOOT_CMD_MKENT(partconf, 5, 0, do_mmc_partconf, "", ""),
+ U_BOOT_CMD_MKENT(rst-function, 3, 0, do_mmc_rst_func, "", ""),
+#endif
+#ifdef CONFIG_SUPPORT_EMMC_RPMB
+ U_BOOT_CMD_MKENT(rpmb, CONFIG_SYS_MAXARGS, 1, do_mmcrpmb, "", ""),
+#endif
+ U_BOOT_CMD_MKENT(setdsr, 2, 0, do_mmc_setdsr, "", ""),
+};
+
+static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ cmd_tbl_t *cp;
+
+ cp = find_cmd_tbl(argv[1], cmd_mmc, ARRAY_SIZE(cmd_mmc));
+
+ /* Drop the mmc command */
+ argc--;
+ argv++;
+
+ if (cp == NULL || argc > cp->maxargs)
+ return CMD_RET_USAGE;
+ if (flag == CMD_FLAG_REPEAT && !cp->repeatable)
+ return CMD_RET_SUCCESS;
- return CMD_RET_USAGE;
+ if (curr_device < 0) {
+ if (get_mmc_num() > 0) {
+ curr_device = 0;
+ } else {
+ puts("No MMC device available\n");
+ return CMD_RET_FAILURE;
+ }
+ }
+ return cp->cmd(cmdtp, flag, argc, argv);
}
U_BOOT_CMD(
- mmc, 6, 1, do_mmcops,
+ mmc, 7, 1, do_mmcops,
"MMC sub system",
- "read addr blk# cnt\n"
+ "info - display info of the current MMC device\n"
+ "mmc read addr blk# cnt\n"
"mmc write addr blk# cnt\n"
"mmc erase blk# cnt\n"
"mmc rescan\n"
" - Change the RST_n_FUNCTION field of the specified device\n"
" WARNING: This is a write-once field and 0 / 1 / 2 are the only valid values.\n"
#endif
- "mmc setdsr - set DSR register value\n"
+#ifdef CONFIG_SUPPORT_EMMC_RPMB
+ "mmc rpmb read addr blk# cnt [address of auth-key] - block size is 256 bytes\n"
+ "mmc rpmb write addr blk# cnt <address of auth-key> - block size is 256 bytes\n"
+ "mmc rpmb key <address of auth-key> - program the RPMB authentication key.\n"
+ "mmc rpmb counter - read the value of the write counter\n"
+#endif
+ "mmc setdsr <value> - set DSR register value\n"
);
+
+/* Old command kept for compatibility. Same as 'mmc info' */
+U_BOOT_CMD(
+ mmcinfo, 1, 0, do_mmcinfo,
+ "display MMC info",
+ "- display info of the current MMC device"
+);
+
#endif /* !CONFIG_GENERIC_MMC */
opts.spread = spread;
if (scrub) {
- if (!scrub_yes)
- puts(scrub_warn);
-
- if (scrub_yes)
+ if (scrub_yes) {
opts.scrub = 1;
- else if (getc() == 'y') {
- puts("y");
- if (getc() == '\r')
+ } else {
+ puts(scrub_warn);
+ if (confirm_yesno()) {
opts.scrub = 1;
- else {
+ } else {
puts("scrub aborted\n");
return 1;
}
- } else {
- puts("scrub aborted\n");
- return 1;
}
}
ret = nand_erase_opts(nand, &opts);
lowup(half + count - 1), page + (half + count - 1) / 2,
half + count
);
-
- i = 0;
- while (1) {
- if (tstc()) {
- const char exp_ans[] = "YES\r";
- char c;
- putc(c = getc());
- if (exp_ans[i++] != c) {
- printf(" Aborting\n");
- return 1;
- } else if (!exp_ans[i]) {
- puts("\n");
- break;
- }
- }
+ if (!confirm_yesno()) {
+ printf(" Aborting\n");
+ return 1;
}
}
U_BOOT_CMD(
part, 5, 1, do_part,
"disk partition related commands",
- "uuid <interface> <dev>:<part>\n"
+ "
part uuid <interface> <dev>:<part>\n"
" - print partition UUID\n"
"part uuid <interface> <dev>:<part> <varname>\n"
" - set environment variable to partition UUID\n"
#include <common.h>
#include <command.h>
#include <g_dnl.h>
+#include <part.h>
#include <usb.h>
#include <usb_mass_storage.h>
+static int ums_read_sector(struct ums *ums_dev,
+ ulong start, lbaint_t blkcnt, void *buf)
+{
+ block_dev_desc_t *block_dev = ums_dev->block_dev;
+ lbaint_t blkstart = start + ums_dev->start_sector;
+ int dev_num = block_dev->dev;
+
+ return block_dev->block_read(dev_num, blkstart, blkcnt, buf);
+}
+
+static int ums_write_sector(struct ums *ums_dev,
+ ulong start, lbaint_t blkcnt, const void *buf)
+{
+ block_dev_desc_t *block_dev = ums_dev->block_dev;
+ lbaint_t blkstart = start + ums_dev->start_sector;
+ int dev_num = block_dev->dev;
+
+ return block_dev->block_write(dev_num, blkstart, blkcnt, buf);
+}
+
+static struct ums ums_dev = {
+ .read_sector = ums_read_sector,
+ .write_sector = ums_write_sector,
+ .name = "UMS disk",
+};
+
+struct ums *ums_init(const char *devtype, const char *devnum)
+{
+ block_dev_desc_t *block_dev;
+ int ret;
+
+ ret = get_device(devtype, devnum, &block_dev);
+ if (ret < 0)
+ return NULL;
+
+ /* f_mass_storage.c assumes SECTOR_SIZE sectors */
+ if (block_dev->blksz != SECTOR_SIZE)
+ return NULL;
+
+ ums_dev.block_dev = block_dev;
+ ums_dev.start_sector = 0;
+ ums_dev.num_sectors = block_dev->lba;
+
+ printf("UMS: disk start sector: %#x, count: %#x\n",
+ ums_dev.start_sector, ums_dev.num_sectors);
+
+ return &ums_dev;
+}
+
int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
+ const char *usb_controller;
+ const char *devtype;
+ const char *devnum;
+ struct ums *ums;
+ unsigned int controller_index;
+ int rc;
+ int cable_ready_timeout __maybe_unused;
+
if (argc < 3)
return CMD_RET_USAGE;
- const char *usb_controller = argv[1];
- const char *mmc_devstring = argv[2];
-
- unsigned int dev_num = simple_strtoul(mmc_devstring, NULL, 0);
+ usb_controller = argv[1];
+ if (argc >= 4) {
+ devtype = argv[2];
+ devnum = argv[3];
+ } else {
+ devtype = "mmc";
+ devnum = argv[2];
+ }
- struct ums *ums = ums_init(dev_num);
+ ums = ums_init(devtype, devnum);
if (!ums)
return CMD_RET_FAILURE;
- unsigned int controller_index = (unsigned int)(simple_strtoul(
- usb_controller, NULL, 0));
+ controller_index = (unsigned int)(simple_strtoul(
+ usb_controller, NULL, 0));
if (board_usb_init(controller_index, USB_INIT_DEVICE)) {
error("Couldn't init USB controller.");
return CMD_RET_FAILURE;
}
- int rc = fsg_init(ums);
+ rc = fsg_init(ums);
if (rc) {
error("fsg_init failed");
return CMD_RET_FAILURE;
}
- g_dnl_register("usb_dnl_ums");
+ rc = g_dnl_register("usb_dnl_ums");
+ if (rc) {
+ error("g_dnl_register failed");
+ return CMD_RET_FAILURE;
+ }
/* Timeout unit: seconds */
- int cable_ready_timeout = UMS_CABLE_READY_TIMEOUT;
+ cable_ready_timeout = UMS_CABLE_READY_TIMEOUT;
if (!g_dnl_board_usb_cable_connected()) {
/*
return CMD_RET_SUCCESS;
}
-U_BOOT_CMD(ums, CONFIG_SYS_MAXARGS, 1, do_usb_mass_storage,
+U_BOOT_CMD(ums, 4, 1, do_usb_mass_storage,
"Use the UMS [User Mass Storage]",
- "ums <USB_controller> <mmc_dev> e.g. ums 0 0"
+ "ums <USB_controller> [<devtype>] <devnum> e.g. ums 0 mmc 0\n"
+ " devtype defaults to mmc"
);
}
return 0;
}
-
+/* Reads user's confirmation.
+ Returns 1 if user's input is "y", "Y", "yes" or "YES"
+*/
+int confirm_yesno(void)
+{
+ int i;
+ char str_input[5];
+
+ /* Flush input */
+ while (tstc())
+ getc();
+ i = 0;
+ while (i < sizeof(str_input)) {
+ str_input[i] = getc();
+ putc(str_input[i]);
+ if (str_input[i] == '\r')
+ break;
+ i++;
+ }
+ putc('\n');
+ if (strncmp(str_input, "y\r", 2) == 0 ||
+ strncmp(str_input, "Y\r", 2) == 0 ||
+ strncmp(str_input, "yes\r", 4) == 0 ||
+ strncmp(str_input, "YES\r", 4) == 0)
+ return 1;
+ return 0;
+}
/* pass 1 to disable ctrlc() checking, 0 to enable.
* returns previous state
*/
--- /dev/null
+/*
+ * Copyright (c) 2011 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <image.h>
+#include <android_image.h>
+
+static char andr_tmp_str[ANDR_BOOT_ARGS_SIZE + 1];
+
+int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify,
+ ulong *os_data, ulong *os_len)
+{
+ /*
+ * Not all Android tools use the id field for signing the image with
+ * sha1 (or anything) so we don't check it. It is not obvious that the
+ * string is null terminated so we take care of this.
+ */
+ strncpy(andr_tmp_str, hdr->name, ANDR_BOOT_NAME_SIZE);
+ andr_tmp_str[ANDR_BOOT_NAME_SIZE] = '\0';
+ if (strlen(andr_tmp_str))
+ printf("Android's image name: %s\n", andr_tmp_str);
+
+ printf("Kernel load addr 0x%08x size %u KiB\n",
+ hdr->kernel_addr, DIV_ROUND_UP(hdr->kernel_size, 1024));
+ strncpy(andr_tmp_str, hdr->cmdline, ANDR_BOOT_ARGS_SIZE);
+ andr_tmp_str[ANDR_BOOT_ARGS_SIZE] = '\0';
+ if (strlen(andr_tmp_str)) {
+ printf("Kernel command line: %s\n", andr_tmp_str);
+ setenv("bootargs", andr_tmp_str);
+ }
+ if (hdr->ramdisk_size)
+ printf("RAM disk load addr 0x%08x size %u KiB\n",
+ hdr->ramdisk_addr,
+ DIV_ROUND_UP(hdr->ramdisk_size, 1024));
+
+ if (os_data) {
+ *os_data = (ulong)hdr;
+ *os_data += hdr->page_size;
+ }
+ if (os_len)
+ *os_len = hdr->kernel_size;
+ return 0;
+}
+
+int android_image_check_header(const struct andr_img_hdr *hdr)
+{
+ return memcmp(ANDR_BOOT_MAGIC, hdr->magic, ANDR_BOOT_MAGIC_SIZE);
+}
+
+ulong android_image_get_end(const struct andr_img_hdr *hdr)
+{
+ u32 size = 0;
+ /*
+ * The header takes a full page, the remaining components are aligned
+ * on page boundary
+ */
+ size += hdr->page_size;
+ size += ALIGN(hdr->kernel_size, hdr->page_size);
+ size += ALIGN(hdr->ramdisk_size, hdr->page_size);
+ size += ALIGN(hdr->second_size, hdr->page_size);
+
+ return size;
+}
+
+ulong android_image_get_kload(const struct andr_img_hdr *hdr)
+{
+ return hdr->kernel_addr;
+}
+
+int android_image_get_ramdisk(const struct andr_img_hdr *hdr,
+ ulong *rd_data, ulong *rd_len)
+{
+ if (!hdr->ramdisk_size)
+ return -1;
+ *rd_data = (unsigned long)hdr;
+ *rd_data += hdr->page_size;
+ *rd_data += ALIGN(hdr->kernel_size, hdr->page_size);
+
+ *rd_len = hdr->ramdisk_size;
+ return 0;
+}
if (image_check_magic(hdr))
format = IMAGE_FORMAT_LEGACY;
#if defined(CONFIG_FIT) || defined(CONFIG_OF_LIBFDT)
- else {
- if (fdt_check_header(img_addr) == 0)
- format = IMAGE_FORMAT_FIT;
- }
+ else if (fdt_check_header(img_addr) == 0)
+ format = IMAGE_FORMAT_FIT;
+#endif
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+ else if (android_image_check_header(img_addr) == 0)
+ format = IMAGE_FORMAT_ANDROID;
#endif
return format;
(ulong)images->legacy_hdr_os);
image_multi_getimg(images->legacy_hdr_os, 1, &rd_data, &rd_len);
- } else {
+ }
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+ else if ((genimg_get_format(images) == IMAGE_FORMAT_ANDROID) &&
+ (!android_image_get_ramdisk((void *)images->os.start,
+ &rd_data, &rd_len))) {
+ /* empty */
+ }
+#endif
+ else {
/*
* no initrd image
*/
#endif
/* Load u-boot */
nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
- CONFIG_SYS_NAND_PAGE_SIZE, (void *)header);
+ sizeof(*header), (void *)header);
spl_parse_image_header(header);
nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
spl_image.size, (void *)spl_image.load_addr);
struct block_drvr {
char *name;
block_dev_desc_t* (*get_dev)(int dev);
+ int (*select_hwpart)(int dev_num, int hwpart);
};
static const struct block_drvr block_drvr[] = {
{ .name = "usb", .get_dev = usb_stor_get_dev, },
#endif
#if defined(CONFIG_MMC)
- { .name = "mmc", .get_dev = mmc_get_dev, },
+ {
+ .name = "mmc",
+ .get_dev = mmc_get_dev,
+ .select_hwpart = mmc_select_hwpart,
+ },
#endif
#if defined(CONFIG_SYSTEMACE)
{ .name = "ace", .get_dev = systemace_get_dev, },
DECLARE_GLOBAL_DATA_PTR;
#ifdef HAVE_BLOCK_DEVICE
-block_dev_desc_t *get_dev(const char *ifname, int dev)
+block_dev_desc_t *get_dev_hwpart(const char *ifname, int dev, int hwpart)
{
const struct block_drvr *drvr = block_drvr;
block_dev_desc_t* (*reloc_get_dev)(int dev);
+ int (*select_hwpart)(int dev_num, int hwpart);
char *name;
+ int ret;
if (!ifname)
return NULL;
while (drvr->name) {
name = drvr->name;
reloc_get_dev = drvr->get_dev;
+ select_hwpart = drvr->select_hwpart;
#ifdef CONFIG_NEEDS_MANUAL_RELOC
name += gd->reloc_off;
reloc_get_dev += gd->reloc_off;
-#endif
- if (strncmp(ifname, name, strlen(name)) == 0)
- return reloc_get_dev(dev);
+ if (select_hwpart)
+ select_hwpart += gd->reloc_off;
+#endif
+ if (strncmp(ifname, name, strlen(name)) == 0) {
+ block_dev_desc_t *dev_desc = reloc_get_dev(dev);
+ if (!dev_desc)
+ return NULL;
+ if (hwpart == -1)
+ return dev_desc;
+ if (!select_hwpart)
+ return NULL;
+ ret = select_hwpart(dev_desc->dev, hwpart);
+ if (ret < 0)
+ return NULL;
+ return dev_desc;
+ }
drvr++;
}
return NULL;
}
+
+block_dev_desc_t *get_dev(const char *ifname, int dev)
+{
+ return get_dev_hwpart(ifname, dev, -1);
+}
#else
+block_dev_desc_t *get_dev_hwpart(const char *ifname, int dev, int hwpart)
+{
+ return NULL;
+}
+
block_dev_desc_t *get_dev(const char *ifname, int dev)
{
return NULL;
return -1;
}
-int get_device(const char *ifname, const char *dev_str,
+int get_device(const char *ifname, const char *dev_hwpart_str,
block_dev_desc_t **dev_desc)
{
char *ep;
- int dev;
+ char *dup_str = NULL;
+ const char *dev_str, *hwpart_str;
+ int dev, hwpart;
+
+ hwpart_str = strchr(dev_hwpart_str, '.');
+ if (hwpart_str) {
+ dup_str = strdup(dev_hwpart_str);
+ dup_str[hwpart_str - dev_hwpart_str] = 0;
+ dev_str = dup_str;
+ hwpart_str++;
+ } else {
+ dev_str = dev_hwpart_str;
+ hwpart = -1;
+ }
dev = simple_strtoul(dev_str, &ep, 16);
if (*ep) {
printf("** Bad device specification %s %s **\n",
ifname, dev_str);
- return -1;
+ dev = -1;
+ goto cleanup;
+ }
+
+ if (hwpart_str) {
+ hwpart = simple_strtoul(hwpart_str, &ep, 16);
+ if (*ep) {
+ printf("** Bad HW partition specification %s %s **\n",
+ ifname, hwpart_str);
+ dev = -1;
+ goto cleanup;
+ }
}
- *dev_desc = get_dev(ifname, dev);
+ *dev_desc = get_dev_hwpart(ifname, dev, hwpart);
if (!(*dev_desc) || ((*dev_desc)->type == DEV_TYPE_UNKNOWN)) {
- printf("** Bad device %s %s **\n", ifname, dev_str);
- return -1;
+ printf("** Bad device %s %s **\n", ifname, dev_hwpart_str);
+ dev = -1;
+ goto cleanup;
}
+cleanup:
+ free(dup_str);
return dev;
}
--- /dev/null
+Android Fastboot
+~~~~~~~~~~~~~~~~
+
+Overview
+========
+The protocol that is used over USB is described in
+README.android-fastboot-protocol in same directory.
+
+The current implementation does not yet support the flash and erase
+commands.
+
+Client installation
+===================
+The counterpart to this gadget is the fastboot client which can
+be found in Android's platform/system/core repository in the fastboot
+folder. It runs on Windows, Linux and even OSX. Linux user are lucky since
+they only need libusb.
+Windows users need to bring some time until they have Android SDK (currently
+http://dl.google.com/android/installer_r12-windows.exe) installed. You
+need to install ADB package which contains the required glue libraries for
+accessing USB. Also you need "Google USB driver package" and "SDK platform
+tools". Once installed the usb driver is placed in your SDK folder under
+extras\google\usb_driver. The android_winusb.inf needs a line like
+
+ %SingleBootLoaderInterface% = USB_Install, USB\VID_0451&PID_D022
+
+either in the [Google.NTx86] section for 32bit Windows or [Google.NTamd64]
+for 64bit Windows. VID and PID should match whatever the fastboot is
+advertising.
+
+Board specific
+==============
+The fastboot gadget relies on the USB download gadget, so the following
+options must be configured:
+
+CONFIG_USBDOWNLOAD_GADGET
+CONFIG_G_DNL_VENDOR_NUM
+CONFIG_G_DNL_PRODUCT_NUM
+CONFIG_G_DNL_MANUFACTURER
+
+The fastboot function is enabled by defining CONFIG_CMD_FASTBOOT and
+CONFIG_ANDROID_BOOT_IMAGE.
+
+The fastboot protocol requires a large memory buffer for downloads. This
+buffer should be as large as possible for a platform. The location of the
+buffer and size are set with CONFIG_USB_FASTBOOT_BUF_ADDR and
+CONFIG_USB_FASTBOOT_BUF_SIZE.
+
+In Action
+=========
+Enter into fastboot by executing the fastboot command in u-boot and you
+should see:
+|GADGET DRIVER: usb_dnl_fastboot
+
+On the client side you can fetch the bootloader version for instance:
+|>fastboot getvar bootloader-version
+|bootloader-version: U-Boot 2014.04-00005-gd24cabc
+|finished. total time: 0.000s
+
+or initiate a reboot:
+|>fastboot reboot
+
+and once the client comes back, the board should reset.
+
+You can also specify a kernel image to boot. You have to either specify
+the an image in Android format _or_ pass a binary kernel and let the
+fastboot client wrap the Android suite around it. On OMAP for instance you
+take zImage kernel and pass it to the fastboot client:
+
+|>fastboot -b 0x80000000 -c "console=ttyO2 earlyprintk root=/dev/ram0
+| mem=128M" boot zImage
+|creating boot image...
+|creating boot image - 1847296 bytes
+|downloading 'boot.img'...
+|OKAY [ 2.766s]
+|booting...
+|OKAY [ -0.000s]
+|finished. total time: 2.766s
+
+and on the gadget side you should see:
+|Starting download of 1847296 bytes
+|........................................................
+|downloading of 1847296 bytes finished
+|Booting kernel..
+|## Booting Android Image at 0x81000000 ...
+|Kernel load addr 0x80008000 size 1801 KiB
+|Kernel command line: console=ttyO2 earlyprintk root=/dev/ram0 mem=128M
+| Loading Kernel Image ... OK
+|OK
+|
+|Starting kernel ...
--- /dev/null
+FastBoot Version 0.4
+----------------------
+
+The fastboot protocol is a mechanism for communicating with bootloaders
+over USB. It is designed to be very straightforward to implement, to
+allow it to be used across a wide range of devices and from hosts running
+Linux, Windows, or OSX.
+
+
+Basic Requirements
+------------------
+
+* Two bulk endpoints (in, out) are required
+* Max packet size must be 64 bytes for full-speed and 512 bytes for
+ high-speed USB
+* The protocol is entirely host-driven and synchronous (unlike the
+ multi-channel, bi-directional, asynchronous ADB protocol)
+
+
+Transport and Framing
+---------------------
+
+1. Host sends a command, which is an ascii string in a single
+ packet no greater than 64 bytes.
+
+2. Client response with a single packet no greater than 64 bytes.
+ The first four bytes of the response are "OKAY", "FAIL", "DATA",
+ or "INFO". Additional bytes may contain an (ascii) informative
+ message.
+
+ a. INFO -> the remaining 60 bytes are an informative message
+ (providing progress or diagnostic messages). They should
+ be displayed and then step #2 repeats
+
+ b. FAIL -> the requested command failed. The remaining 60 bytes
+ of the response (if present) provide a textual failure message
+ to present to the user. Stop.
+
+ c. OKAY -> the requested command completed successfully. Go to #5
+
+ d. DATA -> the requested command is ready for the data phase.
+ A DATA response packet will be 12 bytes long, in the form of
+ DATA00000000 where the 8 digit hexidecimal number represents
+ the total data size to transfer.
+
+3. Data phase. Depending on the command, the host or client will
+ send the indicated amount of data. Short packets are always
+ acceptable and zero-length packets are ignored. This phase continues
+ until the client has sent or received the number of bytes indicated
+ in the "DATA" response above.
+
+4. Client responds with a single packet no greater than 64 bytes.
+ The first four bytes of the response are "OKAY", "FAIL", or "INFO".
+ Similar to #2:
+
+ a. INFO -> display the remaining 60 bytes and return to #4
+
+ b. FAIL -> display the remaining 60 bytes (if present) as a failure
+ reason and consider the command failed. Stop.
+
+ c. OKAY -> success. Go to #5
+
+5. Success. Stop.
+
+
+Example Session
+---------------
+
+Host: "getvar:version" request version variable
+
+Client: "OKAY0.4" return version "0.4"
+
+Host: "getvar:nonexistant" request some undefined variable
+
+Client: "OKAY" return value ""
+
+Host: "download:00001234" request to send 0x1234 bytes of data
+
+Client: "DATA00001234" ready to accept data
+
+Host: < 0x1234 bytes > send data
+
+Client: "OKAY" success
+
+Host: "flash:bootloader" request to flash the data to the bootloader
+
+Client: "INFOerasing flash" indicate status / progress
+ "INFOwriting flash"
+ "OKAY" indicate success
+
+Host: "powerdown" send a command
+
+Client: "FAILunknown command" indicate failure
+
+
+Command Reference
+-----------------
+
+* Command parameters are indicated by printf-style escape sequences.
+
+* Commands are ascii strings and sent without the quotes (which are
+ for illustration only here) and without a trailing 0 byte.
+
+* Commands that begin with a lowercase letter are reserved for this
+ specification. OEM-specific commands should not begin with a
+ lowercase letter, to prevent incompatibilities with future specs.
+
+ "getvar:%s" Read a config/version variable from the bootloader.
+ The variable contents will be returned after the
+ OKAY response.
+
+ "download:%08x" Write data to memory which will be later used
+ by "boot", "ramdisk", "flash", etc. The client
+ will reply with "DATA%08x" if it has enough
+ space in RAM or "FAIL" if not. The size of
+ the download is remembered.
+
+ "verify:%08x" Send a digital signature to verify the downloaded
+ data. Required if the bootloader is "secure"
+ otherwise "flash" and "boot" will be ignored.
+
+ "flash:%s" Write the previously downloaded image to the
+ named partition (if possible).
+
+ "erase:%s" Erase the indicated partition (clear to 0xFFs)
+
+ "boot" The previously downloaded data is a boot.img
+ and should be booted according to the normal
+ procedure for a boot.img
+
+ "continue" Continue booting as normal (if possible)
+
+ "reboot" Reboot the device.
+
+ "reboot-bootloader" Reboot back into the bootloader.
+ Useful for upgrade processes that require upgrading
+ the bootloader and then upgrading other partitions
+ using the new bootloader.
+
+ "powerdown" Power off the device.
+
+
+
+Client Variables
+----------------
+
+The "getvar:%s" command is used to read client variables which
+represent various information about the device and the software
+on it.
+
+The various currently defined names are:
+
+ version Version of FastBoot protocol supported.
+ It should be "0.3" for this document.
+
+ version-bootloader Version string for the Bootloader.
+
+ version-baseband Version string of the Baseband Software
+
+ product Name of the product
+
+ serialno Product serial number
+
+ secure If the value is "yes", this is a secure
+ bootloader requiring a signature before
+ it will install or boot images.
+
+Names starting with a lowercase character are reserved by this
+specification. OEM-specific names should not start with lowercase
+characters.
{
int ret = 0;
+ ret = dfu_write_buffer_drain(dfu);
+ if (ret)
+ return ret;
+
if (dfu->flush_medium)
ret = dfu->flush_medium(dfu);
dfu_file_buf[CONFIG_SYS_DFU_MAX_FILE_SIZE];
static long dfu_file_buf_len;
+static int mmc_access_part(struct dfu_entity *dfu, struct mmc *mmc, int part)
+{
+ int ret;
+
+ if (part == mmc->part_num)
+ return 0;
+
+ ret = mmc_switch_part(dfu->dev_num, part);
+ if (ret) {
+ error("Cannot switch to partition %d\n", part);
+ return ret;
+ }
+ mmc->part_num = part;
+
+ return 0;
+}
+
static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu,
u64 offset, void *buf, long *len)
{
struct mmc *mmc = find_mmc_device(dfu->dev_num);
u32 blk_start, blk_count, n = 0;
+ int ret, part_num_bkp = 0;
/*
* We must ensure that we work in lba_blk_size chunks, so ALIGN
return -EINVAL;
}
+ if (dfu->data.mmc.hw_partition >= 0) {
+ part_num_bkp = mmc->part_num;
+ ret = mmc_access_part(dfu, mmc, dfu->data.mmc.hw_partition);
+ if (ret)
+ return ret;
+ }
+
debug("%s: %s dev: %d start: %d cnt: %d buf: 0x%p\n", __func__,
op == DFU_OP_READ ? "MMC READ" : "MMC WRITE", dfu->dev_num,
blk_start, blk_count, buf);
if (n != blk_count) {
error("MMC operation failed");
+ if (dfu->data.mmc.hw_partition >= 0)
+ mmc_access_part(dfu, mmc, part_num_bkp);
return -EIO;
}
+ if (dfu->data.mmc.hw_partition >= 0) {
+ ret = mmc_access_part(dfu, mmc, part_num_bkp);
+ if (ret)
+ return ret;
+ }
+
return 0;
}
* 2nd and 3rd:
* lba_start and lba_size, for raw write
* mmc_dev and mmc_part, for filesystems and part
+ * 4th (optional):
+ * mmcpart <num> (access to HW eMMC partitions)
*/
int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s)
{
return -ENODEV;
}
+ dfu->data.mmc.hw_partition = -EINVAL;
if (!strcmp(entity_type, "raw")) {
dfu->layout = DFU_RAW_ADDR;
dfu->data.mmc.lba_start = second_arg;
dfu->data.mmc.lba_size = third_arg;
dfu->data.mmc.lba_blk_size = mmc->read_bl_len;
+
+ /*
+ * Check for an extra entry at dfu_alt_info env variable
+ * specifying the mmc HW defined partition number
+ */
+ if (s)
+ if (!strcmp(strsep(&s, " "), "mmcpart"))
+ dfu->data.mmc.hw_partition =
+ simple_strtoul(s, NULL, 0);
+
} else if (!strcmp(entity_type, "part")) {
disk_partition_t partinfo;
block_dev_desc_t *blk_dev = &mmc->block_dev;
return ret;
}
+unsigned int dfu_polltimeout_nand(struct dfu_entity *dfu)
+{
+ /*
+ * Currently, Poll Timeout != 0 is only needed on nand
+ * ubi partition, as the not used sectors need an erase
+ */
+ if (dfu->data.nand.ubi)
+ return DFU_MANIFEST_POLL_TIMEOUT;
+
+ return DFU_DEFAULT_POLL_TIMEOUT;
+}
+
int dfu_fill_entity_nand(struct dfu_entity *dfu, char *s)
{
char *st;
dfu->read_medium = dfu_read_medium_nand;
dfu->write_medium = dfu_write_medium_nand;
dfu->flush_medium = dfu_flush_medium_nand;
+ dfu->poll_timeout = dfu_polltimeout_nand;
/* initial state */
dfu->inited = 0;
/*
* Convert bitstream data and load into the fpga
*/
-int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size)
+int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
+ bitstream_type bstype)
{
printf("Bitstream support not implemented for this FPGA device\n");
return FPGA_FAIL;
}
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+int fpga_fsload(int devnum, const void *buf, size_t size,
+ fpga_fs_info *fpga_fsinfo)
+{
+ int ret_val = FPGA_FAIL; /* assume failure */
+ const fpga_desc *desc = fpga_validate(devnum, buf, size,
+ (char *)__func__);
+
+ if (desc) {
+ switch (desc->devtype) {
+ case fpga_xilinx:
+#if defined(CONFIG_FPGA_XILINX)
+ ret_val = xilinx_loadfs(desc->devdesc, buf, size,
+ fpga_fsinfo);
+#else
+ fpga_no_sup((char *)__func__, "Xilinx devices");
+#endif
+ break;
+ default:
+ printf("%s: Invalid or unsupported device type %d\n",
+ __func__, desc->devtype);
+ }
+ }
+
+ return ret_val;
+}
+#endif
+
/*
* Generic multiplexing code
*/
-int fpga_load(int devnum, const void *buf, size_t bsize)
+int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype)
{
int ret_val = FPGA_FAIL; /* assume failure */
const fpga_desc *desc = fpga_validate(devnum, buf, bsize,
switch (desc->devtype) {
case fpga_xilinx:
#if defined(CONFIG_FPGA_XILINX)
- ret_val = xilinx_load(desc->devdesc, buf, bsize);
+ ret_val = xilinx_load(desc->devdesc, buf, bsize,
+ bstype);
#else
fpga_no_sup((char *)__func__, "Xilinx devices");
#endif
/* ------------------------------------------------------------------------- */
/* Spartan-II Generic Implementation */
-static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize,
+ bitstream_type bstype)
{
int ret_val = FPGA_FAIL;
/* ------------------------------------------------------------------------- */
/* Spartan-II Generic Implementation */
-static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize,
+ bitstream_type bstype)
{
int ret_val = FPGA_FAIL;
static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
-static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize,
+ bitstream_type bstype)
{
int ret_val = FPGA_FAIL;
/* ------------------------------------------------------------------------- */
-int fpga_loadbitstream(int devnum, char *fpgadata, size_t size)
+int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
+ bitstream_type bstype)
{
unsigned int length;
unsigned int swapsize;
dataptr += 4;
printf(" bytes in bitstream = %d\n", swapsize);
- return fpga_load(devnum, dataptr, swapsize);
+ return fpga_load(devnum, dataptr, swapsize, bstype);
}
-int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize)
+int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize,
+ bitstream_type bstype)
{
if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
printf ("%s: Invalid device descriptor\n", __FUNCTION__);
return FPGA_FAIL;
}
- return desc->operations->load(desc, buf, bsize);
+ return desc->operations->load(desc, buf, bsize, bstype);
}
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
+ fpga_fs_info *fpga_fsinfo)
+{
+ if (!xilinx_validate(desc, (char *)__func__)) {
+ printf("%s: Invalid device descriptor\n", __func__);
+ return FPGA_FAIL;
+ }
+
+ if (!desc->operations->loadfs)
+ return FPGA_FAIL;
+
+ return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo);
+}
+#endif
+
int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
#include <common.h>
#include <asm/io.h>
+#include <fs.h>
#include <zynqpl.h>
#include <linux/sizes.h>
#include <asm/arch/hardware.h>
return FPGA_SUCCESS;
}
-static int zynq_dma_xfer_init(u32 partialbit)
+static int zynq_dma_xfer_init(bitstream_type bstype)
{
u32 status, control, isr_status;
unsigned long ts;
/* Clear loopback bit */
clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
- if (!partialbit) {
+ if (bstype != BIT_PARTIAL) {
zynq_slcr_devcfg_disable();
/* Setting PCFG_PROG_B signal to high */
static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
size_t bsize, u32 blocksize, u32 *swap,
- u32 *partialbit)
+ bitstream_type *bstype)
{
u32 *buf_start;
u32 diff;
- /* Detect if we are going working with partial or full bitstream */
- if (bsize != desc->size) {
- printf("%s: Working with partial bitstream\n", __func__);
- *partialbit = 1;
- }
buf_start = check_data((u8 *)buf, blocksize, swap);
if (!buf_start)
return FPGA_FAIL;
}
- if (zynq_dma_xfer_init(*partialbit))
+ if (zynq_dma_xfer_init(*bstype))
return FPGA_FAIL;
return 0;
}
-
-static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize)
+static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize,
+ bitstream_type bstype)
{
unsigned long ts; /* Timestamp */
- u32 partialbit = 0;
u32 isr_status, swap;
/*
* in chunks
*/
if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap,
- &partialbit))
+ &bstype))
return FPGA_FAIL;
buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap);
debug("%s: FPGA config done\n", __func__);
+ if (bstype != BIT_PARTIAL)
+ zynq_slcr_devcfg_enable();
+
+ return FPGA_SUCCESS;
+}
+
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
+ fpga_fs_info *fsinfo)
+{
+ unsigned long ts; /* Timestamp */
+ u32 isr_status, swap;
+ u32 partialbit = 0;
+ u32 blocksize;
+ u32 pos = 0;
+ int fstype;
+ char *interface, *dev_part, *filename;
+
+ blocksize = fsinfo->blocksize;
+ interface = fsinfo->interface;
+ dev_part = fsinfo->dev_part;
+ filename = fsinfo->filename;
+ fstype = fsinfo->fstype;
+
+ if (fs_set_blk_dev(interface, dev_part, fstype))
+ return FPGA_FAIL;
+
+ if (fs_read(filename, (u32) buf, pos, blocksize) < 0)
+ return FPGA_FAIL;
+
+ if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap,
+ &partialbit))
+ return FPGA_FAIL;
+
+ dcache_disable();
+
+ do {
+ buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
+
+ if (zynq_dma_transfer((u32)buf | 1, blocksize >> 2,
+ 0xffffffff, 0))
+ return FPGA_FAIL;
+
+ bsize -= blocksize;
+ pos += blocksize;
+
+ if (fs_set_blk_dev(interface, dev_part, fstype))
+ return FPGA_FAIL;
+
+ if (bsize > blocksize) {
+ if (fs_read(filename, (u32) buf, pos, blocksize) < 0)
+ return FPGA_FAIL;
+ } else {
+ if (fs_read(filename, (u32) buf, pos, bsize) < 0)
+ return FPGA_FAIL;
+ }
+ } while (bsize > blocksize);
+
+ buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
+
+ if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
+ return FPGA_FAIL;
+
+ dcache_enable();
+
+ isr_status = readl(&devcfg_base->int_sts);
+
+ /* Check FPGA configuration completion */
+ ts = get_timer(0);
+ while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
+ if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+ printf("%s: Timeout wait for FPGA to config\n",
+ __func__);
+ return FPGA_FAIL;
+ }
+ isr_status = readl(&devcfg_base->int_sts);
+ }
+
+ debug("%s: FPGA config done\n", __func__);
+
if (!partialbit)
zynq_slcr_devcfg_enable();
return FPGA_SUCCESS;
}
+#endif
static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
struct xilinx_fpga_op zynq_op = {
.load = zynq_load,
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+ .loadfs = zynq_loadfs,
+#endif
.dump = zynq_dump,
.info = zynq_info,
};
#include <common.h>
#include <asm/io.h>
#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
-#define S5P_GPIO_GET_BANK(x) ((x >> S5P_GPIO_BANK_SHIFT) \
- & S5P_GPIO_BANK_MASK)
-
-#define S5P_GPIO_GET_PIN(x) (x & S5P_GPIO_PIN_MASK)
+#define S5P_GPIO_GET_PIN(x) (x % GPIO_PER_BANK)
#define CON_MASK(x) (0xf << ((x) << 2))
#define CON_SFR(x, v) ((v) << ((x) << 2))
#define RATE_MASK(x) (0x1 << (x + 16))
#define RATE_SET(x) (0x1 << (x + 16))
-void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
+#define name_to_gpio(n) s5p_name_to_gpio(n)
+static inline int s5p_name_to_gpio(const char *name)
+{
+ unsigned num, irregular_set_number, irregular_bank_base;
+ const struct gpio_name_num_table *tabp;
+ char this_bank, bank_name, irregular_bank_name;
+ char *endp;
+
+ /*
+ * The gpio name starts with either 'g' or 'gp' followed by the bank
+ * name character. Skip one or two characters depending on the prefix.
+ */
+ if (name[0] == 'g' && name[1] == 'p')
+ name += 2;
+ else if (name[0] == 'g')
+ name++;
+ else
+ return -1; /* Name must start with 'g' */
+
+ bank_name = *name++;
+ if (!*name)
+ return -1; /* At least one digit is required/expected. */
+
+ /*
+ * On both exynos5 and exynos5420 architectures there is a bank of
+ * GPIOs which does not fall into the regular address pattern. Those
+ * banks are c4 on Exynos5 and y7 on Exynos5420. The rest of the below
+ * assignments help to handle these irregularities.
+ */
+#if defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5)
+ if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420()) {
+ tabp = exynos5420_gpio_table;
+ irregular_bank_name = 'y';
+ irregular_set_number = '7';
+ irregular_bank_base = EXYNOS5420_GPIO_Y70;
+ } else {
+ tabp = exynos5_gpio_table;
+ irregular_bank_name = 'c';
+ irregular_set_number = '4';
+ irregular_bank_base = EXYNOS5_GPIO_C40;
+ }
+ } else {
+ if (proid_is_exynos4412())
+ tabp = exynos4x12_gpio_table;
+ else
+ tabp = exynos4_gpio_table;
+ irregular_bank_name = 0;
+ irregular_set_number = 0;
+ irregular_bank_base = 0;
+ }
+#else
+ if (cpu_is_s5pc110())
+ tabp = s5pc110_gpio_table;
+ else
+ tabp = s5pc100_gpio_table;
+ irregular_bank_name = 0;
+ irregular_set_number = 0;
+ irregular_bank_base = 0;
+#endif
+
+ this_bank = tabp->bank;
+ do {
+ if (bank_name == this_bank) {
+ unsigned pin_index; /* pin number within the bank */
+ if ((bank_name == irregular_bank_name) &&
+ (name[0] == irregular_set_number)) {
+ pin_index = name[1] - '0';
+ /* Irregular sets have 8 pins. */
+ if (pin_index >= GPIO_PER_BANK)
+ return -1;
+ num = irregular_bank_base + pin_index;
+ } else {
+ pin_index = simple_strtoul(name, &endp, 8);
+ pin_index -= tabp->bank_offset;
+ /*
+ * Sanity check: bunk 'z' has no set number,
+ * for all other banks there must be exactly
+ * two octal digits, and the resulting number
+ * should not exceed the number of pins in the
+ * bank.
+ */
+ if (((bank_name != 'z') && !name[1]) ||
+ *endp ||
+ (pin_index >= tabp->bank_size))
+ return -1;
+ num = tabp->base + pin_index;
+ }
+ return num;
+ }
+ this_bank = (++tabp)->bank;
+ } while (this_bank);
+
+ return -1;
+}
+
+static void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
{
unsigned int value;
writel(value, &bank->con);
}
-void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en)
-{
- s5p_gpio_cfg_pin(bank, gpio, GPIO_OUTPUT);
- s5p_gpio_set_value(bank, gpio, en);
-}
-
-void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio)
-{
- s5p_gpio_cfg_pin(bank, gpio, GPIO_INPUT);
-}
-
-void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en)
+static void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en)
{
unsigned int value;
writel(value, &bank->dat);
}
-unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio)
+static void s5p_gpio_direction_output(struct s5p_gpio_bank *bank,
+ int gpio, int en)
+{
+ s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_OUTPUT);
+ s5p_gpio_set_value(bank, gpio, en);
+}
+
+static void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio)
+{
+ s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_INPUT);
+}
+
+static unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio)
{
unsigned int value;
return !!(value & DAT_MASK(gpio));
}
-void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
+static void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
{
unsigned int value;
value &= ~PULL_MASK(gpio);
switch (mode) {
- case GPIO_PULL_DOWN:
- case GPIO_PULL_UP:
+ case S5P_GPIO_PULL_DOWN:
+ case S5P_GPIO_PULL_UP:
value |= PULL_MODE(gpio, mode);
break;
default:
writel(value, &bank->pull);
}
-void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode)
+static void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode)
{
unsigned int value;
value &= ~DRV_MASK(gpio);
switch (mode) {
- case GPIO_DRV_1X:
- case GPIO_DRV_2X:
- case GPIO_DRV_3X:
- case GPIO_DRV_4X:
+ case S5P_GPIO_DRV_1X:
+ case S5P_GPIO_DRV_2X:
+ case S5P_GPIO_DRV_3X:
+ case S5P_GPIO_DRV_4X:
value |= DRV_SET(gpio, mode);
break;
default:
writel(value, &bank->drv);
}
-void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
+static void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
{
unsigned int value;
value &= ~RATE_MASK(gpio);
switch (mode) {
- case GPIO_DRV_FAST:
- case GPIO_DRV_SLOW:
+ case S5P_GPIO_DRV_FAST:
+ case S5P_GPIO_DRV_SLOW:
value |= RATE_SET(gpio);
break;
default:
writel(value, &bank->drv);
}
-struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
+struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)
{
- unsigned bank = S5P_GPIO_GET_BANK(gpio);
- unsigned base = s5p_gpio_base(gpio);
+ const struct gpio_info *data;
+ unsigned int upto;
+ int i, count;
+
+ data = get_gpio_data();
+ count = get_bank_num();
+ upto = 0;
+
+ for (i = 0; i < count; i++) {
+ debug("i=%d, upto=%d\n", i, upto);
+ if (gpio < data->max_gpio) {
+ struct s5p_gpio_bank *bank;
+ bank = (struct s5p_gpio_bank *)data->reg_addr;
+ bank += (gpio - upto) / GPIO_PER_BANK;
+ debug("gpio=%d, bank=%p\n", gpio, bank);
+ return bank;
+ }
+
+ upto = data->max_gpio;
+ data++;
+ }
- return (struct s5p_gpio_bank *)(base + bank);
+ return NULL;
}
int s5p_gpio_get_pin(unsigned gpio)
return 0;
}
+
+void gpio_set_pull(int gpio, int mode)
+{
+ s5p_gpio_set_pull(s5p_gpio_get_bank(gpio),
+ s5p_gpio_get_pin(gpio), mode);
+}
+
+void gpio_set_drv(int gpio, int mode)
+{
+ s5p_gpio_set_drv(s5p_gpio_get_bank(gpio),
+ s5p_gpio_get_pin(gpio), mode);
+}
+
+void gpio_cfg_pin(int gpio, int cfg)
+{
+ s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio),
+ s5p_gpio_get_pin(gpio), cfg);
+}
+
+void gpio_set_rate(int gpio, int mode)
+{
+ s5p_gpio_set_rate(s5p_gpio_get_bank(gpio),
+ s5p_gpio_get_pin(gpio), mode);
+}
return 0;
}
+void gpio_config_table(const struct tegra_gpio_config *config, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ switch (config[i].init) {
+ case TEGRA_GPIO_INIT_IN:
+ gpio_direction_input(config[i].gpio);
+ break;
+ case TEGRA_GPIO_INIT_OUT0:
+ gpio_direction_output(config[i].gpio, 0);
+ break;
+ case TEGRA_GPIO_INIT_OUT1:
+ gpio_direction_output(config[i].gpio, 1);
+ break;
+ }
+ set_config(config[i].gpio, 1);
+ }
+}
+
/*
* Display Tegra GPIO information
*/
*/
#define TWSI_FREQUENCY(m, n) \
- ((u8) (CONFIG_SYS_TCLK / (10 * (m + 1) * 2 * (1 << n))))
-
-/*
- * These are required to be reprogrammed before enabling the controller
- * because a reset loses them.
- * Default values come from the spec, but a twsi_reset will change them.
- * twsi_slave_address left uninitialized lest checkpatch.pl complains.
- */
-
-/* Baudrate generator: m (bits 7..4) =4, n (bits 3..0) =4 */
-static u8 twsi_baud_rate = 0x44; /* baudrate at controller reset */
-/* Default frequency corresponding to default m=4, n=4 */
-static u8 twsi_actual_speed = TWSI_FREQUENCY(4, 4);
-/* Default slave address is 0 (so is an uninitialized static) */
-static u8 twsi_slave_address;
+ (CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n)))
/*
* Reset controller.
* Controller reset also resets the baud rate and slave address, so
* re-establish them.
*/
-static void twsi_reset(void)
+static void twsi_reset(u8 baud_rate, u8 slave_address)
{
/* ensure controller will be enabled by any twsi*() function */
twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
/* wait 2 ms -- this is what the Marvell LSP does */
udelay(20000);
/* set baud rate */
- writel(twsi_baud_rate, &twsi->baudrate);
+ writel(baud_rate, &twsi->baudrate);
/* set slave address even though we don't use it */
- writel(twsi_slave_address, &twsi->slave_address);
+ writel(slave_address, &twsi->slave_address);
writel(0, &twsi->xtnd_slave_addr);
/* assert STOP but don't care for the result */
(void) twsi_stop(0);
}
}
}
- /* save baud rate and slave for later calls to twsi_reset */
- twsi_baud_rate = baud;
- twsi_actual_speed = highest_speed;
- twsi_slave_address = slaveadd;
/* reset controller */
- twsi_reset();
+ twsi_reset(baud, slaveadd);
}
/*
obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o
+obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
else
else if (cmd->resp_type & MMC_RSP_PRESENT)
xfertyp |= XFERTYP_RSPTYP_48;
-#if defined(CONFIG_MX53) || defined(CONFIG_T4240QDS)
+#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240)
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
xfertyp |= XFERTYP_CMDTYP_ABORT;
#endif
int timeout;
struct fsl_esdhc_cfg *cfg = mmc->priv;
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
-#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+
uint wml_value;
wml_value = data->blocksize/4;
wml_value = WML_RD_WML_MAX_VAL;
esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
esdhc_write32(®s->dsaddr, (u32)data->dest);
+#endif
} else {
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
flush_dcache_range((ulong)data->src,
(ulong)data->src+data->blocks
*data->blocksize);
-
+#endif
if (wml_value > WML_WR_WML_MAX)
wml_value = WML_WR_WML_MAX_VAL;
if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
wml_value << 16);
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
esdhc_write32(®s->dsaddr, (u32)data->src);
+#endif
}
-#else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
- if (!(data->flags & MMC_DATA_READ)) {
- if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
- printf("\nThe SD card is locked. "
- "Can not write to a locked card.\n\n");
- return TIMEOUT;
- }
- esdhc_write32(®s->dsaddr, (u32)data->src);
- } else
- esdhc_write32(®s->dsaddr, (u32)data->dest);
-#endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
return 0;
}
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
static void check_and_invalidate_dcache_range
(struct mmc_cmd *cmd,
struct mmc_data *data) {
unsigned end = start+size ;
invalidate_dcache_range(start, end);
}
+#endif
+
/*
* Sends a command out on the bus. Takes the mmc pointer,
* a command pointer, and an optional data pointer.
goto out;
}
} while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
-#endif
+
if (data->flags & MMC_DATA_READ)
check_and_invalidate_dcache_range(cmd, data);
+#endif
}
out:
#endif
return TIMEOUT;
}
+ if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR)
+ return SWITCH_ERR;
return 0;
}
err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
if (err)
- return err;
+ return err == SWITCH_ERR ? 0 : err;
/* Now check to see that it worked */
err = mmc_send_ext_csd(mmc, ext_csd);
return 0;
}
+int mmc_select_hwpart(int dev_num, int hwpart)
+{
+ struct mmc *mmc = find_mmc_device(dev_num);
+ int ret;
+
+ if (!mmc)
+ return -1;
+
+ if (mmc->part_num == hwpart)
+ return 0;
+
+ if (mmc->part_config == MMCPART_NOAVAILABLE) {
+ printf("Card doesn't support part_switch\n");
+ return -1;
+ }
+
+ ret = mmc_switch_part(dev_num, hwpart);
+ if (ret)
+ return -1;
+
+ mmc->part_num = hwpart;
+
+ return 0;
+}
+
+
int mmc_switch_part(int dev_num, unsigned int part_num)
{
struct mmc *mmc = find_mmc_device(dev_num);
int mmc_init(struct mmc *mmc)
{
int err = IN_PROGRESS;
- unsigned start = get_timer(0);
+ unsigned start;
if (mmc->has_init)
return 0;
+
+ start = get_timer(0);
+
if (!mmc->init_in_progress)
err = mmc_start_init(mmc);
--- /dev/null
+/*
+ * Copyright 2014, Staubli Faverges
+ * Pierre Aubert
+ *
+ * eMMC- Replay Protected Memory Block
+ * According to JEDEC Standard No. 84-A441
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <mmc.h>
+#include <sha256.h>
+#include "mmc_private.h"
+
+/* Request codes */
+#define RPMB_REQ_KEY 1
+#define RPMB_REQ_WCOUNTER 2
+#define RPMB_REQ_WRITE_DATA 3
+#define RPMB_REQ_READ_DATA 4
+#define RPMB_REQ_STATUS 5
+
+/* Response code */
+#define RPMB_RESP_KEY 0x0100
+#define RPMB_RESP_WCOUNTER 0x0200
+#define RPMB_RESP_WRITE_DATA 0x0300
+#define RPMB_RESP_READ_DATA 0x0400
+
+/* Error codes */
+#define RPMB_OK 0
+#define RPMB_ERR_GENERAL 1
+#define RPMB_ERR_AUTH 2
+#define RPMB_ERR_COUNTER 3
+#define RPMB_ERR_ADDRESS 4
+#define RPMB_ERR_WRITE 5
+#define RPMB_ERR_READ 6
+#define RPMB_ERR_KEY 7
+#define RPMB_ERR_CNT_EXPIRED 0x80
+#define RPMB_ERR_MSK 0x7
+
+/* Sizes of RPMB data frame */
+#define RPMB_SZ_STUFF 196
+#define RPMB_SZ_MAC 32
+#define RPMB_SZ_DATA 256
+#define RPMB_SZ_NONCE 16
+
+#define SHA256_BLOCK_SIZE 64
+
+/* Error messages */
+static const char * const rpmb_err_msg[] = {
+ "",
+ "General failure",
+ "Authentication failure",
+ "Counter failure",
+ "Address failure",
+ "Write failure",
+ "Read failure",
+ "Authentication key not yet programmed",
+};
+
+
+/* Structure of RPMB data frame. */
+struct s_rpmb {
+ unsigned char stuff[RPMB_SZ_STUFF];
+ unsigned char mac[RPMB_SZ_MAC];
+ unsigned char data[RPMB_SZ_DATA];
+ unsigned char nonce[RPMB_SZ_NONCE];
+ unsigned long write_counter;
+ unsigned short address;
+ unsigned short block_count;
+ unsigned short result;
+ unsigned short request;
+};
+
+static int mmc_set_blockcount(struct mmc *mmc, unsigned int blockcount,
+ bool is_rel_write)
+{
+ struct mmc_cmd cmd = {0};
+
+ cmd.cmdidx = MMC_CMD_SET_BLOCK_COUNT;
+ cmd.cmdarg = blockcount & 0x0000FFFF;
+ if (is_rel_write)
+ cmd.cmdarg |= 1 << 31;
+ cmd.resp_type = MMC_RSP_R1;
+
+ return mmc_send_cmd(mmc, &cmd, NULL);
+}
+static int mmc_rpmb_request(struct mmc *mmc, const struct s_rpmb *s,
+ unsigned int count, bool is_rel_write)
+{
+ struct mmc_cmd cmd = {0};
+ struct mmc_data data;
+ int ret;
+
+ ret = mmc_set_blockcount(mmc, count, is_rel_write);
+ if (ret) {
+#ifdef CONFIG_MMC_RPMB_TRACE
+ printf("%s:mmc_set_blockcount-> %d\n", __func__, ret);
+#endif
+ return 1;
+ }
+
+ cmd.cmdidx = MMC_CMD_WRITE_MULTIPLE_BLOCK;
+ cmd.cmdarg = 0;
+ cmd.resp_type = MMC_RSP_R1b;
+
+ data.src = (const char *)s;
+ data.blocks = 1;
+ data.blocksize = MMC_MAX_BLOCK_LEN;
+ data.flags = MMC_DATA_WRITE;
+
+ ret = mmc_send_cmd(mmc, &cmd, &data);
+ if (ret) {
+#ifdef CONFIG_MMC_RPMB_TRACE
+ printf("%s:mmc_send_cmd-> %d\n", __func__, ret);
+#endif
+ return 1;
+ }
+ return 0;
+}
+static int mmc_rpmb_response(struct mmc *mmc, struct s_rpmb *s,
+ unsigned short expected)
+{
+ struct mmc_cmd cmd = {0};
+ struct mmc_data data;
+ int ret;
+
+ ret = mmc_set_blockcount(mmc, 1, false);
+ if (ret) {
+#ifdef CONFIG_MMC_RPMB_TRACE
+ printf("%s:mmc_set_blockcount-> %d\n", __func__, ret);
+#endif
+ return -1;
+ }
+ cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
+ cmd.cmdarg = 0;
+ cmd.resp_type = MMC_RSP_R1;
+
+ data.dest = (char *)s;
+ data.blocks = 1;
+ data.blocksize = MMC_MAX_BLOCK_LEN;
+ data.flags = MMC_DATA_READ;
+
+ ret = mmc_send_cmd(mmc, &cmd, &data);
+ if (ret) {
+#ifdef CONFIG_MMC_RPMB_TRACE
+ printf("%s:mmc_send_cmd-> %d\n", __func__, ret);
+#endif
+ return -1;
+ }
+ /* Check the response and the status */
+ if (be16_to_cpu(s->request) != expected) {
+#ifdef CONFIG_MMC_RPMB_TRACE
+ printf("%s:response= %x\n", __func__,
+ be16_to_cpu(s->request));
+#endif
+ return -1;
+ }
+ ret = be16_to_cpu(s->result);
+ if (ret) {
+ printf("%s %s\n", rpmb_err_msg[ret & RPMB_ERR_MSK],
+ (ret & RPMB_ERR_CNT_EXPIRED) ?
+ "Write counter has expired" : "");
+ }
+
+ /* Return the status of the command */
+ return ret;
+}
+static int mmc_rpmb_status(struct mmc *mmc, unsigned short expected)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct s_rpmb, rpmb_frame, 1);
+
+ memset(rpmb_frame, 0, sizeof(struct s_rpmb));
+ rpmb_frame->request = cpu_to_be16(RPMB_REQ_STATUS);
+ if (mmc_rpmb_request(mmc, rpmb_frame, 1, false))
+ return -1;
+
+ /* Read the result */
+ return mmc_rpmb_response(mmc, rpmb_frame, expected);
+}
+static void rpmb_hmac(unsigned char *key, unsigned char *buff, int len,
+ unsigned char *output)
+{
+ sha256_context ctx;
+ int i;
+ unsigned char k_ipad[SHA256_BLOCK_SIZE];
+ unsigned char k_opad[SHA256_BLOCK_SIZE];
+
+ sha256_starts(&ctx);
+
+ /* According to RFC 4634, the HMAC transform looks like:
+ SHA(K XOR opad, SHA(K XOR ipad, text))
+
+ where K is an n byte key.
+ ipad is the byte 0x36 repeated blocksize times
+ opad is the byte 0x5c repeated blocksize times
+ and text is the data being protected.
+ */
+
+ for (i = 0; i < RPMB_SZ_MAC; i++) {
+ k_ipad[i] = key[i] ^ 0x36;
+ k_opad[i] = key[i] ^ 0x5c;
+ }
+ /* remaining pad bytes are '\0' XOR'd with ipad and opad values */
+ for ( ; i < SHA256_BLOCK_SIZE; i++) {
+ k_ipad[i] = 0x36;
+ k_opad[i] = 0x5c;
+ }
+ sha256_update(&ctx, k_ipad, SHA256_BLOCK_SIZE);
+ sha256_update(&ctx, buff, len);
+ sha256_finish(&ctx, output);
+
+ /* Init context for second pass */
+ sha256_starts(&ctx);
+
+ /* start with outer pad */
+ sha256_update(&ctx, k_opad, SHA256_BLOCK_SIZE);
+
+ /* then results of 1st hash */
+ sha256_update(&ctx, output, RPMB_SZ_MAC);
+
+ /* finish up 2nd pass */
+ sha256_finish(&ctx, output);
+}
+int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *pcounter)
+{
+ int ret;
+ ALLOC_CACHE_ALIGN_BUFFER(struct s_rpmb, rpmb_frame, 1);
+
+ /* Fill the request */
+ memset(rpmb_frame, 0, sizeof(struct s_rpmb));
+ rpmb_frame->request = cpu_to_be16(RPMB_REQ_WCOUNTER);
+ if (mmc_rpmb_request(mmc, rpmb_frame, 1, false))
+ return -1;
+
+ /* Read the result */
+ ret = mmc_rpmb_response(mmc, rpmb_frame, RPMB_RESP_WCOUNTER);
+ if (ret)
+ return ret;
+
+ *pcounter = be32_to_cpu(rpmb_frame->write_counter);
+ return 0;
+}
+int mmc_rpmb_set_key(struct mmc *mmc, void *key)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct s_rpmb, rpmb_frame, 1);
+ /* Fill the request */
+ memset(rpmb_frame, 0, sizeof(struct s_rpmb));
+ rpmb_frame->request = cpu_to_be16(RPMB_REQ_KEY);
+ memcpy(rpmb_frame->mac, key, RPMB_SZ_MAC);
+
+ if (mmc_rpmb_request(mmc, rpmb_frame, 1, true))
+ return -1;
+
+ /* read the operation status */
+ return mmc_rpmb_status(mmc, RPMB_RESP_KEY);
+}
+int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
+ unsigned short cnt, unsigned char *key)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct s_rpmb, rpmb_frame, 1);
+ int i;
+
+ for (i = 0; i < cnt; i++) {
+ /* Fill the request */
+ memset(rpmb_frame, 0, sizeof(struct s_rpmb));
+ rpmb_frame->address = cpu_to_be16(blk + i);
+ rpmb_frame->request = cpu_to_be16(RPMB_REQ_READ_DATA);
+ if (mmc_rpmb_request(mmc, rpmb_frame, 1, false))
+ break;
+
+ /* Read the result */
+ if (mmc_rpmb_response(mmc, rpmb_frame, RPMB_RESP_READ_DATA))
+ break;
+
+ /* Check the HMAC if key is provided */
+ if (key) {
+ unsigned char ret_hmac[RPMB_SZ_MAC];
+
+ rpmb_hmac(key, rpmb_frame->data, 284, ret_hmac);
+ if (memcmp(ret_hmac, rpmb_frame->mac, RPMB_SZ_MAC)) {
+ printf("MAC error on block #%d\n", i);
+ break;
+ }
+ }
+ /* Copy data */
+ memcpy(addr + i * RPMB_SZ_DATA, rpmb_frame->data, RPMB_SZ_DATA);
+ }
+ return i;
+}
+int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
+ unsigned short cnt, unsigned char *key)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct s_rpmb, rpmb_frame, 1);
+ unsigned long wcount;
+ int i;
+
+ for (i = 0; i < cnt; i++) {
+ if (mmc_rpmb_get_counter(mmc, &wcount)) {
+ printf("Cannot read RPMB write counter\n");
+ break;
+ }
+
+ /* Fill the request */
+ memset(rpmb_frame, 0, sizeof(struct s_rpmb));
+ memcpy(rpmb_frame->data, addr + i * RPMB_SZ_DATA, RPMB_SZ_DATA);
+ rpmb_frame->address = cpu_to_be16(blk + i);
+ rpmb_frame->block_count = cpu_to_be16(1);
+ rpmb_frame->write_counter = cpu_to_be32(wcount);
+ rpmb_frame->request = cpu_to_be16(RPMB_REQ_WRITE_DATA);
+ /* Computes HMAC */
+ rpmb_hmac(key, rpmb_frame->data, 284, rpmb_frame->mac);
+
+ if (mmc_rpmb_request(mmc, rpmb_frame, 1, true))
+ break;
+
+ /* Get status */
+ if (mmc_rpmb_status(mmc, RPMB_RESP_WRITE_DATA))
+ break;
+ }
+ return i;
+}
DECLARE_GLOBAL_DATA_PTR;
-struct mmc_host mmc_host[MAX_HOSTS];
+struct mmc_host mmc_host[CONFIG_SYS_MMC_MAX_DEVICE];
#ifndef CONFIG_OF_CONTROL
#error "Please enable device tree support to use this driver"
void tegra_mmc_init(void)
{
- int node_list[MAX_HOSTS], count;
+ int node_list[CONFIG_SYS_MMC_MAX_DEVICE], count;
const void *blob = gd->fdt_blob;
debug("%s entry\n", __func__);
/* See if any Tegra124 MMC controllers are present */
count = fdtdec_find_aliases_for_id(blob, "sdhci",
- COMPAT_NVIDIA_TEGRA124_SDMMC, node_list, MAX_HOSTS);
+ COMPAT_NVIDIA_TEGRA124_SDMMC, node_list,
+ CONFIG_SYS_MMC_MAX_DEVICE);
debug("%s: count of Tegra124 sdhci nodes is %d\n", __func__, count);
if (process_nodes(blob, node_list, count)) {
printf("%s: Error processing T30 mmc node(s)!\n", __func__);
/* See if any Tegra30 MMC controllers are present */
count = fdtdec_find_aliases_for_id(blob, "sdhci",
- COMPAT_NVIDIA_TEGRA30_SDMMC, node_list, MAX_HOSTS);
+ COMPAT_NVIDIA_TEGRA30_SDMMC, node_list,
+ CONFIG_SYS_MMC_MAX_DEVICE);
debug("%s: count of T30 sdhci nodes is %d\n", __func__, count);
if (process_nodes(blob, node_list, count)) {
printf("%s: Error processing T30 mmc node(s)!\n", __func__);
/* Now look for any Tegra20 MMC controllers */
count = fdtdec_find_aliases_for_id(blob, "sdhci",
- COMPAT_NVIDIA_TEGRA20_SDMMC, node_list, MAX_HOSTS);
+ COMPAT_NVIDIA_TEGRA20_SDMMC, node_list,
+ CONFIG_SYS_MMC_MAX_DEVICE);
debug("%s: count of T20 sdhci nodes is %d\n", __func__, count);
if (process_nodes(blob, node_list, count)) {
printf("%s: Error processing T20 mmc node(s)!\n", __func__);
dat[byte_pos] ^= 1 << bit_pos;
printf("nand: bit-flip corrected @data=%d\n", byte_pos);
} else if (byte_pos < error_max) {
- read_ecc[byte_pos - SECTOR_BYTES] = 1 << bit_pos;
+ read_ecc[byte_pos - SECTOR_BYTES] ^= 1 << bit_pos;
printf("nand: bit-flip corrected @oob=%d\n", byte_pos -
SECTOR_BYTES);
} else {
obj-$(CONFIG_PPC_T2081) += t2080.o
obj-$(CONFIG_PPC_T4240) += t4240.o
obj-$(CONFIG_PPC_T4160) += t4240.o
+obj-$(CONFIG_PPC_T4080) += t4240.o
obj-$(CONFIG_PPC_B4420) += b4860.o
obj-$(CONFIG_PPC_B4860) += b4860.o
c45 = 0; /* clause 22 */
dev_addr = regnum & 0x1f;
clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
- } else {
+ } else
setbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
- setbits_be32(®s->mdio_stat, MDIO_STAT_HOLD_15_CLK);
- }
/* Wait till the bus is free */
while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
c45 = 0; /* clause 22 */
dev_addr = regnum & 0x1f;
clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
- } else {
+ } else
setbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
- setbits_be32(®s->mdio_stat, MDIO_STAT_HOLD_15_CLK);
- }
/* Wait till the bus is free */
while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
#define MIIM_VSC8514_18G_QSGMII 0x80e0
#define MIIM_VSC8514_18G_CMDSTAT 0x8000
+/* Vitesse VSC8664 Control/Status Register */
+#define MIIM_VSC8664_SERDES_AND_SIGDET 0x13
+#define MIIM_VSC8664_ADDITIONAL_DEV 0x16
+#define MIIM_VSC8664_EPHY_CON 0x17
+#define MIIM_VSC8664_LED_CON 0x1E
+
+#define PHY_EXT_PAGE_ACCESS_EXTENDED 0x0001
+
/* CIS8201 */
static int vitesse_config(struct phy_device *phydev)
{
return 0;
}
+static int vsc8664_config(struct phy_device *phydev)
+{
+ u32 val;
+
+ /* Enable MAC interface auto-negotiation */
+ phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON);
+ val |= (1 << 13);
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON, val);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
+ PHY_EXT_PAGE_ACCESS_EXTENDED);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET);
+ val |= (1 << 11);
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET, val);
+ phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
+
+ /* Enable LED blink */
+ val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON);
+ val &= ~(1 << 2);
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON, val);
+
+ genphy_config_aneg(phydev);
+
+ return 0;
+}
+
static struct phy_driver VSC8211_driver = {
.name = "Vitesse VSC8211",
.uid = 0xfc4b0,
.shutdown = &genphy_shutdown,
};
+static struct phy_driver VSC8664_driver = {
+ .name = "Vitesse VSC8664",
+ .uid = 0x70660,
+ .mask = 0xffff0,
+ .features = PHY_GBIT_FEATURES,
+ .config = &vsc8664_config,
+ .startup = &vitesse_startup,
+ .shutdown = &genphy_shutdown,
+};
+
/* Vitesse bought Cicada, so we'll put these here */
static struct phy_driver cis8201_driver = {
.name = "CIS8201",
phy_register(&VSC8574_driver);
phy_register(&VSC8514_driver);
phy_register(&VSC8662_driver);
+ phy_register(&VSC8664_driver);
phy_register(&cis8201_driver);
phy_register(&cis8204_driver);
u64 size)
{
u32 sz = (__ilog2_u64(size) - 1);
- u32 flag = PIWAR_EN | PIWAR_LOCAL |
- PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
+ u32 flag = 0;
+#else
+ u32 flag = PIWAR_LOCAL;
+#endif
+
+ flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
out_be32(&pi->pitar, r->phys_start >> 12);
out_be32(&pi->piwbar, r->bus_start >> 12);
# SPDX-License-Identifier: GPL-2.0+
#
+obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o
obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
--- /dev/null
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/ltc3676_pmic.h>
+
+int power_ltc3676_init(unsigned char bus)
+{
+ static const char name[] = "LTC3676_PMIC";
+ struct pmic *p = pmic_alloc();
+
+ if (!p) {
+ printf("%s: POWER allocation error!\n", __func__);
+ return -ENOMEM;
+ }
+
+ p->name = name;
+ p->interface = PMIC_I2C;
+ p->number_of_regs = LTC3676_NUM_OF_REGS;
+ p->hw.i2c.addr = CONFIG_POWER_LTC3676_I2C_ADDR;
+ p->hw.i2c.tx_num = 1;
+ p->bus = bus;
+
+ return 0;
+}
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
-int pmic_init(unsigned char bus)
+int power_pfuze100_init(unsigned char bus)
{
static const char name[] = "PFUZE100_PMIC";
struct pmic *p = pmic_alloc();
#include "asm/immap_qe.h"
#include "qe.h"
+#define MPC85xx_DEVDISR_QE_DISABLE 0x1
+
qe_map_t *qe_immr = NULL;
static qe_snum_t snums[QE_NUM_OF_SNUM];
size_t calc_size = sizeof(struct qe_firmware);
size_t length;
const struct qe_header *hdr;
-
+#ifdef CONFIG_DEEP_SLEEP
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
if (!firmware) {
printf("Invalid address\n");
return -EINVAL;
if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
(hdr->magic[2] != 'F')) {
printf("Not a microcode\n");
+#ifdef CONFIG_DEEP_SLEEP
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
+#endif
return -EPERM;
}
obj-$(CONFIG_USBDOWNLOAD_GADGET) += g_dnl.o
obj-$(CONFIG_DFU_FUNCTION) += f_dfu.o
obj-$(CONFIG_USB_GADGET_MASS_STORAGE) += f_mass_storage.o
+obj-$(CONFIG_CMD_FASTBOOT) += f_fastboot.o
endif
ifdef CONFIG_USB_ETHER
obj-y += ether.o
static struct usb_request *
ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags)
{
- struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
- return &ci_ep->req;
+ struct ci_req *ci_req;
+
+ ci_req = memalign(ARCH_DMA_MINALIGN, sizeof(*ci_req));
+ if (!ci_req)
+ return NULL;
+
+ INIT_LIST_HEAD(&ci_req->queue);
+ ci_req->b_buf = 0;
+
+ return &ci_req->req;
}
-static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req)
+static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *req)
{
- return;
+ struct ci_req *ci_req;
+
+ ci_req = container_of(req, struct ci_req, req);
+ if (ci_req->b_buf)
+ free(ci_req->b_buf);
+ free(ci_req);
}
static void ep_enable(int num, int in, int maxpacket)
return 0;
}
-static int ci_bounce(struct ci_ep *ep, int in)
+static int ci_bounce(struct ci_req *ci_req, int in)
{
- uint32_t addr = (uint32_t)ep->req.buf;
- uint32_t ba;
+ struct usb_request *req = &ci_req->req;
+ uint32_t addr = (uint32_t)req->buf;
+ uint32_t hwaddr;
+ uint32_t aligned_used_len;
/* Input buffer address is not aligned. */
if (addr & (ARCH_DMA_MINALIGN - 1))
goto align;
/* Input buffer length is not aligned. */
- if (ep->req.length & (ARCH_DMA_MINALIGN - 1))
+ if (req->length & (ARCH_DMA_MINALIGN - 1))
goto align;
/* The buffer is well aligned, only flush cache. */
- ep->b_len = ep->req.length;
- ep->b_buf = ep->req.buf;
+ ci_req->hw_len = req->length;
+ ci_req->hw_buf = req->buf;
goto flush;
align:
- /* Use internal buffer for small payloads. */
- if (ep->req.length <= 64) {
- ep->b_len = 64;
- ep->b_buf = ep->b_fast;
- } else {
- ep->b_len = roundup(ep->req.length, ARCH_DMA_MINALIGN);
- ep->b_buf = memalign(ARCH_DMA_MINALIGN, ep->b_len);
- if (!ep->b_buf)
+ if (ci_req->b_buf && req->length > ci_req->b_len) {
+ free(ci_req->b_buf);
+ ci_req->b_buf = 0;
+ }
+ if (!ci_req->b_buf) {
+ ci_req->b_len = roundup(req->length, ARCH_DMA_MINALIGN);
+ ci_req->b_buf = memalign(ARCH_DMA_MINALIGN, ci_req->b_len);
+ if (!ci_req->b_buf)
return -ENOMEM;
}
+ ci_req->hw_len = ci_req->b_len;
+ ci_req->hw_buf = ci_req->b_buf;
+
if (in)
- memcpy(ep->b_buf, ep->req.buf, ep->req.length);
+ memcpy(ci_req->hw_buf, req->buf, req->length);
flush:
- ba = (uint32_t)ep->b_buf;
- flush_dcache_range(ba, ba + ep->b_len);
+ hwaddr = (uint32_t)ci_req->hw_buf;
+ aligned_used_len = roundup(req->length, ARCH_DMA_MINALIGN);
+ flush_dcache_range(hwaddr, hwaddr + aligned_used_len);
return 0;
}
-static void ci_debounce(struct ci_ep *ep, int in)
+static void ci_debounce(struct ci_req *ci_req, int in)
{
- uint32_t addr = (uint32_t)ep->req.buf;
- uint32_t ba = (uint32_t)ep->b_buf;
+ struct usb_request *req = &ci_req->req;
+ uint32_t addr = (uint32_t)req->buf;
+ uint32_t hwaddr = (uint32_t)ci_req->hw_buf;
+ uint32_t aligned_used_len;
- if (in) {
- if (addr == ba)
- return; /* not a bounce */
- goto free;
- }
- invalidate_dcache_range(ba, ba + ep->b_len);
+ if (in)
+ return;
+
+ aligned_used_len = roundup(req->actual, ARCH_DMA_MINALIGN);
+ invalidate_dcache_range(hwaddr, hwaddr + aligned_used_len);
- if (addr == ba)
- return; /* not a bounce */
+ if (addr == hwaddr)
+ return; /* not a bounce */
- memcpy(ep->req.buf, ep->b_buf, ep->req.actual);
-free:
- /* Large payloads use allocated buffer, free it. */
- if (ep->b_buf != ep->b_fast)
- free(ep->b_buf);
+ memcpy(req->buf, ci_req->hw_buf, req->actual);
}
-static int ci_ep_queue(struct usb_ep *ep,
- struct usb_request *req, gfp_t gfp_flags)
+static void ci_ep_submit_next_request(struct ci_ep *ci_ep)
{
- struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
struct ept_queue_item *item;
struct ept_queue_head *head;
- int bit, num, len, in, ret;
+ int bit, num, len, in;
+ struct ci_req *ci_req;
+
+ ci_ep->req_primed = true;
+
num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
item = ci_get_qtd(num, in);
head = ci_get_qh(num, in);
- len = req->length;
- ret = ci_bounce(ci_ep, in);
- if (ret)
- return ret;
+ ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue);
+ len = ci_req->req.length;
item->next = TERMINATE;
item->info = INFO_BYTES(len) | INFO_IOC | INFO_ACTIVE;
- item->page0 = (uint32_t)ci_ep->b_buf;
- item->page1 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x1000;
- item->page2 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x2000;
- item->page3 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x3000;
- item->page4 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x4000;
+ item->page0 = (uint32_t)ci_req->hw_buf;
+ item->page1 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x1000;
+ item->page2 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x2000;
+ item->page3 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x3000;
+ item->page4 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x4000;
ci_flush_qtd(num);
head->next = (unsigned) item;
head->info = 0;
- DBG("ept%d %s queue len %x, buffer %p\n",
- num, in ? "in" : "out", len, ci_ep->b_buf);
+ DBG("ept%d %s queue len %x, req %p, buffer %p\n",
+ num, in ? "in" : "out", len, ci_req, ci_req->hw_buf);
ci_flush_qh(num);
if (in)
bit = EPT_RX(num);
writel(bit, &udc->epprime);
+}
+
+static int ci_ep_queue(struct usb_ep *ep,
+ struct usb_request *req, gfp_t gfp_flags)
+{
+ struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
+ struct ci_req *ci_req = container_of(req, struct ci_req, req);
+ int in, ret;
+ int __maybe_unused num;
+
+ num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+ in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
+
+ ret = ci_bounce(ci_req, in);
+ if (ret)
+ return ret;
+
+ DBG("ept%d %s pre-queue req %p, buffer %p\n",
+ num, in ? "in" : "out", ci_req, ci_req->hw_buf);
+ list_add_tail(&ci_req->queue, &ci_ep->queue);
+
+ if (!ci_ep->req_primed)
+ ci_ep_submit_next_request(ci_ep);
return 0;
}
{
struct ept_queue_item *item;
int num, in, len;
+ struct ci_req *ci_req;
+
num = ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
in = (ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
if (num == 0)
item = ci_get_qtd(num, in);
ci_invalidate_qtd(num);
+ len = (item->info >> 16) & 0x7fff;
if (item->info & 0xff)
printf("EP%d/%s FAIL info=%x pg0=%x\n",
num, in ? "in" : "out", item->info, item->page0);
- len = (item->info >> 16) & 0x7fff;
- ep->req.actual = ep->req.length - len;
- ci_debounce(ep, in);
+ ci_req = list_first_entry(&ep->queue, struct ci_req, queue);
+ list_del_init(&ci_req->queue);
+ ep->req_primed = false;
+
+ if (!list_empty(&ep->queue))
+ ci_ep_submit_next_request(ep);
+
+ ci_req->req.actual = ci_req->req.length - len;
+ ci_debounce(ci_req, in);
- DBG("ept%d %s complete %x\n",
- num, in ? "in" : "out", len);
- ep->req.complete(&ep->ep, &ep->req);
+ DBG("ept%d %s req %p, complete %x\n",
+ num, in ? "in" : "out", ci_req, len);
+ ci_req->req.complete(&ep->ep, &ci_req->req);
if (num == 0) {
- ep->req.length = 0;
- usb_ep_queue(&ep->ep, &ep->req, 0);
+ ci_req->req.length = 0;
+ usb_ep_queue(&ep->ep, &ci_req->req, 0);
ep->desc = &ep0_in_desc;
}
}
static void handle_setup(void)
{
- struct usb_request *req = &controller.ep[0].req;
+ struct ci_ep *ci_ep = &controller.ep[0];
+ struct ci_req *ci_req;
+ struct usb_request *req;
struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
struct ept_queue_head *head;
struct usb_ctrlrequest r;
int status = 0;
int num, in, _num, _in, i;
char *buf;
+
+ ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue);
+ req = &ci_req->req;
head = ci_get_qh(0, 0); /* EP0 OUT */
ci_invalidate_qh(0);
DBG("handle setup %s, %x, %x index %x value %x\n", reqname(r.bRequest),
r.bRequestType, r.bRequest, r.wIndex, r.wValue);
+ list_del_init(&ci_req->queue);
+ ci_ep->req_primed = false;
+
switch (SETUP(r.bRequestType, r.bRequest)) {
case SETUP(USB_RECIP_ENDPOINT, USB_REQ_CLEAR_FEATURE):
_num = r.wIndex & 15;
/* Init EP 0 */
memcpy(&controller.ep[0].ep, &ci_ep_init[0], sizeof(*ci_ep_init));
controller.ep[0].desc = &ep0_in_desc;
+ INIT_LIST_HEAD(&controller.ep[0].queue);
+ controller.ep[0].req_primed = false;
controller.gadget.ep0 = &controller.ep[0].ep;
INIT_LIST_HEAD(&controller.gadget.ep0->ep_list);
for (i = 1; i < NUM_ENDPOINTS; i++) {
memcpy(&controller.ep[i].ep, &ci_ep_init[1],
sizeof(*ci_ep_init));
+ INIT_LIST_HEAD(&controller.ep[i].queue);
+ controller.ep[i].req_primed = false;
list_add_tail(&controller.ep[i].ep.ep_list,
&controller.gadget.ep_list);
}
#define CTRL_TXT_BULK (2 << 18)
#define CTRL_RXT_BULK (2 << 2)
+struct ci_req {
+ struct usb_request req;
+ struct list_head queue;
+ /* Bounce buffer allocated if needed to align the transfer */
+ uint8_t *b_buf;
+ uint32_t b_len;
+ /* Buffer for the current transfer. Either req.buf/len or b_buf/len */
+ uint8_t *hw_buf;
+ uint32_t hw_len;
+};
+
struct ci_ep {
struct usb_ep ep;
struct list_head queue;
+ bool req_primed;
const struct usb_endpoint_descriptor *desc;
-
- struct usb_request req;
- uint8_t *b_buf;
- uint32_t b_len;
- uint8_t b_fast[64] __aligned(ARCH_DMA_MINALIGN);
};
struct ci_drv {
req->length, f_dfu->blk_seq_num);
}
+static inline int dfu_get_manifest_timeout(struct dfu_entity *dfu)
+{
+ return dfu->poll_timeout ? dfu->poll_timeout(dfu) :
+ DFU_MANIFEST_POLL_TIMEOUT;
+}
+
static void handle_getstatus(struct usb_request *req)
{
struct dfu_status *dstat = (struct dfu_status *)req->buf;
struct f_dfu *f_dfu = req->context;
+ struct dfu_entity *dfu = dfu_get_entity(f_dfu->altsetting);
dfu_set_poll_timeout(dstat, 0);
f_dfu->dfu_state = DFU_STATE_dfuMANIFEST;
break;
case DFU_STATE_dfuMANIFEST:
- dfu_set_poll_timeout(dstat, DFU_MANIFEST_POLL_TIMEOUT);
+ dfu_set_poll_timeout(dstat, dfu_get_manifest_timeout(dfu));
+ break;
default:
break;
}
--- /dev/null
+/*
+ * (C) Copyright 2008 - 2009
+ * Windriver, <www.windriver.com>
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * Copyright 2011 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
+ *
+ * Copyright 2014 Linaro, Ltd.
+ * Rob Herring <robh@kernel.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <errno.h>
+#include <malloc.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/composite.h>
+#include <linux/compiler.h>
+#include <version.h>
+#include <g_dnl.h>
+
+#define FASTBOOT_VERSION "0.4"
+
+#define FASTBOOT_INTERFACE_CLASS 0xff
+#define FASTBOOT_INTERFACE_SUB_CLASS 0x42
+#define FASTBOOT_INTERFACE_PROTOCOL 0x03
+
+#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_2_0 (0x0200)
+#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1 (0x0040)
+#define TX_ENDPOINT_MAXIMUM_PACKET_SIZE (0x0040)
+
+/* The 64 defined bytes plus \0 */
+#define RESPONSE_LEN (64 + 1)
+
+#define EP_BUFFER_SIZE 4096
+
+struct f_fastboot {
+ struct usb_function usb_function;
+
+ /* IN/OUT EP's and correspoinding requests */
+ struct usb_ep *in_ep, *out_ep;
+ struct usb_request *in_req, *out_req;
+};
+
+static inline struct f_fastboot *func_to_fastboot(struct usb_function *f)
+{
+ return container_of(f, struct f_fastboot, usb_function);
+}
+
+static struct f_fastboot *fastboot_func;
+static unsigned int download_size;
+static unsigned int download_bytes;
+
+static struct usb_endpoint_descriptor fs_ep_in = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_IN,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = TX_ENDPOINT_MAXIMUM_PACKET_SIZE,
+ .bInterval = 0x00,
+};
+
+static struct usb_endpoint_descriptor fs_ep_out = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_OUT,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = RX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1,
+ .bInterval = 0x00,
+};
+
+static struct usb_endpoint_descriptor hs_ep_out = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_OUT,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = RX_ENDPOINT_MAXIMUM_PACKET_SIZE_2_0,
+ .bInterval = 0x00,
+};
+
+static struct usb_interface_descriptor interface_desc = {
+ .bLength = USB_DT_INTERFACE_SIZE,
+ .bDescriptorType = USB_DT_INTERFACE,
+ .bInterfaceNumber = 0x00,
+ .bAlternateSetting = 0x00,
+ .bNumEndpoints = 0x02,
+ .bInterfaceClass = FASTBOOT_INTERFACE_CLASS,
+ .bInterfaceSubClass = FASTBOOT_INTERFACE_SUB_CLASS,
+ .bInterfaceProtocol = FASTBOOT_INTERFACE_PROTOCOL,
+};
+
+static struct usb_descriptor_header *fb_runtime_descs[] = {
+ (struct usb_descriptor_header *)&interface_desc,
+ (struct usb_descriptor_header *)&fs_ep_in,
+ (struct usb_descriptor_header *)&hs_ep_out,
+ NULL,
+};
+
+/*
+ * static strings, in UTF-8
+ */
+static const char fastboot_name[] = "Android Fastboot";
+
+static struct usb_string fastboot_string_defs[] = {
+ [0].s = fastboot_name,
+ { } /* end of list */
+};
+
+static struct usb_gadget_strings stringtab_fastboot = {
+ .language = 0x0409, /* en-us */
+ .strings = fastboot_string_defs,
+};
+
+static struct usb_gadget_strings *fastboot_strings[] = {
+ &stringtab_fastboot,
+ NULL,
+};
+
+static void rx_handler_command(struct usb_ep *ep, struct usb_request *req);
+
+static void fastboot_complete(struct usb_ep *ep, struct usb_request *req)
+{
+ int status = req->status;
+ if (!status)
+ return;
+ printf("status: %d ep '%s' trans: %d\n", status, ep->name, req->actual);
+}
+
+static int fastboot_bind(struct usb_configuration *c, struct usb_function *f)
+{
+ int id;
+ struct usb_gadget *gadget = c->cdev->gadget;
+ struct f_fastboot *f_fb = func_to_fastboot(f);
+
+ /* DYNAMIC interface numbers assignments */
+ id = usb_interface_id(c, f);
+ if (id < 0)
+ return id;
+ interface_desc.bInterfaceNumber = id;
+
+ id = usb_string_id(c->cdev);
+ if (id < 0)
+ return id;
+ fastboot_string_defs[0].id = id;
+ interface_desc.iInterface = id;
+
+ f_fb->in_ep = usb_ep_autoconfig(gadget, &fs_ep_in);
+ if (!f_fb->in_ep)
+ return -ENODEV;
+ f_fb->in_ep->driver_data = c->cdev;
+
+ f_fb->out_ep = usb_ep_autoconfig(gadget, &fs_ep_out);
+ if (!f_fb->out_ep)
+ return -ENODEV;
+ f_fb->out_ep->driver_data = c->cdev;
+
+ hs_ep_out.bEndpointAddress = fs_ep_out.bEndpointAddress;
+
+ return 0;
+}
+
+static void fastboot_unbind(struct usb_configuration *c, struct usb_function *f)
+{
+ memset(fastboot_func, 0, sizeof(*fastboot_func));
+}
+
+static void fastboot_disable(struct usb_function *f)
+{
+ struct f_fastboot *f_fb = func_to_fastboot(f);
+
+ usb_ep_disable(f_fb->out_ep);
+ usb_ep_disable(f_fb->in_ep);
+
+ if (f_fb->out_req) {
+ free(f_fb->out_req->buf);
+ usb_ep_free_request(f_fb->out_ep, f_fb->out_req);
+ f_fb->out_req = NULL;
+ }
+ if (f_fb->in_req) {
+ free(f_fb->in_req->buf);
+ usb_ep_free_request(f_fb->in_ep, f_fb->in_req);
+ f_fb->in_req = NULL;
+ }
+}
+
+static struct usb_request *fastboot_start_ep(struct usb_ep *ep)
+{
+ struct usb_request *req;
+
+ req = usb_ep_alloc_request(ep, 0);
+ if (!req)
+ return NULL;
+
+ req->length = EP_BUFFER_SIZE;
+ req->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, EP_BUFFER_SIZE);
+ if (!req->buf) {
+ usb_ep_free_request(ep, req);
+ return NULL;
+ }
+
+ memset(req->buf, 0, req->length);
+ return req;
+}
+
+static int fastboot_set_alt(struct usb_function *f,
+ unsigned interface, unsigned alt)
+{
+ int ret;
+ struct usb_composite_dev *cdev = f->config->cdev;
+ struct usb_gadget *gadget = cdev->gadget;
+ struct f_fastboot *f_fb = func_to_fastboot(f);
+
+ debug("%s: func: %s intf: %d alt: %d\n",
+ __func__, f->name, interface, alt);
+
+ /* make sure we don't enable the ep twice */
+ if (gadget->speed == USB_SPEED_HIGH)
+ ret = usb_ep_enable(f_fb->out_ep, &hs_ep_out);
+ else
+ ret = usb_ep_enable(f_fb->out_ep, &fs_ep_out);
+ if (ret) {
+ puts("failed to enable out ep\n");
+ return ret;
+ }
+
+ f_fb->out_req = fastboot_start_ep(f_fb->out_ep);
+ if (!f_fb->out_req) {
+ puts("failed to alloc out req\n");
+ ret = -EINVAL;
+ goto err;
+ }
+ f_fb->out_req->complete = rx_handler_command;
+
+ ret = usb_ep_enable(f_fb->in_ep, &fs_ep_in);
+ if (ret) {
+ puts("failed to enable in ep\n");
+ goto err;
+ }
+
+ f_fb->in_req = fastboot_start_ep(f_fb->in_ep);
+ if (!f_fb->in_req) {
+ puts("failed alloc req in\n");
+ ret = -EINVAL;
+ goto err;
+ }
+ f_fb->in_req->complete = fastboot_complete;
+
+ ret = usb_ep_queue(f_fb->out_ep, f_fb->out_req, 0);
+ if (ret)
+ goto err;
+
+ return 0;
+err:
+ fastboot_disable(f);
+ return ret;
+}
+
+static int fastboot_add(struct usb_configuration *c)
+{
+ struct f_fastboot *f_fb = fastboot_func;
+ int status;
+
+ debug("%s: cdev: 0x%p\n", __func__, c->cdev);
+
+ if (!f_fb) {
+ f_fb = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*f_fb));
+ if (!f_fb)
+ return -ENOMEM;
+
+ fastboot_func = f_fb;
+ memset(f_fb, 0, sizeof(*f_fb));
+ }
+
+ f_fb->usb_function.name = "f_fastboot";
+ f_fb->usb_function.hs_descriptors = fb_runtime_descs;
+ f_fb->usb_function.bind = fastboot_bind;
+ f_fb->usb_function.unbind = fastboot_unbind;
+ f_fb->usb_function.set_alt = fastboot_set_alt;
+ f_fb->usb_function.disable = fastboot_disable;
+ f_fb->usb_function.strings = fastboot_strings;
+
+ status = usb_add_function(c, &f_fb->usb_function);
+ if (status) {
+ free(f_fb);
+ fastboot_func = f_fb;
+ }
+
+ return status;
+}
+DECLARE_GADGET_BIND_CALLBACK(usb_dnl_fastboot, fastboot_add);
+
+int fastboot_tx_write(const char *buffer, unsigned int buffer_size)
+{
+ struct usb_request *in_req = fastboot_func->in_req;
+ int ret;
+
+ memcpy(in_req->buf, buffer, buffer_size);
+ in_req->length = buffer_size;
+ ret = usb_ep_queue(fastboot_func->in_ep, in_req, 0);
+ if (ret)
+ printf("Error %d on queue\n", ret);
+ return 0;
+}
+
+static int fastboot_tx_write_str(const char *buffer)
+{
+ return fastboot_tx_write(buffer, strlen(buffer));
+}
+
+static void compl_do_reset(struct usb_ep *ep, struct usb_request *req)
+{
+ do_reset(NULL, 0, 0, NULL);
+}
+
+static void cb_reboot(struct usb_ep *ep, struct usb_request *req)
+{
+ fastboot_func->in_req->complete = compl_do_reset;
+ fastboot_tx_write_str("OKAY");
+}
+
+static int strcmp_l1(const char *s1, const char *s2)
+{
+ if (!s1 || !s2)
+ return -1;
+ return strncmp(s1, s2, strlen(s1));
+}
+
+static void cb_getvar(struct usb_ep *ep, struct usb_request *req)
+{
+ char *cmd = req->buf;
+ char response[RESPONSE_LEN];
+ const char *s;
+
+ strcpy(response, "OKAY");
+ strsep(&cmd, ":");
+ if (!cmd) {
+ fastboot_tx_write_str("FAILmissing var");
+ return;
+ }
+
+ if (!strcmp_l1("version", cmd)) {
+ strncat(response, FASTBOOT_VERSION, sizeof(response));
+ } else if (!strcmp_l1("bootloader-version", cmd)) {
+ strncat(response, U_BOOT_VERSION, sizeof(response));
+ } else if (!strcmp_l1("downloadsize", cmd)) {
+ char str_num[12];
+
+ sprintf(str_num, "%08x", CONFIG_USB_FASTBOOT_BUF_SIZE);
+ strncat(response, str_num, sizeof(response));
+ } else if (!strcmp_l1("serialno", cmd)) {
+ s = getenv("serial#");
+ if (s)
+ strncat(response, s, sizeof(response));
+ else
+ strcpy(response, "FAILValue not set");
+ } else {
+ strcpy(response, "FAILVariable not implemented");
+ }
+ fastboot_tx_write_str(response);
+}
+
+static unsigned int rx_bytes_expected(void)
+{
+ int rx_remain = download_size - download_bytes;
+ if (rx_remain < 0)
+ return 0;
+ if (rx_remain > EP_BUFFER_SIZE)
+ return EP_BUFFER_SIZE;
+ return rx_remain;
+}
+
+#define BYTES_PER_DOT 0x20000
+static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req)
+{
+ char response[RESPONSE_LEN];
+ unsigned int transfer_size = download_size - download_bytes;
+ const unsigned char *buffer = req->buf;
+ unsigned int buffer_size = req->actual;
+
+ if (req->status != 0) {
+ printf("Bad status: %d\n", req->status);
+ return;
+ }
+
+ if (buffer_size < transfer_size)
+ transfer_size = buffer_size;
+
+ memcpy((void *)CONFIG_USB_FASTBOOT_BUF_ADDR + download_bytes,
+ buffer, transfer_size);
+
+ download_bytes += transfer_size;
+
+ /* Check if transfer is done */
+ if (download_bytes >= download_size) {
+ /*
+ * Reset global transfer variable, keep download_bytes because
+ * it will be used in the next possible flashing command
+ */
+ download_size = 0;
+ req->complete = rx_handler_command;
+ req->length = EP_BUFFER_SIZE;
+
+ sprintf(response, "OKAY");
+ fastboot_tx_write_str(response);
+
+ printf("\ndownloading of %d bytes finished\n", download_bytes);
+ } else {
+ req->length = rx_bytes_expected();
+ if (req->length < ep->maxpacket)
+ req->length = ep->maxpacket;
+ }
+
+ if (download_bytes && !(download_bytes % BYTES_PER_DOT)) {
+ putc('.');
+ if (!(download_bytes % (74 * BYTES_PER_DOT)))
+ putc('\n');
+ }
+ req->actual = 0;
+ usb_ep_queue(ep, req, 0);
+}
+
+static void cb_download(struct usb_ep *ep, struct usb_request *req)
+{
+ char *cmd = req->buf;
+ char response[RESPONSE_LEN];
+
+ strsep(&cmd, ":");
+ download_size = simple_strtoul(cmd, NULL, 16);
+ download_bytes = 0;
+
+ printf("Starting download of %d bytes\n", download_size);
+
+ if (0 == download_size) {
+ sprintf(response, "FAILdata invalid size");
+ } else if (download_size > CONFIG_USB_FASTBOOT_BUF_SIZE) {
+ download_size = 0;
+ sprintf(response, "FAILdata too large");
+ } else {
+ sprintf(response, "DATA%08x", download_size);
+ req->complete = rx_handler_dl_image;
+ req->length = rx_bytes_expected();
+ if (req->length < ep->maxpacket)
+ req->length = ep->maxpacket;
+ }
+ fastboot_tx_write_str(response);
+}
+
+static void do_bootm_on_complete(struct usb_ep *ep, struct usb_request *req)
+{
+ char boot_addr_start[12];
+ char *bootm_args[] = { "bootm", boot_addr_start, NULL };
+
+ puts("Booting kernel..\n");
+
+ sprintf(boot_addr_start, "0x%lx", load_addr);
+ do_bootm(NULL, 0, 2, bootm_args);
+
+ /* This only happens if image is somehow faulty so we start over */
+ do_reset(NULL, 0, 0, NULL);
+}
+
+static void cb_boot(struct usb_ep *ep, struct usb_request *req)
+{
+ fastboot_func->in_req->complete = do_bootm_on_complete;
+ fastboot_tx_write_str("OKAY");
+}
+
+struct cmd_dispatch_info {
+ char *cmd;
+ void (*cb)(struct usb_ep *ep, struct usb_request *req);
+};
+
+static const struct cmd_dispatch_info cmd_dispatch_info[] = {
+ {
+ .cmd = "reboot",
+ .cb = cb_reboot,
+ }, {
+ .cmd = "getvar:",
+ .cb = cb_getvar,
+ }, {
+ .cmd = "download:",
+ .cb = cb_download,
+ }, {
+ .cmd = "boot",
+ .cb = cb_boot,
+ },
+};
+
+static void rx_handler_command(struct usb_ep *ep, struct usb_request *req)
+{
+ char *cmdbuf = req->buf;
+ void (*func_cb)(struct usb_ep *ep, struct usb_request *req) = NULL;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(cmd_dispatch_info); i++) {
+ if (!strcmp_l1(cmd_dispatch_info[i].cmd, cmdbuf)) {
+ func_cb = cmd_dispatch_info[i].cb;
+ break;
+ }
+ }
+
+ if (!func_cb)
+ fastboot_tx_write_str("FAILunknown command");
+ else
+ func_cb(ep, req);
+
+ if (req->status == 0) {
+ *cmdbuf = '\0';
+ req->actual = 0;
+ usb_ep_queue(ep, req, 0);
+ }
+}
}
/*
- * To store last "packet" DFU storage backend requires dfu_write with
- * size parameter equal to 0
+ * To store last "packet" or write file from buffer to filesystem
+ * DFU storage backend requires dfu_flush
*
* This also frees memory malloc'ed by dfu_get_buf(), so no explicit
* need fo call dfu_free_buf() is needed.
*/
- ret = dfu_write(dfu_entity, transfer_buffer, 0, cnt);
- if (ret)
- error("DFU write failed [%d] cnt: %d", ret, cnt);
-
ret = dfu_flush(dfu_entity, transfer_buffer, 0, cnt);
- if (ret) {
+ if (ret)
error("DFU flush failed!");
- return ret;
- }
return ret;
}
#define DELAYED_STATUS (EP0_BUFSIZE + 999) /* An impossibly large value */
/* Number of buffers we will use. 2 is enough for double-buffering */
-#ifndef CONFIG_CI_UDC
#define FSG_NUM_BUFFERS 2
-#else
-#define FSG_NUM_BUFFERS 1 /* ci_udc only allows 1 req per ep at present */
-#endif
/* Default size of buffer length. */
#define FSG_BUFLEN ((u32)16384)
if (!strncmp(phy_type, "utmi", 4)) {
#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
- setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI);
- setbits_be32(&ehci->control, UTMI_PHY_EN);
+ clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+ PHY_CLK_SEL_UTMI);
+ clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+ UTMI_PHY_EN);
udelay(1000); /* delay required for PHY Clk to appear */
#endif
out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
- setbits_be32(&ehci->control, USB_EN);
+ clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+ USB_EN);
} else {
- setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
- clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN);
+ clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+ PHY_CLK_SEL_ULPI);
+ clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
+ CONTROL_REGISTER_W1C_MASK, USB_EN);
udelay(1000); /* delay required for PHY Clk to appear */
if (!usb_phy_clk_valid(ehci))
return -EINVAL;
unsigned enabled:1; /* 1 to enable, 0 to disable */
unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
unsigned initialized:1; /* has this port already been initialized? */
+ enum usb_init_type init_type;
enum dr_mode dr_mode; /* dual role mode */
enum periph_id periph_id;/* peripheral id */
struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */
return PORTSC_PSPD(reg);
}
-/* Put the port into host mode */
-static void set_host_mode(struct fdt_usb *config)
+/* Set up VBUS for host/device mode */
+static void set_up_vbus(struct fdt_usb *config, enum usb_init_type init)
{
/*
- * If we are an OTG port, check if remote host is driving VBus and
- * bail out in this case.
+ * If we are an OTG port initializing in host mode,
+ * check if remote host is driving VBus and bail out in this case.
*/
- if (config->dr_mode == DR_MODE_OTG &&
- (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS))
+ if (init == USB_INIT_HOST &&
+ config->dr_mode == DR_MODE_OTG &&
+ (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) {
+ printf("tegrausb: VBUS input active; not enabling as host\n");
return;
+ }
- /*
- * If not driving, we set the GPIO to enable VBUS. We assume
- * that the pinmux is set up correctly for this.
- */
if (fdt_gpio_isvalid(&config->vbus_gpio)) {
+ int vbus_value;
+
fdtdec_setup_gpio(&config->vbus_gpio);
- gpio_direction_output(config->vbus_gpio.gpio,
- (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ?
- 0 : 1);
- debug("set_host_mode: GPIO %d %s\n", config->vbus_gpio.gpio,
- (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ?
- "low" : "high");
+
+ vbus_value = (init == USB_INIT_HOST) ^
+ !!(config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW);
+ gpio_direction_output(config->vbus_gpio.gpio, vbus_value);
+
+ debug("set_up_vbus: GPIO %d %d\n", config->vbus_gpio.gpio,
+ vbus_value);
}
}
return timing;
}
+/* select the PHY to use with a USB controller */
+static void init_phy_mux(struct fdt_usb *config, uint pts,
+ enum usb_init_type init)
+{
+ struct usb_ctlr *usbctlr = config->reg;
+
+#if defined(CONFIG_TEGRA20)
+ if (config->periph_id == PERIPH_ID_USBD) {
+ clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK,
+ PTS_UTMI << PTS1_SHIFT);
+ clrbits_le32(&usbctlr->port_sc1, STS1);
+ } else {
+ clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
+ PTS_UTMI << PTS_SHIFT);
+ clrbits_le32(&usbctlr->port_sc1, STS);
+ }
+#else
+ /* Set to Host mode (if applicable) after Controller Reset was done */
+ clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC,
+ (init == USB_INIT_HOST) ? USBMODE_CM_HC : 0);
+ /*
+ * Select PHY interface after setting host mode.
+ * For device mode, the ordering requirement is not an issue, since
+ * only the first USB controller supports device mode, and that USB
+ * controller can only talk to a UTMI PHY, so the PHY selection is
+ * already made at reset time, so this write is a no-op.
+ */
+ clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK,
+ pts << PTS_SHIFT);
+ clrbits_le32(&usbctlr->hostpc1_devlc, STS);
+#endif
+}
+
/* set up the UTMI USB controller with the parameters provided */
-static int init_utmi_usb_controller(struct fdt_usb *config)
+static int init_utmi_usb_controller(struct fdt_usb *config,
+ enum usb_init_type init)
{
- u32 val;
+ u32 b_sess_valid_mask, val;
int loop_count;
const unsigned *timing;
struct usb_ctlr *usbctlr = config->reg;
/* Follow the crystal clock disable by >100ns delay */
udelay(1);
+ b_sess_valid_mask = (VBUS_B_SESS_VLD_SW_VALUE | VBUS_B_SESS_VLD_SW_EN);
+ clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask,
+ (init == USB_INIT_DEVICE) ? b_sess_valid_mask : 0);
+
/*
* To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
* mux must be switched to actually use a_sess_vld threshold.
clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
/* Select UTMI parallel interface */
-#if defined(CONFIG_TEGRA20)
- if (config->periph_id == PERIPH_ID_USBD) {
- clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK,
- PTS_UTMI << PTS1_SHIFT);
- clrbits_le32(&usbctlr->port_sc1, STS1);
- } else {
- clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
- PTS_UTMI << PTS_SHIFT);
- clrbits_le32(&usbctlr->port_sc1, STS);
- }
-#else
- clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK,
- PTS_UTMI << PTS_SHIFT);
- clrbits_le32(&usbctlr->hostpc1_devlc, STS);
-#endif
+ init_phy_mux(config, PTS_UTMI, init);
/* Deassert power down state */
clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
#endif
/* set up the ULPI USB controller with the parameters provided */
-static int init_ulpi_usb_controller(struct fdt_usb *config)
+static int init_ulpi_usb_controller(struct fdt_usb *config,
+ enum usb_init_type init)
{
u32 val;
int loop_count;
ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP);
/* Select ULPI parallel interface */
-#if defined(CONFIG_TEGRA20)
- clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
- PTS_ULPI << PTS_SHIFT);
-#else
- clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK,
- PTS_ULPI << PTS_SHIFT);
-#endif
+ init_phy_mux(config, PTS_ULPI, init);
/* enable ULPI transceiver */
setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
return 0;
}
#else
-static int init_ulpi_usb_controller(struct fdt_usb *config)
+static int init_ulpi_usb_controller(struct fdt_usb *config,
+ enum usb_init_type init)
{
printf("No code to set up ULPI controller, please enable"
"CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT");
config = &port[index];
+ switch (init) {
+ case USB_INIT_HOST:
+ switch (config->dr_mode) {
+ case DR_MODE_HOST:
+ case DR_MODE_OTG:
+ break;
+ default:
+ printf("tegrausb: Invalid dr_mode %d for host mode\n",
+ config->dr_mode);
+ return -1;
+ }
+ break;
+ case USB_INIT_DEVICE:
+ if (config->periph_id != PERIPH_ID_USBD) {
+ printf("tegrausb: Device mode only supported on first USB controller\n");
+ return -1;
+ }
+ if (!config->utmi) {
+ printf("tegrausb: Device mode only supported with UTMI PHY\n");
+ return -1;
+ }
+ switch (config->dr_mode) {
+ case DR_MODE_DEVICE:
+ case DR_MODE_OTG:
+ break;
+ default:
+ printf("tegrausb: Invalid dr_mode %d for device mode\n",
+ config->dr_mode);
+ return -1;
+ }
+ break;
+ default:
+ printf("tegrausb: Unknown USB_INIT_* %d\n", init);
+ return -1;
+ }
+
/* skip init, if the port is already initialized */
- if (config->initialized)
+ if (config->initialized && config->init_type == init)
goto success;
- if (config->utmi && init_utmi_usb_controller(config)) {
+ if (config->utmi && init_utmi_usb_controller(config, init)) {
printf("tegrausb: Cannot init port %d\n", index);
return -1;
}
- if (config->ulpi && init_ulpi_usb_controller(config)) {
+ if (config->ulpi && init_ulpi_usb_controller(config, init)) {
printf("tegrausb: Cannot init port %d\n", index);
return -1;
}
- set_host_mode(config);
+ set_up_vbus(config, init);
config->initialized = 1;
+ config->init_type = init;
success:
usbctlr = config->reg;
*hccr = (struct ehci_hccr *)&usbctlr->cap_length;
*hcor = (struct ehci_hcor *)&usbctlr->usb_cmd;
- if (controller->has_hostpc) {
- /* Set to Host mode after Controller Reset was done */
- clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC,
- USBMODE_CM_HC);
- /* Select UTMI parallel interface after setting host mode */
- if (config->utmi) {
- clrsetbits_le32((char *)&usbctlr->usb_cmd +
- HOSTPC1_DEVLC, PTS_MASK,
- PTS_UTMI << PTS_SHIFT);
- clrbits_le32((char *)&usbctlr->usb_cmd +
- HOSTPC1_DEVLC, STS);
- }
- }
return 0;
}
} else
request = NULL;
+ /* send it out, triggering a "txpktrdy cleared" irq */
+ musb_ep_select(musb->mregs, 0);
+ musb_writew(regs, MUSB_CSR0, csr);
+
/* report completions as soon as the fifo's loaded; there's no
* win in waiting till this last packet gets acked. (other than
* very precise fault reporting, needed by USB TMC; possible with
return;
musb->ackpend = 0;
}
-
- /* send it out, triggering a "txpktrdy cleared" irq */
- musb_ep_select(musb->mregs, 0);
- musb_writew(regs, MUSB_CSR0, csr);
}
/*
obj-$(CONFIG_VIDEO_COREBOOT) += coreboot_fb.o
obj-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o
obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
+obj-$(CONFIG_VIDEO_IMX25LCDC) += imx25lcdc.o videomodes.o
obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
obj-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
--- /dev/null
+/*
+ * (C) Copyright 2011
+ * Matthias Weisser <weisserm@arcor.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * imx25lcdc.c - Graphic interface for i.MX25 lcd controller
+ */
+
+#include <common.h>
+
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <video_fb.h>
+#include "videomodes.h"
+
+/*
+ * 4MB (at the end of system RAM)
+ */
+#define VIDEO_MEM_SIZE 0x400000
+
+#define FB_SYNC_CLK_INV (1<<16) /* pixel clock inverted */
+
+/*
+ * Graphic Device
+ */
+static GraphicDevice imx25fb;
+
+void *video_hw_init(void)
+{
+ struct lcdc_regs *lcdc = (struct lcdc_regs *)IMX_LCDC_BASE;
+ struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+ GraphicDevice *pGD = &imx25fb;
+ char *s;
+ u32 *videomem;
+
+ memset(pGD, 0, sizeof(GraphicDevice));
+
+ pGD->gdfIndex = GDF_16BIT_565RGB;
+ pGD->gdfBytesPP = 2;
+ pGD->memSize = VIDEO_MEM_SIZE;
+ pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE;
+
+ videomem = (u32 *)pGD->frameAdrs;
+
+ s = getenv("videomode");
+ if (s != NULL) {
+ struct ctfb_res_modes var_mode;
+ u32 lsr, lpcr, lhcr, lvcr;
+ unsigned long div;
+ int bpp;
+
+ /* Disable all clocks of the LCDC */
+ writel(readl(&ccm->cgr0) & ~((1<<7) | (1<<24)), &ccm->cgr0);
+ writel(readl(&ccm->cgr1) & ~(1<<29), &ccm->cgr1);
+
+ bpp = video_get_params(&var_mode, s);
+
+ if (bpp == 0) {
+ var_mode.xres = 320;
+ var_mode.yres = 240;
+ var_mode.pixclock = 154000;
+ var_mode.left_margin = 68;
+ var_mode.right_margin = 20;
+ var_mode.upper_margin = 4;
+ var_mode.lower_margin = 18;
+ var_mode.hsync_len = 40;
+ var_mode.vsync_len = 6;
+ var_mode.sync = 0;
+ var_mode.vmode = 0;
+ }
+
+ /* Fill memory with white */
+ memset(videomem, 0xFF, var_mode.xres * var_mode.yres * 2);
+
+ imx25fb.winSizeX = var_mode.xres;
+ imx25fb.winSizeY = var_mode.yres;
+
+ /* LCD base clock is 66.6MHZ. We do calculations in kHz */
+ div = 66000 / (1000000000L / var_mode.pixclock);
+ if (div > 63)
+ div = 63;
+ if (0 == div)
+ div = 1;
+
+ lsr = ((var_mode.xres / 16) << 20) |
+ var_mode.yres;
+ lpcr = (1 << 31) |
+ (1 << 30) |
+ (5 << 25) |
+ (1 << 23) |
+ (1 << 22) |
+ (1 << 19) |
+ (1 << 7) |
+ div;
+ lhcr = (var_mode.right_margin << 0) |
+ (var_mode.left_margin << 8) |
+ (var_mode.hsync_len << 26);
+
+ lvcr = (var_mode.lower_margin << 0) |
+ (var_mode.upper_margin << 8) |
+ (var_mode.vsync_len << 26);
+
+ writel((uint32_t)videomem, &lcdc->lssar);
+ writel(lsr, &lcdc->lsr);
+ writel(var_mode.xres * 2 / 4, &lcdc->lvpwr);
+ writel(lpcr, &lcdc->lpcr);
+ writel(lhcr, &lcdc->lhcr);
+ writel(lvcr, &lcdc->lvcr);
+ writel(0x00040060, &lcdc->ldcr);
+
+ writel(0xA90300, &lcdc->lpccr);
+
+ /* Ensable all clocks of the LCDC */
+ writel(readl(&ccm->cgr0) | ((1<<7) | (1<<24)), &ccm->cgr0);
+ writel(readl(&ccm->cgr1) | (1<<29), &ccm->cgr1);
+ }
+
+ return pGD;
+}
--- /dev/null
+/*
+ * This is from the Android Project,
+ * Repository: https://android.googlesource.com/platform/bootable/bootloader/legacy
+ * File: include/boot/bootimg.h
+ * Commit: 4205b865141ff2e255fe1d3bd16de18e217ef06a
+ *
+ * Copyright (C) 2008 The Android Open Source Project
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#ifndef _ANDROID_IMAGE_H_
+#define _ANDROID_IMAGE_H_
+
+#define ANDR_BOOT_MAGIC "ANDROID!"
+#define ANDR_BOOT_MAGIC_SIZE 8
+#define ANDR_BOOT_NAME_SIZE 16
+#define ANDR_BOOT_ARGS_SIZE 512
+
+struct andr_img_hdr {
+ char magic[ANDR_BOOT_MAGIC_SIZE];
+
+ u32 kernel_size; /* size in bytes */
+ u32 kernel_addr; /* physical load addr */
+
+ u32 ramdisk_size; /* size in bytes */
+ u32 ramdisk_addr; /* physical load addr */
+
+ u32 second_size; /* size in bytes */
+ u32 second_addr; /* physical load addr */
+
+ u32 tags_addr; /* physical addr for kernel tags */
+ u32 page_size; /* flash page size we assume */
+ u32 unused[2]; /* future expansion: should be 0 */
+
+ char name[ANDR_BOOT_NAME_SIZE]; /* asciiz product name */
+
+ char cmdline[ANDR_BOOT_ARGS_SIZE];
+
+ u32 id[8]; /* timestamp / checksum / sha1 / etc */
+};
+
+/*
+ * +-----------------+
+ * | boot header | 1 page
+ * +-----------------+
+ * | kernel | n pages
+ * +-----------------+
+ * | ramdisk | m pages
+ * +-----------------+
+ * | second stage | o pages
+ * +-----------------+
+ *
+ * n = (kernel_size + page_size - 1) / page_size
+ * m = (ramdisk_size + page_size - 1) / page_size
+ * o = (second_size + page_size - 1) / page_size
+ *
+ * 0. all entities are page_size aligned in flash
+ * 1. kernel and ramdisk are required (size != 0)
+ * 2. second is optional (second_size == 0 -> no second)
+ * 3. load each element (kernel, ramdisk, second) at
+ * the specified physical address (kernel_addr, etc)
+ * 4. prepare tags at tag_addr. kernel_args[] is
+ * appended to the kernel commandline in the tags.
+ * 5. r0 = 0, r1 = MACHINE_TYPE, r2 = tags_addr
+ * 6. if second_size != 0: jump to second_addr
+ * else: jump to kernel_addr
+ */
+#endif
#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260)
void cpu_init_f (volatile immap_t *immr);
#endif
-#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx)
+#if defined(CONFIG_4xx) || defined(CONFIG_MCF52x2) || defined(CONFIG_MPC86xx)
void cpu_init_f (void);
#endif
+#ifdef CONFIG_MPC85xx
+ulong cpu_init_f(void);
+#endif
int cpu_init_r (void);
#if defined(CONFIG_MPC8260)
int had_ctrlc (void); /* have we had a Control-C since last clear? */
void clear_ctrlc (void); /* clear the Control-C condition */
int disable_ctrlc (int); /* 1 to disable, 0 to enable Control-C detect */
-
+int confirm_yesno(void); /* 1 if input is "y", "Y", "yes" or "YES" */
/*
* STDIO based functions (can always be used)
*/
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
/*
* B4860 QDS board configuration file
*/
#define IDT_SERDES1_ADDRESS 0x6E
#define IDT_SERDES2_ADDRESS 0x6C
+/* Voltage monitor on channel 2*/
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+#define I2C_VOL_MONITOR_ADDR 0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+
+#define CONFIG_ZM7300
+#define I2C_MUX_CH_DPM 0xa
+#define I2C_DPM_ADDR 0x28
+
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
"ramdiskfile=b4860qds/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=b4860qds/b4860qds.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
/* For emulation this causes u-boot to jump to the start of the proof point
app code automatically */
#endif
/* Set up IFC registers for boot location NOR/NAND */
-#if defined(CONFIG_NAND)
+#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DATE
#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_MII
#define CONFIG_CMD_BEDBUG
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#include "../board/freescale/common/ics307_clk.h"
#ifdef CONFIG_36BIT
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
#include "../board/freescale/common/ics307_clk.h"
#ifdef CONFIG_36BIT
#endif
#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
/* High Level Configuration Options */
#define CONFIG_MPC8641 1 /* MPC8641 specific */
#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_PCI
#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_I2C
#undef CONFIG_WATCHDOG
#define CONFIG_CMD_PCI
#define CONFIG_CMD_I2C
#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_USB
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#ifdef CONFIG_P1011RDB
#define CONFIG_P1011
+#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
#ifdef CONFIG_P1020RDB
#define CONFIG_P1020
+#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
#ifdef CONFIG_P2010RDB
#define CONFIG_P2010
+#define CONFIG_SYS_L2_SIZE (512 << 10)
#endif
#ifdef CONFIG_P2020RDB
#define CONFIG_P2020
-#endif
-
-#ifdef CONFIG_NAND
-#define CONFIG_NAND_U_BOOT 1
-#define CONFIG_RAMBOOT_NAND 1
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
-#else
-#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
-#define CONFIG_SYS_TEXT_BASE 0xf8f82000
-#endif /* CONFIG_NAND_SPL */
+#define CONFIG_SYS_L2_SIZE (512 << 10)
#endif
#ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD 1
-#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_SPL_MAX_SIZE (128 * 1024)
+#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS (129 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_MMC_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
#endif
#ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH 1
-#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_SPL_MAX_SIZE (128 * 1024)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_SPI_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE (128 << 10)
+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_TEXT_BASE 0xff800000
+#define CONFIG_SPL_MAX_SIZE 4096
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
+#endif /* not CONFIG_TPL_BUILD */
+
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_TPL_PAD_TO 0x20000
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#endif
#ifndef CONFIG_SYS_TEXT_BASE
#endif
#ifndef CONFIG_SYS_MONITOR_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
+#endif
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_SYS_MEMTEST_END 0x1fffffff
#define CONFIG_PANIC_HANG /* do not reset board on panic */
- /*
- * Config the L2 Cache as L2 SRAM
- */
+/*
+ * Config the L2 Cache as L2 SRAM
+*/
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
+#if defined(CONFIG_P2020RDB)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
+#else
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
+#endif
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
#else
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif /* CONFIG_TPL_BUILD */
+#endif
#endif
-#define CONFIG_SYS_L2_SIZE (512 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-#if defined(CONFIG_NAND_SPL)
+#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR size on P1_P2 RDBs */
+#if defined(CONFIG_P1011RDB) || defined(CONFIG_P1020RDB)
+/*
+ * P1020 and it's derivatives support max 32bit DDR width
+ * So Reduce available DDR size
+*/
+#define CONFIG_SYS_SDRAM_SIZE 512
+#else
+#define CONFIG_SYS_SDRAM_SIZE 1024
+#endif
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
- defined(CONFIG_RAMBOOT_SPIFLASH)
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
-#ifndef CONFIG_NAND_SPL
-#define CONFIG_SYS_NAND_BASE 0xffa00000
+#define CONFIG_SYS_NAND_BASE 0xff800000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
+#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
#else
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#endif
-#else
-#define CONFIG_SYS_NAND_BASE 0xfff00000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-#endif
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
-/* NAND boot: 4K NAND loader config */
-#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
-#define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
-
/* NAND flash config */
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| OR_FCM_TRLX \
| OR_FCM_EHTR)
-#ifdef CONFIG_RAMBOOT_NAND
+#ifdef CONFIG_NAND
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#ifdef CONFIG_NAND_SPL
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
/*
* Environment
*/
-#if defined(CONFIG_SYS_RAMBOOT)
-#if defined(CONFIG_RAMBOOT_NAND)
- #define CONFIG_ENV_IS_IN_NAND 1
- #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
- #define CONFIG_ENV_OFFSET ((768*1024)+CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_RAMBOOT_SDCARD)
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 10000000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#elif defined(CONFIG_SDCARD)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_FSL_FIXED_MMC_LOCATION
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#elif defined(CONFIG_RAMBOOT_SPIFLASH)
- #define CONFIG_ENV_IS_IN_SPI_FLASH
- #define CONFIG_ENV_SPI_BUS 0
- #define CONFIG_ENV_SPI_CS 0
- #define CONFIG_ENV_SPI_MAX_HZ 10000000
- #define CONFIG_ENV_SPI_MODE 0
- #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
- #define CONFIG_ENV_SECT_SIZE 0x10000
- #define CONFIG_ENV_SIZE 0x2000
-#endif
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_OFFSET (512 * 0x800)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
#else
- #define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
- #define CONFIG_ENV_SIZE 0x2000
- #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#endif
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET (1024 * 1024)
+#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
+#elif defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE 0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
+
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
"ramdiskfile=p2041rdb/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=p2041rdb/p2041rdb.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
#define CONFIG_HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
"ramdiskfile=t1040qds/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=t1040qds/t1040qds.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
#define CONFIG_LINUX \
"setenv bootargs root=/dev/ram rw " \
"ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
"fdtaddr=c00000\0" \
"fdtfile=" __stringify(FDTFILE) "\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
#define CONFIG_LINUX \
"setenv bootargs root=/dev/ram rw " \
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
"ramdiskfile=t2080qds/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=t2080qds/t2080qds.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
/*
* For emulation this causes u-boot to jump to the start of the
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
#define CONFIG_CMD_MII
#define CONFIG_CMD_I2C
#define CONFIG_CMD_PING
"ramdiskfile=t2080rdb/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=t2080rdb/t2080rdb.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
/*
* For emulation this causes u-boot to jump to the start of the
"ramdiskfile=t4240emu/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=t4240emu/t4240emu.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
/*
* For emulation this causes u-boot to jump to the start of the proof point
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
"ramdiskfile=t4240qds/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=t4240qds/t4240qds.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
#define CONFIG_HVBOOT \
"setenv bootargs config-addr=0x60000000; " \
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * T4240 RDB board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_T4240RDB
+#define CONFIG_PHYS_64BIT
+
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_PCIE4
+
+#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg
+#endif
+
+#define CONFIG_DDR_ECC
+
+#define CONFIG_CMD_REGINFO
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500 /* BOOKE e500 family */
+#define CONFIG_E500MC /* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
+#define CONFIG_MP /* support multiple processors */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC /* Enable IFC Support */
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCIE1 /* PCIE controler 1 */
+#define CONFIG_PCIE2 /* PCIE controler 2 */
+#define CONFIG_PCIE3 /* PCIE controler 3 */
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BTB /* toggle branch predition */
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
+
+#define CONFIG_SYS_DCSRBAR 0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR3
+
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE 0xe0000000
+#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_PCI */
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_ETHPRIME "FM1@DTSEC1"
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_HVBOOT \
+ "setenv bootargs config-addr=0x60000000; " \
+ "bootm 0x01000000 - 0x00f00000"
+
+#ifdef CONFIG_SYS_NO_FLASH
+#ifndef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 10000000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (512 * 1658)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE 0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_SYS_CLK_FREQ 66666666
+#define CONFIG_DDR_CLK_FREQ 133333333
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS1 0x52
+#define SPD_EEPROM_ADDRESS2 0x54
+#define SPD_EEPROM_ADDRESS3 0x56
+#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
+#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
+
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
+ FTIM0_NOR_TEADC(0x5) | \
+ FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
+ FTIM1_NOR_TRAD_NOR(0x1A) |\
+ FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
+ FTIM2_NOR_TCH(0x4) | \
+ FTIM2_NOR_TWPH(0x0E) | \
+ FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3 0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS 256
+#define CONFIG_SYS_NAND_MAX_OOBFREE 2
+#define CONFIG_SYS_NAND_BASE 0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+ | CSPR_MSEL_NAND /* MSEL = NAND */ \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
+ | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
+ | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
+ | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+ FTIM0_NAND_TWP(0x18) | \
+ FTIM0_NAND_TWCHT(0x07) | \
+ FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+ FTIM1_NAND_TWBE(0x39) | \
+ FTIM1_NAND_TRR(0x0e) | \
+ FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+ FTIM2_NAND_TREH(0x0a) | \
+ FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW 11
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+
+/* I2C */
+#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
+#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
+#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
+#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
+
+#define I2C_MUX_CH_DEFAULT 0x8
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+#define I2C_MUX_CH_VSC3316_FS 0xc
+#define I2C_MUX_CH_VSC3316_BS 0xd
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE 0
+
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS 50
+#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS 50
+#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_DPAA_RMAN
+#define CONFIG_SYS_INTERLAKEN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_CORTINA
+#define CONFIG_CORTINA_FW_ADDR 0xefe00000
+#define CONFIG_CORTINA_FW_LENGTH 0x40000
+#define CONFIG_PHY_TERANETICS
+#define SGMII_PHY_ADDR1 0x0
+#define SGMII_PHY_ADDR2 0x1
+#define SGMII_PHY_ADDR3 0x2
+#define SGMII_PHY_ADDR4 0x3
+#define SGMII_PHY_ADDR5 0x4
+#define SGMII_PHY_ADDR6 0x5
+#define SGMII_PHY_ADDR7 0x6
+#define SGMII_PHY_ADDR8 0x7
+#define FM1_10GEC1_PHY_ADDR 0x10
+#define FM1_10GEC2_PHY_ADDR 0x11
+#define FM2_10GEC1_PHY_ADDR 0x12
+#define FM2_10GEC2_PHY_ADDR 0x13
+#define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
+#define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
+#define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
+#define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
+#endif
+
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_ETHPRIME "FM1@DTSEC1"
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#define CONFIG_HAS_FSL_DR_USB
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+
+#define __USB_PHY_TYPE utmi
+
+/*
+ * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
+ * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
+ * interleaving. It can be cacheline, page, bank, superbank.
+ * See doc/README.fsl-ddr for details.
+ */
+#ifdef CONFIG_PPC_T4240
+#define CTRL_INTLV_PREFERED 3way_4KB
+#else
+#define CTRL_INTLV_PREFERED cacheline
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:" \
+ "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
+ "bank_intlv=auto;" \
+ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+ "netdev=eth0\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot && " \
+ "protect off $ubootaddr +$filesize && " \
+ "erase $ubootaddr +$filesize && " \
+ "cp.b $loadaddr $ubootaddr $filesize && " \
+ "protect on $ubootaddr +$filesize && " \
+ "cmp.b $loadaddr $ubootaddr $filesize\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=t4240rdb/t4240rdb.dtb\0" \
+ "bdev=sda3\0"
+
+#define CONFIG_HVBOOT \
+ "setenv bootargs config-addr=0x60000000; " \
+ "bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_LINUX \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "setenv ramdiskaddr 0x02000000;" \
+ "setenv fdtaddr 0x00c00000;" \
+ "setenv loadaddr 0x1000000;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_LINUX
+
+#include <asm/fsl_secure_boot.h>
+
+#ifdef CONFIG_SECURE_BOOT
+/* Secure Boot target was not getting build for T4240 because of
+ * increased binary size. So the size is being reduced by removing USB
+ * which is anyways not used in Secure Environment.
+ */
+#undef CONFIG_CMD_USB
+#endif
+
+#endif /* __CONFIG_H */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_I2C
#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_LOADS
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_HUSH_PARSER
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_USB
#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FPGA_LOADMK
#undef CONFIG_LCD
/*
#include "tegra30-common.h"
+/* VDD core PMIC */
+#define CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
+
/* Enable fdt support for Beaver. Flash the image in u-boot-dtb.bin */
#define CONFIG_DEFAULT_DEVICE_TREE tegra30-beaver
#define CONFIG_OF_CONTROL
#include "tegra30-common.h"
+/* VDD core PMIC */
+#define CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
+
/* Enable fdt support for Cardhu. Flash the image in u-boot-dtb.bin */
#define CONFIG_DEFAULT_DEVICE_TREE tegra30-cardhu
#define CONFIG_OF_CONTROL
#define CONFIG_CMD_ECHO
#undef CONFIG_CMD_FLASH
#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_IMI
#undef CONFIG_CMD_IMLS
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
#include "../board/freescale/common/ics307_clk.h"
#ifdef CONFIG_RAMBOOT_PBL
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
"ramdiskfile=p4080ds/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=p4080ds/p4080ds.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
#define CONFIG_HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
#define CONFIG_SPL_STACK 0x8001ff00
#define CONFIG_SPL_TEXT_BASE 0x80000000
#define CONFIG_SPL_MAX_FOOTPRINT 32768
+#define CONFIG_SPL_PAD_TO 32768
#endif
/* Load U-Boot Image From MMC */
--- /dev/null
+/*
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * U-Boot file:/include/configs/am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_DRACO_H
+#define __CONFIG_DRACO_H
+
+#define CONFIG_SIEMENS_DRACO
+#define MACH_TYPE_DRACO 4314
+#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_DRACO
+
+#include "siemens-am33x-common.h"
+
+#define CONFIG_SYS_MPUCLK 275
+#define DDR_PLL_FREQ 303
+#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
+
+#define BOARD_DFU_BUTTON_GPIO 27
+#define BOARD_DFU_BUTTON_LED 64 /* red LED */
+#define BOARD_STATUS_LED 103 /* green LED */
+#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */
+
+#undef CONFIG_DOS_PARTITION
+#undef CONFIG_CMD_FAT
+
+
+ /* Physical Memory Map */
+#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define EEPROM_ADDR_DDR3 0x90
+#define EEPROM_ADDR_CHIP 0x120
+
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300
+
+#undef CONFIG_SPL_NET_SUPPORT
+#undef CONFIG_SPL_NET_VCI_STRING
+#undef CONFIG_SPL_ETH_SUPPORT
+
+#undef CONFIG_MII
+#undef CONFIG_PHY_GIGE
+#define CONFIG_PHY_SMSC
+
+#define CONFIG_FACTORYSET
+
+/* Watchdog */
+#define CONFIG_OMAP_WATCHDOG
+
+#ifndef CONFIG_SPL_BUILD
+
+/* Default env settings */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "nand_img_size=0x400000\0" \
+ "optargs=\0" \
+ CONFIG_COMMON_ENV_SETTINGS
+
+#ifndef CONFIG_RESTORE_FLASH
+/* set to negative value for no autoboot */
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_BOOTCOMMAND \
+"if dfubutton; then " \
+ "run dfu_start; " \
+ "reset; " \
+"fi;" \
+"run nand_boot;" \
+"reset;"
+
+
+#else
+#define CONFIG_BOOTDELAY 0
+
+#define CONFIG_BOOTCOMMAND \
+ "setenv autoload no; " \
+ "dhcp; " \
+ "if tftp 80000000 debrick.scr; then " \
+ "source 80000000; " \
+ "fi"
+#endif
+#endif /* CONFIG_SPL_BUILD */
+#endif /* ! __CONFIG_DRACO_H */
#include "siemens-am33x-common.h"
#define CONFIG_SYS_MPUCLK 275
-#define DXR2_IOCTRL_VAL 0x18b
#define DDR_PLL_FREQ 303
#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
#define BOARD_DFU_BUTTON_GPIO 27
-#define BOARD_DFU_BUTTON_LED 64
+#define BOARD_DFU_BUTTON_LED 64 /* red LED */
+#define BOARD_STATUS_LED 103 /* green LED */
#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */
#undef CONFIG_DOS_PARTITION
--- /dev/null
+/*
+ * Copyright (C) 2014 Eukréa Electromatique
+ * Author: Eric Bénard <eric@eukrea.com>
+ *
+ * Configuration settings for the Embest RIoTboard
+ *
+ * based on mx6*sabre*.h which are :
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __RIOTBOARD_CONFIG_H
+#define __RIOTBOARD_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+#include "mx6_common.h"
+#include <linux/sizes.h>
+
+#define CONFIG_MXC_UART_BASE UART2_BASE
+#define CONFIG_CONSOLE_DEV "ttymxc0"
+#define CONFIG_MMCROOT "/dev/mmcblk1p2"
+
+#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
+
+#define CONFIG_MX6
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 4
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+
+#define CONFIG_CMD_SF
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS 0
+#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(2, 30) << 8))
+#define CONFIG_SF_DEFAULT_SPEED 20000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#endif
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_SETEXPR
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 1
+
+#define CONFIG_LOADADDR 0x12000000
+#define CONFIG_SYS_TEXT_BASE 0x17800000
+
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+#define EMMC_ENV \
+ "emmcdev=2\0" \
+ "update_emmc_firmware=" \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "if ${get_cmd} ${update_sd_firmware_filename}; then " \
+ "if mmc dev ${emmcdev}; then " \
+ "setexpr fw_sz ${filesize} / 0x200; " \
+ "setexpr fw_sz ${fw_sz} + 1; " \
+ "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+ "fi; " \
+ "fi\0"
+#else
+#define EMMC_ENV ""
+#endif
+
+#ifdef CONFIG_CMD_SF
+#define SF_ENV \
+ "update_spi_firmware=" \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "if ${get_cmd} ${update_spi_firmware_filename}; then " \
+ "if sf probe; then " \
+ "sf erase 0 0xc0000; " \
+ "sf write ${loadaddr} 0x400 ${filesize}; " \
+ "fi; " \
+ "fi\0"
+#else
+#define SF_ENV ""
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=zImage\0" \
+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "fdt_addr=0x18000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
+ "console=" CONFIG_CONSOLE_DEV "\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+ "mmcpart=1\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "update_sd_firmware=" \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "if mmc dev ${mmcdev}; then " \
+ "if ${get_cmd} ${update_sd_firmware_filename}; then " \
+ "setexpr fw_sz ${filesize} / 0x200; " \
+ "setexpr fw_sz ${fw_sz} + 1; " \
+ "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+ "fi; " \
+ "fi\0" \
+ EMMC_ENV \
+ SF_ENV \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END 0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_STACKSIZE (128 * 1024)
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+/* RiOTboard */
+#define CONFIG_DEFAULT_FDT_FILE "imx6s-riotboard.dtb"
+#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CONFIG_SYS_MMC_ENV_DEV 2 /* SDHC4 */
+#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+/* MarSBoard */
+#define CONFIG_DEFAULT_FDT_FILE "imx6q-marsboard.dtb"
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_ENV_OFFSET (768 * 1024)
+#define CONFIG_ENV_SECT_SIZE (8 * 1024)
+#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#endif
+
+#define CONFIG_OF_LIBFDT
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+/* Framebuffer */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+
+#endif /* __RIOTBOARD_CONFIG_H */
#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_GPIO
+
#endif /* __CONFIG_H */
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_ECHO /* echo arguments */
#define CONFIG_CMD_FPGA /* FPGA configuration Support */
+#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ITEST /* Integer (and string) test */
#define CONFIG_CMD_LOADB /* loadb */
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_ECHO /* echo arguments */
#define CONFIG_CMD_FPGA /* FPGA configuration Support */
+#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ITEST /* Integer (and string) test */
#define CONFIG_CMD_LOADB /* loadb */
#define CONFIG_SERIAL_TAG
#define CONFIG_REVISION_TAG
+#define CONFIG_SYS_GENERIC_BOARD
+
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+#define CONFIG_POWER_LTC3676
+#define CONFIG_POWER_LTC3676_I2C_ADDR 0x3c
/* Various command support */
#include <config_cmd_default.h>
#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
#define CONFIG_USB_HUB_MIN_POWER_ON_DELAY 1200
+/* Framebuffer and LCD */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_CMD_HDMIDETECT
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+
/* serial console (ttymxc1,115200) */
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
+#define CONFIG_SYS_GENERIC_BOARD
+
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M)
* Commands additional to the ones defined in amcc-common.h
*/
#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_FPGAD
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FPGA_LOADMK
#undef CONFIG_CMD_EEPROM
/*
#define CONFIG_CMD_EEPROM
/* U-Boot general configuration */
+#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SYS_PROMPT "K2HK EVM # "
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_PBSIZE 2048
#define CONFIG_ADDR_MAP
#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00800000
-#define CONFIG_SYS_ALT_MEMTEST
-#define CONFIG_PANIC_HANG /* do not reset board on panic */
+#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */
/*
* Config the L3 Cache as L3 SRAM
#define CONFIG_KM_PNVRAM 0x80000
/* physical RAM MTD size [hex] */
#define CONFIG_KM_PHRAM 0x100000
-/* resereved pram area at the end of memroy [hex] */
-#define CONFIG_KM_RESERVED_PRAM 0x0
-/* enable protected RAM */
-#define CONFIG_PRAM 0
+/* reserved pram area at the end of memory [hex]
+ * u-boot reserves some memory for the MP boot page */
+#define CONFIG_KM_RESERVED_PRAM 0x1000
+/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
+ * is not valid yet, which is the case for when u-boot copies itself to RAM */
+#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10)
#define CONFIG_KM_CRAMFS_ADDR 0x2000000
#define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */
*/
#define CONFIG_CMD_PCI
#define CONFIG_CMD_NET
+#define CONFIG_CMD_ERRATA
/* we don't need flash support */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_CMD_NFS
#define CONFIG_CMD_BOOTZ
-#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
-#define CONFIG_CMD_FLASH
-#define CONFIG_SYS_TEXT_BASE 0x00000000
-#else
-/* SPI flash boot is default. */
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_SYS_TEXT_BASE 0xE6304000
-#endif
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */
-#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_FLASH_BASE 0x00000000
-#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
-#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) }
-#define CONFIG_SYS_FLASH_ERASE_TOUT 3000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 3000
-#define CONFIG_SYS_FLASH_LOCK_TOUT 3000
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000
-/* ENV setting */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
- CONFIG_SYS_MONITOR_LEN)
-
-#else /* CONFIG_SYS_USE_BOOT_NORFLASH */
-
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SPI
#define CONFIG_SH_QSPI
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_ADDR 0xC0000
-#endif /* CONFIG_SYS_USE_BOOT_NORFLASH */
-
/* Common ENV setting */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_SECT_SIZE (256 * 1024)
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 10000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define RMOBILE_XTAL_CLK 20000000u
+#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
+#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
#define CONFIG_SH_SCIF_CLK_FREQ 14745600
#define CONFIG_SYS_TMU_CLK_DIV 4
#undef CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_RMOBILE
#define CONFIG_RMOBILE_BOARD_STRING "Lager"
#define CONFIG_SH_GPIO_PFC
-#define MACH_TYPE_LAGER 4538
-#define CONFIG_MACH_TYPE MACH_TYPE_LAGER
#include <asm/arch/rmobile.h>
#define CONFIG_CMD_NFS
#define CONFIG_CMD_BOOTZ
-#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
-#define CONFIG_CMD_FLASH
-#define CONFIG_SYS_TEXT_BASE 0x00000000
-#else
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_SYS_TEXT_BASE 0xE8080000
-#endif
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
-/* USE NOR FLASH */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_FLASH_BASE 0x00000000
-#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
-#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) }
-#define CONFIG_SYS_FLASH_ERASE_TOUT 3000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 3000
-#define CONFIG_SYS_FLASH_LOCK_TOUT 3000
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000
-
-/* ENV setting */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
- CONFIG_SYS_MONITOR_LEN)
-
-#else /* CONFIG_SYS_USE_BOOT_NORFLASH */
-
/* USE SPI */
#define CONFIG_SPI
#define CONFIG_SPI_FLASH_BAR
/* ENV setting */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_ADDR 0xC0000
-#endif
/* Common ENV setting */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
/* Board Clock */
-#define CONFIG_BASE_CLK_FREQ 20000000u
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_BASE_CLK_FREQ / 2) /* EXT / 2 */
-#define CONFIG_PLL1_CLK_FREQ (CONFIG_BASE_CLK_FREQ * 156 / 2)
+#define RMOBILE_XTAL_CLK 20000000u
+#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
+#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
+#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2)
#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12)
#ifndef __CONFIGS_M28EVK_H__
#define __CONFIGS_M28EVK_H__
-
/* System configurations */
#define CONFIG_MX28 /* i.MX28 SoC */
#define MACH_TYPE_M28EVK 3613
* FPGA
*/
#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_FPGA
#define CONFIG_FPGA_XILINX
#define CONFIG_FPGA_SPARTAN3
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
+#define CONFIG_SYS_GENERIC_BOARD
+
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
+#define CONFIG_SYS_GENERIC_BOARD
+
#define CONFIG_OF_LIBFDT
/* Size of malloc() pool */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
+#define CONFIG_SYS_GENERIC_BOARD
+
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
+#define CONFIG_SYS_GENERIC_BOARD
+
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
+#define CONFIG_SYS_GENERIC_BOARD
+
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
#define CONFIG_CMD_PCI
#ifdef CONFIG_CMD_PCI
#define __CONFIG_H
#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
#include <linux/sizes.h>
#include "mx6_common.h"
#define CONFIG_CMD_CACHE
#endif
+#define CONFIG_CMD_SF
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS 0
+#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(4, 11) << 8))
+#define CONFIG_SF_DEFAULT_SPEED 20000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#endif
+
#endif /* __CONFIG_H */
/*
* CPU specifics
*/
+#define CONFIG_SYS_GENERIC_BOARD
/* MXS uses FDT */
#define CONFIG_OF_LIBFDT
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
+#define CONFIG_SYS_GENERIC_BOARD
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_CMD_HDMIDETECT
#define CONFIG_CONSOLE_MUX
#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_TWL4030_USB 1
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETHER_RNDIS
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_VBUS_DRAW 0
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_G_DNL_VENDOR_NUM 0x0451
+#define CONFIG_G_DNL_PRODUCT_NUM 0xd022
+#define CONFIG_G_DNL_MANUFACTURER "TI"
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_ANDROID_BOOT_IMAGE
+#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
+#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000
/* USB EHCI */
#define CONFIG_CMD_USB
"if test $beaglerev = C4; then " \
"setenv fdtfile omap3-beagle.dtb; fi; " \
"if test $beaglerev = xMAB; then " \
- "setenv fdtfile omap3-beagle-xm.dtb; fi; " \
+ "setenv fdtfile omap3-beagle-xm-ab.dtb; fi; " \
"if test $beaglerev = xMC; then " \
"setenv fdtfile omap3-beagle-xm.dtb; fi; " \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine device tree to use; fi; \0" \
+ "validatefdt=" \
+ "if test $beaglerev = xMAB; then " \
+ "if test ! -e mmc ${bootpart} ${bootdir}/${fdtfile}; then " \
+ "setenv fdtfile omap3-beagle-xm.dtb; " \
+ "fi; " \
+ "fi; \0" \
"bootenv=uEnv.txt\0" \
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
"importbootenv=echo Importing environment from mmc ...; " \
"rootfstype=${ramrootfstype}\0" \
"loadramdisk=load mmc ${bootpart} ${rdaddr} ${bootdir}/${ramdisk}\0" \
"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
- "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+ "loadfdt=run validatefdt; load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
#ifdef CONFIG_36BIT
#define CONFIG_PHYS_64BIT
#endif
#endif
#endif
+#if defined(CONFIG_P1020RDB_PD)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
+
#define CONFIG_MMC
#ifdef CONFIG_MMC
--- /dev/null
+/*
+ * Copyright (C) 2013 Gumstix, Inc. - http://www.gumstix.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_PEPPER_H
+#define __CONFIG_PEPPER_H
+
+#define CONFIG_MMC
+#include <configs/ti_am335x_common.h>
+
+#undef CONFIG_BOARD_LATE_INIT
+#undef CONFIG_SPL_OS_BOOT
+
+/* Clock defines */
+#define V_OSCK 24000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK)
+
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT "pepper# "
+
+/* Mach type */
+#define MACH_TYPE_PEPPER 4207 /* Until the next sync */
+#define CONFIG_MACH_TYPE MACH_TYPE_PEPPER
+
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_IS_NOWHERE
+/* Display cpuinfo */
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ DEFAULT_LINUX_BOOT_ENV \
+ "bootdir=/boot\0" \
+ "bootfile=zImage\0" \
+ "fdtfile=am335x-pepper.dtb\0" \
+ "console=ttyO0,115200n8\0" \
+ "optargs=\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "bootenv=uEnv.txt\0" \
+ "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+ "importbootenv=echo Importing environment from mmc ...; " \
+ "env import -t ${loadaddr} ${filesize}\0" \
+ "mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \
+ "load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+ "loaduimage=fatload mmc ${mmcdev}:1 ${loadaddr} uImage\0" \
+ "uimageboot=echo Booting from mmc${mmcdev} ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
+ "ubiboot=echo Booting from nand (ubifs) ...; " \
+ "run ubiargs; run ubiload; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "echo SD/MMC found on device ${mmcdev};" \
+ "if run loadbootenv; then " \
+ "echo Loaded environment from ${bootenv};" \
+ "run importbootenv;" \
+ "fi;" \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "if run mmcload; then " \
+ "run mmcboot;" \
+ "fi;" \
+ "if run loaduimage; then " \
+ "run uimageboot;" \
+ "fi;" \
+ "fi;" \
+
+/* Serial console configuration */
+#define CONFIG_CONS_INDEX 1 /* UART0 */
+#define CONFIG_SERIAL1 1
+#define CONFIG_SYS_NS16550_COM1 0x44e09000
+
+/* Ethernet support */
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ADDR 0
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#define CONFIG_PHY_RESET_DELAY 1000
+
+/* SPL */
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+#endif /* __CONFIG_PEPPER_H */
#include "siemens-am33x-common.h"
#define CONFIG_SYS_MPUCLK 720
-#define DXR2_IOCTRL_VAL 0x18b
+#define DDR_IOCTRL_VAL 0x18b
#define DDR_PLL_FREQ 266
#define BOARD_DFU_BUTTON_GPIO 59
#undef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xf01000 /* 15 MB */
+#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
/*
* I2C Settings
*/
-#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get(j4, 3)
-#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get(j4, 0)
+#define CONFIG_SOFT_I2C_GPIO_SCL S5PC110_GPIO_J43
+#define CONFIG_SOFT_I2C_GPIO_SDA S5PC110_GPIO_J40
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
"onenand write 0x41008000 0xc00000 0x500000\0" \
"bootk=" \
"run loaduimage; bootm 0x40007FC0\0" \
- "updatemmc=" \
- "mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \
- "mmc boot 0 1 1 0\0" \
"updatebackup=" \
- "mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \
- "mmc boot 0 1 1 0\0" \
+ "mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \
+ "mmc dev 0 0\0" \
"updatebootb=" \
"mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
"lpj=lpj=3981312\0" \
/*
* I2C Settings
*/
-#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(1, b, 7)
-#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(1, b, 6)
+#define CONFIG_SOFT_I2C_GPIO_SCL EXYNOS4_GPIO_B7
+#define CONFIG_SOFT_I2C_GPIO_SDA EXYNOS4_GPIO_B6
#define CONFIG_CMD_I2C
*/
#define CONFIG_SOFT_SPI
#define CONFIG_SOFT_SPI_MODE SPI_MODE_3
-#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_get(2, y3, 1)
-#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_get(2, y3, 3)
-#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_get(2, y3, 0)
-#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_get(2, y4, 3)
+#define CONFIG_SOFT_SPI_GPIO_SCLK EXYNOS4_GPIO_Y31
+#define CONFIG_SOFT_SPI_GPIO_MOSI EXYNOS4_GPIO_Y33
+#define CONFIG_SOFT_SPI_GPIO_MISO EXYNOS4_GPIO_Y30
+#define CONFIG_SOFT_SPI_GPIO_CS EXYNOS4_GPIO_Y43
#define SPI_DELAY udelay(1)
#undef SPI_INIT
#define KEY_PWR_INTERRUPT_REG MAX8998_REG_IRQ1
#define KEY_PWR_INTERRUPT_MASK (1 << 7)
-#define KEY_VOL_UP_GPIO exynos4_gpio_get(2, x2, 0)
-#define KEY_VOL_DOWN_GPIO exynos4_gpio_get(2, x2, 1)
+#define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20
+#define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21
#endif /* __ASSEMBLY__ */
/* LCD console */
#define CONFIG_COMMON_ENV_SETTINGS \
"verify=no \0" \
- "project_dir=systemone\0" \
+ "project_dir=targetdir\0" \
"upgrade_available=0\0" \
"altbootcmd=run bootcmd\0" \
"bootlimit=3\0" \
"dfu_args=run bootargs_defaults;" \
"setenv bootargs ${bootargs} ;" \
"mtdparts default; " \
- "dfu 0 nand 0; \0" \
+ "led dfu 1;" \
+ "led stat 0;" \
+ "dfu 0 nand 0;" \
+ "led dfu 0;" \
+ "led stat 1;\0" \
"dfu_alt_info=" DFU_ALT_INFO_NAND "\0" \
"net_args=run bootargs_defaults;" \
"mtdparts default;" \
#undef CONFIG_DEFAULT_DEVICE_TREE
#define CONFIG_DEFAULT_DEVICE_TREE exynos5250-smdk5250
+/* Enable FIT support and comparison */
+#define CONFIG_FIT
+#define CONFIG_FIT_BEST_MATCH
+
#endif /* __CONFIG_SMDK_H */
#define CONFIG_MAX_I2C_NUM 11
+/* Enable FIT support and comparison */
+#define CONFIG_FIT
+#define CONFIG_FIT_BEST_MATCH
+
#endif /* __CONFIG_5420_H */
/* High Level Configuration Options */
#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
#define CONFIG_S5P 1 /* S5P Family */
+#define CONFIG_EXYNOS4 /* EXYNOS4 Family */
#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
#define CONFIG_SMDKV310 1 /* working with SMDKV310*/
#undef CONFIG_DEFAULT_DEVICE_TREE
#define CONFIG_DEFAULT_DEVICE_TREE exynos5250-snow
+/* Enable FIT support and comparison */
+#define CONFIG_FIT
+#define CONFIG_FIT_BEST_MATCH
+
#endif /* __CONFIG_SNOW_H */
#ifndef __T4QDS_H
#define __T4QDS_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_CMD_REGINFO
/* High Level Configuration Options */
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+/*
+ * Common HW configuration.
+ * If this varies between SoCs later, move to tegraNN-common.h
+ * Note: This is number of devices, not max device ID.
+ */
+#define CONFIG_SYS_MMC_MAX_DEVICE 4
+
/*
* select serial console configuration
*/
#define CONFIG_BOOTARGS "Please use defined boot"
#define CONFIG_BOOTCOMMAND "run mmcboot"
-#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
- GENERATED_GBL_DATA_SIZE)
"bootm 0x40007FC0 - ${fdtaddr};" \
"fi;" \
"bootm 0x40007FC0;\0" \
- "updatemmc=" \
- "mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \
- "mmc boot 0 1 1 0\0" \
"updatebackup=" \
- "mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \
- "mmc boot 0 1 1 0\0" \
+ "mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \
+ "mmc dev 0 0\0" \
"updatebootb=" \
"mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
"lpj=lpj=3981312\0" \
#define CONFIG_SYS_I2C_INIT_BOARD
/* I2C FG */
-#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(2, y4, 1)
-#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(2, y4, 0)
+#define CONFIG_SOFT_I2C_GPIO_SCL EXYNOS4_GPIO_Y41
+#define CONFIG_SOFT_I2C_GPIO_SDA EXYNOS4_GPIO_Y40
/* POWER */
#define CONFIG_POWER
#define KEY_PWR_INTERRUPT_REG MAX8997_REG_INT1
#define KEY_PWR_INTERRUPT_MASK (1 << 0)
-#define KEY_VOL_UP_GPIO exynos4_gpio_get(2, x2, 0)
-#define KEY_VOL_DOWN_GPIO exynos4_gpio_get(2, x2, 1)
+#define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20
+#define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21
#endif /* __ASSEMBLY__ */
/* LCD console */
#define CONFIG_BOOTARGS "Please use defined boot"
#define CONFIG_BOOTCOMMAND "run mmcboot"
-#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
- GENERATED_GBL_DATA_SIZE)
"bootm 0x40007FC0 - ${fdtaddr};" \
"fi;" \
"bootm 0x40007FC0;\0" \
- "updatemmc=" \
- "mmc boot 0 1 1 1; mmc write 0x42008000 0 0x200;" \
- "mmc boot 0 1 1 0\0" \
"updatebackup=" \
- "mmc boot 0 1 1 2; mmc write 0x42100000 0 0x200;" \
- " mmc boot 0 1 1 0\0" \
+ "mmc dev 0 2; mmc write 0x51000000 0 0x800;" \
+ " mmc dev 0 0\0" \
"updatebootb=" \
- "mmc read 0x51000000 0x80 0x200; run updatebackup\0" \
- "updateuboot=" \
- "mmc write 0x50000000 0x80 0x400\0" \
+ "mmc read 0x51000000 0x80 0x800; run updatebackup\0" \
"mmcboot=" \
"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
#define KEY_PWR_INTERRUPT_REG MAX77686_REG_PMIC_INT1
#define KEY_PWR_INTERRUPT_MASK (1 << 1)
-#define KEY_VOL_UP_GPIO exynos4x12_gpio_get(2, x2, 2)
-#define KEY_VOL_DOWN_GPIO exynos4x12_gpio_get(2, x3, 3)
+#define KEY_VOL_UP_GPIO EXYNOS4X12_GPIO_X22
+#define KEY_VOL_DOWN_GPIO EXYNOS4X12_GPIO_X33
#endif /* __ASSEMBLY__ */
/* LCD console */
#elif defined(CONFIG_EMMC_BOOT)
#undef CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
+#define CONFIG_SYS_GENERIC_BOARD
+
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M)
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
+#define CONFIG_SYS_GENERIC_BOARD
+
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
#define CONFIG_LOADADDR 0x12000000
#define CONFIG_SYS_TEXT_BASE 0x17800000
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED 100000
+
/* MMC Configuration */
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_CMD_HDMIDETECT
#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
#define CONFIG_DEFAULT_FDT_FILE "imx6dl-wandboard.dtb"
"fi; " \
"fi\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
- "root=${mmcroot}\0" \
+ "root=${mmcroot}; run videoargs\0" \
+ "videoargs=" \
+ "setenv nextcon 0; " \
+ "if hdmidet; then " \
+ "setenv bootargs ${bootargs} " \
+ "video=mxcfb${nextcon}:dev=hdmi,1280x720M@60," \
+ "if=RGB24; " \
+ "setenv fbmen fbmem=28M; " \
+ "setexpr nextcon ${nextcon} + 1; " \
+ "else " \
+ "echo - no HDMI monitor;" \
+ "fi; " \
+ "i2c dev 1; " \
+ "if i2c probe 0x10; then " \
+ "setenv bootargs ${bootargs} " \
+ "video=mxcfb${nextcon}:dev=lcd,800x480@60," \
+ "if=RGB666; " \
+ "if test 0 -eq ${nextcon}; then " \
+ "setenv fbmem fbmem=10M; " \
+ "else " \
+ "setenv fbmem ${fbmem},10M; " \
+ "fi; " \
+ "setexpr nextcon ${nextcon} + 1; " \
+ "else " \
+ "echo '- no FWBADAPT-7WVGA-LCD-F07A-0102 display';" \
+ "fi; " \
+ "setenv bootargs ${bootargs} ${fbmem}\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_FPGA_XILINX
#define CONFIG_FPGA_ZYNQPL
#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FPGA_LOADMK
+#define CONFIG_CMD_FPGA_LOADP
+#define CONFIG_CMD_FPGA_LOADBP
+#define CONFIG_CMD_FPGA_LOADFS
/* Open Firmware flat tree */
#define CONFIG_OF_LIBFDT
unsigned int lba_size;
unsigned int lba_blk_size;
+ /* eMMC HW partition access */
+ int hw_partition;
+
/* FAT/EXT */
unsigned int dev;
unsigned int part;
u64 offset, void *buf, long *len);
int (*flush_medium)(struct dfu_entity *dfu);
+ unsigned int (*poll_timeout)(struct dfu_entity *dfu);
struct list_head list;
void *devdesc; /* real device descriptor */
} fpga_desc; /* end, typedef fpga_desc */
+typedef struct { /* typedef fpga_desc */
+ unsigned int blocksize;
+ char *interface;
+ char *dev_part;
+ char *filename;
+ int fstype;
+} fpga_fs_info;
+
+typedef enum {
+ BIT_FULL = 0,
+ BIT_PARTIAL,
+} bitstream_type;
/* root function definitions */
extern void fpga_init(void);
extern int fpga_add(fpga_type devtype, void *desc);
extern int fpga_count(void);
-extern int fpga_load(int devnum, const void *buf, size_t bsize);
-extern int fpga_loadbitstream(int devnum, char *fpgadata, size_t size);
+extern int fpga_load(int devnum, const void *buf, size_t bsize,
+ bitstream_type bstype);
+extern int fpga_fsload(int devnum, const void *buf, size_t size,
+ fpga_fs_info *fpga_fsinfo);
+extern int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
+ bitstream_type bstype);
extern int fpga_dump(int devnum, const void *buf, size_t bsize);
extern int fpga_info(int devnum);
extern const fpga_desc *const fpga_validate(int devnum, const void *buf,
#define IMAGE_FORMAT_INVALID 0x00
#define IMAGE_FORMAT_LEGACY 0x01 /* legacy image_header based format */
#define IMAGE_FORMAT_FIT 0x02 /* new, libfdt based format */
+#define IMAGE_FORMAT_ANDROID 0x03 /* Android boot image */
int genimg_get_format(const void *img_addr);
int genimg_has_config(bootm_headers_t *images);
#endif /* CONFIG_FIT_VERBOSE */
#endif /* CONFIG_FIT */
+#if defined(CONFIG_ANDROID_BOOT_IMAGE)
+struct andr_img_hdr;
+int android_image_check_header(const struct andr_img_hdr *hdr);
+int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify,
+ ulong *os_data, ulong *os_len);
+int android_image_get_ramdisk(const struct andr_img_hdr *hdr,
+ ulong *rd_data, ulong *rd_len);
+ulong android_image_get_end(const struct andr_img_hdr *hdr);
+ulong android_image_get_kload(const struct andr_img_hdr *hdr);
+
+#endif /* CONFIG_ANDROID_BOOT_IMAGE */
+
#endif /* __IMAGE_H__ */
#define COMM_ERR -18 /* Communications Error */
#define TIMEOUT -19
#define IN_PROGRESS -20 /* operation is in progress */
+#define SWITCH_ERR -21 /* Card reports failure to switch mode */
#define MMC_CMD_GO_IDLE_STATE 0
#define MMC_CMD_SEND_OP_COND 1
#define MMC_CMD_SET_BLOCKLEN 16
#define MMC_CMD_READ_SINGLE_BLOCK 17
#define MMC_CMD_READ_MULTIPLE_BLOCK 18
+#define MMC_CMD_SET_BLOCK_COUNT 23
#define MMC_CMD_WRITE_SINGLE_BLOCK 24
#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
#define MMC_CMD_ERASE_GROUP_START 35
#define SECURE_ERASE 0x80000000
#define MMC_STATUS_MASK (~0x0206BF7F)
+#define MMC_STATUS_SWITCH_ERROR (1 << 7)
#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
#define MMC_STATUS_CURR_STATE (0xf << 9)
#define MMC_STATUS_ERROR (1 << 19)
* boot partitions (2), general purpose partitions (4) in MMC v4.4.
*/
#define MMC_NUM_BOOT_PARTITION 2
+#define MMC_PART_RPMB 3 /* RPMB partition number */
struct mmc_cid {
unsigned long psn;
int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
/* Function to modify the RST_n_FUNCTION field of EXT_CSD */
int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
-
+/* Functions to read / write the RPMB partition */
+int mmc_rpmb_set_key(struct mmc *mmc, void *key);
+int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
+int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
+ unsigned short cnt, unsigned char *key);
+int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
+ unsigned short cnt, unsigned char *key);
/**
* Start device initialization and return immediately; it does not block on
* polling OCR (operation condition register) status. Then you should call
#define LDO1_CTRL 0x50
#define LDO1_VOLTAGE 0x51
+/* LDO2 control/voltage */
+#define LDO2_CTRL 0x52
+#define LDO2_VOLTAGE 0x53
+
/* LDO9 control/voltage */
#define LDO9_CTRL 0x60
#define LDO9_VOLTAGE 0x61
block_dev_desc_t* scsi_get_dev(int dev);
block_dev_desc_t* usb_stor_get_dev(int dev);
block_dev_desc_t* mmc_get_dev(int dev);
+int mmc_select_hwpart(int dev_num, int hwpart);
block_dev_desc_t* systemace_get_dev(int dev);
block_dev_desc_t* mg_disk_get_dev(int dev);
block_dev_desc_t *host_get_dev(int dev);
static inline block_dev_desc_t* scsi_get_dev(int dev) { return NULL; }
static inline block_dev_desc_t* usb_stor_get_dev(int dev) { return NULL; }
static inline block_dev_desc_t* mmc_get_dev(int dev) { return NULL; }
+static inline int mmc_select_hwpart(int dev_num, int hwpart) { return -1; }
static inline block_dev_desc_t* systemace_get_dev(int dev) { return NULL; }
static inline block_dev_desc_t* mg_disk_get_dev(int dev) { return NULL; }
static inline block_dev_desc_t *host_get_dev(int dev) { return NULL; }
--- /dev/null
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LTC3676_PMIC_H_
+#define __LTC3676_PMIC_H_
+
+/* LTC3676 registers */
+enum {
+ LTC3676_BUCK1 = 0x01,
+ LTC3676_BUCK2 = 0x02,
+ LTC3676_BUCK3 = 0x03,
+ LTC3676_BUCK4 = 0x04,
+ LTC3676_LDOA = 0x05,
+ LTC3676_LDOB = 0x06,
+ LTC3676_SQD1 = 0x07,
+ LTC3676_SQD2 = 0x08,
+ LTC3676_CNTRL = 0x09,
+ LTC3676_DVB1A = 0x0A,
+ LTC3676_DVB1B = 0x0B,
+ LTC3676_DVB2A = 0x0C,
+ LTC3676_DVB2B = 0x0D,
+ LTC3676_DVB3A = 0x0E,
+ LTC3676_DVB3B = 0x0F,
+ LTC3676_DVB4A = 0x10,
+ LTC3676_DVB4B = 0x11,
+ LTC3676_MSKIRQ = 0x12,
+ LTC3676_MSKPG = 0x13,
+ LTC3676_USER = 0x14,
+ LTC3676_HRST = 0x1E,
+ LTC3676_CLIRQ = 0x1F,
+ LTC3676_IRQSTAT = 0x15,
+ LTC3676_PGSTATL = 0x16,
+ LTC3676_PGSTATR = 0x17,
+ LTC3676_NUM_OF_REGS = 0x20,
+};
+
+/*
+ * SW Configuration
+ */
+
+#define LTC3676_DVB_MASK 0x1f
+#define LTC3676_PGOOD_MASK (1<<5)
+#define LTC3676_REF_SELA (0<<5)
+#define LTC3676_REF_SELB (1<<5)
+
+int power_ltc3676_init(unsigned char bus);
+#endif
#define SWBST_MODE_AUTO (2 << 2)
#define SWBST_MODE_APS (2 << 3)
+int power_pfuze100_init(unsigned char bus);
#endif
BOOT_MODE_THOR,
BOOT_MODE_UMS,
BOOT_MODE_DFU,
+ BOOT_MODE_GPT,
+ BOOT_MODE_ENV,
BOOT_MODE_EXIT,
};
#include <asm/processor.h>
+#define CONTROL_REGISTER_W1C_MASK 0x00020000 /* W1C: PHY_CLK_VALID */
+
/* Global offsets */
#define FSL_SKIP_PCI 0x100
#define __USB_MASS_STORAGE_H__
#define SECTOR_SIZE 0x200
-#include <mmc.h>
+#include <part.h>
#include <linux/usb/composite.h>
-#ifndef UMS_START_SECTOR
-#define UMS_START_SECTOR 0
-#endif
-
-#ifndef UMS_NUM_SECTORS
-#define UMS_NUM_SECTORS 0
-#endif
-
/* Wait at maximum 60 seconds for cable connection */
#define UMS_CABLE_READY_TIMEOUT 60
unsigned int start_sector;
unsigned int num_sectors;
const char *name;
- struct mmc *mmc;
+ block_dev_desc_t *block_dev;
};
extern struct ums *ums;
int fsg_init(struct ums *);
void fsg_cleanup(void);
-struct ums *ums_init(unsigned int);
int fsg_main_thread(void *);
int fsg_add(struct usb_configuration *c);
#endif /* __USB_MASS_STORAGE_H__ */
} xilinx_desc; /* end, typedef xilinx_desc */
struct xilinx_fpga_op {
- int (*load)(xilinx_desc *, const void *, size_t);
+ int (*load)(xilinx_desc *, const void *, size_t, bitstream_type);
+ int (*loadfs)(xilinx_desc *, const void *, size_t, fpga_fs_info *);
int (*dump)(xilinx_desc *, const void *, size_t);
int (*info)(xilinx_desc *);
};
/* Generic Xilinx Functions
*********************************************************************/
-int xilinx_load(xilinx_desc *desc, const void *image, size_t size);
+int xilinx_load(xilinx_desc *desc, const void *image, size_t size,
+ bitstream_type bstype);
int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize);
int xilinx_info(xilinx_desc *desc);
+int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
+ fpga_fs_info *fpga_fsinfo);
/* Board specific implementation specific function types
*********************************************************************/
obj-$(CONFIG_PHYSMEM) += physmem.o
obj-y += qsort.o
obj-$(CONFIG_SHA1) += sha1.o
+obj-$(CONFIG_SUPPORT_EMMC_RPMB) += sha256.o
obj-$(CONFIG_SHA256) += sha256.o
obj-y += strmhz.o
obj-$(CONFIG_TPM) += tpm.o
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# Copyright 2009-2011 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
-PAD_TO := 0xfff01000
-
-nandobj := $(objtree)/nand_spl/
-
-LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
-LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
- $(LDFLAGS) $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS = start.o resetvec.o
-COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
- nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
-
-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
- -ansi -D__ASSEMBLY__ -P - <$< >$@
-
-# create symbolic links for common files
-
-$(obj)/cache.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
-
-$(obj)/cpu_init_early.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
-
-$(obj)/spl_minimal.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
-
-$(obj)/fsl_law.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
-
-$(obj)/law.c:
- @rm -f $@
- ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
-
-$(obj)/nand_boot_fsl_elbc.c:
- @rm -f $@
- ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
-
-$(obj)/ns16550.c:
- @rm -f $@
- ln -sf $(srctree)/drivers/serial/ns16550.c $@
-
-$(obj)/resetvec.S:
- @rm -f $@
- ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
-
-$(obj)/start.S:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@
-
-$(obj)/tlb.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/tlb.c $@
-
-$(obj)/tlb_table.c:
- @rm -f $@
- ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
+++ /dev/null
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <mpc85xx.h>
-#include <asm/io.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_law.h>
-
-#define SYSCLK_MASK 0x00200000
-#define BOARDREV_MASK 0x10100000
-#define BOARDREV_B 0x10100000
-#define BOARDREV_C 0x00100000
-
-#define SYSCLK_66 66666666
-#define SYSCLK_50 50000000
-#define SYSCLK_100 100000000
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void board_init_f(ulong bootflag)
-{
- uint plat_ratio, bus_clk, sys_clk = 0;
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- uint val, temp, sysclk_mask;
-
- val = pgpio->gpdat;
- sysclk_mask = val & SYSCLK_MASK;
- temp = val & BOARDREV_MASK;
- if (temp == BOARDREV_C) {
- if(sysclk_mask == 0)
- sys_clk = SYSCLK_66;
- else
- sys_clk = SYSCLK_100;
- } else if (temp == BOARDREV_B) {
- if(sysclk_mask == 0)
- sys_clk = SYSCLK_66;
- else
- sys_clk = SYSCLK_50;
- }
-
- plat_ratio = gur->porpllsr & 0x0000003e;
- plat_ratio >>= 1;
- bus_clk = plat_ratio * sys_clk;
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
-
- /* copy code to DDR and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
- CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
# Suppress duplicate signoffs
elif signoff_match:
- if self.commit.CheckDuplicateSignoff(signoff_match.group(1)):
+ if (self.is_log or
+ self.commit.CheckDuplicateSignoff(signoff_match.group(1))):
out = [line]
# Well that means this is an ordinary line
projects / people / ms / u-boot.git / commitdiff
