source "lib/Kconfig"
source "test/Kconfig"
-
-source "scripts/Kconfig"
};
apb {
+ hlcdc: hlcdc@f0000000 {
+ atmel,vl-bpix = <4>;
+ atmel,guard-time = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb666>;
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ display-timings {
+ u-boot,dm-pre-reloc;
+ 480x272 {
+ clock-frequency = <9000000>;
+ hactive = <480>;
+ vactive = <272>;
+ hsync-len = <41>;
+ hfront-porch = <2>;
+ hback-porch = <2>;
+ vfront-porch = <2>;
+ vback-porch = <2>;
+ vsync-len = <11>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+ };
+
qspi0: spi@f0020000 {
status = "okay";
bias-disable;
};
+ pinctrl_lcd_base: pinctrl_lcd_base {
+ pinmux = <PIN_PC30__LCDVSYNC>,
+ <PIN_PC31__LCDHSYNC>,
+ <PIN_PD1__LCDDEN>,
+ <PIN_PD0__LCDPCK>;
+ bias-disable;
+ };
+
+ pinctrl_lcd_pwm: pinctrl_lcd_pwm {
+ pinmux = <PIN_PC28__LCDPWM>;
+ bias-disable;
+ };
+
+ pinctrl_lcd_rgb666: pinctrl_lcd_rgb666 {
+ pinmux = <PIN_PC10__LCDDAT2>,
+ <PIN_PC11__LCDDAT3>,
+ <PIN_PC12__LCDDAT4>,
+ <PIN_PC13__LCDDAT5>,
+ <PIN_PC14__LCDDAT6>,
+ <PIN_PC15__LCDDAT7>,
+ <PIN_PC16__LCDDAT10>,
+ <PIN_PC17__LCDDAT11>,
+ <PIN_PC18__LCDDAT12>,
+ <PIN_PC19__LCDDAT13>,
+ <PIN_PC20__LCDDAT14>,
+ <PIN_PC21__LCDDAT15>,
+ <PIN_PC22__LCDDAT18>,
+ <PIN_PC23__LCDDAT19>,
+ <PIN_PC24__LCDDAT20>,
+ <PIN_PC25__LCDDAT21>,
+ <PIN_PC26__LCDDAT22>,
+ <PIN_PC27__LCDDAT23>;
+ bias-disable;
+ };
+
pinctrl_macb0_phy_irq: macb0_phy_irq {
pinmux = <PIN_PC9__GPIO>;
bias-disable;
ahb {
apb {
+ hlcdc: hlcdc@f0000000 {
+ atmel,vl-bpix = <4>;
+ atmel,guard-time = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb888>;
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ display-timings {
+ u-boot,dm-pre-reloc;
+ 480x272 {
+ clock-frequency = <9000000>;
+ hactive = <480>;
+ vactive = <272>;
+ hsync-len = <41>;
+ hfront-porch = <2>;
+ hback-porch = <2>;
+ vfront-porch = <2>;
+ vback-porch = <2>;
+ vsync-len = <11>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+ };
+
spi0: spi@f8010000 {
u-boot,dm-pre-reloc;
cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
ahb {
apb {
+ hlcdc: hlcdc@f0000000 {
+ atmel,vl-bpix = <4>;
+ atmel,output-mode = <18>;
+ atmel,guard-time = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb666>;
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ display-timings {
+ u-boot,dm-pre-reloc;
+ 800x480 {
+ clock-frequency = <33260000>;
+ hactive = <800>;
+ vactive = <480>;
+ hsync-len = <5>;
+ hfront-porch = <128>;
+ hback-porch = <0>;
+ vfront-porch = <23>;
+ vback-porch = <22>;
+ vsync-len = <5>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+ };
+
adc0: adc@fc034000 {
pinctrl-names = "default";
pinctrl-0 = <
#size-cells = <1>;
u-boot,dm-pre-reloc;
+ hlcdc: hlcdc@f0000000 {
+ compatible = "atmel,at91sam9x5-hlcdc";
+ reg = <0xf0000000 0x2000>;
+ clocks = <&lcdc_clk>;
+ status = "disabled";
+ };
+
pmc: pmc@f0014000 {
compatible = "atmel,sama5d2-pmc", "syscon";
reg = <0xf0014000 0x160>;
/dts-v1/;
#include "sama5d36.dtsi"
#include "sama5d3xmb_cmp.dtsi"
+#include "sama5d3xdm.dtsi"
/ {
model = "Atmel SAMA5D36-EK";
ahb {
apb {
hlcdc: hlcdc@f0030000 {
- compatible = "atmel,sama5d3-hlcdc";
+ compatible = "atmel,at91sam9x5-hlcdc";
reg = <0xf0030000 0x2000>;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
clock-names = "periph_clk","sys_clk", "slow_clk";
status = "disabled";
-
- hlcdc-display-controller {
- compatible = "atmel,hlcdc-display-controller";
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
- };
- };
-
- hlcdc_pwm: hlcdc-pwm {
- compatible = "atmel,hlcdc-pwm";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lcd_pwm>;
- #pwm-cells = <3>;
- };
};
pinctrl@fffff200 {
/ {
ahb {
apb {
+ hlcdc: hlcdc@f0030000 {
+ atmel,vl-bpix = <4>;
+ atmel,output-mode = <24>;
+ atmel,guard-time = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb888_alt>;
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ display-timings {
+ u-boot,dm-pre-reloc;
+ 800x480 {
+ clock-frequency = <24000000>;
+ hactive = <800>;
+ vactive = <480>;
+ hsync-len = <5>;
+ hfront-porch = <64>;
+ hback-porch = <64>;
+ vfront-porch = <22>;
+ vback-porch = <21>;
+ vsync-len = <5>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+ };
+
i2c1: i2c@f0018000 {
qt1070: keyboard@1b {
compatible = "qt1070";
u-boot,dm-pre-reloc;
hlcdc: hlcdc@f0000000 {
- compatible = "atmel,sama5d4-hlcdc";
+ compatible = "atmel,at91sam9x5-hlcdc";
reg = <0xf0000000 0x4000>;
interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
clock-names = "periph_clk","sys_clk", "slow_clk";
status = "disabled";
-
- hlcdc-display-controller {
- compatible = "atmel,hlcdc-display-controller";
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
- };
- };
-
- hlcdc_pwm: hlcdc-pwm {
- compatible = "atmel,hlcdc-pwm";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lcd_pwm>;
- #pwm-cells = <3>;
- };
};
dma1: dma-controller@f0004000 {
slew-rate = <3>;
};
};
+
+ sdmmc1_pins: sdmmc@0 {
+ pins {
+ pinmux = <STM32H7_PC8_FUNC_SDMMC1_D0>,
+ <STM32H7_PC9_FUNC_SDMMC1_D1>,
+ <STM32H7_PC10_FUNC_SDMMC1_D2>,
+ <STM32H7_PC11_FUNC_SDMMC1_D3>,
+ <STM32H7_PC12_FUNC_SDMMC1_CK>,
+ <STM32H7_PD2_FUNC_SDMMC1_CMD>;
+
+ slew-rate = <3>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdmmc1_level_shifter: sdmmc0_ls@0 {
+ pins {
+ pinmux = <STM32H7_PB8_FUNC_SDMMC1_CKIN>,
+ <STM32H7_PB9_FUNC_SDMMC1_CDIR>,
+ <STM32H7_PC6_FUNC_SDMMC1_D0DIR>,
+ <STM32H7_PC7_FUNC_SDMMC1_D123DIR>;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ };
};
};
};
#include "skeleton.dtsi"
#include "armv7-m.dtsi"
#include <dt-bindings/clock/stm32h7-clks.h>
+#include <dt-bindings/mfd/stm32h7-rcc.h>
/ {
clocks {
};
usart1: serial@40011000 {
- compatible = "st,stm32h7-usart", "st,stm32h7-uart";
+ compatible = "st,stm32h7-uart";
reg = <0x40011000 0x400>;
interrupts = <37>;
status = "disabled";
};
usart2: serial@40004400 {
- compatible = "st,stm32h7-usart", "st,stm32h7-uart";
+ compatible = "st,stm32h7-uart";
reg = <0x40004400 0x400>;
interrupts = <38>;
status = "disabled";
compatible = "fixed-clock";
clock-frequency = <4000000>;
};
+
+ sdmmc1: sdmmc@52007000 {
+ compatible = "st,stm32-sdmmc2";
+ reg = <0x52007000 0x1000>;
+ interrupts = <49>;
+ clocks = <&rcc SDMMC1_CK>;
+ resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
+ st,idma = <1>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ status = "disabled";
+ };
};
};
aliases {
serial0 = &usart2;
+ mmc0 = &sdmmc1;
gpio0 = &gpioa;
gpio1 = &gpiob;
gpio2 = &gpioc;
st,sdram-refcount = <1539>;
};
};
+
+&sdmmc1 {
+ status = "okay";
+ pinctrl-0 = <&sdmmc1_pins>;
+ pinctrl-names = "default";
+ bus-width = <4>;
+ cd-gpios = <&gpioi 8 1>;
+};
st,sdram-refcount = <1539>;
};
};
+
+&sdmmc1 {
+ status = "okay";
+ pinctrl-0 = <&sdmmc1_pins>,
+ <&pinctrl_sdmmc1_level_shifter>;
+ pinctrl-names = "default";
+ bus-width = <4>;
+ st,dirpol;
+};
/* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
mrs \xreg1, mpidr_el1
lsr \xreg2, \xreg1, #32
+ lsl \xreg2, \xreg2, #32
lsl \xreg1, \xreg1, #40
lsr \xreg1, \xreg1, #40
orr \xreg1, \xreg1, \xreg2
*/
ldr x0, [x18, #GD_START_ADDR_SP] /* x0 <- gd->start_addr_sp */
bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
- ldr x18, [x18, #GD_BD] /* x18 <- gd->bd */
- sub x18, x18, #GD_SIZE /* new GD is below bd */
+ ldr x18, [x18, #GD_NEW_GD] /* x18 <- gd->new_gd */
adr lr, relocation_return
ldr x9, [x18, #GD_RELOC_OFF] /* x9 <- gd->reloc_off */
isb sy
4: ldp x0, x1, [sp, #16]
bl __asm_flush_dcache_range
-5: ldp x29, x30, [sp],#16
+5: ldp x29, x30, [sp],#32
ret
ENDPROC(relocate_code)
select AT91SAM9X5
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
config TARGET_SAMA5D2_PTC
bool "SAMA5D2 PTC board"
select SAMA5D2
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
config TARGET_SAMA5D27_SOM1_EK
bool "SAMA5D27 SOM1 EK board"
select SAMA5D4
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
config TARGET_SAMA5D4EK
bool "SAMA5D4 Evaluation Kit"
select SAMA5D4
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
config TARGET_MA5D4EVK
bool "Aries MA5D4EVK Evaluation Kit"
/* Stop the timer */
writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1);
- writel((CONFIG_SYS_CLK_FREQ/CONFIG_SYS_HZ_CLOCK) - 1,
+ writel((CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ_CLOCK) - 1,
&gpt1_regs_ptr->psc);
/* Configure timer for auto-reload */
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <debug_uart.h>
-#include <lcd.h>
-#include <atmel_hlcdc.h>
-#ifdef CONFIG_LCD_INFO
-#include <nand.h>
-#include <version.h>
-#endif
#include <asm/mach-types.h>
DECLARE_GLOBAL_DATA_PTR;
}
#endif
-#ifdef CONFIG_LCD
-vidinfo_t panel_info = {
- .vl_col = 800,
- .vl_row = 480,
- .vl_clk = 24000000,
- .vl_sync = LCDC_LCDCFG5_HSPOL | LCDC_LCDCFG5_VSPOL,
- .vl_bpix = LCD_BPP,
- .vl_tft = 1,
- .vl_clk_pol = 1,
- .vl_hsync_len = 128,
- .vl_left_margin = 64,
- .vl_right_margin = 64,
- .vl_vsync_len = 2,
- .vl_upper_margin = 22,
- .vl_lower_margin = 21,
- .mmio = ATMEL_BASE_LCDC,
-};
-
-void lcd_enable(void)
-{
- if (has_lcdc())
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 1); /* power up */
-}
-
-void lcd_disable(void)
-{
- if (has_lcdc())
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 0); /* power down */
-}
-
-static void at91sam9x5ek_lcd_hw_init(void)
-{
- if (has_lcdc()) {
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDPWM */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDVSYNC */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDHSYNC */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDISP */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDPCK */
-
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */
-
- at91_periph_clk_enable(ATMEL_ID_LCDC);
- }
-}
-
-#ifdef CONFIG_LCD_INFO
-void lcd_show_board_info(void)
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
{
- ulong dram_size, nand_size;
- int i;
- char temp[32];
-
- if (has_lcdc()) {
- lcd_printf("%s\n", U_BOOT_VERSION);
- lcd_printf("(C) 2012 ATMEL Corp\n");
- lcd_printf("at91support@atmel.com\n");
- lcd_printf("%s CPU at %s MHz\n",
- get_cpu_name(),
- strmhz(temp, get_cpu_clk_rate()));
-
- dram_size = 0;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
- dram_size += gd->bd->bi_dram[i].size;
- nand_size = 0;
- for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += get_nand_dev_by_index(i)->size;
- lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
- dram_size >> 20,
- nand_size >> 20);
- }
+#ifdef CONFIG_DM_VIDEO
+ at91_video_show_board_info();
+#endif
+ return 0;
}
-#endif /* CONFIG_LCD_INFO */
-#endif /* CONFIG_LCD */
+#endif
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI_HCD)
at91_uhp_hw_init();
-#endif
-#ifdef CONFIG_LCD
- at91sam9x5ek_lcd_hw_init();
#endif
return 0;
}
nand_size = 0;
#ifdef CONFIG_NAND_ATMEL
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i]->size;
+ nand_size += get_nand_dev_by_index(i)->size;
#endif
len += sprintf(&buf[len], "%ld MB SDRAM, %ld MB NAND\n",
*/
#include <common.h>
-#include <atmel_hlcdc.h>
#include <debug_uart.h>
-#include <lcd.h>
-#include <version.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/atmel_pio4.h>
atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1);
}
-#ifdef CONFIG_LCD
-vidinfo_t panel_info = {
- .vl_col = 480,
- .vl_row = 272,
- .vl_clk = 9000000,
- .vl_bpix = LCD_BPP,
- .vl_tft = 1,
- .vl_hsync_len = 41,
- .vl_left_margin = 2,
- .vl_right_margin = 2,
- .vl_vsync_len = 11,
- .vl_upper_margin = 2,
- .vl_lower_margin = 2,
- .mmio = ATMEL_BASE_LCDC,
-};
-
-/* No power up/down pin for the LCD pannel */
-void lcd_enable(void) { /* Empty! */ }
-void lcd_disable(void) { /* Empty! */ }
-
-unsigned int has_lcdc(void)
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
{
- return 1;
-}
-
-static void board_lcd_hw_init(void)
-{
- atmel_pio4_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDPWM */
- atmel_pio4_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDISP */
- atmel_pio4_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDVSYNC */
- atmel_pio4_set_a_periph(AT91_PIO_PORTC, 31, 0); /* LCDHSYNC */
- atmel_pio4_set_a_periph(AT91_PIO_PORTD, 0, 0); /* LCDPCK */
- atmel_pio4_set_a_periph(AT91_PIO_PORTD, 1, 0); /* LCDDEN */
-
- /* LCDDAT0 */
- /* LCDDAT1 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDDAT2 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDDAT3 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDDAT4 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDDAT5 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDDAT6 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDDAT7 */
-
- /* LCDDAT8 */
- /* LCDDAT9 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDDAT10 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDDAT11 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDDAT12 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDDAT13 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDDAT14 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDDAT15 */
-
- /* LCDD16 */
- /* LCDD17 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDDAT18 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDDAT19 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDAT20 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTC, 25, 0); /* LCDDAT21 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDDAT22 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDDAT23 */
-
- at91_periph_clk_enable(ATMEL_ID_LCDC);
-}
-
-#ifdef CONFIG_LCD_INFO
-void lcd_show_board_info(void)
-{
- ulong dram_size;
- int i;
- char temp[32];
-
- lcd_printf("%s\n", U_BOOT_VERSION);
- lcd_printf("2015 ATMEL Corp\n");
- lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
- strmhz(temp, get_cpu_clk_rate()));
-
- dram_size = 0;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
- dram_size += gd->bd->bi_dram[i].size;
-
- lcd_printf("%ld MB SDRAM\n", dram_size >> 20);
+#ifdef CONFIG_DM_VIDEO
+ at91_video_show_board_info();
+#endif
+ return 0;
}
-#endif /* CONFIG_LCD_INFO */
-#endif /* CONFIG_LCD */
+#endif
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
static void board_uart1_hw_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-#ifdef CONFIG_LCD
- board_lcd_hw_init();
-#endif
#ifdef CONFIG_CMD_USB
board_usb_hw_init();
#endif
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
#include <debug_uart.h>
-#include <lcd.h>
#include <linux/ctype.h>
-#include <atmel_hlcdc.h>
#include <phy.h>
#include <micrel.h>
#include <spl.h>
}
#endif
-#ifdef CONFIG_LCD
-vidinfo_t panel_info = {
- .vl_col = 800,
- .vl_row = 480,
- .vl_clk = 24000000,
- .vl_bpix = LCD_BPP,
- .vl_tft = 1,
- .vl_hsync_len = 128,
- .vl_left_margin = 64,
- .vl_right_margin = 64,
- .vl_vsync_len = 2,
- .vl_upper_margin = 22,
- .vl_lower_margin = 21,
- .mmio = ATMEL_BASE_LCDC,
-};
-
-void lcd_enable(void)
-{
-}
-
-void lcd_disable(void)
-{
-}
-
-static void sama5d3xek_lcd_hw_init(void)
-{
- gd->fb_base = CONFIG_SAMA5D3_LCD_BASE;
-
- /* The higher 8 bit of LCD is board related */
- at91_pio3_set_c_periph(AT91_PIO_PORTC, 14, 0); /* LCDD16 */
- at91_pio3_set_c_periph(AT91_PIO_PORTC, 13, 0); /* LCDD17 */
- at91_pio3_set_c_periph(AT91_PIO_PORTC, 12, 0); /* LCDD18 */
- at91_pio3_set_c_periph(AT91_PIO_PORTC, 11, 0); /* LCDD19 */
- at91_pio3_set_c_periph(AT91_PIO_PORTC, 10, 0); /* LCDD20 */
- at91_pio3_set_c_periph(AT91_PIO_PORTC, 15, 0); /* LCDD21 */
- at91_pio3_set_c_periph(AT91_PIO_PORTE, 27, 0); /* LCDD22 */
- at91_pio3_set_c_periph(AT91_PIO_PORTE, 28, 0); /* LCDD23 */
-
- /* Configure lower 16 bit of LCD and enable clock */
- at91_lcd_hw_init();
-}
-
-#ifdef CONFIG_LCD_INFO
-#include <nand.h>
-#include <version.h>
-
-void lcd_show_board_info(void)
-{
- ulong dram_size;
- uint64_t nand_size;
- int i;
- char temp[32];
-
- lcd_printf("%s\n", U_BOOT_VERSION);
- lcd_printf("(C) 2013 ATMEL Corp\n");
- lcd_printf("at91@atmel.com\n");
- lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
- strmhz(temp, get_cpu_clk_rate()));
-
- dram_size = 0;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
- dram_size += gd->bd->bi_dram[i].size;
-
- nand_size = 0;
-#ifdef CONFIG_NAND_ATMEL
- for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += get_nand_dev_by_index(i)->size;
-#endif
- lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
- dram_size >> 20, nand_size >> 20);
-}
-#endif /* CONFIG_LCD_INFO */
-#endif /* CONFIG_LCD */
-
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
{
#endif
#ifdef CONFIG_GENERIC_ATMEL_MCI
sama5d3xek_mci_hw_init();
-#endif
-#ifdef CONFIG_LCD
- if (has_lcdc())
- sama5d3xek_lcd_hw_init();
#endif
return 0;
}
strcat(name, "ek.dtb");
env_set("dtb_name", name);
+#endif
+#ifdef CONFIG_DM_VIDEO
+ at91_video_show_board_info();
#endif
return 0;
}
#include <asm/arch/clk.h>
#include <asm/arch/sama5d3_smc.h>
#include <asm/arch/sama5d4.h>
-#include <atmel_hlcdc.h>
#include <debug_uart.h>
-#include <lcd.h>
-#include <nand.h>
-#include <version.h>
DECLARE_GLOBAL_DATA_PTR;
}
#endif
-#ifdef CONFIG_LCD
-vidinfo_t panel_info = {
- .vl_col = 480,
- .vl_row = 272,
- .vl_clk = 9000000,
- .vl_bpix = LCD_BPP,
- .vl_tft = 1,
- .vl_hsync_len = 41,
- .vl_left_margin = 2,
- .vl_right_margin = 2,
- .vl_vsync_len = 11,
- .vl_upper_margin = 2,
- .vl_lower_margin = 2,
- .mmio = ATMEL_BASE_LCDC,
-};
-
-/* No power up/down pin for the LCD pannel */
-void lcd_enable(void) { /* Empty! */ }
-void lcd_disable(void) { /* Empty! */ }
-
-unsigned int has_lcdc(void)
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
{
- return 1;
-}
-
-static void sama5d4_xplained_lcd_hw_init(void)
-{
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
-
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
-
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
-
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
-
- /* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_LCDC);
-}
-
-#ifdef CONFIG_LCD_INFO
-void lcd_show_board_info(void)
-{
- ulong dram_size, nand_size;
- int i;
- char temp[32];
-
- lcd_printf("%s\n", U_BOOT_VERSION);
- lcd_printf("2014 ATMEL Corp\n");
- lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
- strmhz(temp, get_cpu_clk_rate()));
-
- dram_size = 0;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
- dram_size += gd->bd->bi_dram[i].size;
-
- nand_size = 0;
-#ifdef CONFIG_NAND_ATMEL
- for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += get_nand_dev_by_index(i)->size;
+#ifdef CONFIG_DM_VIDEO
+ at91_video_show_board_info();
#endif
- lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
- dram_size >> 20, nand_size >> 20);
+ return 0;
}
-#endif /* CONFIG_LCD_INFO */
-
-#endif /* CONFIG_LCD */
+#endif
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
static void sama5d4_xplained_serial3_hw_init(void)
#ifdef CONFIG_NAND_ATMEL
sama5d4_xplained_nand_hw_init();
#endif
-#ifdef CONFIG_LCD
- sama5d4_xplained_lcd_hw_init();
-#endif
#ifdef CONFIG_CMD_USB
sama5d4_xplained_usb_hw_init();
#endif
#include <asm/arch/clk.h>
#include <asm/arch/sama5d3_smc.h>
#include <asm/arch/sama5d4.h>
-#include <atmel_hlcdc.h>
#include <debug_uart.h>
-#include <lcd.h>
-#include <nand.h>
-#include <version.h>
DECLARE_GLOBAL_DATA_PTR;
}
#endif
-#ifdef CONFIG_LCD
-vidinfo_t panel_info = {
- .vl_col = 800,
- .vl_row = 480,
- .vl_clk = 33260000,
- .vl_bpix = LCD_BPP,
- .vl_tft = 1,
- .vl_hsync_len = 5,
- .vl_left_margin = 128,
- .vl_right_margin = 0,
- .vl_vsync_len = 5,
- .vl_upper_margin = 23,
- .vl_lower_margin = 22,
- .mmio = ATMEL_BASE_LCDC,
-};
-
-/* No power up/down pin for the LCD pannel */
-void lcd_enable(void) { /* Empty! */ }
-void lcd_disable(void) { /* Empty! */ }
-
-unsigned int has_lcdc(void)
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
{
- return 1;
-}
-
-static void sama5d4ek_lcd_hw_init(void)
-{
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
-
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
-
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
-
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
- at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
-
- /* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_LCDC);
-}
-
-#ifdef CONFIG_LCD_INFO
-void lcd_show_board_info(void)
-{
- ulong dram_size, nand_size;
- int i;
- char temp[32];
-
- lcd_printf("%s\n", U_BOOT_VERSION);
- lcd_printf("2014 ATMEL Corp\n");
- lcd_printf("at91@atmel.com\n");
- lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
- strmhz(temp, get_cpu_clk_rate()));
-
- dram_size = 0;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
- dram_size += gd->bd->bi_dram[i].size;
-
- nand_size = 0;
-#ifdef CONFIG_NAND_ATMEL
- for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += get_nand_dev_by_index(i)->size;
+#ifdef CONFIG_DM_VIDEO
+ at91_video_show_board_info();
#endif
- lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
- dram_size >> 20, nand_size >> 20);
+ return 0;
}
-#endif /* CONFIG_LCD_INFO */
-
-#endif /* CONFIG_LCD */
+#endif
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
static void sama5d4ek_serial3_hw_init(void)
#ifdef CONFIG_NAND_ATMEL
sama5d4ek_nand_hw_init();
#endif
-#ifdef CONFIG_LCD
- sama5d4ek_lcd_hw_init();
-#endif
#ifdef CONFIG_CMD_USB
sama5d4ek_usb_hw_init();
#endif
source "cmd/fastboot/Kconfig"
+config BUILD_BIN2C
+ bool
+
comment "Commands"
menu "Info commands"
config CMD_LZMADEC
bool "lzmadec"
+ default y if CMD_BOOTI
select LZMA
help
Support decompressing an LZMA (Lempel-Ziv-Markov chain algorithm)
config CMD_UNZIP
bool "unzip"
+ default y if CMD_BOOTI
help
Uncompress a zip-compressed memory region.
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_LCD=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_LCD=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_LCD=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_LCD=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
-CONFIG_LCD=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
-CONFIG_LCD=y
CONFIG_FAT_WRITE=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
CONFIG_ATMEL_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
-CONFIG_LCD=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
CONFIG_FAT_WRITE=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
-CONFIG_LCD=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
-CONFIG_LCD=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
CONFIG_FAT_WRITE=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
-CONFIG_LCD=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
CONFIG_FAT_WRITE=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
-CONFIG_LCD=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
-CONFIG_LCD=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
-CONFIG_LCD=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+CONFIG_BOOTARGS="console=ttyAS1,115200 CONSOLE=/dev/ttyAS1 consoleblank=0 root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait mem=992M@0x40000000 vmalloc=256m"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="stih410-b2260 => "
CONFIG_FASTBOOT=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
+CONFIG_DM_MMC=y
+CONFIG_STM32_SDMMC2=y
# CONFIG_PINCTRL_FULL is not set
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_REGEX=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
+CONFIG_DM_MMC=y
+CONFIG_STM32_SDMMC2=y
# CONFIG_PINCTRL_FULL is not set
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_REGEX=y
config STM32_SDMMC2
bool "STMicroelectronics STM32H7 SD/MMC Host Controller support"
- depends on DM_MMC && BLK && OF_CONTROL && DM_MMC_OPS
+ depends on DM_MMC && BLK && OF_CONTROL
help
This selects support for the SD/MMC controller on STM32H7 SoCs.
If you have a board based on such a SoC and with a SD/MMC slot,
config STM32X7_SERIAL
bool "STMicroelectronics STM32 SoCs on-chip UART"
- depends on DM_SERIAL && (STM32F7 || STM32H7)
+ depends on DM_SERIAL && (STM32F4 || STM32F7 || STM32H7)
help
- If you have a machine based on a STM32 F7 or H7 SoC you can
+ If you have a machine based on a STM32 F4, F7 or H7 SoC you can
enable its onboard serial ports, say Y to this option.
If unsure, say N.
static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct stm32x7_serial_platdata *plat = dev->platdata;
- struct stm32_usart *const usart = plat->base;
+ struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+ bool stm32f4 = plat->uart_info->stm32f4;
+ fdt_addr_t base = plat->base;
u32 int_div, mantissa, fraction, oversampling;
int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);
if (int_div < 16) {
oversampling = 8;
- setbits_le32(&usart->cr1, USART_CR1_OVER8);
+ setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
} else {
oversampling = 16;
- clrbits_le32(&usart->cr1, USART_CR1_OVER8);
+ clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
}
mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
fraction = int_div % oversampling;
- writel(mantissa | fraction, &usart->brr);
+ writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
return 0;
}
static int stm32_serial_getc(struct udevice *dev)
{
- struct stm32x7_serial_platdata *plat = dev->platdata;
- struct stm32_usart *const usart = plat->base;
+ struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+ bool stm32f4 = plat->uart_info->stm32f4;
+ fdt_addr_t base = plat->base;
- if ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0)
+ if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_RXNE) == 0)
return -EAGAIN;
- return readl(&usart->rd_dr);
+ return readl(base + RDR_OFFSET(stm32f4));
}
static int stm32_serial_putc(struct udevice *dev, const char c)
{
- struct stm32x7_serial_platdata *plat = dev->platdata;
- struct stm32_usart *const usart = plat->base;
+ struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+ bool stm32f4 = plat->uart_info->stm32f4;
+ fdt_addr_t base = plat->base;
- if ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0)
+ if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_TXE) == 0)
return -EAGAIN;
- writel(c, &usart->tx_dr);
+ writel(c, base + TDR_OFFSET(stm32f4));
return 0;
}
static int stm32_serial_pending(struct udevice *dev, bool input)
{
- struct stm32x7_serial_platdata *plat = dev->platdata;
- struct stm32_usart *const usart = plat->base;
+ struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+ bool stm32f4 = plat->uart_info->stm32f4;
+ fdt_addr_t base = plat->base;
if (input)
- return readl(&usart->sr) & USART_SR_FLAG_RXNE ? 1 : 0;
+ return readl(base + ISR_OFFSET(stm32f4)) &
+ USART_SR_FLAG_RXNE ? 1 : 0;
else
- return readl(&usart->sr) & USART_SR_FLAG_TXE ? 0 : 1;
+ return readl(base + ISR_OFFSET(stm32f4)) &
+ USART_SR_FLAG_TXE ? 0 : 1;
}
static int stm32_serial_probe(struct udevice *dev)
{
- struct stm32x7_serial_platdata *plat = dev->platdata;
- struct stm32_usart *const usart = plat->base;
-
-#ifdef CONFIG_CLK
- int ret;
+ struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
struct clk clk;
+ fdt_addr_t base = plat->base;
+ int ret;
+ bool stm32f4;
+ u8 uart_enable_bit;
+
+ plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
+ stm32f4 = plat->uart_info->stm32f4;
+ uart_enable_bit = plat->uart_info->uart_enable_bit;
ret = clk_get_by_index(dev, 0, &clk);
if (ret < 0)
dev_err(dev, "failed to enable clock\n");
return ret;
}
-#endif
plat->clock_rate = clk_get_rate(&clk);
if (plat->clock_rate < 0) {
return plat->clock_rate;
};
- /* Disable usart-> disable overrun-> enable usart */
- clrbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);
- setbits_le32(&usart->cr3, USART_CR3_OVRDIS);
- setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);
+ /* Disable uart-> disable overrun-> enable uart */
+ clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
+ BIT(uart_enable_bit));
+ if (plat->uart_info->has_overrun_disable)
+ setbits_le32(base + CR3_OFFSET(stm32f4), USART_CR3_OVRDIS);
+ if (plat->uart_info->has_fifo)
+ setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
+ setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
+ BIT(uart_enable_bit));
return 0;
}
-#if CONFIG_IS_ENABLED(OF_CONTROL)
static const struct udevice_id stm32_serial_id[] = {
- {.compatible = "st,stm32f7-usart"},
- {.compatible = "st,stm32f7-uart"},
- {.compatible = "st,stm32h7-usart"},
- {.compatible = "st,stm32h7-uart"},
+ { .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
+ { .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
+ { .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
{}
};
static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
{
struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
- fdt_addr_t addr;
- addr = devfdt_get_addr(dev);
- if (addr == FDT_ADDR_T_NONE)
+ plat->base = devfdt_get_addr(dev);
+ if (plat->base == FDT_ADDR_T_NONE)
return -EINVAL;
- plat->base = (struct stm32_usart *)addr;
-
return 0;
}
-#endif
static const struct dm_serial_ops stm32_serial_ops = {
.putc = stm32_serial_putc,
#ifndef _SERIAL_STM32_X7_
#define _SERIAL_STM32_X7_
-struct stm32_usart {
- u32 cr1;
- u32 cr2;
- u32 cr3;
- u32 brr;
- u32 gtpr;
- u32 rtor;
- u32 rqr;
- u32 sr;
- u32 icr;
- u32 rd_dr;
- u32 tx_dr;
+#define CR1_OFFSET(x) (x ? 0x0c : 0x00)
+#define CR3_OFFSET(x) (x ? 0x14 : 0x08)
+#define BRR_OFFSET(x) (x ? 0x08 : 0x0c)
+#define ISR_OFFSET(x) (x ? 0x00 : 0x1c)
+/*
+ * STM32F4 has one Data Register (DR) for received or transmitted
+ * data, so map Receive Data Register (RDR) and Transmit Data
+ * Register (TDR) at the same offset
+ */
+#define RDR_OFFSET(x) (x ? 0x04 : 0x24)
+#define TDR_OFFSET(x) (x ? 0x04 : 0x28)
+
+struct stm32_uart_info {
+ u8 uart_enable_bit; /* UART_CR1_UE */
+ bool stm32f4; /* true for STM32F4, false otherwise */
+ bool has_overrun_disable;
+ bool has_fifo;
+};
+
+struct stm32_uart_info stm32f4_info = {
+ .stm32f4 = true,
+ .uart_enable_bit = 13,
+ .has_overrun_disable = false,
+ .has_fifo = false,
+};
+
+struct stm32_uart_info stm32f7_info = {
+ .uart_enable_bit = 0,
+ .stm32f4 = false,
+ .has_overrun_disable = true,
+ .has_fifo = false,
+};
+
+struct stm32_uart_info stm32h7_info = {
+ .uart_enable_bit = 0,
+ .stm32f4 = false,
+ .has_overrun_disable = true,
+ .has_fifo = true,
};
/* Information about a serial port */
struct stm32x7_serial_platdata {
- struct stm32_usart *base; /* address of registers in physical memory */
+ fdt_addr_t base; /* address of registers in physical memory */
+ struct stm32_uart_info *uart_info;
unsigned long int clock_rate;
};
-#define USART_CR1_OVER8 (1 << 15)
-#define USART_CR1_TE (1 << 3)
-#define USART_CR1_RE (1 << 2)
-#define USART_CR1_UE (1 << 0)
+#define USART_CR1_FIFOEN BIT(29)
+#define USART_CR1_OVER8 BIT(15)
+#define USART_CR1_TE BIT(3)
+#define USART_CR1_RE BIT(2)
-#define USART_CR3_OVRDIS (1 << 12)
+#define USART_CR3_OVRDIS BIT(12)
-#define USART_SR_FLAG_RXNE (1 << 5)
-#define USART_SR_FLAG_TXE (1 << 7)
+#define USART_SR_FLAG_RXNE BIT(5)
+#define USART_SR_FLAG_TXE BIT(7)
-#define USART_BRR_F_MASK 0xFF
+#define USART_BRR_F_MASK GENMASK(7, 0)
#define USART_BRR_M_SHIFT 4
-#define USART_BRR_M_MASK 0xFFF0
+#define USART_BRR_M_MASK GENMASK(15, 4)
#endif
this option, such displays will not be supported and console output
will be empty.
+config VIDEO_ANSI
+ bool "Support ANSI escape sequences in video console"
+ depends on DM_VIDEO
+ default y if DM_VIDEO
+ help
+ Enable ANSI escape sequence decoding for a more fully functional
+ console.
+
config CONSOLE_NORMAL
bool "Support a simple text console"
depends on DM_VIDEO
*/
#include <common.h>
+#include <linux/ctype.h>
#include <dm.h>
#include <video.h>
#include <video_console.h>
video_sync(dev->parent);
}
+static const struct {
+ unsigned r;
+ unsigned g;
+ unsigned b;
+} colors[] = {
+ { 0x00, 0x00, 0x00 }, /* black */
+ { 0xff, 0x00, 0x00 }, /* red */
+ { 0x00, 0xff, 0x00 }, /* green */
+ { 0xff, 0xff, 0x00 }, /* yellow */
+ { 0x00, 0x00, 0xff }, /* blue */
+ { 0xff, 0x00, 0xff }, /* magenta */
+ { 0x00, 0xff, 0xff }, /* cyan */
+ { 0xff, 0xff, 0xff }, /* white */
+};
+
+static void set_color(struct video_priv *priv, unsigned idx, unsigned *c)
+{
+ switch (priv->bpix) {
+ case VIDEO_BPP16:
+ *c = ((colors[idx].r >> 3) << 0) |
+ ((colors[idx].g >> 2) << 5) |
+ ((colors[idx].b >> 3) << 11);
+ break;
+ case VIDEO_BPP32:
+ *c = 0xff000000 |
+ (colors[idx].r << 0) |
+ (colors[idx].g << 8) |
+ (colors[idx].b << 16);
+ break;
+ default:
+ /* unsupported, leave current color in place */
+ break;
+ }
+}
+
+static char *parsenum(char *s, int *num)
+{
+ char *end;
+ *num = simple_strtol(s, &end, 10);
+ return end;
+}
+
+/*
+ * Process a character while accumulating an escape string. Chars are
+ * accumulated into escape_buf until the end of escape sequence is
+ * found, at which point the sequence is parsed and processed.
+ */
+static void vidconsole_escape_char(struct udevice *dev, char ch)
+{
+ struct vidconsole_priv *priv = dev_get_uclass_priv(dev);
+
+ if (!IS_ENABLED(CONFIG_VIDEO_ANSI))
+ goto error;
+
+ /* Sanity checking for bogus ESC sequences: */
+ if (priv->escape_len >= sizeof(priv->escape_buf))
+ goto error;
+ if (priv->escape_len == 0 && ch != '[')
+ goto error;
+
+ priv->escape_buf[priv->escape_len++] = ch;
+
+ /*
+ * Escape sequences are terminated by a letter, so keep
+ * accumulating until we get one:
+ */
+ if (!isalpha(ch))
+ return;
+
+ /*
+ * clear escape mode first, otherwise things will get highly
+ * surprising if you hit any debug prints that come back to
+ * this console.
+ */
+ priv->escape = 0;
+
+ switch (ch) {
+ case 'H':
+ case 'f': {
+ int row, col;
+ char *s = priv->escape_buf;
+
+ /*
+ * Set cursor position: [%d;%df or [%d;%dH
+ */
+ s++; /* [ */
+ s = parsenum(s, &row);
+ s++; /* ; */
+ s = parsenum(s, &col);
+
+ priv->ycur = row * priv->y_charsize;
+ priv->xcur_frac = priv->xstart_frac +
+ VID_TO_POS(col * priv->x_charsize);
+
+ break;
+ }
+ case 'J': {
+ int mode;
+
+ /*
+ * Clear part/all screen:
+ * [J or [0J - clear screen from cursor down
+ * [1J - clear screen from cursor up
+ * [2J - clear entire screen
+ *
+ * TODO we really only handle entire-screen case, others
+ * probably require some additions to video-uclass (and
+ * are not really needed yet by efi_console)
+ */
+ parsenum(priv->escape_buf + 1, &mode);
+
+ if (mode == 2) {
+ video_clear(dev->parent);
+ video_sync(dev->parent);
+ priv->ycur = 0;
+ priv->xcur_frac = priv->xstart_frac;
+ } else {
+ debug("unsupported clear mode: %d\n", mode);
+ }
+ break;
+ }
+ case 'm': {
+ struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent);
+ char *s = priv->escape_buf;
+ char *end = &priv->escape_buf[priv->escape_len];
+
+ /*
+ * Set graphics mode: [%d;...;%dm
+ *
+ * Currently only supports the color attributes:
+ *
+ * Foreground Colors:
+ *
+ * 30 Black
+ * 31 Red
+ * 32 Green
+ * 33 Yellow
+ * 34 Blue
+ * 35 Magenta
+ * 36 Cyan
+ * 37 White
+ *
+ * Background Colors:
+ *
+ * 40 Black
+ * 41 Red
+ * 42 Green
+ * 43 Yellow
+ * 44 Blue
+ * 45 Magenta
+ * 46 Cyan
+ * 47 White
+ */
+
+ s++; /* [ */
+ while (s < end) {
+ int val;
+
+ s = parsenum(s, &val);
+ s++;
+
+ switch (val) {
+ case 30 ... 37:
+ /* fg color */
+ set_color(vid_priv, val - 30,
+ (unsigned *)&vid_priv->colour_fg);
+ break;
+ case 40 ... 47:
+ /* bg color */
+ set_color(vid_priv, val - 40,
+ (unsigned *)&vid_priv->colour_bg);
+ break;
+ default:
+ /* unknown/unsupported */
+ break;
+ }
+ }
+
+ break;
+ }
+ default:
+ debug("unrecognized escape sequence: %*s\n",
+ priv->escape_len, priv->escape_buf);
+ }
+
+ return;
+
+error:
+ /* something went wrong, just revert to normal mode: */
+ priv->escape = 0;
+}
+
int vidconsole_put_char(struct udevice *dev, char ch)
{
struct vidconsole_priv *priv = dev_get_uclass_priv(dev);
int ret;
+ if (priv->escape) {
+ vidconsole_escape_char(dev, ch);
+ return 0;
+ }
+
switch (ch) {
+ case '\x1b':
+ priv->escape_len = 0;
+ priv->escape = 1;
+ break;
case '\a':
/* beep */
break;
struct udevice *dev = sdev->priv;
vidconsole_put_char(dev, ch);
+ video_sync(dev->parent);
}
static void vidconsole_puts(struct stdio_dev *sdev, const char *s)
for (s = argv[1]; *s; s++)
vidconsole_put_char(dev, *s);
+ video_sync(dev->parent);
+
return 0;
}
return 0;
}
-static int video_clear(struct udevice *dev)
+void video_clear(struct udevice *dev)
{
struct video_priv *priv = dev_get_uclass_priv(dev);
} else {
memset(priv->fb, priv->colour_bg, priv->fb_size);
}
-
- return 0;
}
/* Flush video activity to the caches */
return -1;
}
- block = memalign(ARCH_DMA_MINALIGN, cur_dev->blksz);
+ block = malloc_cache_aligned(cur_dev->blksz);
if (block == NULL) {
debug("Error: allocating block\n");
return -1;
mydata->fatbufnum = -1;
mydata->fat_dirty = 0;
- mydata->fatbuf = memalign(ARCH_DMA_MINALIGN, FATBUFSIZE);
+ mydata->fatbuf = malloc_cache_aligned(FATBUFSIZE);
if (mydata->fatbuf == NULL) {
debug("Error: allocating memory\n");
return -1;
fat_itr *itr;
int ret;
- itr = malloc(sizeof(fat_itr));
+ itr = malloc_cache_aligned(sizeof(fat_itr));
+ if (!itr)
+ return 0;
ret = fat_itr_root(itr, &fsdata);
if (ret)
- return 0;
+ goto out;
ret = fat_itr_resolve(itr, filename, TYPE_ANY);
free(fsdata.fatbuf);
+out:
free(itr);
return ret == 0;
}
fat_itr *itr;
int ret;
- itr = malloc(sizeof(fat_itr));
+ itr = malloc_cache_aligned(sizeof(fat_itr));
+ if (!itr)
+ return -ENOMEM;
ret = fat_itr_root(itr, &fsdata);
if (ret)
- return ret;
+ goto out_free_itr;
ret = fat_itr_resolve(itr, filename, TYPE_FILE);
if (ret) {
*size = 0;
ret = 0;
}
- goto out;
+ goto out_free_both;
}
*size = FAT2CPU32(itr->dent->size);
+out_free_both:
free(fsdata.fatbuf);
-out:
+out_free_itr:
free(itr);
return ret;
}
fat_itr *itr;
int ret;
- itr = malloc(sizeof(fat_itr));
+ itr = malloc_cache_aligned(sizeof(fat_itr));
+ if (!itr)
+ return -ENOMEM;
ret = fat_itr_root(itr, &fsdata);
if (ret)
- return ret;
+ goto out_free_itr;
ret = fat_itr_resolve(itr, filename, TYPE_FILE);
if (ret)
- goto out;
+ goto out_free_both;
printf("reading %s\n", filename);
ret = get_contents(&fsdata, itr->dent, pos, buffer, maxsize, actread);
-out:
+out_free_both:
free(fsdata.fatbuf);
+out_free_itr:
free(itr);
return ret;
}
ret = fat_itr_root(&dir->itr, &dir->fsdata);
if (ret)
- goto fail;
+ goto fail_free_dir;
ret = fat_itr_resolve(&dir->itr, filename, TYPE_DIR);
if (ret)
- goto fail;
+ goto fail_free_both;
*dirsp = (struct fs_dir_stream *)dir;
return 0;
-fail:
+fail_free_both:
free(dir->fsdata.fatbuf);
+fail_free_dir:
free(dir);
return ret;
}
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
-/* LCD */
-#define LCD_BPP LCD_COLOR16
-#define LCD_OUTPUT_BPP 24
-#define CONFIG_LCD_LOGO
-#define CONFIG_LCD_INFO
-#define CONFIG_LCD_INFO_BELOW_LOGO
-#define CONFIG_ATMEL_HLCD
-#define CONFIG_ATMEL_LCD_RGB565
-
-
/*
* BOOTP options
*/
#define CONFIG_SF_DEFAULT_SPEED 30000000
#endif
-/* LCD */
-
-#ifdef CONFIG_LCD
-#define LCD_BPP LCD_COLOR16
-#define LCD_OUTPUT_BPP 24
-#define CONFIG_LCD_LOGO
-#define CONFIG_LCD_INFO
-#define CONFIG_LCD_INFO_BELOW_LOGO
-#define CONFIG_ATMEL_HLCD
-#define CONFIG_ATMEL_LCD_RGB565
-#endif
-
#ifdef CONFIG_SD_BOOT
/* bootstrap + u-boot + env in sd card */
*/
#define ATMEL_PMC_UHP (1 << 6)
-/* LCD */
-#define LCD_BPP LCD_COLOR16
-#define LCD_OUTPUT_BPP 24
-#define CONFIG_LCD_LOGO
-#define CONFIG_LCD_INFO
-#define CONFIG_LCD_INFO_BELOW_LOGO
-#define CONFIG_ATMEL_HLCD
-#define CONFIG_ATMEL_LCD_RGB565
-
/* board specific (not enough SRAM) */
#define CONFIG_SAMA5D3_LCD_BASE 0x23E00000
#define CONFIG_ATMEL_NAND_HW_PMECC
#endif
-/* LCD */
-#ifdef CONFIG_LCD
-#define LCD_BPP LCD_COLOR16
-#define LCD_OUTPUT_BPP 24
-#define CONFIG_LCD_LOGO
-#define CONFIG_LCD_INFO
-#define CONFIG_LCD_INFO_BELOW_LOGO
-#define CONFIG_ATMEL_HLCD
-#define CONFIG_ATMEL_LCD_RGB565
-#endif
-
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x200000
#define CONFIG_ATMEL_NAND_HW_PMECC
#endif
-/* LCD */
-#define LCD_BPP LCD_COLOR16
-#define LCD_OUTPUT_BPP 18
-#define CONFIG_LCD_LOGO
-#define CONFIG_LCD_INFO
-#define CONFIG_LCD_INFO_BELOW_LOGO
-#define CONFIG_ATMEL_HLCD
-#define CONFIG_ATMEL_LCD_RGB565
-
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x200000
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x40000000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define PHYS_SDRAM_1_SIZE 0x3FE00000
+#define PHYS_SDRAM_1_SIZE 0x3E000000
#define CONFIG_SYS_TEXT_BASE 0x7D600000
#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 /* default load addr */
#define CONFIG_SYS_HZ_CLOCK 1000000000 /* 1 GHz */
+#include <config_distro_defaults.h>
/* Environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "board= B2260" \
- "load_addr= #CONFIG_SYS_LOAD_ADDR \0"
+
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(USB, usb, 0) \
+ func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "kernel_addr_r=0x40000000\0" \
+ "fdtfile=stih410-b2260.dtb\0" \
+ "fdt_addr_r=0x47000000\0" \
+ "scriptaddr=0x50000000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "ramdisk_addr_r=0x48000000\0" \
+ BOOTENV
+
#define CONFIG_ENV_SIZE 0x4000
#include <config.h>
#define CONFIG_SYS_FLASH_BASE 0x08000000
-#define CONFIG_SYS_INIT_SP_ADDR 0x30020000
+#define CONFIG_SYS_INIT_SP_ADDR 0x24040000
#define CONFIG_SYS_TEXT_BASE 0x08000000
/*
#include <config.h>
#define CONFIG_SYS_FLASH_BASE 0x08000000
-#define CONFIG_SYS_INIT_SP_ADDR 0x30020000
+#define CONFIG_SYS_INIT_SP_ADDR 0x24040000
#define CONFIG_SYS_TEXT_BASE 0x08000000
/*
*/
int video_reserve(ulong *addrp);
+/**
+ * video_clear() - Clear a device's frame buffer to background color.
+ *
+ * @dev: Device to clear
+ */
+void video_clear(struct udevice *dev);
+
/**
* video_sync() - Sync a device's frame buffer with its hardware
*
* @xsize_frac: Width of the display in fractional units
* @xstart_frac: Left margin for the text console in fractional units
* @last_ch: Last character written to the text console on this line
+ * @escape: TRUE if currently accumulating an ANSI escape sequence
+ * @escape_len: Length of accumulated escape sequence so far
+ * @escape_buf: Buffer to accumulate escape sequence
*/
struct vidconsole_priv {
struct stdio_dev sdev;
int xsize_frac;
int xstart_frac;
int last_ch;
+ /*
+ * ANSI escape sequences are accumulated character by character,
+ * starting after the ESC char (0x1b) until the entire sequence
+ * is consumed at which point it is acted upon.
+ */
+ int escape;
+ int escape_len;
+ char escape_buf[32];
};
/**
DEFINE(GD_START_ADDR_SP, offsetof(struct global_data, start_addr_sp));
+ DEFINE(GD_NEW_GD, offsetof(struct global_data, new_gd));
+
return 0;
}
+++ /dev/null
-config BUILD_BIN2C
- bool
return 0;
}
+static void vidconsole_put_string(struct udevice *dev, const char *str)
+{
+ const char *s;
+
+ for (s = str; *s; s++)
+ vidconsole_put_char(dev, *s);
+}
+
/* Test text output works on the video console */
static int dm_test_video_text(struct unit_test_state *uts)
{
{
struct udevice *dev, *con;
const char *test_string = "Well\b\b\b\bxhe is\r \n\ta very \amodest \bman\n\t\tand Has much to\b\bto be modest about.";
- const char *s;
ut_assertok(select_vidconsole(uts, "vidconsole0"));
ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev));
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
- for (s = test_string; *s; s++)
- vidconsole_put_char(con, *s);
+ vidconsole_put_string(con, test_string);
ut_asserteq(466, compress_frame_buffer(dev));
return 0;
}
DM_TEST(dm_test_video_chars, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+#ifdef CONFIG_VIDEO_ANSI
+#define ANSI_ESC "\x1b"
+/* Test handling of ANSI escape sequences */
+static int dm_test_video_ansi(struct unit_test_state *uts)
+{
+ struct udevice *dev, *con;
+
+ ut_assertok(select_vidconsole(uts, "vidconsole0"));
+ ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev));
+ ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
+
+ /* reference clear: */
+ video_clear(con->parent);
+ video_sync(con->parent);
+ ut_asserteq(46, compress_frame_buffer(dev));
+
+ /* test clear escape sequence: [2J */
+ vidconsole_put_string(con, "A\tB\tC"ANSI_ESC"[2J");
+ ut_asserteq(46, compress_frame_buffer(dev));
+
+ /* test set-cursor: [%d;%df */
+ vidconsole_put_string(con, "abc"ANSI_ESC"[2;2fab"ANSI_ESC"[4;4fcd");
+ ut_asserteq(142, compress_frame_buffer(dev));
+
+ /* test colors (30-37 fg color, 40-47 bg color) */
+ vidconsole_put_string(con, ANSI_ESC"[30;41mfoo"); /* black on red */
+ vidconsole_put_string(con, ANSI_ESC"[33;44mbar"); /* yellow on blue */
+ ut_asserteq(268, compress_frame_buffer(dev));
+
+ return 0;
+}
+DM_TEST(dm_test_video_ansi, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+#endif
+
/**
* check_vidconsole_output() - Run a text console test
*
{
struct udevice *dev, *con;
const char *test_string = "Criticism may not be agreeable, but it is necessary. It fulfils the same function as pain in the human body. It calls attention to an unhealthy state of things. Some see private enterprise as a predatory target to be shot, others as a cow to be milked, but few are those who see it as a sturdy horse pulling the wagon. The \aprice OF\b\bof greatness\n\tis responsibility.\n\nBye";
- const char *s;
ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev));
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
- for (s = test_string; *s; s++)
- vidconsole_put_char(con, *s);
+ vidconsole_put_string(con, test_string);
ut_asserteq(12619, compress_frame_buffer(dev));
return 0;
struct sandbox_sdl_plat *plat;
struct udevice *dev, *con;
const char *test_string = "Criticism may not be agreeable, but it is necessary. It fulfils the same function as pain in the human body. It calls attention to an unhealthy state of things. Some see private enterprise as a predatory target to be shot, others as a cow to be milked, but few are those who see it as a sturdy horse pulling the wagon. The \aprice OF\b\bof greatness\n\tis responsibility.\n\nBye";
- const char *s;
ut_assertok(uclass_find_device(UCLASS_VIDEO, 0, &dev));
ut_assert(!device_active(dev));
ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev));
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
- for (s = test_string; *s; s++)
- vidconsole_put_char(con, *s);
+ vidconsole_put_string(con, test_string);
ut_asserteq(33849, compress_frame_buffer(dev));
return 0;
struct sandbox_sdl_plat *plat;
struct udevice *dev, *con;
const char *test_string = "...Criticism may or may\b\b\b\b\b\bnot be agreeable, but seldom it is necessary\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\bit is necessary. It fulfils the same function as pain in the human body. It calls attention to an unhealthy state of things.";
- const char *s;
ut_assertok(uclass_find_device(UCLASS_VIDEO, 0, &dev));
ut_assert(!device_active(dev));
ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev));
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
- for (s = test_string; *s; s++)
- vidconsole_put_char(con, *s);
+ vidconsole_put_string(con, test_string);
ut_asserteq(34871, compress_frame_buffer(dev));
return 0;
projects / people / ms / u-boot.git / commitdiff
