Remove platform CONFIG_SYS_HZ definition for configs a-z*.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
#define CONFIG_NR_DRAM_BANKS_MAX 2
-/* 1KHz clock tick */
-#define CONFIG_SYS_HZ 1000
-
/* UART configuration */
#if (CONFIG_SYS_LPC32XX_UART >= 3) && (CONFIG_SYS_LPC32XX_UART <= 6)
#define CONFIG_SYS_NS16550_SERIAL
#ifndef CONFIG_SYS_MAXARGS
# define CONFIG_SYS_MAXARGS 16
#endif
-#if defined(CONFIG_SYS_HZ)
-# if (CONFIG_SYS_HZ != 1000)
-# warning "CONFIG_SYS_HZ must always be 1000"
-# endif
-# undef CONFIG_SYS_HZ
-#endif
-#define CONFIG_SYS_HZ 1000
/* Blackfin POST tests */
#ifdef CONFIG_POST_BSPEC1_GPIO_LEDS
/*
* Timer
*/
-#define CONFIG_SYS_HZ 1000 /* timer ticks per second */
/*
* Real Time Clock
#define CONFIG_SYS_LOAD_ADDR 0x00100000
-#define CONFIG_SYS_HZ 1000
#define CONFIG_LOOPW
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-/* decrementer freq: 1ms ticks */
-#define CONFIG_SYS_HZ 1000
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
/* timer clock - 2* OSC_IN system clock */
#define CONFIG_IXP425_TIMER_CLK 66666666
-#define CONFIG_SYS_HZ 1000
/* default load address */
#define CONFIG_SYS_LOAD_ADDR 0x00010000
/* timer clock - 2* OSC_IN system clock */
#define CONFIG_IXP425_TIMER_CLK 66666666
-#define CONFIG_SYS_HZ 1000
/* default load address */
#define CONFIG_SYS_LOAD_ADDR 0x00010000
/* timer clock - 2* OSC_IN system clock */
#define CONFIG_IXP425_TIMER_CLK 66666666
-#define CONFIG_SYS_HZ 1000
/* default load address */
#define CONFIG_SYS_LOAD_ADDR 0x00010000
/* timer clock - 2* OSC_IN system clock */
#define CONFIG_IXP425_TIMER_CLK 66000000
-#define CONFIG_SYS_HZ 1000
/* default load address */
#define CONFIG_SYS_LOAD_ADDR 0x00010000
/*
* Timer
*/
-
-/*
- * According to the discussion in u-boot mailing list before,
- * CONFIG_SYS_HZ at 1000 is mandatory.
- */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CLK_FREQ 48000000
#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
/*
* Timer
*/
-
-/*
- * According to the discussion in u-boot mailing list before,
- * CONFIG_SYS_HZ at 1000 is mandatory.
- */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CLK_FREQ 39062500
#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
/*
* Timer
*/
-
-/*
- * According to the discussion in u-boot mailing list before,
- * CONFIG_SYS_HZ at 1000 is mandatory.
- */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CLK_FREQ (66000000 * 2)
#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_SYS_HZ 1000
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
*/
#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* Physical Memory Map
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO /* To use extended board_into (bd_t) */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_CMDLINE_EDITING /* add command line history */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_LOOPW /* enable loopw command */
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
-#define CONFIG_SYS_HZ 1000
#endif /* __AP325RXA_H */
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
-#define CONFIG_SYS_HZ 1000
#endif /* __AP_SH4A_4A_H */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ 1000
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
-#define CONFIG_SYS_HZ 1000
#endif /* __ARMADILLO_800EVA_H */
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_RD_LVL
#define CONFIG_NR_DRAM_BANKS 8
/*
* Defines processor clock - important for correct timings concerning serial
* interface etc.
- * CONFIG_SYS_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms
*/
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CLK 80000000
#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3)
#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39)
#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3 )
#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
-#define CONFIG_SYS_HZ 1000
/* CPU configuration */
#define CONFIG_AT91RM9200
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
-#define CONFIG_SYS_HZ 1000
/* Define actual evaluation board type from used processor type */
#ifdef CONFIG_AT91SAM9G20
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
-#define CONFIG_SYS_HZ 1000
#ifdef CONFIG_AT91SAM9G10
#define CONFIG_AT91SAM9G10EK /* It's an Atmel AT91SAM9G10 EK*/
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_SYS_HZ 1000
#define CONFIG_AT91SAM9263EK 1 /* It's an AT91SAM9263EK Board */
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_AT91SAM9M10G45EK
#define CONFIG_AT91FAMILY
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */
-#define CONFIG_SYS_HZ 1000
/* Misc CPU related */
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_AT91SAM9RLEK 1 /* It's an AT91SAM9RLEK Board */
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_AT91SAM9X5EK
#define CONFIG_AT91FAMILY
#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 /* "bad" address */
#define CONFIG_SYS_ALLOC_DPRAM
#define CONFIG_AT32AP7000
#define CONFIG_ATNGW100
-#define CONFIG_SYS_HZ 1000
-
/*
* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
* frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
#define CONFIG_AT32AP7000
#define CONFIG_ATNGW100MKII
-/*
- * Timer clock frequency. We're using the CPU-internal COUNT register
- * for this, so this is equivalent to the CPU core clock frequency
- */
-#define CONFIG_SYS_HZ 1000
-
/*
* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
* frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
#define CONFIG_ATSTK1002
#define CONFIG_ATSTK1000
-/*
- * Timer clock frequency. We're using the CPU-internal COUNT register
- * for this, so this is equivalent to the CPU core clock frequency
- */
-#define CONFIG_SYS_HZ 1000
-
/*
* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
* frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
#define CONFIG_ATSTK1003
#define CONFIG_ATSTK1000
-/*
- * Timer clock frequency. We're using the CPU-internal COUNT register
- * for this, so this is equivalent to the CPU core clock frequency
- */
-#define CONFIG_SYS_HZ 1000
-
/*
* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
* frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
#define CONFIG_ATSTK1004
#define CONFIG_ATSTK1000
-/*
- * Timer clock frequency. We're using the CPU-internal COUNT register
- * for this, so this is equivalent to the CPU core clock frequency
- */
-#define CONFIG_SYS_HZ 1000
-
/*
* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
* frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
#define CONFIG_ATSTK1006
#define CONFIG_ATSTK1000
-/*
- * Timer clock frequency. We're using the CPU-internal COUNT register
- * for this, so this is equivalent to the CPU core clock frequency
- */
-#define CONFIG_SYS_HZ 1000
/*
* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
#define CONFIG_SYS_OSCIN_FREQ calimain_get_osc_freq()
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_TEXT_BASE 0x60000000
#define CONFIG_DA850_LOWLEVEL
#define CONFIG_SYS_DA850_PLL_INIT
#define CONFIG_ARM926EJS /* arm926ejs CPU */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SOC_DM365
#define CONFIG_MACH_TYPE MACH_TYPE_DAVINCI_DM365_EVM
#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */
-#define CONFIG_SYS_HZ (1000) /* 1ms resolution ticks */
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */
-#define CONFIG_SYS_HZ (1000) /* 1ms resolution ticks */
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_LOOPW 1
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
/*
* Various low-level settings
*/
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* Physical Memory Map
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* Decrementer freq: 1 ms ticks */
-
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 }
/* ---
* Defines processor clock - important for correct timings concerning serial
* interface etc.
- * CONFIG_SYS_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms
* ---
*/
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CLK 66000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
/*
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#define CONFIG_SYS_ALLOC_DPRAM
/*
* Clock Configuration
*/
-#define CONFIG_SYS_HZ 1000 /* Timer @ 3250000 Hz */
#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
/*
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_HZ 1000
#define CONFIG_HW_WATCHDOG
#define CONFIG_LOADS_ECHO
#define CONFIG_SYS_LOADS_BAUD_CHANGE
#define CONFIG_SYS_MEMTEST_START 0x00100000
#define CONFIG_SYS_MEMTEST_END 0x01000000
#define CONFIG_SYS_LOAD_ADDR 0x100000
-#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* SDRAM Configuration
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#if defined(CONFIG_CPU9G20)
#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39)
#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3)
#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
-#define CONFIG_SYS_HZ 1000
#define CONFIG_ARM920T
#define CONFIG_AT91RM9200
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_TEXT_BASE 0xc1080000
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_DA850_PLL_INIT
#define CONFIG_SYS_DA850_DDR_INIT
#define CONFIG_ARM926EJS /* arm926ejs CPU */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SOC_DM355
/* Memory Info */
#define CONFIG_ARM926EJS /* arm926ejs CPU */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SOC_DM355 /* DM355 based board */
/* Memory Info */
#define CONFIG_ARM926EJS /* arm926ejs CPU */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SOC_DM365
/* Memory Info */
/* Timer Input clock freq */
#define CONFIG_SYS_HZ_CLOCK (CONFIG_SYS_CLK_FREQ/2)
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SOC_DM646X
/* EEPROM definitions for EEPROM */
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SOC_DM644X
/*====================================================*/
/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SOC_DM644X
/*=============*/
/* Memory Info */
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SOC_DM644X
/* EEPROM definitions for Atmel 24LC64 EEPROM chip */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SOC_DM644X
/*====================================================*/
/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
/*-----------------------------------------------------------------------
* PCI stuff
*/
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
*/
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* Physical Memory Map
#define CONFIG_SYS_LOAD_ADDR 0x00100000
-#define CONFIG_SYS_HZ 1000
-
/*
* Various low-level settings
*/
/* timer clock - 2* OSC_IN system clock */
#define CONFIG_IXP425_TIMER_CLK 66666666
-#define CONFIG_SYS_HZ 1000
/* default load address */
#define CONFIG_SYS_LOAD_ADDR 0x00010000
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 /* for MPC8240 only */
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_TEXT_BASE 0xc1080000
#define CONFIG_DA8XX_GPIO
/*----------------------------------------------------------------------*
* Clock and PLL Configuration *
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */
/* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
#define AT91C_MAIN_CLOCK 179404800 /* from 12.288 MHz * 73 / 5 */
#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3)
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
-#define CONFIG_SYS_HZ 1000
#endif /* __ECOVEC_H */
* CLKs configurations
*/
-#define CONFIG_SYS_HZ 1000
-
/*
* Board-specific values for Orion5x MPP low level init:
* - MPPs 12 to 15 are SATA LEDs (mode 5)
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SYS_HZ 1000
#define CONFIG_DA850_LOWLEVEL
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_DA850_PLL_INIT
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#define CONFIG_SYS_FLASH_BASE 0xFF800000
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
/*-----------------------------------------------------------------------
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
-#define CONFIG_SYS_HZ 1000
/* Ether */
#define CONFIG_SH_ETHER 1
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
-#define CONFIG_SYS_HZ 1000
/* 32kB internal SRAM */
#define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_RD_LVL
#define CONFIG_NR_DRAM_BANKS 8
#define CONFIG_FAVR32_EZKIT_EXT_FLASH
-/*
- * Timer clock frequency. We're using the CPU-internal COUNT register
- * for this, so this is equivalent to the CPU core clock frequency
- */
-#define CONFIG_SYS_HZ 1000
-
/*
* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
* frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
-
/*
* Physical Memory Map
*/
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_DISPLAY_BOARDINFO 1
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
/*
* Various low-level settings
*/
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
/*-----------------------------------------------------------------------
* USB stuff
*-----------------------------------------------------------------------
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
/*
* Various low-level settings
*/
#define CONFIG_AT32AP
#define CONFIG_AT32AP7000
-/*
- * Timer clock frequency. We're using the CPU-internal COUNT register
- * for this, so this is equivalent to the CPU core clock frequency
- */
-#define CONFIG_SYS_HZ 1000
-
/*
* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
* frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
/***** Gaisler GRLIB IP-Cores Config ********/
/* AMBA Plug & Play info display on startup */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
/***** Gaisler GRLIB IP-Cores Config ********/
#define CONFIG_SYS_GRLIB_SDRAM 0
#define CONFIG_CLOCKS_IN_MHZ
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
/* memtest works from the end of the exception vector table
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
#define CONFIG_AT32AP7000
#define CONFIG_HAMMERHEAD
-#define CONFIG_SYS_HZ 1000
-
/*
* Set up the PLL to run at 125 MHz, the CPU to run at the PLL
* frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_AIS_CONFIG_FILE "board/$(BOARDDIR)/hawkboard-ais-nand.cfg"
#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_SYS_ALLOC_DPRAM 1 /* use allocation routines */
/*
* Low Level Configuration Settings
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SYS_NO_FLASH
-#define CFG_HZ 1000
-#define CONFIG_SYS_HZ CFG_HZ
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
/*
* Enable loopw command.
*/
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#define CONFIG_SYS_I2C_SPEED 50000
/* Platform/Board specific defs */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000 /* 1ms clock */
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550
*/
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
/*
* Physical Memory Map
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
/* Physical Memory Map */
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_MX27
#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_LOAD_ADDR 0 /* default load address */
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_CMDLINE_EDITING 1
/*-----------------------------------------------------------------------
#define CONFIG_SYS_LOAD_ADDR 0 /* default load address */
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_CMDLINE_EDITING
/*
#define CONFIG_SYS_MIPS_TIMER_FREQ (incaip_get_cpuclk() / 2)
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_LOAD_ADDR 0x80100000 /* default load address */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
/*
* Enable loopw command.
*/
#define CONFIG_SYS_TEXT_BASE 0x01000000
#define CONFIG_SYS_MEMTEST_START 0x100000
#define CONFIG_SYS_MEMTEST_END 0x10000000
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */
#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_DA850_PLL_INIT
#define CONFIG_SYS_DA850_DDR_INIT
#define CONFIG_SYS_TEXT_BASE 0xc1080000
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_LOOPW
/*
#define CONFIG_MB86R0x
#define CONFIG_MB86R0x_IOCLK get_bus_freq(0)
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_TEXT_BASE 0x10000000
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
#define CONFIG_SYS_BARGSIZE 256 /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0xc0040000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0xc2000000 /* 4..128 MB */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CPUSPEED 0x0a /* core clock 206MHz */
#define CONFIG_SYS_BAUDRATE_TABLE { 19200, 38400, 57600, 115200 }
#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#define CONFIG_SYS_ALT_MEMTEST /* memory test, takes time */
-#define CONFIG_SYS_HZ 1000 /* decr. freq: 1 ms ticks */
-
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_SYS_MEMTEST_END 0x07C00000
#define CONFIG_SYS_LOAD_ADDR 0x00100000
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_CPU_CLK (1196000000)
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
-#define CFG_HZ (1000)
-#define CONFIG_SYS_HZ CFG_HZ
/* Ether */
#define CONFIG_NET_MULTI
/* FIXME: 32.768 MHz is the crystal frequency but */
/* the real frequency is lower by about 0.75% */
#define CONFIG_SYS_CLK_FREQ 32768000
-#define CONFIG_SYS_HZ 1000
/* Bit-field values for MCCR1. */
#define CONFIG_SYS_ROMNAL 0
#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_AUTO_COMPLETE 1
-/*
- * Clock Configuration
- */
-#define CONFIG_SYS_HZ 1000 /* Timer @ 3250000 Hz */
-
/*
* DRAM Map
*/
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
#ifdef CONFIG_MMC
#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
/*
* When the watchdog is enabled, output must be fast enough in Linux.
*/
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_MX53
#define CONFIG_MXC_GPIO
-#define CONFIG_SYS_HZ 1000
#include <asm/arch/imx-regs.h>
/*use Hardware WDT */
#define CONFIG_HW_WATCHDOG
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
*/
#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
/*
* Physical Memory Map
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ 1000
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq */
/* Misc CPU related */
#define CONFIG_SKIP_LOWLEVEL_INIT
/* architecture dependent code */
#define CONFIG_SYS_USR_EXCEP /* user exception */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo"
#define CONFIG_MIMC200_EXT_FLASH
-#define CONFIG_SYS_HZ 1000
-
/*
* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
* frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default kernel load addr */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
/*
* Various low-level settings
*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */
-
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
-#define CONFIG_SYS_HZ 1000
/* UART */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
-#define CONFIG_SYS_HZ 1000
/* PCMCIA */
#define CONFIG_IDE_PCMCIA 1
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
-#define CONFIG_SYS_HZ 1000
#endif /* __MS7722SE_H */
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
-#define CONFIG_SYS_HZ 1000
#endif /* __MS7750SE_H */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_DISPLAY_BOARDINFO 1
#define CONFIG_CMDLINE_EDITING 1
/*
* CLKs configurations
*/
-#define CONFIG_SYS_HZ 1000
/*
* NS16550 Configuration
#define CONFIG_SYS_MEMTEST_END 0x0AF00000 /* 63 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x08800000 /* default load address */
-/*#define CONFIG_SYS_HZ 1000 */
#define CONFIG_SYS_HZ 3686400
#define CONFIG_SYS_CPUSPEED 0x141
/* High Level Configuration Options */
#define CONFIG_MX25
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_TEXT_BASE 0x81200000
#define CONFIG_MXC_GPIO
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_CMDLINE_EDITING 1
/*-----------------------------------------------------------------------
/* default load address */
#define CONFIG_SYS_LOAD_ADDR 0x81000000
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_CMDLINE_EDITING
/*-----------------------------------------------------------------------
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
-
/*
* Physical Memory Map
*/
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
/*-----------------------------------------------------------------------
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
/*-----------------------------------------------------------------------
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
/* Physical Memory Map */
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
/* Physical Memory Map */
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
/* Physical Memory Map */
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
/* Physical Memory Map */
#define CONFIG_SYS_MEMTEST_END 0x10010000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
#define CONFIG_STACKSIZE (128 * 1024)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_512M)
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
#define CONFIG_STACKSIZE SZ_128K
* CPU specifics
*/
-/* Ticks per second */
-#define CONFIG_SYS_HZ 1000
-
/* MXS uses FDT */
#define CONFIG_OF_LIBFDT
#define CONFIG_BOARD_LATE_INIT /* call board_late_init during start up */
/* timing informazion */
-#define CONFIG_SYS_HZ 1000 /* Mandatory... */
#define CONFIG_SYS_TIMERBASE 0x101E2000
/* serial port (PL011) configuration */
#define CONFIG_SYS_LOW_RES_TIMER
#define CONFIG_SYS_NIOS_TMRBASE CONFIG_SYS_TIMER_BASE
#define CONFIG_SYS_NIOS_TMRIRQ CONFIG_SYS_TIMER_IRQ
-#define CONFIG_SYS_HZ 1000 /* Always 1000 */
#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/
#define CONFIG_SYS_NIOS_TMRCNT \
(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_TIMER_FREQ / 1000) - 1)
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
*/
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
/*
* Stack sizes
#define CONFIG_SYS_LOAD_ADDR 0x100000
/* decrementer freq: 1 ms ticks */
-#define CONFIG_SYS_HZ 1000
/*
* Various low-level settings
*/
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
/* Size of environment - 128KB */
#define CONFIG_ENV_SIZE (128 << 10)
*/
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
/*
* Physical Memory Map
*/
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
*/
#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* Physical Memory Map
/* Use General purpose timer 1 */
#define CONFIG_SYS_TIMERBASE GPT2_BASE
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
/*
* SDRAM Memory Map
*/
#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
-#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* Physical Memory Map
/*
* TIMER
*/
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_OPENRISC_TMR_HZ 100
/*
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
-#define CONFIG_SYS_HZ 1000
-
/* ORIGEN has 4 bank of DRAM */
#define CONFIG_NR_DRAM_BANKS 4
#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq */
/* Misc CPU related */
#define CONFIG_SKIP_LOWLEVEL_INIT
/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
/*
* For booting Linux, the board info and command line data
/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_LOAD_ADDR 0x08000000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
* Clock Configuration
*/
#undef CONFIG_SYS_CLKS_IN_HZ
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */
/*
#define CONFIG_SYS_MIPS_TIMER_FREQ 396000000
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_DISPLAY_BOARDINFO 1
/* Platform/Board specific defs */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000 /* 1ms clock */
#define CONFIG_CONS_INDEX 1
/* NS16550 Configuration */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_LYNXKDI 1 /* support kdi files */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Decrementer freq: 1ms ticks */
-#define CONFIG_SYS_HZ 1000
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */
#define CONFIG_IXP425_TIMER_CLK 66666666
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
/***************************************************************
* Platform/Board specific defines start here.
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261"
#define CONFIG_PM9261 1 /* on a Ronetix PM9261 Board */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263"
#define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */
#define CONFIG_ARCH_CPU_INIT
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_TEXT_BASE 0x73f00000
#define CONFIG_ARCH_CPU_INIT
*/
#define CONFIG_SYS_BUS_CLK CONFIG_BUS_CLK
-#define CONFIG_SYS_HZ 1000
/*
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR 0x140000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */
/* the exception vector table */
#define CONFIG_SYS_LOAD_ADDR 0xa0800000 /* default load address */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
#define RTC 1 /* enable 32KHz osc */
*/
#define CONFIG_SYS_MHZ 250 /* arbitrary value */
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_DCACHE_SIZE 16384 /* arbitrary value */
#define CONFIG_SYS_ICACHE_SIZE 16384 /* arbitrary value */
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-#define CONFIG_SYS_HZ 1000
-
/* Cached addr */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-#define CONFIG_SYS_HZ 1000
-
/* Cached addr */
#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
-#define CONFIG_SYS_HZ 1000
#endif /* __R0P7734_H */
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
/*
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
-#define CONFIG_SYS_HZ 1000
/* PCI Controller */
#if defined(CONFIG_CMD_PCI)
*/
#define CONFIG_MACH_TYPE MACH_TYPE_BCM2708
-/* Timer */
-#define CONFIG_SYS_HZ 1000
-
/* Memory layout */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000000)
-#define CONFIG_SYS_HZ 1000
-
/* Goni has 3 banks of DRAM, but swap the bank */
#define CONFIG_NR_DRAM_BANKS 3
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
-#define CONFIG_SYS_HZ 1000
-
/* Universal has 2 banks of DRAM */
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_SYS_ALT_MEMTEST /* Select full-featured memory test */
#define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_AT91FAMILY
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_ENV_SIZE 8192
#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_SYS_HZ 1000
-
/* Memory things - we don't really want a memory test */
#define CONFIG_SYS_LOAD_ADDR 0x00000000
#define CONFIG_SYS_MEMTEST_START 0x00100000
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12.000 MHz crystal */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
/*-----------------------------------------------------------------------
* IIC stuff
*-----------------------------------------------------------------------
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
-#define CONFIG_SYS_HZ 1000
#endif /* __SH7752EVB_H */
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
-#define CONFIG_SYS_HZ 1000
#endif /* __SH7757LCR_H */
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
-#define CONFIG_SYS_HZ 1000
/* Ether */
#define CONFIG_SH_ETHER 1
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
-#define CONFIG_SYS_HZ 1000
#endif /* __SH7785LCR_H */
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
-#define CONFIG_SYS_HZ 1000
/* Network device */
#define CONFIG_DRIVER_NE2000
+ (8 * 1024 * 1024))
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
-#define CONFIG_SYS_HZ 1000 /* 1ms clock */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
/* Platform/Board specific defs */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_LOAD_ADDR 0x30800000
-#define CONFIG_SYS_HZ 1000
-
/* support additional compression methods */
#define CONFIG_BZIP2
#define CONFIG_LZO
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5e00000)
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_HZ 1000
-
/* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
-#define CONFIG_SYS_HZ 1000
-
/* SMDKV310 has 4 bank of DRAM */
#define CONFIG_NR_DRAM_BANKS 4
#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_SYS_HZ 1000
/* CPU */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_MEMTEST_START 0x00000000
#define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF
-#define CONFIG_SYS_HZ 1000 /* must be 1000 */
/*-----------------------------------------------------------------------
* Size of environment and malloc() pool
/* reload value when timer count to zero */
#define TIMER_LOAD_VAL 0xFFFFFFFF
/* Timer info */
-#define CONFIG_SYS_HZ 1000
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_TIMER_CLOCK_KHZ 2400
#else
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_LOAD_ADDR 0x00100000
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_SYS_BAUDRATE_TABLE { 2400, 4800, 9600, 19200 }
/*
#define CONFIG_I2C_CHIPADDRESS 0x50
/* Timer, HZ specific defines */
-#define CONFIG_SYS_HZ 1000
/* Flash configuration */
#if defined(CONFIG_FLASH_PNOR)
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */
-#define CONFIG_SYS_HZ 1000 /* 1ms resolution */
/* misc settings */
#define CONFIG_CMDLINE_TAG /* pass commandline to Kernel */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
/*
* For booting Linux, the board info and command line data
*/
#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
/*
* Physical Memory Map
#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_TCLOCK_RATE/4)
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_LOAD_ADDR 0x80400000 /* default load address */
#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
-#define CONFIG_SYS_HZ 1000
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
+ PHYS_DRAM_1_SIZE - (8 << 12))
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default */
-#define CONFIG_SYS_HZ 1000 /* 1ms clock */
#define CONFIG_OMAP_GPIO
#define CONFIG_MMC
*/
#define CONFIG_SYS_TIMERBASE 0x4802E000
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550
#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
-#define CONFIG_SYS_HZ 1000 /* 1ms clock */
#define CONFIG_CMD_ASKEN
#define CONFIG_CMD_ECHO
/* Timer information. */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000 /* 1ms clock */
/* I2C IP block */
#define CONFIG_I2C
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_TIMERBASE TNETV107X_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get_rate(TNETV107X_LPSC_TIMER0)
-#define CONFIG_SYS_HZ 1000
#define CONFIG_PLL_SYS_EXT_FREQ 25000000
#define CONFIG_PLL_TDM_EXT_FREQ 19200000
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
-#define CONFIG_SYS_HZ 1000
/* Misc CPU related */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
-#define CONFIG_SYS_HZ 1000
-
/* TRATS has 4 banks of DRAM */
#define CONFIG_NR_DRAM_BANKS 4
#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
*/
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
#ifdef CONFIG_MMC
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ 1000
-
#define CONFIG_CMDLINE_EDITING
/* MMC boot support */
*/
#define CONFIG_MX25
#define CONFIG_MX25_CLK32 32000 /* OSC32K frequency */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */
#define CONFIG_SYS_MEMTEST_START 0x00000000
#define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF
-#define CONFIG_SYS_HZ 1000 /* must be 1000 */
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
/*
*------------------------------------------------------------------*/
#define CONFIG_SYS_CLK_FREQ 33000000
-#define CONFIG_SYS_HZ 1000
/*#define CONFIG_SYS_ETH_DEV_FN 0x7800 */
/*#define CONFIG_SYS_ETH_IOBASE 0x00104000 */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#define CONFIG_MIPS32 /* MIPS 4Kc CPU core */
#define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */
#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SKIP_LOWLEVEL_INIT /* SDRAM is initialized by the bootstrap code */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
-#define CONFIG_SYS_HZ 1000 /* 1ms ticks */
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_MEMTEST_START V2M_BASE
#define CONFIG_SYS_MEMTEST_END 0x20000000
-#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_SYS_MEMTEST_END 0x87C00000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
/*
* Stack sizes
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_HUSH_PARSER
/* clocks */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */
#define MHZ180
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max num of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */
-#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
/*
* Clock Configuration
*/
-#define CONFIG_SYS_HZ 1000 /* Timer @ 3250000 Hz */
#define CONFIG_SYS_CPUSPEED 0x190 /* 312MHz */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
-
-
/*
* Stack sizes
*
#include <asm/arch/hardware.h>
/* Timer, HZ specific defines */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_HZ_CLOCK 8300000
#define CONFIG_SYS_TEXT_BASE 0x00800040
#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */
/*
/* default load address */
#define CONFIG_SYS_EXTBDINFO 1
/* Extended board_into (bd_t) */
-#define CONFIG_SYS_HZ 1000
/* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING /* add command line history */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */
#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
#define CONFIG_PANIC_HANG /* do not reset board on panic */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */
#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_MX25
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_TEXT_BASE 0xA0000000
#define CONFIG_MACH_TYPE MACH_TYPE_ZMX25
/* CPU clock */
#define CONFIG_CPU_FREQ_HZ 800000000
-#define CONFIG_SYS_HZ 1000
/* Ram */
#define CONFIG_NR_DRAM_BANKS 1
projects / people / ms / u-boot.git / commitdiff
