people/ms/u-boot.git
4 years agoeeprom: fix eeprom write procedure
Alexey Brodkin [Mon, 14 Dec 2015 15:45:34 +0000 (18:45 +0300)] 
eeprom: fix eeprom write procedure

This fixes commit 1a37889b0ad084a740b4f785031d7ae9955d947b:
----------------------->8--------------------
eeprom: Pull out the RW loop

Unify the code for doing read/write into single function, since the
code for both the read and write is almost identical. This again
trims down the code duplication.
----------------------->8--------------------

where the same one routine is utilized for both EEPROM writing and
reading. The only difference was supposed to be a "read" flag which
in both cases was set with 1 somehow.

That lead to a missing delay in case of writing which lead to write
failure (in my case no data was written).

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Acked-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Heiko Schocher <hs@denx.de>
4 years agoRevert "include/linux: move typdef for uintptr_t"
York Sun [Wed, 16 Dec 2015 06:12:24 +0000 (14:12 +0800)] 
Revert "include/linux: move typdef for uintptr_t"

This reverts commit e8f954a756a825130d11b9c8fca70101dd8b3ac5, which
causes compiling errors on 32-bit hosts.

Acked-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
4 years agoMerge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Tue, 15 Dec 2015 01:27:23 +0000 (20:27 -0500)] 
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

4 years agoarmv8: Add sata support on Layerscape ARMv8 board
Tang Yuantian [Wed, 9 Dec 2015 07:32:18 +0000 (15:32 +0800)] 
armv8: Add sata support on Layerscape ARMv8 board

Freescale ARM-based Layerscape contains a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2080aqds, ls2080ardb and
ls1043aqds boards.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
4 years agodrivers/crypto/fsl: fix endianness issue in RNG
Aneesh Bansal [Tue, 8 Dec 2015 08:24:30 +0000 (13:54 +0530)] 
drivers/crypto/fsl: fix endianness issue in RNG

For Setting and clearing the bits in SEC Block registers
sec_clrbits32() and sec_setbits32() are used which work as
per endianness of CAAM block.
So these must be used with SEC register address as argument.
If the value is read in a local variable, then the functions
will not behave correctly where endianness of CAAM and core is
different.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
CC: Alex Porosanu <alexandru.porosanu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
4 years agoarmv8/ls1043ardb: add SECURE BOOT target for NOR
Aneesh Bansal [Tue, 8 Dec 2015 08:24:29 +0000 (13:54 +0530)] 
armv8/ls1043ardb: add SECURE BOOT target for NOR

LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
4 years agoinclude/linux: move typdef for uintptr_t
Aneesh Bansal [Tue, 8 Dec 2015 08:24:28 +0000 (13:54 +0530)] 
include/linux: move typdef for uintptr_t

uintptr_t which is a typdef for unsigned long is needed for creating
pointers (32 or 64 bit depending on Core) from 32 bit variables
storing the address.
If a 32 bit variable (u32) is typecasted to a pointer (void *),
compiler gives a warning in case size of pointer on the core is 64 bit.

The typdef has been moved from include/compiler.h to include/linux/types.h

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
4 years agoarmv8: Make SEC read/write as snoopable for LS1043
Aneesh Bansal [Tue, 8 Dec 2015 08:24:27 +0000 (13:54 +0530)] 
armv8: Make SEC read/write as snoopable for LS1043

For LS1043, SEC read/writes are made snoopable by setting
the corresponding bits in SCFG to avoid coherency issues.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
4 years agoarmv8: define usec2ticks function
Aneesh Bansal [Tue, 8 Dec 2015 08:24:26 +0000 (13:54 +0530)] 
armv8: define usec2ticks function

usec2ticks() function has been defined for ARMv8 which will
be used by SEC Driver.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
4 years agofsl_qspi: Pet the watchdog while reading/writing
Alexander Stein [Wed, 4 Nov 2015 08:19:10 +0000 (09:19 +0100)] 
fsl_qspi: Pet the watchdog while reading/writing

When reading a large blob. e.g. a linux kernel (several MiBs) a watchdog
timeout might occur meanwhile. So pet the watchdog while operating on
the flash.

Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Reviewed-by: York Sun <yorksun@freescale.com>
4 years agoarmv8: fsl-layerscale: Rewrite reserving memory for MC and debug server
York Sun [Mon, 7 Dec 2015 19:08:58 +0000 (11:08 -0800)] 
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server

MC and debug server are not board-specific. Move reserving memory to SoC
file, using the new board_reserve_ram_top function. Reduce debug server
memory by 2MB to make room for secure memory.

In the system with MC and debug server, the top of u-boot memory
is not the end of memory. PRAM is not used for this reservation.

Signed-off-by: York Sun <yorksun@freescale.com>
4 years agocommon: Rewrite hiding the end of memory
York Sun [Mon, 7 Dec 2015 19:05:29 +0000 (11:05 -0800)] 
common: Rewrite hiding the end of memory

As the name may be confusing, the CONFIG_SYS_MEM_TOP_HIDE reserves
some memory from the end of ram, tracked by gd->ram_size. It is not
always the top of u-boot visible memory. Rewrite the macro with a
weak function to provide flexibility for complex calcuation. Legacy
use of this macro is still supported.

Signed-off-by: York Sun <yorksun@freescale.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agoarmv8: fsl-layerscape: Make DDR non secure in MMU tables
York Sun [Fri, 4 Dec 2015 19:57:08 +0000 (11:57 -0800)] 
armv8: fsl-layerscape: Make DDR non secure in MMU tables

DDR has been set as secure in MMU tables. Non-secure master such
as SDHC DMA cannot access data correctly. Mixing secure and non-
secure MMU entries requirs the MMU tables themselves in secure
memory. This patch moves MMU tables into a secure DDR area.

Early MMU tables are changed to set DDR as non-secure. A new
table is added into final MMU tables so secure memory can have
2MB granuality.

gd->secure_ram tracks the location of this secure memory. For
ARMv8 SoCs, the RAM base is not zero and RAM is divided into several
banks. gd->secure_ram needs to be maintained before using. This
maintenance is board-specific, depending on the SoC and memory
bank of the secure memory falls into.

Signed-off-by: York Sun <yorksun@freescale.com>
4 years agoReserve secure memory
York Sun [Fri, 4 Dec 2015 19:57:07 +0000 (11:57 -0800)] 
Reserve secure memory

Secure memory is at the end of memory, separated and reserved
from OS, tracked by gd->secure_ram. Secure memory can host
MMU tables, security monitor, etc. This is different from PRAM
used to reserve private memory. PRAM offers memory at the top
of u-boot memory, not necessarily the real end of memory for
systems with very large DDR. Using the end of memory simplifies
MMU setup and avoid memory fragmentation.

"bdinfo" command shows gd->secure_ram value if this memory is
marked as secured.

Signed-off-by: York Sun <yorksun@freescale.com>
4 years agomove erratum a008336 and a008514 to soc specific file
Yao Yuan [Sat, 5 Dec 2015 06:59:14 +0000 (14:59 +0800)] 
move erratum a008336 and a008514 to soc specific file

As the errata A008336 and A008514 do not apply to all LS series SoCs
(such as LS1021A, LS1043A) we move them to an soc specific file

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
4 years agoarmv7/fsl-ls102xa: Workaround for DDR erratum A008514
Yao Yuan [Sat, 5 Dec 2015 06:59:13 +0000 (14:59 +0800)] 
armv7/fsl-ls102xa: Workaround for DDR erratum A008514

This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.

The value: 63b2_0042h comes from the hardware team.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
4 years agoarmv7: ls102xa: cci-400: Enable snoop and DVM message requests.
Yao Yuan [Sat, 5 Dec 2015 06:59:12 +0000 (14:59 +0800)] 
armv7: ls102xa: cci-400: Enable snoop and DVM message requests.

Enable snoop and DVM message on all CCI-400 slave ports. Setting
on disabled feature (snoop or DVM) is ignored by CCI-400.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
[York Sun: Add commit message]
Reviewed-by: York Sun <yorksun@freescale.com>
4 years agoarmv7: omap-common: Rework SPL board_mmc_init()
Tom Rini [Mon, 14 Dec 2015 16:08:38 +0000 (11:08 -0500)] 
armv7: omap-common: Rework SPL board_mmc_init()

Since the changes in a1e56cf the way that we had board_mmc_init()
structured for OMAP parts (so that we always report device 0) are no
longer functional.  For now, make the case of booting from the second
device initialize both devices (we have no devices that only have the
second device as MMC).  A further rework and consolidation of the
functions should be done at a later date.

Tested on Beaglebone Black (SD and eMMC boot).

Reported-by: Vagrant Cascadian <vagrant@debian.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
4 years agospl: mmc: use block device number, not hard-coded 0
Eric Nelson [Sat, 5 Dec 2015 19:32:28 +0000 (12:32 -0700)] 
spl: mmc: use block device number, not hard-coded 0

In order to support boot from multiple devices through board_boot_order,
it's necessary to use the block number of a device.

The use of a hard-coded 0 for the device number also creates a need
to re-order block devices for use in SPL like this:
http://git.denx.de/?p=u-boot.git;a=blob;f=board/freescale/mx6slevk/mx6slevk.c;hb=HEAD#l195

Signed-off-by: Eric Nelson <eric@nelint.com>
4 years agoarm: ls102xa: enable all the snoop signal for masters.
Yao Yuan [Sat, 5 Dec 2015 06:59:11 +0000 (14:59 +0800)] 
arm: ls102xa: enable all the snoop signal for masters.

Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.

SNPCNFGCR contains the bits to drive snoop signal
for various masters.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
4 years agoarm: ls1021a: merge SoC specific code in a separate file
Yao Yuan [Sat, 5 Dec 2015 06:59:10 +0000 (14:59 +0800)] 
arm: ls1021a: merge SoC specific code in a separate file

Create a soc.c file to put the code for soc special settings.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
4 years agoqbman_portal.c: Update BUG_ON() call in qbman_swp_mc_submit
Tom Rini [Sat, 28 Nov 2015 13:04:42 +0000 (08:04 -0500)] 
qbman_portal.c: Update BUG_ON() call in qbman_swp_mc_submit

With gcc-5.x we get a warning about the ambiguity of BUG_ON(!a != b) and
becomes BUG_ON((!a) != b).  In this case reading of the function leads to
us wanting to rewrite this as BUG_ON(a != b).

Cc: Prabhakar Kushwaha <prabhakar@freescale.com>
Cc: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Cc: Haiying Wang <Haiying.Wang@freescale.com>
Cc: Roy Pledge <Roy.Pledge@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <yorksun@freescale.com>
4 years agofsl_*_serdes.c: Modify memset call in serdes_init
Tom Rini [Sat, 28 Nov 2015 13:04:41 +0000 (08:04 -0500)] 
fsl_*_serdes.c: Modify memset call in serdes_init

GCC 5.x does not like sizeof(array_variable) and errors out.  Change these
calls to be instead sizeof(u8) (as that's what serdes_prtcl_map is) *
SERDES_PRCTL_COUNT (the number of array elements).

Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <yorksun@freescale.com>
4 years agoEnable console log from earlyconsole in Linux bootargs
Pratiyush Mohan Srivastava [Sat, 31 Oct 2015 10:20:18 +0000 (15:50 +0530)] 
Enable console log from earlyconsole in Linux bootargs

Remove 115200 from "earlycon" to avoid loss of initial
log messages during linux kernel 4.1  bootup

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
4 years agoarmv8/ls1043ardb: Add support for >2GB memory
Shaohui Xie [Mon, 23 Nov 2015 07:23:48 +0000 (15:23 +0800)] 
armv8/ls1043ardb: Add support for >2GB memory

This patch also expose the complete DDR region(s) to Linux.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
4 years agofsl/ddr: updated ddr errata-A008378 for arm and power SoCs
Shengzhou Liu [Fri, 20 Nov 2015 07:52:04 +0000 (15:52 +0800)] 
fsl/ddr: updated ddr errata-A008378 for arm and power SoCs

DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0,
T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on
LS102x Rev2.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
4 years agofsl/errata: move fsl_errata.h to common directory
Shengzhou Liu [Fri, 20 Nov 2015 07:52:03 +0000 (15:52 +0800)] 
fsl/errata: move fsl_errata.h to common directory

move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h
to make it public for both ARM and POWER SoCs.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: fix soc.h path in fsl_errata.h]
Reviewed-by: York Sun <yorksun@freescale.com>
4 years agoarm: ls102x: add get_svr and IS_SVR_REV helper
Shengzhou Liu [Fri, 20 Nov 2015 07:52:02 +0000 (15:52 +0800)] 
arm: ls102x: add get_svr and IS_SVR_REV helper

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
4 years agofreescale: fman: make sure phy-handle property is big endian
Shaohui Xie [Tue, 10 Nov 2015 11:20:16 +0000 (19:20 +0800)] 
freescale: fman: make sure phy-handle property is big endian

When creating phy-handle property, an unsigned int value is created by
fdt_create_phandle, and memcpy is used to get the value, since DTS is
big endian, the value cannot be used directly on little endian SoCs,
it should be converted by cpu_to_fdt32.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
4 years agoarmv8/ls2080ardb: Update DDR settings for four chip-select case
York Sun [Wed, 4 Nov 2015 18:03:23 +0000 (10:03 -0800)] 
armv8/ls2080ardb: Update DDR settings for four chip-select case

When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm,
and 2T timing is enabled.

Signed-off-by: York Sun <yorksun@freescale.com>
4 years agoarmv8/ls2080aqds: Update DDR settings for four chip-select case
York Sun [Wed, 4 Nov 2015 18:03:22 +0000 (10:03 -0800)] 
armv8/ls2080aqds: Update DDR settings for four chip-select case

When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm,
and 2T timing is enabled.

Signed-off-by: York Sun <yorksun@freescale.com>
4 years agodriver/ddr/fsl: Update timing config for heavy load
York Sun [Wed, 4 Nov 2015 18:03:21 +0000 (10:03 -0800)] 
driver/ddr/fsl: Update timing config for heavy load

In case four chip-selects are all active, the turnaround times need to
increase to avoid overlapping under heavy load.

Signed-off-by: York Sun <yorksun@freescale.com>
4 years agodriver/ddr/fsl: Update workaround for A008511 for vref range
York Sun [Wed, 4 Nov 2015 18:03:20 +0000 (10:03 -0800)] 
driver/ddr/fsl: Update workaround for A008511 for vref range

The workaround requires different setting for range 1 vs 2.
Also adjust timeout value for waiting for controller to be idle.

Signed-off-by: York Sun <yorksun@freescale.com>
4 years agodriver/ddr/fsl: Update MR5 RTT park
York Sun [Wed, 4 Nov 2015 18:03:19 +0000 (10:03 -0800)] 
driver/ddr/fsl: Update MR5 RTT park

For four chip-selects enabled case, RTT is parked on all of them.

Signed-off-by: York Sun <yorksun@freescale.com>
4 years agodriver/ddr/fsl: Update DDR4 MR6 for Vref range
York Sun [Wed, 4 Nov 2015 18:03:18 +0000 (10:03 -0800)] 
driver/ddr/fsl: Update DDR4 MR6 for Vref range

MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec.

Signed-off-by: York Sun <yorksun@freescale.com>
4 years agodriver/ddr/fsl: Update DDR4 RTT values
York Sun [Wed, 4 Nov 2015 18:03:17 +0000 (10:03 -0800)] 
driver/ddr/fsl: Update DDR4 RTT values

DDR4 has different RTT value and code according to JEDEC spec. Update
the macros and options .

Signed-off-by: York Sun <yorksun@freescale.com>
4 years agopart: fix "part list ... -bootable varname" to use hex
Stephen Warren [Wed, 9 Dec 2015 16:48:04 +0000 (09:48 -0700)] 
part: fix "part list ... -bootable varname" to use hex

Unfortunately U-Boot assumes that almost all numbers are in hex, including
partition numbers passed to e.g. "load". So, the command "part list mmc 0
-bootable devplist" should use hex when writing partition numbers into
$devplist, so they'll be correctly interpreted.

Change-Id: I9a70b19749643876baadb45efbc3decaef8bfee2
Fixes: 0798d6fd4191 ("part: Add support for list filtering on bootable partitions")
Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
4 years agotools: env: include compiler.h
Peter Robinson [Wed, 9 Dec 2015 07:15:33 +0000 (07:15 +0000)] 
tools: env: include compiler.h

With gcc 5.2 and later we get a bunch of "error: unknown type name" for
'uint8_t', 'uint32_t' and friends.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
4 years agom68k: add private libgcc
angelo@sysam.it [Sun, 6 Dec 2015 16:47:59 +0000 (17:47 +0100)] 
m68k: add private libgcc

Add private libgcc

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
4 years agocommon: cli_hush: Fix up simple typo
Nishanth Menon [Fri, 4 Dec 2015 19:02:11 +0000 (13:02 -0600)] 
common: cli_hush: Fix up simple typo

Correct the spelling for character..

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agosiemens,am33x: remove ddr3 delay workaround
Egli, Samuel [Wed, 2 Dec 2015 14:27:57 +0000 (15:27 +0100)] 
siemens,am33x: remove ddr3 delay workaround

Signed-off-by: Samuel Egli <samuel.egli@siemens.com>
Cc: Roger Meier <r.meier@siemens.com>
Cc: Heiko Schocher <hs@denx.de>
4 years agoam33xx,ddr3: fix ddr3 sdram configuration
Egli, Samuel [Wed, 2 Dec 2015 14:27:56 +0000 (15:27 +0100)] 
am33xx,ddr3: fix ddr3 sdram configuration

This patch fixes the DDR3 initialization procedure in
order to comply with DDR3 standard. A 500 us delay is specified
between the DDR3 reset and clock enable signal. Until now,
this delay was not respected. Some DDR3 chips don't bother
but the bigger the RAM becomes the more likely it seems that
this delay is needed. We observed that DRAM > 256 MB from
the manufacturer Samsung have an issue when the specification
is not respected.

Changes:

1) Add a 1 ms wait for L3 timeout error trigger

2) Don't delay DDR3 initialization
Bit 31 of emif_sdram_ref_ctrl shouldn't be set because his
suppresses the initialization of DDR3

Signed-off-by: Samuel Egli <samuel.egli@siemens.com>
Reviewed-by: James Doublesin <doublesin@ti.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Roger Meier <r.meier@siemens.com>
Cc: Heiko Schocher <hs@denx.de>
4 years agoVxWorks: fixup MAC address for VxWorks
Miao Yan [Wed, 2 Dec 2015 07:39:01 +0000 (23:39 -0800)] 
VxWorks: fixup MAC address for VxWorks

VxWorks 7 kernels retrieve 'local-mac-addr' from dtb and use
that for NIC MAC address. As a result, when booting the same
kernel image on multiple boards, there will be address
conflicts.

So fixup MAC address when booting VxWorks 7 kernels

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agostm32: Convert serial driver to DM
Kamil Lulko [Tue, 1 Dec 2015 08:08:19 +0000 (09:08 +0100)] 
stm32: Convert serial driver to DM

Signed-off-by: Kamil Lulko <kamil.lulko@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agoMerge branch 'master' of git://git.denx.de/u-boot-spi
Tom Rini [Fri, 11 Dec 2015 20:07:44 +0000 (15:07 -0500)] 
Merge branch 'master' of git://git.denx.de/u-boot-spi

4 years agospi: xilinx: Add new compatible strings
Michal Simek [Fri, 11 Dec 2015 11:41:14 +0000 (12:41 +0100)] 
spi: xilinx: Add new compatible strings

Add xlnx,xps-spi-2.00.a/b which is compatible string
listed in the Linux kernel.
Remove origin one which has no real background.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
4 years agomailmap: Update Jagan Teki's name and email address
Jagan Teki [Sun, 6 Dec 2015 19:56:13 +0000 (01:26 +0530)] 
mailmap: Update Jagan Teki's name and email address

Used quite different name's and e-mail address, all of
them mapped to standard name and e-mail address.

Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
4 years agosf: Rename sf_ops.c to spi-flash.c
Jagan Teki [Sun, 6 Dec 2015 17:59:02 +0000 (23:29 +0530)] 
sf: Rename sf_ops.c to spi-flash.c

Since all spi-flash core operations are moved into
sf_ops.c then it's better to renamed as spi-flash.c

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
4 years agosf: Use static for file-scope functions
Jagan Teki [Sun, 6 Dec 2015 16:14:12 +0000 (21:44 +0530)] 
sf: Use static for file-scope functions

Used static for file-scope functions in sf_probe.c

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
4 years agosf: sf_probe: Remove spi_slave pointer argument
Jagan Teki [Sun, 6 Dec 2015 16:03:32 +0000 (21:33 +0530)] 
sf: sf_probe: Remove spi_slave pointer argument

Since spi_slave is a spi pointer in spi_flash{} then assign
spi_slave{} pointer to flash->spi and remove spi_slave
pointer argument to
- spi_flash_probe_slave
- spi_flash_scan

Tested-by: Jagan Teki <jteki@openedev.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
4 years agosf: ops: Fix missing break on spansion read_bar
Jagan Teki [Fri, 20 Nov 2015 07:30:15 +0000 (13:00 +0530)] 
sf: ops: Fix missing break on spansion read_bar

For assigning read_bar commands in spansion case, break
is missing this patch add that break.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
4 years agosf: Remove unneeded SST_BP and SST_WP
Jagan Teki [Wed, 25 Nov 2015 19:33:33 +0000 (01:03 +0530)] 
sf: Remove unneeded SST_BP and SST_WP

SST parts added on sf_params.c supports both SST_WR which consits
of both BP and WP and there is a spi controller ich which supports
only BP so the relevent _write hook set based on "slave->op_mode_tx"
hence there is no respective change required from flash side hance
removed these.

Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
4 years agosf: Remove unneeded header includes
Jagan Teki [Tue, 3 Nov 2015 19:10:32 +0000 (00:40 +0530)] 
sf: Remove unneeded header includes

Removed unneeded header includes in sf_ops and sf_probe

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
4 years agosf: Flash power up read-only based on idcode0
Jagan Teki [Tue, 29 Sep 2015 20:31:23 +0000 (02:01 +0530)] 
sf: Flash power up read-only based on idcode0

Using macro's for flash power up read-only access code
leads wrong behaviour hence use idcode0 for runtime
detection, hence the flash which require this functionality
gets detected at runtime.

Tested-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
4 years agosf: Use simple name for register access functions
Jagan Teki [Tue, 29 Sep 2015 16:59:33 +0000 (22:29 +0530)] 
sf: Use simple name for register access functions

Most of the register access function are static,
so used simple name to represent each.

Tested-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
4 years agosf: Fix Makefile
Jagan Teki [Tue, 29 Sep 2015 13:46:29 +0000 (19:16 +0530)] 
sf: Fix Makefile

This patch removes unneeded ifdef and fixed accordingly.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
4 years agosf: Use static for file-scope functions
Jagan Teki [Tue, 29 Sep 2015 12:56:08 +0000 (18:26 +0530)] 
sf: Use static for file-scope functions

Use static for file-scope functions and removed
them from header files.

Tested-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
4 years agosf: probe: Code cleanup
Jagan Teki [Tue, 3 Nov 2015 18:57:35 +0000 (00:27 +0530)] 
sf: probe: Code cleanup

- Move bar read code below the bar write hance both
  at once place, hence it easy for #ifdef macro only
  once and readable.
- Move read_cmd_array at top

Tested-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
4 years agosf: Move read_id code to sf_ops
Jagan Teki [Tue, 29 Sep 2015 12:36:04 +0000 (18:06 +0530)] 
sf: Move read_id code to sf_ops

read_id code is related to spi_flash stuff
hence moved to sf_ops.

Tested-by: Jagan Teki <jteki@openedev.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
4 years agosf: Move spi_flash_scan code to sf_ops
Jagan Teki [Fri, 11 Dec 2015 16:06:34 +0000 (21:36 +0530)] 
sf: Move spi_flash_scan code to sf_ops

Intension is that sf_ops should deals all spi_flash
related stuff and sf_probe (which should renamed future)
should be an interface layer for spi_flash versus spi drivers.

sf_ops => spi_flash interface
sf_probe => interface layer vs spi_flash(sf_probe) to spi drivers

Tested-by: Jagan Teki <jteki@openedev.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
4 years agosf: spi_flash_validate_params => spi_flash_scan
Jagan Teki [Tue, 29 Sep 2015 11:58:20 +0000 (17:28 +0530)] 
sf: spi_flash_validate_params => spi_flash_scan

Rename spi_flash_validate_params to spi_flash_scan
as this code not only deals with params setup but
also configure all spi_flash attributes.

And also moved all flash related code into
spi_flash_scan for future functionality addition.

Tested-by: Jagan Teki <jteki@openedev.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
4 years agospi: Kconfig: Fix correct target name for ZynqMP
Michal Simek [Mon, 7 Dec 2015 10:33:58 +0000 (11:33 +0100)] 
spi: Kconfig: Fix correct target name for ZynqMP

ZynqMP is using different symbol.
Use correct one.

Reviewed-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4 years agospi: zynq_spi: Add cadence compatible string
Michal Simek [Mon, 7 Dec 2015 12:06:54 +0000 (13:06 +0100)] 
spi: zynq_spi: Add cadence compatible string

Extend compatible list table for cdns,spi-r1p6 compatible string.

Reviewed-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4 years agoimx: mx7dsabresd: Add QSPI support
Peng Fan [Mon, 30 Nov 2015 09:45:02 +0000 (17:45 +0800)] 
imx: mx7dsabresd: Add QSPI support

Support qspi flashes for mx7dsabresd
1. introduce pin mux settings
2. enable qspi clock
3. introduce related macro definitions

Default QSPI is not enabled, since we need hardware rework to use QSPI,
see SPF-28590, page 9:
"
QSPI signals are muxed with EPDC_D[7:0]
When using QSPI: de-populate R388-R391, R396-R399
populate R392-R395, R299, R300
"

After hardware rework, define CONFIG_FSL_QSPI in mx7dsabresd.h. qspi
flashes can be deteced and read/erase/write. Log info:
"
=> sf probe
SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB
=> sf read 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Read: OK
=> sf erase 0 0x4000000
SF: 67108864 bytes @ 0x0 Erased: OK
=> sf write 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Written: OK
"

Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Adrian Alonso <aalonso@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
4 years agospi: ti_qspi: Fix SPI_3WIRE checking using mode
Jagan Teki [Thu, 3 Dec 2015 16:55:20 +0000 (22:25 +0530)] 
spi: ti_qspi: Fix SPI_3WIRE checking using mode

SPI_3WIRE is spi mode not spi flags, so this patch fixed
the spi-3wire checking throgh mode instead of flags.

Cc: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
4 years agospi: Get spi-3wire from dts
Jagan Teki [Thu, 3 Dec 2015 16:49:05 +0000 (22:19 +0530)] 
spi: Get spi-3wire from dts

spi-3wire is used when SI/SO signals shared so get
the same from dts node and assign to mode on slave
plat->mode.

Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
4 years agoMerge git://git.denx.de/u-boot-dm
Tom Rini [Fri, 11 Dec 2015 15:29:28 +0000 (10:29 -0500)] 
Merge git://git.denx.de/u-boot-dm

4 years agoMerge branch 'master' of http://git.denx.de/u-boot-sunxi
Tom Rini [Fri, 11 Dec 2015 14:06:51 +0000 (09:06 -0500)] 
Merge branch 'master' of git.denx.de/u-boot-sunxi

4 years agoKconfig: i2c: Fix indentation
Michal Simek [Tue, 8 Dec 2015 10:18:54 +0000 (11:18 +0100)] 
Kconfig: i2c: Fix indentation

Use tabs instead of space for indentation.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agoKconfig: i2c: Fix typo Suport -> Support
Michal Simek [Tue, 8 Dec 2015 10:18:53 +0000 (11:18 +0100)] 
Kconfig: i2c: Fix typo Suport -> Support

Fix typo in command description.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agodm: serial: Minor coding style cleanup of some comments
Stefan Roese [Thu, 26 Nov 2015 12:38:43 +0000 (13:38 +0100)] 
dm: serial: Minor coding style cleanup of some comments

Fix incorrect comment alignments.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
4 years agodm: core: Fix Kconfig text to mention SPL in SPL_OF_TRANSLATE
Stefan Roese [Thu, 26 Nov 2015 12:38:01 +0000 (13:38 +0100)] 
dm: core: Fix Kconfig text to mention SPL in SPL_OF_TRANSLATE

Add a remark about SPL to this Kconfig option. Otherwise its identitcal
to the non-SPL version, which is confusing.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
4 years agobuildman: README: add links for toolchains not available on kernel.org
Thomas Chou [Thu, 12 Nov 2015 01:29:09 +0000 (09:29 +0800)] 
buildman: README: add links for toolchains not available on 

Add links for toolchains not available on kernel.org.

The sh4 toolchains from kernel.org dose not work for some boards,
so use the sh from Sourcery.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agosunxi: Fix H3 DRAM DQ read delay configuration
Jens Kuske [Thu, 10 Dec 2015 10:41:02 +0000 (11:41 +0100)] 
sunxi: Fix H3 DRAM DQ read delay configuration

The read delays were set incorrectly, leading to reliability
issues at higher DRAM clock speeds. This commit adjusts this
to match the vendor boot0 behaviour.

Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Tested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
4 years agosun4i: clock: Cleanup some whitespace errors
Olliver Schinagl [Thu, 3 Dec 2015 16:49:29 +0000 (17:49 +0100)] 
sun4i: clock: Cleanup some whitespace errors

Add some spaces around operators.

Signed-off-by: Olliver Schinagl <o.schinagl@ultimaker.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
4 years agosunxi: twi: Enable clocks on sun7i
Olliver Schinagl [Thu, 3 Dec 2015 16:49:28 +0000 (17:49 +0100)] 
sunxi: twi: Enable clocks on sun7i

Commit 6c739c5d added code to enable i2c bus 4 and 5 on the sun7i SoC
but forgot to extend the range check in clock_twi_onoff, resulting in
the clock not getting enabled.

The range-check is not needed at all, since clock_twi_onoff only gets
called with such high indexes when CONFIG_I2C3_ENABLE / CONFIG_I2C4_ENABLE
is set and Kconfig already only allows these on sun6i / sun7i.

This commit removes the range-check all together fixing i2c bus 4 and 5
not working on sun7i.

Signed-off-by: Olliver Schinagl <o.schinagl@ultimaker.com>
[hdegoede@redhat.com] Remove range check instead of extending it
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
4 years agosunxi: select SYS_NS16550 from Kconfig
Hans de Goede [Thu, 10 Dec 2015 10:10:17 +0000 (11:10 +0100)] 
sunxi: select SYS_NS16550 from Kconfig

Select SYS_NS16550 from Kconfig instead of setting it in all our
defconfig files.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
4 years agosunxi: Add suport for A83T HomletV2 Board by Allwinner
vishnupatekar [Sat, 28 Nov 2015 17:07:27 +0000 (01:07 +0800)] 
sunxi: Add suport for A83T HomletV2 Board by Allwinner

Add dts and defconfig for h8homletv2 board.

H8Homlet Proto v2.0 Board is A83T Dev Board by Allwinner.
It has UART, ethernet, USB, HDMI, etc ports on it.
A83T patches are tested on this board.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
4 years agosunxi: dts: sun8i: Add Allwinner A83T dtsi
vishnupatekar [Sat, 28 Nov 2015 17:07:26 +0000 (01:07 +0800)] 
sunxi: dts: sun8i: Add Allwinner A83T dtsi

Allwinner A83T is new octa-core cortex-a7 SOC.
This adds the basic dtsi, the clocks differs from
earlier sun8i SOCs.

This is not yet included in kernel.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
4 years agosunxi: Add support for Allwinner A83T DRAM
vishnupatekar [Sat, 28 Nov 2015 17:07:25 +0000 (01:07 +0800)] 
sunxi: Add support for Allwinner A83T DRAM

Add support for A83T dram. Register are different from sun8i A33.
init code is similar to A33 dram init.
hope we'll shift duplicate code in dram_sun8i_*
to dram helper in future.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
4 years agosunxi: clk: add basic clocks for A83T
vishnupatekar [Sat, 28 Nov 2015 17:07:24 +0000 (01:07 +0800)] 
sunxi: clk: add basic clocks for A83T

Add basic clocks pll1, pll5, and some default values from allwinner u-boot.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
[hdegoede@redhat.com] Fix PLL6 init to run at 600 MHz instead of 288 MHz,
fixing the mmc support not working
[hdegoede@redhat.com] Fix PLL init code to properly wait for the PLL-s to
stabilize, fixing cold-booting directly from sdcard not working
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
4 years agosunxi: power: enabled support for axp818
vishnupatekar [Sat, 28 Nov 2015 17:07:22 +0000 (01:07 +0800)] 
sunxi: power: enabled support for axp818

Enabled support for AXP818 in SPL and u-boot.
DCDC1, DCDC2, DCDC3 and DCSC5 are enabled.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
4 years agosunxi: power: axp818: add support for axp818 driver
vishnupatekar [Sat, 28 Nov 2015 17:07:21 +0000 (01:07 +0800)] 
sunxi: power: axp818: add support for axp818 driver

AXP818 is rsb based PMIC and used on Allwinner A83T H8 Homlet dev board.
It's registers are different and calculating reg config is different than
that of earlier axp power ICs.

DCDC1, DCDC2, DCDC3 and DCDC5 is implemented at the moment.
all other voltages can be added subsequently.
AXP datasheet is uploaded to wiki:
http://linux-sunxi.org/File:AXP818_datasheet_Revision1.0.pdf

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
4 years agosunxi: Add support for UART0 in PB pin group on A83T
vishnupatekar [Sat, 28 Nov 2015 17:07:20 +0000 (01:07 +0800)] 
sunxi: Add support for UART0 in PB pin group on A83T

On A83T, PB9,PB10 are UART0 pins.
On allwinner A83T Dev board(h8homlet), this uart0 serial connector
is exposed.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
4 years agosunxi: Add Machine Support for A83T SOC
vishnupatekar [Sat, 28 Nov 2015 17:07:19 +0000 (01:07 +0800)] 
sunxi: Add Machine Support for A83T SOC

Allwinner A83T is octa-core cortex-a7 SOC.
This enables support for A83T.

SMP is not yet supported.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
4 years agosunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs
Hans de Goede [Fri, 20 Nov 2015 18:29:49 +0000 (19:29 +0100)] 
sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs

According to the datasheets the max speed of AHB1 is 276 MHz, so
setting it to PLL6 / 3 which gives us 200MHz everywhere is fine,
and gives us a nice speed-up in certain workloads.

Suggested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Tested-by: Chen-Yu Tsai <wens@csie.org>
4 years agox86: Remove HAVE_ACPI_RESUME
Bin Meng [Thu, 26 Nov 2015 01:46:09 +0000 (17:46 -0800)] 
x86: Remove HAVE_ACPI_RESUME

These are currently dead codes. Until we have complete ACPI support,
we don't know if it works or not. Remove to avoid confusion.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
4 years agox86: Remove CPU_INTEL_SOCKET_RPGA989
Bin Meng [Thu, 26 Nov 2015 01:46:08 +0000 (17:46 -0800)] 
x86: Remove CPU_INTEL_SOCKET_RPGA989

This Kconfig option name indicates it has something to do with cpu
socket, however it is actually not the case. Remove it and move
options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
4 years agox86: Clean up ivybridge/chrome Kconfig options
Bin Meng [Thu, 26 Nov 2015 01:46:07 +0000 (17:46 -0800)] 
x86: Clean up ivybridge/chrome Kconfig options

There are some options which are never used, and also some options
which are selected by others but have never been a Kconfg option.
Clean these up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
4 years agox86: ivybridge: Remove NORTHBRIDGE_INTEL_SANDYBRIDGE
Bin Meng [Thu, 26 Nov 2015 01:46:06 +0000 (17:46 -0800)] 
x86: ivybridge: Remove NORTHBRIDGE_INTEL_SANDYBRIDGE

NORTHBRIDGE_INTEL_SANDYBRIDGE is for sandybridge, not ivybridge.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
4 years agocommon: Remove timer_init() call for x86
Bin Meng [Wed, 9 Dec 2015 01:31:40 +0000 (17:31 -0800)] 
common: Remove timer_init() call for x86

With driver model timer support, there should not be an explict
call to timer_init(). Remove this call for x86.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
4 years agox86: Move i8254_init() to x86_cpu_init_f()
Bin Meng [Wed, 9 Dec 2015 01:31:39 +0000 (17:31 -0800)] 
x86: Move i8254_init() to x86_cpu_init_f()

Right now i8254_init() is called from timer_init() in the tsc timer
driver. But actually i8254 and tsc are completely different things.
Since tsc timer has been converted to driver model, we should find
a new place that is appropriate for U-Boot to call i8254_init(),
which is now x86_cpu_init_f().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
4 years agox86: Fix PCI UART compatible string for crownbay and galileo
Bin Meng [Mon, 7 Dec 2015 13:28:13 +0000 (05:28 -0800)] 
x86: Fix PCI UART compatible string for crownbay and galileo

With recent ns16550 driver changes, we only changed the legacy UART
(at I/O port 0x3f8) compatible string, but forgot to change the PCI
UART compatible string. Now fix it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
4 years agofdt: Change OF_BAD_ADDR to FDT_ADDR_T_NONE
Bin Meng [Mon, 7 Dec 2015 09:39:47 +0000 (01:39 -0800)] 
fdt: Change OF_BAD_ADDR to FDT_ADDR_T_NONE

Currently OF_BAD_ADDR is always -1ULL. When using OF_BAD_ADDR as the
return value of dev_get_addr(), it creates potential size mismatch
as dev_get_addr() uses FDT_ADDR_T_NONE as the return value which can
be either -1U or -1ULL depending on CONFIG_PHYS_64BIT. Now we change
OF_BAD_ADDR to FDT_ADDR_T_NONE to avoid such case.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
4 years agoaxs10x: add support of generic EHCI USB 2.0 controller
Alexey Brodkin [Mon, 30 Nov 2015 17:53:25 +0000 (20:53 +0300)] 
axs10x: add support of generic EHCI USB 2.0 controller

This commit adds support of USB 2.0 storage media on AXS10x boards.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
4 years agoPrepare v2016.01-rc2
Tom Rini [Mon, 7 Dec 2015 19:23:45 +0000 (14:23 -0500)] 
Prepare v2016.01-rc2

Signed-off-by: Tom Rini <trini@konsulko.com>
4 years agomkimage: Fix warning from fix for generating multi and script images again
Marek Vasut [Mon, 7 Dec 2015 17:01:54 +0000 (18:01 +0100)] 
mkimage: Fix warning from fix for generating multi and script images again

Seems 6ae6e160 broke creating images in certain cases, there
are two problems with that patch.

First is that the expression "!x == 4 || !x == 6" is ambiguous.  The
intention here was "!(x == 4) || !(x == 6)" based on reading further in
the file, where this was borrowed from.  This however is interpreted by
gcc as "(!x) == 4 || (!x) == 6" and always false.  gcc-5.x will warn
about this case.

The second problem is that we do not want to test for the case of "(NOT x
is 4) OR (NOT x is 6)" but instead "(x is not equal to 4) AND (x is not
equal to 6)".  This is because in those two cases we already execute the
code question in another part of the file.  Rewrite the expression and
add parenthesis for clarity.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Philippe De Swert <philippedeswert@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
[trini: Re-word Marek's explanation]

4 years agoCONFIG_NEEDS_MANUAL_RELOC: Fix warnings when not set
Tom Rini [Mon, 7 Dec 2015 13:23:29 +0000 (08:23 -0500)] 
CONFIG_NEEDS_MANUAL_RELOC: Fix warnings when not set

Now that we may compile (but not link) code calling fixup_cmdtable when
this is not set, we need to always have the declaration available.  We
should also make sure that anyone calling the function includes
<command.h> as that's where the function declaration is.

Signed-off-by: Tom Rini <trini@konsulko.com>
4 years agoMerge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze
Tom Rini [Mon, 7 Dec 2015 13:13:02 +0000 (08:13 -0500)] 
Merge branch 'zynq' of git://denx.de/git/u-boot-microblaze

4 years agodm: core: Enable SPL_SIMPLE_BUS by default
Michal Simek [Tue, 1 Dec 2015 07:37:16 +0000 (08:37 +0100)] 
dm: core: Enable SPL_SIMPLE_BUS by default

This option is needed for all SoCs which have nodes on bus. Without
enabling this drivers are not found and probed.
Issue was found on Zynq MMC probe.
Enable this option by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>