From a4a43fcf9cca1ebd3d26f9a01b923b7393d69c54 Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Wed, 8 Jun 2016 08:04:03 +0300 Subject: [PATCH] arc/cache: Flush & invalidate all caches right before enabling IOC According to ARC HS databook it is required to flush and disable caches prior programming IOC registers. Otherwise ongoing coherent memory operations may not observe the coherency protocols as expected. But since in ARC HS v2.1 there's no way to disable SLC (AKA L2 cache) we're doing our best flushing and invalidating it. Signed-off-by: Alexey Brodkin --- arch/arc/lib/cache.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index a27499e027..b6ec83112c 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -209,6 +209,9 @@ void cache_init(void) read_decode_cache_bcr_arcv2(); if (ioc_exists) { + flush_dcache_all(); + invalidate_dcache_all(); + /* IO coherency base - 0x8z */ write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, 0x80000); /* IO coherency aperture size - 512Mb: 0x8z-0xAz */ -- 2.39.2