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Commit | Line | Data |
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f7075c3a SS |
1 | From: Sean Cross <xobs@kosagi.com> |
2 | Subject: [PATCH 1/3] ARM: imx: Add LVDS general-purpose clocks to i.MX6Q | |
3 | ||
4 | The i.MX6 has two general-purpose LVDS clocks that can be driven | |
5 | from a variety of sources. This patch adds a mux and a gate for | |
6 | both of these clocks. | |
7 | ||
8 | Signed-off-by: Sean Cross <xobs@kosagi.com> | |
9 | Signed-off-by: Shawn Guo <shawn.guo@linaro.org> | |
10 | --- | |
11 | .../devicetree/bindings/clock/imx6q-clock.txt | 4 ++++ | |
12 | arch/arm/mach-imx/clk-imx6q.c | 20 +++++++++++++++++++- | |
13 | 2 files changed, 23 insertions(+), 1 deletion(-) | |
14 | ||
15 | --- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt | |
16 | +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt | |
17 | @@ -208,6 +208,10 @@ clocks and IDs. | |
18 | pll4_post_div 193 | |
19 | pll5_post_div 194 | |
20 | pll5_video_div 195 | |
21 | + lvds1_sel 204 | |
22 | + lvds2_sel 205 | |
23 | + lvds1_gate 206 | |
24 | + lvds2_gate 207 | |
25 | ||
26 | Examples: | |
27 | ||
28 | --- a/arch/arm/mach-imx/clk-imx6q.c | |
29 | +++ b/arch/arm/mach-imx/clk-imx6q.c | |
30 | @@ -205,6 +205,11 @@ static const char *vpu_axi_sels[] = { "a | |
31 | static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", | |
32 | "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", | |
33 | "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", }; | |
34 | +static const char *lvds_sels[] = { | |
35 | + "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", | |
36 | + "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref", | |
37 | + "pcie_ref", "sata_ref", | |
38 | +}; | |
39 | ||
40 | enum mx6q_clks { | |
41 | dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, | |
42 | @@ -238,7 +243,8 @@ enum mx6q_clks { | |
43 | pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg, | |
44 | ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, | |
45 | sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, | |
46 | - usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, clk_max | |
47 | + usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, | |
48 | + lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, clk_max | |
49 | }; | |
50 | ||
51 | static struct clk *clk[clk_max]; | |
52 | @@ -340,6 +346,18 @@ int __init mx6q_clocks_init(void) | |
53 | base + 0xe0, 0, 2, 0, clk_enet_ref_table, | |
54 | &imx_ccm_lock); | |
55 | ||
56 | + clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); | |
57 | + clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); | |
58 | + | |
59 | + /* | |
60 | + * lvds1_gate and lvds2_gate are pseudo-gates. Both can be | |
61 | + * independently configured as clock inputs or outputs. We treat | |
62 | + * the "output_enable" bit as a gate, even though it's really just | |
63 | + * enabling clock output. | |
64 | + */ | |
65 | + clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "dummy", base + 0x160, 10); | |
66 | + clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "dummy", base + 0x160, 11); | |
67 | + | |
68 | /* name parent_name reg idx */ | |
69 | clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); | |
70 | clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); |