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Commit | Line | Data |
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00e5a55c BS |
1 | From: Suresh Siddha <suresh.b.siddha@intel.com> |
2 | Subject: x64, x2apic/intr-remap: support for x2apic physical mode support | |
3 | References: fate #303948 and fate #303984 | |
4 | Patch-Mainline: queued for .28 | |
5 | Commit-ID: 2d9579a124d746a3e0e0ba45e57d80800ee80807 | |
6 | ||
7 | Signed-off-by: Thomas Renninger <trenn@suse.de> | |
8 | ||
9 | x2apic Physical mode support. By default we will use x2apic cluster mode. | |
10 | x2apic physical mode can be selected using "x2apic_phys" boot parameter. | |
11 | ||
12 | Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> | |
13 | Cc: akpm@linux-foundation.org | |
14 | Cc: arjan@linux.intel.com | |
15 | Cc: andi@firstfloor.org | |
16 | Cc: ebiederm@xmission.com | |
17 | Cc: jbarnes@virtuousgeek.org | |
18 | Cc: steiner@sgi.com | |
19 | Signed-off-by: Ingo Molnar <mingo@elte.hu> | |
20 | ||
21 | --- | |
22 | Documentation/kernel-parameters.txt | 4 + | |
23 | arch/x86/kernel/Makefile | 1 | |
24 | arch/x86/kernel/genapic_64.c | 18 ++++- | |
25 | arch/x86/kernel/genx2apic_phys.c | 122 ++++++++++++++++++++++++++++++++++++ | |
26 | include/asm-x86/genapic_64.h | 1 | |
27 | 5 files changed, 143 insertions(+), 3 deletions(-) | |
28 | ||
29 | --- a/arch/x86/kernel/genapic_64.c | |
30 | +++ b/arch/x86/kernel/genapic_64.c | |
31 | @@ -30,6 +30,15 @@ DEFINE_PER_CPU(int, x2apic_extra_bits); | |
32 | ||
33 | struct genapic __read_mostly *genapic = &apic_flat; | |
34 | ||
35 | +static int x2apic_phys = 0; | |
36 | + | |
37 | +static int set_x2apic_phys_mode(char *arg) | |
38 | +{ | |
39 | + x2apic_phys = 1; | |
40 | + return 0; | |
41 | +} | |
42 | +early_param("x2apic_phys", set_x2apic_phys_mode); | |
43 | + | |
44 | static enum uv_system_type uv_system_type; | |
45 | ||
46 | /* | |
47 | @@ -39,9 +48,12 @@ void __init setup_apic_routing(void) | |
48 | { | |
49 | if (uv_system_type == UV_NON_UNIQUE_APIC) | |
50 | genapic = &apic_x2apic_uv_x; | |
51 | - else if (cpu_has_x2apic && intr_remapping_enabled) | |
52 | - genapic = &apic_x2apic_cluster; | |
53 | - else | |
54 | + else if (cpu_has_x2apic && intr_remapping_enabled) { | |
55 | + if (x2apic_phys) | |
56 | + genapic = &apic_x2apic_phys; | |
57 | + else | |
58 | + genapic = &apic_x2apic_cluster; | |
59 | + } else | |
60 | #ifdef CONFIG_ACPI | |
61 | /* | |
62 | * Quirk: some x86_64 machines can only use physical APIC mode | |
63 | --- /dev/null | |
64 | +++ b/arch/x86/kernel/genx2apic_phys.c | |
65 | @@ -0,0 +1,122 @@ | |
66 | +#include <linux/threads.h> | |
67 | +#include <linux/cpumask.h> | |
68 | +#include <linux/string.h> | |
69 | +#include <linux/kernel.h> | |
70 | +#include <linux/ctype.h> | |
71 | +#include <linux/init.h> | |
72 | +#include <asm/smp.h> | |
73 | +#include <asm/ipi.h> | |
74 | +#include <asm/genapic.h> | |
75 | + | |
76 | + | |
77 | +/* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */ | |
78 | + | |
79 | +static cpumask_t x2apic_target_cpus(void) | |
80 | +{ | |
81 | + return cpumask_of_cpu(0); | |
82 | +} | |
83 | + | |
84 | +static cpumask_t x2apic_vector_allocation_domain(int cpu) | |
85 | +{ | |
86 | + cpumask_t domain = CPU_MASK_NONE; | |
87 | + cpu_set(cpu, domain); | |
88 | + return domain; | |
89 | +} | |
90 | + | |
91 | +static void __x2apic_send_IPI_dest(unsigned int apicid, int vector, | |
92 | + unsigned int dest) | |
93 | +{ | |
94 | + unsigned long cfg; | |
95 | + | |
96 | + cfg = __prepare_ICR(0, vector, dest); | |
97 | + | |
98 | + /* | |
99 | + * send the IPI. | |
100 | + */ | |
101 | + x2apic_icr_write(cfg, apicid); | |
102 | +} | |
103 | + | |
104 | +static void x2apic_send_IPI_mask(cpumask_t mask, int vector) | |
105 | +{ | |
106 | + unsigned long flags; | |
107 | + unsigned long query_cpu; | |
108 | + | |
109 | + local_irq_save(flags); | |
110 | + for_each_cpu_mask(query_cpu, mask) { | |
111 | + __x2apic_send_IPI_dest(per_cpu(x86_cpu_to_apicid, query_cpu), | |
112 | + vector, APIC_DEST_PHYSICAL); | |
113 | + } | |
114 | + local_irq_restore(flags); | |
115 | +} | |
116 | + | |
117 | +static void x2apic_send_IPI_allbutself(int vector) | |
118 | +{ | |
119 | + cpumask_t mask = cpu_online_map; | |
120 | + | |
121 | + cpu_clear(smp_processor_id(), mask); | |
122 | + | |
123 | + if (!cpus_empty(mask)) | |
124 | + x2apic_send_IPI_mask(mask, vector); | |
125 | +} | |
126 | + | |
127 | +static void x2apic_send_IPI_all(int vector) | |
128 | +{ | |
129 | + x2apic_send_IPI_mask(cpu_online_map, vector); | |
130 | +} | |
131 | + | |
132 | +static int x2apic_apic_id_registered(void) | |
133 | +{ | |
134 | + return 1; | |
135 | +} | |
136 | + | |
137 | +static unsigned int x2apic_cpu_mask_to_apicid(cpumask_t cpumask) | |
138 | +{ | |
139 | + int cpu; | |
140 | + | |
141 | + /* | |
142 | + * We're using fixed IRQ delivery, can only return one phys APIC ID. | |
143 | + * May as well be the first. | |
144 | + */ | |
145 | + cpu = first_cpu(cpumask); | |
146 | + if ((unsigned)cpu < NR_CPUS) | |
147 | + return per_cpu(x86_cpu_to_apicid, cpu); | |
148 | + else | |
149 | + return BAD_APICID; | |
150 | +} | |
151 | + | |
152 | +static unsigned int x2apic_read_id(void) | |
153 | +{ | |
154 | + return apic_read(APIC_ID); | |
155 | +} | |
156 | + | |
157 | +static unsigned int phys_pkg_id(int index_msb) | |
158 | +{ | |
159 | + return x2apic_read_id() >> index_msb; | |
160 | +} | |
161 | + | |
162 | +void x2apic_send_IPI_self(int vector) | |
163 | +{ | |
164 | + apic_write(APIC_SELF_IPI, vector); | |
165 | +} | |
166 | + | |
167 | +void init_x2apic_ldr(void) | |
168 | +{ | |
169 | + return; | |
170 | +} | |
171 | + | |
172 | +struct genapic apic_x2apic_phys = { | |
173 | + .name = "physical x2apic", | |
174 | + .int_delivery_mode = dest_Fixed, | |
175 | + .int_dest_mode = (APIC_DEST_PHYSICAL != 0), | |
176 | + .target_cpus = x2apic_target_cpus, | |
177 | + .vector_allocation_domain = x2apic_vector_allocation_domain, | |
178 | + .apic_id_registered = x2apic_apic_id_registered, | |
179 | + .init_apic_ldr = init_x2apic_ldr, | |
180 | + .send_IPI_all = x2apic_send_IPI_all, | |
181 | + .send_IPI_allbutself = x2apic_send_IPI_allbutself, | |
182 | + .send_IPI_mask = x2apic_send_IPI_mask, | |
183 | + .send_IPI_self = x2apic_send_IPI_self, | |
184 | + .cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid, | |
185 | + .phys_pkg_id = phys_pkg_id, | |
186 | + .read_apic_id = x2apic_read_id, | |
187 | +}; | |
188 | --- a/arch/x86/kernel/Makefile | |
189 | +++ b/arch/x86/kernel/Makefile | |
190 | @@ -104,6 +104,7 @@ obj-$(CONFIG_OLPC) += olpc.o | |
191 | ifeq ($(CONFIG_X86_64),y) | |
192 | obj-y += genapic_64.o genapic_flat_64.o genx2apic_uv_x.o tlb_uv.o | |
193 | obj-y += genx2apic_cluster.o | |
194 | + obj-y += genx2apic_phys.o | |
195 | obj-y += bios_uv.o | |
196 | obj-$(CONFIG_X86_PM_TIMER) += pmtimer_64.o | |
197 | obj-$(CONFIG_AUDIT) += audit_64.o | |
198 | --- a/Documentation/kernel-parameters.txt | |
199 | +++ b/Documentation/kernel-parameters.txt | |
200 | @@ -1430,6 +1430,10 @@ and is between 256 and 4096 characters. | |
201 | ||
202 | nox2apic [X86-64,APIC] Do not enable x2APIC mode. | |
203 | ||
204 | + x2apic_phys [X86-64,APIC] Use x2apic physical mode instead of | |
205 | + default x2apic cluster mode on platforms | |
206 | + supporting x2apic. | |
207 | + | |
208 | noltlbs [PPC] Do not use large page/tlb entries for kernel | |
209 | lowmem mapping on PPC40x. | |
210 | ||
211 | --- a/include/asm-x86/genapic_64.h | |
212 | +++ b/include/asm-x86/genapic_64.h | |
213 | @@ -36,6 +36,7 @@ extern struct genapic *genapic; | |
214 | extern struct genapic apic_flat; | |
215 | extern struct genapic apic_physflat; | |
216 | extern struct genapic apic_x2apic_cluster; | |
217 | +extern struct genapic apic_x2apic_phys; | |
218 | extern int acpi_madt_oem_check(char *, char *); | |
219 | ||
220 | extern void apic_send_IPI_self(int vector); |