projects / people / pmueller / ipfire-2.x.git / blame
| Commit | Line | Data |
|---|---|---|
| 00e5a55c BS |
1 | From: Stefan Assmann <sassmann@suse.de> |
| 2 | Subject: pci: add quirk to disable boot interrupt generation on intel 6300ESB | |
| 3 | ||
| 4 | Add a quirk to disable legacy boot interrupt generation on intel devices | |
| 5 | that support disabling it. | |
| 6 | ||
| 7 | This patch benefited from discussions with Alexander Graf, Torsten Duwe, | |
| 8 | Ihno Krumreich, Daniel Gollub, Hannes Reinecke. The conclusions we drew | |
| 9 | and the patch itself are the authors' responsibility alone. | |
| 10 | ||
| 11 | Signed-off-by: Stefan Assmann <sassmann@suse.de> | |
| 12 | Signed-off-by: Olaf Dabrunz <od@suse.de> | |
| 13 | Signed-off-by: Ingo Molnar <mingo@elte.hu> | |
| 14 | --- | |
| 15 | drivers/pci/quirks.c | 30 ++++++++++++++++++++++++++++++ | |
| 16 | 1 file changed, 30 insertions(+) | |
| 17 | ||
| 18 | --- a/drivers/pci/quirks.c | |
| 19 | +++ b/drivers/pci/quirks.c | |
| 20 | @@ -1423,6 +1423,36 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN | |
| 21 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); | |
| 22 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); | |
| 23 | ||
| 24 | +#ifdef CONFIG_X86_IO_APIC | |
| 25 | +/* | |
| 26 | + * On some chipsets we can disable the generation of legacy INTx boot | |
| 27 | + * interrupts. | |
| 28 | + */ | |
| 29 | + | |
| 30 | +/* | |
| 31 | + * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no | |
| 32 | + * 300641-004US, section 5.7.3. | |
| 33 | + */ | |
| 34 | +#define INTEL_6300_IOAPIC_ABAR 0x40 | |
| 35 | +#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) | |
| 36 | + | |
| 37 | +static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) | |
| 38 | +{ | |
| 39 | + u16 pci_config_word; | |
| 40 | + | |
| 41 | + if (noioapicquirk) | |
| 42 | + return; | |
| 43 | + | |
| 44 | + pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word); | |
| 45 | + pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; | |
| 46 | + pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); | |
| 47 | + | |
| 48 | + printk(KERN_INFO "disabled boot interrupt on device 0x%04x:0x%04x\n", | |
| 49 | + dev->vendor, dev->device); | |
| 50 | +} | |
| 51 | +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); | |
| 52 | +#endif /* CONFIG_X86_IO_APIC */ | |
| 53 | + | |
| 54 | /* | |
| 55 | * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size | |
| 56 | * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. |