]>
Commit | Line | Data |
---|---|---|
00e5a55c BS |
1 | Commit-Id: f162a5d1b326d54b0be7e3100f69763d8a707721 |
2 | From: Francois Romieu <romieu@fr.zoreil.com> | |
3 | Date: Sun, 1 Jun 2008 22:37:49 +0200 | |
4 | Acked-by: Karsten Keil <kkeil@novell.com> | |
5 | Reference: bnc#448168 | |
6 | Subject: [PATCH] r8169: add 8168/8101 registers description | |
7 | ||
8 | Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> | |
9 | Cc: Edward Hsu <edward_hsu@realtek.com.tw> | |
10 | ||
11 | Index: linux-2.6.27/drivers/net/r8169.c | |
12 | =================================================================== | |
13 | --- linux-2.6.27.orig/drivers/net/r8169.c | |
14 | +++ linux-2.6.27/drivers/net/r8169.c | |
15 | @@ -197,9 +197,6 @@ enum rtl_registers { | |
16 | Config5 = 0x56, | |
17 | MultiIntr = 0x5c, | |
18 | PHYAR = 0x60, | |
19 | - TBICSR = 0x64, | |
20 | - TBI_ANAR = 0x68, | |
21 | - TBI_LPAR = 0x6a, | |
22 | PHYstatus = 0x6c, | |
23 | RxMaxSize = 0xda, | |
24 | CPlusCmd = 0xe0, | |
25 | @@ -213,6 +210,32 @@ enum rtl_registers { | |
26 | FuncForceEvent = 0xfc, | |
27 | }; | |
28 | ||
29 | +enum rtl8110_registers { | |
30 | + TBICSR = 0x64, | |
31 | + TBI_ANAR = 0x68, | |
32 | + TBI_LPAR = 0x6a, | |
33 | +}; | |
34 | + | |
35 | +enum rtl8168_8101_registers { | |
36 | + CSIDR = 0x64, | |
37 | + CSIAR = 0x68, | |
38 | +#define CSIAR_FLAG 0x80000000 | |
39 | +#define CSIAR_WRITE_CMD 0x80000000 | |
40 | +#define CSIAR_BYTE_ENABLE 0x0f | |
41 | +#define CSIAR_BYTE_ENABLE_SHIFT 12 | |
42 | +#define CSIAR_ADDR_MASK 0x0fff | |
43 | + | |
44 | + EPHYAR = 0x80, | |
45 | +#define EPHYAR_FLAG 0x80000000 | |
46 | +#define EPHYAR_WRITE_CMD 0x80000000 | |
47 | +#define EPHYAR_REG_MASK 0x1f | |
48 | +#define EPHYAR_REG_SHIFT 16 | |
49 | +#define EPHYAR_DATA_MASK 0xffff | |
50 | + DBG_REG = 0xd1, | |
51 | +#define FIX_NAK_1 (1 << 4) | |
52 | +#define FIX_NAK_2 (1 << 3) | |
53 | +}; | |
54 | + | |
55 | enum rtl_register_content { | |
56 | /* InterruptStatusBits */ | |
57 | SYSErr = 0x8000, | |
58 | @@ -266,7 +289,13 @@ enum rtl_register_content { | |
59 | TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ | |
60 | ||
61 | /* Config1 register p.24 */ | |
62 | + LEDS1 = (1 << 7), | |
63 | + LEDS0 = (1 << 6), | |
64 | MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */ | |
65 | + Speed_down = (1 << 4), | |
66 | + MEMMAP = (1 << 3), | |
67 | + IOMAP = (1 << 2), | |
68 | + VPD = (1 << 1), | |
69 | PMEnable = (1 << 0), /* Power Management Enable */ | |
70 | ||
71 | /* Config2 register p. 25 */ | |
72 | @@ -276,6 +305,7 @@ enum rtl_register_content { | |
73 | /* Config3 register p.25 */ | |
74 | MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ | |
75 | LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ | |
76 | + Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ | |
77 | ||
78 | /* Config5 register p.27 */ | |
79 | BWF = (1 << 6), /* Accept Broadcast wakeup frame */ | |
80 | @@ -293,7 +323,16 @@ enum rtl_register_content { | |
81 | TBINwComplete = 0x01000000, | |
82 | ||
83 | /* CPlusCmd p.31 */ | |
84 | - PktCntrDisable = (1 << 7), // 8168 | |
85 | + EnableBist = (1 << 15), // 8168 8101 | |
86 | + Mac_dbgo_oe = (1 << 14), // 8168 8101 | |
87 | + Normal_mode = (1 << 13), // unused | |
88 | + Force_half_dup = (1 << 12), // 8168 8101 | |
89 | + Force_rxflow_en = (1 << 11), // 8168 8101 | |
90 | + Force_txflow_en = (1 << 10), // 8168 8101 | |
91 | + Cxpl_dbg_sel = (1 << 9), // 8168 8101 | |
92 | + ASF = (1 << 8), // 8168 8101 | |
93 | + PktCntrDisable = (1 << 7), // 8168 8101 | |
94 | + Mac_dbgo_sel = 0x001c, // 8168 | |
95 | RxVlan = (1 << 6), | |
96 | RxChkSum = (1 << 5), | |
97 | PCIDAC = (1 << 4), |