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Fix oinkmaster patch.
[people/pmueller/ipfire-2.x.git] / src / patches / suse-2.6.27.39 / patches.drivers / 0014-Staging-add-w35und-wifi-driver.patch
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BS		 1From 66101de10957e07a6fd0365d5af9adf650246d14 Mon Sep 17 00:00:00 2001
2From: Pavel Machek <pavel@suse.cz>
3Date: Wed, 1 Oct 2008 14:36:56 +0200
4Subject: [PATCH 14/23] Staging: add w35und wifi driver
5Patch-mainline: 2.6.28
6
7This is driver for w35und usb wifi -- also in kohjinsha
8subnotebook. It should work well enough to associate and ping, but it
9obviously needs to be rewritten two more times...
10
11OTOH worst horrors (like embedded wifi stack) should have been fixed
12already...
13
14Signed-off-by: Pavel Machek <pavel@suse.cz>
15Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
16---
17 drivers/staging/Kconfig | 2 +
18 drivers/staging/Makefile | 1 +
19 drivers/staging/winbond/Kconfig | 7 +
20 drivers/staging/winbond/Makefile | 18 +
21 drivers/staging/winbond/README | 10 +
22 drivers/staging/winbond/adapter.h | 23 +
23 drivers/staging/winbond/bss_f.h | 59 +
24 drivers/staging/winbond/bssdscpt.h | 156 ++
25 drivers/staging/winbond/ds_tkip.h | 33 +
26 drivers/staging/winbond/gl_80211.h | 125 ++
27 drivers/staging/winbond/ioctls.h | 678 ++++++++
28 drivers/staging/winbond/linux/common.h | 143 ++
29 drivers/staging/winbond/linux/sysdef.h | 73 +
30 drivers/staging/winbond/linux/wb35reg.c | 747 ++++++++
31 drivers/staging/winbond/linux/wb35reg_f.h | 56 +
32 drivers/staging/winbond/linux/wb35reg_s.h | 170 ++
33 drivers/staging/winbond/linux/wb35rx.c | 337 ++++
34 drivers/staging/winbond/linux/wb35rx_f.h | 17 +
35 drivers/staging/winbond/linux/wb35rx_s.h | 48 +
36 drivers/staging/winbond/linux/wb35tx.c | 313 ++++
37 drivers/staging/winbond/linux/wb35tx_f.h | 20 +
38 drivers/staging/winbond/linux/wb35tx_s.h | 47 +
39 drivers/staging/winbond/linux/wbusb.c | 404 +++++
40 drivers/staging/winbond/linux/wbusb_f.h | 34 +
41 drivers/staging/winbond/linux/wbusb_s.h | 42 +
42 drivers/staging/winbond/localpara.h | 275 +++
43 drivers/staging/winbond/mac_structures.h | 670 +++++++
44 drivers/staging/winbond/mds.c | 630 +++++++
45 drivers/staging/winbond/mds_f.h | 33 +
46 drivers/staging/winbond/mds_s.h | 183 ++
47 drivers/staging/winbond/mlme_mib.h | 84 +
48 drivers/staging/winbond/mlme_s.h | 195 +++
49 drivers/staging/winbond/mlmetxrx.c | 150 ++
50 drivers/staging/winbond/mlmetxrx_f.h | 52 +
51 drivers/staging/winbond/mto.c | 1229 +++++++++++++
52 drivers/staging/winbond/mto.h | 265 +++
53 drivers/staging/winbond/mto_f.h | 7 +
54 drivers/staging/winbond/os_common.h | 2 +
55 drivers/staging/winbond/phy_calibration.c | 1759 +++++++++++++++++++
56 drivers/staging/winbond/phy_calibration.h | 101 ++
57 drivers/staging/winbond/reg.c | 2683 +++++++++++++++++++++++++++++
58 drivers/staging/winbond/rxisr.c | 30 +
59 drivers/staging/winbond/scan_s.h | 115 ++
60 drivers/staging/winbond/sme_api.c | 13 +
61 drivers/staging/winbond/sme_api.h | 265 +++
62 drivers/staging/winbond/sme_s.h | 228 +++
63 drivers/staging/winbond/wb35_ver.h | 30 +
64 drivers/staging/winbond/wbhal.c | 878 ++++++++++
65 drivers/staging/winbond/wbhal_f.h | 122 ++
66 drivers/staging/winbond/wbhal_s.h | 615 +++++++
67 drivers/staging/winbond/wblinux.c | 277 +++
68 drivers/staging/winbond/wblinux_f.h | 23 +
69 drivers/staging/winbond/wblinux_s.h | 45 +
70 53 files changed, 14522 insertions(+), 0 deletions(-)
71 create mode 100644 drivers/staging/winbond/Kconfig
72 create mode 100644 drivers/staging/winbond/Makefile
73 create mode 100644 drivers/staging/winbond/README
74 create mode 100644 drivers/staging/winbond/adapter.h
75 create mode 100644 drivers/staging/winbond/bss_f.h
76 create mode 100644 drivers/staging/winbond/bssdscpt.h
77 create mode 100644 drivers/staging/winbond/ds_tkip.h
78 create mode 100644 drivers/staging/winbond/gl_80211.h
79 create mode 100644 drivers/staging/winbond/ioctls.h
80 create mode 100644 drivers/staging/winbond/linux/common.h
81 create mode 100644 drivers/staging/winbond/linux/sysdef.h
82 create mode 100644 drivers/staging/winbond/linux/wb35reg.c
83 create mode 100644 drivers/staging/winbond/linux/wb35reg_f.h
84 create mode 100644 drivers/staging/winbond/linux/wb35reg_s.h
85 create mode 100644 drivers/staging/winbond/linux/wb35rx.c
86 create mode 100644 drivers/staging/winbond/linux/wb35rx_f.h
87 create mode 100644 drivers/staging/winbond/linux/wb35rx_s.h
88 create mode 100644 drivers/staging/winbond/linux/wb35tx.c
89 create mode 100644 drivers/staging/winbond/linux/wb35tx_f.h
90 create mode 100644 drivers/staging/winbond/linux/wb35tx_s.h
91 create mode 100644 drivers/staging/winbond/linux/wbusb.c
92 create mode 100644 drivers/staging/winbond/linux/wbusb_f.h
93 create mode 100644 drivers/staging/winbond/linux/wbusb_s.h
94 create mode 100644 drivers/staging/winbond/localpara.h
95 create mode 100644 drivers/staging/winbond/mac_structures.h
96 create mode 100644 drivers/staging/winbond/mds.c
97 create mode 100644 drivers/staging/winbond/mds_f.h
98 create mode 100644 drivers/staging/winbond/mds_s.h
99 create mode 100644 drivers/staging/winbond/mlme_mib.h
100 create mode 100644 drivers/staging/winbond/mlme_s.h
101 create mode 100644 drivers/staging/winbond/mlmetxrx.c
102 create mode 100644 drivers/staging/winbond/mlmetxrx_f.h
103 create mode 100644 drivers/staging/winbond/mto.c
104 create mode 100644 drivers/staging/winbond/mto.h
105 create mode 100644 drivers/staging/winbond/mto_f.h
106 create mode 100644 drivers/staging/winbond/os_common.h
107 create mode 100644 drivers/staging/winbond/phy_calibration.c
108 create mode 100644 drivers/staging/winbond/phy_calibration.h
109 create mode 100644 drivers/staging/winbond/reg.c
110 create mode 100644 drivers/staging/winbond/rxisr.c
111 create mode 100644 drivers/staging/winbond/scan_s.h
112 create mode 100644 drivers/staging/winbond/sme_api.c
113 create mode 100644 drivers/staging/winbond/sme_api.h
114 create mode 100644 drivers/staging/winbond/sme_s.h
115 create mode 100644 drivers/staging/winbond/wb35_ver.h
116 create mode 100644 drivers/staging/winbond/wbhal.c
117 create mode 100644 drivers/staging/winbond/wbhal_f.h
118 create mode 100644 drivers/staging/winbond/wbhal_s.h
119 create mode 100644 drivers/staging/winbond/wblinux.c
120 create mode 100644 drivers/staging/winbond/wblinux_f.h
121 create mode 100644 drivers/staging/winbond/wblinux_s.h
122
123diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
124index 4dbf795..fdbdf84 100644
125--- a/drivers/staging/Kconfig
126+++ b/drivers/staging/Kconfig
127@@ -35,4 +35,6 @@ source "drivers/staging/go7007/Kconfig"
128
129 source "drivers/staging/usbip/Kconfig"
130
131+source "drivers/staging/winbond/Kconfig"
132+
133 endif # STAGING
134diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
135index be42c0d..9b576c9 100644
136--- a/drivers/staging/Makefile
137+++ b/drivers/staging/Makefile
138@@ -6,3 +6,4 @@ obj-$(CONFIG_SXG) += sxg/
139 obj-$(CONFIG_ME4000) += me4000/
140 obj-$(CONFIG_VIDEO_GO7007) += go7007/
141 obj-$(CONFIG_USB_IP_COMMON) += usbip/
142+obj-$(CONFIG_W35UND) += winbond/
143diff --git a/drivers/staging/winbond/Kconfig b/drivers/staging/winbond/Kconfig
144new file mode 100644
145index 0000000..10d72be
146--- /dev/null
147+++ b/drivers/staging/winbond/Kconfig
148@@ -0,0 +1,7 @@
149+config W35UND
150+ tristate "Winbond driver"
151+ depends on MAC80211 && WLAN_80211 && EXPERIMENTAL && !4KSTACKS
152+ default n
153+ ---help---
154+ This is highly experimental driver for winbond wifi card on some Kohjinsha notebooks
155+ Check http://code.google.com/p/winbondport/ for new version
156diff --git a/drivers/staging/winbond/Makefile b/drivers/staging/winbond/Makefile
157new file mode 100644
158index 0000000..29c98bf
159--- /dev/null
160+++ b/drivers/staging/winbond/Makefile
161@@ -0,0 +1,18 @@
162+ DRIVER_DIR=./linux
163+
164+w35und-objs := $(DRIVER_DIR)/wbusb.o $(DRIVER_DIR)/wb35reg.o $(DRIVER_DIR)/wb35rx.o $(DRIVER_DIR)/wb35tx.o \
165+ mds.o \
166+ mlmetxrx.o \
167+ mto.o \
168+ phy_calibration.o \
169+ reg.o \
170+ rxisr.o \
171+ sme_api.o \
172+ wbhal.o \
173+ wblinux.o \
174+
175+
176+obj-$(CONFIG_W35UND) += w35und.o
177+
178+
179+
180diff --git a/drivers/staging/winbond/README b/drivers/staging/winbond/README
181new file mode 100644
182index 0000000..707b6b3
183--- /dev/null
184+++ b/drivers/staging/winbond/README
185@@ -0,0 +1,10 @@
186+TODO:
187+ - sparse cleanups
188+ - checkpatch cleanups
189+ - kerneldoc cleanups
190+ - remove typedefs
191+ - remove unused ioctls
192+ - use cfg80211 for regulatory stuff
193+
194+Please send patches to Greg Kroah-Hartman <greg@kroah.com> and
195+Pavel Machek <pavel@suse.cz>
196diff --git a/drivers/staging/winbond/adapter.h b/drivers/staging/winbond/adapter.h
197new file mode 100644
198index 0000000..609701d
199--- /dev/null
200+++ b/drivers/staging/winbond/adapter.h
201@@ -0,0 +1,23 @@
202+//
203+// ADAPTER.H -
204+// Windows NDIS global variable 'Adapter' typedef
205+//
206+#define MAX_ANSI_STRING 40
207+typedef struct WB32_ADAPTER
208+{
209+ u32 AdapterIndex; // 20060703.4 Add for using pAdapterContext global Adapter point
210+
211+ WB_LOCALDESCRIPT sLocalPara; // Myself connected parameters
212+ PWB_BSSDESCRIPTION asBSSDescriptElement;
213+
214+ MLME_FRAME sMlmeFrame; // connect to peerSTA parameters
215+
216+ MTO_PARAMETERS sMtoPara; // MTO_struct ...
217+ hw_data_t sHwData; //For HAL
218+ MDS Mds;
219+
220+ WBLINUX WbLinux;
221+ struct iw_statistics iw_stats;
222+
223+ u8 LinkName[MAX_ANSI_STRING];
224+} WB32_ADAPTER, ADAPTER, *PWB32_ADAPTER, *PADAPTER;
225diff --git a/drivers/staging/winbond/bss_f.h b/drivers/staging/winbond/bss_f.h
226new file mode 100644
227index 0000000..c957bc9
228--- /dev/null
229+++ b/drivers/staging/winbond/bss_f.h
230@@ -0,0 +1,59 @@
231+//
232+// BSS descriptor DataBase management global function
233+//
234+
235+void vBSSdescriptionInit(PWB32_ADAPTER Adapter);
236+void vBSSfoundList(PWB32_ADAPTER Adapter);
237+u8 boChanFilter(PWB32_ADAPTER Adapter, u8 ChanNo);
238+u16 wBSSallocateEntry(PWB32_ADAPTER Adapter);
239+u16 wBSSGetEntry(PWB32_ADAPTER Adapter);
240+void vSimpleHouseKeeping(PWB32_ADAPTER Adapter);
241+u16 wBSShouseKeeping(PWB32_ADAPTER Adapter);
242+void ClearBSSdescpt(PWB32_ADAPTER Adapter, u16 i);
243+u16 wBSSfindBssID(PWB32_ADAPTER Adapter, u8 *pbBssid);
244+u16 wBSSfindDedicateCandidate(PWB32_ADAPTER Adapter, struct SSID_Element *psSsid, u8 *pbBssid);
245+u16 wBSSfindMACaddr(PWB32_ADAPTER Adapter, u8 *pbMacAddr);
246+u16 wBSSsearchMACaddr(PWB32_ADAPTER Adapter, u8 *pbMacAddr, u8 band);
247+u16 wBSSaddScanData(PWB32_ADAPTER, u16, psRXDATA);
248+u16 wBSSUpdateScanData(PWB32_ADAPTER Adapter, u16 wBssIdx, psRXDATA psRcvData);
249+u16 wBSScreateIBSSdata(PWB32_ADAPTER Adapter, PWB_BSSDESCRIPTION psDesData);
250+void DesiredRate2BSSdescriptor(PWB32_ADAPTER Adapter, PWB_BSSDESCRIPTION psDesData,
251+ u8 *pBasicRateSet, u8 BasicRateCount,
252+ u8 *pOperationRateSet, u8 OperationRateCount);
253+void DesiredRate2InfoElement(PWB32_ADAPTER Adapter, u8 *addr, u16 *iFildOffset,
254+ u8 *pBasicRateSet, u8 BasicRateCount,
255+ u8 *pOperationRateSet, u8 OperationRateCount);
256+void BSSAddIBSSdata(PWB32_ADAPTER Adapter, PWB_BSSDESCRIPTION psDesData);
257+unsigned char boCmpMacAddr( PUCHAR, PUCHAR );
258+unsigned char boCmpSSID(struct SSID_Element *psSSID1, struct SSID_Element *psSSID2);
259+u16 wBSSfindSSID(PWB32_ADAPTER Adapter, struct SSID_Element *psSsid);
260+u16 wRoamingQuery(PWB32_ADAPTER Adapter);
261+void vRateToBitmap(PWB32_ADAPTER Adapter, u16 index);
262+u8 bRateToBitmapIndex(PWB32_ADAPTER Adapter, u8 bRate);
263+u8 bBitmapToRate(u8 i);
264+unsigned char boIsERPsta(PWB32_ADAPTER Adapter, u16 i);
265+unsigned char boCheckConnect(PWB32_ADAPTER Adapter);
266+unsigned char boCheckSignal(PWB32_ADAPTER Adapter);
267+void AddIBSSIe(PWB32_ADAPTER Adapter,PWB_BSSDESCRIPTION psDesData );//added by ws for WPA_None06/01/04
268+void BssScanUpToDate(PWB32_ADAPTER Adapter);
269+void BssUpToDate(PWB32_ADAPTER Adapter);
270+void RateSort(u8 *RateArray, u8 num, u8 mode);
271+void RateReSortForSRate(PWB32_ADAPTER Adapter, u8 *RateArray, u8 num);
272+void Assemble_IE(PWB32_ADAPTER Adapter, u16 wBssIdx);
273+void SetMaxTxRate(PWB32_ADAPTER Adapter);
274+
275+void CreateWpaIE(PWB32_ADAPTER Adapter, u16* iFildOffset, PUCHAR msg, struct Management_Frame* msgHeader,
276+ struct Association_Request_Frame_Body* msgBody, u16 iMSindex); //added by WS 05/14/05
277+
278+#ifdef _WPA2_
279+void CreateRsnIE(PWB32_ADAPTER Adapter, u16* iFildOffset, PUCHAR msg, struct Management_Frame* msgHeader,
280+ struct Association_Request_Frame_Body* msgBody, u16 iMSindex);//added by WS 05/14/05
281+
282+u16 SearchPmkid(PWB32_ADAPTER Adapter, struct Management_Frame* msgHeader,
283+ struct PMKID_Information_Element * AssoReq_PMKID );
284+#endif
285+
286+
287+
288+
289+
290diff --git a/drivers/staging/winbond/bssdscpt.h b/drivers/staging/winbond/bssdscpt.h
291new file mode 100644
292index 0000000..97150a2
293--- /dev/null
294+++ b/drivers/staging/winbond/bssdscpt.h
295@@ -0,0 +1,156 @@
296+//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
297+// bssdscpt.c
298+// BSS descriptor data base
299+// history :
300+//
301+// Description:
302+// BSS descriptor data base will store the information of the stations at the
303+// surrounding environment. The first entry( psBSS(0) ) will not be used and the
304+// second one( psBSS(1) ) will be used for the broadcast address.
305+//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
306+
307+//#define MAX_ACC_RSSI_COUNT 10
308+#define MAX_ACC_RSSI_COUNT 6
309+
310+///////////////////////////////////////////////////////////////////////////
311+//
312+// BSS Description set Element , to store scan received Beacon information
313+//
314+// Our's differs slightly from the specs. The specify a PHY_Parameter_Set.
315+// Since we're only doing a DS design right now, we just have a DS structure.
316+//////////////////////////////////////////////////////////////////////////////
317+typedef struct BSSDescriptionElement
318+{
319+ u32 SlotValid;
320+ u32 PowerSaveMode;
321+ RXLAYER1 RxLayer1;
322+
323+ u8 abPeerAddress[ MAC_ADDR_LENGTH + 2 ]; // peer MAC Address associated with this session. 6-OCTET value
324+ u32 dwBgScanStamp; // BgScan Sequence Counter stamp, record psROAM->dwScanCounter.
325+
326+ u16 Beacon_Period;
327+ u16 wATIM_Window;
328+
329+ u8 abBssID[ MAC_ADDR_LENGTH + 2 ]; // 6B
330+
331+ u8 bBssType;
332+ u8 DTIM_Period; // 1 octet usually from TIM element, if present
333+ u8 boInTimerHandler;
334+ u8 boERP; // analysis ERP or (extended) supported rate element
335+
336+ u8 Timestamp[8];
337+ u8 BasicRate[32];
338+ u8 OperationalRate[32];
339+ u32 dwBasicRateBitmap; //bit map, retrieve from SupportedRateSet
340+ u32 dwOperationalRateBitmap; //bit map, retrieve from SupportedRateSet and
341+ // ExtendedSupportedRateSet
342+ // For RSSI calculating
343+ u32 HalRssi[MAX_ACC_RSSI_COUNT]; // Encode. It must use MACRO of HAL to get the LNA and AGC data
344+ u32 HalRssiIndex;
345+
346+ ////From beacon/probe response
347+ struct SSID_Element SSID; // 34B
348+ u8 reserved_1[ 2 ];
349+
350+ struct Capability_Information_Element CapabilityInformation; // 2B
351+ u8 reserved_2[ 2 ];
352+
353+ struct CF_Parameter_Set_Element CF_Parameter_Set; // 8B
354+ struct IBSS_Parameter_Set_Element IBSS_Parameter_Set; // 4B
355+ struct TIM_Element TIM_Element_Set; // 256B
356+
357+ struct DS_Parameter_Set_Element DS_Parameter_Set; // 3B
358+ u8 reserved_3;
359+
360+ struct ERP_Information_Element ERP_Information_Set; // 3B
361+ u8 reserved_4;
362+
363+ struct Supported_Rates_Element SupportedRateSet; // 10B
364+ u8 reserved_5[2];
365+
366+ struct Extended_Supported_Rates_Element ExtendedSupportedRateSet; // 257B
367+ u8 reserved_6[3];
368+
369+ u8 band;
370+ u8 reserved_7[3];
371+
372+ // for MLME module
373+ u16 wState; // the current state of the system
374+ u16 wIndex; // THIS BSS element entry index
375+
376+ void* psAdapter; // pointer to THIS Adapter
377+ OS_TIMER nTimer; // MLME timer
378+
379+ // Authentication
380+ u16 wAuthAlgo; // peer MAC MLME use Auth algorithm, default OPEN_AUTH
381+ u16 wAuthSeqNum; // current local MAC sendout AuthReq sequence number
382+
383+ u8 auth_challengeText[128];
384+
385+ ////For XP:
386+ u32 ies_len; // information element length
387+ u8 ies[256]; // information element
388+
389+ ////For WPA
390+ u8 RsnIe_Type[2]; //added by ws for distinguish WPA and WPA2 05/14/04
391+ u8 RsnIe_len;
392+ u8 Rsn_Num;
393+
394+ // to record the rsn cipher suites,addded by ws 09/05/04
395+ SUITE_SELECTOR group_cipher; // 4B
396+ SUITE_SELECTOR pairwise_key_cipher_suites[WLAN_MAX_PAIRWISE_CIPHER_SUITE_COUNT];
397+ SUITE_SELECTOR auth_key_mgt_suites[WLAN_MAX_AUTH_KEY_MGT_SUITE_LIST_COUNT];
398+
399+ u16 pairwise_key_cipher_suite_count;
400+ u16 auth_key_mgt_suite_count;
401+
402+ u8 pairwise_key_cipher_suite_selected;
403+ u8 auth_key_mgt_suite_selected;
404+ u8 reserved_8[2];
405+
406+ struct RSN_Capability_Element rsn_capabilities; // 2B
407+ u8 reserved_9[2];
408+
409+ //to record the rsn cipher suites for WPA2
410+ #ifdef _WPA2_
411+ u32 pre_auth; //added by WS for distinguish for 05/04/04
412+ SUITE_SELECTOR wpa2_group_cipher; // 4B
413+ SUITE_SELECTOR wpa2_pairwise_key_cipher_suites[WLAN_MAX_PAIRWISE_CIPHER_SUITE_COUNT];
414+ SUITE_SELECTOR wpa2_auth_key_mgt_suites[WLAN_MAX_AUTH_KEY_MGT_SUITE_LIST_COUNT];
415+
416+ u16 wpa2_pairwise_key_cipher_suite_count;
417+ u16 wpa2_auth_key_mgt_suite_count;
418+
419+ u8 wpa2_pairwise_key_cipher_suite_selected;
420+ u8 wpa2_auth_key_mgt_suite_selected;
421+ u8 reserved_10[2];
422+
423+ struct RSN_Capability_Element wpa2_rsn_capabilities; // 2B
424+ u8 reserved_11[2];
425+ #endif //endif _WPA2_
426+
427+ //For Replay protection
428+// u8 PairwiseTSC[6];
429+// u8 GroupTSC[6];
430+
431+ ////For up-to-date
432+ u32 ScanTimeStamp; //for the decision whether the station/AP(may exist at
433+ //different channels) has left. It must be detected by
434+ //scanning. Local device may connected or disconnected.
435+ u32 BssTimeStamp; //Only for the decision whether the station/AP(exist in
436+ //the same channel, and no scanning) if local device has
437+ //connected successfully.
438+
439+ // 20061108 Add for storing WPS_IE. [E id][Length][OUI][Data]
440+ u8 WPS_IE_Data[MAX_IE_APPEND_SIZE];
441+ u16 WPS_IE_length;
442+ u16 WPS_IE_length_tmp; // For verify there is an WPS_IE in Beacon or probe response
443+
444+} WB_BSSDESCRIPTION, *PWB_BSSDESCRIPTION;
445+
446+#define wBSSConnectedSTA(Adapter) \
447+ ((u16)(Adapter)->sLocalPara.wConnectedSTAindex)
448+
449+#define psBSS(i) (&(Adapter->asBSSDescriptElement[(i)]))
450+
451+
452diff --git a/drivers/staging/winbond/ds_tkip.h b/drivers/staging/winbond/ds_tkip.h
453new file mode 100644
454index 0000000..29e5055
455--- /dev/null
456+++ b/drivers/staging/winbond/ds_tkip.h
457@@ -0,0 +1,33 @@
458+// Rotation functions on 32 bit values
459+#define ROL32( A, n ) \
460+ ( ((A) << (n)) | ( ((A)>>(32-(n))) & ( (1UL << (n)) - 1 ) ) )
461+
462+#define ROR32( A, n ) ROL32( (A), 32-(n) )
463+
464+
465+typedef struct tkip
466+{
467+ u32 K0, K1; // Key
468+ union
469+ {
470+ struct // Current state
471+ {
472+ u32 L;
473+ u32 R;
474+ };
475+ u8 LR[8];
476+ };
477+ union
478+ {
479+ u32 M; // Message accumulator (single word)
480+ u8 Mb[4];
481+ };
482+ s32 bytes_in_M; // # bytes in M
483+} tkip_t;
484+
485+//void _append_data( PUCHAR pData, u16 size, tkip_t *p );
486+void Mds_MicGet( void* Adapter, void* pRxLayer1, PUCHAR pKey, PUCHAR pMic );
487+void Mds_MicFill( void* Adapter, void* pDes, PUCHAR XmitBufAddress );
488+
489+
490+
491diff --git a/drivers/staging/winbond/gl_80211.h b/drivers/staging/winbond/gl_80211.h
492new file mode 100644
493index 0000000..1806d81
494--- /dev/null
495+++ b/drivers/staging/winbond/gl_80211.h
496@@ -0,0 +1,125 @@
497+
498+#ifndef __GL_80211_H__
499+#define __GL_80211_H__
500+
501+/****************** CONSTANT AND MACRO SECTION ******************************/
502+
503+/* BSS Type */
504+enum {
505+ WLAN_BSSTYPE_INFRASTRUCTURE = 0,
506+ WLAN_BSSTYPE_INDEPENDENT,
507+ WLAN_BSSTYPE_ANY_BSS,
508+};
509+
510+
511+
512+/* Preamble_Type, see <SFS-802.11G-MIB-203> */
513+typedef enum preamble_type {
514+ WLAN_PREAMBLE_TYPE_SHORT,
515+ WLAN_PREAMBLE_TYPE_LONG,
516+} preamble_type_e;
517+
518+
519+/* Slot_Time_Type, see <SFS-802.11G-MIB-208> */
520+typedef enum slot_time_type {
521+ WLAN_SLOT_TIME_TYPE_LONG,
522+ WLAN_SLOT_TIME_TYPE_SHORT,
523+} slot_time_type_e;
524+
525+/*--------------------------------------------------------------------------*/
526+/* Encryption Mode */
527+typedef enum {
528+ WEP_DISABLE = 0,
529+ WEP_64,
530+ WEP_128,
531+
532+ ENCRYPT_DISABLE,
533+ ENCRYPT_WEP,
534+ ENCRYPT_WEP_NOKEY,
535+ ENCRYPT_TKIP,
536+ ENCRYPT_TKIP_NOKEY,
537+ ENCRYPT_CCMP,
538+ ENCRYPT_CCMP_NOKEY,
539+} encryption_mode_e;
540+
541+typedef enum _WLAN_RADIO {
542+ WLAN_RADIO_ON,
543+ WLAN_RADIO_OFF,
544+ WLAN_RADIO_MAX, // not a real type, defined as an upper bound
545+} WLAN_RADIO;
546+
547+typedef struct _WLAN_RADIO_STATUS {
548+ WLAN_RADIO HWStatus;
549+ WLAN_RADIO SWStatus;
550+} WLAN_RADIO_STATUS;
551+
552+//----------------------------------------------------------------------------
553+// 20041021 1.1.81.1000 ybjiang
554+// add for radio notification
555+typedef
556+void (*RADIO_NOTIFICATION_HANDLER)(
557+ void *Data,
558+ void *RadioStatusBuffer,
559+ u32 RadioStatusBufferLen
560+ );
561+
562+typedef struct _WLAN_RADIO_NOTIFICATION
563+{
564+ RADIO_NOTIFICATION_HANDLER RadioChangeHandler;
565+ void *Data;
566+} WLAN_RADIO_NOTIFICATION;
567+
568+//----------------------------------------------------------------------------
569+// 20041102 1.1.91.1000 ybjiang
570+// add for OID_802_11_CUST_REGION_CAPABILITIES and OID_802_11_OID_REGION
571+typedef enum _WLAN_REGION_CODE
572+{
573+ WLAN_REGION_UNKNOWN,
574+ WLAN_REGION_EUROPE,
575+ WLAN_REGION_JAPAN,
576+ WLAN_REGION_USA,
577+ WLAN_REGION_FRANCE,
578+ WLAN_REGION_SPAIN,
579+ WLAN_REGION_ISRAEL,
580+ WLAN_REGION_MAX, // not a real type, defined as an upper bound
581+} WLAN_REGION_CODE;
582+
583+#define REGION_NAME_MAX_LENGTH 256
584+
585+typedef struct _WLAN_REGION_CHANNELS
586+{
587+ u32 Length;
588+ u32 NameLength;
589+ u8 Name[REGION_NAME_MAX_LENGTH];
590+ WLAN_REGION_CODE Code;
591+ u32 Frequency[1];
592+} WLAN_REGION_CHANNELS;
593+
594+typedef struct _WLAN_REGION_CAPABILITIES
595+{
596+ u32 NumberOfItems;
597+ WLAN_REGION_CHANNELS Region[1];
598+} WLAN_REGION_CAPABILITIES;
599+
600+typedef struct _region_name_map {
601+ WLAN_REGION_CODE region;
602+ u8 *name;
603+ u32 *channels;
604+} region_name_map;
605+
606+/*--------------------------------------------------------------------------*/
607+#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
608+#define MACSTR "%02X:%02X:%02X:%02X:%02X:%02X"
609+
610+// TODO: 0627 kevin
611+#define MIC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5], (a)[6], (a)[7]
612+#define MICSTR "%02X %02X %02X %02X %02X %02X %02X %02X"
613+
614+#define MICKEY2STR(a) MIC2STR(a)
615+#define MICKEYSTR MICSTR
616+
617+
618+#endif /* __GL_80211_H__ */
619+/*** end of file ***/
620+
621+
622diff --git a/drivers/staging/winbond/ioctls.h b/drivers/staging/winbond/ioctls.h
623new file mode 100644
624index 0000000..e8b35dc
625--- /dev/null
626+++ b/drivers/staging/winbond/ioctls.h
627@@ -0,0 +1,678 @@
628+//============================================================================
629+// IOCTLS.H -
630+//
631+// Description:
632+// Define the IOCTL codes.
633+//
634+// Revision history:
635+// --------------------------------------------------------------------------
636+//
637+// Copyright (c) 2002-2004 Winbond Electronics Corp. All rights reserved.
638+//=============================================================================
639+
640+#ifndef _IOCTLS_H
641+#define _IOCTLS_H
642+
643+// PD43 Keep it - Used with the Win33 application
644+// #include <winioctl.h>
645+
646+//========================================================
647+// 20040108 ADD the follow for test
648+//========================================================
649+#define INFORMATION_LENGTH sizeof(unsigned int)
650+
651+#define WB32_IOCTL_INDEX 0x0900 //­×§ďĽHŤKŹŰŽe//
652+
653+#define Wb32_RegisterRead CTL_CODE( \
654+ FILE_DEVICE_UNKNOWN, \
655+ WB32_IOCTL_INDEX + 0, \
656+ METHOD_BUFFERED, \
657+ FILE_ANY_ACCESS)
658+
659+#define Wb32_RegisterWrite CTL_CODE( \
660+ FILE_DEVICE_UNKNOWN, \
661+ WB32_IOCTL_INDEX + 1, \
662+ METHOD_BUFFERED, \
663+ FILE_ANY_ACCESS)
664+
665+#define Wb32_SendPacket CTL_CODE( \
666+ FILE_DEVICE_UNKNOWN, \
667+ WB32_IOCTL_INDEX + 2, \
668+ METHOD_BUFFERED, \
669+ FILE_ANY_ACCESS)
670+
671+#define Wb32_QuerySendResult CTL_CODE( \
672+ FILE_DEVICE_UNKNOWN, \
673+ WB32_IOCTL_INDEX + 3, \
674+ METHOD_BUFFERED, \
675+ FILE_ANY_ACCESS)
676+
677+#define Wb32_SetFragmentThreshold CTL_CODE( \
678+ FILE_DEVICE_UNKNOWN, \
679+ WB32_IOCTL_INDEX + 4, \
680+ METHOD_BUFFERED, \
681+ FILE_ANY_ACCESS)
682+
683+#define Wb32_SetLinkStatus CTL_CODE( \
684+ FILE_DEVICE_UNKNOWN, \
685+ WB32_IOCTL_INDEX + 5, \
686+ METHOD_BUFFERED, \
687+ FILE_ANY_ACCESS)
688+
689+#define Wb32_SetBulkIn CTL_CODE( \
690+ FILE_DEVICE_UNKNOWN, \
691+ WB32_IOCTL_INDEX + 6, \
692+ METHOD_BUFFERED, \
693+ FILE_ANY_ACCESS)
694+
695+#define Wb32_LoopbackTest CTL_CODE( \
696+ FILE_DEVICE_UNKNOWN, \
697+ WB32_IOCTL_INDEX + 7, \
698+ METHOD_BUFFERED, \
699+ FILE_ANY_ACCESS)
700+
701+#define Wb35_EEPromRead CTL_CODE( \
702+ FILE_DEVICE_UNKNOWN, \
703+ WB32_IOCTL_INDEX + 8, \
704+ METHOD_BUFFERED, \
705+ FILE_ANY_ACCESS)
706+
707+#define Wb35_EEPromWrite CTL_CODE( \
708+ FILE_DEVICE_UNKNOWN, \
709+ WB32_IOCTL_INDEX + 9, \
710+ METHOD_BUFFERED, \
711+ FILE_ANY_ACCESS)
712+
713+#define Wb35_FlashReadData CTL_CODE( \
714+ FILE_DEVICE_UNKNOWN, \
715+ WB32_IOCTL_INDEX + 10, \
716+ METHOD_BUFFERED, \
717+ FILE_ANY_ACCESS)
718+
719+#define Wb35_FlashWrite CTL_CODE( \
720+ FILE_DEVICE_UNKNOWN, \
721+ WB32_IOCTL_INDEX + 11, \
722+ METHOD_BUFFERED, \
723+ FILE_ANY_ACCESS)
724+
725+#define Wb35_FlashWriteBurst CTL_CODE( \
726+ FILE_DEVICE_UNKNOWN, \
727+ WB32_IOCTL_INDEX + 12, \
728+ METHOD_BUFFERED, \
729+ FILE_ANY_ACCESS)
730+
731+#define Wb35_TxBurstStart CTL_CODE( \
732+ FILE_DEVICE_UNKNOWN, \
733+ WB32_IOCTL_INDEX + 13, \
734+ METHOD_BUFFERED, \
735+ FILE_ANY_ACCESS)
736+
737+#define Wb35_TxBurstStop CTL_CODE( \
738+ FILE_DEVICE_UNKNOWN, \
739+ WB32_IOCTL_INDEX + 14, \
740+ METHOD_BUFFERED, \
741+ FILE_ANY_ACCESS)
742+
743+#define Wb35_TxBurstStatus CTL_CODE( \
744+ FILE_DEVICE_UNKNOWN, \
745+ WB32_IOCTL_INDEX + 15, \
746+ METHOD_BUFFERED, \
747+ FILE_ANY_ACCESS)
748+
749+// For IOCTL interface
750+//================================================
751+#define LINKNAME_STRING "\\DosDevices\\W35UND"
752+#define NTDEVICE_STRING "\\Device\\W35UND"
753+#define APPLICATION_LINK "\\\\.\\W35UND"
754+
755+#define WB_IOCTL_INDEX 0x0800
756+#define WB_IOCTL_TS_INDEX WB_IOCTL_INDEX + 60
757+#define WB_IOCTL_DUT_INDEX WB_IOCTL_TS_INDEX + 40
758+
759+//=============================================================================
760+// IOCTLS defined for DUT (Device Under Test)
761+
762+// IOCTL_WB_802_11_DUT_MAC_ADDRESS
763+// Query: Return the dot11StationID
764+// Set : Set the dot11StationID. Demo only.
765+//
766+#define IOCTL_WB_802_11_DUT_MAC_ADDRESS CTL_CODE( \
767+ FILE_DEVICE_UNKNOWN, \
768+ WB_IOCTL_DUT_INDEX + 1, \
769+ METHOD_BUFFERED, \
770+ FILE_ANY_ACCESS)
771+
772+// IOCTL_WB_802_11_DUT_BSS_DESCRIPTION
773+// Query: Return the info. of the current connected BSS.
774+// Set : None.
775+//
776+#define IOCTL_WB_802_11_DUT_BSS_DESCRIPTION CTL_CODE( \
777+ FILE_DEVICE_UNKNOWN, \
778+ WB_IOCTL_DUT_INDEX + 2, \
779+ METHOD_BUFFERED, \
780+ FILE_ANY_ACCESS)
781+
782+// IOCTL_WB_802_11_DUT_TX_RATE
783+// Query: Return the current transmission rate.
784+// Set : Set the transmission rate of the Tx packets.
785+//
786+#define IOCTL_WB_802_11_DUT_TX_RATE CTL_CODE( \
787+ FILE_DEVICE_UNKNOWN, \
788+ WB_IOCTL_DUT_INDEX + 3, \
789+ METHOD_BUFFERED, \
790+ FILE_ANY_ACCESS)
791+
792+// IOCTL_WB_802_11_DUT_CURRENT_STA_STATE
793+// Query: Return the current STA state. (WB_STASTATE type)
794+// Set : None.
795+//
796+#define IOCTL_WB_802_11_DUT_CURRENT_STA_STATE CTL_CODE( \
797+ FILE_DEVICE_UNKNOWN, \
798+ WB_IOCTL_DUT_INDEX + 4, \
799+ METHOD_BUFFERED, \
800+ FILE_ANY_ACCESS)
801+
802+/////////// 10/31/02' Added /////////////////////
803+
804+// IOCTL_WB_802_11_DUT_START_IBSS_REQUEST
805+// Query: None.
806+// Set : Start a new IBSS
807+//
808+#define IOCTL_WB_802_11_DUT_START_IBSS_REQUEST CTL_CODE( \
809+ FILE_DEVICE_UNKNOWN, \
810+ WB_IOCTL_DUT_INDEX + 5, \
811+ METHOD_BUFFERED, \
812+ FILE_ANY_ACCESS)
813+
814+// IOCTL_WB_802_11_DUT_JOIN_REQUEST
815+// Query: None.
816+// Set : Synchronize with the selected BSS
817+//
818+#define IOCTL_WB_802_11_DUT_JOIN_REQUEST CTL_CODE( \
819+ FILE_DEVICE_UNKNOWN, \
820+ WB_IOCTL_DUT_INDEX + 6, \
821+ METHOD_BUFFERED, \
822+ FILE_ANY_ACCESS)
823+
824+// IOCTL_WB_802_11_DUT_AUTHEN_REQUEST
825+// Query: None.
826+// Set : Authenticate with the BSS
827+//
828+#define IOCTL_WB_802_11_DUT_AUTHEN_REQUEST CTL_CODE( \
829+ FILE_DEVICE_UNKNOWN, \
830+ WB_IOCTL_DUT_INDEX + 7, \
831+ METHOD_BUFFERED, \
832+ FILE_ANY_ACCESS)
833+
834+// IOCTL_WB_802_11_DUT_DEAUTHEN_REQUEST
835+// Query: None.
836+// Set : DeAuthenticate withe the BSS
837+//
838+#define IOCTL_WB_802_11_DUT_DEAUTHEN_REQUEST CTL_CODE( \
839+ FILE_DEVICE_UNKNOWN, \
840+ WB_IOCTL_DUT_INDEX + 8, \
841+ METHOD_BUFFERED, \
842+ FILE_ANY_ACCESS)
843+
844+// IOCTL_WB_802_11_DUT_ASSOC_REQUEST
845+// Query: None.
846+// Set : Associate withe the BSS
847+//
848+#define IOCTL_WB_802_11_DUT_ASSOC_REQUEST CTL_CODE( \
849+ FILE_DEVICE_UNKNOWN, \
850+ WB_IOCTL_DUT_INDEX + 9, \
851+ METHOD_BUFFERED, \
852+ FILE_ANY_ACCESS)
853+
854+// IOCTL_WB_802_11_DUT_REASSOC_REQUEST
855+// Query: None.
856+// Set : ReAssociate withe the BSS
857+//
858+#define IOCTL_WB_802_11_DUT_REASSOC_REQUEST CTL_CODE( \
859+ FILE_DEVICE_UNKNOWN, \
860+ WB_IOCTL_DUT_INDEX + 10, \
861+ METHOD_BUFFERED, \
862+ FILE_ANY_ACCESS)
863+
864+
865+// IOCTL_WB_802_11_DUT_DISASSOC_REQUEST
866+// Query: None.
867+// Set : DisAssociate withe the BSS
868+//
869+#define IOCTL_WB_802_11_DUT_DISASSOC_REQUEST CTL_CODE( \
870+ FILE_DEVICE_UNKNOWN, \
871+ WB_IOCTL_DUT_INDEX + 11, \
872+ METHOD_BUFFERED, \
873+ FILE_ANY_ACCESS)
874+
875+// IOCTL_WB_802_11_DUT_FRAG_THRESHOLD
876+// Query: Return the dot11FragmentThreshold
877+// Set : Set the dot11FragmentThreshold
878+//
879+#define IOCTL_WB_802_11_DUT_FRAG_THRESHOLD CTL_CODE( \
880+ FILE_DEVICE_UNKNOWN, \
881+ WB_IOCTL_DUT_INDEX + 12, \
882+ METHOD_BUFFERED, \
883+ FILE_ANY_ACCESS)
884+
885+// IOCTL_WB_802_11_DUT_RTS_THRESHOLD
886+// Query: Return the dot11RTSThreshold
887+// Set : Set the dot11RTSThresold
888+//
889+#define IOCTL_WB_802_11_DUT_RTS_THRESHOLD CTL_CODE( \
890+ FILE_DEVICE_UNKNOWN, \
891+ WB_IOCTL_DUT_INDEX + 13, \
892+ METHOD_BUFFERED, \
893+ FILE_ANY_ACCESS)
894+
895+// IOCTL_WB_802_11_DUT_WEP_KEYMODE
896+// Query: Get the WEP key mode.
897+// Set : Set the WEP key mode: disable/64 bits/128 bits
898+//
899+#define IOCTL_WB_802_11_DUT_WEP_KEYMODE CTL_CODE( \
900+ FILE_DEVICE_UNKNOWN, \
901+ WB_IOCTL_DUT_INDEX + 14, \
902+ METHOD_BUFFERED, \
903+ FILE_ANY_ACCESS)
904+
905+// IOCTL_WB_802_11_DUT_WEP_KEYVALUE
906+// Query: None.
907+// Set : fill in the WEP key value
908+//
909+#define IOCTL_WB_802_11_DUT_WEP_KEYVALUE CTL_CODE( \
910+ FILE_DEVICE_UNKNOWN, \
911+ WB_IOCTL_DUT_INDEX + 15, \
912+ METHOD_BUFFERED, \
913+ FILE_ANY_ACCESS)
914+
915+// IOCTL_WB_802_11_DUT_RESET
916+// Query: None.
917+// Set : Reset S/W and H/W
918+//
919+#define IOCTL_WB_802_11_DUT_RESET CTL_CODE( \
920+ FILE_DEVICE_UNKNOWN, \
921+ WB_IOCTL_DUT_INDEX + 16, \
922+ METHOD_BUFFERED, \
923+ FILE_ANY_ACCESS)
924+
925+// IOCTL_WB_802_11_DUT_POWER_SAVE
926+// Query: None.
927+// Set : Set Power Save Mode
928+//
929+#define IOCTL_WB_802_11_DUT_POWER_SAVE CTL_CODE( \
930+ FILE_DEVICE_UNKNOWN, \
931+ WB_IOCTL_DUT_INDEX + 17, \
932+ METHOD_BUFFERED, \
933+ FILE_ANY_ACCESS)
934+
935+// IOCTL_WB_802_11_DUT_BSSID_LIST_SCAN
936+// Query: None.
937+// Set :
938+//
939+#define IOCTL_WB_802_11_DUT_BSSID_LIST_SCAN CTL_CODE( \
940+ FILE_DEVICE_UNKNOWN, \
941+ WB_IOCTL_DUT_INDEX + 18, \
942+ METHOD_BUFFERED, \
943+ FILE_ANY_ACCESS)
944+
945+// IOCTL_WB_802_11_DUT_BSSID_LIST
946+// Query: Return the BSS info of BSSs in the last scanning process
947+// Set : None.
948+//
949+#define IOCTL_WB_802_11_DUT_BSSID_LIST CTL_CODE( \
950+ FILE_DEVICE_UNKNOWN, \
951+ WB_IOCTL_DUT_INDEX + 19, \
952+ METHOD_BUFFERED, \
953+ FILE_ANY_ACCESS)
954+
955+// IOCTL_WB_802_11_DUT_STATISTICS
956+// Query: Return the statistics of Tx/Rx.
957+// Set : None.
958+//
959+#define IOCTL_WB_802_11_DUT_STATISTICS CTL_CODE( \
960+ FILE_DEVICE_UNKNOWN, \
961+ WB_IOCTL_DUT_INDEX + 20, \
962+ METHOD_BUFFERED, \
963+ FILE_ANY_ACCESS)
964+
965+// IOCTL_WB_802_11_DUT_ACCEPT_BEACON
966+// Query: Return the current mode to accept beacon or not.
967+// Set : Enable or disable allowing the HW-MAC to pass the beacon to the SW-MAC
968+// Arguments: unsigned char
969+//
970+#define IOCTL_WB_802_11_DUT_ACCEPT_BEACON CTL_CODE( \
971+ FILE_DEVICE_UNKNOWN, \
972+ WB_IOCTL_DUT_INDEX + 21, \
973+ METHOD_BUFFERED, \
974+ FILE_ANY_ACCESS)
975+
976+// IOCTL_WB_802_11_DUT_ROAMING
977+// Query: Return the roaming function status
978+// Set : Enable/Disable the roaming function.
979+#define IOCTL_WB_802_11_DUT_ROAMING CTL_CODE( \
980+ FILE_DEVICE_UNKNOWN, \
981+ WB_IOCTL_DUT_INDEX + 22, \
982+ METHOD_BUFFERED, \
983+ FILE_ANY_ACCESS)
984+
985+// IOCTL_WB_802_11_DUT_DTO
986+// Query: Return the DTO(Data Throughput Optimization)
987+// function status (TRUE or FALSE)
988+// Set : Enable/Disable the DTO function.
989+//
990+#define IOCTL_WB_802_11_DUT_DTO CTL_CODE( \
991+ FILE_DEVICE_UNKNOWN, \
992+ WB_IOCTL_DUT_INDEX + 23, \
993+ METHOD_BUFFERED, \
994+ FILE_ANY_ACCESS)
995+
996+// IOCTL_WB_802_11_DUT_ANTENNA_DIVERSITY
997+// Query: Return the antenna diversity status. (TRUE/ON or FALSE/OFF)
998+// Set : Enable/Disable the antenna diversity.
999+//
1000+#define IOCTL_WB_802_11_DUT_ANTENNA_DIVERSITY CTL_CODE( \
1001+ FILE_DEVICE_UNKNOWN, \
1002+ WB_IOCTL_DUT_INDEX + 24, \
1003+ METHOD_BUFFERED, \
1004+ FILE_ANY_ACCESS)
1005+
1006+//-------------- new added for a+b+g ---------------------
1007+// IOCTL_WB_802_11_DUT_MAC_OPERATION_MODE
1008+// Query: Return the MAC operation mode. (MODE_802_11_BG, MODE_802_11_A,
1009+// MODE_802_11_ABG, MODE_802_11_BG_IBSS)
1010+// Set : Set the MAC operation mode.
1011+//
1012+#define IOCTL_WB_802_11_DUT_MAC_OPERATION_MODE CTL_CODE( \
1013+ FILE_DEVICE_UNKNOWN, \
1014+ WB_IOCTL_DUT_INDEX + 25, \
1015+ METHOD_BUFFERED, \
1016+ FILE_ANY_ACCESS)
1017+
1018+// IOCTL_WB_802_11_DUT_TX_RATE_REDEFINED
1019+// Query: Return the current tx rate which follows the definition in spec. (for
1020+// example, 5.5M => 0x0b)
1021+// Set : None
1022+//
1023+#define IOCTL_WB_802_11_DUT_TX_RATE_REDEFINED CTL_CODE( \
1024+ FILE_DEVICE_UNKNOWN, \
1025+ WB_IOCTL_DUT_INDEX + 26, \
1026+ METHOD_BUFFERED, \
1027+ FILE_ANY_ACCESS)
1028+
1029+// IOCTL_WB_802_11_DUT_PREAMBLE_MODE
1030+// Query: Return the preamble mode. (auto or long)
1031+// Set : Set the preamble mode.
1032+//
1033+#define IOCTL_WB_802_11_DUT_PREAMBLE_MODE CTL_CODE( \
1034+ FILE_DEVICE_UNKNOWN, \
1035+ WB_IOCTL_DUT_INDEX + 27, \
1036+ METHOD_BUFFERED, \
1037+ FILE_ANY_ACCESS)
1038+
1039+// IOCTL_WB_802_11_DUT_SLOT_TIME_MODE
1040+// Query: Return the slot time mode. (auto or long)
1041+// Set : Set the slot time mode.
1042+//
1043+#define IOCTL_WB_802_11_DUT_SLOT_TIME_MODE CTL_CODE( \
1044+ FILE_DEVICE_UNKNOWN, \
1045+ WB_IOCTL_DUT_INDEX + 28, \
1046+ METHOD_BUFFERED, \
1047+ FILE_ANY_ACCESS)
1048+//------------------------------------------------------------------
1049+
1050+// IOCTL_WB_802_11_DUT_ADVANCE_STATUS
1051+// Query:
1052+// Set : NONE
1053+//
1054+#define IOCTL_WB_802_11_DUT_ADVANCE_STATUS CTL_CODE( \
1055+ FILE_DEVICE_UNKNOWN, \
1056+ WB_IOCTL_DUT_INDEX + 29, \
1057+ METHOD_BUFFERED, \
1058+ FILE_ANY_ACCESS)
1059+
1060+// IOCTL_WB_802_11_DUT_TX_RATE_MODE
1061+// Query: Return the tx rate mode. (RATE_AUTO, RATE_1M, .., RATE_54M, RATE_MAX)
1062+// Set : Set the tx rate mode. (RATE_AUTO, RATE_1M, .., RATE_54M, RATE_MAX)
1063+//
1064+#define IOCTL_WB_802_11_DUT_TX_RATE_MODE CTL_CODE( \
1065+ FILE_DEVICE_UNKNOWN, \
1066+ WB_IOCTL_DUT_INDEX + 30, \
1067+ METHOD_BUFFERED, \
1068+ FILE_ANY_ACCESS)
1069+
1070+// IOCTL_WB_802_11_DUT_DTO_PARA
1071+// Query: Return the DTO parameters
1072+// Set : Set the DTO parameters
1073+//
1074+#define IOCTL_WB_802_11_DUT_DTO_PARA CTL_CODE( \
1075+ FILE_DEVICE_UNKNOWN, \
1076+ WB_IOCTL_DUT_INDEX + 31, \
1077+ METHOD_BUFFERED, \
1078+ FILE_ANY_ACCESS)
1079+
1080+// IOCTL_WB_802_11_DUT_EVENT_LOG
1081+// Query: Return event log
1082+// Set : Reset event log
1083+//
1084+#define IOCTL_WB_802_11_DUT_EVENT_LOG CTL_CODE( \
1085+ FILE_DEVICE_UNKNOWN, \
1086+ WB_IOCTL_DUT_INDEX + 32, \
1087+ METHOD_BUFFERED, \
1088+ FILE_ANY_ACCESS)
1089+
1090+// IOCTL_WB_802_11_DUT_CWMIN
1091+// Query: NONE(It will be obtained by IOCTL_WB_802_11_DUT_ADVANCE_STATUS)
1092+// Set : Set CWMin value
1093+//
1094+#define IOCTL_WB_802_11_DUT_CWMIN CTL_CODE( \
1095+ FILE_DEVICE_UNKNOWN, \
1096+ WB_IOCTL_DUT_INDEX + 33, \
1097+ METHOD_BUFFERED, \
1098+ FILE_ANY_ACCESS)
1099+
1100+// IOCTL_WB_802_11_DUT_CWMAX
1101+// Query: NONE(It will be obtained by IOCTL_WB_802_11_DUT_ADVANCE_STATUS)
1102+// Set : Set CWMax value
1103+//
1104+#define IOCTL_WB_802_11_DUT_CWMAX CTL_CODE( \
1105+ FILE_DEVICE_UNKNOWN, \
1106+ WB_IOCTL_DUT_INDEX + 34, \
1107+ METHOD_BUFFERED, \
1108+ FILE_ANY_ACCESS)
1109+
1110+
1111+//==========================================================
1112+// IOCTLs for Testing
1113+
1114+// IOCTL_WB_802_11_TS_SET_CXX_REG
1115+// Query: None
1116+// Set : Write the value to one of Cxx register.
1117+//
1118+#define IOCTL_WB_802_11_TS_SET_CXX_REG CTL_CODE( \
1119+ FILE_DEVICE_UNKNOWN, \
1120+ WB_IOCTL_TS_INDEX + 0, \
1121+ METHOD_BUFFERED, \
1122+ FILE_ANY_ACCESS)
1123+
1124+// IOCTL_WB_802_11_TS_GET_CXX_REG
1125+// Query: Return the value of the Cxx register.
1126+// Set : Write the reg no. (0x00, 0x04, 0x08 etc)
1127+//
1128+#define IOCTL_WB_802_11_TS_GET_CXX_REG CTL_CODE( \
1129+ FILE_DEVICE_UNKNOWN, \
1130+ WB_IOCTL_TS_INDEX + 1, \
1131+ METHOD_BUFFERED, \
1132+ FILE_ANY_ACCESS)
1133+
1134+// IOCTL_WB_802_11_TS_SET_DXX_REG
1135+// Query: None
1136+// Set : Write the value to one of Dxx register.
1137+//
1138+#define IOCTL_WB_802_11_TS_SET_DXX_REG CTL_CODE( \
1139+ FILE_DEVICE_UNKNOWN, \
1140+ WB_IOCTL_TS_INDEX + 2, \
1141+ METHOD_BUFFERED, \
1142+ FILE_ANY_ACCESS)
1143+
1144+// IOCTL_WB_802_11_TS_GET_DXX_REG
1145+// Query: Return the value of the Dxx register.
1146+// Set : Write the reg no. (0x00, 0x04, 0x08 etc)
1147+//
1148+#define IOCTL_WB_802_11_TS_GET_DXX_REG CTL_CODE( \
1149+ FILE_DEVICE_UNKNOWN, \
1150+ WB_IOCTL_TS_INDEX + 3, \
1151+ METHOD_BUFFERED, \
1152+ FILE_ANY_ACCESS)
1153+
1154+//============================================================
1155+// [TS]
1156+
1157+#define IOCTL_WB_802_11_TS_TX_RATE CTL_CODE( \
1158+ FILE_DEVICE_UNKNOWN, \
1159+ WB_IOCTL_TS_INDEX + 4, \
1160+ METHOD_BUFFERED, \
1161+ FILE_ANY_ACCESS)
1162+
1163+#define IOCTL_WB_802_11_TS_CURRENT_CHANNEL CTL_CODE( \
1164+ FILE_DEVICE_UNKNOWN, \
1165+ WB_IOCTL_TS_INDEX + 5, \
1166+ METHOD_BUFFERED, \
1167+ FILE_ANY_ACCESS)
1168+
1169+#define IOCTL_WB_802_11_TS_ENABLE_SEQNO CTL_CODE( \
1170+ FILE_DEVICE_UNKNOWN, \
1171+ WB_IOCTL_TS_INDEX + 6, \
1172+ METHOD_BUFFERED, \
1173+ FILE_ANY_ACCESS)
1174+
1175+#define IOCTL_WB_802_11_TS_ENALBE_ACKEDPACKET CTL_CODE( \
1176+ FILE_DEVICE_UNKNOWN, \
1177+ WB_IOCTL_TS_INDEX + 7, \
1178+ METHOD_BUFFERED, \
1179+ FILE_ANY_ACCESS)
1180+
1181+#define IOCTL_WB_802_11_TS_INHIBIT_CRC CTL_CODE( \
1182+ FILE_DEVICE_UNKNOWN, \
1183+ WB_IOCTL_TS_INDEX + 8, \
1184+ METHOD_BUFFERED, \
1185+ FILE_ANY_ACCESS)
1186+
1187+#define IOCTL_WB_802_11_TS_RESET_RCV_COUNTER CTL_CODE( \
1188+ FILE_DEVICE_UNKNOWN, \
1189+ WB_IOCTL_TS_INDEX + 9, \
1190+ METHOD_BUFFERED, \
1191+ FILE_ANY_ACCESS)
1192+
1193+#define IOCTL_WB_802_11_TS_SET_TX_TRIGGER CTL_CODE( \
1194+ FILE_DEVICE_UNKNOWN, \
1195+ WB_IOCTL_TS_INDEX + 10, \
1196+ METHOD_BUFFERED, \
1197+ FILE_ANY_ACCESS)
1198+
1199+#define IOCTL_WB_802_11_TS_FAILED_TX_COUNT CTL_CODE( \
1200+ FILE_DEVICE_UNKNOWN, \
1201+ WB_IOCTL_TS_INDEX + 11, \
1202+ METHOD_BUFFERED, \
1203+ FILE_ANY_ACCESS)
1204+
1205+// [TS1]
1206+#define IOCTL_WB_802_11_TS_TX_POWER CTL_CODE( \
1207+ FILE_DEVICE_UNKNOWN, \
1208+ WB_IOCTL_TS_INDEX + 12, \
1209+ METHOD_BUFFERED, \
1210+ FILE_ANY_ACCESS)
1211+
1212+#define IOCTL_WB_802_11_TS_MODE_ENABLE CTL_CODE( \
1213+ FILE_DEVICE_UNKNOWN, \
1214+ WB_IOCTL_TS_INDEX + 13, \
1215+ METHOD_BUFFERED, \
1216+ FILE_ANY_ACCESS)
1217+
1218+#define IOCTL_WB_802_11_TS_MODE_DISABLE CTL_CODE( \
1219+ FILE_DEVICE_UNKNOWN, \
1220+ WB_IOCTL_TS_INDEX + 14, \
1221+ METHOD_BUFFERED, \
1222+ FILE_ANY_ACCESS)
1223+
1224+#define IOCTL_WB_802_11_TS_ANTENNA CTL_CODE( \
1225+ FILE_DEVICE_UNKNOWN, \
1226+ WB_IOCTL_TS_INDEX + 15, \
1227+ METHOD_BUFFERED, \
1228+ FILE_ANY_ACCESS)
1229+
1230+#define IOCTL_WB_802_11_TS_ADAPTER_INFO CTL_CODE( \
1231+ FILE_DEVICE_UNKNOWN, \
1232+ WB_IOCTL_TS_INDEX + 16, \
1233+ METHOD_BUFFERED, \
1234+ FILE_ANY_ACCESS)
1235+
1236+#define IOCTL_WB_802_11_TS_MAC_ADDRESS CTL_CODE( \
1237+ FILE_DEVICE_UNKNOWN, \
1238+ WB_IOCTL_TS_INDEX + 17, \
1239+ METHOD_BUFFERED, \
1240+ FILE_ANY_ACCESS)
1241+
1242+#define IOCTL_WB_802_11_TS_BSSID CTL_CODE( \
1243+ FILE_DEVICE_UNKNOWN, \
1244+ WB_IOCTL_TS_INDEX + 18, \
1245+ METHOD_BUFFERED, \
1246+ FILE_ANY_ACCESS)
1247+
1248+#define IOCTL_WB_802_11_TS_RF_PARAMETER CTL_CODE( \
1249+ FILE_DEVICE_UNKNOWN, \
1250+ WB_IOCTL_TS_INDEX + 19, \
1251+ METHOD_BUFFERED, \
1252+ FILE_ANY_ACCESS)
1253+
1254+#define IOCTL_WB_802_11_TS_FILTER CTL_CODE( \
1255+ FILE_DEVICE_UNKNOWN, \
1256+ WB_IOCTL_TS_INDEX + 20, \
1257+ METHOD_BUFFERED, \
1258+ FILE_ANY_ACCESS)
1259+
1260+#define IOCTL_WB_802_11_TS_CALIBRATION CTL_CODE( \
1261+ FILE_DEVICE_UNKNOWN, \
1262+ WB_IOCTL_TS_INDEX + 21, \
1263+ METHOD_BUFFERED, \
1264+ FILE_ANY_ACCESS)
1265+
1266+#define IOCTL_WB_802_11_TS_BSS_MODE CTL_CODE( \
1267+ FILE_DEVICE_UNKNOWN, \
1268+ WB_IOCTL_TS_INDEX + 22, \
1269+ METHOD_BUFFERED, \
1270+ FILE_ANY_ACCESS)
1271+
1272+#define IOCTL_WB_802_11_TS_SET_SSID CTL_CODE( \
1273+ FILE_DEVICE_UNKNOWN, \
1274+ WB_IOCTL_TS_INDEX + 23, \
1275+ METHOD_BUFFERED, \
1276+ FILE_ANY_ACCESS)
1277+
1278+#define IOCTL_WB_802_11_TS_IBSS_CHANNEL CTL_CODE( \
1279+ FILE_DEVICE_UNKNOWN, \
1280+ WB_IOCTL_TS_INDEX + 24, \
1281+ METHOD_BUFFERED, \
1282+ FILE_ANY_ACCESS)
1283+
1284+// set/query the slot time value(short or long slot time)
1285+#define IOCTL_WB_802_11_TS_SLOT_TIME CTL_CODE( \
1286+ FILE_DEVICE_UNKNOWN, \
1287+ WB_IOCTL_TS_INDEX + 25, \
1288+ METHOD_BUFFERED, \
1289+ FILE_ANY_ACCESS)
1290+
1291+#define IOCTL_WB_802_11_TS_SLOT_TIME CTL_CODE( \
1292+ FILE_DEVICE_UNKNOWN, \
1293+ WB_IOCTL_TS_INDEX + 25, \
1294+ METHOD_BUFFERED, \
1295+ FILE_ANY_ACCESS)
1296+
1297+#define IOCTL_WB_802_11_TS_RX_STATISTICS CTL_CODE( \
1298+ FILE_DEVICE_UNKNOWN, \
1299+ WB_IOCTL_TS_INDEX + 26, \
1300+ METHOD_BUFFERED, \
1301+ FILE_ANY_ACCESS)
1302+
1303+#endif // #ifndef _IOCTLS_H
1304+
1305+
1306diff --git a/drivers/staging/winbond/linux/common.h b/drivers/staging/winbond/linux/common.h
1307new file mode 100644
1308index 0000000..6b00bad
1309--- /dev/null
1310+++ b/drivers/staging/winbond/linux/common.h
1311@@ -0,0 +1,143 @@
1312+//
1313+// common.h
1314+//
1315+// This file contains the OS dependant definition and function.
1316+// Every OS has this file individual.
1317+//
1318+
1319+#define DebugUsbdStatusInformation( _A )
1320+
1321+#ifndef COMMON_DEF
1322+#define COMMON_DEF
1323+
1324+#include <linux/version.h>
1325+#include <linux/usb.h>
1326+#include <linux/kernel.h> //need for kernel alert
1327+#include <linux/autoconf.h>
1328+#include <linux/sched.h>
1329+#include <linux/signal.h>
1330+#include <linux/slab.h> //memory allocate
1331+#include <linux/module.h>
1332+#include <linux/netdevice.h>
1333+#include <linux/etherdevice.h>
1334+#include <linux/init.h>//need for init and exit modules marco
1335+#include <linux/ctype.h>
1336+#include <linux/wait.h>
1337+#include <linux/list.h>
1338+#include <linux/wireless.h>
1339+#include <linux/if_arp.h>
1340+#include <asm/uaccess.h>
1341+#include <net/iw_handler.h>
1342+#include <linux/skbuff.h>
1343+
1344+
1345+//#define DEBUG_ENABLED 1
1346+
1347+
1348+
1349+//===============================================================
1350+// Common type definition
1351+//===============================================================
1352+
1353+typedef u8* PUCHAR;
1354+typedef s8* PCHAR;
1355+typedef u8* PBOOLEAN;
1356+typedef u16* PUSHORT;
1357+typedef u32* PULONG;
1358+typedef s16* PSHORT;
1359+
1360+
1361+//===========================================
1362+#define IGNORE 2
1363+#define SUCCESS 1
1364+#define FAILURE 0
1365+
1366+
1367+#ifndef true
1368+#define true 1
1369+#endif
1370+
1371+#ifndef false
1372+#define false 0
1373+#endif
1374+
1375+// PD43 20021108
1376+#ifndef TRUE
1377+#define TRUE 1
1378+#endif
1379+
1380+#ifndef FALSE
1381+#define FALSE 0
1382+#endif
1383+
1384+#define STATUS_MEDIA_CONNECT 1
1385+#define STATUS_MEDIA_DISCONNECT 0
1386+
1387+#ifndef BIT
1388+#define BIT(x) (1 << (x))
1389+#endif
1390+
1391+typedef struct urb * PURB;
1392+
1393+
1394+
1395+//==================================================================================================
1396+// Common function definition
1397+//==================================================================================================
1398+#ifndef abs
1399+#define abs(_T) ((_T) < 0 ? -_T : _T)
1400+#endif
1401+#define DEBUG_ENABLED
1402+#define ETH_LENGTH_OF_ADDRESS 6
1403+#ifdef DEBUG_ENABLED
1404+#define WBDEBUG( _M ) printk _M
1405+#else
1406+#define WBDEBUG( _M ) 0
1407+#endif
1408+
1409+#define OS_DISCONNECTED 0
1410+#define OS_CONNECTED 1
1411+
1412+
1413+#define OS_EVENT_INDICATE( _A, _B, _F )
1414+#define OS_PMKID_STATUS_EVENT( _A )
1415+
1416+
1417+/* Uff, no, longs are not atomic on all architectures Linux
1418+ * supports. This should really use atomic_t */
1419+
1420+#define OS_ATOMIC u32
1421+#define OS_ATOMIC_READ( _A, _V ) _V
1422+#define OS_ATOMIC_INC( _A, _V ) EncapAtomicInc( _A, (void*)_V )
1423+#define OS_ATOMIC_DEC( _A, _V ) EncapAtomicDec( _A, (void*)_V )
1424+#define OS_MEMORY_CLEAR( _A, _S ) memset( (PUCHAR)_A,0,_S)
1425+#define OS_MEMORY_COMPARE( _A, _B, _S ) (memcmp(_A,_B,_S)? 0 : 1) // Definition is reverse with Ndis 1: the same 0: different
1426+
1427+
1428+#define OS_SPIN_LOCK spinlock_t
1429+#define OS_SPIN_LOCK_ALLOCATE( _S ) spin_lock_init( _S );
1430+#define OS_SPIN_LOCK_FREE( _S )
1431+#define OS_SPIN_LOCK_ACQUIRED( _S ) spin_lock_irq( _S )
1432+#define OS_SPIN_LOCK_RELEASED( _S ) spin_unlock_irq( _S );
1433+
1434+#define OS_TIMER struct timer_list
1435+#define OS_TIMER_INITIAL( _T, _F, _P ) \
1436+{ \
1437+ init_timer( _T ); \
1438+ (_T)->function = (void *)_F##_1a; \
1439+ (_T)->data = (unsigned long)_P; \
1440+}
1441+
1442+// _S : Millisecond
1443+// 20060420 At least 1 large than jiffies
1444+#define OS_TIMER_SET( _T, _S ) \
1445+{ \
1446+ (_T)->expires = jiffies + ((_S*HZ+999)/1000);\
1447+ add_timer( _T ); \
1448+}
1449+#define OS_TIMER_CANCEL( _T, _B ) del_timer_sync( _T )
1450+#define OS_TIMER_GET_SYS_TIME( _T ) (*_T=jiffies)
1451+
1452+
1453+#endif // COMMON_DEF
1454+
1455diff --git a/drivers/staging/winbond/linux/sysdef.h b/drivers/staging/winbond/linux/sysdef.h
1456new file mode 100644
1457index 0000000..d46d63e
1458--- /dev/null
1459+++ b/drivers/staging/winbond/linux/sysdef.h
1460@@ -0,0 +1,73 @@
1461+
1462+
1463+//
1464+// Winbond WLAN System Configuration defines
1465+//
1466+
1467+//=====================================================================
1468+// Current directory is Linux
1469+// The definition WB_LINUX is a keyword for this OS
1470+//=====================================================================
1471+#ifndef SYS_DEF_H
1472+#define SYS_DEF_H
1473+#define WB_LINUX
1474+#define WB_LINUX_WPA_PSK
1475+
1476+
1477+//#define _IBSS_BEACON_SEQ_STICK_
1478+#define _USE_FALLBACK_RATE_
1479+//#define ANTDIV_DEFAULT_ON
1480+
1481+#define _WPA2_ // 20061122 It's needed for current Linux driver
1482+
1483+
1484+#ifndef _WPA_PSK_DEBUG
1485+#undef _WPA_PSK_DEBUG
1486+#endif
1487+
1488+// debug print options, mark what debug you don't need
1489+
1490+#ifdef FULL_DEBUG
1491+#define _PE_STATE_DUMP_
1492+#define _PE_TX_DUMP_
1493+#define _PE_RX_DUMP_
1494+#define _PE_OID_DUMP_
1495+#define _PE_DTO_DUMP_
1496+#define _PE_REG_DUMP_
1497+#define _PE_USB_INI_DUMP_
1498+#endif
1499+
1500+
1501+
1502+#include "common.h" // Individual file depends on OS
1503+
1504+#include "../wb35_ver.h"
1505+#include "../mac_structures.h"
1506+#include "../ds_tkip.h"
1507+#include "../localpara.h"
1508+#include "../sme_s.h"
1509+#include "../scan_s.h"
1510+#include "../mds_s.h"
1511+#include "../mlme_s.h"
1512+#include "../bssdscpt.h"
1513+#include "../sme_api.h"
1514+#include "../gl_80211.h"
1515+#include "../mto.h"
1516+#include "../wblinux_s.h"
1517+#include "../wbhal_s.h"
1518+
1519+
1520+#include "../adapter.h"
1521+
1522+#include "../mlme_mib.h"
1523+#include "../mds_f.h"
1524+#include "../bss_f.h"
1525+#include "../mlmetxrx_f.h"
1526+#include "../mto_f.h"
1527+#include "../wbhal_f.h"
1528+#include "../wblinux_f.h"
1529+// Kernel Timer resolution, NDIS is 10ms, 10000us
1530+#define MIN_TIMEOUT_VAL (10) //ms
1531+
1532+
1533+#endif
1534diff --git a/drivers/staging/winbond/linux/wb35reg.c b/drivers/staging/winbond/linux/wb35reg.c
1535new file mode 100644
1536index 0000000..2c0b454
1537--- /dev/null
1538+++ b/drivers/staging/winbond/linux/wb35reg.c
1539@@ -0,0 +1,747 @@
1540+#include "sysdef.h"
1541+
1542+extern void phy_calibration_winbond(hw_data_t *phw_data, u32 frequency);
1543+
1544+// TRUE : read command process successfully
1545+// FALSE : register not support
1546+// RegisterNo : start base
1547+// pRegisterData : data point
1548+// NumberOfData : number of register data
1549+// Flag : AUTO_INCREMENT - RegisterNo will auto increment 4
1550+// NO_INCREMENT - Function will write data into the same register
1551+unsigned char
1552+Wb35Reg_BurstWrite(phw_data_t pHwData, u16 RegisterNo, PULONG pRegisterData, u8 NumberOfData, u8 Flag)
1553+{
1554+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
1555+ PURB pUrb = NULL;
1556+ PREG_QUEUE pRegQueue = NULL;
1557+ u16 UrbSize;
1558+ struct usb_ctrlrequest *dr;
1559+ u16 i, DataSize = NumberOfData*4;
1560+
1561+ // Module shutdown
1562+ if (pHwData->SurpriseRemove)
1563+ return FALSE;
1564+
1565+ // Trying to use burst write function if use new hardware
1566+ UrbSize = sizeof(REG_QUEUE) + DataSize + sizeof(struct usb_ctrlrequest);
1567+ OS_MEMORY_ALLOC( (void* *)&pRegQueue, UrbSize );
1568+ pUrb = wb_usb_alloc_urb(0);
1569+ if( pUrb && pRegQueue ) {
1570+ pRegQueue->DIRECT = 2;// burst write register
1571+ pRegQueue->INDEX = RegisterNo;
1572+ pRegQueue->pBuffer = (PULONG)((PUCHAR)pRegQueue + sizeof(REG_QUEUE));
1573+ memcpy( pRegQueue->pBuffer, pRegisterData, DataSize );
1574+ //the function for reversing register data from little endian to big endian
1575+ for( i=0; i<NumberOfData ; i++ )
1576+ pRegQueue->pBuffer[i] = cpu_to_le32( pRegQueue->pBuffer[i] );
1577+
1578+ dr = (struct usb_ctrlrequest *)((PUCHAR)pRegQueue + sizeof(REG_QUEUE) + DataSize);
1579+ dr->bRequestType = USB_TYPE_VENDOR | USB_DIR_OUT | USB_RECIP_DEVICE;
1580+ dr->bRequest = 0x04; // USB or vendor-defined request code, burst mode
1581+ dr->wValue = cpu_to_le16( Flag ); // 0: Register number auto-increment, 1: No auto increment
1582+ dr->wIndex = cpu_to_le16( RegisterNo );
1583+ dr->wLength = cpu_to_le16( DataSize );
1584+ pRegQueue->Next = NULL;
1585+ pRegQueue->pUsbReq = dr;
1586+ pRegQueue->pUrb = pUrb;
1587+
1588+ OS_SPIN_LOCK_ACQUIRED( &pWb35Reg->EP0VM_spin_lock );
1589+ if (pWb35Reg->pRegFirst == NULL)
1590+ pWb35Reg->pRegFirst = pRegQueue;
1591+ else
1592+ pWb35Reg->pRegLast->Next = pRegQueue;
1593+ pWb35Reg->pRegLast = pRegQueue;
1594+
1595+ OS_SPIN_LOCK_RELEASED( &pWb35Reg->EP0VM_spin_lock );
1596+
1597+ // Start EP0VM
1598+ Wb35Reg_EP0VM_start(pHwData);
1599+
1600+ return TRUE;
1601+ } else {
1602+ if (pUrb)
1603+ usb_free_urb(pUrb);
1604+ if (pRegQueue)
1605+ kfree(pRegQueue);
1606+ return FALSE;
1607+ }
1608+ return FALSE;
1609+}
1610+
1611+void
1612+Wb35Reg_Update(phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue)
1613+{
1614+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
1615+ switch (RegisterNo) {
1616+ case 0x3b0: pWb35Reg->U1B0 = RegisterValue; break;
1617+ case 0x3bc: pWb35Reg->U1BC_LEDConfigure = RegisterValue; break;
1618+ case 0x400: pWb35Reg->D00_DmaControl = RegisterValue; break;
1619+ case 0x800: pWb35Reg->M00_MacControl = RegisterValue; break;
1620+ case 0x804: pWb35Reg->M04_MulticastAddress1 = RegisterValue; break;
1621+ case 0x808: pWb35Reg->M08_MulticastAddress2 = RegisterValue; break;
1622+ case 0x824: pWb35Reg->M24_MacControl = RegisterValue; break;
1623+ case 0x828: pWb35Reg->M28_MacControl = RegisterValue; break;
1624+ case 0x82c: pWb35Reg->M2C_MacControl = RegisterValue; break;
1625+ case 0x838: pWb35Reg->M38_MacControl = RegisterValue; break;
1626+ case 0x840: pWb35Reg->M40_MacControl = RegisterValue; break;
1627+ case 0x844: pWb35Reg->M44_MacControl = RegisterValue; break;
1628+ case 0x848: pWb35Reg->M48_MacControl = RegisterValue; break;
1629+ case 0x84c: pWb35Reg->M4C_MacStatus = RegisterValue; break;
1630+ case 0x860: pWb35Reg->M60_MacControl = RegisterValue; break;
1631+ case 0x868: pWb35Reg->M68_MacControl = RegisterValue; break;
1632+ case 0x870: pWb35Reg->M70_MacControl = RegisterValue; break;
1633+ case 0x874: pWb35Reg->M74_MacControl = RegisterValue; break;
1634+ case 0x878: pWb35Reg->M78_ERPInformation = RegisterValue; break;
1635+ case 0x87C: pWb35Reg->M7C_MacControl = RegisterValue; break;
1636+ case 0x880: pWb35Reg->M80_MacControl = RegisterValue; break;
1637+ case 0x884: pWb35Reg->M84_MacControl = RegisterValue; break;
1638+ case 0x888: pWb35Reg->M88_MacControl = RegisterValue; break;
1639+ case 0x898: pWb35Reg->M98_MacControl = RegisterValue; break;
1640+ case 0x100c: pWb35Reg->BB0C = RegisterValue; break;
1641+ case 0x102c: pWb35Reg->BB2C = RegisterValue; break;
1642+ case 0x1030: pWb35Reg->BB30 = RegisterValue; break;
1643+ case 0x103c: pWb35Reg->BB3C = RegisterValue; break;
1644+ case 0x1048: pWb35Reg->BB48 = RegisterValue; break;
1645+ case 0x104c: pWb35Reg->BB4C = RegisterValue; break;
1646+ case 0x1050: pWb35Reg->BB50 = RegisterValue; break;
1647+ case 0x1054: pWb35Reg->BB54 = RegisterValue; break;
1648+ case 0x1058: pWb35Reg->BB58 = RegisterValue; break;
1649+ case 0x105c: pWb35Reg->BB5C = RegisterValue; break;
1650+ case 0x1060: pWb35Reg->BB60 = RegisterValue; break;
1651+ }
1652+}
1653+
1654+// TRUE : read command process successfully
1655+// FALSE : register not support
1656+unsigned char
1657+Wb35Reg_WriteSync( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue )
1658+{
1659+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
1660+ int ret = -1;
1661+
1662+ // Module shutdown
1663+ if (pHwData->SurpriseRemove)
1664+ return FALSE;
1665+
1666+ RegisterValue = cpu_to_le32(RegisterValue);
1667+
1668+ // update the register by send usb message------------------------------------
1669+ pWb35Reg->SyncIoPause = 1;
1670+
1671+ // 20060717.5 Wait until EP0VM stop
1672+ while (pWb35Reg->EP0vm_state != VM_STOP)
1673+ OS_SLEEP(10000);
1674+
1675+ // Sync IoCallDriver
1676+ pWb35Reg->EP0vm_state = VM_RUNNING;
1677+ ret = usb_control_msg( pHwData->WbUsb.udev,
1678+ usb_sndctrlpipe( pHwData->WbUsb.udev, 0 ),
1679+ 0x03, USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT,
1680+ 0x0,RegisterNo, &RegisterValue, 4, HZ*100 );
1681+ pWb35Reg->EP0vm_state = VM_STOP;
1682+ pWb35Reg->SyncIoPause = 0;
1683+
1684+ Wb35Reg_EP0VM_start(pHwData);
1685+
1686+ if (ret < 0) {
1687+ #ifdef _PE_REG_DUMP_
1688+ WBDEBUG(("EP0 Write register usb message sending error\n"));
1689+ #endif
1690+
1691+ pHwData->SurpriseRemove = 1; // 20060704.2
1692+ return FALSE;
1693+ }
1694+
1695+ return TRUE;
1696+}
1697+
1698+// TRUE : read command process successfully
1699+// FALSE : register not support
1700+unsigned char
1701+Wb35Reg_Write( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue )
1702+{
1703+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
1704+ struct usb_ctrlrequest *dr;
1705+ PURB pUrb = NULL;
1706+ PREG_QUEUE pRegQueue = NULL;
1707+ u16 UrbSize;
1708+
1709+
1710+ // Module shutdown
1711+ if (pHwData->SurpriseRemove)
1712+ return FALSE;
1713+
1714+ // update the register by send urb request------------------------------------
1715+ UrbSize = sizeof(REG_QUEUE) + sizeof(struct usb_ctrlrequest);
1716+ OS_MEMORY_ALLOC( (void* *)&pRegQueue, UrbSize );
1717+ pUrb = wb_usb_alloc_urb(0);
1718+ if (pUrb && pRegQueue) {
1719+ pRegQueue->DIRECT = 1;// burst write register
1720+ pRegQueue->INDEX = RegisterNo;
1721+ pRegQueue->VALUE = cpu_to_le32(RegisterValue);
1722+ pRegQueue->RESERVED_VALID = FALSE;
1723+ dr = (struct usb_ctrlrequest *)((PUCHAR)pRegQueue + sizeof(REG_QUEUE));
1724+ dr->bRequestType = USB_TYPE_VENDOR|USB_DIR_OUT |USB_RECIP_DEVICE;
1725+ dr->bRequest = 0x03; // USB or vendor-defined request code, burst mode
1726+ dr->wValue = cpu_to_le16(0x0);
1727+ dr->wIndex = cpu_to_le16(RegisterNo);
1728+ dr->wLength = cpu_to_le16(4);
1729+
1730+ // Enter the sending queue
1731+ pRegQueue->Next = NULL;
1732+ pRegQueue->pUsbReq = dr;
1733+ pRegQueue->pUrb = pUrb;
1734+
1735+ OS_SPIN_LOCK_ACQUIRED(&pWb35Reg->EP0VM_spin_lock );
1736+ if (pWb35Reg->pRegFirst == NULL)
1737+ pWb35Reg->pRegFirst = pRegQueue;
1738+ else
1739+ pWb35Reg->pRegLast->Next = pRegQueue;
1740+ pWb35Reg->pRegLast = pRegQueue;
1741+
1742+ OS_SPIN_LOCK_RELEASED( &pWb35Reg->EP0VM_spin_lock );
1743+
1744+ // Start EP0VM
1745+ Wb35Reg_EP0VM_start(pHwData);
1746+
1747+ return TRUE;
1748+ } else {
1749+ if (pUrb)
1750+ usb_free_urb(pUrb);
1751+ kfree(pRegQueue);
1752+ return FALSE;
1753+ }
1754+}
1755+
1756+//This command will be executed with a user defined value. When it completes,
1757+//this value is useful. For example, hal_set_current_channel will use it.
1758+// TRUE : read command process successfully
1759+// FALSE : register not support
1760+unsigned char
1761+Wb35Reg_WriteWithCallbackValue( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue,
1762+ PCHAR pValue, s8 Len)
1763+{
1764+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
1765+ struct usb_ctrlrequest *dr;
1766+ PURB pUrb = NULL;
1767+ PREG_QUEUE pRegQueue = NULL;
1768+ u16 UrbSize;
1769+
1770+ // Module shutdown
1771+ if (pHwData->SurpriseRemove)
1772+ return FALSE;
1773+
1774+ // update the register by send urb request------------------------------------
1775+ UrbSize = sizeof(REG_QUEUE) + sizeof(struct usb_ctrlrequest);
1776+ OS_MEMORY_ALLOC((void* *) &pRegQueue, UrbSize );
1777+ pUrb = wb_usb_alloc_urb(0);
1778+ if (pUrb && pRegQueue) {
1779+ pRegQueue->DIRECT = 1;// burst write register
1780+ pRegQueue->INDEX = RegisterNo;
1781+ pRegQueue->VALUE = cpu_to_le32(RegisterValue);
1782+ //NOTE : Users must guarantee the size of value will not exceed the buffer size.
1783+ memcpy(pRegQueue->RESERVED, pValue, Len);
1784+ pRegQueue->RESERVED_VALID = TRUE;
1785+ dr = (struct usb_ctrlrequest *)((PUCHAR)pRegQueue + sizeof(REG_QUEUE));
1786+ dr->bRequestType = USB_TYPE_VENDOR|USB_DIR_OUT |USB_RECIP_DEVICE;
1787+ dr->bRequest = 0x03; // USB or vendor-defined request code, burst mode
1788+ dr->wValue = cpu_to_le16(0x0);
1789+ dr->wIndex = cpu_to_le16(RegisterNo);
1790+ dr->wLength = cpu_to_le16(4);
1791+
1792+ // Enter the sending queue
1793+ pRegQueue->Next = NULL;
1794+ pRegQueue->pUsbReq = dr;
1795+ pRegQueue->pUrb = pUrb;
1796+ OS_SPIN_LOCK_ACQUIRED (&pWb35Reg->EP0VM_spin_lock );
1797+ if( pWb35Reg->pRegFirst == NULL )
1798+ pWb35Reg->pRegFirst = pRegQueue;
1799+ else
1800+ pWb35Reg->pRegLast->Next = pRegQueue;
1801+ pWb35Reg->pRegLast = pRegQueue;
1802+
1803+ OS_SPIN_LOCK_RELEASED ( &pWb35Reg->EP0VM_spin_lock );
1804+
1805+ // Start EP0VM
1806+ Wb35Reg_EP0VM_start(pHwData);
1807+ return TRUE;
1808+ } else {
1809+ if (pUrb)
1810+ usb_free_urb(pUrb);
1811+ kfree(pRegQueue);
1812+ return FALSE;
1813+ }
1814+}
1815+
1816+// TRUE : read command process successfully
1817+// FALSE : register not support
1818+// pRegisterValue : It must be a resident buffer due to asynchronous read register.
1819+unsigned char
1820+Wb35Reg_ReadSync( phw_data_t pHwData, u16 RegisterNo, PULONG pRegisterValue )
1821+{
1822+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
1823+ PULONG pltmp = pRegisterValue;
1824+ int ret = -1;
1825+
1826+ // Module shutdown
1827+ if (pHwData->SurpriseRemove)
1828+ return FALSE;
1829+
1830+ // Read the register by send usb message------------------------------------
1831+
1832+ pWb35Reg->SyncIoPause = 1;
1833+
1834+ // 20060717.5 Wait until EP0VM stop
1835+ while (pWb35Reg->EP0vm_state != VM_STOP)
1836+ OS_SLEEP(10000);
1837+
1838+ pWb35Reg->EP0vm_state = VM_RUNNING;
1839+ ret = usb_control_msg( pHwData->WbUsb.udev,
1840+ usb_rcvctrlpipe(pHwData->WbUsb.udev, 0),
1841+ 0x01, USB_TYPE_VENDOR|USB_RECIP_DEVICE|USB_DIR_IN,
1842+ 0x0, RegisterNo, pltmp, 4, HZ*100 );
1843+
1844+ *pRegisterValue = cpu_to_le32(*pltmp);
1845+
1846+ pWb35Reg->EP0vm_state = VM_STOP;
1847+
1848+ Wb35Reg_Update( pHwData, RegisterNo, *pRegisterValue );
1849+ pWb35Reg->SyncIoPause = 0;
1850+
1851+ Wb35Reg_EP0VM_start( pHwData );
1852+
1853+ if (ret < 0) {
1854+ #ifdef _PE_REG_DUMP_
1855+ WBDEBUG(("EP0 Read register usb message sending error\n"));
1856+ #endif
1857+
1858+ pHwData->SurpriseRemove = 1; // 20060704.2
1859+ return FALSE;
1860+ }
1861+
1862+ return TRUE;
1863+}
1864+
1865+// TRUE : read command process successfully
1866+// FALSE : register not support
1867+// pRegisterValue : It must be a resident buffer due to asynchronous read register.
1868+unsigned char
1869+Wb35Reg_Read(phw_data_t pHwData, u16 RegisterNo, PULONG pRegisterValue )
1870+{
1871+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
1872+ struct usb_ctrlrequest * dr;
1873+ PURB pUrb;
1874+ PREG_QUEUE pRegQueue;
1875+ u16 UrbSize;
1876+
1877+ // Module shutdown
1878+ if (pHwData->SurpriseRemove)
1879+ return FALSE;
1880+
1881+ // update the variable by send Urb to read register ------------------------------------
1882+ UrbSize = sizeof(REG_QUEUE) + sizeof(struct usb_ctrlrequest);
1883+ OS_MEMORY_ALLOC( (void* *)&pRegQueue, UrbSize );
1884+ pUrb = wb_usb_alloc_urb(0);
1885+ if( pUrb && pRegQueue )
1886+ {
1887+ pRegQueue->DIRECT = 0;// read register
1888+ pRegQueue->INDEX = RegisterNo;
1889+ pRegQueue->pBuffer = pRegisterValue;
1890+ dr = (struct usb_ctrlrequest *)((PUCHAR)pRegQueue + sizeof(REG_QUEUE));
1891+ dr->bRequestType = USB_TYPE_VENDOR|USB_RECIP_DEVICE|USB_DIR_IN;
1892+ dr->bRequest = 0x01; // USB or vendor-defined request code, burst mode
1893+ dr->wValue = cpu_to_le16(0x0);
1894+ dr->wIndex = cpu_to_le16 (RegisterNo);
1895+ dr->wLength = cpu_to_le16 (4);
1896+
1897+ // Enter the sending queue
1898+ pRegQueue->Next = NULL;
1899+ pRegQueue->pUsbReq = dr;
1900+ pRegQueue->pUrb = pUrb;
1901+ OS_SPIN_LOCK_ACQUIRED ( &pWb35Reg->EP0VM_spin_lock );
1902+ if( pWb35Reg->pRegFirst == NULL )
1903+ pWb35Reg->pRegFirst = pRegQueue;
1904+ else
1905+ pWb35Reg->pRegLast->Next = pRegQueue;
1906+ pWb35Reg->pRegLast = pRegQueue;
1907+
1908+ OS_SPIN_LOCK_RELEASED( &pWb35Reg->EP0VM_spin_lock );
1909+
1910+ // Start EP0VM
1911+ Wb35Reg_EP0VM_start( pHwData );
1912+
1913+ return TRUE;
1914+ } else {
1915+ if (pUrb)
1916+ usb_free_urb( pUrb );
1917+ kfree(pRegQueue);
1918+ return FALSE;
1919+ }
1920+}
1921+
1922+
1923+void
1924+Wb35Reg_EP0VM_start( phw_data_t pHwData )
1925+{
1926+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
1927+
1928+ if (OS_ATOMIC_INC( pHwData->Adapter, &pWb35Reg->RegFireCount) == 1) {
1929+ pWb35Reg->EP0vm_state = VM_RUNNING;
1930+ Wb35Reg_EP0VM(pHwData);
1931+ } else
1932+ OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Reg->RegFireCount );
1933+}
1934+
1935+void
1936+Wb35Reg_EP0VM(phw_data_t pHwData )
1937+{
1938+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
1939+ PURB pUrb;
1940+ struct usb_ctrlrequest *dr;
1941+ PULONG pBuffer;
1942+ int ret = -1;
1943+ PREG_QUEUE pRegQueue;
1944+
1945+
1946+ if (pWb35Reg->SyncIoPause)
1947+ goto cleanup;
1948+
1949+ if (pHwData->SurpriseRemove)
1950+ goto cleanup;
1951+
1952+ // Get the register data and send to USB through Irp
1953+ OS_SPIN_LOCK_ACQUIRED( &pWb35Reg->EP0VM_spin_lock );
1954+ pRegQueue = pWb35Reg->pRegFirst;
1955+ OS_SPIN_LOCK_RELEASED( &pWb35Reg->EP0VM_spin_lock );
1956+
1957+ if (!pRegQueue)
1958+ goto cleanup;
1959+
1960+ // Get an Urb, send it
1961+ pUrb = (PURB)pRegQueue->pUrb;
1962+
1963+ dr = pRegQueue->pUsbReq;
1964+ pUrb = pRegQueue->pUrb;
1965+ pBuffer = pRegQueue->pBuffer;
1966+ if (pRegQueue->DIRECT == 1) // output
1967+ pBuffer = &pRegQueue->VALUE;
1968+
1969+ usb_fill_control_urb( pUrb, pHwData->WbUsb.udev,
1970+ REG_DIRECTION(pHwData->WbUsb.udev,pRegQueue),
1971+ (PUCHAR)dr,pBuffer,cpu_to_le16(dr->wLength),
1972+ Wb35Reg_EP0VM_complete, (void*)pHwData);
1973+
1974+ pWb35Reg->EP0vm_state = VM_RUNNING;
1975+
1976+ ret = wb_usb_submit_urb( pUrb );
1977+
1978+ if (ret < 0) {
1979+#ifdef _PE_REG_DUMP_
1980+ WBDEBUG(("EP0 Irp sending error\n"));
1981+#endif
1982+ goto cleanup;
1983+ }
1984+
1985+ return;
1986+
1987+ cleanup:
1988+ pWb35Reg->EP0vm_state = VM_STOP;
1989+ OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Reg->RegFireCount );
1990+}
1991+
1992+
1993+void
1994+Wb35Reg_EP0VM_complete(PURB pUrb)
1995+{
1996+ phw_data_t pHwData = (phw_data_t)pUrb->context;
1997+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
1998+ PREG_QUEUE pRegQueue;
1999+
2000+
2001+ // Variable setting
2002+ pWb35Reg->EP0vm_state = VM_COMPLETED;
2003+ pWb35Reg->EP0VM_status = pUrb->status;
2004+
2005+ if (pHwData->SurpriseRemove) { // Let WbWlanHalt to handle surprise remove
2006+ pWb35Reg->EP0vm_state = VM_STOP;
2007+ OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Reg->RegFireCount );
2008+ } else {
2009+ // Complete to send, remove the URB from the first
2010+ OS_SPIN_LOCK_ACQUIRED( &pWb35Reg->EP0VM_spin_lock );
2011+ pRegQueue = pWb35Reg->pRegFirst;
2012+ if (pRegQueue == pWb35Reg->pRegLast)
2013+ pWb35Reg->pRegLast = NULL;
2014+ pWb35Reg->pRegFirst = pWb35Reg->pRegFirst->Next;
2015+ OS_SPIN_LOCK_RELEASED( &pWb35Reg->EP0VM_spin_lock );
2016+
2017+ if (pWb35Reg->EP0VM_status) {
2018+#ifdef _PE_REG_DUMP_
2019+ WBDEBUG(("EP0 IoCompleteRoutine return error\n"));
2020+ DebugUsbdStatusInformation( pWb35Reg->EP0VM_status );
2021+#endif
2022+ pWb35Reg->EP0vm_state = VM_STOP;
2023+ pHwData->SurpriseRemove = 1;
2024+ } else {
2025+ // Success. Update the result
2026+
2027+ // Start the next send
2028+ Wb35Reg_EP0VM(pHwData);
2029+ }
2030+
2031+ kfree(pRegQueue);
2032+ }
2033+
2034+ usb_free_urb(pUrb);
2035+}
2036+
2037+
2038+void
2039+Wb35Reg_destroy(phw_data_t pHwData)
2040+{
2041+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
2042+ PURB pUrb;
2043+ PREG_QUEUE pRegQueue;
2044+
2045+
2046+ Uxx_power_off_procedure(pHwData);
2047+
2048+ // Wait for Reg operation completed
2049+ do {
2050+ OS_SLEEP(10000); // Delay for waiting function enter 940623.1.a
2051+ } while (pWb35Reg->EP0vm_state != VM_STOP);
2052+ OS_SLEEP(10000); // Delay for waiting function enter 940623.1.b
2053+
2054+ // Release all the data in RegQueue
2055+ OS_SPIN_LOCK_ACQUIRED( &pWb35Reg->EP0VM_spin_lock );
2056+ pRegQueue = pWb35Reg->pRegFirst;
2057+ while (pRegQueue) {
2058+ if (pRegQueue == pWb35Reg->pRegLast)
2059+ pWb35Reg->pRegLast = NULL;
2060+ pWb35Reg->pRegFirst = pWb35Reg->pRegFirst->Next;
2061+
2062+ pUrb = pRegQueue->pUrb;
2063+ OS_SPIN_LOCK_RELEASED( &pWb35Reg->EP0VM_spin_lock );
2064+ if (pUrb) {
2065+ usb_free_urb(pUrb);
2066+ kfree(pRegQueue);
2067+ } else {
2068+ #ifdef _PE_REG_DUMP_
2069+ WBDEBUG(("EP0 queue release error\n"));
2070+ #endif
2071+ }
2072+ OS_SPIN_LOCK_ACQUIRED( &pWb35Reg->EP0VM_spin_lock );
2073+
2074+ pRegQueue = pWb35Reg->pRegFirst;
2075+ }
2076+ OS_SPIN_LOCK_RELEASED( &pWb35Reg->EP0VM_spin_lock );
2077+
2078+ // Free resource
2079+ OS_SPIN_LOCK_FREE( &pWb35Reg->EP0VM_spin_lock );
2080+}
2081+
2082+//====================================================================================
2083+// The function can be run in passive-level only.
2084+//====================================================================================
2085+unsigned char Wb35Reg_initial(phw_data_t pHwData)
2086+{
2087+ PWB35REG pWb35Reg=&pHwData->Wb35Reg;
2088+ u32 ltmp;
2089+ u32 SoftwareSet, VCO_trim, TxVga, Region_ScanInterval;
2090+
2091+ // Spin lock is acquired for read and write IRP command
2092+ OS_SPIN_LOCK_ALLOCATE( &pWb35Reg->EP0VM_spin_lock );
2093+
2094+ // Getting RF module type from EEPROM ------------------------------------
2095+ Wb35Reg_WriteSync( pHwData, 0x03b4, 0x080d0000 ); // Start EEPROM access + Read + address(0x0d)
2096+ Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp );
2097+
2098+ //Update RF module type and determine the PHY type by inf or EEPROM
2099+ pWb35Reg->EEPROMPhyType = (u8)( ltmp & 0xff );
2100+ // 0 V MAX2825, 1 V MAX2827, 2 V MAX2828, 3 V MAX2829
2101+ // 16V AL2230, 17 - AL7230, 18 - AL2230S
2102+ // 32 Reserved
2103+ // 33 - W89RF242(TxVGA 0~19), 34 - W89RF242(TxVGA 0~34)
2104+ if (pWb35Reg->EEPROMPhyType != RF_DECIDE_BY_INF) {
2105+ if( (pWb35Reg->EEPROMPhyType == RF_MAXIM_2825) ||
2106+ (pWb35Reg->EEPROMPhyType == RF_MAXIM_2827) ||
2107+ (pWb35Reg->EEPROMPhyType == RF_MAXIM_2828) ||
2108+ (pWb35Reg->EEPROMPhyType == RF_MAXIM_2829) ||
2109+ (pWb35Reg->EEPROMPhyType == RF_MAXIM_V1) ||
2110+ (pWb35Reg->EEPROMPhyType == RF_AIROHA_2230) ||
2111+ (pWb35Reg->EEPROMPhyType == RF_AIROHA_2230S) ||
2112+ (pWb35Reg->EEPROMPhyType == RF_AIROHA_7230) ||
2113+ (pWb35Reg->EEPROMPhyType == RF_WB_242) ||
2114+ (pWb35Reg->EEPROMPhyType == RF_WB_242_1))
2115+ pHwData->phy_type = pWb35Reg->EEPROMPhyType;
2116+ }
2117+
2118+ // Power On procedure running. The relative parameter will be set according to phy_type
2119+ Uxx_power_on_procedure( pHwData );
2120+
2121+ // Reading MAC address
2122+ Uxx_ReadEthernetAddress( pHwData );
2123+
2124+ // Read VCO trim for RF parameter
2125+ Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08200000 );
2126+ Wb35Reg_ReadSync( pHwData, 0x03b4, &VCO_trim );
2127+
2128+ // Read Antenna On/Off of software flag
2129+ Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08210000 );
2130+ Wb35Reg_ReadSync( pHwData, 0x03b4, &SoftwareSet );
2131+
2132+ // Read TXVGA
2133+ Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08100000 );
2134+ Wb35Reg_ReadSync( pHwData, 0x03b4, &TxVga );
2135+
2136+ // Get Scan interval setting from EEPROM offset 0x1c
2137+ Wb35Reg_WriteSync( pHwData, 0x03b4, 0x081d0000 );
2138+ Wb35Reg_ReadSync( pHwData, 0x03b4, &Region_ScanInterval );
2139+
2140+ // Update Ethernet address
2141+ memcpy( pHwData->CurrentMacAddress, pHwData->PermanentMacAddress, ETH_LENGTH_OF_ADDRESS );
2142+
2143+ // Update software variable
2144+ pHwData->SoftwareSet = (u16)(SoftwareSet & 0xffff);
2145+ TxVga &= 0x000000ff;
2146+ pHwData->PowerIndexFromEEPROM = (u8)TxVga;
2147+ pHwData->VCO_trim = (u8)VCO_trim & 0xff;
2148+ if (pHwData->VCO_trim == 0xff)
2149+ pHwData->VCO_trim = 0x28;
2150+
2151+ pWb35Reg->EEPROMRegion = (u8)(Region_ScanInterval>>8); // 20060720
2152+ if( pWb35Reg->EEPROMRegion<1 || pWb35Reg->EEPROMRegion>6 )
2153+ pWb35Reg->EEPROMRegion = REGION_AUTO;
2154+
2155+ //For Get Tx VGA from EEPROM 20060315.5 move here
2156+ GetTxVgaFromEEPROM( pHwData );
2157+
2158+ // Set Scan Interval
2159+ pHwData->Scan_Interval = (u8)(Region_ScanInterval & 0xff) * 10;
2160+ if ((pHwData->Scan_Interval == 2550) || (pHwData->Scan_Interval < 10)) // Is default setting 0xff * 10
2161+ pHwData->Scan_Interval = SCAN_MAX_CHNL_TIME;
2162+
2163+ // Initial register
2164+ RFSynthesizer_initial(pHwData);
2165+
2166+ BBProcessor_initial(pHwData); // Async write, must wait until complete
2167+
2168+ Wb35Reg_phy_calibration(pHwData);
2169+
2170+ Mxx_initial(pHwData);
2171+ Dxx_initial(pHwData);
2172+
2173+ if (pHwData->SurpriseRemove)
2174+ return FALSE;
2175+ else
2176+ return TRUE; // Initial fail
2177+}
2178+
2179+//===================================================================================
2180+// CardComputeCrc --
2181+//
2182+// Description:
2183+// Runs the AUTODIN II CRC algorithm on buffer Buffer of length, Length.
2184+//
2185+// Arguments:
2186+// Buffer - the input buffer
2187+// Length - the length of Buffer
2188+//
2189+// Return Value:
2190+// The 32-bit CRC value.
2191+//
2192+// Note:
2193+// This is adapted from the comments in the assembly language
2194+// version in _GENREQ.ASM of the DWB NE1000/2000 driver.
2195+//==================================================================================
2196+u32
2197+CardComputeCrc(PUCHAR Buffer, u32 Length)
2198+{
2199+ u32 Crc, Carry;
2200+ u32 i, j;
2201+ u8 CurByte;
2202+
2203+ Crc = 0xffffffff;
2204+
2205+ for (i = 0; i < Length; i++) {
2206+
2207+ CurByte = Buffer[i];
2208+
2209+ for (j = 0; j < 8; j++) {
2210+
2211+ Carry = ((Crc & 0x80000000) ? 1 : 0) ^ (CurByte & 0x01);
2212+ Crc <<= 1;
2213+ CurByte >>= 1;
2214+
2215+ if (Carry) {
2216+ Crc =(Crc ^ 0x04c11db6) | Carry;
2217+ }
2218+ }
2219+ }
2220+
2221+ return Crc;
2222+}
2223+
2224+
2225+//==================================================================
2226+// BitReverse --
2227+// Reverse the bits in the input argument, dwData, which is
2228+// regarded as a string of bits with the length, DataLength.
2229+//
2230+// Arguments:
2231+// dwData :
2232+// DataLength :
2233+//
2234+// Return:
2235+// The converted value.
2236+//==================================================================
2237+u32 BitReverse( u32 dwData, u32 DataLength)
2238+{
2239+ u32 HalfLength, i, j;
2240+ u32 BitA, BitB;
2241+
2242+ if ( DataLength <= 0) return 0; // No conversion is done.
2243+ dwData = dwData & (0xffffffff >> (32 - DataLength));
2244+
2245+ HalfLength = DataLength / 2;
2246+ for ( i = 0, j = DataLength-1 ; i < HalfLength; i++, j--)
2247+ {
2248+ BitA = GetBit( dwData, i);
2249+ BitB = GetBit( dwData, j);
2250+ if (BitA && !BitB) {
2251+ dwData = ClearBit( dwData, i);
2252+ dwData = SetBit( dwData, j);
2253+ } else if (!BitA && BitB) {
2254+ dwData = SetBit( dwData, i);
2255+ dwData = ClearBit( dwData, j);
2256+ } else
2257+ {
2258+ // Do nothing since these two bits are of the save values.
2259+ }
2260+ }
2261+
2262+ return dwData;
2263+}
2264+
2265+void Wb35Reg_phy_calibration( phw_data_t pHwData )
2266+{
2267+ u32 BB3c, BB54;
2268+
2269+ if ((pHwData->phy_type == RF_WB_242) ||
2270+ (pHwData->phy_type == RF_WB_242_1)) {
2271+ phy_calibration_winbond ( pHwData, 2412 ); // Sync operation
2272+ Wb35Reg_ReadSync( pHwData, 0x103c, &BB3c );
2273+ Wb35Reg_ReadSync( pHwData, 0x1054, &BB54 );
2274+
2275+ pHwData->BB3c_cal = BB3c;
2276+ pHwData->BB54_cal = BB54;
2277+
2278+ RFSynthesizer_initial(pHwData);
2279+ BBProcessor_initial(pHwData); // Async operation
2280+
2281+ Wb35Reg_WriteSync( pHwData, 0x103c, BB3c );
2282+ Wb35Reg_WriteSync( pHwData, 0x1054, BB54 );
2283+ }
2284+}
2285+
2286+
2287diff --git a/drivers/staging/winbond/linux/wb35reg_f.h b/drivers/staging/winbond/linux/wb35reg_f.h
2288new file mode 100644
2289index 0000000..38e2906
2290--- /dev/null
2291+++ b/drivers/staging/winbond/linux/wb35reg_f.h
2292@@ -0,0 +1,56 @@
2293+//====================================
2294+// Interface function declare
2295+//====================================
2296+unsigned char Wb35Reg_initial( phw_data_t pHwData );
2297+void Uxx_power_on_procedure( phw_data_t pHwData );
2298+void Uxx_power_off_procedure( phw_data_t pHwData );
2299+void Uxx_ReadEthernetAddress( phw_data_t pHwData );
2300+void Dxx_initial( phw_data_t pHwData );
2301+void Mxx_initial( phw_data_t pHwData );
2302+void RFSynthesizer_initial( phw_data_t pHwData );
2303+//void RFSynthesizer_SwitchingChannel( phw_data_t pHwData, s8 Channel );
2304+void RFSynthesizer_SwitchingChannel( phw_data_t pHwData, ChanInfo Channel );
2305+void BBProcessor_initial( phw_data_t pHwData );
2306+void BBProcessor_RateChanging( phw_data_t pHwData, u8 rate ); // 20060613.1
2307+//void RF_RateChanging( phw_data_t pHwData, u8 rate ); // 20060626.5.c Add
2308+u8 RFSynthesizer_SetPowerIndex( phw_data_t pHwData, u8 PowerIndex );
2309+u8 RFSynthesizer_SetMaxim2828_24Power( phw_data_t, u8 index );
2310+u8 RFSynthesizer_SetMaxim2828_50Power( phw_data_t, u8 index );
2311+u8 RFSynthesizer_SetMaxim2827_24Power( phw_data_t, u8 index );
2312+u8 RFSynthesizer_SetMaxim2827_50Power( phw_data_t, u8 index );
2313+u8 RFSynthesizer_SetMaxim2825Power( phw_data_t, u8 index );
2314+u8 RFSynthesizer_SetAiroha2230Power( phw_data_t, u8 index );
2315+u8 RFSynthesizer_SetAiroha7230Power( phw_data_t, u8 index );
2316+u8 RFSynthesizer_SetWinbond242Power( phw_data_t, u8 index );
2317+void GetTxVgaFromEEPROM( phw_data_t pHwData );
2318+void EEPROMTxVgaAdjust( phw_data_t pHwData ); // 20060619.5 Add
2319+
2320+#define RFWriteControlData( _A, _V ) Wb35Reg_Write( _A, 0x0864, _V )
2321+
2322+void Wb35Reg_destroy( phw_data_t pHwData );
2323+
2324+unsigned char Wb35Reg_Read( phw_data_t pHwData, u16 RegisterNo, PULONG pRegisterValue );
2325+unsigned char Wb35Reg_ReadSync( phw_data_t pHwData, u16 RegisterNo, PULONG pRegisterValue );
2326+unsigned char Wb35Reg_Write( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue );
2327+unsigned char Wb35Reg_WriteSync( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue );
2328+unsigned char Wb35Reg_WriteWithCallbackValue( phw_data_t pHwData,
2329+ u16 RegisterNo,
2330+ u32 RegisterValue,
2331+ PCHAR pValue,
2332+ s8 Len);
2333+unsigned char Wb35Reg_BurstWrite( phw_data_t pHwData, u16 RegisterNo, PULONG pRegisterData, u8 NumberOfData, u8 Flag );
2334+
2335+void Wb35Reg_EP0VM( phw_data_t pHwData );
2336+void Wb35Reg_EP0VM_start( phw_data_t pHwData );
2337+void Wb35Reg_EP0VM_complete( PURB pUrb );
2338+
2339+u32 BitReverse( u32 dwData, u32 DataLength);
2340+
2341+void CardGetMulticastBit( u8 Address[MAC_ADDR_LENGTH], u8 *Byte, u8 *Value );
2342+u32 CardComputeCrc( PUCHAR Buffer, u32 Length );
2343+
2344+void Wb35Reg_phy_calibration( phw_data_t pHwData );
2345+void Wb35Reg_Update( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue );
2346+unsigned char adjust_TXVGA_for_iq_mag( phw_data_t pHwData );
2347+
2348+
2349diff --git a/drivers/staging/winbond/linux/wb35reg_s.h b/drivers/staging/winbond/linux/wb35reg_s.h
2350new file mode 100644
2351index 0000000..a7595b1
2352--- /dev/null
2353+++ b/drivers/staging/winbond/linux/wb35reg_s.h
2354@@ -0,0 +1,170 @@
2355+//=======================================================================================
2356+/*
2357+ HAL setting function
2358+
2359+ ========================================
2360+ |Uxx| |Dxx| |Mxx| |BB| |RF|
2361+ ========================================
2362+ | |
2363+ Wb35Reg_Read Wb35Reg_Write
2364+
2365+ ----------------------------------------
2366+ WbUsb_CallUSBDASync supplied By WbUsb module
2367+*/
2368+//=======================================================================================
2369+
2370+#define GetBit( dwData, i) ( dwData & (0x00000001 << i))
2371+#define SetBit( dwData, i) ( dwData | (0x00000001 << i))
2372+#define ClearBit( dwData, i) ( dwData & ~(0x00000001 << i))
2373+
2374+#define IGNORE_INCREMENT 0
2375+#define AUTO_INCREMENT 0
2376+#define NO_INCREMENT 1
2377+#define REG_DIRECTION(_x,_y) ((_y)->DIRECT ==0 ? usb_rcvctrlpipe(_x,0) : usb_sndctrlpipe(_x,0))
2378+#define REG_BUF_SIZE(_x) ((_x)->bRequest== 0x04 ? cpu_to_le16((_x)->wLength) : 4)
2379+
2380+// 20060613.2 Add the follow definition
2381+#define BB48_DEFAULT_AL2230_11B 0x0033447c
2382+#define BB4C_DEFAULT_AL2230_11B 0x0A00FEFF
2383+#define BB48_DEFAULT_AL2230_11G 0x00332C1B
2384+#define BB4C_DEFAULT_AL2230_11G 0x0A00FEFF
2385+
2386+
2387+#define BB48_DEFAULT_WB242_11B 0x00292315 //backoff 2dB
2388+#define BB4C_DEFAULT_WB242_11B 0x0800FEFF //backoff 2dB
2389+//#define BB48_DEFAULT_WB242_11B 0x00201B11 //backoff 4dB
2390+//#define BB4C_DEFAULT_WB242_11B 0x0600FF00 //backoff 4dB
2391+#define BB48_DEFAULT_WB242_11G 0x00453B24
2392+#define BB4C_DEFAULT_WB242_11G 0x0E00FEFF
2393+
2394+//====================================
2395+// Default setting for Mxx
2396+//====================================
2397+#define DEFAULT_CWMIN 31 //(M2C) CWmin. Its value is in the range 0-31.
2398+#define DEFAULT_CWMAX 1023 //(M2C) CWmax. Its value is in the range 0-1023.
2399+#define DEFAULT_AID 1 //(M34) AID. Its value is in the range 1-2007.
2400+
2401+#ifdef _USE_FALLBACK_RATE_
2402+#define DEFAULT_RATE_RETRY_LIMIT 2 //(M38) as named
2403+#else
2404+#define DEFAULT_RATE_RETRY_LIMIT 7 //(M38) as named
2405+#endif
2406+
2407+#define DEFAULT_LONG_RETRY_LIMIT 7 //(M38) LongRetryLimit. Its value is in the range 0-15.
2408+#define DEFAULT_SHORT_RETRY_LIMIT 7 //(M38) ShortRetryLimit. Its value is in the range 0-15.
2409+#define DEFAULT_PIFST 25 //(M3C) PIFS Time. Its value is in the range 0-65535.
2410+#define DEFAULT_EIFST 354 //(M3C) EIFS Time. Its value is in the range 0-1048575.
2411+#define DEFAULT_DIFST 45 //(M3C) DIFS Time. Its value is in the range 0-65535.
2412+#define DEFAULT_SIFST 5 //(M3C) SIFS Time. Its value is in the range 0-65535.
2413+#define DEFAULT_OSIFST 10 //(M3C) Original SIFS Time. Its value is in the range 0-15.
2414+#define DEFAULT_ATIMWD 0 //(M40) ATIM Window. Its value is in the range 0-65535.
2415+#define DEFAULT_SLOT_TIME 20 //(M40) ($) SlotTime. Its value is in the range 0-255.
2416+#define DEFAULT_MAX_TX_MSDU_LIFE_TIME 512 //(M44) MaxTxMSDULifeTime. Its value is in the range 0-4294967295.
2417+#define DEFAULT_BEACON_INTERVAL 500 //(M48) Beacon Interval. Its value is in the range 0-65535.
2418+#define DEFAULT_PROBE_DELAY_TIME 200 //(M48) Probe Delay Time. Its value is in the range 0-65535.
2419+#define DEFAULT_PROTOCOL_VERSION 0 //(M4C)
2420+#define DEFAULT_MAC_POWER_STATE 2 //(M4C) 2: MAC at power active
2421+#define DEFAULT_DTIM_ALERT_TIME 0
2422+
2423+
2424+typedef struct _REG_QUEUE
2425+{
2426+ struct urb *pUrb;
2427+ void* pUsbReq;
2428+ void* Next;
2429+ union
2430+ {
2431+ u32 VALUE;
2432+ PULONG pBuffer;
2433+ };
2434+ u8 RESERVED[4];// space reserved for communication
2435+
2436+ u16 INDEX; // For storing the register index
2437+ u8 RESERVED_VALID; //Indicate whether the RESERVED space is valid at this command.
2438+ u8 DIRECT; // 0:In 1:Out
2439+
2440+} REG_QUEUE, *PREG_QUEUE;
2441+
2442+//====================================
2443+// Internal variable for module
2444+//====================================
2445+#define MAX_SQ3_FILTER_SIZE 5
2446+typedef struct _WB35REG
2447+{
2448+ //============================
2449+ // Register Bank backup
2450+ //============================
2451+ u32 U1B0; //bit16 record the h/w radio on/off status
2452+ u32 U1BC_LEDConfigure;
2453+ u32 D00_DmaControl;
2454+ u32 M00_MacControl;
2455+ union {
2456+ struct {
2457+ u32 M04_MulticastAddress1;
2458+ u32 M08_MulticastAddress2;
2459+ };
2460+ u8 Multicast[8]; // contents of card multicast registers
2461+ };
2462+
2463+ u32 M24_MacControl;
2464+ u32 M28_MacControl;
2465+ u32 M2C_MacControl;
2466+ u32 M38_MacControl;
2467+ u32 M3C_MacControl; // 20060214 backup only
2468+ u32 M40_MacControl;
2469+ u32 M44_MacControl; // 20060214 backup only
2470+ u32 M48_MacControl; // 20060214 backup only
2471+ u32 M4C_MacStatus;
2472+ u32 M60_MacControl; // 20060214 backup only
2473+ u32 M68_MacControl; // 20060214 backup only
2474+ u32 M70_MacControl; // 20060214 backup only
2475+ u32 M74_MacControl; // 20060214 backup only
2476+ u32 M78_ERPInformation;//930206.2.b
2477+ u32 M7C_MacControl; // 20060214 backup only
2478+ u32 M80_MacControl; // 20060214 backup only
2479+ u32 M84_MacControl; // 20060214 backup only
2480+ u32 M88_MacControl; // 20060214 backup only
2481+ u32 M98_MacControl; // 20060214 backup only
2482+
2483+ //[20040722 WK]
2484+ //Baseband register
2485+ u32 BB0C; // Used for LNA calculation
2486+ u32 BB2C; //
2487+ u32 BB30; //11b acquisition control register
2488+ u32 BB3C;
2489+ u32 BB48; // 20051221.1.a 20060613.1 Fix OBW issue of 11b/11g rate
2490+ u32 BB4C; // 20060613.1 Fix OBW issue of 11b/11g rate
2491+ u32 BB50; //mode control register
2492+ u32 BB54;
2493+ u32 BB58; //IQ_ALPHA
2494+ u32 BB5C; // For test
2495+ u32 BB60; // for WTO read value
2496+
2497+ //-------------------
2498+ // VM
2499+ //-------------------
2500+ OS_SPIN_LOCK EP0VM_spin_lock; // 4B
2501+ u32 EP0VM_status;//$$
2502+ PREG_QUEUE pRegFirst;
2503+ PREG_QUEUE pRegLast;
2504+ OS_ATOMIC RegFireCount;
2505+
2506+ // Hardware status
2507+ u8 EP0vm_state;
2508+ u8 mac_power_save;
2509+ u8 EEPROMPhyType; // 0 ~ 15 for Maxim (0 ĄV MAX2825, 1 ĄV MAX2827, 2 ĄV MAX2828, 3 ĄV MAX2829),
2510+ // 16 ~ 31 for Airoha (16 ĄV AL2230, 11 - AL7230)
2511+ // 32 ~ Reserved
2512+ // 33 ~ 47 For WB242 ( 33 - WB242, 34 - WB242 with new Txvga 0.5 db step)
2513+ // 48 ~ 255 ARE RESERVED.
2514+ u8 EEPROMRegion; //Region setting in EEPROM
2515+
2516+ u32 SyncIoPause; // If user use the Sync Io to access Hw, then pause the async access
2517+
2518+ u8 LNAValue[4]; //Table for speed up running
2519+ u32 SQ3_filter[MAX_SQ3_FILTER_SIZE];
2520+ u32 SQ3_index;
2521+
2522+} WB35REG, *PWB35REG;
2523+
2524+
2525diff --git a/drivers/staging/winbond/linux/wb35rx.c b/drivers/staging/winbond/linux/wb35rx.c
2526new file mode 100644
2527index 0000000..26157eb
2528--- /dev/null
2529+++ b/drivers/staging/winbond/linux/wb35rx.c
2530@@ -0,0 +1,337 @@
2531+//============================================================================
2532+// Copyright (c) 1996-2002 Winbond Electronic Corporation
2533+//
2534+// Module Name:
2535+// Wb35Rx.c
2536+//
2537+// Abstract:
2538+// Processing the Rx message from down layer
2539+//
2540+//============================================================================
2541+#include "sysdef.h"
2542+
2543+
2544+void Wb35Rx_start(phw_data_t pHwData)
2545+{
2546+ PWB35RX pWb35Rx = &pHwData->Wb35Rx;
2547+
2548+ // Allow only one thread to run into the Wb35Rx() function
2549+ if (OS_ATOMIC_INC(pHwData->Adapter, &pWb35Rx->RxFireCounter) == 1) {
2550+ pWb35Rx->EP3vm_state = VM_RUNNING;
2551+ Wb35Rx(pHwData);
2552+ } else
2553+ OS_ATOMIC_DEC(pHwData->Adapter, &pWb35Rx->RxFireCounter);
2554+}
2555+
2556+// This function cannot reentrain
2557+void Wb35Rx( phw_data_t pHwData )
2558+{
2559+ PWB35RX pWb35Rx = &pHwData->Wb35Rx;
2560+ PUCHAR pRxBufferAddress;
2561+ PURB pUrb = (PURB)pWb35Rx->RxUrb;
2562+ int retv;
2563+ u32 RxBufferId;
2564+
2565+ //
2566+ // Issuing URB
2567+ //
2568+ do {
2569+ if (pHwData->SurpriseRemove || pHwData->HwStop)
2570+ break;
2571+
2572+ if (pWb35Rx->rx_halt)
2573+ break;
2574+
2575+ // Get RxBuffer's ID
2576+ RxBufferId = pWb35Rx->RxBufferId;
2577+ if (!pWb35Rx->RxOwner[RxBufferId]) {
2578+ // It's impossible to run here.
2579+ #ifdef _PE_RX_DUMP_
2580+ WBDEBUG(("Rx driver fifo unavailable\n"));
2581+ #endif
2582+ break;
2583+ }
2584+
2585+ // Update buffer point, then start to bulkin the data from USB
2586+ pWb35Rx->RxBufferId++;
2587+ pWb35Rx->RxBufferId %= MAX_USB_RX_BUFFER_NUMBER;
2588+
2589+ pWb35Rx->CurrentRxBufferId = RxBufferId;
2590+
2591+ if (1 != OS_MEMORY_ALLOC((void* *)&pWb35Rx->pDRx, MAX_USB_RX_BUFFER)) {
2592+ printk("w35und: Rx memory alloc failed\n");
2593+ break;
2594+ }
2595+ pRxBufferAddress = pWb35Rx->pDRx;
2596+
2597+ usb_fill_bulk_urb(pUrb, pHwData->WbUsb.udev,
2598+ usb_rcvbulkpipe(pHwData->WbUsb.udev, 3),
2599+ pRxBufferAddress, MAX_USB_RX_BUFFER,
2600+ Wb35Rx_Complete, pHwData);
2601+
2602+ pWb35Rx->EP3vm_state = VM_RUNNING;
2603+
2604+ retv = wb_usb_submit_urb(pUrb);
2605+
2606+ if (retv != 0) {
2607+ printk("Rx URB sending error\n");
2608+ break;
2609+ }
2610+ return;
2611+ } while(FALSE);
2612+
2613+ // VM stop
2614+ pWb35Rx->EP3vm_state = VM_STOP;
2615+ OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Rx->RxFireCounter );
2616+}
2617+
2618+void Wb35Rx_Complete(PURB pUrb)
2619+{
2620+ phw_data_t pHwData = pUrb->context;
2621+ PWB35RX pWb35Rx = &pHwData->Wb35Rx;
2622+ PUCHAR pRxBufferAddress;
2623+ u32 SizeCheck;
2624+ u16 BulkLength;
2625+ u32 RxBufferId;
2626+ R00_DESCRIPTOR R00;
2627+
2628+ // Variable setting
2629+ pWb35Rx->EP3vm_state = VM_COMPLETED;
2630+ pWb35Rx->EP3VM_status = pUrb->status;//Store the last result of Irp
2631+
2632+ do {
2633+ RxBufferId = pWb35Rx->CurrentRxBufferId;
2634+
2635+ pRxBufferAddress = pWb35Rx->pDRx;
2636+ BulkLength = (u16)pUrb->actual_length;
2637+
2638+ // The IRP is completed
2639+ pWb35Rx->EP3vm_state = VM_COMPLETED;
2640+
2641+ if (pHwData->SurpriseRemove || pHwData->HwStop) // Must be here, or RxBufferId is invalid
2642+ break;
2643+
2644+ if (pWb35Rx->rx_halt)
2645+ break;
2646+
2647+ // Start to process the data only in successful condition
2648+ pWb35Rx->RxOwner[ RxBufferId ] = 0; // Set the owner to driver
2649+ R00.value = le32_to_cpu(*(PULONG)pRxBufferAddress);
2650+
2651+ // The URB is completed, check the result
2652+ if (pWb35Rx->EP3VM_status != 0) {
2653+ #ifdef _PE_USB_STATE_DUMP_
2654+ WBDEBUG(("EP3 IoCompleteRoutine return error\n"));
2655+ DebugUsbdStatusInformation( pWb35Rx->EP3VM_status );
2656+ #endif
2657+ pWb35Rx->EP3vm_state = VM_STOP;
2658+ break;
2659+ }
2660+
2661+ // 20060220 For recovering. check if operating in single USB mode
2662+ if (!HAL_USB_MODE_BURST(pHwData)) {
2663+ SizeCheck = R00.R00_receive_byte_count; //20060926 anson's endian
2664+ if ((SizeCheck & 0x03) > 0)
2665+ SizeCheck -= 4;
2666+ SizeCheck = (SizeCheck + 3) & ~0x03;
2667+ SizeCheck += 12; // 8 + 4 badbeef
2668+ if ((BulkLength > 1600) ||
2669+ (SizeCheck > 1600) ||
2670+ (BulkLength != SizeCheck) ||
2671+ (BulkLength == 0)) { // Add for fail Urb
2672+ pWb35Rx->EP3vm_state = VM_STOP;
2673+ pWb35Rx->Ep3ErrorCount2++;
2674+ }
2675+ }
2676+
2677+ // Indicating the receiving data
2678+ pWb35Rx->ByteReceived += BulkLength;
2679+ pWb35Rx->RxBufferSize[ RxBufferId ] = BulkLength;
2680+
2681+ if (!pWb35Rx->RxOwner[ RxBufferId ])
2682+ Wb35Rx_indicate(pHwData);
2683+
2684+ kfree(pWb35Rx->pDRx);
2685+ // Do the next receive
2686+ Wb35Rx(pHwData);
2687+ return;
2688+
2689+ } while(FALSE);
2690+
2691+ pWb35Rx->RxOwner[ RxBufferId ] = 1; // Set the owner to hardware
2692+ OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Rx->RxFireCounter );
2693+ pWb35Rx->EP3vm_state = VM_STOP;
2694+}
2695+
2696+//=====================================================================================
2697+unsigned char Wb35Rx_initial(phw_data_t pHwData)
2698+{
2699+ PWB35RX pWb35Rx = &pHwData->Wb35Rx;
2700+
2701+ // Initial the Buffer Queue
2702+ Wb35Rx_reset_descriptor( pHwData );
2703+
2704+ pWb35Rx->RxUrb = wb_usb_alloc_urb(0);
2705+ return (!!pWb35Rx->RxUrb);
2706+}
2707+
2708+void Wb35Rx_stop(phw_data_t pHwData)
2709+{
2710+ PWB35RX pWb35Rx = &pHwData->Wb35Rx;
2711+
2712+ // Canceling the Irp if already sends it out.
2713+ if (pWb35Rx->EP3vm_state == VM_RUNNING) {
2714+ usb_unlink_urb( pWb35Rx->RxUrb ); // Only use unlink, let Wb35Rx_destroy to free them
2715+ #ifdef _PE_RX_DUMP_
2716+ WBDEBUG(("EP3 Rx stop\n"));
2717+ #endif
2718+ }
2719+}
2720+
2721+// Needs process context
2722+void Wb35Rx_destroy(phw_data_t pHwData)
2723+{
2724+ PWB35RX pWb35Rx = &pHwData->Wb35Rx;
2725+
2726+ do {
2727+ OS_SLEEP(10000); // Delay for waiting function enter 940623.1.a
2728+ } while (pWb35Rx->EP3vm_state != VM_STOP);
2729+ OS_SLEEP(10000); // Delay for waiting function exit 940623.1.b
2730+
2731+ if (pWb35Rx->RxUrb)
2732+ usb_free_urb( pWb35Rx->RxUrb );
2733+ #ifdef _PE_RX_DUMP_
2734+ WBDEBUG(("Wb35Rx_destroy OK\n"));
2735+ #endif
2736+}
2737+
2738+void Wb35Rx_reset_descriptor( phw_data_t pHwData )
2739+{
2740+ PWB35RX pWb35Rx = &pHwData->Wb35Rx;
2741+ u32 i;
2742+
2743+ pWb35Rx->ByteReceived = 0;
2744+ pWb35Rx->RxProcessIndex = 0;
2745+ pWb35Rx->RxBufferId = 0;
2746+ pWb35Rx->EP3vm_state = VM_STOP;
2747+ pWb35Rx->rx_halt = 0;
2748+
2749+ // Initial the Queue. The last buffer is reserved for used if the Rx resource is unavailable.
2750+ for( i=0; i<MAX_USB_RX_BUFFER_NUMBER; i++ )
2751+ pWb35Rx->RxOwner[i] = 1;
2752+}
2753+
2754+void Wb35Rx_adjust(PDESCRIPTOR pRxDes)
2755+{
2756+ PULONG pRxBufferAddress;
2757+ u32 DecryptionMethod;
2758+ u32 i;
2759+ u16 BufferSize;
2760+
2761+ DecryptionMethod = pRxDes->R01.R01_decryption_method;
2762+ pRxBufferAddress = pRxDes->buffer_address[0];
2763+ BufferSize = pRxDes->buffer_size[0];
2764+
2765+ // Adjust the last part of data. Only data left
2766+ BufferSize -= 4; // For CRC-32
2767+ if (DecryptionMethod)
2768+ BufferSize -= 4;
2769+ if (DecryptionMethod == 3) // For CCMP
2770+ BufferSize -= 4;
2771+
2772+ // Adjust the IV field which after 802.11 header and ICV field.
2773+ if (DecryptionMethod == 1) // For WEP
2774+ {
2775+ for( i=6; i>0; i-- )
2776+ pRxBufferAddress[i] = pRxBufferAddress[i-1];
2777+ pRxDes->buffer_address[0] = pRxBufferAddress + 1;
2778+ BufferSize -= 4; // 4 byte for IV
2779+ }
2780+ else if( DecryptionMethod ) // For TKIP and CCMP
2781+ {
2782+ for (i=7; i>1; i--)
2783+ pRxBufferAddress[i] = pRxBufferAddress[i-2];
2784+ pRxDes->buffer_address[0] = pRxBufferAddress + 2;//Update the descriptor, shift 8 byte
2785+ BufferSize -= 8; // 8 byte for IV + ICV
2786+ }
2787+ pRxDes->buffer_size[0] = BufferSize;
2788+}
2789+
2790+extern void packet_came(char *pRxBufferAddress, int PacketSize);
2791+
2792+
2793+u16 Wb35Rx_indicate(phw_data_t pHwData)
2794+{
2795+ DESCRIPTOR RxDes;
2796+ PWB35RX pWb35Rx = &pHwData->Wb35Rx;
2797+ PUCHAR pRxBufferAddress;
2798+ u16 PacketSize;
2799+ u16 stmp, BufferSize, stmp2 = 0;
2800+ u32 RxBufferId;
2801+
2802+ // Only one thread be allowed to run into the following
2803+ do {
2804+ RxBufferId = pWb35Rx->RxProcessIndex;
2805+ if (pWb35Rx->RxOwner[ RxBufferId ]) //Owner by VM
2806+ break;
2807+
2808+ pWb35Rx->RxProcessIndex++;
2809+ pWb35Rx->RxProcessIndex %= MAX_USB_RX_BUFFER_NUMBER;
2810+
2811+ pRxBufferAddress = pWb35Rx->pDRx;
2812+ BufferSize = pWb35Rx->RxBufferSize[ RxBufferId ];
2813+
2814+ // Parse the bulkin buffer
2815+ while (BufferSize >= 4) {
2816+ if ((cpu_to_le32(*(PULONG)pRxBufferAddress) & 0x0fffffff) == RX_END_TAG) //Is ending? 921002.9.a
2817+ break;
2818+
2819+ // Get the R00 R01 first
2820+ RxDes.R00.value = le32_to_cpu(*(PULONG)pRxBufferAddress);
2821+ PacketSize = (u16)RxDes.R00.R00_receive_byte_count;
2822+ RxDes.R01.value = le32_to_cpu(*((PULONG)(pRxBufferAddress+4)));
2823+ // For new DMA 4k
2824+ if ((PacketSize & 0x03) > 0)
2825+ PacketSize -= 4;
2826+
2827+ // Basic check for Rx length. Is length valid?
2828+ if (PacketSize > MAX_PACKET_SIZE) {
2829+ #ifdef _PE_RX_DUMP_
2830+ WBDEBUG(("Serious ERROR : Rx data size too long, size =%d\n", PacketSize));
2831+ #endif
2832+
2833+ pWb35Rx->EP3vm_state = VM_STOP;
2834+ pWb35Rx->Ep3ErrorCount2++;
2835+ break;
2836+ }
2837+
2838+ // Start to process Rx buffer
2839+// RxDes.Descriptor_ID = RxBufferId; // Due to synchronous indicate, the field doesn't necessary to use.
2840+ BufferSize -= 8; //subtract 8 byte for 35's USB header length
2841+ pRxBufferAddress += 8;
2842+
2843+ RxDes.buffer_address[0] = pRxBufferAddress;
2844+ RxDes.buffer_size[0] = PacketSize;
2845+ RxDes.buffer_number = 1;
2846+ RxDes.buffer_start_index = 0;
2847+ RxDes.buffer_total_size = RxDes.buffer_size[0];
2848+ Wb35Rx_adjust(&RxDes);
2849+
2850+ packet_came(pRxBufferAddress, PacketSize);
2851+
2852+ // Move RxBuffer point to the next
2853+ stmp = PacketSize + 3;
2854+ stmp &= ~0x03; // 4n alignment
2855+ pRxBufferAddress += stmp;
2856+ BufferSize -= stmp;
2857+ stmp2 += stmp;
2858+ }
2859+
2860+ // Reclaim resource
2861+ pWb35Rx->RxOwner[ RxBufferId ] = 1;
2862+ } while(TRUE);
2863+
2864+ return stmp2;
2865+}
2866+
2867+
2868diff --git a/drivers/staging/winbond/linux/wb35rx_f.h b/drivers/staging/winbond/linux/wb35rx_f.h
2869new file mode 100644
2870index 0000000..daa3e73
2871--- /dev/null
2872+++ b/drivers/staging/winbond/linux/wb35rx_f.h
2873@@ -0,0 +1,17 @@
2874+//====================================
2875+// Interface function declare
2876+//====================================
2877+void Wb35Rx_reset_descriptor( phw_data_t pHwData );
2878+unsigned char Wb35Rx_initial( phw_data_t pHwData );
2879+void Wb35Rx_destroy( phw_data_t pHwData );
2880+void Wb35Rx_stop( phw_data_t pHwData );
2881+u16 Wb35Rx_indicate( phw_data_t pHwData );
2882+void Wb35Rx_adjust( PDESCRIPTOR pRxDes );
2883+void Wb35Rx_start( phw_data_t pHwData );
2884+
2885+void Wb35Rx( phw_data_t pHwData );
2886+void Wb35Rx_Complete( PURB pUrb );
2887+
2888+
2889+
2890+
2891diff --git a/drivers/staging/winbond/linux/wb35rx_s.h b/drivers/staging/winbond/linux/wb35rx_s.h
2892new file mode 100644
2893index 0000000..53b831f
2894--- /dev/null
2895+++ b/drivers/staging/winbond/linux/wb35rx_s.h
2896@@ -0,0 +1,48 @@
2897+//============================================================================
2898+// wb35rx.h --
2899+//============================================================================
2900+
2901+// Definition for this module used
2902+#define MAX_USB_RX_BUFFER 4096 // This parameter must be 4096 931130.4.f
2903+
2904+#define MAX_USB_RX_BUFFER_NUMBER ETHERNET_RX_DESCRIPTORS // Maximum 254, 255 is RESERVED ID
2905+#define RX_INTERFACE 0 // Interface 1
2906+#define RX_PIPE 2 // Pipe 3
2907+#define MAX_PACKET_SIZE 1600 //1568 // 8 + 1532 + 4 + 24(IV EIV MIC ICV CRC) for check DMA data 931130.4.g
2908+#define RX_END_TAG 0x0badbeef
2909+
2910+
2911+//====================================
2912+// Internal variable for module
2913+//====================================
2914+typedef struct _WB35RX
2915+{
2916+ u32 ByteReceived;// For calculating throughput of BulkIn
2917+ OS_ATOMIC RxFireCounter;// Does Wb35Rx module fire?
2918+
2919+ u8 RxBuffer[ MAX_USB_RX_BUFFER_NUMBER ][ ((MAX_USB_RX_BUFFER+3) & ~0x03 ) ];
2920+ u16 RxBufferSize[ ((MAX_USB_RX_BUFFER_NUMBER+1) & ~0x01) ];
2921+ u8 RxOwner[ ((MAX_USB_RX_BUFFER_NUMBER+3) & ~0x03 ) ];//Ownership of buffer 0: SW 1:HW
2922+
2923+ u32 RxProcessIndex;//The next index to process
2924+ u32 RxBufferId;
2925+ u32 EP3vm_state;
2926+
2927+ u32 rx_halt; // For VM stopping
2928+
2929+ u16 MoreDataSize;
2930+ u16 PacketSize;
2931+
2932+ u32 CurrentRxBufferId; // For complete routine usage
2933+ u32 Rx3UrbCancel;
2934+
2935+ u32 LastR1; // For RSSI reporting
2936+ struct urb * RxUrb;
2937+ u32 Ep3ErrorCount2; // 20060625.1 Usbd for Rx DMA error count
2938+
2939+ int EP3VM_status;
2940+ PUCHAR pDRx;
2941+
2942+} WB35RX, *PWB35RX;
2943+
2944+
2945diff --git a/drivers/staging/winbond/linux/wb35tx.c b/drivers/staging/winbond/linux/wb35tx.c
2946new file mode 100644
2947index 0000000..cf19c3b
2948--- /dev/null
2949+++ b/drivers/staging/winbond/linux/wb35tx.c
2950@@ -0,0 +1,313 @@
2951+//============================================================================
2952+// Copyright (c) 1996-2002 Winbond Electronic Corporation
2953+//
2954+// Module Name:
2955+// Wb35Tx.c
2956+//
2957+// Abstract:
2958+// Processing the Tx message and put into down layer
2959+//
2960+//============================================================================
2961+#include "sysdef.h"
2962+
2963+
2964+unsigned char
2965+Wb35Tx_get_tx_buffer(phw_data_t pHwData, PUCHAR *pBuffer )
2966+{
2967+ PWB35TX pWb35Tx = &pHwData->Wb35Tx;
2968+
2969+ *pBuffer = pWb35Tx->TxBuffer[0];
2970+ return TRUE;
2971+}
2972+
2973+void Wb35Tx_start(phw_data_t pHwData)
2974+{
2975+ PWB35TX pWb35Tx = &pHwData->Wb35Tx;
2976+
2977+ // Allow only one thread to run into function
2978+ if (OS_ATOMIC_INC(pHwData->Adapter, &pWb35Tx->TxFireCounter) == 1) {
2979+ pWb35Tx->EP4vm_state = VM_RUNNING;
2980+ Wb35Tx(pHwData);
2981+ } else
2982+ OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Tx->TxFireCounter );
2983+}
2984+
2985+
2986+void Wb35Tx(phw_data_t pHwData)
2987+{
2988+ PWB35TX pWb35Tx = &pHwData->Wb35Tx;
2989+ PADAPTER Adapter = pHwData->Adapter;
2990+ PUCHAR pTxBufferAddress;
2991+ PMDS pMds = &Adapter->Mds;
2992+ struct urb * pUrb = (struct urb *)pWb35Tx->Tx4Urb;
2993+ int retv;
2994+ u32 SendIndex;
2995+
2996+
2997+ if (pHwData->SurpriseRemove || pHwData->HwStop)
2998+ goto cleanup;
2999+
3000+ if (pWb35Tx->tx_halt)
3001+ goto cleanup;
3002+
3003+ // Ownership checking
3004+ SendIndex = pWb35Tx->TxSendIndex;
3005+ if (!pMds->TxOwner[SendIndex]) //No more data need to be sent, return immediately
3006+ goto cleanup;
3007+
3008+ pTxBufferAddress = pWb35Tx->TxBuffer[SendIndex];
3009+ //
3010+ // Issuing URB
3011+ //
3012+ usb_fill_bulk_urb(pUrb, pHwData->WbUsb.udev,
3013+ usb_sndbulkpipe(pHwData->WbUsb.udev, 4),
3014+ pTxBufferAddress, pMds->TxBufferSize[ SendIndex ],
3015+ Wb35Tx_complete, pHwData);
3016+
3017+ pWb35Tx->EP4vm_state = VM_RUNNING;
3018+ retv = wb_usb_submit_urb( pUrb );
3019+ if (retv<0) {
3020+ printk("EP4 Tx Irp sending error\n");
3021+ goto cleanup;
3022+ }
3023+
3024+ // Check if driver needs issue Irp for EP2
3025+ pWb35Tx->TxFillCount += pMds->TxCountInBuffer[SendIndex];
3026+ if (pWb35Tx->TxFillCount > 12)
3027+ Wb35Tx_EP2VM_start( pHwData );
3028+
3029+ pWb35Tx->ByteTransfer += pMds->TxBufferSize[SendIndex];
3030+ return;
3031+
3032+ cleanup:
3033+ pWb35Tx->EP4vm_state = VM_STOP;
3034+ OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Tx->TxFireCounter );
3035+}
3036+
3037+
3038+void Wb35Tx_complete(struct urb * pUrb)
3039+{
3040+ phw_data_t pHwData = pUrb->context;
3041+ PADAPTER Adapter = (PADAPTER)pHwData->Adapter;
3042+ PWB35TX pWb35Tx = &pHwData->Wb35Tx;
3043+ PMDS pMds = &Adapter->Mds;
3044+
3045+ printk("wb35: tx complete\n");
3046+ // Variable setting
3047+ pWb35Tx->EP4vm_state = VM_COMPLETED;
3048+ pWb35Tx->EP4VM_status = pUrb->status; //Store the last result of Irp
3049+ pMds->TxOwner[ pWb35Tx->TxSendIndex ] = 0;// Set the owner. Free the owner bit always.
3050+ pWb35Tx->TxSendIndex++;
3051+ pWb35Tx->TxSendIndex %= MAX_USB_TX_BUFFER_NUMBER;
3052+
3053+ do {
3054+ if (pHwData->SurpriseRemove || pHwData->HwStop) // Let WbWlanHalt to handle surprise remove
3055+ break;
3056+
3057+ if (pWb35Tx->tx_halt)
3058+ break;
3059+
3060+ // The URB is completed, check the result
3061+ if (pWb35Tx->EP4VM_status != 0) {
3062+ printk("URB submission failed\n");
3063+ pWb35Tx->EP4vm_state = VM_STOP;
3064+ break; // Exit while(FALSE);
3065+ }
3066+
3067+ Mds_Tx(Adapter);
3068+ Wb35Tx(pHwData);
3069+ return;
3070+ } while(FALSE);
3071+
3072+ OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Tx->TxFireCounter );
3073+ pWb35Tx->EP4vm_state = VM_STOP;
3074+}
3075+
3076+void Wb35Tx_reset_descriptor( phw_data_t pHwData )
3077+{
3078+ PWB35TX pWb35Tx = &pHwData->Wb35Tx;
3079+
3080+ pWb35Tx->TxSendIndex = 0;
3081+ pWb35Tx->tx_halt = 0;
3082+}
3083+
3084+unsigned char Wb35Tx_initial(phw_data_t pHwData)
3085+{
3086+ PWB35TX pWb35Tx = &pHwData->Wb35Tx;
3087+
3088+ pWb35Tx->Tx4Urb = wb_usb_alloc_urb(0);
3089+ if (!pWb35Tx->Tx4Urb)
3090+ return FALSE;
3091+
3092+ pWb35Tx->Tx2Urb = wb_usb_alloc_urb(0);
3093+ if (!pWb35Tx->Tx2Urb)
3094+ {
3095+ usb_free_urb( pWb35Tx->Tx4Urb );
3096+ return FALSE;
3097+ }
3098+
3099+ return TRUE;
3100+}
3101+
3102+//======================================================
3103+void Wb35Tx_stop(phw_data_t pHwData)
3104+{
3105+ PWB35TX pWb35Tx = &pHwData->Wb35Tx;
3106+
3107+ // Trying to canceling the Trp of EP2
3108+ if (pWb35Tx->EP2vm_state == VM_RUNNING)
3109+ usb_unlink_urb( pWb35Tx->Tx2Urb ); // Only use unlink, let Wb35Tx_destrot to free them
3110+ #ifdef _PE_TX_DUMP_
3111+ WBDEBUG(("EP2 Tx stop\n"));
3112+ #endif
3113+
3114+ // Trying to canceling the Irp of EP4
3115+ if (pWb35Tx->EP4vm_state == VM_RUNNING)
3116+ usb_unlink_urb( pWb35Tx->Tx4Urb ); // Only use unlink, let Wb35Tx_destrot to free them
3117+ #ifdef _PE_TX_DUMP_
3118+ WBDEBUG(("EP4 Tx stop\n"));
3119+ #endif
3120+}
3121+
3122+//======================================================
3123+void Wb35Tx_destroy(phw_data_t pHwData)
3124+{
3125+ PWB35TX pWb35Tx = &pHwData->Wb35Tx;
3126+
3127+ // Wait for VM stop
3128+ do {
3129+ OS_SLEEP(10000); // Delay for waiting function enter 940623.1.a
3130+ } while( (pWb35Tx->EP2vm_state != VM_STOP) && (pWb35Tx->EP4vm_state != VM_STOP) );
3131+ OS_SLEEP(10000); // Delay for waiting function enter 940623.1.b
3132+
3133+ if (pWb35Tx->Tx4Urb)
3134+ usb_free_urb( pWb35Tx->Tx4Urb );
3135+
3136+ if (pWb35Tx->Tx2Urb)
3137+ usb_free_urb( pWb35Tx->Tx2Urb );
3138+
3139+ #ifdef _PE_TX_DUMP_
3140+ WBDEBUG(("Wb35Tx_destroy OK\n"));
3141+ #endif
3142+}
3143+
3144+void Wb35Tx_CurrentTime(phw_data_t pHwData, u32 TimeCount)
3145+{
3146+ PWB35TX pWb35Tx = &pHwData->Wb35Tx;
3147+ unsigned char Trigger = FALSE;
3148+
3149+ if (pWb35Tx->TxTimer > TimeCount)
3150+ Trigger = TRUE;
3151+ else if (TimeCount > (pWb35Tx->TxTimer+500))
3152+ Trigger = TRUE;
3153+
3154+ if (Trigger) {
3155+ pWb35Tx->TxTimer = TimeCount;
3156+ Wb35Tx_EP2VM_start( pHwData );
3157+ }
3158+}
3159+
3160+void Wb35Tx_EP2VM_start(phw_data_t pHwData)
3161+{
3162+ PWB35TX pWb35Tx = &pHwData->Wb35Tx;
3163+
3164+ // Allow only one thread to run into function
3165+ if (OS_ATOMIC_INC( pHwData->Adapter, &pWb35Tx->TxResultCount ) == 1) {
3166+ pWb35Tx->EP2vm_state = VM_RUNNING;
3167+ Wb35Tx_EP2VM( pHwData );
3168+ }
3169+ else
3170+ OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Tx->TxResultCount );
3171+}
3172+
3173+
3174+void Wb35Tx_EP2VM(phw_data_t pHwData)
3175+{
3176+ PWB35TX pWb35Tx = &pHwData->Wb35Tx;
3177+ struct urb * pUrb = (struct urb *)pWb35Tx->Tx2Urb;
3178+ PULONG pltmp = (PULONG)pWb35Tx->EP2_buf;
3179+ int retv;
3180+
3181+ do {
3182+ if (pHwData->SurpriseRemove || pHwData->HwStop)
3183+ break;
3184+
3185+ if (pWb35Tx->tx_halt)
3186+ break;
3187+
3188+ //
3189+ // Issuing URB
3190+ //
3191+ usb_fill_int_urb( pUrb, pHwData->WbUsb.udev, usb_rcvintpipe(pHwData->WbUsb.udev,2),
3192+ pltmp, MAX_INTERRUPT_LENGTH, Wb35Tx_EP2VM_complete, pHwData, 32);
3193+
3194+ pWb35Tx->EP2vm_state = VM_RUNNING;
3195+ retv = wb_usb_submit_urb( pUrb );
3196+
3197+ if(retv < 0) {
3198+ #ifdef _PE_TX_DUMP_
3199+ WBDEBUG(("EP2 Tx Irp sending error\n"));
3200+ #endif
3201+ break;
3202+ }
3203+
3204+ return;
3205+
3206+ } while(FALSE);
3207+
3208+ pWb35Tx->EP2vm_state = VM_STOP;
3209+ OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Tx->TxResultCount );
3210+}
3211+
3212+
3213+void Wb35Tx_EP2VM_complete(struct urb * pUrb)
3214+{
3215+ phw_data_t pHwData = pUrb->context;
3216+ T02_DESCRIPTOR T02, TSTATUS;
3217+ PADAPTER Adapter = (PADAPTER)pHwData->Adapter;
3218+ PWB35TX pWb35Tx = &pHwData->Wb35Tx;
3219+ PULONG pltmp = (PULONG)pWb35Tx->EP2_buf;
3220+ u32 i;
3221+ u16 InterruptInLength;
3222+
3223+
3224+ // Variable setting
3225+ pWb35Tx->EP2vm_state = VM_COMPLETED;
3226+ pWb35Tx->EP2VM_status = pUrb->status;
3227+
3228+ do {
3229+ // For Linux 2.4. Interrupt will always trigger
3230+ if( pHwData->SurpriseRemove || pHwData->HwStop ) // Let WbWlanHalt to handle surprise remove
3231+ break;
3232+
3233+ if( pWb35Tx->tx_halt )
3234+ break;
3235+
3236+ //The Urb is completed, check the result
3237+ if (pWb35Tx->EP2VM_status != 0) {
3238+ WBDEBUG(("EP2 IoCompleteRoutine return error\n"));
3239+ pWb35Tx->EP2vm_state= VM_STOP;
3240+ break; // Exit while(FALSE);
3241+ }
3242+
3243+ // Update the Tx result
3244+ InterruptInLength = pUrb->actual_length;
3245+ // Modify for minimum memory access and DWORD alignment.
3246+ T02.value = cpu_to_le32(pltmp[0]) >> 8; // [31:8] -> [24:0]
3247+ InterruptInLength -= 1;// 20051221.1.c Modify the follow for more stable
3248+ InterruptInLength >>= 2; // InterruptInLength/4
3249+ for (i=1; i<=InterruptInLength; i++) {
3250+ T02.value |= ((cpu_to_le32(pltmp[i]) & 0xff) << 24);
3251+
3252+ TSTATUS.value = T02.value; //20061009 anson's endian
3253+ Mds_SendComplete( Adapter, &TSTATUS );
3254+ T02.value = cpu_to_le32(pltmp[i]) >> 8;
3255+ }
3256+
3257+ return;
3258+ } while(FALSE);
3259+
3260+ OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Tx->TxResultCount );
3261+ pWb35Tx->EP2vm_state = VM_STOP;
3262+}
3263+
3264diff --git a/drivers/staging/winbond/linux/wb35tx_f.h b/drivers/staging/winbond/linux/wb35tx_f.h
3265new file mode 100644
3266index 0000000..7705a84
3267--- /dev/null
3268+++ b/drivers/staging/winbond/linux/wb35tx_f.h
3269@@ -0,0 +1,20 @@
3270+//====================================
3271+// Interface function declare
3272+//====================================
3273+unsigned char Wb35Tx_initial( phw_data_t pHwData );
3274+void Wb35Tx_destroy( phw_data_t pHwData );
3275+unsigned char Wb35Tx_get_tx_buffer( phw_data_t pHwData, PUCHAR *pBuffer );
3276+
3277+void Wb35Tx_EP2VM( phw_data_t pHwData );
3278+void Wb35Tx_EP2VM_start( phw_data_t pHwData );
3279+void Wb35Tx_EP2VM_complete( PURB purb );
3280+
3281+void Wb35Tx_start( phw_data_t pHwData );
3282+void Wb35Tx_stop( phw_data_t pHwData );
3283+void Wb35Tx( phw_data_t pHwData );
3284+void Wb35Tx_complete( PURB purb );
3285+void Wb35Tx_reset_descriptor( phw_data_t pHwData );
3286+
3287+void Wb35Tx_CurrentTime( phw_data_t pHwData, u32 TimeCount );
3288+
3289+
3290diff --git a/drivers/staging/winbond/linux/wb35tx_s.h b/drivers/staging/winbond/linux/wb35tx_s.h
3291new file mode 100644
3292index 0000000..ac43257
3293--- /dev/null
3294+++ b/drivers/staging/winbond/linux/wb35tx_s.h
3295@@ -0,0 +1,47 @@
3296+//====================================
3297+// IS89C35 Tx related definition
3298+//====================================
3299+#define TX_INTERFACE 0 // Interface 1
3300+#define TX_PIPE 3 // endpoint 4
3301+#define TX_INTERRUPT 1 // endpoint 2
3302+#define MAX_INTERRUPT_LENGTH 64 // It must be 64 for EP2 hardware
3303+
3304+
3305+
3306+//====================================
3307+// Internal variable for module
3308+//====================================
3309+
3310+
3311+typedef struct _WB35TX
3312+{
3313+ // For Tx buffer
3314+ u8 TxBuffer[ MAX_USB_TX_BUFFER_NUMBER ][ MAX_USB_TX_BUFFER ];
3315+
3316+ // For Interrupt pipe
3317+ u8 EP2_buf[MAX_INTERRUPT_LENGTH];
3318+
3319+ OS_ATOMIC TxResultCount;// For thread control of EP2 931130.4.m
3320+ OS_ATOMIC TxFireCounter;// For thread control of EP4 931130.4.n
3321+ u32 ByteTransfer;
3322+
3323+ u32 TxSendIndex;// The next index of Mds array to be sent
3324+ u32 EP2vm_state; // for EP2vm state
3325+ u32 EP4vm_state; // for EP4vm state
3326+ u32 tx_halt; // Stopping VM
3327+
3328+ struct urb * Tx4Urb;
3329+ struct urb * Tx2Urb;
3330+
3331+ int EP2VM_status;
3332+ int EP4VM_status;
3333+
3334+ u32 TxFillCount; // 20060928
3335+ u32 TxTimer; // 20060928 Add if sending packet not great than 13
3336+
3337+} WB35TX, *PWB35TX;
3338+
3339+
3340+
3341+
3342+
3343diff --git a/drivers/staging/winbond/linux/wbusb.c b/drivers/staging/winbond/linux/wbusb.c
3344new file mode 100644
3345index 0000000..cbad5fb
3346--- /dev/null
3347+++ b/drivers/staging/winbond/linux/wbusb.c
3348@@ -0,0 +1,404 @@
3349+/*
3350+ * Copyright 2008 Pavel Machek <pavel@suse.cz>
3351+ *
3352+ * Distribute under GPLv2.
3353+ */
3354+#include "sysdef.h"
3355+#include <net/mac80211.h>
3356+
3357+
3358+MODULE_AUTHOR( DRIVER_AUTHOR );
3359+MODULE_DESCRIPTION( DRIVER_DESC );
3360+MODULE_LICENSE("GPL");
3361+MODULE_VERSION("0.1");
3362+
3363+
3364+//============================================================
3365+// vendor ID and product ID can into here for others
3366+//============================================================
3367+static struct usb_device_id Id_Table[] =
3368+{
3369+ {USB_DEVICE( 0x0416, 0x0035 )},
3370+ {USB_DEVICE( 0x18E8, 0x6201 )},
3371+ {USB_DEVICE( 0x18E8, 0x6206 )},
3372+ {USB_DEVICE( 0x18E8, 0x6217 )},
3373+ {USB_DEVICE( 0x18E8, 0x6230 )},
3374+ {USB_DEVICE( 0x18E8, 0x6233 )},
3375+ {USB_DEVICE( 0x1131, 0x2035 )},
3376+ { }
3377+};
3378+
3379+MODULE_DEVICE_TABLE(usb, Id_Table);
3380+
3381+static struct usb_driver wb35_driver = {
3382+ .name = "w35und",
3383+ .probe = wb35_probe,
3384+ .disconnect = wb35_disconnect,
3385+ .id_table = Id_Table,
3386+};
3387+
3388+static const struct ieee80211_rate wbsoft_rates[] = {
3389+ { .bitrate = 10, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
3390+};
3391+
3392+static const struct ieee80211_channel wbsoft_channels[] = {
3393+ { .center_freq = 2412},
3394+};
3395+
3396+int wbsoft_enabled;
3397+struct ieee80211_hw *my_dev;
3398+PADAPTER my_adapter;
3399+
3400+static int wbsoft_add_interface(struct ieee80211_hw *dev,
3401+ struct ieee80211_if_init_conf *conf)
3402+{
3403+ printk("wbsoft_add interface called\n");
3404+ return 0;
3405+}
3406+
3407+static void wbsoft_remove_interface(struct ieee80211_hw *dev,
3408+ struct ieee80211_if_init_conf *conf)
3409+{
3410+ printk("wbsoft_remove interface called\n");
3411+}
3412+
3413+static int wbsoft_nop(void)
3414+{
3415+ printk("wbsoft_nop called\n");
3416+ return 0;
3417+}
3418+
3419+static void wbsoft_configure_filter(struct ieee80211_hw *dev,
3420+ unsigned int changed_flags,
3421+ unsigned int *total_flags,
3422+ int mc_count, struct dev_mc_list *mclist)
3423+{
3424+ unsigned int bit_nr, new_flags;
3425+ u32 mc_filter[2];
3426+ int i;
3427+
3428+ new_flags = 0;
3429+
3430+ if (*total_flags & FIF_PROMISC_IN_BSS) {
3431+ new_flags |= FIF_PROMISC_IN_BSS;
3432+ mc_filter[1] = mc_filter[0] = ~0;
3433+ } else if ((*total_flags & FIF_ALLMULTI) || (mc_count > 32)) {
3434+ new_flags |= FIF_ALLMULTI;
3435+ mc_filter[1] = mc_filter[0] = ~0;
3436+ } else {
3437+ mc_filter[1] = mc_filter[0] = 0;
3438+ for (i = 0; i < mc_count; i++) {
3439+ if (!mclist)
3440+ break;
3441+ printk("Should call ether_crc here\n");
3442+ //bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3443+ bit_nr = 0;
3444+
3445+ bit_nr &= 0x3F;
3446+ mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3447+ mclist = mclist->next;
3448+ }
3449+ }
3450+
3451+ dev->flags &= ~IEEE80211_HW_RX_INCLUDES_FCS;
3452+
3453+ *total_flags = new_flags;
3454+}
3455+
3456+static int wbsoft_tx(struct ieee80211_hw *dev, struct sk_buff *skb,
3457+ struct ieee80211_tx_control *control)
3458+{
3459+ char *buffer = kmalloc(skb->len, GFP_ATOMIC);
3460+ printk("Sending frame %d bytes\n", skb->len);
3461+ memcpy(buffer, skb->data, skb->len);
3462+ if (1 == MLMESendFrame(my_adapter, buffer, skb->len, FRAME_TYPE_802_11_MANAGEMENT))
3463+ printk("frame sent ok (%d bytes)?\n", skb->len);
3464+ return NETDEV_TX_OK;
3465+}
3466+
3467+
3468+static int wbsoft_start(struct ieee80211_hw *dev)
3469+{
3470+ wbsoft_enabled = 1;
3471+ printk("wbsoft_start called\n");
3472+ return 0;
3473+}
3474+
3475+static int wbsoft_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
3476+{
3477+ ChanInfo ch;
3478+ printk("wbsoft_config called\n");
3479+
3480+ ch.band = 1;
3481+ ch.ChanNo = 1; /* Should use channel_num, or something, as that is already pre-translated */
3482+
3483+
3484+ hal_set_current_channel(&my_adapter->sHwData, ch);
3485+ hal_set_beacon_period(&my_adapter->sHwData, conf->beacon_int);
3486+// hal_set_cap_info(&my_adapter->sHwData, ?? );
3487+// hal_set_ssid(phw_data_t pHwData, PUCHAR pssid, u8 ssid_len); ??
3488+ hal_set_accept_broadcast(&my_adapter->sHwData, 1);
3489+ hal_set_accept_promiscuous(&my_adapter->sHwData, 1);
3490+ hal_set_accept_multicast(&my_adapter->sHwData, 1);
3491+ hal_set_accept_beacon(&my_adapter->sHwData, 1);
3492+ hal_set_radio_mode(&my_adapter->sHwData, 0);
3493+ //hal_set_antenna_number( phw_data_t pHwData, u8 number )
3494+ //hal_set_rf_power(phw_data_t pHwData, u8 PowerIndex)
3495+
3496+
3497+// hal_start_bss(&my_adapter->sHwData, WLAN_BSSTYPE_INFRASTRUCTURE); ??
3498+
3499+//void hal_set_rates(phw_data_t pHwData, PUCHAR pbss_rates,
3500+// u8 length, unsigned char basic_rate_set)
3501+
3502+ return 0;
3503+}
3504+
3505+static int wbsoft_config_interface(struct ieee80211_hw *dev,
3506+ struct ieee80211_vif *vif,
3507+ struct ieee80211_if_conf *conf)
3508+{
3509+ printk("wbsoft_config_interface called\n");
3510+ return 0;
3511+}
3512+
3513+static u64 wbsoft_get_tsf(struct ieee80211_hw *dev)
3514+{
3515+ printk("wbsoft_get_tsf called\n");
3516+ return 0;
3517+}
3518+
3519+static const struct ieee80211_ops wbsoft_ops = {
3520+ .tx = wbsoft_tx,
3521+ .start = wbsoft_start, /* Start can be pretty much empty as we do WbWLanInitialize() during probe? */
3522+ .stop = wbsoft_nop,
3523+ .add_interface = wbsoft_add_interface,
3524+ .remove_interface = wbsoft_remove_interface,
3525+ .config = wbsoft_config,
3526+ .config_interface = wbsoft_config_interface,
3527+ .configure_filter = wbsoft_configure_filter,
3528+ .get_stats = wbsoft_nop,
3529+ .get_tx_stats = wbsoft_nop,
3530+ .get_tsf = wbsoft_get_tsf,
3531+// conf_tx: hal_set_cwmin()/hal_set_cwmax;
3532+};
3533+
3534+struct wbsoft_priv {
3535+};
3536+
3537+
3538+int __init wb35_init(void)
3539+{
3540+ printk("[w35und]driver init\n");
3541+ return usb_register(&wb35_driver);
3542+}
3543+
3544+void __exit wb35_exit(void)
3545+{
3546+ printk("[w35und]driver exit\n");
3547+ usb_deregister( &wb35_driver );
3548+}
3549+
3550+module_init(wb35_init);
3551+module_exit(wb35_exit);
3552+
3553+// Usb kernel subsystem will call this function when a new device is plugged into.
3554+int wb35_probe(struct usb_interface *intf, const struct usb_device_id *id_table)
3555+{
3556+ PADAPTER Adapter;
3557+ PWBLINUX pWbLinux;
3558+ PWBUSB pWbUsb;
3559+ struct usb_host_interface *interface;
3560+ struct usb_endpoint_descriptor *endpoint;
3561+ int i, ret = -1;
3562+ u32 ltmp;
3563+ struct usb_device *udev = interface_to_usbdev(intf);
3564+
3565+ usb_get_dev(udev);
3566+
3567+ printk("[w35und]wb35_probe ->\n");
3568+
3569+ do {
3570+ for (i=0; i<(sizeof(Id_Table)/sizeof(struct usb_device_id)); i++ ) {
3571+ if ((udev->descriptor.idVendor == Id_Table[i].idVendor) &&
3572+ (udev->descriptor.idProduct == Id_Table[i].idProduct)) {
3573+ printk("[w35und]Found supported hardware\n");
3574+ break;
3575+ }
3576+ }
3577+ if ((i == (sizeof(Id_Table)/sizeof(struct usb_device_id)))) {
3578+ #ifdef _PE_USB_INI_DUMP_
3579+ WBDEBUG(("[w35und] This is not the one we are interested about\n"));
3580+ #endif
3581+ return -ENODEV;
3582+ }
3583+
3584+ // 20060630.2 Check the device if it already be opened
3585+ ret = usb_control_msg(udev, usb_rcvctrlpipe( udev, 0 ),
3586+ 0x01, USB_TYPE_VENDOR|USB_RECIP_DEVICE|USB_DIR_IN,
3587+ 0x0, 0x400, &ltmp, 4, HZ*100 );
3588+ if( ret < 0 )
3589+ break;
3590+
3591+ ltmp = cpu_to_le32(ltmp);
3592+ if (ltmp) // Is already initialized?
3593+ break;
3594+
3595+
3596+ Adapter = kzalloc(sizeof(ADAPTER), GFP_KERNEL);
3597+
3598+ my_adapter = Adapter;
3599+ pWbLinux = &Adapter->WbLinux;
3600+ pWbUsb = &Adapter->sHwData.WbUsb;
3601+ pWbUsb->udev = udev;
3602+
3603+ interface = intf->cur_altsetting;
3604+ endpoint = &interface->endpoint[0].desc;
3605+
3606+ if (endpoint[2].wMaxPacketSize == 512) {
3607+ printk("[w35und] Working on USB 2.0\n");
3608+ pWbUsb->IsUsb20 = 1;
3609+ }
3610+
3611+ if (!WbWLanInitialize(Adapter)) {
3612+ printk("[w35und]WbWLanInitialize fail\n");
3613+ break;
3614+ }
3615+
3616+ {
3617+ struct wbsoft_priv *priv;
3618+ struct ieee80211_hw *dev;
3619+ int res;
3620+
3621+ dev = ieee80211_alloc_hw(sizeof(*priv), &wbsoft_ops);
3622+
3623+ if (!dev) {
3624+ printk("w35und: ieee80211 alloc failed\n" );
3625+ BUG();
3626+ }
3627+
3628+ my_dev = dev;
3629+
3630+ SET_IEEE80211_DEV(dev, &udev->dev);
3631+ {
3632+ phw_data_t pHwData = &Adapter->sHwData;
3633+ unsigned char dev_addr[MAX_ADDR_LEN];
3634+ hal_get_permanent_address(pHwData, dev_addr);
3635+ SET_IEEE80211_PERM_ADDR(dev, dev_addr);
3636+ }
3637+
3638+
3639+ dev->extra_tx_headroom = 12; /* FIXME */
3640+ dev->flags = 0;
3641+
3642+ dev->channel_change_time = 1000;
3643+// dev->max_rssi = 100;
3644+
3645+ dev->queues = 1;
3646+
3647+ static struct ieee80211_supported_band band;
3648+
3649+ band.channels = wbsoft_channels;
3650+ band.n_channels = ARRAY_SIZE(wbsoft_channels);
3651+ band.bitrates = wbsoft_rates;
3652+ band.n_bitrates = ARRAY_SIZE(wbsoft_rates);
3653+
3654+ dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &band;
3655+#if 0
3656+ wbsoft_modes[0].num_channels = 1;
3657+ wbsoft_modes[0].channels = wbsoft_channels;
3658+ wbsoft_modes[0].mode = MODE_IEEE80211B;
3659+ wbsoft_modes[0].num_rates = ARRAY_SIZE(wbsoft_rates);
3660+ wbsoft_modes[0].rates = wbsoft_rates;
3661+
3662+ res = ieee80211_register_hwmode(dev, &wbsoft_modes[0]);
3663+ BUG_ON(res);
3664+#endif
3665+
3666+ res = ieee80211_register_hw(dev);
3667+ BUG_ON(res);
3668+ }
3669+
3670+ usb_set_intfdata( intf, Adapter );
3671+
3672+ printk("[w35und] _probe OK\n");
3673+ return 0;
3674+
3675+ } while(FALSE);
3676+
3677+ return -ENOMEM;
3678+}
3679+
3680+void packet_came(char *pRxBufferAddress, int PacketSize)
3681+{
3682+ struct sk_buff *skb;
3683+ struct ieee80211_rx_status rx_status = {0};
3684+
3685+ if (!wbsoft_enabled)
3686+ return;
3687+
3688+ skb = dev_alloc_skb(PacketSize);
3689+ if (!skb) {
3690+ printk("Not enough memory for packet, FIXME\n");
3691+ return;
3692+ }
3693+
3694+ memcpy(skb_put(skb, PacketSize),
3695+ pRxBufferAddress,
3696+ PacketSize);
3697+
3698+/*
3699+ rx_status.rate = 10;
3700+ rx_status.channel = 1;
3701+ rx_status.freq = 12345;
3702+ rx_status.phymode = MODE_IEEE80211B;
3703+*/
3704+
3705+ ieee80211_rx_irqsafe(my_dev, skb, &rx_status);
3706+}
3707+
3708+unsigned char
3709+WbUsb_initial(phw_data_t pHwData)
3710+{
3711+ return 1;
3712+}
3713+
3714+
3715+void
3716+WbUsb_destroy(phw_data_t pHwData)
3717+{
3718+}
3719+
3720+int wb35_open(struct net_device *netdev)
3721+{
3722+ PADAPTER Adapter = (PADAPTER)netdev->priv;
3723+ phw_data_t pHwData = &Adapter->sHwData;
3724+
3725+ netif_start_queue(netdev);
3726+
3727+ //TODO : put here temporarily
3728+ hal_set_accept_broadcast(pHwData, 1); // open accept broadcast
3729+
3730+ return 0;
3731+}
3732+
3733+int wb35_close(struct net_device *netdev)
3734+{
3735+ netif_stop_queue(netdev);
3736+ return 0;
3737+}
3738+
3739+void wb35_disconnect(struct usb_interface *intf)
3740+{
3741+ PWBLINUX pWbLinux;
3742+ PADAPTER Adapter = usb_get_intfdata(intf);
3743+ usb_set_intfdata(intf, NULL);
3744+
3745+ pWbLinux = &Adapter->WbLinux;
3746+
3747+ // Card remove
3748+ WbWlanHalt(Adapter);
3749+
3750+}
3751+
3752+
3753diff --git a/drivers/staging/winbond/linux/wbusb_f.h b/drivers/staging/winbond/linux/wbusb_f.h
3754new file mode 100644
3755index 0000000..cae29e1
3756--- /dev/null
3757+++ b/drivers/staging/winbond/linux/wbusb_f.h
3758@@ -0,0 +1,34 @@
3759+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
3760+// Copyright (c) 1996-2004 Winbond Electronic Corporation
3761+//
3762+// Module Name:
3763+// wbusb_f.h
3764+//
3765+// Abstract:
3766+// Linux driver.
3767+//
3768+// Author:
3769+//
3770+//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
3771+
3772+int wb35_open(struct net_device *netdev);
3773+int wb35_close(struct net_device *netdev);
3774+unsigned char WbUsb_initial(phw_data_t pHwData);
3775+void WbUsb_destroy(phw_data_t pHwData);
3776+unsigned char WbWLanInitialize(PADAPTER Adapter);
3777+#define WbUsb_Stop( _A )
3778+
3779+int wb35_probe(struct usb_interface *intf,const struct usb_device_id *id_table);
3780+void wb35_disconnect(struct usb_interface *intf);
3781+
3782+
3783+#define wb_usb_submit_urb(_A) usb_submit_urb(_A, GFP_ATOMIC)
3784+#define wb_usb_alloc_urb(_A) usb_alloc_urb(_A, GFP_ATOMIC)
3785+
3786+#define WbUsb_CheckForHang( _P )
3787+#define WbUsb_DetectStart( _P, _I )
3788+
3789+
3790+
3791+
3792+
3793diff --git a/drivers/staging/winbond/linux/wbusb_s.h b/drivers/staging/winbond/linux/wbusb_s.h
3794new file mode 100644
3795index 0000000..d5c1d53
3796--- /dev/null
3797+++ b/drivers/staging/winbond/linux/wbusb_s.h
3798@@ -0,0 +1,42 @@
3799+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
3800+// Copyright (c) 1996-2004 Winbond Electronic Corporation
3801+//
3802+// Module Name:
3803+// wbusb_s.h
3804+//
3805+// Abstract:
3806+// Linux driver.
3807+//
3808+// Author:
3809+//
3810+//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
3811+
3812+#define OS_SLEEP( _MT ) { set_current_state(TASK_INTERRUPTIBLE); \
3813+ schedule_timeout( _MT*HZ/1000000 ); }
3814+
3815+
3816+//---------------------------------------------------------------------------
3817+// RW_CONTEXT --
3818+//
3819+// Used to track driver-generated io irps
3820+//---------------------------------------------------------------------------
3821+typedef struct _RW_CONTEXT
3822+{
3823+ void* pHwData;
3824+ PURB pUrb;
3825+ void* pCallBackFunctionParameter;
3826+} RW_CONTEXT, *PRW_CONTEXT;
3827+
3828+
3829+
3830+
3831+#define DRIVER_AUTHOR "Original by: Jeff Lee<YY_Lee@issc.com.tw> Adapted to 2.6.x by Costantino Leandro (Rxart Desktop) <le_costantino@pixartargentina.com.ar>"
3832+#define DRIVER_DESC "IS89C35 802.11bg WLAN USB Driver"
3833+
3834+
3835+
3836+typedef struct _WBUSB {
3837+ u32 IsUsb20;
3838+ struct usb_device *udev;
3839+ u32 DetectCount;
3840+} WBUSB, *PWBUSB;
3841diff --git a/drivers/staging/winbond/localpara.h b/drivers/staging/winbond/localpara.h
3842new file mode 100644
3843index 0000000..268cf91
3844--- /dev/null
3845+++ b/drivers/staging/winbond/localpara.h
3846@@ -0,0 +1,275 @@
3847+//=============================================================
3848+// LocalPara.h -
3849+//=============================================================
3850+//Define the local ability
3851+
3852+#define LOCAL_DEFAULT_BEACON_PERIOD 100 //ms
3853+#define LOCAL_DEFAULT_ATIM_WINDOW 0
3854+#define LOCAL_DEFAULT_ERP_CAPABILITY 0x0431 //0x0001: ESS
3855+ //0x0010: Privacy
3856+ //0x0020: short preamble
3857+ //0x0400: short slot time
3858+#define LOCAL_DEFAULT_LISTEN_INTERVAL 5
3859+
3860+//#define LOCAL_DEFAULT_24_CHANNEL_NUM 11 // channel 1..11
3861+#define LOCAL_DEFAULT_24_CHANNEL_NUM 13 // channel 1..13
3862+#define LOCAL_DEFAULT_5_CHANNEL_NUM 8 // channel 36..64
3863+
3864+#define LOCAL_USA_24_CHANNEL_NUM 11
3865+#define LOCAL_USA_5_CHANNEL_NUM 12
3866+#define LOCAL_EUROPE_24_CHANNEL_NUM 13
3867+#define LOCAL_EUROPE_5_CHANNEL_NUM 19
3868+#define LOCAL_JAPAN_24_CHANNEL_NUM 14
3869+#define LOCAL_JAPAN_5_CHANNEL_NUM 11
3870+#define LOCAL_UNKNOWN_24_CHANNEL_NUM 14
3871+#define LOCAL_UNKNOWN_5_CHANNEL_NUM 34 //not include 165
3872+
3873+
3874+#define psLOCAL (&(Adapter->sLocalPara))
3875+
3876+#define MODE_802_11_BG 0
3877+#define MODE_802_11_A 1
3878+#define MODE_802_11_ABG 2
3879+#define MODE_802_11_BG_IBSS 3
3880+#define MODE_802_11_B 4
3881+#define MODE_AUTO 255
3882+
3883+#define BAND_TYPE_DSSS 0
3884+#define BAND_TYPE_OFDM_24 1
3885+#define BAND_TYPE_OFDM_5 2
3886+
3887+//refer Bitmap2RateValue table
3888+#define LOCAL_ALL_SUPPORTED_RATES_BITMAP 0x130c1a66 //the bitmap value of all the H/W supported rates
3889+ //1, 2, 5.5, 11, 6, 9, 12, 18, 24, 36, 48, 54
3890+#define LOCAL_OFDM_SUPPORTED_RATES_BITMAP 0x130c1240 //the bitmap value of all the H/W supported rates
3891+ //except to non-OFDM rates
3892+ //6, 9, 12, 18, 24, 36, 48, 54
3893+
3894+#define LOCAL_11B_SUPPORTED_RATE_BITMAP 0x826
3895+#define LOCAL_11B_BASIC_RATE_BITMAP 0x826
3896+#define LOCAL_11B_OPERATION_RATE_BITMAP 0x826
3897+#define LOCAL_11G_BASIC_RATE_BITMAP 0x826 //1, 2, 5.5, 11
3898+#define LOCAL_11G_OPERATION_RATE_BITMAP 0x130c1240 //6, 9, 12, 18, 24, 36, 48, 54
3899+#define LOCAL_11A_BASIC_RATE_BITMAP 0x01001040 //6, 12, 24
3900+#define LOCAL_11A_OPERATION_RATE_BITMAP 0x120c0200 //9, 18, 36, 48, 54
3901+
3902+
3903+
3904+#define PWR_ACTIVE 0
3905+#define PWR_SAVE 1
3906+#define PWR_TX_IDLE_CYCLE 6
3907+
3908+//bPreambleMode and bSlotTimeMode
3909+#define AUTO_MODE 0
3910+#define LONG_MODE 1
3911+
3912+//Region definition
3913+#define REGION_AUTO 0xff
3914+#define REGION_UNKNOWN 0
3915+#define REGION_EUROPE 1 //ETSI
3916+#define REGION_JAPAN 2 //MKK
3917+#define REGION_USA 3 //FCC
3918+#define REGION_FRANCE 4 //FRANCE
3919+#define REGION_SPAIN 5 //SPAIN
3920+#define REGION_ISRAEL 6 //ISRAEL
3921+//#define REGION_CANADA 7 //IC
3922+
3923+#define MAX_BSS_DESCRIPT_ELEMENT 32
3924+#define MAX_PMKID_CandidateList 16
3925+
3926+//High byte : Event number, low byte : reason
3927+//Event definition
3928+//-- SME/MLME event
3929+#define EVENT_RCV_DEAUTH 0x0100
3930+#define EVENT_JOIN_FAIL 0x0200
3931+#define EVENT_AUTH_FAIL 0x0300
3932+#define EVENT_ASSOC_FAIL 0x0400
3933+#define EVENT_LOST_SIGNAL 0x0500
3934+#define EVENT_BSS_DESCRIPT_LACK 0x0600
3935+#define EVENT_COUNTERMEASURE 0x0700
3936+#define EVENT_JOIN_FILTER 0x0800
3937+//-- TX/RX event
3938+#define EVENT_RX_BUFF_UNAVAILABLE 0x4100
3939+
3940+#define EVENT_CONNECT 0x8100
3941+#define EVENT_DISCONNECT 0x8200
3942+#define EVENT_SCAN_REQ 0x8300
3943+
3944+//Reason of Event
3945+#define EVENT_REASON_FILTER_BASIC_RATE 0x0001
3946+#define EVENT_REASON_FILTER_PRIVACY 0x0002
3947+#define EVENT_REASON_FILTER_AUTH_MODE 0x0003
3948+#define EVENT_REASON_TIMEOUT 0x00ff
3949+
3950+// 20061108 WPS IE buffer
3951+#define MAX_IE_APPEND_SIZE 256 + 4 // Due to [E id][Length][OUI][Data] may 257 bytes
3952+
3953+typedef struct _EVENTLOG
3954+{
3955+ u16 Count; //Total count from start
3956+ u16 index; //Buffer index, 0 ~ 63
3957+ u32 EventValue[64]; //BYTE 3~2 : count, BYTE 1 : Event, BYTE 0 : reason
3958+} Event_Log, *pEvent_Log;
3959+
3960+typedef struct _ChanInfo
3961+{
3962+ u8 band;
3963+ u8 ChanNo;
3964+} ChanInfo, *pChanInfo;
3965+
3966+typedef struct _CHAN_LIST
3967+{
3968+ u16 Count;
3969+ ChanInfo Channel[50]; // 100B
3970+} CHAN_LIST, *psCHAN_LIST;
3971+
3972+typedef struct _RadioOff
3973+{
3974+ u8 boHwRadioOff;
3975+ u8 boSwRadioOff;
3976+} RadioOff, *psRadioOff;
3977+
3978+//===========================================================================
3979+typedef struct LOCAL_PARA
3980+{
3981+ u8 PermanentAddress[ MAC_ADDR_LENGTH + 2 ]; // read from EPROM, manufacture set for each NetCard
3982+ u8 ThisMacAddress[ MAC_ADDR_LENGTH + 2 ]; // the driver will use actually.
3983+
3984+ u32 MTUsize; // Ind to Uplayer, Max transmission unit size
3985+
3986+ u8 region_INF; //region setting from INF
3987+ u8 region; //real region setting of the device
3988+ u8 Reserved_1[2];
3989+
3990+ //// power-save variables
3991+ u8 iPowerSaveMode; // 0 indicates it is on, 1 indicates it is off
3992+ u8 ShutDowned;
3993+ u8 ATIMmode;
3994+ u8 ExcludeUnencrypted;
3995+
3996+ u16 CheckCountForPS; //Unit ime count for the decision to enter PS mode
3997+ u8 boHasTxActivity; //tx activity has occurred
3998+ u8 boMacPsValid; //Power save mode obtained from H/W is valid or not
3999+
4000+ //// Rate
4001+ u8 TxRateMode; // Initial, input from Registry, may be updated by GUI
4002+ //Tx Rate Mode: auto(DTO on), max, 1M, 2M, ..
4003+ u8 CurrentTxRate; // The current Tx rate
4004+ u8 CurrentTxRateForMng; // The current Tx rate for management frames
4005+ // It will be decided before connection succeeds.
4006+ u8 CurrentTxFallbackRate;
4007+
4008+ //for Rate handler
4009+ u8 BRateSet[32]; //basic rate set
4010+ u8 SRateSet[32]; //support rate set
4011+
4012+ u8 NumOfBRate;
4013+ u8 NumOfSRate;
4014+ u8 NumOfDsssRateInSRate; //number of DSSS rates in supported rate set
4015+ u8 reserved1;
4016+
4017+ u32 dwBasicRateBitmap; //bit map of basic rates
4018+ u32 dwSupportRateBitmap; //bit map of all support rates including
4019+ //basic and operational rates
4020+
4021+ ////For SME/MLME handler
4022+ u16 wOldSTAindex; // valid when boHandover=TRUE, store old connected STA index
4023+ u16 wConnectedSTAindex; // Index of peerly connected AP or IBSS in
4024+ // the descriptionset.
4025+ u16 Association_ID; // The Association ID in the (Re)Association
4026+ // Response frame.
4027+ u16 ListenInterval; // The listen interval when SME invoking MLME_
4028+ // (Re)Associate_Request().
4029+
4030+ RadioOff RadioOffStatus;
4031+ u8 Reserved0[2];
4032+
4033+ u8 boMsRadioOff; // Ndis demands to be true when set Disassoc. OID and be false when set SSID OID.
4034+ u8 boAntennaDiversity; //TRUE/ON or FALSE/OFF
4035+ u8 bAntennaNo; //which antenna
4036+ u8 bConnectFlag; //the connect status flag for roaming task
4037+
4038+ u8 RoamStatus;
4039+ u8 reserved7[3];
4040+
4041+ ChanInfo CurrentChan; //Current channel no. and channel band. It may be changed by scanning.
4042+ u8 boHandover; // Roaming, Hnadover to other AP.
4043+ u8 boCCAbusy;
4044+
4045+ u16 CWMax; // It may not be the real value that H/W used
4046+ u8 CWMin; // 255: set according to 802.11 spec.
4047+ u8 reserved2;
4048+
4049+ //11G:
4050+ u8 bMacOperationMode; // operation in 802.11b or 802.11g
4051+ u8 bSlotTimeMode; //AUTO, s32
4052+ u8 bPreambleMode; //AUTO, s32
4053+ u8 boNonERPpresent;
4054+
4055+ u8 boProtectMechanism; // H/W will take the necessary action based on this variable
4056+ u8 boShortPreamble; // H/W will take the necessary action based on this variable
4057+ u8 boShortSlotTime; // H/W will take the necessary action based on this variable
4058+ u8 reserved_3;
4059+
4060+ u32 RSN_IE_Bitmap; //added by WS
4061+ u32 RSN_OUI_Type; //added by WS
4062+
4063+ //For the BSSID
4064+ u8 HwBssid[MAC_ADDR_LENGTH + 2];
4065+ u32 HwBssidValid;
4066+
4067+ //For scan list
4068+ u8 BssListCount; //Total count of valid descriptor indexes
4069+ u8 boReceiveUncorrectInfo; //important settings in beacon/probe resp. have been changed
4070+ u8 NoOfJoinerInIbss;
4071+ u8 reserved_4;
4072+
4073+ u8 BssListIndex[ (MAX_BSS_DESCRIPT_ELEMENT+3) & ~0x03 ]; //Store the valid descriptor indexes obtained from scannings
4074+ u8 JoinerInIbss[ (MAX_BSS_DESCRIPT_ELEMENT+3) & ~0x03 ]; //save the BssDescriptor index in this
4075+ //IBSS. The index 0 is local descriptor
4076+ //(psLOCAL->wConnectedSTAindex).
4077+ //If CONNECTED : NoOfJoinerInIbss >=2
4078+ // else : NoOfJoinerInIbss <=1
4079+
4080+ //// General Statistics, count at Rx_handler or Tx_callback interrupt handler
4081+ u64 GS_XMIT_OK; // Good Frames Transmitted
4082+ u64 GS_RCV_OK; // Good Frames Received
4083+ u32 GS_RCV_ERROR; // Frames received with crc error
4084+ u32 GS_XMIT_ERROR; // Bad Frames Transmitted
4085+ u32 GS_RCV_NO_BUFFER; // Receive Buffer underrun
4086+ u32 GS_XMIT_ONE_COLLISION; // one collision
4087+ u32 GS_XMIT_MORE_COLLISIONS;// more collisions
4088+
4089+ //================================================================
4090+ // Statistics (no matter whether it had done successfully) -wkchen
4091+ //================================================================
4092+ u32 _NumRxMSDU;
4093+ u32 _NumTxMSDU;
4094+ u32 _dot11WEPExcludedCount;
4095+ u32 _dot11WEPUndecryptableCount;
4096+ u32 _dot11FrameDuplicateCount;
4097+
4098+ ChanInfo IbssChanSetting; // 2B. Start IBSS Channel setting by registry or WWU.
4099+ u8 reserved_5[2]; //It may not be used after considering RF type,
4100+ //region and modulation type.
4101+
4102+ CHAN_LIST sSupportChanList; // 86B. It will be obtained according to RF type and region
4103+ u8 reserved_6[2]; //two variables are for wep key error detection added by ws 02/02/04
4104+
4105+ u32 bWepKeyError;
4106+ u32 bToSelfPacketReceived;
4107+ u32 WepKeyDetectTimerCount;
4108+
4109+ Event_Log EventLog;
4110+
4111+ u16 SignalLostTh;
4112+ u16 SignalRoamTh;
4113+
4114+ // 20061108 WPS IE Append
4115+ u8 IE_Append_data[MAX_IE_APPEND_SIZE];
4116+ u16 IE_Append_size;
4117+ u16 reserved_7;
4118+
4119+} WB_LOCALDESCRIPT, *PWB_LOCALDESCRIPT;
4120+
4121+
4122diff --git a/drivers/staging/winbond/mac_structures.h b/drivers/staging/winbond/mac_structures.h
4123new file mode 100644
4124index 0000000..031d2cb
4125--- /dev/null
4126+++ b/drivers/staging/winbond/mac_structures.h
4127@@ -0,0 +1,670 @@
4128+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
4129+// MAC_Structures.h
4130+//
4131+// This file contains the definitions and data structures used by SW-MAC.
4132+//
4133+// Revision Histoy
4134+//=================
4135+// 0.1 2002 UN00
4136+// 0.2 20021004 PD43 CCLiu6
4137+// 20021018 PD43 CCLiu6
4138+// Add enum_TxRate type
4139+// Modify enum_STAState type
4140+// 0.3 20021023 PE23 CYLiu update MAC session struct
4141+// 20021108
4142+// 20021122 PD43 Austin
4143+// Deleted some unused.
4144+// 20021129 PD43 Austin
4145+// 20030617 increase the 802.11g definition
4146+//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
4147+
4148+#ifndef _MAC_Structures_H_
4149+#define _MAC_Structures_H_
4150+
4151+
4152+//=========================================================
4153+// Some miscellaneous definitions
4154+//-----
4155+#define MAX_CHANNELS 30
4156+#define MAC_ADDR_LENGTH 6
4157+#define MAX_WEP_KEY_SIZE 16 // 128 bits
4158+#define MAX_802_11_FRAGMENT_NUMBER 10 // By spec
4159+
4160+//========================================================
4161+// 802.11 Frame define
4162+//-----
4163+#define MASK_PROTOCOL_VERSION_TYPE 0x0F
4164+#define MASK_FRAGMENT_NUMBER 0x000F
4165+#define SEQUENCE_NUMBER_SHIFT 4
4166+#define DIFFER_11_TO_3 18
4167+#define DOT_11_MAC_HEADER_SIZE 24
4168+#define DOT_11_SNAP_SIZE 6
4169+#define DOT_11_DURATION_OFFSET 2
4170+#define DOT_11_SEQUENCE_OFFSET 22 //Sequence control offset
4171+#define DOT_11_TYPE_OFFSET 30 //The start offset of 802.11 Frame//
4172+#define DOT_11_DATA_OFFSET 24
4173+#define DOT_11_DA_OFFSET 4
4174+#define DOT_3_TYPE_ARP 0x80F3
4175+#define DOT_3_TYPE_IPX 0x8137
4176+#define DOT_3_TYPE_OFFSET 12
4177+
4178+
4179+#define ETHERNET_HEADER_SIZE 14
4180+#define MAX_ETHERNET_PACKET_SIZE 1514
4181+
4182+
4183+//----- management : Type of Bits (2, 3) and Subtype of Bits (4, 5, 6, 7)
4184+#define MAC_SUBTYPE_MNGMNT_ASSOC_REQUEST 0x00
4185+#define MAC_SUBTYPE_MNGMNT_ASSOC_RESPONSE 0x10
4186+#define MAC_SUBTYPE_MNGMNT_REASSOC_REQUEST 0x20
4187+#define MAC_SUBTYPE_MNGMNT_REASSOC_RESPONSE 0x30
4188+#define MAC_SUBTYPE_MNGMNT_PROBE_REQUEST 0x40
4189+#define MAC_SUBTYPE_MNGMNT_PROBE_RESPONSE 0x50
4190+#define MAC_SUBTYPE_MNGMNT_BEACON 0x80
4191+#define MAC_SUBTYPE_MNGMNT_ATIM 0x90
4192+#define MAC_SUBTYPE_MNGMNT_DISASSOCIATION 0xA0
4193+#define MAC_SUBTYPE_MNGMNT_AUTHENTICATION 0xB0
4194+#define MAC_SUBTYPE_MNGMNT_DEAUTHENTICATION 0xC0
4195+
4196+//----- control : Type of Bits (2, 3) and Subtype of Bits (4, 5, 6, 7)
4197+#define MAC_SUBTYPE_CONTROL_PSPOLL 0xA4
4198+#define MAC_SUBTYPE_CONTROL_RTS 0xB4
4199+#define MAC_SUBTYPE_CONTROL_CTS 0xC4
4200+#define MAC_SUBTYPE_CONTROL_ACK 0xD4
4201+#define MAC_SUBTYPE_CONTROL_CFEND 0xE4
4202+#define MAC_SUBTYPE_CONTROL_CFEND_CFACK 0xF4
4203+
4204+//----- data : Type of Bits (2, 3) and Subtype of Bits (4, 5, 6, 7)
4205+#define MAC_SUBTYPE_DATA 0x08
4206+#define MAC_SUBTYPE_DATA_CFACK 0x18
4207+#define MAC_SUBTYPE_DATA_CFPOLL 0x28
4208+#define MAC_SUBTYPE_DATA_CFACK_CFPOLL 0x38
4209+#define MAC_SUBTYPE_DATA_NULL 0x48
4210+#define MAC_SUBTYPE_DATA_CFACK_NULL 0x58
4211+#define MAC_SUBTYPE_DATA_CFPOLL_NULL 0x68
4212+#define MAC_SUBTYPE_DATA_CFACK_CFPOLL_NULL 0x78
4213+
4214+//----- Frame Type of Bits (2, 3)
4215+#define MAC_TYPE_MANAGEMENT 0x00
4216+#define MAC_TYPE_CONTROL 0x04
4217+#define MAC_TYPE_DATA 0x08
4218+
4219+//----- definitions for Management Frame Element ID (1 BYTE)
4220+#define ELEMENT_ID_SSID 0
4221+#define ELEMENT_ID_SUPPORTED_RATES 1
4222+#define ELEMENT_ID_FH_PARAMETER_SET 2
4223+#define ELEMENT_ID_DS_PARAMETER_SET 3
4224+#define ELEMENT_ID_CF_PARAMETER_SET 4
4225+#define ELEMENT_ID_TIM 5
4226+#define ELEMENT_ID_IBSS_PARAMETER_SET 6
4227+// 7~15 reserverd
4228+#define ELEMENT_ID_CHALLENGE_TEXT 16
4229+// 17~31 reserved for challenge text extension
4230+// 32~255 reserved
4231+//-- 11G --
4232+#define ELEMENT_ID_ERP_INFORMATION 42
4233+#define ELEMENT_ID_EXTENDED_SUPPORTED_RATES 50
4234+
4235+//-- WPA --
4236+
4237+#define ELEMENT_ID_RSN_WPA 221
4238+#ifdef _WPA2_
4239+#define ELEMENT_ID_RSN_WPA2 48
4240+#endif //endif WPA2
4241+
4242+#define WLAN_MAX_PAIRWISE_CIPHER_SUITE_COUNT ((u16) 6)
4243+#define WLAN_MAX_AUTH_KEY_MGT_SUITE_LIST_COUNT ((u16) 2)
4244+
4245+#ifdef WB_LINUX
4246+#define UNALIGNED
4247+#endif
4248+
4249+//========================================================
4250+typedef enum enum_PowerManagementMode
4251+{
4252+ ACTIVE = 0,
4253+ POWER_SAVE
4254+} WB_PM_Mode, *PWB_PM_MODE;
4255+
4256+//===================================================================
4257+// Reason Code (Table 18): indicate the reason of DisAssoc, DeAuthen
4258+// length of ReasonCode is 2 Octs.
4259+//===================================================================
4260+#define REASON_REASERED 0
4261+#define REASON_UNSPECIDIED 1
4262+#define REASON_PREAUTH_INVALID 2
4263+#define DEAUTH_REASON_LEFT_BSS 3
4264+#define DISASS_REASON_AP_INACTIVE 4
4265+#define DISASS_REASON_AP_BUSY 5
4266+#define REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6
4267+#define REASON_CLASS3_FRAME_FROM_NONASSO_STA 7
4268+#define DISASS_REASON_LEFT_BSS 8
4269+#define REASON_NOT_AUTH_YET 9
4270+//802.11i define
4271+#define REASON_INVALID_IE 13
4272+#define REASON_MIC_ERROR 14
4273+#define REASON_4WAY_HANDSHAKE_TIMEOUT 15
4274+#define REASON_GROUPKEY_UPDATE_TIMEOUT 16
4275+#define REASON_IE_DIFF_4WAY_ASSOC 17
4276+#define REASON_INVALID_MULTICAST_CIPHER 18
4277+#define REASON_INVALID_UNICAST_CIPHER 19
4278+#define REASON_INVALID_AKMP 20
4279+#define REASON_UNSUPPORTED_RSNIE_VERSION 21
4280+#define REASON_INVALID_RSNIE_CAPABILITY 22
4281+#define REASON_802_1X_AUTH_FAIL 23
4282+#define REASON_CIPHER_REJECT_PER_SEC_POLICY 14
4283+
4284+/*
4285+//===========================================================
4286+// enum_MMPDUResultCode --
4287+// Status code (2 Octs) in the MMPDU's frame body. Table.19
4288+//
4289+//===========================================================
4290+enum enum_MMPDUResultCode
4291+{
4292+// SUCCESS = 0, // Redefined
4293+ UNSPECIFIED_FAILURE = 1,
4294+
4295+ // 2 - 9 Reserved
4296+
4297+ NOT_SUPPROT_CAPABILITIES = 10,
4298+
4299+ //REASSOCIATION_DENIED
4300+ //
4301+ REASSOC_DENIED_UNABLE_CFM_ASSOC_EXIST = 11,
4302+
4303+ //ASSOCIATION_DENIED_NOT_IN_STANDARD
4304+ //
4305+ ASSOC_DENIED_REASON_NOT_IN_STANDARD = 12,
4306+ PEER_NOT_SUPPORT_AUTH_ALGORITHM = 13,
4307+ AUTH_SEQNUM_OUT_OF_EXPECT = 14,
4308+ AUTH_REJECT_REASON_CHALLENGE_FAIL = 15,
4309+ AUTH_REJECT_REASON_WAIT_TIMEOUT = 16,
4310+ ASSOC_DENIED_REASON_AP_BUSY = 17,
4311+ ASSOC_DENIED_REASON_NOT_SUPPORT_BASIC_RATE = 18
4312+} WB_MMPDURESULTCODE, *PWB_MMPDURESULTCODE;
4313+*/
4314+
4315+//===========================================================
4316+// enum_TxRate --
4317+// Define the transmission constants based on W89C32 MAC
4318+// target specification.
4319+//===========================================================
4320+typedef enum enum_TxRate
4321+{
4322+ TXRATE_1M = 0,
4323+ TXRATE_2MLONG = 2,
4324+ TXRATE_2MSHORT = 3,
4325+ TXRATE_55MLONG = 4,
4326+ TXRATE_55MSHORT = 5,
4327+ TXRATE_11MLONG = 6,
4328+ TXRATE_11MSHORT = 7,
4329+ TXRATE_AUTO = 255 // PD43 20021108
4330+} WB_TXRATE, *PWB_TXRATE;
4331+
4332+
4333+#define RATE_BITMAP_1M 1
4334+#define RATE_BITMAP_2M 2
4335+#define RATE_BITMAP_5dot5M 5
4336+#define RATE_BITMAP_6M 6
4337+#define RATE_BITMAP_9M 9
4338+#define RATE_BITMAP_11M 11
4339+#define RATE_BITMAP_12M 12
4340+#define RATE_BITMAP_18M 18
4341+#define RATE_BITMAP_22M 22
4342+#define RATE_BITMAP_24M 24
4343+#define RATE_BITMAP_33M 17
4344+#define RATE_BITMAP_36M 19
4345+#define RATE_BITMAP_48M 25
4346+#define RATE_BITMAP_54M 28
4347+
4348+#define RATE_AUTO 0
4349+#define RATE_1M 2
4350+#define RATE_2M 4
4351+#define RATE_5dot5M 11
4352+#define RATE_6M 12
4353+#define RATE_9M 18
4354+#define RATE_11M 22
4355+#define RATE_12M 24
4356+#define RATE_18M 36
4357+#define RATE_22M 44
4358+#define RATE_24M 48
4359+#define RATE_33M 66
4360+#define RATE_36M 72
4361+#define RATE_48M 96
4362+#define RATE_54M 108
4363+#define RATE_MAX 255
4364+
4365+//CAPABILITY
4366+#define CAPABILITY_ESS_BIT 0x0001
4367+#define CAPABILITY_IBSS_BIT 0x0002
4368+#define CAPABILITY_CF_POLL_BIT 0x0004
4369+#define CAPABILITY_CF_POLL_REQ_BIT 0x0008
4370+#define CAPABILITY_PRIVACY_BIT 0x0010
4371+#define CAPABILITY_SHORT_PREAMBLE_BIT 0x0020
4372+#define CAPABILITY_PBCC_BIT 0x0040
4373+#define CAPABILITY_CHAN_AGILITY_BIT 0x0080
4374+#define CAPABILITY_SHORT_SLOT_TIME_BIT 0x0400
4375+#define CAPABILITY_DSSS_OFDM_BIT 0x2000
4376+
4377+
4378+struct Capability_Information_Element
4379+{
4380+ union
4381+ {
4382+ u16 __attribute__ ((packed)) wValue;
4383+ #ifdef _BIG_ENDIAN_ //20060926 add by anson's endian
4384+ struct _Capability
4385+ {
4386+ //-- 11G --
4387+ u8 Reserved3 : 2;
4388+ u8 DSSS_OFDM : 1;
4389+ u8 Reserved2 : 2;
4390+ u8 Short_Slot_Time : 1;
4391+ u8 Reserved1 : 2;
4392+ u8 Channel_Agility : 1;
4393+ u8 PBCC : 1;
4394+ u8 ShortPreamble : 1;
4395+ u8 CF_Privacy : 1;
4396+ u8 CF_Poll_Request : 1;
4397+ u8 CF_Pollable : 1;
4398+ u8 IBSS : 1;
4399+ u8 ESS : 1;
4400+ } __attribute__ ((packed)) Capability;
4401+ #else
4402+ struct _Capability
4403+ {
4404+ u8 ESS : 1;
4405+ u8 IBSS : 1;
4406+ u8 CF_Pollable : 1;
4407+ u8 CF_Poll_Request : 1;
4408+ u8 CF_Privacy : 1;
4409+ u8 ShortPreamble : 1;
4410+ u8 PBCC : 1;
4411+ u8 Channel_Agility : 1;
4412+ u8 Reserved1 : 2;
4413+ //-- 11G --
4414+ u8 Short_Slot_Time : 1;
4415+ u8 Reserved2 : 2;
4416+ u8 DSSS_OFDM : 1;
4417+ u8 Reserved3 : 2;
4418+ } __attribute__ ((packed)) Capability;
4419+ #endif
4420+ }__attribute__ ((packed)) ;
4421+}__attribute__ ((packed));
4422+
4423+struct FH_Parameter_Set_Element
4424+{
4425+ u8 Element_ID;
4426+ u8 Length;
4427+ u8 Dwell_Time[2];
4428+ u8 Hop_Set;
4429+ u8 Hop_Pattern;
4430+ u8 Hop_Index;
4431+};
4432+
4433+struct DS_Parameter_Set_Element
4434+{
4435+ u8 Element_ID;
4436+ u8 Length;
4437+ u8 Current_Channel;
4438+};
4439+
4440+struct Supported_Rates_Element
4441+{
4442+ u8 Element_ID;
4443+ u8 Length;
4444+ u8 SupportedRates[8];
4445+}__attribute__ ((packed));
4446+
4447+struct SSID_Element
4448+{
4449+ u8 Element_ID;
4450+ u8 Length;
4451+ u8 SSID[32];
4452+}__attribute__ ((packed)) ;
4453+
4454+struct CF_Parameter_Set_Element
4455+{
4456+ u8 Element_ID;
4457+ u8 Length;
4458+ u8 CFP_Count;
4459+ u8 CFP_Period;
4460+ u8 CFP_MaxDuration[2]; // in Time Units
4461+ u8 CFP_DurRemaining[2]; // in time units
4462+};
4463+
4464+struct TIM_Element
4465+{
4466+ u8 Element_ID;
4467+ u8 Length;
4468+ u8 DTIM_Count;
4469+ u8 DTIM_Period;
4470+ u8 Bitmap_Control;
4471+ u8 Partial_Virtual_Bitmap[251];
4472+};
4473+
4474+struct IBSS_Parameter_Set_Element
4475+{
4476+ u8 Element_ID;
4477+ u8 Length;
4478+ u8 ATIM_Window[2];
4479+};
4480+
4481+struct Challenge_Text_Element
4482+{
4483+ u8 Element_ID;
4484+ u8 Length;
4485+ u8 Challenge_Text[253];
4486+};
4487+
4488+struct PHY_Parameter_Set_Element
4489+{
4490+// int aSlotTime;
4491+// int aSifsTime;
4492+ s32 aCCATime;
4493+ s32 aRxTxTurnaroundTime;
4494+ s32 aTxPLCPDelay;
4495+ s32 RxPLCPDelay;
4496+ s32 aRxTxSwitchTime;
4497+ s32 aTxRampOntime;
4498+ s32 aTxRampOffTime;
4499+ s32 aTxRFDelay;
4500+ s32 aRxRFDelay;
4501+ s32 aAirPropagationTime;
4502+ s32 aMACProcessingDelay;
4503+ s32 aPreambleLength;
4504+ s32 aPLCPHeaderLength;
4505+ s32 aMPDUDurationFactor;
4506+ s32 aMPDUMaxLength;
4507+// int aCWmin;
4508+// int aCWmax;
4509+};
4510+
4511+//-- 11G --
4512+struct ERP_Information_Element
4513+{
4514+ u8 Element_ID;
4515+ u8 Length;
4516+ #ifdef _BIG_ENDIAN_ //20060926 add by anson's endian
4517+ u8 Reserved:5; //20060926 add by anson
4518+ u8 Barker_Preamble_Mode:1;
4519+ u8 Use_Protection:1;
4520+ u8 NonERP_Present:1;
4521+ #else
4522+ u8 NonERP_Present:1;
4523+ u8 Use_Protection:1;
4524+ u8 Barker_Preamble_Mode:1;
4525+ u8 Reserved:5;
4526+ #endif
4527+};
4528+
4529+struct Extended_Supported_Rates_Element
4530+{
4531+ u8 Element_ID;
4532+ u8 Length;
4533+ u8 ExtendedSupportedRates[255];
4534+}__attribute__ ((packed));
4535+
4536+//WPA(802.11i draft 3.0)
4537+#define VERSION_WPA 1
4538+#ifdef _WPA2_
4539+#define VERSION_WPA2 1
4540+#endif //end def _WPA2_
4541+#define OUI_WPA 0x00F25000 //WPA2.0 OUI=00:50:F2, the MSB is reserved for suite type
4542+#ifdef _WPA2_
4543+#define OUI_WPA2 0x00AC0F00 // for wpa2 change to 0x00ACOF04 by Ws 26/04/04
4544+#endif //end def _WPA2_
4545+
4546+#define OUI_WPA_ADDITIONAL 0x01
4547+#define WLAN_MIN_RSN_WPA_LENGTH 6 //added by ws 09/10/04
4548+#ifdef _WPA2_
4549+#define WLAN_MIN_RSN_WPA2_LENGTH 2 // Fix to 2 09/14/05
4550+#endif //end def _WPA2_
4551+
4552+#define oui_wpa (u32)(OUI_WPA|OUI_WPA_ADDITIONAL)
4553+
4554+#define WPA_OUI_BIG ((u32) 0x01F25000)//added by ws 09/23/04
4555+#define WPA_OUI_LITTLE ((u32) 0x01F25001)//added by ws 09/23/04
4556+
4557+#define WPA_WPS_OUI cpu_to_le32(0x04F25000) // 20061108 For WPS. It's little endian. Big endian is 0x0050F204
4558+
4559+//-----WPA2-----
4560+#ifdef _WPA2_
4561+#define WPA2_OUI_BIG ((u32)0x01AC0F00)
4562+#define WPA2_OUI_LITTLE ((u32)0x01AC0F01)
4563+#endif //end def _WPA2_
4564+
4565+//Authentication suite
4566+#define OUI_AUTH_WPA_NONE 0x00 //for WPA_NONE
4567+#define OUI_AUTH_8021X 0x01
4568+#define OUI_AUTH_PSK 0x02
4569+//Cipher suite
4570+#define OUI_CIPHER_GROUP_KEY 0x00 //added by ws 05/21/04
4571+#define OUI_CIPHER_WEP_40 0x01
4572+#define OUI_CIPHER_TKIP 0x02
4573+#define OUI_CIPHER_CCMP 0x04
4574+#define OUI_CIPHER_WEP_104 0x05
4575+
4576+typedef struct _SUITE_SELECTOR_
4577+{
4578+ union
4579+ {
4580+ u8 Value[4];
4581+ struct _SUIT_
4582+ {
4583+ u8 OUI[3];
4584+ u8 Type;
4585+ }SuitSelector;
4586+ };
4587+}SUITE_SELECTOR;
4588+
4589+//-- WPA --
4590+struct RSN_Information_Element
4591+{
4592+ u8 Element_ID;
4593+ u8 Length;
4594+ UNALIGNED SUITE_SELECTOR OuiWPAAdditional;//WPA version 2.0 additional field, and should be 00:50:F2:01
4595+ u16 Version;
4596+ SUITE_SELECTOR GroupKeySuite;
4597+ u16 PairwiseKeySuiteCount;
4598+ SUITE_SELECTOR PairwiseKeySuite[1];
4599+}__attribute__ ((packed));
4600+struct RSN_Auth_Sub_Information_Element
4601+{
4602+ u16 AuthKeyMngtSuiteCount;
4603+ SUITE_SELECTOR AuthKeyMngtSuite[1];
4604+}__attribute__ ((packed));
4605+
4606+//-- WPA2 --
4607+struct RSN_Capability_Element
4608+{
4609+ union
4610+ {
4611+ u16 __attribute__ ((packed)) wValue;
4612+ #ifdef _BIG_ENDIAN_ //20060927 add by anson's endian
4613+ struct _RSN_Capability
4614+ {
4615+ u16 __attribute__ ((packed)) Reserved2 : 8; // 20051201
4616+ u16 __attribute__ ((packed)) Reserved1 : 2;
4617+ u16 __attribute__ ((packed)) GTK_Replay_Counter : 2;
4618+ u16 __attribute__ ((packed)) PTK_Replay_Counter : 2;
4619+ u16 __attribute__ ((packed)) No_Pairwise : 1;
4620+ u16 __attribute__ ((packed)) Pre_Auth : 1;
4621+ }__attribute__ ((packed)) RSN_Capability;
4622+ #else
4623+ struct _RSN_Capability
4624+ {
4625+ u16 __attribute__ ((packed)) Pre_Auth : 1;
4626+ u16 __attribute__ ((packed)) No_Pairwise : 1;
4627+ u16 __attribute__ ((packed)) PTK_Replay_Counter : 2;
4628+ u16 __attribute__ ((packed)) GTK_Replay_Counter : 2;
4629+ u16 __attribute__ ((packed)) Reserved1 : 2;
4630+ u16 __attribute__ ((packed)) Reserved2 : 8; // 20051201
4631+ }__attribute__ ((packed)) RSN_Capability;
4632+ #endif
4633+
4634+ }__attribute__ ((packed)) ;
4635+}__attribute__ ((packed)) ;
4636+
4637+#ifdef _WPA2_
4638+typedef struct _PMKID
4639+{
4640+ u8 pValue[16];
4641+}PMKID;
4642+
4643+struct WPA2_RSN_Information_Element
4644+{
4645+ u8 Element_ID;
4646+ u8 Length;
4647+ u16 Version;
4648+ SUITE_SELECTOR GroupKeySuite;
4649+ u16 PairwiseKeySuiteCount;
4650+ SUITE_SELECTOR PairwiseKeySuite[1];
4651+
4652+}__attribute__ ((packed));
4653+
4654+struct WPA2_RSN_Auth_Sub_Information_Element
4655+{
4656+ u16 AuthKeyMngtSuiteCount;
4657+ SUITE_SELECTOR AuthKeyMngtSuite[1];
4658+}__attribute__ ((packed));
4659+
4660+
4661+struct PMKID_Information_Element
4662+{
4663+ u16 PMKID_Count;
4664+ PMKID pmkid [16] ;
4665+}__attribute__ ((packed));
4666+
4667+#endif //enddef _WPA2_
4668+//============================================================
4669+// MAC Frame structure (different type) and subfield structure
4670+//============================================================
4671+struct MAC_frame_control
4672+{
4673+ u8 mac_frame_info; // a combination of the [Protocol Version, Control Type, Control Subtype]
4674+ #ifdef _BIG_ENDIAN_ //20060927 add by anson's endian
4675+ u8 order:1;
4676+ u8 WEP:1;
4677+ u8 more_data:1;
4678+ u8 pwr_mgt:1;
4679+ u8 retry:1;
4680+ u8 more_frag:1;
4681+ u8 from_ds:1;
4682+ u8 to_ds:1;
4683+ #else
4684+ u8 to_ds:1;
4685+ u8 from_ds:1;
4686+ u8 more_frag:1;
4687+ u8 retry:1;
4688+ u8 pwr_mgt:1;
4689+ u8 more_data:1;
4690+ u8 WEP:1;
4691+ u8 order:1;
4692+ #endif
4693+} __attribute__ ((packed));
4694+
4695+struct Management_Frame {
4696+ struct MAC_frame_control frame_control; // 2B, ToDS,FromDS,MoreFrag,MoreData,Order=0
4697+ u16 duration;
4698+ u8 DA[MAC_ADDR_LENGTH]; // Addr1
4699+ u8 SA[MAC_ADDR_LENGTH]; // Addr2
4700+ u8 BSSID[MAC_ADDR_LENGTH]; // Addr3
4701+ u16 Sequence_Control;
4702+ // Management Frame Body <= 325 bytes
4703+ // FCS 4 bytes
4704+}__attribute__ ((packed));
4705+
4706+// SW-MAC don't Tx/Rx Control-Frame, HW-MAC do it.
4707+struct Control_Frame {
4708+ struct MAC_frame_control frame_control; // ToDS,FromDS,MoreFrag,Retry,MoreData,WEP,Order=0
4709+ u16 duration;
4710+ u8 RA[MAC_ADDR_LENGTH];
4711+ u8 TA[MAC_ADDR_LENGTH];
4712+ u16 FCS;
4713+}__attribute__ ((packed));
4714+
4715+struct Data_Frame {
4716+ struct MAC_frame_control frame_control;
4717+ u16 duration;
4718+ u8 Addr1[MAC_ADDR_LENGTH];
4719+ u8 Addr2[MAC_ADDR_LENGTH];
4720+ u8 Addr3[MAC_ADDR_LENGTH];
4721+ u16 Sequence_Control;
4722+ u8 Addr4[MAC_ADDR_LENGTH]; // only exist when ToDS=FromDS=1
4723+ // Data Frame Body <= 2312
4724+ // FCS
4725+}__attribute__ ((packed));
4726+
4727+struct Disassociation_Frame_Body
4728+{
4729+ u16 reasonCode;
4730+}__attribute__ ((packed));
4731+
4732+struct Association_Request_Frame_Body
4733+{
4734+ u16 capability_information;
4735+ u16 listenInterval;
4736+ u8 Current_AP_Address[MAC_ADDR_LENGTH];//for reassociation only
4737+ // SSID (2+32 bytes)
4738+ // Supported_Rates (2+8 bytes)
4739+}__attribute__ ((packed));
4740+
4741+struct Association_Response_Frame_Body
4742+{
4743+ u16 capability_information;
4744+ u16 statusCode;
4745+ u16 Association_ID;
4746+ struct Supported_Rates_Element supportedRates;
4747+}__attribute__ ((packed));
4748+
4749+/*struct Reassociation_Request_Frame_Body
4750+{
4751+ u16 capability_information;
4752+ u16 listenInterval;
4753+ u8 Current_AP_Address[MAC_ADDR_LENGTH];
4754+ // SSID (2+32 bytes)
4755+ // Supported_Rates (2+8 bytes)
4756+};*/
4757+// eliminated by WS 07/22/04 comboined with associateion request frame.
4758+
4759+struct Reassociation_Response_Frame_Body
4760+{
4761+ u16 capability_information;
4762+ u16 statusCode;
4763+ u16 Association_ID;
4764+ struct Supported_Rates_Element supportedRates;
4765+}__attribute__ ((packed));
4766+
4767+struct Deauthentication_Frame_Body
4768+{
4769+ u16 reasonCode;
4770+}__attribute__ ((packed));
4771+
4772+
4773+struct Probe_Response_Frame_Body
4774+{
4775+ u16 Timestamp;
4776+ u16 Beacon_Interval;
4777+ u16 Capability_Information;
4778+ // SSID
4779+ // Supported_Rates
4780+ // PHY parameter Set (DS Parameters)
4781+ // CF parameter Set
4782+ // IBSS parameter Set
4783+}__attribute__ ((packed));
4784+
4785+struct Authentication_Frame_Body
4786+{
4787+ u16 algorithmNumber;
4788+ u16 sequenceNumber;
4789+ u16 statusCode;
4790+ // NB: don't include ChallengeText in this structure
4791+ // struct Challenge_Text_Element sChallengeTextElement; // wkchen added
4792+}__attribute__ ((packed));
4793+
4794+
4795+#endif // _MAC_Structure_H_
4796+
4797+
4798diff --git a/drivers/staging/winbond/mds.c b/drivers/staging/winbond/mds.c
4799new file mode 100644
4800index 0000000..8ce6389
4801--- /dev/null
4802+++ b/drivers/staging/winbond/mds.c
4803@@ -0,0 +1,630 @@
4804+#include "os_common.h"
4805+
4806+void
4807+Mds_reset_descriptor(PADAPTER Adapter)
4808+{
4809+ PMDS pMds = &Adapter->Mds;
4810+
4811+ pMds->TxPause = 0;
4812+ pMds->TxThreadCount = 0;
4813+ pMds->TxFillIndex = 0;
4814+ pMds->TxDesIndex = 0;
4815+ pMds->ScanTxPause = 0;
4816+ memset(pMds->TxOwner, 0, ((MAX_USB_TX_BUFFER_NUMBER + 3) & ~0x03));
4817+}
4818+
4819+unsigned char
4820+Mds_initial(PADAPTER Adapter)
4821+{
4822+ PMDS pMds = &Adapter->Mds;
4823+
4824+ pMds->TxPause = FALSE;
4825+ pMds->TxRTSThreshold = DEFAULT_RTSThreshold;
4826+ pMds->TxFragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD;
4827+
4828+ vRxTimerInit(Adapter);//for WPA countermeasure
4829+
4830+ return hal_get_tx_buffer( &Adapter->sHwData, &pMds->pTxBuffer );
4831+}
4832+
4833+void
4834+Mds_Destroy(PADAPTER Adapter)
4835+{
4836+ vRxTimerStop(Adapter);
4837+}
4838+
4839+void
4840+Mds_Tx(PADAPTER Adapter)
4841+{
4842+ phw_data_t pHwData = &Adapter->sHwData;
4843+ PMDS pMds = &Adapter->Mds;
4844+ DESCRIPTOR TxDes;
4845+ PDESCRIPTOR pTxDes = &TxDes;
4846+ PUCHAR XmitBufAddress;
4847+ u16 XmitBufSize, PacketSize, stmp, CurrentSize, FragmentThreshold;
4848+ u8 FillIndex, TxDesIndex, FragmentCount, FillCount;
4849+ unsigned char BufferFilled = FALSE, MICAdd = 0;
4850+
4851+
4852+ if (pMds->TxPause)
4853+ return;
4854+ if (!hal_driver_init_OK(pHwData))
4855+ return;
4856+
4857+ //Only one thread can be run here
4858+ if (!OS_ATOMIC_INC( Adapter, &pMds->TxThreadCount) == 1)
4859+ goto cleanup;
4860+
4861+ // Start to fill the data
4862+ do {
4863+ FillIndex = pMds->TxFillIndex;
4864+ if (pMds->TxOwner[FillIndex]) { // Is owned by software 0:Yes 1:No
4865+#ifdef _PE_TX_DUMP_
4866+ WBDEBUG(("[Mds_Tx] Tx Owner is H/W.\n"));
4867+#endif
4868+ break;
4869+ }
4870+
4871+ XmitBufAddress = pMds->pTxBuffer + (MAX_USB_TX_BUFFER * FillIndex); //Get buffer
4872+ XmitBufSize = 0;
4873+ FillCount = 0;
4874+ do {
4875+ PacketSize = Adapter->sMlmeFrame.len;
4876+ if (!PacketSize)
4877+ break;
4878+
4879+ //For Check the buffer resource
4880+ FragmentThreshold = CURRENT_FRAGMENT_THRESHOLD;
4881+ //931130.5.b
4882+ FragmentCount = PacketSize/FragmentThreshold + 1;
4883+ stmp = PacketSize + FragmentCount*32 + 8;//931130.5.c 8:MIC
4884+ if ((XmitBufSize + stmp) >= MAX_USB_TX_BUFFER) {
4885+ printk("[Mds_Tx] Excess max tx buffer.\n");
4886+ break; // buffer is not enough
4887+ }
4888+
4889+
4890+ //
4891+ // Start transmitting
4892+ //
4893+ BufferFilled = TRUE;
4894+
4895+ /* Leaves first u8 intact */
4896+ memset((PUCHAR)pTxDes + 1, 0, sizeof(DESCRIPTOR) - 1);
4897+
4898+ TxDesIndex = pMds->TxDesIndex;//Get the current ID
4899+ pTxDes->Descriptor_ID = TxDesIndex;
4900+ pMds->TxDesFrom[ TxDesIndex ] = 2;//Storing the information of source comming from
4901+ pMds->TxDesIndex++;
4902+ pMds->TxDesIndex %= MAX_USB_TX_DESCRIPTOR;
4903+
4904+ MLME_GetNextPacket( Adapter, pTxDes );
4905+
4906+ // Copy header. 8byte USB + 24byte 802.11Hdr. Set TxRate, Preamble type
4907+ Mds_HeaderCopy( Adapter, pTxDes, XmitBufAddress );
4908+
4909+ // For speed up Key setting
4910+ if (pTxDes->EapFix) {
4911+#ifdef _PE_TX_DUMP_
4912+ WBDEBUG(("35: EPA 4th frame detected. Size = %d\n", PacketSize));
4913+#endif
4914+ pHwData->IsKeyPreSet = 1;
4915+ }
4916+
4917+ // Copy (fragment) frame body, and set USB, 802.11 hdr flag
4918+ CurrentSize = Mds_BodyCopy(Adapter, pTxDes, XmitBufAddress);
4919+
4920+ // Set RTS/CTS and Normal duration field into buffer
4921+ Mds_DurationSet(Adapter, pTxDes, XmitBufAddress);
4922+
4923+ //
4924+ // Calculation MIC from buffer which maybe fragment, then fill into temporary address 8 byte
4925+ // 931130.5.e
4926+ if (MICAdd)
4927+ Mds_MicFill( Adapter, pTxDes, XmitBufAddress );
4928+
4929+ //Shift to the next address
4930+ XmitBufSize += CurrentSize;
4931+ XmitBufAddress += CurrentSize;
4932+
4933+#ifdef _IBSS_BEACON_SEQ_STICK_
4934+ if ((XmitBufAddress[ DOT_11_DA_OFFSET+8 ] & 0xfc) != MAC_SUBTYPE_MNGMNT_PROBE_REQUEST) // +8 for USB hdr
4935+#endif
4936+ pMds->TxToggle = TRUE;
4937+
4938+ // Get packet to transmit completed, 1:TESTSTA 2:MLME 3: Ndis data
4939+ MLME_SendComplete(Adapter, 0, TRUE);
4940+
4941+ // Software TSC count 20060214
4942+ pMds->TxTsc++;
4943+ if (pMds->TxTsc == 0)
4944+ pMds->TxTsc_2++;
4945+
4946+ FillCount++; // 20060928
4947+ } while (HAL_USB_MODE_BURST(pHwData)); // End of multiple MSDU copy loop. FALSE = single TRUE = multiple sending
4948+
4949+ // Move to the next one, if necessary
4950+ if (BufferFilled) {
4951+ // size setting
4952+ pMds->TxBufferSize[ FillIndex ] = XmitBufSize;
4953+
4954+ // 20060928 set Tx count
4955+ pMds->TxCountInBuffer[FillIndex] = FillCount;
4956+
4957+ // Set owner flag
4958+ pMds->TxOwner[FillIndex] = 1;
4959+
4960+ pMds->TxFillIndex++;
4961+ pMds->TxFillIndex %= MAX_USB_TX_BUFFER_NUMBER;
4962+ BufferFilled = FALSE;
4963+ } else
4964+ break;
4965+
4966+ if (!PacketSize) // No more pk for transmitting
4967+ break;
4968+
4969+ } while(TRUE);
4970+
4971+ //
4972+ // Start to send by lower module
4973+ //
4974+ if (!pHwData->IsKeyPreSet)
4975+ Wb35Tx_start(pHwData);
4976+
4977+ cleanup:
4978+ OS_ATOMIC_DEC( Adapter, &pMds->TxThreadCount );
4979+}
4980+
4981+void
4982+Mds_SendComplete(PADAPTER Adapter, PT02_DESCRIPTOR pT02)
4983+{
4984+ PMDS pMds = &Adapter->Mds;
4985+ phw_data_t pHwData = &Adapter->sHwData;
4986+ u8 PacketId = (u8)pT02->T02_Tx_PktID;
4987+ unsigned char SendOK = TRUE;
4988+ u8 RetryCount, TxRate;
4989+
4990+ if (pT02->T02_IgnoreResult) // Don't care the result
4991+ return;
4992+ if (pT02->T02_IsLastMpdu) {
4993+ //TODO: DTO -- get the retry count and fragment count
4994+ // Tx rate
4995+ TxRate = pMds->TxRate[ PacketId ][ 0 ];
4996+ RetryCount = (u8)pT02->T02_MPDU_Cnt;
4997+ if (pT02->value & FLAG_ERROR_TX_MASK) {
4998+ SendOK = FALSE;
4999+
5000+ if (pT02->T02_transmit_abort || pT02->T02_out_of_MaxTxMSDULiftTime) {
5001+ //retry error
5002+ pHwData->dto_tx_retry_count += (RetryCount+1);
5003+ //[for tx debug]
5004+ if (RetryCount<7)
5005+ pHwData->tx_retry_count[RetryCount] += RetryCount;
5006+ else
5007+ pHwData->tx_retry_count[7] += RetryCount;
5008+ #ifdef _PE_STATE_DUMP_
5009+ WBDEBUG(("dto_tx_retry_count =%d\n", pHwData->dto_tx_retry_count));
5010+ #endif
5011+ MTO_SetTxCount(Adapter, TxRate, RetryCount);
5012+ }
5013+ pHwData->dto_tx_frag_count += (RetryCount+1);
5014+
5015+ //[for tx debug]
5016+ if (pT02->T02_transmit_abort_due_to_TBTT)
5017+ pHwData->tx_TBTT_start_count++;
5018+ if (pT02->T02_transmit_without_encryption_due_to_wep_on_false)
5019+ pHwData->tx_WepOn_false_count++;
5020+ if (pT02->T02_discard_due_to_null_wep_key)
5021+ pHwData->tx_Null_key_count++;
5022+ } else {
5023+ if (pT02->T02_effective_transmission_rate)
5024+ pHwData->tx_ETR_count++;
5025+ MTO_SetTxCount(Adapter, TxRate, RetryCount);
5026+ }
5027+
5028+ // Clear send result buffer
5029+ pMds->TxResult[ PacketId ] = 0;
5030+ } else
5031+ pMds->TxResult[ PacketId ] |= ((u16)(pT02->value & 0x0ffff));
5032+}
5033+
5034+void
5035+Mds_HeaderCopy(PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR TargetBuffer)
5036+{
5037+ PMDS pMds = &Adapter->Mds;
5038+ PUCHAR src_buffer = pDes->buffer_address[0];//931130.5.g
5039+ PT00_DESCRIPTOR pT00;
5040+ PT01_DESCRIPTOR pT01;
5041+ u16 stmp;
5042+ u8 i, ctmp1, ctmp2, ctmpf;
5043+ u16 FragmentThreshold = CURRENT_FRAGMENT_THRESHOLD;
5044+
5045+
5046+ stmp = pDes->buffer_total_size;
5047+ //
5048+ // Set USB header 8 byte
5049+ //
5050+ pT00 = (PT00_DESCRIPTOR)TargetBuffer;
5051+ TargetBuffer += 4;
5052+ pT01 = (PT01_DESCRIPTOR)TargetBuffer;
5053+ TargetBuffer += 4;
5054+
5055+ pT00->value = 0;// Clear
5056+ pT01->value = 0;// Clear
5057+
5058+ pT00->T00_tx_packet_id = pDes->Descriptor_ID;// Set packet ID
5059+ pT00->T00_header_length = 24;// Set header length
5060+ pT01->T01_retry_abort_ebable = 1;//921013 931130.5.h
5061+
5062+ // Key ID setup
5063+ pT01->T01_wep_id = 0;
5064+
5065+ FragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD; //Do not fragment
5066+ // Copy full data, the 1'st buffer contain all the data 931130.5.j
5067+ memcpy( TargetBuffer, src_buffer, DOT_11_MAC_HEADER_SIZE );// Copy header
5068+ pDes->buffer_address[0] = src_buffer + DOT_11_MAC_HEADER_SIZE;
5069+ pDes->buffer_total_size -= DOT_11_MAC_HEADER_SIZE;
5070+ pDes->buffer_size[0] = pDes->buffer_total_size;
5071+
5072+ // Set fragment threshold
5073+ FragmentThreshold -= (DOT_11_MAC_HEADER_SIZE + 4);
5074+ pDes->FragmentThreshold = FragmentThreshold;
5075+
5076+ // Set more frag bit
5077+ TargetBuffer[1] |= 0x04;// Set more frag bit
5078+
5079+ //
5080+ // Set tx rate
5081+ //
5082+ stmp = *(PUSHORT)(TargetBuffer+30); // 2n alignment address
5083+
5084+ //Use basic rate
5085+ ctmp1 = ctmpf = CURRENT_TX_RATE_FOR_MNG;
5086+
5087+ pDes->TxRate = ctmp1;
5088+ #ifdef _PE_TX_DUMP_
5089+ WBDEBUG(("Tx rate =%x\n", ctmp1));
5090+ #endif
5091+
5092+ pT01->T01_modulation_type = (ctmp1%3) ? 0 : 1;
5093+
5094+ for( i=0; i<2; i++ ) {
5095+ if( i == 1 )
5096+ ctmp1 = ctmpf;
5097+
5098+ pMds->TxRate[pDes->Descriptor_ID][i] = ctmp1; // backup the ta rate and fall back rate
5099+
5100+ if( ctmp1 == 108) ctmp2 = 7;
5101+ else if( ctmp1 == 96 ) ctmp2 = 6; // Rate convert for USB
5102+ else if( ctmp1 == 72 ) ctmp2 = 5;
5103+ else if( ctmp1 == 48 ) ctmp2 = 4;
5104+ else if( ctmp1 == 36 ) ctmp2 = 3;
5105+ else if( ctmp1 == 24 ) ctmp2 = 2;
5106+ else if( ctmp1 == 18 ) ctmp2 = 1;
5107+ else if( ctmp1 == 12 ) ctmp2 = 0;
5108+ else if( ctmp1 == 22 ) ctmp2 = 3;
5109+ else if( ctmp1 == 11 ) ctmp2 = 2;
5110+ else if( ctmp1 == 4 ) ctmp2 = 1;
5111+ else ctmp2 = 0; // if( ctmp1 == 2 ) or default
5112+
5113+ if( i == 0 )
5114+ pT01->T01_transmit_rate = ctmp2;
5115+ else
5116+ pT01->T01_fall_back_rate = ctmp2;
5117+ }
5118+
5119+ //
5120+ // Set preamble type
5121+ //
5122+ if ((pT01->T01_modulation_type == 0) && (pT01->T01_transmit_rate == 0)) // RATE_1M
5123+ pDes->PreambleMode = WLAN_PREAMBLE_TYPE_LONG;
5124+ else
5125+ pDes->PreambleMode = CURRENT_PREAMBLE_MODE;
5126+ pT01->T01_plcp_header_length = pDes->PreambleMode; // Set preamble
5127+
5128+}
5129+
5130+// The function return the 4n size of usb pk
5131+u16
5132+Mds_BodyCopy(PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR TargetBuffer)
5133+{
5134+ PT00_DESCRIPTOR pT00;
5135+ PMDS pMds = &Adapter->Mds;
5136+ PUCHAR buffer, src_buffer, pctmp;
5137+ u16 Size = 0;
5138+ u16 SizeLeft, CopySize, CopyLeft, stmp;
5139+ u8 buf_index, FragmentCount = 0;
5140+
5141+
5142+ // Copy fragment body
5143+ buffer = TargetBuffer; // shift 8B usb + 24B 802.11
5144+ SizeLeft = pDes->buffer_total_size;
5145+ buf_index = pDes->buffer_start_index;
5146+
5147+ pT00 = (PT00_DESCRIPTOR)buffer;
5148+ while (SizeLeft) {
5149+ pT00 = (PT00_DESCRIPTOR)buffer;
5150+ CopySize = SizeLeft;
5151+ if (SizeLeft > pDes->FragmentThreshold) {
5152+ CopySize = pDes->FragmentThreshold;
5153+ pT00->T00_frame_length = 24 + CopySize;//Set USB length
5154+ } else
5155+ pT00->T00_frame_length = 24 + SizeLeft;//Set USB length
5156+
5157+ SizeLeft -= CopySize;
5158+
5159+ // 1 Byte operation
5160+ pctmp = (PUCHAR)( buffer + 8 + DOT_11_SEQUENCE_OFFSET );
5161+ *pctmp &= 0xf0;
5162+ *pctmp |= FragmentCount;//931130.5.m
5163+ if( !FragmentCount )
5164+ pT00->T00_first_mpdu = 1;
5165+
5166+ buffer += 32; // 8B usb + 24B 802.11 header
5167+ Size += 32;
5168+
5169+ // Copy into buffer
5170+ stmp = CopySize + 3;
5171+ stmp &= ~0x03;//4n Alignment
5172+ Size += stmp;// Current 4n offset of mpdu
5173+
5174+ while (CopySize) {
5175+ // Copy body
5176+ src_buffer = pDes->buffer_address[buf_index];
5177+ CopyLeft = CopySize;
5178+ if (CopySize >= pDes->buffer_size[buf_index]) {
5179+ CopyLeft = pDes->buffer_size[buf_index];
5180+
5181+ // Get the next buffer of descriptor
5182+ buf_index++;
5183+ buf_index %= MAX_DESCRIPTOR_BUFFER_INDEX;
5184+ } else {
5185+ PUCHAR pctmp = pDes->buffer_address[buf_index];
5186+ pctmp += CopySize;
5187+ pDes->buffer_address[buf_index] = pctmp;
5188+ pDes->buffer_size[buf_index] -= CopySize;
5189+ }
5190+
5191+ memcpy(buffer, src_buffer, CopyLeft);
5192+ buffer += CopyLeft;
5193+ CopySize -= CopyLeft;
5194+ }
5195+
5196+ // 931130.5.n
5197+ if (pMds->MicAdd) {
5198+ if (!SizeLeft) {
5199+ pMds->MicWriteAddress[ pMds->MicWriteIndex ] = buffer - pMds->MicAdd;
5200+ pMds->MicWriteSize[ pMds->MicWriteIndex ] = pMds->MicAdd;
5201+ pMds->MicAdd = 0;
5202+ }
5203+ else if( SizeLeft < 8 ) //931130.5.p
5204+ {
5205+ pMds->MicAdd = SizeLeft;
5206+ pMds->MicWriteAddress[ pMds->MicWriteIndex ] = buffer - ( 8 - SizeLeft );
5207+ pMds->MicWriteSize[ pMds->MicWriteIndex ] = 8 - SizeLeft;
5208+ pMds->MicWriteIndex++;
5209+ }
5210+ }
5211+
5212+ // Does it need to generate the new header for next mpdu?
5213+ if (SizeLeft) {
5214+ buffer = TargetBuffer + Size; // Get the next 4n start address
5215+ memcpy( buffer, TargetBuffer, 32 );//Copy 8B USB +24B 802.11
5216+ pT00 = (PT00_DESCRIPTOR)buffer;
5217+ pT00->T00_first_mpdu = 0;
5218+ }
5219+
5220+ FragmentCount++;
5221+ }
5222+
5223+ pT00->T00_last_mpdu = 1;
5224+ pT00->T00_IsLastMpdu = 1;
5225+ buffer = (PUCHAR)pT00 + 8; // +8 for USB hdr
5226+ buffer[1] &= ~0x04; // Clear more frag bit of 802.11 frame control
5227+ pDes->FragmentCount = FragmentCount; // Update the correct fragment number
5228+ return Size;
5229+}
5230+
5231+
5232+void
5233+Mds_DurationSet( PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR buffer )
5234+{
5235+ PT00_DESCRIPTOR pT00;
5236+ PT01_DESCRIPTOR pT01;
5237+ u16 Duration, NextBodyLen, OffsetSize;
5238+ u8 Rate, i;
5239+ unsigned char CTS_on = FALSE, RTS_on = FALSE;
5240+ PT00_DESCRIPTOR pNextT00;
5241+ u16 BodyLen;
5242+ unsigned char boGroupAddr = FALSE;
5243+
5244+
5245+ OffsetSize = pDes->FragmentThreshold + 32 + 3;
5246+ OffsetSize &= ~0x03;
5247+ Rate = pDes->TxRate >> 1;
5248+ if (!Rate)
5249+ Rate = 1;
5250+
5251+ pT00 = (PT00_DESCRIPTOR)buffer;
5252+ pT01 = (PT01_DESCRIPTOR)(buffer+4);
5253+ pNextT00 = (PT00_DESCRIPTOR)(buffer+OffsetSize);
5254+
5255+ if( buffer[ DOT_11_DA_OFFSET+8 ] & 0x1 ) // +8 for USB hdr
5256+ boGroupAddr = TRUE;
5257+
5258+ //========================================
5259+ // Set RTS/CTS mechanism
5260+ //========================================
5261+ if (!boGroupAddr)
5262+ {
5263+ //NOTE : If the protection mode is enabled and the MSDU will be fragmented,
5264+ // the tx rates of MPDUs will all be DSSS rates. So it will not use
5265+ // CTS-to-self in this case. CTS-To-self will only be used when without
5266+ // fragmentation. -- 20050112
5267+ BodyLen = (u16)pT00->T00_frame_length; //include 802.11 header
5268+ BodyLen += 4; //CRC
5269+
5270+ if( BodyLen >= CURRENT_RTS_THRESHOLD )
5271+ RTS_on = TRUE; // Using RTS
5272+ else
5273+ {
5274+ if( pT01->T01_modulation_type ) // Is using OFDM
5275+ {
5276+ if( CURRENT_PROTECT_MECHANISM ) // Is using protect
5277+ CTS_on = TRUE; // Using CTS
5278+ }
5279+ }
5280+ }
5281+
5282+ if( RTS_on || CTS_on )
5283+ {
5284+ if( pT01->T01_modulation_type) // Is using OFDM
5285+ {
5286+ //CTS duration
5287+ // 2 SIFS + DATA transmit time + 1 ACK
5288+ // ACK Rate : 24 Mega bps
5289+ // ACK frame length = 14 bytes
5290+ Duration = 2*DEFAULT_SIFSTIME +
5291+ 2*PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION +
5292+ ((BodyLen*8 + 22 + Rate*4 - 1)/(Rate*4))*Tsym +
5293+ ((112 + 22 + 95)/96)*Tsym;
5294+ }
5295+ else //DSSS
5296+ {
5297+ //CTS duration
5298+ // 2 SIFS + DATA transmit time + 1 ACK
5299+ // Rate : ?? Mega bps
5300+ // ACK frame length = 14 bytes
5301+ if( pT01->T01_plcp_header_length ) //long preamble
5302+ Duration = LONG_PREAMBLE_PLUS_PLCPHEADER_TIME*2;
5303+ else
5304+ Duration = SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME*2;
5305+
5306+ Duration += ( ((BodyLen + 14)*8 + Rate-1) / Rate +
5307+ DEFAULT_SIFSTIME*2 );
5308+ }
5309+
5310+ if( RTS_on )
5311+ {
5312+ if( pT01->T01_modulation_type ) // Is using OFDM
5313+ {
5314+ //CTS + 1 SIFS + CTS duration
5315+ //CTS Rate : 24 Mega bps
5316+ //CTS frame length = 14 bytes
5317+ Duration += (DEFAULT_SIFSTIME +
5318+ PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION +
5319+ ((112 + 22 + 95)/96)*Tsym);
5320+ }
5321+ else
5322+ {
5323+ //CTS + 1 SIFS + CTS duration
5324+ //CTS Rate : ?? Mega bps
5325+ //CTS frame length = 14 bytes
5326+ if( pT01->T01_plcp_header_length ) //long preamble
5327+ Duration += LONG_PREAMBLE_PLUS_PLCPHEADER_TIME;
5328+ else
5329+ Duration += SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME;
5330+
5331+ Duration += ( ((112 + Rate-1) / Rate) + DEFAULT_SIFSTIME );
5332+ }
5333+ }
5334+
5335+ // Set the value into USB descriptor
5336+ pT01->T01_add_rts = RTS_on ? 1 : 0;
5337+ pT01->T01_add_cts = CTS_on ? 1 : 0;
5338+ pT01->T01_rts_cts_duration = Duration;
5339+ }
5340+
5341+ //=====================================
5342+ // Fill the more fragment descriptor
5343+ //=====================================
5344+ if( boGroupAddr )
5345+ Duration = 0;
5346+ else
5347+ {
5348+ for( i=pDes->FragmentCount-1; i>0; i-- )
5349+ {
5350+ NextBodyLen = (u16)pNextT00->T00_frame_length;
5351+ NextBodyLen += 4; //CRC
5352+
5353+ if( pT01->T01_modulation_type )
5354+ {
5355+ //OFDM
5356+ // data transmit time + 3 SIFS + 2 ACK
5357+ // Rate : ??Mega bps
5358+ // ACK frame length = 14 bytes, tx rate = 24M
5359+ Duration = PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION * 3;
5360+ Duration += (((NextBodyLen*8 + 22 + Rate*4 - 1)/(Rate*4)) * Tsym +
5361+ (((2*14)*8 + 22 + 95)/96)*Tsym +
5362+ DEFAULT_SIFSTIME*3);
5363+ }
5364+ else
5365+ {
5366+ //DSSS
5367+ // data transmit time + 2 ACK + 3 SIFS
5368+ // Rate : ??Mega bps
5369+ // ACK frame length = 14 bytes
5370+ //TODO :
5371+ if( pT01->T01_plcp_header_length ) //long preamble
5372+ Duration = LONG_PREAMBLE_PLUS_PLCPHEADER_TIME*3;
5373+ else
5374+ Duration = SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME*3;
5375+
5376+ Duration += ( ((NextBodyLen + (2*14))*8 + Rate-1) / Rate +
5377+ DEFAULT_SIFSTIME*3 );
5378+ }
5379+
5380+ ((PUSHORT)buffer)[5] = cpu_to_le16(Duration);// 4 USHOR for skip 8B USB, 2USHORT=FC + Duration
5381+
5382+ //----20061009 add by anson's endian
5383+ pNextT00->value = cpu_to_le32(pNextT00->value);
5384+ pT01->value = cpu_to_le32( pT01->value );
5385+ //----end 20061009 add by anson's endian
5386+
5387+ buffer += OffsetSize;
5388+ pT01 = (PT01_DESCRIPTOR)(buffer+4);
5389+ if (i != 1) //The last fragment will not have the next fragment
5390+ pNextT00 = (PT00_DESCRIPTOR)(buffer+OffsetSize);
5391+ }
5392+
5393+ //=====================================
5394+ // Fill the last fragment descriptor
5395+ //=====================================
5396+ if( pT01->T01_modulation_type )
5397+ {
5398+ //OFDM
5399+ // 1 SIFS + 1 ACK
5400+ // Rate : 24 Mega bps
5401+ // ACK frame length = 14 bytes
5402+ Duration = PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION;
5403+ //The Tx rate of ACK use 24M
5404+ Duration += (((112 + 22 + 95)/96)*Tsym + DEFAULT_SIFSTIME );
5405+ }
5406+ else
5407+ {
5408+ // DSSS
5409+ // 1 ACK + 1 SIFS
5410+ // Rate : ?? Mega bps
5411+ // ACK frame length = 14 bytes(112 bits)
5412+ if( pT01->T01_plcp_header_length ) //long preamble
5413+ Duration = LONG_PREAMBLE_PLUS_PLCPHEADER_TIME;
5414+ else
5415+ Duration = SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME;
5416+
5417+ Duration += ( (112 + Rate-1)/Rate + DEFAULT_SIFSTIME );
5418+ }
5419+ }
5420+
5421+ ((PUSHORT)buffer)[5] = cpu_to_le16(Duration);// 4 USHOR for skip 8B USB, 2USHORT=FC + Duration
5422+ pT00->value = cpu_to_le32(pT00->value);
5423+ pT01->value = cpu_to_le32(pT01->value);
5424+ //--end 20061009 add
5425+
5426+}
5427+
5428+void MDS_EthernetPacketReceive( PADAPTER Adapter, PRXLAYER1 pRxLayer1 )
5429+{
5430+ OS_RECEIVE_PACKET_INDICATE( Adapter, pRxLayer1 );
5431+}
5432+
5433+
5434diff --git a/drivers/staging/winbond/mds_f.h b/drivers/staging/winbond/mds_f.h
5435new file mode 100644
5436index 0000000..651188b
5437--- /dev/null
5438+++ b/drivers/staging/winbond/mds_f.h
5439@@ -0,0 +1,33 @@
5440+unsigned char Mds_initial( PADAPTER Adapter );
5441+void Mds_Destroy( PADAPTER Adapter );
5442+void Mds_Tx( PADAPTER Adapter );
5443+void Mds_HeaderCopy( PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR TargetBuffer );
5444+u16 Mds_BodyCopy( PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR TargetBuffer );
5445+void Mds_DurationSet( PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR TargetBuffer );
5446+void Mds_SendComplete( PADAPTER Adapter, PT02_DESCRIPTOR pT02 );
5447+void Mds_MpduProcess( PADAPTER Adapter, PDESCRIPTOR pRxDes );
5448+void Mds_reset_descriptor( PADAPTER Adapter );
5449+extern void DataDmp(u8 *pdata, u32 len, u32 offset);
5450+
5451+
5452+void vRxTimerInit(PWB32_ADAPTER Adapter);
5453+void vRxTimerStart(PWB32_ADAPTER Adapter, int timeout_value);
5454+void RxTimerHandler_1a( PADAPTER Adapter);
5455+void vRxTimerStop(PWB32_ADAPTER Adapter);
5456+void RxTimerHandler( void* SystemSpecific1,
5457+ PWB32_ADAPTER Adapter,
5458+ void* SystemSpecific2,
5459+ void* SystemSpecific3);
5460+
5461+
5462+// For Asynchronous indicating. The routine collocates with USB.
5463+void Mds_MsduProcess( PWB32_ADAPTER Adapter, PRXLAYER1 pRxLayer1, u8 SlotIndex);
5464+
5465+// For data frame sending 20060802
5466+u16 MDS_GetPacketSize( PADAPTER Adapter );
5467+void MDS_GetNextPacket( PADAPTER Adapter, PDESCRIPTOR pDes );
5468+void MDS_GetNextPacketComplete( PADAPTER Adapter, PDESCRIPTOR pDes );
5469+void MDS_SendResult( PADAPTER Adapter, u8 PacketId, unsigned char SendOK );
5470+void MDS_EthernetPacketReceive( PADAPTER Adapter, PRXLAYER1 pRxLayer1 );
5471+
5472+
5473diff --git a/drivers/staging/winbond/mds_s.h b/drivers/staging/winbond/mds_s.h
5474new file mode 100644
5475index 0000000..4738279
5476--- /dev/null
5477+++ b/drivers/staging/winbond/mds_s.h
5478@@ -0,0 +1,183 @@
5479+////////////////////////////////////////////////////////////////////////////////////////////////////////
5480+#define MAX_USB_TX_DESCRIPTOR 15 // IS89C35 ability
5481+#define MAX_USB_TX_BUFFER_NUMBER 4 // Virtual pre-buffer number of MAX_USB_TX_BUFFER
5482+#define MAX_USB_TX_BUFFER 4096 // IS89C35 ability 4n alignment is required for hardware
5483+
5484+#define MDS_EVENT_INDICATE( _A, _B, _F ) OS_EVENT_INDICATE( _A, _B, _F )
5485+#define AUTH_REQUEST_PAIRWISE_ERROR 0 // _F flag setting
5486+#define AUTH_REQUEST_GROUP_ERROR 1 // _F flag setting
5487+
5488+// For variable setting
5489+#define CURRENT_BSS_TYPE psBSS(psLOCAL->wConnectedSTAindex)->bBssType
5490+#define CURRENT_WEP_MODE psSME->_dot11PrivacyInvoked
5491+#define CURRENT_BSSID psBSS(psLOCAL->wConnectedSTAindex)->abBssID
5492+#define CURRENT_DESIRED_WPA_ENABLE ((psSME->bDesiredAuthMode==WPA_AUTH)||(psSME->bDesiredAuthMode==WPAPSK_AUTH))
5493+#ifdef _WPA2_
5494+#define CURRENT_DESIRED_WPA2_ENABLE ((psSME->bDesiredAuthMode==WPA2_AUTH)||(psSME->bDesiredAuthMode==WPA2PSK_AUTH))
5495+#endif //end def _WPA2_
5496+#define CURRENT_PAIRWISE_KEY_OK psSME->pairwise_key_ok
5497+//[20040712 WS]
5498+#define CURRENT_GROUP_KEY_OK psSME->group_key_ok
5499+#define CURRENT_PAIRWISE_KEY psSME->tx_mic_key
5500+#define CURRENT_GROUP_KEY psSME->group_tx_mic_key
5501+#define CURRENT_ENCRYPT_STATUS psSME->encrypt_status
5502+#define CURRENT_WEP_ID Adapter->sSmePara._dot11WEPDefaultKeyID
5503+#define CURRENT_CONTROL_PORT_BLOCK ( psSME->wpa_ok!=1 || (Adapter->Mds.boCounterMeasureBlock==1 && (CURRENT_ENCRYPT_STATUS==ENCRYPT_TKIP)) )
5504+#define CURRENT_FRAGMENT_THRESHOLD (Adapter->Mds.TxFragmentThreshold & ~0x1)
5505+#define CURRENT_PREAMBLE_MODE psLOCAL->boShortPreamble?WLAN_PREAMBLE_TYPE_SHORT:WLAN_PREAMBLE_TYPE_LONG
5506+#define CURRENT_LINK_ON OS_LINK_STATUS
5507+#define CURRENT_TX_RATE Adapter->sLocalPara.CurrentTxRate
5508+#define CURRENT_FALL_BACK_TX_RATE Adapter->sLocalPara.CurrentTxFallbackRate
5509+#define CURRENT_TX_RATE_FOR_MNG Adapter->sLocalPara.CurrentTxRateForMng
5510+#define CURRENT_PROTECT_MECHANISM psLOCAL->boProtectMechanism
5511+#define CURRENT_RTS_THRESHOLD Adapter->Mds.TxRTSThreshold
5512+
5513+#define MIB_GS_XMIT_OK_INC Adapter->sLocalPara.GS_XMIT_OK++
5514+#define MIB_GS_RCV_OK_INC Adapter->sLocalPara.GS_RCV_OK++
5515+#define MIB_GS_XMIT_ERROR_INC Adapter->sLocalPara.GS_XMIT_ERROR
5516+
5517+//---------- TX -----------------------------------
5518+#define ETHERNET_TX_DESCRIPTORS MAX_USB_TX_BUFFER_NUMBER
5519+
5520+//---------- RX ------------------------------------
5521+#define ETHERNET_RX_DESCRIPTORS 8 //It's not necessary to allocate more than 2 in sync indicate
5522+
5523+//================================================================
5524+// Configration default value
5525+//================================================================
5526+#define DEFAULT_MULTICASTLISTMAX 32 // standard
5527+#define DEFAULT_TX_BURSTLENGTH 3 // 32 Longwords
5528+#define DEFAULT_RX_BURSTLENGTH 3 // 32 Longwords
5529+#define DEFAULT_TX_THRESHOLD 0 // Full Packet
5530+#define DEFAULT_RX_THRESHOLD 0 // Full Packet
5531+#define DEFAULT_MAXTXRATE 6 // 11 Mbps (Long)
5532+#define DEFAULT_CHANNEL 3 // Chennel 3
5533+#define DEFAULT_RTSThreshold 2347 // Disable RTS
5534+//#define DEFAULT_PME 1 // Enable
5535+#define DEFAULT_PME 0 // Disable
5536+#define DEFAULT_SIFSTIME 10
5537+#define DEFAULT_ACKTIME_1ML 304 // 148+44+112 911220 by LCC
5538+#define DEFAULT_ACKTIME_2ML 248 // 148+44+56 911220 by LCC
5539+#define DEFAULT_FRAGMENT_THRESHOLD 2346 // No fragment
5540+#define DEFAULT_PREAMBLE_LENGTH 72
5541+#define DEFAULT_PLCPHEADERTIME_LENGTH 24
5542+
5543+/*------------------------------------------------------------------------
5544+ 0.96 sec since time unit of the R03 for the current, W89C32 is about 60ns
5545+ instead of 960 ns. This shall be fixed in the future W89C32
5546+ -------------------------------------------------------------------------*/
5547+#define DEFAULT_MAX_RECEIVE_TIME 16440000
5548+
5549+#define RX_BUF_SIZE 2352 // 600 // For 301 must be multiple of 8
5550+#define MAX_RX_DESCRIPTORS 18 // Rx Layer 2
5551+#define MAX_BUFFER_QUEUE 8 // The value is always equal 8 due to NDIS_PACKET's MiniportReserved field size
5552+
5553+
5554+// For brand-new rx system
5555+#define MDS_ID_IGNORE ETHERNET_RX_DESCRIPTORS
5556+
5557+// For Tx Packet status classify
5558+#define PACKET_FREE_TO_USE 0
5559+#define PACKET_COME_FROM_NDIS 0x08
5560+#define PACKET_COME_FROM_MLME 0x80
5561+#define PACKET_SEND_COMPLETE 0xff
5562+
5563+typedef struct _MDS
5564+{
5565+ // For Tx usage
5566+ u8 TxOwner[ ((MAX_USB_TX_BUFFER_NUMBER + 3) & ~0x03) ];
5567+ PUCHAR pTxBuffer;
5568+ u16 TxBufferSize[ ((MAX_USB_TX_BUFFER_NUMBER + 1) & ~0x01) ];
5569+ u8 TxDesFrom[ ((MAX_USB_TX_DESCRIPTOR + 3) & ~0x03) ];//931130.4.u // 1: MLME 2: NDIS control 3: NDIS data
5570+ u8 TxCountInBuffer[ ((MAX_USB_TX_DESCRIPTOR + 3) & ~0x03) ]; // 20060928
5571+
5572+ u8 TxFillIndex;//the next index of TxBuffer can be used
5573+ u8 TxDesIndex;//The next index of TxDes can be used
5574+ u8 ScanTxPause; //data Tx pause because the scanning is progressing, but probe request Tx won't.
5575+ u8 TxPause;//For pause the Mds_Tx modult
5576+
5577+ OS_ATOMIC TxThreadCount;//For thread counting 931130.4.v
5578+//950301 delete due to HW
5579+// OS_ATOMIC TxConcurrentCount;//931130.4.w
5580+
5581+ u16 TxResult[ ((MAX_USB_TX_DESCRIPTOR + 1) & ~0x01) ];//Collect the sending result of Mpdu
5582+
5583+ u8 MicRedundant[8]; // For tmp use
5584+ PUCHAR MicWriteAddress[2]; //The start address to fill the Mic, use 2 point due to Mic maybe fragment
5585+
5586+ u16 MicWriteSize[2]; //931130.4.x
5587+
5588+ u16 MicAdd; // If want to add the Mic, this variable equal to 8
5589+ u16 MicWriteIndex;//The number of MicWriteAddress 931130.4.y
5590+
5591+ u8 TxRate[ ((MAX_USB_TX_DESCRIPTOR+1)&~0x01) ][2]; // [0] current tx rate, [1] fall back rate
5592+ u8 TxInfo[ ((MAX_USB_TX_DESCRIPTOR+1)&~0x01) ]; //Store information for callback function
5593+
5594+ //WKCHEN added for scanning mechanism
5595+ u8 TxToggle; //It is TRUE if there are tx activities in some time interval
5596+ u8 Reserved_[3];
5597+
5598+ //---------- for Tx Parameter
5599+ u16 TxFragmentThreshold; // For frame body only
5600+ u16 TxRTSThreshold;
5601+
5602+ u32 MaxReceiveTime;//911220.3 Add
5603+
5604+ // depend on OS,
5605+ u32 MulticastListNo;
5606+ u32 PacketFilter; // Setting by NDIS, the current packet filter in use.
5607+ u8 MulticastAddressesArray[DEFAULT_MULTICASTLISTMAX][MAC_ADDR_LENGTH];
5608+
5609+ //COUNTERMEASURE
5610+ u8 bMICfailCount;
5611+ u8 boCounterMeasureBlock;
5612+ u8 reserved_4[2];
5613+
5614+ //NDIS_MINIPORT_TIMER nTimer;
5615+ OS_TIMER nTimer;
5616+
5617+ u32 TxTsc; // 20060214
5618+ u32 TxTsc_2; // 20060214
5619+
5620+} MDS, *PMDS;
5621+
5622+
5623+typedef struct _RxBuffer
5624+{
5625+ PUCHAR pBufferAddress; // Pointer the received data buffer.
5626+ u16 BufferSize;
5627+ u8 RESERVED;
5628+ u8 BufferIndex;// Only 1 byte
5629+} RXBUFFER, *PRXBUFFER;
5630+
5631+//
5632+// Reveive Layer 1 Format.
5633+//----------------------------
5634+typedef struct _RXLAYER1
5635+{
5636+ u16 SequenceNumber; // The sequence number of the last received packet.
5637+ u16 BufferTotalSize;
5638+
5639+ u32 InUsed;
5640+ u32 DecryptionMethod; // The desired defragment number of the next incoming packet.
5641+
5642+ u8 DeFragmentNumber;
5643+ u8 FrameType;
5644+ u8 TypeEncapsulated;
5645+ u8 BufferNumber;
5646+
5647+ u32 FirstFrameArrivedTime;
5648+
5649+ RXBUFFER BufferQueue[ MAX_BUFFER_QUEUE ];
5650+
5651+ u8 LastFrameType; // 20061004 for fix intel 3945 's bug
5652+ u8 RESERVED[3]; //@@ anson
5653+
5654+ /////////////////////////////////////////////////////////////////////////////////////////////
5655+ // For brand-new Rx system
5656+ u8 ReservedBuffer[ 2400 ];//If Buffer ID is reserved one, it must copy the data into this area
5657+ PUCHAR ReservedBufferPoint;// Point to the next availabe address of reserved buffer
5658+
5659+}RXLAYER1, * PRXLAYER1;
5660+
5661+
5662diff --git a/drivers/staging/winbond/mlme_mib.h b/drivers/staging/winbond/mlme_mib.h
5663new file mode 100644
5664index 0000000..8975973
5665--- /dev/null
5666+++ b/drivers/staging/winbond/mlme_mib.h
5667@@ -0,0 +1,84 @@
5668+//============================================================================
5669+// MLMEMIB.H -
5670+//
5671+// Description:
5672+// Get and Set some of MLME MIB attributes.
5673+//
5674+// Revision history:
5675+// --------------------------------------------------------------------------
5676+// 20030117 PD43 Austin Liu
5677+// Initial release
5678+//
5679+// Copyright (c) 2003 Winbond Electronics Corp. All rights reserved.
5680+//============================================================================
5681+
5682+#ifndef _MLME_MIB_H
5683+#define _MLME_MIB_H
5684+
5685+//============================================================================
5686+// MLMESetExcludeUnencrypted --
5687+//
5688+// Description:
5689+// Set the dot11ExcludeUnencrypted value.
5690+//
5691+// Arguments:
5692+// Adapter - The pointer to the miniport adapter context.
5693+// ExUnencrypted - unsigned char type. The value to be set.
5694+//
5695+// Return values:
5696+// None.
5697+//============================================================================
5698+#define MLMESetExcludeUnencrypted(Adapter, ExUnencrypted) \
5699+{ \
5700+ (Adapter)->sLocalPara.ExcludeUnencrypted = ExUnencrypted; \
5701+}
5702+
5703+//============================================================================
5704+// MLMEGetExcludeUnencrypted --
5705+//
5706+// Description:
5707+// Get the dot11ExcludeUnencrypted value.
5708+//
5709+// Arguments:
5710+// Adapter - The pointer to the miniport adapter context.
5711+//
5712+// Return values:
5713+// unsigned char type. The current dot11ExcludeUnencrypted value.
5714+//============================================================================
5715+#define MLMEGetExcludeUnencrypted(Adapter) ((unsigned char) (Adapter)->sLocalPara.ExcludeUnencrypted)
5716+
5717+//============================================================================
5718+// MLMESetMaxReceiveLifeTime --
5719+//
5720+// Description:
5721+// Set the dot11MaxReceiveLifeTime value.
5722+//
5723+// Arguments:
5724+// Adapter - The pointer to the miniport adapter context.
5725+// ReceiveLifeTime- u32 type. The value to be set.
5726+//
5727+// Return values:
5728+// None.
5729+//============================================================================
5730+#define MLMESetMaxReceiveLifeTime(Adapter, ReceiveLifeTime) \
5731+{ \
5732+ (Adapter)->Mds.MaxReceiveTime = ReceiveLifeTime; \
5733+}
5734+
5735+//============================================================================
5736+// MLMESetMaxReceiveLifeTime --
5737+//
5738+// Description:
5739+// Get the dot11MaxReceiveLifeTime value.
5740+//
5741+// Arguments:
5742+// Adapter - The pointer to the miniport adapter context.
5743+//
5744+// Return values:
5745+// u32 type. The current dot11MaxReceiveLifeTime value.
5746+//============================================================================
5747+#define MLMEGetMaxReceiveLifeTime(Adapter) ((u32) (Adapter)->Mds.MaxReceiveTime)
5748+
5749+#endif
5750+
5751+
5752diff --git a/drivers/staging/winbond/mlme_s.h b/drivers/staging/winbond/mlme_s.h
5753new file mode 100644
5754index 0000000..58094f6
5755--- /dev/null
5756+++ b/drivers/staging/winbond/mlme_s.h
5757@@ -0,0 +1,195 @@
5758+//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
5759+// Mlme.h
5760+// Define the related definitions of MLME module
5761+// history -- 01/14/03' created
5762+//
5763+//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
5764+
5765+#define AUTH_REJECT_REASON_CHALLENGE_FAIL 1
5766+
5767+//====== the state of MLME module
5768+#define INACTIVE 0x0
5769+#define IDLE_SCAN 0x1
5770+
5771+//====== the state of MLME/ESS module
5772+#define STATE_1 0x2
5773+#define AUTH_REQ 0x3
5774+#define AUTH_WEP 0x4
5775+#define STATE_2 0x5
5776+#define ASSOC_REQ 0x6
5777+#define STATE_3 0x7
5778+
5779+//====== the state of MLME/IBSS module
5780+#define IBSS_JOIN_SYNC 0x8
5781+#define IBSS_AUTH_REQ 0x9
5782+#define IBSS_AUTH_CHANLGE 0xa
5783+#define IBSS_AUTH_WEP 0xb
5784+#define IBSS_AUTH_IND 0xc
5785+#define IBSS_STATE_2 0xd
5786+
5787+
5788+
5789+//=========================================
5790+//depend on D5C(MAC timing control 03 register): MaxTxMSDULifeTime default 0x80000us
5791+#define AUTH_FAIL_TIMEOUT 550
5792+#define ASSOC_FAIL_TIMEOUT 550
5793+#define REASSOC_FAIL_TIMEOUT 550
5794+
5795+
5796+
5797+//
5798+// MLME task global CONSTANTS, STRUCTURE, variables
5799+//
5800+
5801+
5802+/////////////////////////////////////////////////////////////
5803+// enum_ResultCode --
5804+// Result code returned from MLME to SME.
5805+//
5806+/////////////////////////////////////////////////////////////
5807+// PD43 20030829 Modifiled
5808+//#define SUCCESS 0
5809+#define MLME_SUCCESS 0 //follow spec.
5810+#define INVALID_PARAMETERS 1 //Not following spec.
5811+#define NOT_SUPPPORTED 2
5812+#define TIMEOUT 3
5813+#define TOO_MANY_SIMULTANEOUS_REQUESTS 4
5814+#define REFUSED 5
5815+#define BSS_ALREADY_STARTED_OR_JOINED 6
5816+#define TRANSMIT_FRAME_FAIL 7
5817+#define NO_BSS_FOUND 8
5818+#define RETRY 9
5819+#define GIVE_UP 10
5820+
5821+
5822+#define OPEN_AUTH 0
5823+#define SHARE_AUTH 1
5824+#define ANY_AUTH 2
5825+#define WPA_AUTH 3 //for WPA
5826+#define WPAPSK_AUTH 4
5827+#define WPANONE_AUTH 5
5828+///////////////////////////////////////////// added by ws 04/19/04
5829+#ifdef _WPA2_
5830+#define WPA2_AUTH 6//for WPA2
5831+#define WPA2PSK_AUTH 7
5832+#endif //end def _WPA2_
5833+
5834+//////////////////////////////////////////////////////////////////
5835+//define the msg type of MLME module
5836+//////////////////////////////////////////////////////////////////
5837+//--------------------------------------------------------
5838+//from SME
5839+
5840+#define MLMEMSG_AUTH_REQ 0x0b
5841+#define MLMEMSG_DEAUTH_REQ 0x0c
5842+#define MLMEMSG_ASSOC_REQ 0x0d
5843+#define MLMEMSG_REASSOC_REQ 0x0e
5844+#define MLMEMSG_DISASSOC_REQ 0x0f
5845+#define MLMEMSG_START_IBSS_REQ 0x10
5846+#define MLMEMSG_IBSS_NET_CFM 0x11
5847+
5848+//from RX :
5849+#define MLMEMSG_RCV_MLMEFRAME 0x20
5850+#define MLMEMSG_RCV_ASSOCRSP 0x22
5851+#define MLMEMSG_RCV_REASSOCRSP 0x24
5852+#define MLMEMSG_RCV_DISASSOC 0x2b
5853+#define MLMEMSG_RCV_AUTH 0x2c
5854+#define MLMEMSG_RCV_DEAUTH 0x2d
5855+
5856+
5857+//from TX callback
5858+#define MLMEMSG_TX_CALLBACK 0x40
5859+#define MLMEMSG_ASSOCREQ_CALLBACK 0x41
5860+#define MLMEMSG_REASSOCREQ_CALLBACK 0x43
5861+#define MLMEMSG_DISASSOC_CALLBACK 0x4a
5862+#define MLMEMSG_AUTH_CALLBACK 0x4c
5863+#define MLMEMSG_DEAUTH_CALLBACK 0x4d
5864+
5865+//#define MLMEMSG_JOIN_FAIL 4
5866+//#define MLMEMSG_AUTHEN_FAIL 18
5867+#define MLMEMSG_TIMEOUT 0x50
5868+
5869+///////////////////////////////////////////////////////////////////////////
5870+//Global data structures
5871+#define MAX_NUM_TX_MMPDU 2
5872+#define MAX_MMPDU_SIZE 1512
5873+#define MAX_NUM_RX_MMPDU 6
5874+
5875+
5876+///////////////////////////////////////////////////////////////////////////
5877+//MACRO
5878+#define boMLME_InactiveState(_AA_) (_AA_->wState==INACTIVE)
5879+#define boMLME_IdleScanState(_BB_) (_BB_->wState==IDLE_SCAN)
5880+#define boMLME_FoundSTAinfo(_CC_) (_CC_->wState>=IDLE_SCAN)
5881+
5882+typedef struct _MLME_FRAME
5883+{
5884+ //NDIS_PACKET MLME_Packet;
5885+ PCHAR pMMPDU;
5886+ u16 len;
5887+ u8 DataType;
5888+ u8 IsInUsed;
5889+
5890+ OS_SPIN_LOCK MLMESpinLock;
5891+
5892+ u8 TxMMPDU[MAX_NUM_TX_MMPDU][MAX_MMPDU_SIZE];
5893+ u8 TxMMPDUInUse[ (MAX_NUM_TX_MMPDU+3) & ~0x03 ];
5894+
5895+ u16 wNumTxMMPDU;
5896+ u16 wNumTxMMPDUDiscarded;
5897+
5898+ u8 RxMMPDU[MAX_NUM_RX_MMPDU][MAX_MMPDU_SIZE];
5899+ u8 SaveRxBufSlotInUse[ (MAX_NUM_RX_MMPDU+3) & ~0x03 ];
5900+
5901+ u16 wNumRxMMPDU;
5902+ u16 wNumRxMMPDUDiscarded;
5903+
5904+ u16 wNumRxMMPDUInMLME; // Number of the Rx MMPDU
5905+ u16 reserved_1; // in MLME.
5906+ // excluding the discarded
5907+} MLME_FRAME, *psMLME_FRAME;
5908+
5909+typedef struct _AUTHREQ {
5910+
5911+ u8 peerMACaddr[MAC_ADDR_LENGTH];
5912+ u16 wAuthAlgorithm;
5913+
5914+} MLME_AUTHREQ_PARA, *psMLME_AUTHREQ_PARA;
5915+
5916+struct _Reason_Code {
5917+
5918+ u8 peerMACaddr[MAC_ADDR_LENGTH];
5919+ u16 wReasonCode;
5920+};
5921+typedef struct _Reason_Code MLME_DEAUTHREQ_PARA, *psMLME_DEAUTHREQ_PARA;
5922+typedef struct _Reason_Code MLME_DISASSOCREQ_PARA, *psMLME_DISASSOCREQ_PARA;
5923+
5924+typedef struct _ASSOCREQ {
5925+ u8 PeerSTAAddr[MAC_ADDR_LENGTH];
5926+ u16 CapabilityInfo;
5927+ u16 ListenInterval;
5928+
5929+}__attribute__ ((packed)) MLME_ASSOCREQ_PARA, *psMLME_ASSOCREQ_PARA;
5930+
5931+typedef struct _REASSOCREQ {
5932+ u8 NewAPAddr[MAC_ADDR_LENGTH];
5933+ u16 CapabilityInfo;
5934+ u16 ListenInterval;
5935+
5936+}__attribute__ ((packed)) MLME_REASSOCREQ_PARA, *psMLME_REASSOCREQ_PARA;
5937+
5938+typedef struct _MLMECALLBACK {
5939+
5940+ u8 *psFramePtr;
5941+ u8 bResult;
5942+
5943+} MLME_TXCALLBACK, *psMLME_TXCALLBACK;
5944+
5945+typedef struct _RXDATA
5946+{
5947+ s32 FrameLength;
5948+ u8 __attribute__ ((packed)) *pbFramePtr;
5949+
5950+}__attribute__ ((packed)) RXDATA, *psRXDATA;
5951+
5952+
5953diff --git a/drivers/staging/winbond/mlmetxrx.c b/drivers/staging/winbond/mlmetxrx.c
5954new file mode 100644
5955index 0000000..46b091e
5956--- /dev/null
5957+++ b/drivers/staging/winbond/mlmetxrx.c
5958@@ -0,0 +1,150 @@
5959+//============================================================================
5960+// Module Name:
5961+// MLMETxRx.C
5962+//
5963+// Description:
5964+// The interface between MDS (MAC Data Service) and MLME.
5965+//
5966+// Revision History:
5967+// --------------------------------------------------------------------------
5968+// 200209 UN20 Jennifer Xu
5969+// Initial Release
5970+// 20021108 PD43 Austin Liu
5971+// 20030117 PD43 Austin Liu
5972+// Deleted MLMEReturnPacket and MLMEProcThread()
5973+//
5974+// Copyright (c) 1996-2002 Winbond Electronics Corp. All Rights Reserved.
5975+//============================================================================
5976+#include "os_common.h"
5977+
5978+void MLMEResetTxRx(PWB32_ADAPTER Adapter)
5979+{
5980+ s32 i;
5981+
5982+ // Reset the interface between MDS and MLME
5983+ for (i = 0; i < MAX_NUM_TX_MMPDU; i++)
5984+ Adapter->sMlmeFrame.TxMMPDUInUse[i] = FALSE;
5985+ for (i = 0; i < MAX_NUM_RX_MMPDU; i++)
5986+ Adapter->sMlmeFrame.SaveRxBufSlotInUse[i] = FALSE;
5987+
5988+ Adapter->sMlmeFrame.wNumRxMMPDUInMLME = 0;
5989+ Adapter->sMlmeFrame.wNumRxMMPDUDiscarded = 0;
5990+ Adapter->sMlmeFrame.wNumRxMMPDU = 0;
5991+ Adapter->sMlmeFrame.wNumTxMMPDUDiscarded = 0;
5992+ Adapter->sMlmeFrame.wNumTxMMPDU = 0;
5993+ Adapter->sLocalPara.boCCAbusy = FALSE;
5994+ Adapter->sLocalPara.iPowerSaveMode = PWR_ACTIVE; // Power active
5995+}
5996+
5997+//=============================================================================
5998+// Function:
5999+// MLMEGetMMPDUBuffer()
6000+//
6001+// Description:
6002+// Return the pointer to an available data buffer with
6003+// the size MAX_MMPDU_SIZE for a MMPDU.
6004+//
6005+// Arguments:
6006+// Adapter - pointer to the miniport adapter context.
6007+//
6008+// Return value:
6009+// NULL : No available data buffer available
6010+// Otherwise: Pointer to the data buffer
6011+//=============================================================================
6012+
6013+/* FIXME: Should this just be replaced with kmalloc() and kfree()? */
6014+u8 *MLMEGetMMPDUBuffer(PWB32_ADAPTER Adapter)
6015+{
6016+ s32 i;
6017+ u8 *returnVal;
6018+
6019+ for (i = 0; i< MAX_NUM_TX_MMPDU; i++) {
6020+ if (Adapter->sMlmeFrame.TxMMPDUInUse[i] == FALSE)
6021+ break;
6022+ }
6023+ if (i >= MAX_NUM_TX_MMPDU) return NULL;
6024+
6025+ returnVal = (u8 *)&(Adapter->sMlmeFrame.TxMMPDU[i]);
6026+ Adapter->sMlmeFrame.TxMMPDUInUse[i] = TRUE;
6027+
6028+ return returnVal;
6029+}
6030+
6031+//=============================================================================
6032+u8 MLMESendFrame(PWB32_ADAPTER Adapter, u8 *pMMPDU, u16 len, u8 DataType)
6033+/* DataType : FRAME_TYPE_802_11_MANAGEMENT, FRAME_TYPE_802_11_MANAGEMENT_CHALLENGE,
6034+ FRAME_TYPE_802_11_DATA */
6035+{
6036+ if (Adapter->sMlmeFrame.IsInUsed != PACKET_FREE_TO_USE) {
6037+ Adapter->sMlmeFrame.wNumTxMMPDUDiscarded++;
6038+ return FALSE;
6039+ }
6040+ Adapter->sMlmeFrame.IsInUsed = PACKET_COME_FROM_MLME;
6041+
6042+ // Keep information for sending
6043+ Adapter->sMlmeFrame.pMMPDU = pMMPDU;
6044+ Adapter->sMlmeFrame.DataType = DataType;
6045+ // len must be the last setting due to QUERY_SIZE_SECOND of Mds
6046+ Adapter->sMlmeFrame.len = len;
6047+ Adapter->sMlmeFrame.wNumTxMMPDU++;
6048+
6049+ // H/W will enter power save by set the register. S/W don't send null frame
6050+ //with PWRMgt bit enbled to enter power save now.
6051+
6052+ // Transmit NDIS packet
6053+ Mds_Tx(Adapter);
6054+ return TRUE;
6055+}
6056+
6057+void
6058+MLME_GetNextPacket(PADAPTER Adapter, PDESCRIPTOR pDes)
6059+{
6060+#define DESCRIPTOR_ADD_BUFFER( _D, _A, _S ) \
6061+{\
6062+ _D->InternalUsed = _D->buffer_start_index + _D->buffer_number; \
6063+ _D->InternalUsed %= MAX_DESCRIPTOR_BUFFER_INDEX; \
6064+ _D->buffer_address[ _D->InternalUsed ] = _A; \
6065+ _D->buffer_size[ _D->InternalUsed ] = _S; \
6066+ _D->buffer_total_size += _S; \
6067+ _D->buffer_number++;\
6068+}
6069+
6070+ DESCRIPTOR_ADD_BUFFER( pDes, Adapter->sMlmeFrame.pMMPDU, Adapter->sMlmeFrame.len );
6071+ pDes->Type = Adapter->sMlmeFrame.DataType;
6072+}
6073+
6074+void MLMEfreeMMPDUBuffer(PWB32_ADAPTER Adapter, PCHAR pData)
6075+{
6076+ int i;
6077+
6078+ // Reclaim the data buffer
6079+ for (i = 0; i < MAX_NUM_TX_MMPDU; i++) {
6080+ if (pData == (PCHAR)&(Adapter->sMlmeFrame.TxMMPDU[i]))
6081+ break;
6082+ }
6083+ if (Adapter->sMlmeFrame.TxMMPDUInUse[i])
6084+ Adapter->sMlmeFrame.TxMMPDUInUse[i] = FALSE;
6085+ else {
6086+ // Something wrong
6087+ // PD43 Add debug code here???
6088+ }
6089+}
6090+
6091+void
6092+MLME_SendComplete(PADAPTER Adapter, u8 PacketID, unsigned char SendOK)
6093+{
6094+ MLME_TXCALLBACK TxCallback;
6095+
6096+ // Reclaim the data buffer
6097+ Adapter->sMlmeFrame.len = 0;
6098+ MLMEfreeMMPDUBuffer( Adapter, Adapter->sMlmeFrame.pMMPDU );
6099+
6100+
6101+ TxCallback.bResult = MLME_SUCCESS;
6102+
6103+ // Return resource
6104+ Adapter->sMlmeFrame.IsInUsed = PACKET_FREE_TO_USE;
6105+}
6106+
6107+
6108+
6109diff --git a/drivers/staging/winbond/mlmetxrx_f.h b/drivers/staging/winbond/mlmetxrx_f.h
6110new file mode 100644
6111index 0000000..d74e225
6112--- /dev/null
6113+++ b/drivers/staging/winbond/mlmetxrx_f.h
6114@@ -0,0 +1,52 @@
6115+//================================================================
6116+// MLMETxRx.H --
6117+//
6118+// Functions defined in MLMETxRx.c.
6119+//
6120+// Copyright (c) 2002 Winbond Electrics Corp. All Rights Reserved.
6121+//================================================================
6122+#ifndef _MLMETXRX_H
6123+#define _MLMETXRX_H
6124+
6125+void
6126+MLMEProcThread(
6127+ PWB32_ADAPTER Adapter
6128+ );
6129+
6130+void MLMEResetTxRx( PWB32_ADAPTER Adapter);
6131+
6132+u8 *
6133+MLMEGetMMPDUBuffer(
6134+ PWB32_ADAPTER Adapter
6135+ );
6136+
6137+void MLMEfreeMMPDUBuffer( PWB32_ADAPTER Adapter, PCHAR pData);
6138+
6139+void MLME_GetNextPacket( PADAPTER Adapter, PDESCRIPTOR pDes );
6140+u8 MLMESendFrame( PWB32_ADAPTER Adapter,
6141+ u8 *pMMPDU,
6142+ u16 len,
6143+ u8 DataType);
6144+
6145+void
6146+MLME_SendComplete( PWB32_ADAPTER Adapter, u8 PacketID, unsigned char SendOK );
6147+
6148+void
6149+MLMERcvFrame(
6150+ PWB32_ADAPTER Adapter,
6151+ PRXBUFFER pRxBufferArray,
6152+ u8 NumOfBuffer,
6153+ u8 ReturnSlotIndex
6154+ );
6155+
6156+void
6157+MLMEReturnPacket(
6158+ PWB32_ADAPTER Adapter,
6159+ PUCHAR pRxBufer
6160+ );
6161+#ifdef _IBSS_BEACON_SEQ_STICK_
6162+s8 SendBCNullData(PWB32_ADAPTER Adapter, u16 wIdx);
6163+#endif
6164+
6165+#endif
6166+
6167diff --git a/drivers/staging/winbond/mto.c b/drivers/staging/winbond/mto.c
6168new file mode 100644
6169index 0000000..2ef60e5
6170--- /dev/null
6171+++ b/drivers/staging/winbond/mto.c
6172@@ -0,0 +1,1229 @@
6173+//============================================================================
6174+// MTO.C -
6175+//
6176+// Description:
6177+// MAC Throughput Optimization for W89C33 802.11g WLAN STA.
6178+//
6179+// The following MIB attributes or internal variables will be affected
6180+// while the MTO is being executed:
6181+// dot11FragmentationThreshold,
6182+// dot11RTSThreshold,
6183+// transmission rate and PLCP preamble type,
6184+// CCA mode,
6185+// antenna diversity.
6186+//
6187+// Revision history:
6188+// --------------------------------------------------------------------------
6189+// 20031227 UN20 Pete Chao
6190+// First draft
6191+// 20031229 Turbo copy from PD43
6192+// 20040210 Kevin revised
6193+// Copyright (c) 2003 Winbond Electronics Corp. All rights reserved.
6194+//============================================================================
6195+
6196+// LA20040210_DTO kevin
6197+#include "os_common.h"
6198+
6199+// Declare SQ3 to rate and fragmentation threshold table
6200+// Declare fragmentation thresholds table
6201+#define MTO_MAX_SQ3_LEVELS 14
6202+#define MTO_MAX_FRAG_TH_LEVELS 5
6203+#define MTO_MAX_DATA_RATE_LEVELS 12
6204+
6205+u16 MTO_Frag_Th_Tbl[MTO_MAX_FRAG_TH_LEVELS] =
6206+{
6207+ 256, 384, 512, 768, 1536
6208+};
6209+
6210+u8 MTO_SQ3_Level[MTO_MAX_SQ3_LEVELS] =
6211+{
6212+ 0, 26, 30, 32, 34, 35, 37, 42, 44, 46, 54, 62, 78, 81
6213+};
6214+u8 MTO_SQ3toRate[MTO_MAX_SQ3_LEVELS] =
6215+{
6216+ 0, 1, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11
6217+};
6218+u8 MTO_SQ3toFrag[MTO_MAX_SQ3_LEVELS] =
6219+{
6220+ 0, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4
6221+};
6222+
6223+// One Exchange Time table
6224+//
6225+u16 MTO_One_Exchange_Time_Tbl_l[MTO_MAX_FRAG_TH_LEVELS][MTO_MAX_DATA_RATE_LEVELS] =
6226+{
6227+ { 2554, 1474, 822, 0, 0, 636, 0, 0, 0, 0, 0, 0},
6228+ { 3578, 1986, 1009, 0, 0, 729, 0, 0, 0, 0, 0, 0},
6229+ { 4602, 2498, 1195, 0, 0, 822, 0, 0, 0, 0, 0, 0},
6230+ { 6650, 3522, 1567, 0, 0, 1009, 0, 0, 0, 0, 0, 0},
6231+ {12794, 6594, 2684, 0, 0, 1567, 0, 0, 0, 0, 0, 0}
6232+};
6233+
6234+u16 MTO_One_Exchange_Time_Tbl_s[MTO_MAX_FRAG_TH_LEVELS][MTO_MAX_DATA_RATE_LEVELS] =
6235+{
6236+ { 0, 1282, 630, 404, 288, 444, 232, 172, 144, 116, 100, 96},
6237+ { 0, 1794, 817, 572, 400, 537, 316, 228, 188, 144, 124, 116},
6238+ { 0, 2306, 1003, 744, 516, 630, 400, 288, 228, 172, 144, 136},
6239+ { 0, 3330, 1375, 1084, 744, 817, 572, 400, 316, 228, 188, 172},
6240+ { 0, 6402, 2492, 2108, 1424, 1375, 1084, 740, 572, 400, 316, 284}
6241+};
6242+
6243+#define MTO_ONE_EXCHANGE_TIME(preamble_type, frag_th_lvl, data_rate_lvl) \
6244+ (preamble_type) ? MTO_One_Exchange_Time_Tbl_s[frag_th_lvl][data_rate_lvl] : \
6245+ MTO_One_Exchange_Time_Tbl_l[frag_th_lvl][data_rate_lvl]
6246+
6247+// Declare data rate table
6248+//The following table will be changed at anytime if the opration rate supported by AP don't
6249+//match the table
6250+u8 MTO_Data_Rate_Tbl[MTO_MAX_DATA_RATE_LEVELS] =
6251+{
6252+ 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108
6253+};
6254+
6255+//The Stardard_Data_Rate_Tbl and Level2PerTbl table is used to indirectly retreive PER
6256+//information from Rate_PER_TBL
6257+//The default settings is AP can support full rate set.
6258+static u8 Stardard_Data_Rate_Tbl[MTO_MAX_DATA_RATE_LEVELS] =
6259+{
6260+ 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108
6261+};
6262+static u8 Level2PerTbl[MTO_MAX_DATA_RATE_LEVELS] =
6263+{
6264+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11
6265+};
6266+//How many kind of tx rate can be supported by AP
6267+//DTO will change Rate between MTO_Data_Rate_Tbl[0] and MTO_Data_Rate_Tbl[MTO_DataRateAvailableLevel-1]
6268+static u8 MTO_DataRateAvailableLevel = MTO_MAX_DATA_RATE_LEVELS;
6269+//Smoothed PER table for each different RATE based on packet length of 1514
6270+static int Rate_PER_TBL[91][MTO_MAX_DATA_RATE_LEVELS] = {
6271+// 1M 2M 5.5M 11M 6M 9M 12M 18M 24M 36M 48M 54M
6272+/* 0% */{ 93, 177, 420, 538, 690, 774, 1001, 1401, 1768, 2358, 2838, 3039},
6273+/* 1% */{ 92, 176, 416, 533, 683, 767, 992, 1389, 1752, 2336, 2811, 3010},
6274+/* 2% */{ 91, 174, 412, 528, 675, 760, 983, 1376, 1735, 2313, 2783, 2979},
6275+/* 3% */{ 90, 172, 407, 523, 667, 753, 973, 1363, 1719, 2290, 2755, 2948},
6276+/* 4% */{ 90, 170, 403, 518, 659, 746, 964, 1350, 1701, 2266, 2726, 2916},
6277+/* 5% */{ 89, 169, 398, 512, 651, 738, 954, 1336, 1684, 2242, 2696, 2884},
6278+/* 6% */{ 88, 167, 394, 507, 643, 731, 944, 1322, 1666, 2217, 2665, 2851},
6279+/* 7% */{ 87, 165, 389, 502, 635, 723, 935, 1308, 1648, 2192, 2634, 2817},
6280+/* 8% */{ 86, 163, 384, 497, 626, 716, 924, 1294, 1629, 2166, 2602, 2782},
6281+/* 9% */{ 85, 161, 380, 491, 618, 708, 914, 1279, 1611, 2140, 2570, 2747},
6282+/* 10% */{ 84, 160, 375, 486, 609, 700, 904, 1265, 1591, 2113, 2537, 2711},
6283+/* 11% */{ 83, 158, 370, 480, 600, 692, 894, 1250, 1572, 2086, 2503, 2675},
6284+/* 12% */{ 82, 156, 365, 475, 592, 684, 883, 1234, 1552, 2059, 2469, 2638},
6285+/* 13% */{ 81, 154, 360, 469, 583, 676, 872, 1219, 1532, 2031, 2435, 2600},
6286+/* 14% */{ 80, 152, 355, 464, 574, 668, 862, 1204, 1512, 2003, 2400, 2562},
6287+/* 15% */{ 79, 150, 350, 458, 565, 660, 851, 1188, 1492, 1974, 2365, 2524},
6288+/* 16% */{ 78, 148, 345, 453, 556, 652, 840, 1172, 1471, 1945, 2329, 2485},
6289+/* 17% */{ 77, 146, 340, 447, 547, 643, 829, 1156, 1450, 1916, 2293, 2446},
6290+/* 18% */{ 76, 144, 335, 441, 538, 635, 818, 1140, 1429, 1887, 2256, 2406},
6291+/* 19% */{ 75, 143, 330, 436, 529, 627, 807, 1124, 1408, 1857, 2219, 2366},
6292+/* 20% */{ 74, 141, 325, 430, 520, 618, 795, 1107, 1386, 1827, 2182, 2326},
6293+/* 21% */{ 73, 139, 320, 424, 510, 610, 784, 1091, 1365, 1797, 2145, 2285},
6294+/* 22% */{ 72, 137, 314, 418, 501, 601, 772, 1074, 1343, 1766, 2107, 2244},
6295+/* 23% */{ 71, 135, 309, 412, 492, 592, 761, 1057, 1321, 1736, 2069, 2203},
6296+/* 24% */{ 70, 133, 304, 407, 482, 584, 749, 1040, 1299, 1705, 2031, 2161},
6297+/* 25% */{ 69, 131, 299, 401, 473, 575, 738, 1023, 1277, 1674, 1992, 2120},
6298+/* 26% */{ 68, 129, 293, 395, 464, 566, 726, 1006, 1254, 1642, 1953, 2078},
6299+/* 27% */{ 67, 127, 288, 389, 454, 557, 714, 989, 1232, 1611, 1915, 2035},
6300+/* 28% */{ 66, 125, 283, 383, 445, 549, 703, 972, 1209, 1579, 1876, 1993},
6301+/* 29% */{ 65, 123, 278, 377, 436, 540, 691, 955, 1187, 1548, 1836, 1951},
6302+/* 30% */{ 64, 121, 272, 371, 426, 531, 679, 937, 1164, 1516, 1797, 1908},
6303+/* 31% */{ 63, 119, 267, 365, 417, 522, 667, 920, 1141, 1484, 1758, 1866},
6304+/* 32% */{ 62, 117, 262, 359, 407, 513, 655, 902, 1118, 1453, 1719, 1823},
6305+/* 33% */{ 61, 115, 256, 353, 398, 504, 643, 885, 1095, 1421, 1679, 1781},
6306+/* 34% */{ 60, 113, 251, 347, 389, 495, 631, 867, 1072, 1389, 1640, 1738},
6307+/* 35% */{ 59, 111, 246, 341, 379, 486, 619, 850, 1049, 1357, 1600, 1695},
6308+/* 36% */{ 58, 108, 240, 335, 370, 477, 607, 832, 1027, 1325, 1561, 1653},
6309+/* 37% */{ 57, 106, 235, 329, 361, 468, 595, 815, 1004, 1293, 1522, 1610},
6310+/* 38% */{ 56, 104, 230, 323, 351, 459, 584, 797, 981, 1261, 1483, 1568},
6311+/* 39% */{ 55, 102, 224, 317, 342, 450, 572, 780, 958, 1230, 1443, 1526},
6312+/* 40% */{ 54, 100, 219, 311, 333, 441, 560, 762, 935, 1198, 1404, 1484},
6313+/* 41% */{ 53, 98, 214, 305, 324, 432, 548, 744, 912, 1166, 1366, 1442},
6314+/* 42% */{ 52, 96, 209, 299, 315, 423, 536, 727, 889, 1135, 1327, 1400},
6315+/* 43% */{ 51, 94, 203, 293, 306, 414, 524, 709, 866, 1104, 1289, 1358},
6316+/* 44% */{ 50, 92, 198, 287, 297, 405, 512, 692, 844, 1072, 1250, 1317},
6317+/* 45% */{ 49, 90, 193, 281, 288, 396, 500, 675, 821, 1041, 1212, 1276},
6318+/* 46% */{ 48, 88, 188, 275, 279, 387, 488, 657, 799, 1011, 1174, 1236},
6319+/* 47% */{ 47, 86, 183, 269, 271, 378, 476, 640, 777, 980, 1137, 1195},
6320+/* 48% */{ 46, 84, 178, 262, 262, 369, 464, 623, 754, 949, 1100, 1155},
6321+/* 49% */{ 45, 82, 173, 256, 254, 360, 452, 606, 732, 919, 1063, 1116},
6322+/* 50% */{ 44, 80, 168, 251, 245, 351, 441, 589, 710, 889, 1026, 1076},
6323+/* 51% */{ 43, 78, 163, 245, 237, 342, 429, 572, 689, 860, 990, 1038},
6324+/* 52% */{ 42, 76, 158, 239, 228, 333, 417, 555, 667, 830, 955, 999},
6325+/* 53% */{ 41, 74, 153, 233, 220, 324, 406, 538, 645, 801, 919, 961},
6326+/* 54% */{ 40, 72, 148, 227, 212, 315, 394, 522, 624, 773, 884, 924},
6327+/* 55% */{ 39, 70, 143, 221, 204, 307, 383, 505, 603, 744, 850, 887},
6328+/* 56% */{ 38, 68, 138, 215, 196, 298, 371, 489, 582, 716, 816, 851},
6329+/* 57% */{ 37, 67, 134, 209, 189, 289, 360, 473, 562, 688, 783, 815},
6330+/* 58% */{ 36, 65, 129, 203, 181, 281, 349, 457, 541, 661, 750, 780},
6331+/* 59% */{ 35, 63, 124, 197, 174, 272, 338, 441, 521, 634, 717, 745},
6332+/* 60% */{ 34, 61, 120, 192, 166, 264, 327, 425, 501, 608, 686, 712},
6333+/* 61% */{ 33, 59, 115, 186, 159, 255, 316, 409, 482, 582, 655, 678},
6334+/* 62% */{ 32, 57, 111, 180, 152, 247, 305, 394, 462, 556, 624, 646},
6335+/* 63% */{ 31, 55, 107, 174, 145, 238, 294, 379, 443, 531, 594, 614},
6336+/* 64% */{ 30, 53, 102, 169, 138, 230, 283, 364, 425, 506, 565, 583},
6337+/* 65% */{ 29, 52, 98, 163, 132, 222, 273, 349, 406, 482, 536, 553},
6338+/* 66% */{ 28, 50, 94, 158, 125, 214, 262, 334, 388, 459, 508, 523},
6339+/* 67% */{ 27, 48, 90, 152, 119, 206, 252, 320, 370, 436, 481, 495},
6340+/* 68% */{ 26, 46, 86, 147, 113, 198, 242, 306, 353, 413, 455, 467},
6341+/* 69% */{ 26, 44, 82, 141, 107, 190, 231, 292, 336, 391, 429, 440},
6342+/* 70% */{ 25, 43, 78, 136, 101, 182, 221, 278, 319, 370, 405, 414},
6343+/* 71% */{ 24, 41, 74, 130, 95, 174, 212, 265, 303, 350, 381, 389},
6344+/* 72% */{ 23, 39, 71, 125, 90, 167, 202, 252, 287, 329, 358, 365},
6345+/* 73% */{ 22, 37, 67, 119, 85, 159, 192, 239, 271, 310, 335, 342},
6346+/* 74% */{ 21, 36, 63, 114, 80, 151, 183, 226, 256, 291, 314, 320},
6347+/* 75% */{ 20, 34, 60, 109, 75, 144, 174, 214, 241, 273, 294, 298},
6348+/* 76% */{ 19, 32, 57, 104, 70, 137, 164, 202, 227, 256, 274, 278},
6349+/* 77% */{ 18, 31, 53, 99, 66, 130, 155, 190, 213, 239, 256, 259},
6350+/* 78% */{ 17, 29, 50, 94, 62, 122, 146, 178, 200, 223, 238, 241},
6351+/* 79% */{ 16, 28, 47, 89, 58, 115, 138, 167, 187, 208, 222, 225},
6352+/* 80% */{ 16, 26, 44, 84, 54, 109, 129, 156, 175, 194, 206, 209},
6353+/* 81% */{ 15, 24, 41, 79, 50, 102, 121, 146, 163, 180, 192, 194},
6354+/* 82% */{ 14, 23, 39, 74, 47, 95, 113, 136, 151, 167, 178, 181},
6355+/* 83% */{ 13, 21, 36, 69, 44, 89, 105, 126, 140, 155, 166, 169},
6356+/* 84% */{ 12, 20, 33, 64, 41, 82, 97, 116, 130, 144, 155, 158},
6357+/* 85% */{ 11, 19, 31, 60, 39, 76, 89, 107, 120, 134, 145, 149},
6358+/* 86% */{ 11, 17, 29, 55, 36, 70, 82, 98, 110, 125, 136, 140},
6359+/* 87% */{ 10, 16, 26, 51, 34, 64, 75, 90, 102, 116, 128, 133},
6360+/* 88% */{ 9, 14, 24, 46, 32, 58, 68, 81, 93, 108, 121, 128},
6361+/* 89% */{ 8, 13, 22, 42, 31, 52, 61, 74, 86, 102, 116, 124},
6362+/* 90% */{ 7, 12, 21, 37, 29, 46, 54, 66, 79, 96, 112, 121}
6363+};
6364+
6365+#define RSSIBUF_NUM 10
6366+#define RSSI2RATE_SIZE 9
6367+
6368+static TXRETRY_REC TxRateRec={MTO_MAX_DATA_RATE_LEVELS - 1, 0}; //new record=>TxRateRec
6369+static int TxRetryRate;
6370+//static int SQ3, BSS_PK_CNT, NIDLESLOT, SLOT_CNT, INTERF_CNT, GAP_CNT, DS_EVM;
6371+static s32 RSSIBuf[RSSIBUF_NUM]={-70, -70, -70, -70, -70, -70, -70, -70, -70, -70};
6372+static s32 RSSISmoothed=-700;
6373+static int RSSIBufIndex=0;
6374+static u8 max_rssi_rate;
6375+static int rate_tbl[13] = {0,1,2,5,11,6,9,12,18,24,36,48,54};
6376+//[WKCHEN]static core_data_t *pMTOcore_data=NULL;
6377+
6378+static int TotalTxPkt = 0;
6379+static int TotalTxPktRetry = 0;
6380+static int TxPktPerAnt[3] = {0,0,0};
6381+static int RXRSSIANT[3] ={-70,-70,-70};
6382+static int TxPktRetryPerAnt[3] = {0,0,0};
6383+//static int TxDominateFlag=FALSE;
6384+static u8 old_antenna[4]={1 ,0 ,1 ,0};
6385+static int retryrate_rec[MTO_MAX_DATA_RATE_LEVELS];//this record the retry rate at different data rate
6386+
6387+static int PeriodTotalTxPkt = 0;
6388+static int PeriodTotalTxPktRetry = 0;
6389+
6390+typedef struct
6391+{
6392+ s32 RSSI;
6393+ u8 TxRate;
6394+}RSSI2RATE;
6395+
6396+static RSSI2RATE RSSI2RateTbl[RSSI2RATE_SIZE] =
6397+{
6398+ {-740, 108}, // 54M
6399+ {-760, 96}, // 48M
6400+ {-820, 72}, // 36M
6401+ {-850, 48}, // 24M
6402+ {-870, 36}, // 18M
6403+ {-890, 24}, // 12M
6404+ {-900, 12}, // 6M
6405+ {-920, 11}, // 5.5M
6406+ {-950, 4}, // 2M
6407+};
6408+static u8 untogglecount;
6409+static u8 last_rate_ant; //this is used for antenna backoff-hh
6410+
6411+u8 boSparseTxTraffic = FALSE;
6412+
6413+void MTO_Init(MTO_FUNC_INPUT);
6414+void AntennaToggleInitiator(MTO_FUNC_INPUT);
6415+void AntennaToggleState(MTO_FUNC_INPUT);
6416+void TxPwrControl(MTO_FUNC_INPUT);
6417+void GetFreshAntennaData(MTO_FUNC_INPUT);
6418+void TxRateReductionCtrl(MTO_FUNC_INPUT);
6419+/** 1.1.31.1000 Turbo modify */
6420+//void MTO_SetDTORateRange(int type);
6421+void MTO_SetDTORateRange(MTO_FUNC_INPUT, u8 *pRateArray, u8 ArraySize);
6422+void MTO_SetTxCount(MTO_FUNC_INPUT, u8 t0, u8 index);
6423+void MTO_TxFailed(MTO_FUNC_INPUT);
6424+void SmoothRSSI(s32 new_rssi);
6425+void hal_get_dto_para(MTO_FUNC_INPUT, char *buffer);
6426+u8 CalcNewRate(MTO_FUNC_INPUT, u8 old_rate, u32 retry_cnt, u32 tx_frag_cnt);
6427+u8 GetMaxRateLevelFromRSSI(void);
6428+u8 MTO_GetTxFallbackRate(MTO_FUNC_INPUT);
6429+int Divide(int a, int b);
6430+void multiagc(MTO_FUNC_INPUT, u8 high_gain_mode);
6431+
6432+//===========================================================================
6433+// MTO_Init --
6434+//
6435+// Description:
6436+// Set DTO Tx Rate Scope because different AP could have different Rate set.
6437+// After our staion join with AP, LM core will call this function to initialize
6438+// Tx Rate table.
6439+//
6440+// Arguments:
6441+// pRateArray - The pointer to the Tx Rate Array by the following order
6442+// - 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108
6443+// - DTO won't check whether rate order is invalid or not
6444+// ArraySize - The array size to indicate how many tx rate we can choose
6445+//
6446+// sample code:
6447+// {
6448+// u8 RateArray[4] = {2, 4, 11, 22};
6449+// MTO_SetDTORateRange(RateArray, 4);
6450+// }
6451+//
6452+// Return Value:
6453+// None
6454+//============================================================================
6455+void MTO_SetDTORateRange(MTO_FUNC_INPUT,u8 *pRateArray, u8 ArraySize)
6456+{
6457+ u8 i, j=0;
6458+
6459+ for(i=0;i<ArraySize;i++)
6460+ {
6461+ if(pRateArray[i] == 22)
6462+ break;
6463+ }
6464+ if(i < ArraySize) //we need adjust the order of rate list because 11Mbps rate exists
6465+ {
6466+ for(;i>0;i--)
6467+ {
6468+ if(pRateArray[i-1] <= 11)
6469+ break;
6470+ pRateArray[i] = pRateArray[i-1];
6471+ }
6472+ pRateArray[i] = 22;
6473+ MTO_OFDM_RATE_LEVEL() = i;
6474+ }
6475+ else
6476+ {
6477+ for(i=0; i<ArraySize; i++)
6478+ {
6479+ if (pRateArray[i] >= 12)
6480+ break;
6481+ }
6482+ MTO_OFDM_RATE_LEVEL() = i;
6483+ }
6484+
6485+ for(i=0;i<ArraySize;i++)
6486+ {
6487+ MTO_Data_Rate_Tbl[i] = pRateArray[i];
6488+ for(;j<MTO_MAX_DATA_RATE_LEVELS;j++)
6489+ {
6490+ if(Stardard_Data_Rate_Tbl[j] == pRateArray[i])
6491+ break;
6492+ }
6493+ Level2PerTbl[i] = j;
6494+ #ifdef _PE_DTO_DUMP_
6495+ WBDEBUG(("[MTO]:Op Rate[%d]: %d\n",i, MTO_Data_Rate_Tbl[i]));
6496+ #endif
6497+ }
6498+ MTO_DataRateAvailableLevel = ArraySize;
6499+ if( MTO_DATA().RatePolicy ) // 0 means that no registry setting
6500+ {
6501+ if( MTO_DATA().RatePolicy == 1 )
6502+ TxRateRec.tx_rate = 0; //ascent
6503+ else
6504+ TxRateRec.tx_rate = MTO_DataRateAvailableLevel -1 ; //descent
6505+ }
6506+ else
6507+ {
6508+ if( MTO_INITTXRATE_MODE )
6509+ TxRateRec.tx_rate = 0; //ascent
6510+ else
6511+ TxRateRec.tx_rate = MTO_DataRateAvailableLevel -1 ; //descent
6512+ }
6513+ TxRateRec.tx_retry_rate = 0;
6514+ //set default rate for initial use
6515+ MTO_RATE_LEVEL() = TxRateRec.tx_rate;
6516+ MTO_FALLBACK_RATE_LEVEL() = MTO_RATE_LEVEL();
6517+}
6518+
6519+//===========================================================================
6520+// MTO_Init --
6521+//
6522+// Description:
6523+// Initialize MTO parameters.
6524+//
6525+// This function should be invoked during system initialization.
6526+//
6527+// Arguments:
6528+// Adapter - The pointer to the Miniport Adapter Context
6529+//
6530+// Return Value:
6531+// None
6532+//============================================================================
6533+void MTO_Init(MTO_FUNC_INPUT)
6534+{
6535+ int i;
6536+ //WBDEBUG(("[MTO] -> MTO_Init()\n"));
6537+ //[WKCHEN]pMTOcore_data = pcore_data;
6538+// 20040510 Turbo add for global variable
6539+ MTO_TMR_CNT() = 0;
6540+ MTO_TOGGLE_STATE() = TOGGLE_STATE_IDLE;
6541+ MTO_TX_RATE_REDUCTION_STATE() = RATE_CHGSTATE_IDLE;
6542+ MTO_BACKOFF_TMR() = 0;
6543+ MTO_LAST_RATE() = 11;
6544+ MTO_CO_EFFICENT() = 0;
6545+
6546+ //MTO_TH_FIXANT() = MTO_DEFAULT_TH_FIXANT;
6547+ MTO_TH_CNT() = MTO_DEFAULT_TH_CNT;
6548+ MTO_TH_SQ3() = MTO_DEFAULT_TH_SQ3;
6549+ MTO_TH_IDLE_SLOT() = MTO_DEFAULT_TH_IDLE_SLOT;
6550+ MTO_TH_PR_INTERF() = MTO_DEFAULT_TH_PR_INTERF;
6551+
6552+ MTO_TMR_AGING() = MTO_DEFAULT_TMR_AGING;
6553+ MTO_TMR_PERIODIC() = MTO_DEFAULT_TMR_PERIODIC;
6554+
6555+ //[WKCHEN]MTO_CCA_MODE_SETUP()= (u8) hal_get_cca_mode(MTO_HAL());
6556+ //[WKCHEN]MTO_CCA_MODE() = MTO_CCA_MODE_SETUP();
6557+
6558+ //MTO_PREAMBLE_TYPE() = MTO_PREAMBLE_LONG;
6559+ MTO_PREAMBLE_TYPE() = MTO_PREAMBLE_SHORT; // for test
6560+
6561+ MTO_ANT_SEL() = hal_get_antenna_number(MTO_HAL());
6562+ MTO_ANT_MAC() = MTO_ANT_SEL();
6563+ MTO_CNT_ANT(0) = 0;
6564+ MTO_CNT_ANT(1) = 0;
6565+ MTO_SQ_ANT(0) = 0;
6566+ MTO_SQ_ANT(1) = 0;
6567+ MTO_ANT_DIVERSITY() = MTO_ANTENNA_DIVERSITY_ON;
6568+ //CardSet_AntennaDiversity(Adapter, MTO_ANT_DIVERSITY());
6569+ //PLMESetAntennaDiversity( Adapter, MTO_ANT_DIVERSITY());
6570+
6571+ MTO_AGING_TIMEOUT() = 0;//MTO_TMR_AGING() / MTO_TMR_PERIODIC();
6572+
6573+ // The following parameters should be initialized to the values set by user
6574+ //
6575+ //MTO_RATE_LEVEL() = 10;
6576+ MTO_RATE_LEVEL() = 0;
6577+ MTO_FALLBACK_RATE_LEVEL() = MTO_RATE_LEVEL();
6578+ MTO_FRAG_TH_LEVEL() = 4;
6579+ /** 1.1.23.1000 Turbo modify from -1 to +1
6580+ MTO_RTS_THRESHOLD() = MTO_FRAG_TH() - 1;
6581+ MTO_RTS_THRESHOLD_SETUP() = MTO_FRAG_TH() - 1;
6582+ */
6583+ MTO_RTS_THRESHOLD() = MTO_FRAG_TH() + 1;
6584+ MTO_RTS_THRESHOLD_SETUP() = MTO_FRAG_TH() + 1;
6585+ // 1.1.23.1000 Turbo add for mto change preamble from 0 to 1
6586+ MTO_RATE_CHANGE_ENABLE() = 1;
6587+ MTO_FRAG_CHANGE_ENABLE() = 0; // 1.1.29.1000 Turbo add don't support frag
6588+ //The default valud of ANTDIV_DEFAULT_ON will be decided by EEPROM
6589+ //#ifdef ANTDIV_DEFAULT_ON
6590+ //MTO_ANT_DIVERSITY_ENABLE() = 1;
6591+ //#else
6592+ //MTO_ANT_DIVERSITY_ENABLE() = 0;
6593+ //#endif
6594+ MTO_POWER_CHANGE_ENABLE() = 1;
6595+ MTO_PREAMBLE_CHANGE_ENABLE()= 1;
6596+ MTO_RTS_CHANGE_ENABLE() = 0; // 1.1.29.1000 Turbo add don't support frag
6597+ // 20040512 Turbo add
6598+ //old_antenna[0] = 1;
6599+ //old_antenna[1] = 0;
6600+ //old_antenna[2] = 1;
6601+ //old_antenna[3] = 0;
6602+ for (i=0;i<MTO_MAX_DATA_RATE_LEVELS;i++)
6603+ retryrate_rec[i]=5;
6604+
6605+ MTO_TXFLOWCOUNT() = 0;
6606+ //--------- DTO threshold parameters -------------
6607+ //MTOPARA_PERIODIC_CHECK_CYCLE() = 50;
6608+ MTOPARA_PERIODIC_CHECK_CYCLE() = 10;
6609+ MTOPARA_RSSI_TH_FOR_ANTDIV() = 10;
6610+ MTOPARA_TXCOUNT_TH_FOR_CALC_RATE() = 50;
6611+ MTOPARA_TXRATE_INC_TH() = 10;
6612+ MTOPARA_TXRATE_DEC_TH() = 30;
6613+ MTOPARA_TXRATE_EQ_TH() = 40;
6614+ MTOPARA_TXRATE_BACKOFF() = 12;
6615+ MTOPARA_TXRETRYRATE_REDUCE() = 6;
6616+ if ( MTO_TXPOWER_FROM_EEPROM == 0xff)
6617+ {
6618+ switch( MTO_HAL()->phy_type)
6619+ {
6620+ case RF_AIROHA_2230:
6621+ case RF_AIROHA_2230S: // 20060420 Add this
6622+ MTOPARA_TXPOWER_INDEX() = 46; // MAX-8 // @@ Only for AL 2230
6623+ break;
6624+ case RF_AIROHA_7230:
6625+ MTOPARA_TXPOWER_INDEX() = 49;
6626+ break;
6627+ case RF_WB_242:
6628+ MTOPARA_TXPOWER_INDEX() = 10;
6629+ break;
6630+ case RF_WB_242_1:
6631+ MTOPARA_TXPOWER_INDEX() = 24; // ->10 20060316.1 modify
6632+ break;
6633+ }
6634+ }
6635+ else //follow the setting from EEPROM
6636+ MTOPARA_TXPOWER_INDEX() = MTO_TXPOWER_FROM_EEPROM;
6637+ hal_set_rf_power(MTO_HAL(), (u8)MTOPARA_TXPOWER_INDEX());
6638+ //------------------------------------------------
6639+
6640+ // For RSSI turning 20060808.4 Cancel load from EEPROM
6641+ MTO_DATA().RSSI_high = -41;
6642+ MTO_DATA().RSSI_low = -60;
6643+}
6644+
6645+//---------------------------------------------------------------------------//
6646+static u32 DTO_Rx_Info[13][3];
6647+static u32 DTO_RxCRCFail_Info[13][3];
6648+static u32 AntennaToggleBkoffTimer=5;
6649+typedef struct{
6650+ int RxRate;
6651+ int RxRatePkts;
6652+ int index;
6653+}RXRATE_ANT;
6654+RXRATE_ANT RxRatePeakAnt[3];
6655+
6656+#define ANT0 0
6657+#define ANT1 1
6658+#define OLD_ANT 2
6659+
6660+void SearchPeakRxRate(int index)
6661+{
6662+ int i;
6663+ RxRatePeakAnt[index].RxRatePkts=0;
6664+ //Find out the best rx rate which is used on different antenna
6665+ for(i=1;i<13;i++)
6666+ {
6667+ if(DTO_Rx_Info[i][index] > (u32) RxRatePeakAnt[index].RxRatePkts)
6668+ {
6669+ RxRatePeakAnt[index].RxRatePkts = DTO_Rx_Info[i][index];
6670+ RxRatePeakAnt[index].RxRate = rate_tbl[i];
6671+ RxRatePeakAnt[index].index = i;
6672+ }
6673+ }
6674+}
6675+
6676+void ResetDTO_RxInfo(int index, MTO_FUNC_INPUT)
6677+{
6678+ int i;
6679+
6680+ #ifdef _PE_DTO_DUMP_
6681+ WBDEBUG(("ResetDTOrx\n"));
6682+ #endif
6683+
6684+ for(i=0;i<13;i++)
6685+ DTO_Rx_Info[i][index] = MTO_HAL()->rx_ok_count[i];
6686+
6687+ for(i=0;i<13;i++)
6688+ DTO_RxCRCFail_Info[i][index] = MTO_HAL()->rx_err_count[i];
6689+
6690+ TotalTxPkt = 0;
6691+ TotalTxPktRetry = 0;
6692+}
6693+
6694+void GetDTO_RxInfo(int index, MTO_FUNC_INPUT)
6695+{
6696+ int i;
6697+
6698+ #ifdef _PE_DTO_DUMP_
6699+ WBDEBUG(("GetDTOrx\n"));
6700+ #endif
6701+
6702+ //PDEBUG(("[MTO]:DTO_Rx_Info[%d]=%d, rx_ok_count=%d\n", index, DTO_Rx_Info[0][index], phw_data->rx_ok_count[0]));
6703+ for(i=0;i<13;i++)
6704+ DTO_Rx_Info[i][index] = abs(MTO_HAL()->rx_ok_count[i] - DTO_Rx_Info[i][index]);
6705+ if(DTO_Rx_Info[0][index]==0) DTO_Rx_Info[0][index] = 1;
6706+
6707+ for(i=0;i<13;i++)
6708+ DTO_RxCRCFail_Info[i][index] = MTO_HAL()->rx_err_count[i] - DTO_RxCRCFail_Info[i][index];
6709+
6710+ TxPktPerAnt[index] = TotalTxPkt;
6711+ TxPktRetryPerAnt[index] = TotalTxPktRetry;
6712+ TotalTxPkt = 0;
6713+ TotalTxPktRetry = 0;
6714+}
6715+
6716+void OutputDebugInfo(int index1, int index2)
6717+{
6718+ #ifdef _PE_DTO_DUMP_
6719+ WBDEBUG(("[HHDTO]:Total Rx (%d)\t\t(%d) \n ", DTO_Rx_Info[0][index1], DTO_Rx_Info[0][index2]));
6720+ WBDEBUG(("[HHDTO]:RECEIVE RSSI: (%d)\t\t(%d) \n ", RXRSSIANT[index1], RXRSSIANT[index2]));
6721+ WBDEBUG(("[HHDTO]:TX packet correct rate: (%d)%%\t\t(%d)%% \n ",Divide(TxPktPerAnt[index1]*100,TxPktRetryPerAnt[index1]), Divide(TxPktPerAnt[index2]*100,TxPktRetryPerAnt[index2])));
6722+ #endif
6723+ {
6724+ int tmp1, tmp2;
6725+ #ifdef _PE_DTO_DUMP_
6726+ WBDEBUG(("[HHDTO]:Total Tx (%d)\t\t(%d) \n ", TxPktPerAnt[index1], TxPktPerAnt[index2]));
6727+ WBDEBUG(("[HHDTO]:Total Tx retry (%d)\t\t(%d) \n ", TxPktRetryPerAnt[index1], TxPktRetryPerAnt[index2]));
6728+ #endif
6729+ tmp1 = TxPktPerAnt[index1] + DTO_Rx_Info[0][index1];
6730+ tmp2 = TxPktPerAnt[index2] + DTO_Rx_Info[0][index2];
6731+ #ifdef _PE_DTO_DUMP_
6732+ WBDEBUG(("[HHDTO]:Total Tx+RX (%d)\t\t(%d) \n ", tmp1, tmp2));
6733+ #endif
6734+ }
6735+}
6736+
6737+unsigned char TxDominate(int index)
6738+{
6739+ int tmp;
6740+
6741+ tmp = TxPktPerAnt[index] + DTO_Rx_Info[0][index];
6742+
6743+ if(Divide(TxPktPerAnt[index]*100, tmp) > 40)
6744+ return TRUE;
6745+ else
6746+ return FALSE;
6747+}
6748+
6749+unsigned char CmpTxRetryRate(int index1, int index2)
6750+{
6751+ int tx_retry_rate1, tx_retry_rate2;
6752+ tx_retry_rate1 = Divide((TxPktRetryPerAnt[index1] - TxPktPerAnt[index1])*100, TxPktRetryPerAnt[index1]);
6753+ tx_retry_rate2 = Divide((TxPktRetryPerAnt[index2] - TxPktPerAnt[index2])*100, TxPktRetryPerAnt[index2]);
6754+ #ifdef _PE_DTO_DUMP_
6755+ WBDEBUG(("[MTO]:TxRetry Ant0: (%d%%) Ant1: (%d%%) \n ", tx_retry_rate1, tx_retry_rate2));
6756+ #endif
6757+
6758+ if(tx_retry_rate1 > tx_retry_rate2)
6759+ return TRUE;
6760+ else
6761+ return FALSE;
6762+}
6763+
6764+void GetFreshAntennaData(MTO_FUNC_INPUT)
6765+{
6766+ u8 x;
6767+
6768+ x = hal_get_antenna_number(MTO_HAL());
6769+ //hal_get_bss_pk_cnt(MTO_HAL());
6770+ //hal_get_est_sq3(MTO_HAL(), 1);
6771+ old_antenna[0] = x;
6772+ //if this is the function for timer
6773+ ResetDTO_RxInfo(x, MTO_FUNC_INPUT_DATA);
6774+ if(AntennaToggleBkoffTimer)
6775+ AntennaToggleBkoffTimer--;
6776+ if (abs(last_rate_ant-MTO_RATE_LEVEL())>1) //backoff timer reset
6777+ AntennaToggleBkoffTimer=0;
6778+
6779+ if (MTO_ANT_DIVERSITY() != MTO_ANTENNA_DIVERSITY_ON ||
6780+ MTO_ANT_DIVERSITY_ENABLE() != 1)
6781+ AntennaToggleBkoffTimer=1;
6782+ #ifdef _PE_DTO_DUMP_
6783+ WBDEBUG(("[HHDTO]:**last data rate=%d,now data rate=%d**antenna toggle timer=%d",last_rate_ant,MTO_RATE_LEVEL(),AntennaToggleBkoffTimer));
6784+ #endif
6785+ last_rate_ant=MTO_RATE_LEVEL();
6786+ if(AntennaToggleBkoffTimer==0)
6787+ {
6788+ MTO_TOGGLE_STATE() = TOGGLE_STATE_WAIT0;
6789+ #ifdef _PE_DTO_DUMP_
6790+ WBDEBUG(("[HHDTO]:===state is starting==for antenna toggle==="));
6791+ #endif
6792+ }
6793+ else
6794+ MTO_TOGGLE_STATE() = TOGGLE_STATE_IDLE;
6795+
6796+ if ((MTO_BACKOFF_TMR()!=0)&&(MTO_RATE_LEVEL()>MTO_DataRateAvailableLevel - 3))
6797+ {
6798+ MTO_TOGGLE_STATE() = TOGGLE_STATE_IDLE;
6799+ #ifdef _PE_DTO_DUMP_
6800+ WBDEBUG(("[HHDTO]:===the data rate is %d (good)and will not toogle ===",MTO_DATA_RATE()>>1));
6801+ #endif
6802+ }
6803+
6804+
6805+}
6806+
6807+int WB_PCR[2]; //packet correct rate
6808+
6809+void AntennaToggleState(MTO_FUNC_INPUT)
6810+{
6811+ int decideantflag = 0;
6812+ u8 x;
6813+ s32 rssi;
6814+
6815+ if(MTO_ANT_DIVERSITY_ENABLE() != 1)
6816+ return;
6817+ x = hal_get_antenna_number(MTO_HAL());
6818+ switch(MTO_TOGGLE_STATE())
6819+ {
6820+
6821+ //Missing.....
6822+ case TOGGLE_STATE_IDLE:
6823+ case TOGGLE_STATE_BKOFF:
6824+ break;;
6825+
6826+ case TOGGLE_STATE_WAIT0://========
6827+ GetDTO_RxInfo(x, MTO_FUNC_INPUT_DATA);
6828+ sme_get_rssi(MTO_FUNC_INPUT_DATA, &rssi);
6829+ RXRSSIANT[x] = rssi;
6830+ #ifdef _PE_DTO_DUMP_
6831+ WBDEBUG(("[HHDTO] **wait0==== Collecting Ant%d--rssi=%d\n", x,RXRSSIANT[x]));
6832+ #endif
6833+
6834+ //change antenna and reset the data at changed antenna
6835+ x = (~x) & 0x01;
6836+ MTO_ANT_SEL() = x;
6837+ hal_set_antenna_number(MTO_HAL(), MTO_ANT_SEL());
6838+ LOCAL_ANTENNA_NO() = x;
6839+
6840+ MTO_TOGGLE_STATE() = TOGGLE_STATE_WAIT1;//go to wait1
6841+ ResetDTO_RxInfo(x, MTO_FUNC_INPUT_DATA);
6842+ break;
6843+ case TOGGLE_STATE_WAIT1://=====wait1
6844+ //MTO_CNT_ANT(x) = hal_get_bss_pk_cnt(MTO_HAL());
6845+ //RXRSSIANT[x] = hal_get_rssi(MTO_HAL());
6846+ sme_get_rssi(MTO_FUNC_INPUT_DATA, &rssi);
6847+ RXRSSIANT[x] = rssi;
6848+ GetDTO_RxInfo(x, MTO_FUNC_INPUT_DATA);
6849+ #ifdef _PE_DTO_DUMP_
6850+ WBDEBUG(("[HHDTO] **wait1==== Collecting Ant%d--rssi=%d\n", x,RXRSSIANT[x]));
6851+ #endif
6852+ MTO_TOGGLE_STATE() = TOGGLE_STATE_MAKEDESISION;
6853+ break;
6854+ case TOGGLE_STATE_MAKEDESISION:
6855+ #ifdef _PE_DTO_DUMP_
6856+ WBDEBUG(("[HHDTO]:Ant--0-----------------1---\n"));
6857+ OutputDebugInfo(ANT0,ANT1);
6858+ #endif
6859+ //PDEBUG(("[HHDTO] **decision====\n "));
6860+
6861+ //=====following is the decision produrce
6862+ //
6863+ // first: compare the rssi if difference >10
6864+ // select the larger one
6865+ // ,others go to second
6866+ // second: comapre the tx+rx packet count if difference >100
6867+ // use larger total packets antenna
6868+ // third::compare the tx PER if packets>20
6869+ // if difference >5% using the bigger one
6870+ //
6871+ // fourth:compare the RX PER if packets>20
6872+ // if PER difference <5%
6873+ // using old antenna
6874+ //
6875+ //
6876+ if (abs(RXRSSIANT[ANT0]-RXRSSIANT[ANT1]) > MTOPARA_RSSI_TH_FOR_ANTDIV())//====rssi_th
6877+ {
6878+ if (RXRSSIANT[ANT0]>RXRSSIANT[ANT1])
6879+ {
6880+ decideantflag=1;
6881+ MTO_ANT_MAC() = ANT0;
6882+ }
6883+ else
6884+ {
6885+ decideantflag=1;
6886+ MTO_ANT_MAC() = ANT1;
6887+ }
6888+ #ifdef _PE_DTO_DUMP_
6889+ WBDEBUG(("Select antenna by RSSI\n"));
6890+ #endif
6891+ }
6892+ else if (abs(TxPktPerAnt[ANT0] + DTO_Rx_Info[0][ANT0]-TxPktPerAnt[ANT1]-DTO_Rx_Info[0][ANT1])<50)//=====total packet_th
6893+ {
6894+ #ifdef _PE_DTO_DUMP_
6895+ WBDEBUG(("Total tx/rx is close\n"));
6896+ #endif
6897+ if (TxDominate(ANT0) && TxDominate(ANT1))
6898+ {
6899+ if ((TxPktPerAnt[ANT0]>10) && (TxPktPerAnt[ANT1]>10))//====tx packet_th
6900+ {
6901+ WB_PCR[ANT0]=Divide(TxPktPerAnt[ANT0]*100,TxPktRetryPerAnt[ANT0]);
6902+ WB_PCR[ANT1]=Divide(TxPktPerAnt[ANT1]*100,TxPktRetryPerAnt[ANT1]);
6903+ if (abs(WB_PCR[ANT0]-WB_PCR[ANT1])>5)// tx PER_th
6904+ {
6905+ #ifdef _PE_DTO_DUMP_
6906+ WBDEBUG(("Decide by Tx correct rate\n"));
6907+ #endif
6908+ if (WB_PCR[ANT0]>WB_PCR[ANT1])
6909+ {
6910+ decideantflag=1;
6911+ MTO_ANT_MAC() = ANT0;
6912+ }
6913+ else
6914+ {
6915+ decideantflag=1;
6916+ MTO_ANT_MAC() = ANT1;
6917+ }
6918+ }
6919+ else
6920+ {
6921+ decideantflag=0;
6922+ untogglecount++;
6923+ MTO_ANT_MAC() = old_antenna[0];
6924+ }
6925+ }
6926+ else
6927+ {
6928+ decideantflag=0;
6929+ MTO_ANT_MAC() = old_antenna[0];
6930+ }
6931+ }
6932+ else if ((DTO_Rx_Info[0][ANT0]>10)&&(DTO_Rx_Info[0][ANT1]>10))//rx packet th
6933+ {
6934+ #ifdef _PE_DTO_DUMP_
6935+ WBDEBUG(("Decide by Rx\n"));
6936+ #endif
6937+ if (abs(DTO_Rx_Info[0][ANT0] - DTO_Rx_Info[0][ANT1])>50)
6938+ {
6939+ if (DTO_Rx_Info[0][ANT0] > DTO_Rx_Info[0][ANT1])
6940+ {
6941+ decideantflag=1;
6942+ MTO_ANT_MAC() = ANT0;
6943+ }
6944+ else
6945+ {
6946+ decideantflag=1;
6947+ MTO_ANT_MAC() = ANT1;
6948+ }
6949+ }
6950+ else
6951+ {
6952+ decideantflag=0;
6953+ untogglecount++;
6954+ MTO_ANT_MAC() = old_antenna[0];
6955+ }
6956+ }
6957+ else
6958+ {
6959+ decideantflag=0;
6960+ MTO_ANT_MAC() = old_antenna[0];
6961+ }
6962+ }
6963+ else if ((TxPktPerAnt[ANT0]+DTO_Rx_Info[0][ANT0])>(TxPktPerAnt[ANT1]+DTO_Rx_Info[0][ANT1]))//use more packekts
6964+ {
6965+ #ifdef _PE_DTO_DUMP_
6966+ WBDEBUG(("decide by total tx/rx : ANT 0\n"));
6967+ #endif
6968+
6969+ decideantflag=1;
6970+ MTO_ANT_MAC() = ANT0;
6971+ }
6972+ else
6973+ {
6974+ #ifdef _PE_DTO_DUMP_
6975+ WBDEBUG(("decide by total tx/rx : ANT 1\n"));
6976+ #endif
6977+ decideantflag=1;
6978+ MTO_ANT_MAC() = ANT1;
6979+
6980+ }
6981+ //this is force ant toggle
6982+ if (decideantflag==1)
6983+ untogglecount=0;
6984+
6985+ untogglecount=untogglecount%4;
6986+ if (untogglecount==3) //change antenna
6987+ MTO_ANT_MAC() = ((~old_antenna[0]) & 0x1);
6988+ #ifdef _PE_DTO_DUMP_
6989+ WBDEBUG(("[HHDTO]:==================untoggle-count=%d",untogglecount));
6990+ #endif
6991+
6992+
6993+
6994+
6995+ //PDEBUG(("[HHDTO] **********************************DTO ENABLE=%d",MTO_ANT_DIVERSITY_ENABLE()));
6996+ if(MTO_ANT_DIVERSITY_ENABLE() == 1)
6997+ {
6998+ MTO_ANT_SEL() = MTO_ANT_MAC();
6999+ hal_set_antenna_number(MTO_HAL(), MTO_ANT_SEL());
7000+ LOCAL_ANTENNA_NO() = MTO_ANT_SEL();
7001+ #ifdef _PE_DTO_DUMP_
7002+ WBDEBUG(("[HHDTO] ==decision==*******antflag=%d******************selected antenna=%d\n",decideantflag,MTO_ANT_SEL()));
7003+ #endif
7004+ }
7005+ if (decideantflag)
7006+ {
7007+ old_antenna[3]=old_antenna[2];//store antenna info
7008+ old_antenna[2]=old_antenna[1];
7009+ old_antenna[1]=old_antenna[0];
7010+ old_antenna[0]= MTO_ANT_MAC();
7011+ }
7012+ #ifdef _PE_DTO_DUMP_
7013+ WBDEBUG(("[HHDTO]:**old antenna=[%d][%d][%d][%d]\n",old_antenna[0],old_antenna[1],old_antenna[2],old_antenna[3]));
7014+ #endif
7015+ if (old_antenna[0]!=old_antenna[1])
7016+ AntennaToggleBkoffTimer=0;
7017+ else if (old_antenna[1]!=old_antenna[2])
7018+ AntennaToggleBkoffTimer=1;
7019+ else if (old_antenna[2]!=old_antenna[3])
7020+ AntennaToggleBkoffTimer=2;
7021+ else
7022+ AntennaToggleBkoffTimer=4;
7023+
7024+ #ifdef _PE_DTO_DUMP_
7025+ WBDEBUG(("[HHDTO]:**back off timer=%d",AntennaToggleBkoffTimer));
7026+ #endif
7027+
7028+ ResetDTO_RxInfo(MTO_ANT_MAC(), MTO_FUNC_INPUT_DATA);
7029+ if (AntennaToggleBkoffTimer==0 && decideantflag)
7030+ MTO_TOGGLE_STATE() = TOGGLE_STATE_WAIT0;
7031+ else
7032+ MTO_TOGGLE_STATE() = TOGGLE_STATE_IDLE;
7033+ break;
7034+ }
7035+
7036+}
7037+
7038+void multiagc(MTO_FUNC_INPUT, u8 high_gain_mode )
7039+{
7040+ s32 rssi;
7041+ hw_data_t *pHwData = MTO_HAL();
7042+
7043+ sme_get_rssi(MTO_FUNC_INPUT_DATA, &rssi);
7044+
7045+ if( (RF_WB_242 == pHwData->phy_type) ||
7046+ (RF_WB_242_1 == pHwData->phy_type) ) // 20060619.5 Add
7047+ {
7048+ if (high_gain_mode==1)
7049+ {
7050+ //hw_set_dxx_reg(phw_data, 0x0C, 0xf8f52230);
7051+ //hw_set_dxx_reg(phw_data, 0x20, 0x06C43440);
7052+ Wb35Reg_Write( pHwData, 0x100C, 0xF2F32232 ); // 940916 0xf8f52230 );
7053+ Wb35Reg_Write( pHwData, 0x1020, 0x04cb3440 ); // 940915 0x06C43440
7054+ }
7055+ else if (high_gain_mode==0)
7056+ {
7057+ //hw_set_dxx_reg(phw_data, 0x0C, 0xEEEE000D);
7058+ //hw_set_dxx_reg(phw_data, 0x20, 0x06c41440);
7059+ Wb35Reg_Write( pHwData, 0x100C, 0xEEEE000D );
7060+ Wb35Reg_Write( pHwData, 0x1020, 0x04cb1440 ); // 940915 0x06c41440
7061+ }
7062+ #ifdef _PE_DTO_DUMP_
7063+ WBDEBUG(("[HHDTOAGC] **rssi=%d, high gain mode=%d", rssi, high_gain_mode));
7064+ #endif
7065+ }
7066+}
7067+
7068+void TxPwrControl(MTO_FUNC_INPUT)
7069+{
7070+ s32 rssi;
7071+ hw_data_t *pHwData = MTO_HAL();
7072+
7073+ sme_get_rssi(MTO_FUNC_INPUT_DATA, &rssi);
7074+ if( (RF_WB_242 == pHwData->phy_type) ||
7075+ (RF_WB_242_1 == pHwData->phy_type) ) // 20060619.5 Add
7076+ {
7077+ static u8 high_gain_mode; //this is for winbond RF switch LNA
7078+ //using different register setting
7079+
7080+ if (high_gain_mode==1)
7081+ {
7082+ if( rssi > MTO_DATA().RSSI_high )
7083+ {
7084+ //hw_set_dxx_reg(phw_data, 0x0C, 0xf8f52230);
7085+ //hw_set_dxx_reg(phw_data, 0x20, 0x05541640);
7086+ high_gain_mode=0;
7087+ }
7088+ else
7089+ {
7090+ //hw_set_dxx_reg(phw_data, 0x0C, 0xf8f51830);
7091+ //hw_set_dxx_reg(phw_data, 0x20, 0x05543E40);
7092+ high_gain_mode=1;
7093+ }
7094+ }
7095+ else //if (high_gain_mode==0)
7096+ {
7097+ if( rssi < MTO_DATA().RSSI_low )
7098+ {
7099+ //hw_set_dxx_reg(phw_data, 0x0C, 0xf8f51830);
7100+ //hw_set_dxx_reg(phw_data, 0x20, 0x05543E40);
7101+ high_gain_mode=1;
7102+ }
7103+ else
7104+ {
7105+ //hw_set_dxx_reg(phw_data, 0x0C, 0xf8f52230);
7106+ //hw_set_dxx_reg(phw_data, 0x20, 0x05541640);
7107+ high_gain_mode=0;
7108+ }
7109+ }
7110+
7111+ // Always high gain 20051014. Using the initial value only.
7112+ multiagc(MTO_FUNC_INPUT_DATA, high_gain_mode);
7113+ }
7114+}
7115+
7116+
7117+u8 CalcNewRate(MTO_FUNC_INPUT, u8 old_rate, u32 retry_cnt, u32 tx_frag_cnt)
7118+{
7119+ int i;
7120+ u8 new_rate;
7121+ u32 retry_rate;
7122+ int TxThrouput1, TxThrouput2, TxThrouput3, BestThroupht;
7123+
7124+ if(tx_frag_cnt < MTOPARA_TXCOUNT_TH_FOR_CALC_RATE()) //too few packets transmit
7125+ {
7126+ return 0xff;
7127+ }
7128+ retry_rate = Divide(retry_cnt * 100, tx_frag_cnt);
7129+
7130+ if(retry_rate > 90) retry_rate = 90; //always truncate to 90% due to lookup table size
7131+ #ifdef _PE_DTO_DUMP_
7132+ WBDEBUG(("##### Current level =%d, Retry count =%d, Frag count =%d\n",
7133+ old_rate, retry_cnt, tx_frag_cnt));
7134+ WBDEBUG(("*##* Retry rate =%d, throughput =%d\n",
7135+ retry_rate, Rate_PER_TBL[retry_rate][old_rate]));
7136+ WBDEBUG(("TxRateRec.tx_rate =%d, Retry rate = %d, throughput = %d\n",
7137+ TxRateRec.tx_rate, TxRateRec.tx_retry_rate,
7138+ Rate_PER_TBL[TxRateRec.tx_retry_rate][Level2PerTbl[TxRateRec.tx_rate]]));
7139+ WBDEBUG(("old_rate-1 =%d, Retry rate = %d, throughput = %d\n",
7140+ old_rate-1, retryrate_rec[old_rate-1],
7141+ Rate_PER_TBL[retryrate_rec[old_rate-1]][old_rate-1]));
7142+ WBDEBUG(("old_rate+1 =%d, Retry rate = %d, throughput = %d\n",
7143+ old_rate+1, retryrate_rec[old_rate+1],
7144+ Rate_PER_TBL[retryrate_rec[old_rate+1]][old_rate+1]));
7145+ #endif
7146+
7147+ //following is for record the retry rate at the different data rate
7148+ if (abs(retry_rate-retryrate_rec[old_rate])<50)//---the per TH
7149+ retryrate_rec[old_rate] = retry_rate; //update retry rate
7150+ else
7151+ {
7152+ for (i=0;i<MTO_DataRateAvailableLevel;i++) //reset all retry rate
7153+ retryrate_rec[i]=0;
7154+ retryrate_rec[old_rate] = retry_rate;
7155+ #ifdef _PE_DTO_DUMP_
7156+ WBDEBUG(("Reset retry rate table\n"));
7157+ #endif
7158+ }
7159+
7160+ if(TxRateRec.tx_rate > old_rate) //Decrease Tx Rate
7161+ {
7162+ TxThrouput1 = Rate_PER_TBL[TxRateRec.tx_retry_rate][Level2PerTbl[TxRateRec.tx_rate]];
7163+ TxThrouput2 = Rate_PER_TBL[retry_rate][Level2PerTbl[old_rate]];
7164+ if(TxThrouput1 > TxThrouput2)
7165+ {
7166+ new_rate = TxRateRec.tx_rate;
7167+ BestThroupht = TxThrouput1;
7168+ }
7169+ else
7170+ {
7171+ new_rate = old_rate;
7172+ BestThroupht = TxThrouput2;
7173+ }
7174+ if((old_rate > 0) &&(retry_rate>MTOPARA_TXRATE_DEC_TH())) //Min Rate
7175+ {
7176+ TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate-1]][Level2PerTbl[old_rate-1]];
7177+ if(BestThroupht < TxThrouput3)
7178+ {
7179+ new_rate = old_rate - 1;
7180+ #ifdef _PE_DTO_DUMP_
7181+ WBDEBUG(("--------\n"));
7182+ #endif
7183+ BestThroupht = TxThrouput3;
7184+ }
7185+ }
7186+ }
7187+ else if(TxRateRec.tx_rate < old_rate) //Increase Tx Rate
7188+ {
7189+ TxThrouput1 = Rate_PER_TBL[TxRateRec.tx_retry_rate][Level2PerTbl[TxRateRec.tx_rate]];
7190+ TxThrouput2 = Rate_PER_TBL[retry_rate][Level2PerTbl[old_rate]];
7191+ if(TxThrouput1 > TxThrouput2)
7192+ {
7193+ new_rate = TxRateRec.tx_rate;
7194+ BestThroupht = TxThrouput1;
7195+ }
7196+ else
7197+ {
7198+ new_rate = old_rate;
7199+ BestThroupht = TxThrouput2;
7200+ }
7201+ if ((old_rate < MTO_DataRateAvailableLevel - 1)&&(retry_rate<MTOPARA_TXRATE_INC_TH()))
7202+ {
7203+ //TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate+1]][Level2PerTbl[old_rate+1]];
7204+ if (retryrate_rec[old_rate+1] > MTOPARA_TXRETRYRATE_REDUCE())
7205+ TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate+1]-MTOPARA_TXRETRYRATE_REDUCE()][Level2PerTbl[old_rate+1]];
7206+ else
7207+ TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate+1]][Level2PerTbl[old_rate+1]];
7208+ if(BestThroupht < TxThrouput3)
7209+ {
7210+ new_rate = old_rate + 1;
7211+ #ifdef _PE_DTO_DUMP_
7212+ WBDEBUG(("++++++++++\n"));
7213+ #endif
7214+ BestThroupht = TxThrouput3;
7215+ }
7216+ }
7217+ }
7218+ else //Tx Rate no change
7219+ {
7220+ TxThrouput2 = Rate_PER_TBL[retry_rate][Level2PerTbl[old_rate]];
7221+ new_rate = old_rate;
7222+ BestThroupht = TxThrouput2;
7223+
7224+ if (retry_rate <MTOPARA_TXRATE_EQ_TH()) //th for change higher rate
7225+ {
7226+ if(old_rate < MTO_DataRateAvailableLevel - 1)
7227+ {
7228+ //TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate+1]][Level2PerTbl[old_rate+1]];
7229+ if (retryrate_rec[old_rate+1] > MTOPARA_TXRETRYRATE_REDUCE())
7230+ TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate+1]-MTOPARA_TXRETRYRATE_REDUCE()][Level2PerTbl[old_rate+1]];
7231+ else
7232+ TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate+1]][Level2PerTbl[old_rate+1]];
7233+ if(BestThroupht < TxThrouput3)
7234+ {
7235+ new_rate = old_rate + 1;
7236+ BestThroupht = TxThrouput3;
7237+ #ifdef _PE_DTO_DUMP_
7238+ WBDEBUG(("=++++++++++\n"));
7239+ #endif
7240+ }
7241+ }
7242+ }
7243+ else
7244+ if(old_rate > 0) //Min Rate
7245+ {
7246+ TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate-1]][Level2PerTbl[old_rate-1]];
7247+ if(BestThroupht < TxThrouput3)
7248+ {
7249+ new_rate = old_rate - 1;
7250+ #ifdef _PE_DTO_DUMP_
7251+ WBDEBUG(("=--------\n"));
7252+ #endif
7253+ BestThroupht = TxThrouput3;
7254+ }
7255+ }
7256+ }
7257+
7258+ if (!LOCAL_IS_IBSS_MODE())
7259+ {
7260+ max_rssi_rate = GetMaxRateLevelFromRSSI();
7261+ #ifdef _PE_DTO_DUMP_
7262+ WBDEBUG(("[MTO]:RSSI2Rate=%d\n", MTO_Data_Rate_Tbl[max_rssi_rate]));
7263+ #endif
7264+ if(new_rate > max_rssi_rate)
7265+ new_rate = max_rssi_rate;
7266+ }
7267+
7268+ //save new rate;
7269+ TxRateRec.tx_rate = old_rate;
7270+ TxRateRec.tx_retry_rate = (u8) retry_rate;
7271+ TxRetryRate = retry_rate;
7272+ return new_rate;
7273+}
7274+
7275+void SmoothRSSI(s32 new_rssi)
7276+{
7277+ RSSISmoothed = RSSISmoothed + new_rssi - RSSIBuf[RSSIBufIndex];
7278+ RSSIBuf[RSSIBufIndex] = new_rssi;
7279+ RSSIBufIndex = (RSSIBufIndex + 1) % 10;
7280+}
7281+
7282+u8 GetMaxRateLevelFromRSSI(void)
7283+{
7284+ u8 i;
7285+ u8 TxRate;
7286+
7287+ for(i=0;i<RSSI2RATE_SIZE;i++)
7288+ {
7289+ if(RSSISmoothed > RSSI2RateTbl[i].RSSI)
7290+ break;
7291+ }
7292+ #ifdef _PE_DTO_DUMP_
7293+ WBDEBUG(("[MTO]:RSSI=%d\n", Divide(RSSISmoothed, 10)));
7294+ #endif
7295+ if(i < RSSI2RATE_SIZE)
7296+ TxRate = RSSI2RateTbl[i].TxRate;
7297+ else
7298+ TxRate = 2; //divided by 2 = 1Mbps
7299+
7300+ for(i=MTO_DataRateAvailableLevel-1;i>0;i--)
7301+ {
7302+ if(TxRate >=MTO_Data_Rate_Tbl[i])
7303+ break;
7304+ }
7305+ return i;
7306+}
7307+
7308+//===========================================================================
7309+// Description:
7310+// If we enable DTO, we will ignore the tx count with different tx rate from
7311+// DTO rate. This is because when we adjust DTO tx rate, there could be some
7312+// packets in the tx queue with previous tx rate
7313+void MTO_SetTxCount(MTO_FUNC_INPUT, u8 tx_rate, u8 index)
7314+{
7315+ MTO_TXFLOWCOUNT()++;
7316+ if ((MTO_ENABLE==1) && (MTO_RATE_CHANGE_ENABLE()==1))
7317+ {
7318+ if(tx_rate == MTO_DATA_RATE())
7319+ {
7320+ if (index == 0)
7321+ {
7322+ if (boSparseTxTraffic)
7323+ MTO_HAL()->dto_tx_frag_count += MTOPARA_PERIODIC_CHECK_CYCLE();
7324+ else
7325+ MTO_HAL()->dto_tx_frag_count += 1;
7326+ }
7327+ else
7328+ {
7329+ if (index<8)
7330+ {
7331+ MTO_HAL()->dto_tx_retry_count += index;
7332+ MTO_HAL()->dto_tx_frag_count += (index+1);
7333+ }
7334+ else
7335+ {
7336+ MTO_HAL()->dto_tx_retry_count += 7;
7337+ MTO_HAL()->dto_tx_frag_count += 7;
7338+ }
7339+ }
7340+ }
7341+ else if(MTO_DATA_RATE()>48 && tx_rate ==48)
7342+ {//ALFRED
7343+ if (index<3) //for reduciing data rate scheme ,
7344+ //do not calcu different data rate
7345+ //3 is the reducing data rate at retry
7346+ {
7347+ MTO_HAL()->dto_tx_retry_count += index;
7348+ MTO_HAL()->dto_tx_frag_count += (index+1);
7349+ }
7350+ else
7351+ {
7352+ MTO_HAL()->dto_tx_retry_count += 3;
7353+ MTO_HAL()->dto_tx_frag_count += 3;
7354+ }
7355+
7356+ }
7357+ }
7358+ else
7359+ {
7360+ MTO_HAL()->dto_tx_retry_count += index;
7361+ MTO_HAL()->dto_tx_frag_count += (index+1);
7362+ }
7363+ TotalTxPkt ++;
7364+ TotalTxPktRetry += (index+1);
7365+
7366+ PeriodTotalTxPkt ++;
7367+ PeriodTotalTxPktRetry += (index+1);
7368+}
7369+
7370+u8 MTO_GetTxFallbackRate(MTO_FUNC_INPUT)
7371+{
7372+ return MTO_DATA_FALLBACK_RATE();
7373+}
7374+
7375+
7376+//===========================================================================
7377+// MTO_TxFailed --
7378+//
7379+// Description:
7380+// Failure of transmitting a packet indicates that certain MTO parmeters
7381+// may need to be adjusted. This function is called when NIC just failed
7382+// to transmit a packet or when MSDULifeTime expired.
7383+//
7384+// Arguments:
7385+// Adapter - The pointer to the Miniport Adapter Context
7386+//
7387+// Return Value:
7388+// None
7389+//============================================================================
7390+void MTO_TxFailed(MTO_FUNC_INPUT)
7391+{
7392+ return;
7393+}
7394+
7395+int Divide(int a, int b)
7396+{
7397+ if (b==0) b=1;
7398+ return a/b;
7399+}
7400+
7401+
7402diff --git a/drivers/staging/winbond/mto.h b/drivers/staging/winbond/mto.h
7403new file mode 100644
7404index 0000000..f47936f
7405--- /dev/null
7406+++ b/drivers/staging/winbond/mto.h
7407@@ -0,0 +1,265 @@
7408+//==================================================================
7409+// MTO.H
7410+//
7411+// Revision history
7412+//=================================
7413+// 20030110 UN20 Pete Chao
7414+// Initial Release
7415+//
7416+// Copyright (c) 2003 Winbond Electronics Corp. All rights reserved.
7417+//==================================================================
7418+#ifndef __MTO_H__
7419+#define __MTO_H__
7420+
7421+#define MTO_DEFAULT_TH_CNT 5
7422+#define MTO_DEFAULT_TH_SQ3 112 //OLD IS 13 reference JohnXu
7423+#define MTO_DEFAULT_TH_IDLE_SLOT 15
7424+#define MTO_DEFAULT_TH_PR_INTERF 30
7425+#define MTO_DEFAULT_TMR_AGING 25 // unit: slot time 10 reference JohnXu
7426+#define MTO_DEFAULT_TMR_PERIODIC 5 // unit: slot time
7427+
7428+#define MTO_ANTENNA_DIVERSITY_OFF 0
7429+#define MTO_ANTENNA_DIVERSITY_ON 1
7430+
7431+// LA20040210_DTO kevin
7432+//#define MTO_PREAMBLE_LONG 0
7433+//#define MTO_PREAMBLE_SHORT 1
7434+#define MTO_PREAMBLE_LONG WLAN_PREAMBLE_TYPE_LONG
7435+#define MTO_PREAMBLE_SHORT WLAN_PREAMBLE_TYPE_SHORT
7436+
7437+typedef enum {
7438+ TOGGLE_STATE_IDLE = 0,
7439+ TOGGLE_STATE_WAIT0 = 1,
7440+ TOGGLE_STATE_WAIT1 = 2,
7441+ TOGGLE_STATE_MAKEDESISION = 3,
7442+ TOGGLE_STATE_BKOFF = 4
7443+} TOGGLE_STATE;
7444+
7445+typedef enum {
7446+ RATE_CHGSTATE_IDLE = 0,
7447+ RATE_CHGSTATE_CALCULATE = 1,
7448+ RATE_CHGSTATE_BACKOFF = 2
7449+} TX_RATE_REDUCTION_STATE;
7450+
7451+//============================================================================
7452+// struct _MTOParameters --
7453+//
7454+// Defines the parameters used in the MAC Throughput Optimization algorithm
7455+//============================================================================
7456+typedef struct _MTO_PARAMETERS
7457+{
7458+ u8 Th_Fixant;
7459+ u8 Th_Cnt;
7460+ u8 Th_SQ3;
7461+ u8 Th_IdleSlot;
7462+
7463+ u16 Tmr_Aging;
7464+ u8 Th_PrInterf;
7465+ u8 Tmr_Periodic;
7466+
7467+ //--------- wkchen added -------------
7468+ u32 TxFlowCount; //to judge what kind the tx flow(sparse or busy) is
7469+ //------------------------------------------------
7470+
7471+ //--------- DTO threshold parameters -------------
7472+ u16 DTO_PeriodicCheckCycle;
7473+ u16 DTO_RssiThForAntDiv;
7474+
7475+ u16 DTO_TxCountThForCalcNewRate;
7476+ u16 DTO_TxRateIncTh;
7477+
7478+ u16 DTO_TxRateDecTh;
7479+ u16 DTO_TxRateEqTh;
7480+
7481+ u16 DTO_TxRateBackOff;
7482+ u16 DTO_TxRetryRateReduce;
7483+
7484+ u16 DTO_TxPowerIndex; //0 ~ 31
7485+ u16 reserved_1;
7486+ //------------------------------------------------
7487+
7488+ u8 PowerChangeEnable;
7489+ u8 AntDiversityEnable;
7490+ u8 Ant_mac;
7491+ u8 Ant_div;
7492+
7493+ u8 CCA_Mode;
7494+ u8 CCA_Mode_Setup;
7495+ u8 Preamble_Type;
7496+ u8 PreambleChangeEnable;
7497+
7498+ u8 DataRateLevel;
7499+ u8 DataRateChangeEnable;
7500+ u8 FragThresholdLevel;
7501+ u8 FragThresholdChangeEnable;
7502+
7503+ u16 RTSThreshold;
7504+ u16 RTSThreshold_Setup;
7505+
7506+ u32 AvgIdleSlot;
7507+ u32 Pr_Interf;
7508+ u32 AvgGapBtwnInterf;
7509+
7510+ u8 RTSChangeEnable;
7511+ u8 Ant_sel;
7512+ u8 aging_timeout;
7513+ u8 reserved_2;
7514+
7515+ u32 Cnt_Ant[2];
7516+ u32 SQ_Ant[2];
7517+
7518+// 20040510 remove from globe vairable
7519+ u32 TmrCnt;
7520+ u32 BackoffTmr;
7521+ TOGGLE_STATE ToggleState;
7522+ TX_RATE_REDUCTION_STATE TxRateReductionState;
7523+
7524+ u8 Last_Rate;
7525+ u8 Co_efficent;
7526+ u8 FallbackRateLevel;
7527+ u8 OfdmRateLevel;
7528+
7529+ u8 RatePolicy;
7530+ u8 reserved_3[3];
7531+
7532+ // For RSSI turning
7533+ s32 RSSI_high;
7534+ s32 RSSI_low;
7535+
7536+} MTO_PARAMETERS, *PMTO_PARAMETERS;
7537+
7538+
7539+#define MTO_FUNC_INPUT PWB32_ADAPTER Adapter
7540+#define MTO_FUNC_INPUT_DATA Adapter
7541+#define MTO_DATA() (Adapter->sMtoPara)
7542+#define MTO_HAL() (&Adapter->sHwData)
7543+#define MTO_SET_PREAMBLE_TYPE(x) // 20040511 Turbo mark LM_PREAMBLE_TYPE(&pcore_data->lm_data) = (x)
7544+#define MTO_ENABLE (Adapter->sLocalPara.TxRateMode == RATE_AUTO)
7545+#define MTO_TXPOWER_FROM_EEPROM (Adapter->sHwData.PowerIndexFromEEPROM)
7546+#define LOCAL_ANTENNA_NO() (Adapter->sLocalPara.bAntennaNo)
7547+#define LOCAL_IS_CONNECTED() (Adapter->sLocalPara.wConnectedSTAindex != 0)
7548+#define LOCAL_IS_IBSS_MODE() (Adapter->asBSSDescriptElement[Adapter->sLocalPara.wConnectedSTAindex].bBssType == IBSS_NET)
7549+#define MTO_INITTXRATE_MODE (Adapter->sHwData.SoftwareSet&0x2) //bit 1
7550+// 20040510 Turbo add
7551+#define MTO_TMR_CNT() MTO_DATA().TmrCnt
7552+#define MTO_TOGGLE_STATE() MTO_DATA().ToggleState
7553+#define MTO_TX_RATE_REDUCTION_STATE() MTO_DATA().TxRateReductionState
7554+#define MTO_BACKOFF_TMR() MTO_DATA().BackoffTmr
7555+#define MTO_LAST_RATE() MTO_DATA().Last_Rate
7556+#define MTO_CO_EFFICENT() MTO_DATA().Co_efficent
7557+
7558+#define MTO_TH_CNT() MTO_DATA().Th_Cnt
7559+#define MTO_TH_SQ3() MTO_DATA().Th_SQ3
7560+#define MTO_TH_IDLE_SLOT() MTO_DATA().Th_IdleSlot
7561+#define MTO_TH_PR_INTERF() MTO_DATA().Th_PrInterf
7562+
7563+#define MTO_TMR_AGING() MTO_DATA().Tmr_Aging
7564+#define MTO_TMR_PERIODIC() MTO_DATA().Tmr_Periodic
7565+
7566+#define MTO_POWER_CHANGE_ENABLE() MTO_DATA().PowerChangeEnable
7567+#define MTO_ANT_DIVERSITY_ENABLE() Adapter->sLocalPara.boAntennaDiversity
7568+#define MTO_ANT_MAC() MTO_DATA().Ant_mac
7569+#define MTO_ANT_DIVERSITY() MTO_DATA().Ant_div
7570+#define MTO_CCA_MODE() MTO_DATA().CCA_Mode
7571+#define MTO_CCA_MODE_SETUP() MTO_DATA().CCA_Mode_Setup
7572+#define MTO_PREAMBLE_TYPE() MTO_DATA().Preamble_Type
7573+#define MTO_PREAMBLE_CHANGE_ENABLE() MTO_DATA().PreambleChangeEnable
7574+
7575+#define MTO_RATE_LEVEL() MTO_DATA().DataRateLevel
7576+#define MTO_FALLBACK_RATE_LEVEL() MTO_DATA().FallbackRateLevel
7577+#define MTO_OFDM_RATE_LEVEL() MTO_DATA().OfdmRateLevel
7578+#define MTO_RATE_CHANGE_ENABLE() MTO_DATA().DataRateChangeEnable
7579+#define MTO_FRAG_TH_LEVEL() MTO_DATA().FragThresholdLevel
7580+#define MTO_FRAG_CHANGE_ENABLE() MTO_DATA().FragThresholdChangeEnable
7581+#define MTO_RTS_THRESHOLD() MTO_DATA().RTSThreshold
7582+#define MTO_RTS_CHANGE_ENABLE() MTO_DATA().RTSChangeEnable
7583+#define MTO_RTS_THRESHOLD_SETUP() MTO_DATA().RTSThreshold_Setup
7584+
7585+#define MTO_AVG_IDLE_SLOT() MTO_DATA().AvgIdleSlot
7586+#define MTO_PR_INTERF() MTO_DATA().Pr_Interf
7587+#define MTO_AVG_GAP_BTWN_INTERF() MTO_DATA().AvgGapBtwnInterf
7588+
7589+#define MTO_ANT_SEL() MTO_DATA().Ant_sel
7590+#define MTO_CNT_ANT(x) MTO_DATA().Cnt_Ant[(x)]
7591+#define MTO_SQ_ANT(x) MTO_DATA().SQ_Ant[(x)]
7592+#define MTO_AGING_TIMEOUT() MTO_DATA().aging_timeout
7593+
7594+
7595+#define MTO_TXFLOWCOUNT() MTO_DATA().TxFlowCount
7596+//--------- DTO threshold parameters -------------
7597+#define MTOPARA_PERIODIC_CHECK_CYCLE() MTO_DATA().DTO_PeriodicCheckCycle
7598+#define MTOPARA_RSSI_TH_FOR_ANTDIV() MTO_DATA().DTO_RssiThForAntDiv
7599+#define MTOPARA_TXCOUNT_TH_FOR_CALC_RATE() MTO_DATA().DTO_TxCountThForCalcNewRate
7600+#define MTOPARA_TXRATE_INC_TH() MTO_DATA().DTO_TxRateIncTh
7601+#define MTOPARA_TXRATE_DEC_TH() MTO_DATA().DTO_TxRateDecTh
7602+#define MTOPARA_TXRATE_EQ_TH() MTO_DATA().DTO_TxRateEqTh
7603+#define MTOPARA_TXRATE_BACKOFF() MTO_DATA().DTO_TxRateBackOff
7604+#define MTOPARA_TXRETRYRATE_REDUCE() MTO_DATA().DTO_TxRetryRateReduce
7605+#define MTOPARA_TXPOWER_INDEX() MTO_DATA().DTO_TxPowerIndex
7606+//------------------------------------------------
7607+
7608+
7609+extern u8 MTO_Data_Rate_Tbl[];
7610+extern u16 MTO_Frag_Th_Tbl[];
7611+
7612+#define MTO_DATA_RATE() MTO_Data_Rate_Tbl[MTO_RATE_LEVEL()]
7613+#define MTO_DATA_FALLBACK_RATE() MTO_Data_Rate_Tbl[MTO_FALLBACK_RATE_LEVEL()] //next level
7614+#define MTO_FRAG_TH() MTO_Frag_Th_Tbl[MTO_FRAG_TH_LEVEL()]
7615+
7616+typedef struct {
7617+ u8 tx_rate;
7618+ u8 tx_retry_rate;
7619+} TXRETRY_REC;
7620+
7621+typedef struct _STATISTICS_INFO {
7622+ u32 Rate54M;
7623+ u32 Rate48M;
7624+ u32 Rate36M;
7625+ u32 Rate24M;
7626+ u32 Rate18M;
7627+ u32 Rate12M;
7628+ u32 Rate9M;
7629+ u32 Rate6M;
7630+ u32 Rate11MS;
7631+ u32 Rate11ML;
7632+ u32 Rate55MS;
7633+ u32 Rate55ML;
7634+ u32 Rate2MS;
7635+ u32 Rate2ML;
7636+ u32 Rate1M;
7637+ u32 Rate54MOK;
7638+ u32 Rate48MOK;
7639+ u32 Rate36MOK;
7640+ u32 Rate24MOK;
7641+ u32 Rate18MOK;
7642+ u32 Rate12MOK;
7643+ u32 Rate9MOK;
7644+ u32 Rate6MOK;
7645+ u32 Rate11MSOK;
7646+ u32 Rate11MLOK;
7647+ u32 Rate55MSOK;
7648+ u32 Rate55MLOK;
7649+ u32 Rate2MSOK;
7650+ u32 Rate2MLOK;
7651+ u32 Rate1MOK;
7652+ u32 SQ3;
7653+ s32 RSSIAVG;
7654+ s32 RSSIMAX;
7655+ s32 TXRATE;
7656+ s32 TxRetryRate;
7657+ s32 BSS_PK_CNT;
7658+ s32 NIDLESLOT;
7659+ s32 SLOT_CNT;
7660+ s32 INTERF_CNT;
7661+ s32 GAP_CNT;
7662+ s32 DS_EVM;
7663+ s32 RcvBeaconNum;
7664+ s32 RXRATE;
7665+ s32 RxBytes;
7666+ s32 TxBytes;
7667+ s32 Antenna;
7668+} STATISTICS_INFO, *PSTATISTICS_INFO;
7669+
7670+#endif //__MTO_H__
7671+
7672+
7673diff --git a/drivers/staging/winbond/mto_f.h b/drivers/staging/winbond/mto_f.h
7674new file mode 100644
7675index 0000000..30b3df2
7676--- /dev/null
7677+++ b/drivers/staging/winbond/mto_f.h
7678@@ -0,0 +1,7 @@
7679+extern void MTO_Init(PWB32_ADAPTER);
7680+extern void MTO_PeriodicTimerExpired(PWB32_ADAPTER);
7681+extern void MTO_SetDTORateRange(PWB32_ADAPTER, u8 *, u8);
7682+extern u8 MTO_GetTxRate(MTO_FUNC_INPUT, u32 fpdu_len);
7683+extern u8 MTO_GetTxFallbackRate(MTO_FUNC_INPUT);
7684+extern void MTO_SetTxCount(MTO_FUNC_INPUT, u8 t0, u8 index);
7685+
7686diff --git a/drivers/staging/winbond/os_common.h b/drivers/staging/winbond/os_common.h
7687new file mode 100644
7688index 0000000..e24ff41
7689--- /dev/null
7690+++ b/drivers/staging/winbond/os_common.h
7691@@ -0,0 +1,2 @@
7692+#include "linux/sysdef.h"
7693+
7694diff --git a/drivers/staging/winbond/phy_calibration.c b/drivers/staging/winbond/phy_calibration.c
7695new file mode 100644
7696index 0000000..272a650
7697--- /dev/null
7698+++ b/drivers/staging/winbond/phy_calibration.c
7699@@ -0,0 +1,1759 @@
7700+/*
7701+ * phy_302_calibration.c
7702+ *
7703+ * Copyright (C) 2002, 2005 Winbond Electronics Corp.
7704+ *
7705+ * modification history
7706+ * ---------------------------------------------------------------------------
7707+ * 0.01.001, 2003-04-16, Kevin created
7708+ *
7709+ */
7710+
7711+/****************** INCLUDE FILES SECTION ***********************************/
7712+#include "os_common.h"
7713+#include "phy_calibration.h"
7714+
7715+
7716+/****************** DEBUG CONSTANT AND MACRO SECTION ************************/
7717+
7718+/****************** LOCAL CONSTANT AND MACRO SECTION ************************/
7719+#define LOOP_TIMES 20
7720+#define US 1000//MICROSECOND
7721+
7722+#define AG_CONST 0.6072529350
7723+#define FIXED(X) ((s32)((X) * 32768.0))
7724+#define DEG2RAD(X) 0.017453 * (X)
7725+
7726+/****************** LOCAL TYPE DEFINITION SECTION ***************************/
7727+typedef s32 fixed; /* 16.16 fixed-point */
7728+
7729+static const fixed Angles[]=
7730+{
7731+ FIXED(DEG2RAD(45.0)), FIXED(DEG2RAD(26.565)), FIXED(DEG2RAD(14.0362)),
7732+ FIXED(DEG2RAD(7.12502)), FIXED(DEG2RAD(3.57633)), FIXED(DEG2RAD(1.78991)),
7733+ FIXED(DEG2RAD(0.895174)),FIXED(DEG2RAD(0.447614)),FIXED(DEG2RAD(0.223811)),
7734+ FIXED(DEG2RAD(0.111906)),FIXED(DEG2RAD(0.055953)),FIXED(DEG2RAD(0.027977))
7735+};
7736+
7737+/****************** LOCAL FUNCTION DECLARATION SECTION **********************/
7738+//void _phy_rf_write_delay(hw_data_t *phw_data);
7739+//void phy_init_rf(hw_data_t *phw_data);
7740+
7741+/****************** FUNCTION DEFINITION SECTION *****************************/
7742+
7743+s32 _s13_to_s32(u32 data)
7744+{
7745+ u32 val;
7746+
7747+ val = (data & 0x0FFF);
7748+
7749+ if ((data & BIT(12)) != 0)
7750+ {
7751+ val |= 0xFFFFF000;
7752+ }
7753+
7754+ return ((s32) val);
7755+}
7756+
7757+u32 _s32_to_s13(s32 data)
7758+{
7759+ u32 val;
7760+
7761+ if (data > 4095)
7762+ {
7763+ data = 4095;
7764+ }
7765+ else if (data < -4096)
7766+ {
7767+ data = -4096;
7768+ }
7769+
7770+ val = data & 0x1FFF;
7771+
7772+ return val;
7773+}
7774+
7775+/****************************************************************************/
7776+s32 _s4_to_s32(u32 data)
7777+{
7778+ s32 val;
7779+
7780+ val = (data & 0x0007);
7781+
7782+ if ((data & BIT(3)) != 0)
7783+ {
7784+ val |= 0xFFFFFFF8;
7785+ }
7786+
7787+ return val;
7788+}
7789+
7790+u32 _s32_to_s4(s32 data)
7791+{
7792+ u32 val;
7793+
7794+ if (data > 7)
7795+ {
7796+ data = 7;
7797+ }
7798+ else if (data < -8)
7799+ {
7800+ data = -8;
7801+ }
7802+
7803+ val = data & 0x000F;
7804+
7805+ return val;
7806+}
7807+
7808+/****************************************************************************/
7809+s32 _s5_to_s32(u32 data)
7810+{
7811+ s32 val;
7812+
7813+ val = (data & 0x000F);
7814+
7815+ if ((data & BIT(4)) != 0)
7816+ {
7817+ val |= 0xFFFFFFF0;
7818+ }
7819+
7820+ return val;
7821+}
7822+
7823+u32 _s32_to_s5(s32 data)
7824+{
7825+ u32 val;
7826+
7827+ if (data > 15)
7828+ {
7829+ data = 15;
7830+ }
7831+ else if (data < -16)
7832+ {
7833+ data = -16;
7834+ }
7835+
7836+ val = data & 0x001F;
7837+
7838+ return val;
7839+}
7840+
7841+/****************************************************************************/
7842+s32 _s6_to_s32(u32 data)
7843+{
7844+ s32 val;
7845+
7846+ val = (data & 0x001F);
7847+
7848+ if ((data & BIT(5)) != 0)
7849+ {
7850+ val |= 0xFFFFFFE0;
7851+ }
7852+
7853+ return val;
7854+}
7855+
7856+u32 _s32_to_s6(s32 data)
7857+{
7858+ u32 val;
7859+
7860+ if (data > 31)
7861+ {
7862+ data = 31;
7863+ }
7864+ else if (data < -32)
7865+ {
7866+ data = -32;
7867+ }
7868+
7869+ val = data & 0x003F;
7870+
7871+ return val;
7872+}
7873+
7874+/****************************************************************************/
7875+s32 _s9_to_s32(u32 data)
7876+{
7877+ s32 val;
7878+
7879+ val = data & 0x00FF;
7880+
7881+ if ((data & BIT(8)) != 0)
7882+ {
7883+ val |= 0xFFFFFF00;
7884+ }
7885+
7886+ return val;
7887+}
7888+
7889+u32 _s32_to_s9(s32 data)
7890+{
7891+ u32 val;
7892+
7893+ if (data > 255)
7894+ {
7895+ data = 255;
7896+ }
7897+ else if (data < -256)
7898+ {
7899+ data = -256;
7900+ }
7901+
7902+ val = data & 0x01FF;
7903+
7904+ return val;
7905+}
7906+
7907+/****************************************************************************/
7908+s32 _floor(s32 n)
7909+{
7910+ if (n > 0)
7911+ {
7912+ n += 5;
7913+ }
7914+ else
7915+ {
7916+ n -= 5;
7917+ }
7918+
7919+ return (n/10);
7920+}
7921+
7922+/****************************************************************************/
7923+// The following code is sqare-root function.
7924+// sqsum is the input and the output is sq_rt;
7925+// The maximum of sqsum = 2^27 -1;
7926+u32 _sqrt(u32 sqsum)
7927+{
7928+ u32 sq_rt;
7929+
7930+ int g0, g1, g2, g3, g4;
7931+ int seed;
7932+ int next;
7933+ int step;
7934+
7935+ g4 = sqsum / 100000000;
7936+ g3 = (sqsum - g4*100000000) /1000000;
7937+ g2 = (sqsum - g4*100000000 - g3*1000000) /10000;
7938+ g1 = (sqsum - g4*100000000 - g3*1000000 - g2*10000) /100;
7939+ g0 = (sqsum - g4*100000000 - g3*1000000 - g2*10000 - g1*100);
7940+
7941+ next = g4;
7942+ step = 0;
7943+ seed = 0;
7944+ while (((seed+1)*(step+1)) <= next)
7945+ {
7946+ step++;
7947+ seed++;
7948+ }
7949+
7950+ sq_rt = seed * 10000;
7951+ next = (next-(seed*step))*100 + g3;
7952+
7953+ step = 0;
7954+ seed = 2 * seed * 10;
7955+ while (((seed+1)*(step+1)) <= next)
7956+ {
7957+ step++;
7958+ seed++;
7959+ }
7960+
7961+ sq_rt = sq_rt + step * 1000;
7962+ next = (next - seed * step) * 100 + g2;
7963+ seed = (seed + step) * 10;
7964+ step = 0;
7965+ while (((seed+1)*(step+1)) <= next)
7966+ {
7967+ step++;
7968+ seed++;
7969+ }
7970+
7971+ sq_rt = sq_rt + step * 100;
7972+ next = (next - seed * step) * 100 + g1;
7973+ seed = (seed + step) * 10;
7974+ step = 0;
7975+
7976+ while (((seed+1)*(step+1)) <= next)
7977+ {
7978+ step++;
7979+ seed++;
7980+ }
7981+
7982+ sq_rt = sq_rt + step * 10;
7983+ next = (next - seed* step) * 100 + g0;
7984+ seed = (seed + step) * 10;
7985+ step = 0;
7986+
7987+ while (((seed+1)*(step+1)) <= next)
7988+ {
7989+ step++;
7990+ seed++;
7991+ }
7992+
7993+ sq_rt = sq_rt + step;
7994+
7995+ return sq_rt;
7996+}
7997+
7998+/****************************************************************************/
7999+void _sin_cos(s32 angle, s32 *sin, s32 *cos)
8000+{
8001+ fixed X, Y, TargetAngle, CurrAngle;
8002+ unsigned Step;
8003+
8004+ X=FIXED(AG_CONST); // AG_CONST * cos(0)
8005+ Y=0; // AG_CONST * sin(0)
8006+ TargetAngle=abs(angle);
8007+ CurrAngle=0;
8008+
8009+ for (Step=0; Step < 12; Step++)
8010+ {
8011+ fixed NewX;
8012+
8013+ if(TargetAngle > CurrAngle)
8014+ {
8015+ NewX=X - (Y >> Step);
8016+ Y=(X >> Step) + Y;
8017+ X=NewX;
8018+ CurrAngle += Angles[Step];
8019+ }
8020+ else
8021+ {
8022+ NewX=X + (Y >> Step);
8023+ Y=-(X >> Step) + Y;
8024+ X=NewX;
8025+ CurrAngle -= Angles[Step];
8026+ }
8027+ }
8028+
8029+ if (angle > 0)
8030+ {
8031+ *cos = X;
8032+ *sin = Y;
8033+ }
8034+ else
8035+ {
8036+ *cos = X;
8037+ *sin = -Y;
8038+ }
8039+}
8040+
8041+
8042+void _reset_rx_cal(hw_data_t *phw_data)
8043+{
8044+ u32 val;
8045+
8046+ hw_get_dxx_reg(phw_data, 0x54, &val);
8047+
8048+ if (phw_data->revision == 0x2002) // 1st-cut
8049+ {
8050+ val &= 0xFFFF0000;
8051+ }
8052+ else // 2nd-cut
8053+ {
8054+ val &= 0x000003FF;
8055+ }
8056+
8057+ hw_set_dxx_reg(phw_data, 0x54, val);
8058+}
8059+
8060+
8061+// ************for winbond calibration*********
8062+//
8063+
8064+//
8065+//
8066+// *********************************************
8067+void _rxadc_dc_offset_cancellation_winbond(hw_data_t *phw_data, u32 frequency)
8068+{
8069+ u32 reg_agc_ctrl3;
8070+ u32 reg_a_acq_ctrl;
8071+ u32 reg_b_acq_ctrl;
8072+ u32 val;
8073+
8074+ PHY_DEBUG(("[CAL] -> [1]_rxadc_dc_offset_cancellation()\n"));
8075+ phy_init_rf(phw_data);
8076+
8077+ // set calibration channel
8078+ if( (RF_WB_242 == phw_data->phy_type) ||
8079+ (RF_WB_242_1 == phw_data->phy_type) ) // 20060619.5 Add
8080+ {
8081+ if ((frequency >= 2412) && (frequency <= 2484))
8082+ {
8083+ // w89rf242 change frequency to 2390Mhz
8084+ PHY_DEBUG(("[CAL] W89RF242/11G/Channel=2390Mhz\n"));
8085+ phy_set_rf_data(phw_data, 3, (3<<24)|0x025586);
8086+
8087+ }
8088+ }
8089+ else
8090+ {
8091+
8092+ }
8093+
8094+ // reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel
8095+ hw_get_dxx_reg(phw_data, 0x5C, &val);
8096+ val &= ~(0x03FF);
8097+ hw_set_dxx_reg(phw_data, 0x5C, val);
8098+
8099+ // reset the TX and RX IQ calibration data
8100+ hw_set_dxx_reg(phw_data, 0x3C, 0);
8101+ hw_set_dxx_reg(phw_data, 0x54, 0);
8102+
8103+ hw_set_dxx_reg(phw_data, 0x58, 0x30303030); // IQ_Alpha Changed
8104+
8105+ // a. Disable AGC
8106+ hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3);
8107+ reg_agc_ctrl3 &= ~BIT(2);
8108+ reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
8109+ hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
8110+
8111+ hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val);
8112+ val |= MASK_AGC_FIX_GAIN;
8113+ hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
8114+
8115+ // b. Turn off BB RX
8116+ hw_get_dxx_reg(phw_data, REG_A_ACQ_CTRL, &reg_a_acq_ctrl);
8117+ reg_a_acq_ctrl |= MASK_AMER_OFF_REG;
8118+ hw_set_dxx_reg(phw_data, REG_A_ACQ_CTRL, reg_a_acq_ctrl);
8119+
8120+ hw_get_dxx_reg(phw_data, REG_B_ACQ_CTRL, &reg_b_acq_ctrl);
8121+ reg_b_acq_ctrl |= MASK_BMER_OFF_REG;
8122+ hw_set_dxx_reg(phw_data, REG_B_ACQ_CTRL, reg_b_acq_ctrl);
8123+
8124+ // c. Make sure MAC is in receiving mode
8125+ // d. Turn ON ADC calibration
8126+ // - ADC calibrator is triggered by this signal rising from 0 to 1
8127+ hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val);
8128+ val &= ~MASK_ADC_DC_CAL_STR;
8129+ hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val);
8130+
8131+ val |= MASK_ADC_DC_CAL_STR;
8132+ hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val);
8133+ pa_stall_execution(US); // *MUST* wait for a while
8134+
8135+ // e. The result are shown in "adc_dc_cal_i[8:0] and adc_dc_cal_q[8:0]"
8136+#ifdef _DEBUG
8137+ hw_get_dxx_reg(phw_data, REG_OFFSET_READ, &val);
8138+ PHY_DEBUG(("[CAL] REG_OFFSET_READ = 0x%08X\n", val));
8139+
8140+ PHY_DEBUG(("[CAL] ** adc_dc_cal_i = %d (0x%04X)\n",
8141+ _s9_to_s32(val&0x000001FF), val&0x000001FF));
8142+ PHY_DEBUG(("[CAL] ** adc_dc_cal_q = %d (0x%04X)\n",
8143+ _s9_to_s32((val&0x0003FE00)>>9), (val&0x0003FE00)>>9));
8144+#endif
8145+
8146+ hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val);
8147+ val &= ~MASK_ADC_DC_CAL_STR;
8148+ hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val);
8149+
8150+ // f. Turn on BB RX
8151+ //hw_get_dxx_reg(phw_data, REG_A_ACQ_CTRL, &reg_a_acq_ctrl);
8152+ reg_a_acq_ctrl &= ~MASK_AMER_OFF_REG;
8153+ hw_set_dxx_reg(phw_data, REG_A_ACQ_CTRL, reg_a_acq_ctrl);
8154+
8155+ //hw_get_dxx_reg(phw_data, REG_B_ACQ_CTRL, &reg_b_acq_ctrl);
8156+ reg_b_acq_ctrl &= ~MASK_BMER_OFF_REG;
8157+ hw_set_dxx_reg(phw_data, REG_B_ACQ_CTRL, reg_b_acq_ctrl);
8158+
8159+ // g. Enable AGC
8160+ //hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val);
8161+ reg_agc_ctrl3 |= BIT(2);
8162+ reg_agc_ctrl3 &= ~(MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
8163+ hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
8164+}
8165+
8166+////////////////////////////////////////////////////////
8167+void _txidac_dc_offset_cancellation_winbond(hw_data_t *phw_data)
8168+{
8169+ u32 reg_agc_ctrl3;
8170+ u32 reg_mode_ctrl;
8171+ u32 reg_dc_cancel;
8172+ s32 iqcal_image_i;
8173+ s32 iqcal_image_q;
8174+ u32 sqsum;
8175+ s32 mag_0;
8176+ s32 mag_1;
8177+ s32 fix_cancel_dc_i = 0;
8178+ u32 val;
8179+ int loop;
8180+
8181+ PHY_DEBUG(("[CAL] -> [2]_txidac_dc_offset_cancellation()\n"));
8182+
8183+ // a. Set to "TX calibration mode"
8184+
8185+ //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits
8186+ phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2);
8187+ //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit
8188+ phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6);
8189+ //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized
8190+ phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A);
8191+ //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized
8192+ phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C);
8193+ //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode
8194+ phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
8195+
8196+ hw_set_dxx_reg(phw_data, 0x58, 0x30303030); // IQ_Alpha Changed
8197+
8198+ // a. Disable AGC
8199+ hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3);
8200+ reg_agc_ctrl3 &= ~BIT(2);
8201+ reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
8202+ hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
8203+
8204+ hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val);
8205+ val |= MASK_AGC_FIX_GAIN;
8206+ hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
8207+
8208+ // b. set iqcal_mode[1:0] to 0x2 and set iqcal_tone[3:2] to 0
8209+ hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
8210+
8211+ PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
8212+ reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE);
8213+
8214+ // mode=2, tone=0
8215+ //reg_mode_ctrl |= (MASK_CALIB_START|2);
8216+
8217+ // mode=2, tone=1
8218+ //reg_mode_ctrl |= (MASK_CALIB_START|2|(1<<2));
8219+
8220+ // mode=2, tone=2
8221+ reg_mode_ctrl |= (MASK_CALIB_START|2|(2<<2));
8222+ hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
8223+ PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
8224+ pa_stall_execution(US);
8225+
8226+ hw_get_dxx_reg(phw_data, 0x5C, &reg_dc_cancel);
8227+ PHY_DEBUG(("[CAL] DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel));
8228+
8229+ for (loop = 0; loop < LOOP_TIMES; loop++)
8230+ {
8231+ PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop));
8232+
8233+ // c.
8234+ // reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel
8235+ reg_dc_cancel &= ~(0x03FF);
8236+ PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
8237+ hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
8238+ pa_stall_execution(US);
8239+
8240+ hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
8241+ PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val));
8242+
8243+ iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
8244+ iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
8245+ sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q;
8246+ mag_0 = (s32) _sqrt(sqsum);
8247+ PHY_DEBUG(("[CAL] mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
8248+ mag_0, iqcal_image_i, iqcal_image_q));
8249+
8250+ // d.
8251+ reg_dc_cancel |= (1 << CANCEL_DC_I_SHIFT);
8252+ PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
8253+ hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
8254+ pa_stall_execution(US);
8255+
8256+ hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
8257+ PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val));
8258+
8259+ iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
8260+ iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
8261+ sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q;
8262+ mag_1 = (s32) _sqrt(sqsum);
8263+ PHY_DEBUG(("[CAL] mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
8264+ mag_1, iqcal_image_i, iqcal_image_q));
8265+
8266+ // e. Calculate the correct DC offset cancellation value for I
8267+ if (mag_0 != mag_1)
8268+ {
8269+ fix_cancel_dc_i = (mag_0*10000) / (mag_0*10000 - mag_1*10000);
8270+ }
8271+ else
8272+ {
8273+ if (mag_0 == mag_1)
8274+ {
8275+ PHY_DEBUG(("[CAL] ***** mag_0 = mag_1 !!\n"));
8276+ }
8277+
8278+ fix_cancel_dc_i = 0;
8279+ }
8280+
8281+ PHY_DEBUG(("[CAL] ** fix_cancel_dc_i = %d (0x%04X)\n",
8282+ fix_cancel_dc_i, _s32_to_s5(fix_cancel_dc_i)));
8283+
8284+ if ((abs(mag_1-mag_0)*6) > mag_0)
8285+ {
8286+ break;
8287+ }
8288+ }
8289+
8290+ if ( loop >= 19 )
8291+ fix_cancel_dc_i = 0;
8292+
8293+ reg_dc_cancel &= ~(0x03FF);
8294+ reg_dc_cancel |= (_s32_to_s5(fix_cancel_dc_i) << CANCEL_DC_I_SHIFT);
8295+ hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
8296+ PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
8297+
8298+ // g.
8299+ reg_mode_ctrl &= ~MASK_CALIB_START;
8300+ hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
8301+ PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
8302+ pa_stall_execution(US);
8303+}
8304+
8305+///////////////////////////////////////////////////////
8306+void _txqdac_dc_offset_cacellation_winbond(hw_data_t *phw_data)
8307+{
8308+ u32 reg_agc_ctrl3;
8309+ u32 reg_mode_ctrl;
8310+ u32 reg_dc_cancel;
8311+ s32 iqcal_image_i;
8312+ s32 iqcal_image_q;
8313+ u32 sqsum;
8314+ s32 mag_0;
8315+ s32 mag_1;
8316+ s32 fix_cancel_dc_q = 0;
8317+ u32 val;
8318+ int loop;
8319+
8320+ PHY_DEBUG(("[CAL] -> [3]_txqdac_dc_offset_cacellation()\n"));
8321+ //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits
8322+ phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2);
8323+ //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit
8324+ phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6);
8325+ //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized
8326+ phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A);
8327+ //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized
8328+ phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C);
8329+ //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode
8330+ phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
8331+
8332+ hw_set_dxx_reg(phw_data, 0x58, 0x30303030); // IQ_Alpha Changed
8333+
8334+ // a. Disable AGC
8335+ hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3);
8336+ reg_agc_ctrl3 &= ~BIT(2);
8337+ reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
8338+ hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
8339+
8340+ hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val);
8341+ val |= MASK_AGC_FIX_GAIN;
8342+ hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
8343+
8344+ // a. set iqcal_mode[1:0] to 0x3 and set iqcal_tone[3:2] to 0
8345+ hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
8346+ PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
8347+
8348+ //reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE);
8349+ reg_mode_ctrl &= ~(MASK_IQCAL_MODE);
8350+ reg_mode_ctrl |= (MASK_CALIB_START|3);
8351+ hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
8352+ PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
8353+ pa_stall_execution(US);
8354+
8355+ hw_get_dxx_reg(phw_data, 0x5C, &reg_dc_cancel);
8356+ PHY_DEBUG(("[CAL] DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel));
8357+
8358+ for (loop = 0; loop < LOOP_TIMES; loop++)
8359+ {
8360+ PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop));
8361+
8362+ // b.
8363+ // reset cancel_dc_q[4:0] in register DC_Cancel
8364+ reg_dc_cancel &= ~(0x001F);
8365+ PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
8366+ hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
8367+ pa_stall_execution(US);
8368+
8369+ hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
8370+ PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val));
8371+ pa_stall_execution(US);
8372+
8373+ iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
8374+ iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
8375+ sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q;
8376+ mag_0 = _sqrt(sqsum);
8377+ PHY_DEBUG(("[CAL] mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
8378+ mag_0, iqcal_image_i, iqcal_image_q));
8379+
8380+ // c.
8381+ reg_dc_cancel |= (1 << CANCEL_DC_Q_SHIFT);
8382+ PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
8383+ hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
8384+ pa_stall_execution(US);
8385+
8386+ hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
8387+ PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val));
8388+ pa_stall_execution(US);
8389+
8390+ iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
8391+ iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
8392+ sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q;
8393+ mag_1 = _sqrt(sqsum);
8394+ PHY_DEBUG(("[CAL] mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
8395+ mag_1, iqcal_image_i, iqcal_image_q));
8396+
8397+ // d. Calculate the correct DC offset cancellation value for I
8398+ if (mag_0 != mag_1)
8399+ {
8400+ fix_cancel_dc_q = (mag_0*10000) / (mag_0*10000 - mag_1*10000);
8401+ }
8402+ else
8403+ {
8404+ if (mag_0 == mag_1)
8405+ {
8406+ PHY_DEBUG(("[CAL] ***** mag_0 = mag_1 !!\n"));
8407+ }
8408+
8409+ fix_cancel_dc_q = 0;
8410+ }
8411+
8412+ PHY_DEBUG(("[CAL] ** fix_cancel_dc_q = %d (0x%04X)\n",
8413+ fix_cancel_dc_q, _s32_to_s5(fix_cancel_dc_q)));
8414+
8415+ if ((abs(mag_1-mag_0)*6) > mag_0)
8416+ {
8417+ break;
8418+ }
8419+ }
8420+
8421+ if ( loop >= 19 )
8422+ fix_cancel_dc_q = 0;
8423+
8424+ reg_dc_cancel &= ~(0x001F);
8425+ reg_dc_cancel |= (_s32_to_s5(fix_cancel_dc_q) << CANCEL_DC_Q_SHIFT);
8426+ hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
8427+ PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
8428+
8429+
8430+ // f.
8431+ reg_mode_ctrl &= ~MASK_CALIB_START;
8432+ hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
8433+ PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
8434+ pa_stall_execution(US);
8435+}
8436+
8437+//20060612.1.a 20060718.1 Modify
8438+u8 _tx_iq_calibration_loop_winbond(hw_data_t *phw_data,
8439+ s32 a_2_threshold,
8440+ s32 b_2_threshold)
8441+{
8442+ u32 reg_mode_ctrl;
8443+ s32 iq_mag_0_tx;
8444+ s32 iqcal_tone_i0;
8445+ s32 iqcal_tone_q0;
8446+ s32 iqcal_tone_i;
8447+ s32 iqcal_tone_q;
8448+ u32 sqsum;
8449+ s32 rot_i_b;
8450+ s32 rot_q_b;
8451+ s32 tx_cal_flt_b[4];
8452+ s32 tx_cal[4];
8453+ s32 tx_cal_reg[4];
8454+ s32 a_2, b_2;
8455+ s32 sin_b, sin_2b;
8456+ s32 cos_b, cos_2b;
8457+ s32 divisor;
8458+ s32 temp1, temp2;
8459+ u32 val;
8460+ u16 loop;
8461+ s32 iqcal_tone_i_avg,iqcal_tone_q_avg;
8462+ u8 verify_count;
8463+ int capture_time;
8464+
8465+ PHY_DEBUG(("[CAL] -> _tx_iq_calibration_loop()\n"));
8466+ PHY_DEBUG(("[CAL] ** a_2_threshold = %d\n", a_2_threshold));
8467+ PHY_DEBUG(("[CAL] ** b_2_threshold = %d\n", b_2_threshold));
8468+
8469+ verify_count = 0;
8470+
8471+ hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
8472+ PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
8473+
8474+ loop = LOOP_TIMES;
8475+
8476+ while (loop > 0)
8477+ {
8478+ PHY_DEBUG(("[CAL] [%d.] <_tx_iq_calibration_loop>\n", (LOOP_TIMES-loop+1)));
8479+
8480+ iqcal_tone_i_avg=0;
8481+ iqcal_tone_q_avg=0;
8482+ if( !hw_set_dxx_reg(phw_data, 0x3C, 0x00) ) // 20060718.1 modify
8483+ return 0;
8484+ for(capture_time=0;capture_time<10;capture_time++)
8485+ {
8486+ // a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to
8487+ // enable "IQ alibration Mode II"
8488+ reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE);
8489+ reg_mode_ctrl &= ~MASK_IQCAL_MODE;
8490+ reg_mode_ctrl |= (MASK_CALIB_START|0x02);
8491+ reg_mode_ctrl |= (MASK_CALIB_START|0x02|2<<2);
8492+ hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
8493+ PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
8494+ pa_stall_execution(US);
8495+
8496+ // b.
8497+ hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
8498+ PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val));
8499+ pa_stall_execution(US);
8500+
8501+ iqcal_tone_i0 = _s13_to_s32(val & 0x00001FFF);
8502+ iqcal_tone_q0 = _s13_to_s32((val & 0x03FFE000) >> 13);
8503+ PHY_DEBUG(("[CAL] ** iqcal_tone_i0=%d, iqcal_tone_q0=%d\n",
8504+ iqcal_tone_i0, iqcal_tone_q0));
8505+
8506+ sqsum = iqcal_tone_i0*iqcal_tone_i0 +
8507+ iqcal_tone_q0*iqcal_tone_q0;
8508+ iq_mag_0_tx = (s32) _sqrt(sqsum);
8509+ PHY_DEBUG(("[CAL] ** iq_mag_0_tx=%d\n", iq_mag_0_tx));
8510+
8511+ // c. Set "calib_start" to 0x0
8512+ reg_mode_ctrl &= ~MASK_CALIB_START;
8513+ hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
8514+ PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
8515+ pa_stall_execution(US);
8516+
8517+ // d. Set iqcal_mode[1:0] to 0x3 and set "calib_start" to 0x1 to
8518+ // enable "IQ alibration Mode II"
8519+ //hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val);
8520+ hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
8521+ reg_mode_ctrl &= ~MASK_IQCAL_MODE;
8522+ reg_mode_ctrl |= (MASK_CALIB_START|0x03);
8523+ hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
8524+ PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
8525+ pa_stall_execution(US);
8526+
8527+ // e.
8528+ hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
8529+ PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val));
8530+ pa_stall_execution(US);
8531+
8532+ iqcal_tone_i = _s13_to_s32(val & 0x00001FFF);
8533+ iqcal_tone_q = _s13_to_s32((val & 0x03FFE000) >> 13);
8534+ PHY_DEBUG(("[CAL] ** iqcal_tone_i = %d, iqcal_tone_q = %d\n",
8535+ iqcal_tone_i, iqcal_tone_q));
8536+ if( capture_time == 0)
8537+ {
8538+ continue;
8539+ }
8540+ else
8541+ {
8542+ iqcal_tone_i_avg=( iqcal_tone_i_avg*(capture_time-1) +iqcal_tone_i)/capture_time;
8543+ iqcal_tone_q_avg=( iqcal_tone_q_avg*(capture_time-1) +iqcal_tone_q)/capture_time;
8544+ }
8545+ }
8546+
8547+ iqcal_tone_i = iqcal_tone_i_avg;
8548+ iqcal_tone_q = iqcal_tone_q_avg;
8549+
8550+
8551+ rot_i_b = (iqcal_tone_i * iqcal_tone_i0 +
8552+ iqcal_tone_q * iqcal_tone_q0) / 1024;
8553+ rot_q_b = (iqcal_tone_i * iqcal_tone_q0 * (-1) +
8554+ iqcal_tone_q * iqcal_tone_i0) / 1024;
8555+ PHY_DEBUG(("[CAL] ** rot_i_b = %d, rot_q_b = %d\n",
8556+ rot_i_b, rot_q_b));
8557+
8558+ // f.
8559+ divisor = ((iq_mag_0_tx * iq_mag_0_tx * 2)/1024 - rot_i_b) * 2;
8560+
8561+ if (divisor == 0)
8562+ {
8563+ PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> ERROR *******\n"));
8564+ PHY_DEBUG(("[CAL] ** divisor=0 to calculate EPS and THETA !!\n"));
8565+ PHY_DEBUG(("[CAL] ******************************************\n"));
8566+ break;
8567+ }
8568+
8569+ a_2 = (rot_i_b * 32768) / divisor;
8570+ b_2 = (rot_q_b * (-32768)) / divisor;
8571+ PHY_DEBUG(("[CAL] ***** EPSILON/2 = %d\n", a_2));
8572+ PHY_DEBUG(("[CAL] ***** THETA/2 = %d\n", b_2));
8573+
8574+ phw_data->iq_rsdl_gain_tx_d2 = a_2;
8575+ phw_data->iq_rsdl_phase_tx_d2 = b_2;
8576+
8577+ //if ((abs(a_2) < 150) && (abs(b_2) < 100))
8578+ //if ((abs(a_2) < 200) && (abs(b_2) < 200))
8579+ if ((abs(a_2) < a_2_threshold) && (abs(b_2) < b_2_threshold))
8580+ {
8581+ verify_count++;
8582+
8583+ PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *************\n"));
8584+ PHY_DEBUG(("[CAL] ** VERIFY OK # %d !!\n", verify_count));
8585+ PHY_DEBUG(("[CAL] ******************************************\n"));
8586+
8587+ if (verify_count > 2)
8588+ {
8589+ PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n"));
8590+ PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION (EPS,THETA) OK !!\n"));
8591+ PHY_DEBUG(("[CAL] **************************************\n"));
8592+ return 0;
8593+ }
8594+
8595+ continue;
8596+ }
8597+ else
8598+ {
8599+ verify_count = 0;
8600+ }
8601+
8602+ _sin_cos(b_2, &sin_b, &cos_b);
8603+ _sin_cos(b_2*2, &sin_2b, &cos_2b);
8604+ PHY_DEBUG(("[CAL] ** sin(b/2)=%d, cos(b/2)=%d\n", sin_b, cos_b));
8605+ PHY_DEBUG(("[CAL] ** sin(b)=%d, cos(b)=%d\n", sin_2b, cos_2b));
8606+
8607+ if (cos_2b == 0)
8608+ {
8609+ PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> ERROR *******\n"));
8610+ PHY_DEBUG(("[CAL] ** cos(b)=0 !!\n"));
8611+ PHY_DEBUG(("[CAL] ******************************************\n"));
8612+ break;
8613+ }
8614+
8615+ // 1280 * 32768 = 41943040
8616+ temp1 = (41943040/cos_2b)*cos_b;
8617+
8618+ //temp2 = (41943040/cos_2b)*sin_b*(-1);
8619+ if (phw_data->revision == 0x2002) // 1st-cut
8620+ {
8621+ temp2 = (41943040/cos_2b)*sin_b*(-1);
8622+ }
8623+ else // 2nd-cut
8624+ {
8625+ temp2 = (41943040*4/cos_2b)*sin_b*(-1);
8626+ }
8627+
8628+ tx_cal_flt_b[0] = _floor(temp1/(32768+a_2));
8629+ tx_cal_flt_b[1] = _floor(temp2/(32768+a_2));
8630+ tx_cal_flt_b[2] = _floor(temp2/(32768-a_2));
8631+ tx_cal_flt_b[3] = _floor(temp1/(32768-a_2));
8632+ PHY_DEBUG(("[CAL] ** tx_cal_flt_b[0] = %d\n", tx_cal_flt_b[0]));
8633+ PHY_DEBUG(("[CAL] tx_cal_flt_b[1] = %d\n", tx_cal_flt_b[1]));
8634+ PHY_DEBUG(("[CAL] tx_cal_flt_b[2] = %d\n", tx_cal_flt_b[2]));
8635+ PHY_DEBUG(("[CAL] tx_cal_flt_b[3] = %d\n", tx_cal_flt_b[3]));
8636+
8637+ tx_cal[2] = tx_cal_flt_b[2];
8638+ tx_cal[2] = tx_cal[2] +3;
8639+ tx_cal[1] = tx_cal[2];
8640+ tx_cal[3] = tx_cal_flt_b[3] - 128;
8641+ tx_cal[0] = -tx_cal[3]+1;
8642+
8643+ PHY_DEBUG(("[CAL] tx_cal[0] = %d\n", tx_cal[0]));
8644+ PHY_DEBUG(("[CAL] tx_cal[1] = %d\n", tx_cal[1]));
8645+ PHY_DEBUG(("[CAL] tx_cal[2] = %d\n", tx_cal[2]));
8646+ PHY_DEBUG(("[CAL] tx_cal[3] = %d\n", tx_cal[3]));
8647+
8648+ //if ((tx_cal[0] == 0) && (tx_cal[1] == 0) &&
8649+ // (tx_cal[2] == 0) && (tx_cal[3] == 0))
8650+ //{
8651+ // PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *************\n"));
8652+ // PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION COMPLETE !!\n"));
8653+ // PHY_DEBUG(("[CAL] ******************************************\n"));
8654+ // return 0;
8655+ //}
8656+
8657+ // g.
8658+ if (phw_data->revision == 0x2002) // 1st-cut
8659+ {
8660+ hw_get_dxx_reg(phw_data, 0x54, &val);
8661+ PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val));
8662+ tx_cal_reg[0] = _s4_to_s32((val & 0xF0000000) >> 28);
8663+ tx_cal_reg[1] = _s4_to_s32((val & 0x0F000000) >> 24);
8664+ tx_cal_reg[2] = _s4_to_s32((val & 0x00F00000) >> 20);
8665+ tx_cal_reg[3] = _s4_to_s32((val & 0x000F0000) >> 16);
8666+ }
8667+ else // 2nd-cut
8668+ {
8669+ hw_get_dxx_reg(phw_data, 0x3C, &val);
8670+ PHY_DEBUG(("[CAL] ** 0x3C = 0x%08X\n", val));
8671+ tx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27);
8672+ tx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21);
8673+ tx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15);
8674+ tx_cal_reg[3] = _s5_to_s32((val & 0x00007C00) >> 10);
8675+
8676+ }
8677+
8678+ PHY_DEBUG(("[CAL] ** tx_cal_reg[0] = %d\n", tx_cal_reg[0]));
8679+ PHY_DEBUG(("[CAL] tx_cal_reg[1] = %d\n", tx_cal_reg[1]));
8680+ PHY_DEBUG(("[CAL] tx_cal_reg[2] = %d\n", tx_cal_reg[2]));
8681+ PHY_DEBUG(("[CAL] tx_cal_reg[3] = %d\n", tx_cal_reg[3]));
8682+
8683+ if (phw_data->revision == 0x2002) // 1st-cut
8684+ {
8685+ if (((tx_cal_reg[0]==7) || (tx_cal_reg[0]==(-8))) &&
8686+ ((tx_cal_reg[3]==7) || (tx_cal_reg[3]==(-8))))
8687+ {
8688+ PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n"));
8689+ PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION SATUATION !!\n"));
8690+ PHY_DEBUG(("[CAL] **************************************\n"));
8691+ break;
8692+ }
8693+ }
8694+ else // 2nd-cut
8695+ {
8696+ if (((tx_cal_reg[0]==31) || (tx_cal_reg[0]==(-32))) &&
8697+ ((tx_cal_reg[3]==31) || (tx_cal_reg[3]==(-32))))
8698+ {
8699+ PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n"));
8700+ PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION SATUATION !!\n"));
8701+ PHY_DEBUG(("[CAL] **************************************\n"));
8702+ break;
8703+ }
8704+ }
8705+
8706+ tx_cal[0] = tx_cal[0] + tx_cal_reg[0];
8707+ tx_cal[1] = tx_cal[1] + tx_cal_reg[1];
8708+ tx_cal[2] = tx_cal[2] + tx_cal_reg[2];
8709+ tx_cal[3] = tx_cal[3] + tx_cal_reg[3];
8710+ PHY_DEBUG(("[CAL] ** apply tx_cal[0] = %d\n", tx_cal[0]));
8711+ PHY_DEBUG(("[CAL] apply tx_cal[1] = %d\n", tx_cal[1]));
8712+ PHY_DEBUG(("[CAL] apply tx_cal[2] = %d\n", tx_cal[2]));
8713+ PHY_DEBUG(("[CAL] apply tx_cal[3] = %d\n", tx_cal[3]));
8714+
8715+ if (phw_data->revision == 0x2002) // 1st-cut
8716+ {
8717+ val &= 0x0000FFFF;
8718+ val |= ((_s32_to_s4(tx_cal[0]) << 28)|
8719+ (_s32_to_s4(tx_cal[1]) << 24)|
8720+ (_s32_to_s4(tx_cal[2]) << 20)|
8721+ (_s32_to_s4(tx_cal[3]) << 16));
8722+ hw_set_dxx_reg(phw_data, 0x54, val);
8723+ PHY_DEBUG(("[CAL] ** CALIB_DATA = 0x%08X\n", val));
8724+ return 0;
8725+ }
8726+ else // 2nd-cut
8727+ {
8728+ val &= 0x000003FF;
8729+ val |= ((_s32_to_s5(tx_cal[0]) << 27)|
8730+ (_s32_to_s6(tx_cal[1]) << 21)|
8731+ (_s32_to_s6(tx_cal[2]) << 15)|
8732+ (_s32_to_s5(tx_cal[3]) << 10));
8733+ hw_set_dxx_reg(phw_data, 0x3C, val);
8734+ PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION = 0x%08X\n", val));
8735+ return 0;
8736+ }
8737+
8738+ // i. Set "calib_start" to 0x0
8739+ reg_mode_ctrl &= ~MASK_CALIB_START;
8740+ hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
8741+ PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
8742+
8743+ loop--;
8744+ }
8745+
8746+ return 1;
8747+}
8748+
8749+void _tx_iq_calibration_winbond(hw_data_t *phw_data)
8750+{
8751+ u32 reg_agc_ctrl3;
8752+#ifdef _DEBUG
8753+ s32 tx_cal_reg[4];
8754+
8755+#endif
8756+ u32 reg_mode_ctrl;
8757+ u32 val;
8758+ u8 result;
8759+
8760+ PHY_DEBUG(("[CAL] -> [4]_tx_iq_calibration()\n"));
8761+
8762+ //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits
8763+ phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2);
8764+ //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit
8765+ phy_set_rf_data(phw_data, 11, (11<<24)|0x19BDD6); // 20060612.1.a 0x1905D6);
8766+ //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized
8767+ phy_set_rf_data(phw_data, 5, (5<<24)|0x24C60A); //0x24C60A (high temperature)
8768+ //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized
8769+ phy_set_rf_data(phw_data, 6, (6<<24)|0x34880C); // 20060612.1.a 0x06890C);
8770+ //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode
8771+ phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
8772+ //; [BB-chip]: Calibration (6f).Send test pattern
8773+ //; [BB-chip]: Calibration (6g). Search RXGCL optimal value
8774+ //; [BB-chip]: Calibration (6h). Caculate TX-path IQ imbalance and setting TX path IQ compensation table
8775+ //phy_set_rf_data(phw_data, 3, (3<<24)|0x025586);
8776+
8777+ OS_SLEEP(30000); // 20060612.1.a 30ms delay. Add the follow 2 lines
8778+ //To adjust TXVGA to fit iq_mag_0 range from 1250 ~ 1750
8779+ adjust_TXVGA_for_iq_mag( phw_data );
8780+
8781+ // a. Disable AGC
8782+ hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3);
8783+ reg_agc_ctrl3 &= ~BIT(2);
8784+ reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
8785+ hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
8786+
8787+ hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val);
8788+ val |= MASK_AGC_FIX_GAIN;
8789+ hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
8790+
8791+ result = _tx_iq_calibration_loop_winbond(phw_data, 150, 100);
8792+
8793+ if (result > 0)
8794+ {
8795+ if (phw_data->revision == 0x2002) // 1st-cut
8796+ {
8797+ hw_get_dxx_reg(phw_data, 0x54, &val);
8798+ val &= 0x0000FFFF;
8799+ hw_set_dxx_reg(phw_data, 0x54, val);
8800+ }
8801+ else // 2nd-cut
8802+ {
8803+ hw_get_dxx_reg(phw_data, 0x3C, &val);
8804+ val &= 0x000003FF;
8805+ hw_set_dxx_reg(phw_data, 0x3C, val);
8806+ }
8807+
8808+ result = _tx_iq_calibration_loop_winbond(phw_data, 300, 200);
8809+
8810+ if (result > 0)
8811+ {
8812+ if (phw_data->revision == 0x2002) // 1st-cut
8813+ {
8814+ hw_get_dxx_reg(phw_data, 0x54, &val);
8815+ val &= 0x0000FFFF;
8816+ hw_set_dxx_reg(phw_data, 0x54, val);
8817+ }
8818+ else // 2nd-cut
8819+ {
8820+ hw_get_dxx_reg(phw_data, 0x3C, &val);
8821+ val &= 0x000003FF;
8822+ hw_set_dxx_reg(phw_data, 0x3C, val);
8823+ }
8824+
8825+ result = _tx_iq_calibration_loop_winbond(phw_data, 500, 400);
8826+ if (result > 0)
8827+ {
8828+ if (phw_data->revision == 0x2002) // 1st-cut
8829+ {
8830+ hw_get_dxx_reg(phw_data, 0x54, &val);
8831+ val &= 0x0000FFFF;
8832+ hw_set_dxx_reg(phw_data, 0x54, val);
8833+ }
8834+ else // 2nd-cut
8835+ {
8836+ hw_get_dxx_reg(phw_data, 0x3C, &val);
8837+ val &= 0x000003FF;
8838+ hw_set_dxx_reg(phw_data, 0x3C, val);
8839+ }
8840+
8841+
8842+ result = _tx_iq_calibration_loop_winbond(phw_data, 700, 500);
8843+
8844+ if (result > 0)
8845+ {
8846+ PHY_DEBUG(("[CAL] ** <_tx_iq_calibration> **************\n"));
8847+ PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION FAILURE !!\n"));
8848+ PHY_DEBUG(("[CAL] **************************************\n"));
8849+
8850+ if (phw_data->revision == 0x2002) // 1st-cut
8851+ {
8852+ hw_get_dxx_reg(phw_data, 0x54, &val);
8853+ val &= 0x0000FFFF;
8854+ hw_set_dxx_reg(phw_data, 0x54, val);
8855+ }
8856+ else // 2nd-cut
8857+ {
8858+ hw_get_dxx_reg(phw_data, 0x3C, &val);
8859+ val &= 0x000003FF;
8860+ hw_set_dxx_reg(phw_data, 0x3C, val);
8861+ }
8862+ }
8863+ }
8864+ }
8865+ }
8866+
8867+ // i. Set "calib_start" to 0x0
8868+ hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
8869+ reg_mode_ctrl &= ~MASK_CALIB_START;
8870+ hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
8871+ PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
8872+
8873+ // g. Enable AGC
8874+ //hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val);
8875+ reg_agc_ctrl3 |= BIT(2);
8876+ reg_agc_ctrl3 &= ~(MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
8877+ hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
8878+
8879+#ifdef _DEBUG
8880+ if (phw_data->revision == 0x2002) // 1st-cut
8881+ {
8882+ hw_get_dxx_reg(phw_data, 0x54, &val);
8883+ PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val));
8884+ tx_cal_reg[0] = _s4_to_s32((val & 0xF0000000) >> 28);
8885+ tx_cal_reg[1] = _s4_to_s32((val & 0x0F000000) >> 24);
8886+ tx_cal_reg[2] = _s4_to_s32((val & 0x00F00000) >> 20);
8887+ tx_cal_reg[3] = _s4_to_s32((val & 0x000F0000) >> 16);
8888+ }
8889+ else // 2nd-cut
8890+ {
8891+ hw_get_dxx_reg(phw_data, 0x3C, &val);
8892+ PHY_DEBUG(("[CAL] ** 0x3C = 0x%08X\n", val));
8893+ tx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27);
8894+ tx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21);
8895+ tx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15);
8896+ tx_cal_reg[3] = _s5_to_s32((val & 0x00007C00) >> 10);
8897+
8898+ }
8899+
8900+ PHY_DEBUG(("[CAL] ** tx_cal_reg[0] = %d\n", tx_cal_reg[0]));
8901+ PHY_DEBUG(("[CAL] tx_cal_reg[1] = %d\n", tx_cal_reg[1]));
8902+ PHY_DEBUG(("[CAL] tx_cal_reg[2] = %d\n", tx_cal_reg[2]));
8903+ PHY_DEBUG(("[CAL] tx_cal_reg[3] = %d\n", tx_cal_reg[3]));
8904+#endif
8905+
8906+
8907+ // for test - BEN
8908+ // RF Control Override
8909+}
8910+
8911+/////////////////////////////////////////////////////////////////////////////////////////
8912+u8 _rx_iq_calibration_loop_winbond(hw_data_t *phw_data, u16 factor, u32 frequency)
8913+{
8914+ u32 reg_mode_ctrl;
8915+ s32 iqcal_tone_i;
8916+ s32 iqcal_tone_q;
8917+ s32 iqcal_image_i;
8918+ s32 iqcal_image_q;
8919+ s32 rot_tone_i_b;
8920+ s32 rot_tone_q_b;
8921+ s32 rot_image_i_b;
8922+ s32 rot_image_q_b;
8923+ s32 rx_cal_flt_b[4];
8924+ s32 rx_cal[4];
8925+ s32 rx_cal_reg[4];
8926+ s32 a_2, b_2;
8927+ s32 sin_b, sin_2b;
8928+ s32 cos_b, cos_2b;
8929+ s32 temp1, temp2;
8930+ u32 val;
8931+ u16 loop;
8932+
8933+ u32 pwr_tone;
8934+ u32 pwr_image;
8935+ u8 verify_count;
8936+
8937+ s32 iqcal_tone_i_avg,iqcal_tone_q_avg;
8938+ s32 iqcal_image_i_avg,iqcal_image_q_avg;
8939+ u16 capture_time;
8940+
8941+ PHY_DEBUG(("[CAL] -> [5]_rx_iq_calibration_loop()\n"));
8942+ PHY_DEBUG(("[CAL] ** factor = %d\n", factor));
8943+
8944+
8945+// RF Control Override
8946+ hw_get_cxx_reg(phw_data, 0x80, &val);
8947+ val |= BIT(19);
8948+ hw_set_cxx_reg(phw_data, 0x80, val);
8949+
8950+// RF_Ctrl
8951+ hw_get_cxx_reg(phw_data, 0xE4, &val);
8952+ val |= BIT(0);
8953+ hw_set_cxx_reg(phw_data, 0xE4, val);
8954+ PHY_DEBUG(("[CAL] ** RF_CTRL(0xE4) = 0x%08X", val));
8955+
8956+ hw_set_dxx_reg(phw_data, 0x58, 0x44444444); // IQ_Alpha
8957+
8958+ // b.
8959+
8960+ hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
8961+ PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
8962+
8963+ verify_count = 0;
8964+
8965+ //for (loop = 0; loop < 1; loop++)
8966+ //for (loop = 0; loop < LOOP_TIMES; loop++)
8967+ loop = LOOP_TIMES;
8968+ while (loop > 0)
8969+ {
8970+ PHY_DEBUG(("[CAL] [%d.] <_rx_iq_calibration_loop>\n", (LOOP_TIMES-loop+1)));
8971+ iqcal_tone_i_avg=0;
8972+ iqcal_tone_q_avg=0;
8973+ iqcal_image_i_avg=0;
8974+ iqcal_image_q_avg=0;
8975+ capture_time=0;
8976+
8977+ for(capture_time=0; capture_time<10; capture_time++)
8978+ {
8979+ // i. Set "calib_start" to 0x0
8980+ reg_mode_ctrl &= ~MASK_CALIB_START;
8981+ if( !hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl) )//20060718.1 modify
8982+ return 0;
8983+ PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
8984+ pa_stall_execution(US);
8985+
8986+ reg_mode_ctrl &= ~MASK_IQCAL_MODE;
8987+ reg_mode_ctrl |= (MASK_CALIB_START|0x1);
8988+ hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
8989+ PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
8990+ pa_stall_execution(US); //Should be read out after 450us
8991+
8992+ // c.
8993+ hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
8994+ PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val));
8995+
8996+ iqcal_tone_i = _s13_to_s32(val & 0x00001FFF);
8997+ iqcal_tone_q = _s13_to_s32((val & 0x03FFE000) >> 13);
8998+ PHY_DEBUG(("[CAL] ** iqcal_tone_i = %d, iqcal_tone_q = %d\n",
8999+ iqcal_tone_i, iqcal_tone_q));
9000+
9001+ hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
9002+ PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val));
9003+
9004+ iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
9005+ iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
9006+ PHY_DEBUG(("[CAL] ** iqcal_image_i = %d, iqcal_image_q = %d\n",
9007+ iqcal_image_i, iqcal_image_q));
9008+ if( capture_time == 0)
9009+ {
9010+ continue;
9011+ }
9012+ else
9013+ {
9014+ iqcal_image_i_avg=( iqcal_image_i_avg*(capture_time-1) +iqcal_image_i)/capture_time;
9015+ iqcal_image_q_avg=( iqcal_image_q_avg*(capture_time-1) +iqcal_image_q)/capture_time;
9016+ iqcal_tone_i_avg=( iqcal_tone_i_avg*(capture_time-1) +iqcal_tone_i)/capture_time;
9017+ iqcal_tone_q_avg=( iqcal_tone_q_avg*(capture_time-1) +iqcal_tone_q)/capture_time;
9018+ }
9019+ }
9020+
9021+
9022+ iqcal_image_i = iqcal_image_i_avg;
9023+ iqcal_image_q = iqcal_image_q_avg;
9024+ iqcal_tone_i = iqcal_tone_i_avg;
9025+ iqcal_tone_q = iqcal_tone_q_avg;
9026+
9027+ // d.
9028+ rot_tone_i_b = (iqcal_tone_i * iqcal_tone_i +
9029+ iqcal_tone_q * iqcal_tone_q) / 1024;
9030+ rot_tone_q_b = (iqcal_tone_i * iqcal_tone_q * (-1) +
9031+ iqcal_tone_q * iqcal_tone_i) / 1024;
9032+ rot_image_i_b = (iqcal_image_i * iqcal_tone_i -
9033+ iqcal_image_q * iqcal_tone_q) / 1024;
9034+ rot_image_q_b = (iqcal_image_i * iqcal_tone_q +
9035+ iqcal_image_q * iqcal_tone_i) / 1024;
9036+
9037+ PHY_DEBUG(("[CAL] ** rot_tone_i_b = %d\n", rot_tone_i_b));
9038+ PHY_DEBUG(("[CAL] ** rot_tone_q_b = %d\n", rot_tone_q_b));
9039+ PHY_DEBUG(("[CAL] ** rot_image_i_b = %d\n", rot_image_i_b));
9040+ PHY_DEBUG(("[CAL] ** rot_image_q_b = %d\n", rot_image_q_b));
9041+
9042+ // f.
9043+ if (rot_tone_i_b == 0)
9044+ {
9045+ PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> ERROR *******\n"));
9046+ PHY_DEBUG(("[CAL] ** rot_tone_i_b=0 to calculate EPS and THETA !!\n"));
9047+ PHY_DEBUG(("[CAL] ******************************************\n"));
9048+ break;
9049+ }
9050+
9051+ a_2 = (rot_image_i_b * 32768) / rot_tone_i_b -
9052+ phw_data->iq_rsdl_gain_tx_d2;
9053+ b_2 = (rot_image_q_b * 32768) / rot_tone_i_b -
9054+ phw_data->iq_rsdl_phase_tx_d2;
9055+
9056+ PHY_DEBUG(("[CAL] ** iq_rsdl_gain_tx_d2 = %d\n", phw_data->iq_rsdl_gain_tx_d2));
9057+ PHY_DEBUG(("[CAL] ** iq_rsdl_phase_tx_d2= %d\n", phw_data->iq_rsdl_phase_tx_d2));
9058+ PHY_DEBUG(("[CAL] ***** EPSILON/2 = %d\n", a_2));
9059+ PHY_DEBUG(("[CAL] ***** THETA/2 = %d\n", b_2));
9060+
9061+ _sin_cos(b_2, &sin_b, &cos_b);
9062+ _sin_cos(b_2*2, &sin_2b, &cos_2b);
9063+ PHY_DEBUG(("[CAL] ** sin(b/2)=%d, cos(b/2)=%d\n", sin_b, cos_b));
9064+ PHY_DEBUG(("[CAL] ** sin(b)=%d, cos(b)=%d\n", sin_2b, cos_2b));
9065+
9066+ if (cos_2b == 0)
9067+ {
9068+ PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> ERROR *******\n"));
9069+ PHY_DEBUG(("[CAL] ** cos(b)=0 !!\n"));
9070+ PHY_DEBUG(("[CAL] ******************************************\n"));
9071+ break;
9072+ }
9073+
9074+ // 1280 * 32768 = 41943040
9075+ temp1 = (41943040/cos_2b)*cos_b;
9076+
9077+ //temp2 = (41943040/cos_2b)*sin_b*(-1);
9078+ if (phw_data->revision == 0x2002) // 1st-cut
9079+ {
9080+ temp2 = (41943040/cos_2b)*sin_b*(-1);
9081+ }
9082+ else // 2nd-cut
9083+ {
9084+ temp2 = (41943040*4/cos_2b)*sin_b*(-1);
9085+ }
9086+
9087+ rx_cal_flt_b[0] = _floor(temp1/(32768+a_2));
9088+ rx_cal_flt_b[1] = _floor(temp2/(32768-a_2));
9089+ rx_cal_flt_b[2] = _floor(temp2/(32768+a_2));
9090+ rx_cal_flt_b[3] = _floor(temp1/(32768-a_2));
9091+
9092+ PHY_DEBUG(("[CAL] ** rx_cal_flt_b[0] = %d\n", rx_cal_flt_b[0]));
9093+ PHY_DEBUG(("[CAL] rx_cal_flt_b[1] = %d\n", rx_cal_flt_b[1]));
9094+ PHY_DEBUG(("[CAL] rx_cal_flt_b[2] = %d\n", rx_cal_flt_b[2]));
9095+ PHY_DEBUG(("[CAL] rx_cal_flt_b[3] = %d\n", rx_cal_flt_b[3]));
9096+
9097+ rx_cal[0] = rx_cal_flt_b[0] - 128;
9098+ rx_cal[1] = rx_cal_flt_b[1];
9099+ rx_cal[2] = rx_cal_flt_b[2];
9100+ rx_cal[3] = rx_cal_flt_b[3] - 128;
9101+ PHY_DEBUG(("[CAL] ** rx_cal[0] = %d\n", rx_cal[0]));
9102+ PHY_DEBUG(("[CAL] rx_cal[1] = %d\n", rx_cal[1]));
9103+ PHY_DEBUG(("[CAL] rx_cal[2] = %d\n", rx_cal[2]));
9104+ PHY_DEBUG(("[CAL] rx_cal[3] = %d\n", rx_cal[3]));
9105+
9106+ // e.
9107+ pwr_tone = (iqcal_tone_i*iqcal_tone_i + iqcal_tone_q*iqcal_tone_q);
9108+ pwr_image = (iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q)*factor;
9109+
9110+ PHY_DEBUG(("[CAL] ** pwr_tone = %d\n", pwr_tone));
9111+ PHY_DEBUG(("[CAL] ** pwr_image = %d\n", pwr_image));
9112+
9113+ if (pwr_tone > pwr_image)
9114+ {
9115+ verify_count++;
9116+
9117+ PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *************\n"));
9118+ PHY_DEBUG(("[CAL] ** VERIFY OK # %d !!\n", verify_count));
9119+ PHY_DEBUG(("[CAL] ******************************************\n"));
9120+
9121+ if (verify_count > 2)
9122+ {
9123+ PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n"));
9124+ PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION OK !!\n"));
9125+ PHY_DEBUG(("[CAL] **************************************\n"));
9126+ return 0;
9127+ }
9128+
9129+ continue;
9130+ }
9131+ // g.
9132+ hw_get_dxx_reg(phw_data, 0x54, &val);
9133+ PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val));
9134+
9135+ if (phw_data->revision == 0x2002) // 1st-cut
9136+ {
9137+ rx_cal_reg[0] = _s4_to_s32((val & 0x0000F000) >> 12);
9138+ rx_cal_reg[1] = _s4_to_s32((val & 0x00000F00) >> 8);
9139+ rx_cal_reg[2] = _s4_to_s32((val & 0x000000F0) >> 4);
9140+ rx_cal_reg[3] = _s4_to_s32((val & 0x0000000F));
9141+ }
9142+ else // 2nd-cut
9143+ {
9144+ rx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27);
9145+ rx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21);
9146+ rx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15);
9147+ rx_cal_reg[3] = _s5_to_s32((val & 0x00007C00) >> 10);
9148+ }
9149+
9150+ PHY_DEBUG(("[CAL] ** rx_cal_reg[0] = %d\n", rx_cal_reg[0]));
9151+ PHY_DEBUG(("[CAL] rx_cal_reg[1] = %d\n", rx_cal_reg[1]));
9152+ PHY_DEBUG(("[CAL] rx_cal_reg[2] = %d\n", rx_cal_reg[2]));
9153+ PHY_DEBUG(("[CAL] rx_cal_reg[3] = %d\n", rx_cal_reg[3]));
9154+
9155+ if (phw_data->revision == 0x2002) // 1st-cut
9156+ {
9157+ if (((rx_cal_reg[0]==7) || (rx_cal_reg[0]==(-8))) &&
9158+ ((rx_cal_reg[3]==7) || (rx_cal_reg[3]==(-8))))
9159+ {
9160+ PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n"));
9161+ PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION SATUATION !!\n"));
9162+ PHY_DEBUG(("[CAL] **************************************\n"));
9163+ break;
9164+ }
9165+ }
9166+ else // 2nd-cut
9167+ {
9168+ if (((rx_cal_reg[0]==31) || (rx_cal_reg[0]==(-32))) &&
9169+ ((rx_cal_reg[3]==31) || (rx_cal_reg[3]==(-32))))
9170+ {
9171+ PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n"));
9172+ PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION SATUATION !!\n"));
9173+ PHY_DEBUG(("[CAL] **************************************\n"));
9174+ break;
9175+ }
9176+ }
9177+
9178+ rx_cal[0] = rx_cal[0] + rx_cal_reg[0];
9179+ rx_cal[1] = rx_cal[1] + rx_cal_reg[1];
9180+ rx_cal[2] = rx_cal[2] + rx_cal_reg[2];
9181+ rx_cal[3] = rx_cal[3] + rx_cal_reg[3];
9182+ PHY_DEBUG(("[CAL] ** apply rx_cal[0] = %d\n", rx_cal[0]));
9183+ PHY_DEBUG(("[CAL] apply rx_cal[1] = %d\n", rx_cal[1]));
9184+ PHY_DEBUG(("[CAL] apply rx_cal[2] = %d\n", rx_cal[2]));
9185+ PHY_DEBUG(("[CAL] apply rx_cal[3] = %d\n", rx_cal[3]));
9186+
9187+ hw_get_dxx_reg(phw_data, 0x54, &val);
9188+ if (phw_data->revision == 0x2002) // 1st-cut
9189+ {
9190+ val &= 0x0000FFFF;
9191+ val |= ((_s32_to_s4(rx_cal[0]) << 12)|
9192+ (_s32_to_s4(rx_cal[1]) << 8)|
9193+ (_s32_to_s4(rx_cal[2]) << 4)|
9194+ (_s32_to_s4(rx_cal[3])));
9195+ hw_set_dxx_reg(phw_data, 0x54, val);
9196+ }
9197+ else // 2nd-cut
9198+ {
9199+ val &= 0x000003FF;
9200+ val |= ((_s32_to_s5(rx_cal[0]) << 27)|
9201+ (_s32_to_s6(rx_cal[1]) << 21)|
9202+ (_s32_to_s6(rx_cal[2]) << 15)|
9203+ (_s32_to_s5(rx_cal[3]) << 10));
9204+ hw_set_dxx_reg(phw_data, 0x54, val);
9205+
9206+ if( loop == 3 )
9207+ return 0;
9208+ }
9209+ PHY_DEBUG(("[CAL] ** CALIB_DATA = 0x%08X\n", val));
9210+
9211+ loop--;
9212+ }
9213+
9214+ return 1;
9215+}
9216+
9217+//////////////////////////////////////////////////////////
9218+
9219+//////////////////////////////////////////////////////////////////////////
9220+void _rx_iq_calibration_winbond(hw_data_t *phw_data, u32 frequency)
9221+{
9222+// figo 20050523 marked thsi flag for can't compile for relesase
9223+#ifdef _DEBUG
9224+ s32 rx_cal_reg[4];
9225+ u32 val;
9226+#endif
9227+
9228+ u8 result;
9229+
9230+ PHY_DEBUG(("[CAL] -> [5]_rx_iq_calibration()\n"));
9231+// a. Set RFIC to "RX calibration mode"
9232+ //; ----- Calibration (7). RX path IQ imbalance calibration loop
9233+ // 0x01 0xFFBFC2 ; 3FEFF ; Calibration (7a). enable RX IQ calibration loop circuits
9234+ phy_set_rf_data(phw_data, 1, (1<<24)|0xEFBFC2);
9235+ // 0x0B 0x1A01D6 ; 06817 ; Calibration (7b). enable RX I/Q cal loop SW1 circuit
9236+ phy_set_rf_data(phw_data, 11, (11<<24)|0x1A05D6);
9237+ //0x05 0x24848A ; 09212 ; Calibration (7c). setting TX-VGA gain (TXGCH) to 2 --> to be optimized
9238+ phy_set_rf_data(phw_data, 5, (5<<24)| phw_data->txvga_setting_for_cal);
9239+ //0x06 0x06840C ; 01A10 ; Calibration (7d). RXGCH=00; RXGCL=010 000 (RXVGA) --> to be optimized
9240+ phy_set_rf_data(phw_data, 6, (6<<24)|0x06834C);
9241+ //0x00 0xFFF1C0 ; 3F7C7 ; Calibration (7e). turn on IQ imbalance/Test mode
9242+ phy_set_rf_data(phw_data, 0, (0<<24)|0xFFF1C0);
9243+
9244+ // ; [BB-chip]: Calibration (7f). Send test pattern
9245+ // ; [BB-chip]: Calibration (7g). Search RXGCL optimal value
9246+ // ; [BB-chip]: Calibration (7h). Caculate RX-path IQ imbalance and setting RX path IQ compensation table
9247+
9248+ result = _rx_iq_calibration_loop_winbond(phw_data, 12589, frequency);
9249+
9250+ if (result > 0)
9251+ {
9252+ _reset_rx_cal(phw_data);
9253+ result = _rx_iq_calibration_loop_winbond(phw_data, 7943, frequency);
9254+
9255+ if (result > 0)
9256+ {
9257+ _reset_rx_cal(phw_data);
9258+ result = _rx_iq_calibration_loop_winbond(phw_data, 5011, frequency);
9259+
9260+ if (result > 0)
9261+ {
9262+ PHY_DEBUG(("[CAL] ** <_rx_iq_calibration> **************\n"));
9263+ PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION FAILURE !!\n"));
9264+ PHY_DEBUG(("[CAL] **************************************\n"));
9265+ _reset_rx_cal(phw_data);
9266+ }
9267+ }
9268+ }
9269+
9270+#ifdef _DEBUG
9271+ hw_get_dxx_reg(phw_data, 0x54, &val);
9272+ PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val));
9273+
9274+ if (phw_data->revision == 0x2002) // 1st-cut
9275+ {
9276+ rx_cal_reg[0] = _s4_to_s32((val & 0x0000F000) >> 12);
9277+ rx_cal_reg[1] = _s4_to_s32((val & 0x00000F00) >> 8);
9278+ rx_cal_reg[2] = _s4_to_s32((val & 0x000000F0) >> 4);
9279+ rx_cal_reg[3] = _s4_to_s32((val & 0x0000000F));
9280+ }
9281+ else // 2nd-cut
9282+ {
9283+ rx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27);
9284+ rx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21);
9285+ rx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15);
9286+ rx_cal_reg[3] = _s5_to_s32((val & 0x00007C00) >> 10);
9287+ }
9288+
9289+ PHY_DEBUG(("[CAL] ** rx_cal_reg[0] = %d\n", rx_cal_reg[0]));
9290+ PHY_DEBUG(("[CAL] rx_cal_reg[1] = %d\n", rx_cal_reg[1]));
9291+ PHY_DEBUG(("[CAL] rx_cal_reg[2] = %d\n", rx_cal_reg[2]));
9292+ PHY_DEBUG(("[CAL] rx_cal_reg[3] = %d\n", rx_cal_reg[3]));
9293+#endif
9294+
9295+}
9296+
9297+////////////////////////////////////////////////////////////////////////
9298+void phy_calibration_winbond(hw_data_t *phw_data, u32 frequency)
9299+{
9300+ u32 reg_mode_ctrl;
9301+ u32 iq_alpha;
9302+
9303+ PHY_DEBUG(("[CAL] -> phy_calibration_winbond()\n"));
9304+
9305+ // 20040701 1.1.25.1000 kevin
9306+ hw_get_cxx_reg(phw_data, 0x80, &mac_ctrl);
9307+ hw_get_cxx_reg(phw_data, 0xE4, &rf_ctrl);
9308+ hw_get_dxx_reg(phw_data, 0x58, &iq_alpha);
9309+
9310+
9311+
9312+ _rxadc_dc_offset_cancellation_winbond(phw_data, frequency);
9313+ //_txidac_dc_offset_cancellation_winbond(phw_data);
9314+ //_txqdac_dc_offset_cacellation_winbond(phw_data);
9315+
9316+ _tx_iq_calibration_winbond(phw_data);
9317+ _rx_iq_calibration_winbond(phw_data, frequency);
9318+
9319+ //------------------------------------------------------------------------
9320+ hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
9321+ reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE|MASK_CALIB_START); // set when finish
9322+ hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
9323+ PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
9324+
9325+ // i. Set RFIC to "Normal mode"
9326+ hw_set_cxx_reg(phw_data, 0x80, mac_ctrl);
9327+ hw_set_cxx_reg(phw_data, 0xE4, rf_ctrl);
9328+ hw_set_dxx_reg(phw_data, 0x58, iq_alpha);
9329+
9330+
9331+ //------------------------------------------------------------------------
9332+ phy_init_rf(phw_data);
9333+
9334+}
9335+
9336+//===========================
9337+void phy_set_rf_data( phw_data_t pHwData, u32 index, u32 value )
9338+{
9339+ u32 ltmp=0;
9340+
9341+ switch( pHwData->phy_type )
9342+ {
9343+ case RF_MAXIM_2825:
9344+ case RF_MAXIM_V1: // 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331)
9345+ ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 );
9346+ break;
9347+
9348+ case RF_MAXIM_2827:
9349+ ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 );
9350+ break;
9351+
9352+ case RF_MAXIM_2828:
9353+ ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 );
9354+ break;
9355+
9356+ case RF_MAXIM_2829:
9357+ ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 );
9358+ break;
9359+
9360+ case RF_AIROHA_2230:
9361+ case RF_AIROHA_2230S: // 20060420 Add this
9362+ ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( value, 20 );
9363+ break;
9364+
9365+ case RF_AIROHA_7230:
9366+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | (value&0xffffff);
9367+ break;
9368+
9369+ case RF_WB_242:
9370+ case RF_WB_242_1: // 20060619.5 Add
9371+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( value, 24 );
9372+ break;
9373+ }
9374+
9375+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
9376+}
9377+
9378+// 20060717 modify as Bruce's mail
9379+unsigned char adjust_TXVGA_for_iq_mag(hw_data_t *phw_data)
9380+{
9381+ int init_txvga = 0;
9382+ u32 reg_mode_ctrl;
9383+ u32 val;
9384+ s32 iqcal_tone_i0;
9385+ s32 iqcal_tone_q0;
9386+ u32 sqsum;
9387+ s32 iq_mag_0_tx;
9388+ u8 reg_state;
9389+ int current_txvga;
9390+
9391+
9392+ reg_state = 0;
9393+ for( init_txvga=0; init_txvga<10; init_txvga++)
9394+ {
9395+ current_txvga = ( 0x24C40A|(init_txvga<<6) );
9396+ phy_set_rf_data(phw_data, 5, ((5<<24)|current_txvga) );
9397+ phw_data->txvga_setting_for_cal = current_txvga;
9398+
9399+ //pa_stall_execution(30000);//Sleep(30);
9400+ OS_SLEEP(30000); // 20060612.1.a
9401+
9402+ if( !hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl) ) // 20060718.1 modify
9403+ return FALSE;
9404+
9405+ PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
9406+
9407+ // a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to
9408+ // enable "IQ alibration Mode II"
9409+ reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE);
9410+ reg_mode_ctrl &= ~MASK_IQCAL_MODE;
9411+ reg_mode_ctrl |= (MASK_CALIB_START|0x02);
9412+ reg_mode_ctrl |= (MASK_CALIB_START|0x02|2<<2);
9413+ hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
9414+ PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
9415+
9416+ //pa_stall_execution(US);
9417+ OS_SLEEP(1); // 20060612.1.a
9418+
9419+ //pa_stall_execution(300);//Sleep(30);
9420+ OS_SLEEP(300); // 20060612.1.a
9421+
9422+ // b.
9423+ hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
9424+
9425+ PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val));
9426+ //pa_stall_execution(US);
9427+ //pa_stall_execution(300);//Sleep(30);
9428+ OS_SLEEP(300); // 20060612.1.a
9429+
9430+ iqcal_tone_i0 = _s13_to_s32(val & 0x00001FFF);
9431+ iqcal_tone_q0 = _s13_to_s32((val & 0x03FFE000) >> 13);
9432+ PHY_DEBUG(("[CAL] ** iqcal_tone_i0=%d, iqcal_tone_q0=%d\n",
9433+ iqcal_tone_i0, iqcal_tone_q0));
9434+
9435+ sqsum = iqcal_tone_i0*iqcal_tone_i0 + iqcal_tone_q0*iqcal_tone_q0;
9436+ iq_mag_0_tx = (s32) _sqrt(sqsum);
9437+ PHY_DEBUG(("[CAL] ** auto_adjust_txvga_for_iq_mag_0_tx=%d\n", iq_mag_0_tx));
9438+
9439+ if( iq_mag_0_tx>=700 && iq_mag_0_tx<=1750 )
9440+ break;
9441+ else if(iq_mag_0_tx > 1750)
9442+ {
9443+ init_txvga=-2;
9444+ continue;
9445+ }
9446+ else
9447+ continue;
9448+
9449+ }
9450+
9451+ if( iq_mag_0_tx>=700 && iq_mag_0_tx<=1750 )
9452+ return TRUE;
9453+ else
9454+ return FALSE;
9455+}
9456+
9457+
9458+
9459diff --git a/drivers/staging/winbond/phy_calibration.h b/drivers/staging/winbond/phy_calibration.h
9460new file mode 100644
9461index 0000000..b6a65d3
9462--- /dev/null
9463+++ b/drivers/staging/winbond/phy_calibration.h
9464@@ -0,0 +1,101 @@
9465+// 20031229 Turbo add
9466+#define REG_AGC_CTRL1 0x1000
9467+#define REG_AGC_CTRL2 0x1004
9468+#define REG_AGC_CTRL3 0x1008
9469+#define REG_AGC_CTRL4 0x100C
9470+#define REG_AGC_CTRL5 0x1010
9471+#define REG_AGC_CTRL6 0x1014
9472+#define REG_AGC_CTRL7 0x1018
9473+#define REG_AGC_CTRL8 0x101C
9474+#define REG_AGC_CTRL9 0x1020
9475+#define REG_AGC_CTRL10 0x1024
9476+#define REG_CCA_CTRL 0x1028
9477+#define REG_A_ACQ_CTRL 0x102C
9478+#define REG_B_ACQ_CTRL 0x1030
9479+#define REG_A_TXRX_CTRL 0x1034
9480+#define REG_B_TXRX_CTRL 0x1038
9481+#define REG_A_TX_COEF3 0x103C
9482+#define REG_A_TX_COEF2 0x1040
9483+#define REG_A_TX_COEF1 0x1044
9484+#define REG_B_TX_COEF2 0x1048
9485+#define REG_B_TX_COEF1 0x104C
9486+#define REG_MODE_CTRL 0x1050
9487+#define REG_CALIB_DATA 0x1054
9488+#define REG_IQ_ALPHA 0x1058
9489+#define REG_DC_CANCEL 0x105C
9490+#define REG_WTO_READ 0x1060
9491+#define REG_OFFSET_READ 0x1064
9492+#define REG_CALIB_READ1 0x1068
9493+#define REG_CALIB_READ2 0x106C
9494+#define REG_A_FREQ_EST 0x1070
9495+
9496+
9497+
9498+
9499+// 20031101 Turbo add
9500+#define MASK_AMER_OFF_REG BIT(31)
9501+
9502+#define MASK_BMER_OFF_REG BIT(31)
9503+
9504+#define MASK_LNA_FIX_GAIN (BIT(3)|BIT(4))
9505+#define MASK_AGC_FIX BIT(1)
9506+
9507+#define MASK_AGC_FIX_GAIN 0xFF00
9508+
9509+#define MASK_ADC_DC_CAL_STR BIT(10)
9510+#define MASK_CALIB_START BIT(4)
9511+#define MASK_IQCAL_TONE_SEL (BIT(3)|BIT(2))
9512+#define MASK_IQCAL_MODE (BIT(1)|BIT(0))
9513+
9514+#define MASK_TX_CAL_0 0xF0000000
9515+#define TX_CAL_0_SHIFT 28
9516+#define MASK_TX_CAL_1 0x0F000000
9517+#define TX_CAL_1_SHIFT 24
9518+#define MASK_TX_CAL_2 0x00F00000
9519+#define TX_CAL_2_SHIFT 20
9520+#define MASK_TX_CAL_3 0x000F0000
9521+#define TX_CAL_3_SHIFT 16
9522+#define MASK_RX_CAL_0 0x0000F000
9523+#define RX_CAL_0_SHIFT 12
9524+#define MASK_RX_CAL_1 0x00000F00
9525+#define RX_CAL_1_SHIFT 8
9526+#define MASK_RX_CAL_2 0x000000F0
9527+#define RX_CAL_2_SHIFT 4
9528+#define MASK_RX_CAL_3 0x0000000F
9529+#define RX_CAL_3_SHIFT 0
9530+
9531+#define MASK_CANCEL_DC_I 0x3E0
9532+#define CANCEL_DC_I_SHIFT 5
9533+#define MASK_CANCEL_DC_Q 0x01F
9534+#define CANCEL_DC_Q_SHIFT 0
9535+
9536+// LA20040210 kevin
9537+//#define MASK_ADC_DC_CAL_I(x) (((x)&0x1FE00)>>9)
9538+//#define MASK_ADC_DC_CAL_Q(x) ((x)&0x1FF)
9539+#define MASK_ADC_DC_CAL_I(x) (((x)&0x0003FE00)>>9)
9540+#define MASK_ADC_DC_CAL_Q(x) ((x)&0x000001FF)
9541+
9542+// LA20040210 kevin (Turbo has wrong definition)
9543+//#define MASK_IQCAL_TONE_I 0x7FFC000
9544+//#define SHIFT_IQCAL_TONE_I(x) ((x)>>13)
9545+//#define MASK_IQCAL_TONE_Q 0x1FFF
9546+//#define SHIFT_IQCAL_TONE_Q(x) ((x)>>0)
9547+#define MASK_IQCAL_TONE_I 0x00001FFF
9548+#define SHIFT_IQCAL_TONE_I(x) ((x)>>0)
9549+#define MASK_IQCAL_TONE_Q 0x03FFE000
9550+#define SHIFT_IQCAL_TONE_Q(x) ((x)>>13)
9551+
9552+// LA20040210 kevin (Turbo has wrong definition)
9553+//#define MASK_IQCAL_IMAGE_I 0x7FFC000
9554+//#define SHIFT_IQCAL_IMAGE_I(x) ((x)>>13)
9555+//#define MASK_IQCAL_IMAGE_Q 0x1FFF
9556+//#define SHIFT_IQCAL_IMAGE_Q(x) ((x)>>0)
9557+
9558+//#define MASK_IQCAL_IMAGE_I 0x00001FFF
9559+//#define SHIFT_IQCAL_IMAGE_I(x) ((x)>>0)
9560+//#define MASK_IQCAL_IMAGE_Q 0x03FFE000
9561+//#define SHIFT_IQCAL_IMAGE_Q(x) ((x)>>13)
9562+
9563+void phy_set_rf_data( phw_data_t pHwData, u32 index, u32 value );
9564+#define phy_init_rf( _A ) //RFSynthesizer_initial( _A )
9565+
9566diff --git a/drivers/staging/winbond/reg.c b/drivers/staging/winbond/reg.c
9567new file mode 100644
9568index 0000000..b475c7a
9569--- /dev/null
9570+++ b/drivers/staging/winbond/reg.c
9571@@ -0,0 +1,2683 @@
9572+#include "os_common.h"
9573+
9574+///////////////////////////////////////////////////////////////////////////////////////////////////
9575+// Original Phy.h
9576+//*****************************************************************************
9577+
9578+/*****************************************************************************
9579+; For MAXIM2825/6/7 Ver. 331 or more
9580+; Edited by Tiger, Sep-17-2003
9581+; revised by Ben, Sep-18-2003
9582+
9583+0x00 0x000a2
9584+0x01 0x21cc0
9585+;0x02 0x13802
9586+0x02 0x1383a
9587+
9588+;channe1 01 ; 0x03 0x30142 ; 0x04 0x0b333;
9589+;channe1 02 ;0x03 0x32141 ;0x04 0x08444;
9590+;channe1 03 ;0x03 0x32143 ;0x04 0x0aeee;
9591+;channe1 04 ;0x03 0x32142 ;0x04 0x0b333;
9592+;channe1 05 ;0x03 0x31141 ;0x04 0x08444;
9593+;channe1 06 ;
9594+0x03 0x31143;
9595+0x04 0x0aeee;
9596+;channe1 07 ;0x03 0x31142 ;0x04 0x0b333;
9597+;channe1 08 ;0x03 0x33141 ;0x04 0x08444;
9598+;channe1 09 ;0x03 0x33143 ;0x04 0x0aeee;
9599+;channe1 10 ;0x03 0x33142 ;0x04 0x0b333;
9600+;channe1 11 ;0x03 0x30941 ;0x04 0x08444;
9601+;channe1 12 ;0x03 0x30943 ;0x04 0x0aeee;
9602+;channe1 13 ;0x03 0x30942 ;0x04 0x0b333;
9603+
9604+0x05 0x28986
9605+0x06 0x18008
9606+0x07 0x38400
9607+0x08 0x05100; 100 Hz DC
9608+;0x08 0x05900; 30 KHz DC
9609+0x09 0x24f08
9610+0x0a 0x17e00, 0x17ea0
9611+0x0b 0x37d80
9612+0x0c 0x0c900 // 0x0ca00 (lager power 9db than 0x0c000), 0x0c000
9613+*****************************************************************************/
9614+// MAX2825 (pure b/g)
9615+u32 max2825_rf_data[] =
9616+{
9617+ (0x00<<18)|0x000a2,
9618+ (0x01<<18)|0x21cc0,
9619+ (0x02<<18)|0x13806,
9620+ (0x03<<18)|0x30142,
9621+ (0x04<<18)|0x0b333,
9622+ (0x05<<18)|0x289A6,
9623+ (0x06<<18)|0x18008,
9624+ (0x07<<18)|0x38000,
9625+ (0x08<<18)|0x05100,
9626+ (0x09<<18)|0x24f08,
9627+ (0x0A<<18)|0x14000,
9628+ (0x0B<<18)|0x37d80,
9629+ (0x0C<<18)|0x0c100 // 11a: 0x0c300, 11g: 0x0c100
9630+};
9631+
9632+u32 max2825_channel_data_24[][3] =
9633+{
9634+ {(0x03<<18)|0x30142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 01
9635+ {(0x03<<18)|0x32141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 02
9636+ {(0x03<<18)|0x32143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 03
9637+ {(0x03<<18)|0x32142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 04
9638+ {(0x03<<18)|0x31141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 05
9639+ {(0x03<<18)|0x31143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 06
9640+ {(0x03<<18)|0x31142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 07
9641+ {(0x03<<18)|0x33141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 08
9642+ {(0x03<<18)|0x33143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 09
9643+ {(0x03<<18)|0x33142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 10
9644+ {(0x03<<18)|0x30941, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 11
9645+ {(0x03<<18)|0x30943, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 12
9646+ {(0x03<<18)|0x30942, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 13
9647+ {(0x03<<18)|0x32941, (0x04<<18)|0x09999, (0x05<<18)|0x289A6} // 14 (2484MHz) hhmodify
9648+};
9649+
9650+u32 max2825_power_data_24[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100};
9651+
9652+/****************************************************************************/
9653+// MAX2827 (a/b/g)
9654+u32 max2827_rf_data[] =
9655+{
9656+ (0x00<<18)|0x000a2,
9657+ (0x01<<18)|0x21cc0,
9658+ (0x02<<18)|0x13806,
9659+ (0x03<<18)|0x30142,
9660+ (0x04<<18)|0x0b333,
9661+ (0x05<<18)|0x289A6,
9662+ (0x06<<18)|0x18008,
9663+ (0x07<<18)|0x38000,
9664+ (0x08<<18)|0x05100,
9665+ (0x09<<18)|0x24f08,
9666+ (0x0A<<18)|0x14000,
9667+ (0x0B<<18)|0x37d80,
9668+ (0x0C<<18)|0x0c100 // 11a: 0x0c300, 11g: 0x0c100
9669+};
9670+
9671+u32 max2827_channel_data_24[][3] =
9672+{
9673+ {(0x03<<18)|0x30142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 01
9674+ {(0x03<<18)|0x32141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 02
9675+ {(0x03<<18)|0x32143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 03
9676+ {(0x03<<18)|0x32142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 04
9677+ {(0x03<<18)|0x31141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 05
9678+ {(0x03<<18)|0x31143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 06
9679+ {(0x03<<18)|0x31142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 07
9680+ {(0x03<<18)|0x33141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 08
9681+ {(0x03<<18)|0x33143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 09
9682+ {(0x03<<18)|0x33142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 10
9683+ {(0x03<<18)|0x30941, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 11
9684+ {(0x03<<18)|0x30943, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 12
9685+ {(0x03<<18)|0x30942, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 13
9686+ {(0x03<<18)|0x32941, (0x04<<18)|0x09999, (0x05<<18)|0x289A6} // 14 (2484MHz) hhmodify
9687+};
9688+
9689+u32 max2827_channel_data_50[][3] =
9690+{
9691+ {(0x03<<18)|0x33cc3, (0x04<<18)|0x08ccc, (0x05<<18)|0x2A9A6}, // channel 36
9692+ {(0x03<<18)|0x302c0, (0x04<<18)|0x08000, (0x05<<18)|0x2A9A6}, // channel 40
9693+ {(0x03<<18)|0x302c2, (0x04<<18)|0x0b333, (0x05<<18)|0x2A9A6}, // channel 44
9694+ {(0x03<<18)|0x322c1, (0x04<<18)|0x09999, (0x05<<18)|0x2A9A6}, // channel 48
9695+ {(0x03<<18)|0x312c1, (0x04<<18)|0x0a666, (0x05<<18)|0x2A9A6}, // channel 52
9696+ {(0x03<<18)|0x332c3, (0x04<<18)|0x08ccc, (0x05<<18)|0x2A9A6}, // channel 56
9697+ {(0x03<<18)|0x30ac0, (0x04<<18)|0x08000, (0x05<<18)|0x2A9A6}, // channel 60
9698+ {(0x03<<18)|0x30ac2, (0x04<<18)|0x0b333, (0x05<<18)|0x2A9A6} // channel 64
9699+};
9700+
9701+u32 max2827_power_data_24[] = {(0x0C<<18)|0x0C000, (0x0C<<18)|0x0D600, (0x0C<<18)|0x0C100};
9702+u32 max2827_power_data_50[] = {(0x0C<<18)|0x0C400, (0x0C<<18)|0x0D500, (0x0C<<18)|0x0C300};
9703+
9704+/****************************************************************************/
9705+// MAX2828 (a/b/g)
9706+u32 max2828_rf_data[] =
9707+{
9708+ (0x00<<18)|0x000a2,
9709+ (0x01<<18)|0x21cc0,
9710+ (0x02<<18)|0x13806,
9711+ (0x03<<18)|0x30142,
9712+ (0x04<<18)|0x0b333,
9713+ (0x05<<18)|0x289A6,
9714+ (0x06<<18)|0x18008,
9715+ (0x07<<18)|0x38000,
9716+ (0x08<<18)|0x05100,
9717+ (0x09<<18)|0x24f08,
9718+ (0x0A<<18)|0x14000,
9719+ (0x0B<<18)|0x37d80,
9720+ (0x0C<<18)|0x0c100 // 11a: 0x0c300, 11g: 0x0c100
9721+};
9722+
9723+u32 max2828_channel_data_24[][3] =
9724+{
9725+ {(0x03<<18)|0x30142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 01
9726+ {(0x03<<18)|0x32141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 02
9727+ {(0x03<<18)|0x32143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 03
9728+ {(0x03<<18)|0x32142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 04
9729+ {(0x03<<18)|0x31141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 05
9730+ {(0x03<<18)|0x31143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 06
9731+ {(0x03<<18)|0x31142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 07
9732+ {(0x03<<18)|0x33141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 08
9733+ {(0x03<<18)|0x33143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 09
9734+ {(0x03<<18)|0x33142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 10
9735+ {(0x03<<18)|0x30941, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 11
9736+ {(0x03<<18)|0x30943, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 12
9737+ {(0x03<<18)|0x30942, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 13
9738+ {(0x03<<18)|0x32941, (0x04<<18)|0x09999, (0x05<<18)|0x289A6} // 14 (2484MHz) hhmodify
9739+};
9740+
9741+u32 max2828_channel_data_50[][3] =
9742+{
9743+ {(0x03<<18)|0x33cc3, (0x04<<18)|0x08ccc, (0x05<<18)|0x289A6}, // channel 36
9744+ {(0x03<<18)|0x302c0, (0x04<<18)|0x08000, (0x05<<18)|0x289A6}, // channel 40
9745+ {(0x03<<18)|0x302c2, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channel 44
9746+ {(0x03<<18)|0x322c1, (0x04<<18)|0x09999, (0x05<<18)|0x289A6}, // channel 48
9747+ {(0x03<<18)|0x312c1, (0x04<<18)|0x0a666, (0x05<<18)|0x289A6}, // channel 52
9748+ {(0x03<<18)|0x332c3, (0x04<<18)|0x08ccc, (0x05<<18)|0x289A6}, // channel 56
9749+ {(0x03<<18)|0x30ac0, (0x04<<18)|0x08000, (0x05<<18)|0x289A6}, // channel 60
9750+ {(0x03<<18)|0x30ac2, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6} // channel 64
9751+};
9752+
9753+u32 max2828_power_data_24[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100};
9754+u32 max2828_power_data_50[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100};
9755+
9756+/****************************************************************************/
9757+// LA20040728 kevin
9758+// MAX2829 (a/b/g)
9759+u32 max2829_rf_data[] =
9760+{
9761+ (0x00<<18)|0x000a2,
9762+ (0x01<<18)|0x23520,
9763+ (0x02<<18)|0x13802,
9764+ (0x03<<18)|0x30142,
9765+ (0x04<<18)|0x0b333,
9766+ (0x05<<18)|0x28906,
9767+ (0x06<<18)|0x18008,
9768+ (0x07<<18)|0x3B500,
9769+ (0x08<<18)|0x05100,
9770+ (0x09<<18)|0x24f08,
9771+ (0x0A<<18)|0x14000,
9772+ (0x0B<<18)|0x37d80,
9773+ (0x0C<<18)|0x0F300 //TXVGA=51, (MAX-6 dB)
9774+};
9775+
9776+u32 max2829_channel_data_24[][3] =
9777+{
9778+ {(3<<18)|0x30142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 01 (2412MHz)
9779+ {(3<<18)|0x32141, (4<<18)|0x08444, (5<<18)|0x289C6}, // 02 (2417MHz)
9780+ {(3<<18)|0x32143, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 03 (2422MHz)
9781+ {(3<<18)|0x32142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 04 (2427MHz)
9782+ {(3<<18)|0x31141, (4<<18)|0x08444, (5<<18)|0x289C6}, // 05 (2432MHz)
9783+ {(3<<18)|0x31143, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 06 (2437MHz)
9784+ {(3<<18)|0x31142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 07 (2442MHz)
9785+ {(3<<18)|0x33141, (4<<18)|0x08444, (5<<18)|0x289C6}, // 08 (2447MHz)
9786+ {(3<<18)|0x33143, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 09 (2452MHz)
9787+ {(3<<18)|0x33142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 10 (2457MHz)
9788+ {(3<<18)|0x30941, (4<<18)|0x08444, (5<<18)|0x289C6}, // 11 (2462MHz)
9789+ {(3<<18)|0x30943, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 12 (2467MHz)
9790+ {(3<<18)|0x30942, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 13 (2472MHz)
9791+ {(3<<18)|0x32941, (4<<18)|0x09999, (5<<18)|0x289C6}, // 14 (2484MHz) hh-modify
9792+};
9793+
9794+u32 max2829_channel_data_50[][4] =
9795+{
9796+ {36, (3<<18)|0x33cc3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 36 (5.180GHz)
9797+ {40, (3<<18)|0x302c0, (4<<18)|0x08000, (5<<18)|0x2A946}, // 40 (5.200GHz)
9798+ {44, (3<<18)|0x302c2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 44 (5.220GHz)
9799+ {48, (3<<18)|0x322c1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 48 (5.240GHz)
9800+ {52, (3<<18)|0x312c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 52 (5.260GHz)
9801+ {56, (3<<18)|0x332c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 56 (5.280GHz)
9802+ {60, (3<<18)|0x30ac0, (4<<18)|0x08000, (5<<18)|0x2A946}, // 60 (5.300GHz)
9803+ {64, (3<<18)|0x30ac2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 64 (5.320GHz)
9804+
9805+ {100, (3<<18)|0x30ec0, (4<<18)|0x08000, (5<<18)|0x2A9C6}, // 100 (5.500GHz)
9806+ {104, (3<<18)|0x30ec2, (4<<18)|0x0b333, (5<<18)|0x2A9C6}, // 104 (5.520GHz)
9807+ {108, (3<<18)|0x32ec1, (4<<18)|0x09999, (5<<18)|0x2A9C6}, // 108 (5.540GHz)
9808+ {112, (3<<18)|0x31ec1, (4<<18)|0x0a666, (5<<18)|0x2A9C6}, // 112 (5.560GHz)
9809+ {116, (3<<18)|0x33ec3, (4<<18)|0x08ccc, (5<<18)|0x2A9C6}, // 116 (5.580GHz)
9810+ {120, (3<<18)|0x301c0, (4<<18)|0x08000, (5<<18)|0x2A9C6}, // 120 (5.600GHz)
9811+ {124, (3<<18)|0x301c2, (4<<18)|0x0b333, (5<<18)|0x2A9C6}, // 124 (5.620GHz)
9812+ {128, (3<<18)|0x321c1, (4<<18)|0x09999, (5<<18)|0x2A9C6}, // 128 (5.640GHz)
9813+ {132, (3<<18)|0x311c1, (4<<18)|0x0a666, (5<<18)|0x2A9C6}, // 132 (5.660GHz)
9814+ {136, (3<<18)|0x331c3, (4<<18)|0x08ccc, (5<<18)|0x2A9C6}, // 136 (5.680GHz)
9815+ {140, (3<<18)|0x309c0, (4<<18)|0x08000, (5<<18)|0x2A9C6}, // 140 (5.700GHz)
9816+
9817+ {149, (3<<18)|0x329c2, (4<<18)|0x0b333, (5<<18)|0x2A9C6}, // 149 (5.745GHz)
9818+ {153, (3<<18)|0x319c1, (4<<18)|0x09999, (5<<18)|0x2A9C6}, // 153 (5.765GHz)
9819+ {157, (3<<18)|0x339c1, (4<<18)|0x0a666, (5<<18)|0x2A9C6}, // 157 (5.785GHz)
9820+ {161, (3<<18)|0x305c3, (4<<18)|0x08ccc, (5<<18)|0x2A9C6}, // 161 (5.805GHz)
9821+
9822+ // Japan
9823+ { 184, (3<<18)|0x308c2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 184 (4.920GHz)
9824+ { 188, (3<<18)|0x328c1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 188 (4.940GHz)
9825+ { 192, (3<<18)|0x318c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 192 (4.960GHz)
9826+ { 196, (3<<18)|0x338c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 196 (4.980GHz)
9827+ { 8, (3<<18)|0x324c1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 8 (5.040GHz)
9828+ { 12, (3<<18)|0x314c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 12 (5.060GHz)
9829+ { 16, (3<<18)|0x334c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 16 (5.080GHz)
9830+ { 34, (3<<18)|0x31cc2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 34 (5.170GHz)
9831+ { 38, (3<<18)|0x33cc1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 38 (5.190GHz)
9832+ { 42, (3<<18)|0x302c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 42 (5.210GHz)
9833+ { 46, (3<<18)|0x322c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 46 (5.230GHz)
9834+};
9835+
9836+/*****************************************************************************
9837+; For MAXIM2825/6/7 Ver. 317 or less
9838+; Edited by Tiger, Sep-17-2003 for 2.4Ghz channels
9839+; Updated by Tiger, Sep-22-2003 for 5.0Ghz channels
9840+; Corrected by Tiger, Sep-23-2003, for 0x03 and 0x04 of 5.0Ghz channels
9841+
9842+0x00 0x00080
9843+0x01 0x214c0
9844+0x02 0x13802
9845+
9846+;2.4GHz Channels
9847+;channe1 01 (2.412GHz); 0x03 0x30143 ;0x04 0x0accc
9848+;channe1 02 (2.417GHz); 0x03 0x32140 ;0x04 0x09111
9849+;channe1 03 (2.422GHz); 0x03 0x32142 ;0x04 0x0bbbb
9850+;channe1 04 (2.427GHz); 0x03 0x32143 ;0x04 0x0accc
9851+;channe1 05 (2.432GHz); 0x03 0x31140 ;0x04 0x09111
9852+;channe1 06 (2.437GHz); 0x03 0x31142 ;0x04 0x0bbbb
9853+;channe1 07 (2.442GHz); 0x03 0x31143 ;0x04 0x0accc
9854+;channe1 08 (2.447GHz); 0x03 0x33140 ;0x04 0x09111
9855+;channe1 09 (2.452GHz); 0x03 0x33142 ;0x04 0x0bbbb
9856+;channe1 10 (2.457GHz); 0x03 0x33143 ;0x04 0x0accc
9857+;channe1 11 (2.462GHz); 0x03 0x30940 ;0x04 0x09111
9858+;channe1 12 (2.467GHz); 0x03 0x30942 ;0x04 0x0bbbb
9859+;channe1 13 (2.472GHz); 0x03 0x30943 ;0x04 0x0accc
9860+
9861+;5.0Ghz Channels
9862+;channel 36 (5.180GHz); 0x03 0x33cc0 ;0x04 0x0b333
9863+;channel 40 (5.200GHz); 0x03 0x302c0 ;0x04 0x08000
9864+;channel 44 (5.220GHz); 0x03 0x302c2 ;0x04 0x0b333
9865+;channel 48 (5.240GHz); 0x03 0x322c1 ;0x04 0x09999
9866+;channel 52 (5.260GHz); 0x03 0x312c1 ;0x04 0x0a666
9867+;channel 56 (5.280GHz); 0x03 0x332c3 ;0x04 0x08ccc
9868+;channel 60 (5.300GHz); 0x03 0x30ac0 ;0x04 0x08000
9869+;channel 64 (5.320GHz); 0x03 0x30ac2 ;0x04 0x08333
9870+
9871+;2.4GHz band ;0x05 0x28986;
9872+;5.0GHz band
9873+0x05 0x2a986
9874+
9875+0x06 0x18008
9876+0x07 0x38400
9877+0x08 0x05108
9878+0x09 0x27ff8
9879+0x0a 0x14000
9880+0x0b 0x37f99
9881+0x0c 0x0c000
9882+*****************************************************************************/
9883+u32 maxim_317_rf_data[] =
9884+{
9885+ (0x00<<18)|0x000a2,
9886+ (0x01<<18)|0x214c0,
9887+ (0x02<<18)|0x13802,
9888+ (0x03<<18)|0x30143,
9889+ (0x04<<18)|0x0accc,
9890+ (0x05<<18)|0x28986,
9891+ (0x06<<18)|0x18008,
9892+ (0x07<<18)|0x38400,
9893+ (0x08<<18)|0x05108,
9894+ (0x09<<18)|0x27ff8,
9895+ (0x0A<<18)|0x14000,
9896+ (0x0B<<18)|0x37f99,
9897+ (0x0C<<18)|0x0c000
9898+};
9899+
9900+u32 maxim_317_channel_data_24[][3] =
9901+{
9902+ {(0x03<<18)|0x30143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 01
9903+ {(0x03<<18)|0x32140, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 02
9904+ {(0x03<<18)|0x32142, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 03
9905+ {(0x03<<18)|0x32143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 04
9906+ {(0x03<<18)|0x31140, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 05
9907+ {(0x03<<18)|0x31142, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 06
9908+ {(0x03<<18)|0x31143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 07
9909+ {(0x03<<18)|0x33140, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 08
9910+ {(0x03<<18)|0x33142, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 09
9911+ {(0x03<<18)|0x33143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 10
9912+ {(0x03<<18)|0x30940, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 11
9913+ {(0x03<<18)|0x30942, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 12
9914+ {(0x03<<18)|0x30943, (0x04<<18)|0x0accc, (0x05<<18)|0x28986} // channe1 13
9915+};
9916+
9917+u32 maxim_317_channel_data_50[][3] =
9918+{
9919+ {(0x03<<18)|0x33cc0, (0x04<<18)|0x0b333, (0x05<<18)|0x2a986}, // channel 36
9920+ {(0x03<<18)|0x302c0, (0x04<<18)|0x08000, (0x05<<18)|0x2a986}, // channel 40
9921+ {(0x03<<18)|0x302c3, (0x04<<18)|0x0accc, (0x05<<18)|0x2a986}, // channel 44
9922+ {(0x03<<18)|0x322c1, (0x04<<18)|0x09666, (0x05<<18)|0x2a986}, // channel 48
9923+ {(0x03<<18)|0x312c2, (0x04<<18)|0x09999, (0x05<<18)|0x2a986}, // channel 52
9924+ {(0x03<<18)|0x332c0, (0x04<<18)|0x0b333, (0x05<<18)|0x2a99e}, // channel 56
9925+ {(0x03<<18)|0x30ac0, (0x04<<18)|0x08000, (0x05<<18)|0x2a99e}, // channel 60
9926+ {(0x03<<18)|0x30ac3, (0x04<<18)|0x0accc, (0x05<<18)|0x2a99e} // channel 64
9927+};
9928+
9929+u32 maxim_317_power_data_24[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100};
9930+u32 maxim_317_power_data_50[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100};
9931+
9932+/*****************************************************************************
9933+;;AL2230 MP (Mass Production Version)
9934+;;RF Registers Setting for Airoha AL2230 silicon after June 1st, 2004
9935+;;Updated by Tiger Huang (June 1st, 2004)
9936+;;20-bit length and LSB first
9937+
9938+;;Ch01 (2412MHz) ;0x00 0x09EFC ;0x01 0x8CCCC;
9939+;;Ch02 (2417MHz) ;0x00 0x09EFC ;0x01 0x8CCCD;
9940+;;Ch03 (2422MHz) ;0x00 0x09E7C ;0x01 0x8CCCC;
9941+;;Ch04 (2427MHz) ;0x00 0x09E7C ;0x01 0x8CCCD;
9942+;;Ch05 (2432MHz) ;0x00 0x05EFC ;0x01 0x8CCCC;
9943+;;Ch06 (2437MHz) ;0x00 0x05EFC ;0x01 0x8CCCD;
9944+;;Ch07 (2442MHz) ;0x00 0x05E7C ;0x01 0x8CCCC;
9945+;;Ch08 (2447MHz) ;0x00 0x05E7C ;0x01 0x8CCCD;
9946+;;Ch09 (2452MHz) ;0x00 0x0DEFC ;0x01 0x8CCCC;
9947+;;Ch10 (2457MHz) ;0x00 0x0DEFC ;0x01 0x8CCCD;
9948+;;Ch11 (2462MHz) ;0x00 0x0DE7C ;0x01 0x8CCCC;
9949+;;Ch12 (2467MHz) ;0x00 0x0DE7C ;0x01 0x8CCCD;
9950+;;Ch13 (2472MHz) ;0x00 0x03EFC ;0x01 0x8CCCC;
9951+;;Ch14 (2484Mhz) ;0x00 0x03E7C ;0x01 0x86666;
9952+
9953+0x02 0x401D8; RXDCOC BW 100Hz for RXHP low
9954+;;0x02 0x481DC; RXDCOC BW 30Khz for RXHP low
9955+
9956+0x03 0xCFFF0
9957+0x04 0x23800
9958+0x05 0xA3B72
9959+0x06 0x6DA01
9960+0x07 0xE1688
9961+0x08 0x11600
9962+0x09 0x99E02
9963+0x0A 0x5DDB0
9964+0x0B 0xD9900
9965+0x0C 0x3FFBD
9966+0x0D 0xB0000
9967+0x0F 0xF00A0
9968+
9969+;RF Calibration for Airoha AL2230
9970+;Edit by Ben Chang (01/30/04)
9971+;Updated by Tiger Huang (03/03/04)
9972+0x0f 0xf00a0 ; Initial Setting
9973+0x0f 0xf00b0 ; Activate TX DCC
9974+0x0f 0xf02a0 ; Activate Phase Calibration
9975+0x0f 0xf00e0 ; Activate Filter RC Calibration
9976+0x0f 0xf00a0 ; Restore Initial Setting
9977+*****************************************************************************/
9978+
9979+u32 al2230_rf_data[] =
9980+{
9981+ (0x00<<20)|0x09EFC,
9982+ (0x01<<20)|0x8CCCC,
9983+ (0x02<<20)|0x40058,// 20060627 Anson 0x401D8,
9984+ (0x03<<20)|0xCFFF0,
9985+ (0x04<<20)|0x24100,// 20060627 Anson 0x23800,
9986+ (0x05<<20)|0xA3B2F,// 20060627 Anson 0xA3B72
9987+ (0x06<<20)|0x6DA01,
9988+ (0x07<<20)|0xE3628,// 20060627 Anson 0xE1688,
9989+ (0x08<<20)|0x11600,
9990+ (0x09<<20)|0x9DC02,// 20060627 Anosn 0x97602,//0x99E02, //0x9AE02
9991+ (0x0A<<20)|0x5ddb0, // 941206 For QCOM interference 0x588b0,//0x5DDB0, 940601 adj 0x5aa30 for bluetooth
9992+ (0x0B<<20)|0xD9900,
9993+ (0x0C<<20)|0x3FFBD,
9994+ (0x0D<<20)|0xB0000,
9995+ (0x0F<<20)|0xF01A0 // 20060627 Anson 0xF00A0
9996+};
9997+
9998+u32 al2230s_rf_data[] =
9999+{
10000+ (0x00<<20)|0x09EFC,
10001+ (0x01<<20)|0x8CCCC,
10002+ (0x02<<20)|0x40058,// 20060419 0x401D8,
10003+ (0x03<<20)|0xCFFF0,
10004+ (0x04<<20)|0x24100,// 20060419 0x23800,
10005+ (0x05<<20)|0xA3B2F,// 20060419 0xA3B72,
10006+ (0x06<<20)|0x6DA01,
10007+ (0x07<<20)|0xE3628,// 20060419 0xE1688,
10008+ (0x08<<20)|0x11600,
10009+ (0x09<<20)|0x9DC02,// 20060419 0x97602,//0x99E02, //0x9AE02
10010+ (0x0A<<20)|0x5DDB0,// 941206 For QCOM interference 0x588b0,//0x5DDB0, 940601 adj 0x5aa30 for bluetooth
10011+ (0x0B<<20)|0xD9900,
10012+ (0x0C<<20)|0x3FFBD,
10013+ (0x0D<<20)|0xB0000,
10014+ (0x0F<<20)|0xF01A0 // 20060419 0xF00A0
10015+};
10016+
10017+u32 al2230_channel_data_24[][2] =
10018+{
10019+ {(0x00<<20)|0x09EFC, (0x01<<20)|0x8CCCC}, // channe1 01
10020+ {(0x00<<20)|0x09EFC, (0x01<<20)|0x8CCCD}, // channe1 02
10021+ {(0x00<<20)|0x09E7C, (0x01<<20)|0x8CCCC}, // channe1 03
10022+ {(0x00<<20)|0x09E7C, (0x01<<20)|0x8CCCD}, // channe1 04
10023+ {(0x00<<20)|0x05EFC, (0x01<<20)|0x8CCCC}, // channe1 05
10024+ {(0x00<<20)|0x05EFC, (0x01<<20)|0x8CCCD}, // channe1 06
10025+ {(0x00<<20)|0x05E7C, (0x01<<20)|0x8CCCC}, // channe1 07
10026+ {(0x00<<20)|0x05E7C, (0x01<<20)|0x8CCCD}, // channe1 08
10027+ {(0x00<<20)|0x0DEFC, (0x01<<20)|0x8CCCC}, // channe1 09
10028+ {(0x00<<20)|0x0DEFC, (0x01<<20)|0x8CCCD}, // channe1 10
10029+ {(0x00<<20)|0x0DE7C, (0x01<<20)|0x8CCCC}, // channe1 11
10030+ {(0x00<<20)|0x0DE7C, (0x01<<20)|0x8CCCD}, // channe1 12
10031+ {(0x00<<20)|0x03EFC, (0x01<<20)|0x8CCCC}, // channe1 13
10032+ {(0x00<<20)|0x03E7C, (0x01<<20)|0x86666} // channe1 14
10033+};
10034+
10035+// Current setting. u32 airoha_power_data_24[] = {(0x09<<20)|0x90202, (0x09<<20)|0x96602, (0x09<<20)|0x97602};
10036+#define AIROHA_TXVGA_LOW_INDEX 31 // Index for 0x90202
10037+#define AIROHA_TXVGA_MIDDLE_INDEX 12 // Index for 0x96602
10038+#define AIROHA_TXVGA_HIGH_INDEX 8 // Index for 0x97602 1.0.24.0 1.0.28.0
10039+/*
10040+u32 airoha_power_data_24[] =
10041+{
10042+ 0x9FE02, // Max - 0 dB
10043+ 0x9BE02, // Max - 1 dB
10044+ 0x9DE02, // Max - 2 dB
10045+ 0x99E02, // Max - 3 dB
10046+ 0x9EE02, // Max - 4 dB
10047+ 0x9AE02, // Max - 5 dB
10048+ 0x9CE02, // Max - 6 dB
10049+ 0x98E02, // Max - 7 dB
10050+ 0x97602, // Max - 8 dB
10051+ 0x93602, // Max - 9 dB
10052+ 0x95602, // Max - 10 dB
10053+ 0x91602, // Max - 11 dB
10054+ 0x96602, // Max - 12 dB
10055+ 0x92602, // Max - 13 dB
10056+ 0x94602, // Max - 14 dB
10057+ 0x90602, // Max - 15 dB
10058+ 0x97A02, // Max - 16 dB
10059+ 0x93A02, // Max - 17 dB
10060+ 0x95A02, // Max - 18 dB
10061+ 0x91A02, // Max - 19 dB
10062+ 0x96A02, // Max - 20 dB
10063+ 0x92A02, // Max - 21 dB
10064+ 0x94A02, // Max - 22 dB
10065+ 0x90A02, // Max - 23 dB
10066+ 0x97202, // Max - 24 dB
10067+ 0x93202, // Max - 25 dB
10068+ 0x95202, // Max - 26 dB
10069+ 0x91202, // Max - 27 dB
10070+ 0x96202, // Max - 28 dB
10071+ 0x92202, // Max - 29 dB
10072+ 0x94202, // Max - 30 dB
10073+ 0x90202 // Max - 31 dB
10074+};
10075+*/
10076+
10077+// 20040927 1.1.69.1000 ybjiang
10078+// from John
10079+u32 al2230_txvga_data[][2] =
10080+{
10081+ //value , index
10082+ {0x090202, 0},
10083+ {0x094202, 2},
10084+ {0x092202, 4},
10085+ {0x096202, 6},
10086+ {0x091202, 8},
10087+ {0x095202, 10},
10088+ {0x093202, 12},
10089+ {0x097202, 14},
10090+ {0x090A02, 16},
10091+ {0x094A02, 18},
10092+ {0x092A02, 20},
10093+ {0x096A02, 22},
10094+ {0x091A02, 24},
10095+ {0x095A02, 26},
10096+ {0x093A02, 28},
10097+ {0x097A02, 30},
10098+ {0x090602, 32},
10099+ {0x094602, 34},
10100+ {0x092602, 36},
10101+ {0x096602, 38},
10102+ {0x091602, 40},
10103+ {0x095602, 42},
10104+ {0x093602, 44},
10105+ {0x097602, 46},
10106+ {0x090E02, 48},
10107+ {0x098E02, 49},
10108+ {0x094E02, 50},
10109+ {0x09CE02, 51},
10110+ {0x092E02, 52},
10111+ {0x09AE02, 53},
10112+ {0x096E02, 54},
10113+ {0x09EE02, 55},
10114+ {0x091E02, 56},
10115+ {0x099E02, 57},
10116+ {0x095E02, 58},
10117+ {0x09DE02, 59},
10118+ {0x093E02, 60},
10119+ {0x09BE02, 61},
10120+ {0x097E02, 62},
10121+ {0x09FE02, 63}
10122+};
10123+
10124+//--------------------------------
10125+// For Airoha AL7230, 2.4Ghz band
10126+// Edit by Tiger, (March, 9, 2005)
10127+// 24bit, MSB first
10128+
10129+//channel independent registers:
10130+u32 al7230_rf_data_24[] =
10131+{
10132+ (0x00<<24)|0x003790,
10133+ (0x01<<24)|0x133331,
10134+ (0x02<<24)|0x841FF2,
10135+ (0x03<<24)|0x3FDFA3,
10136+ (0x04<<24)|0x7FD784,
10137+ (0x05<<24)|0x802B55,
10138+ (0x06<<24)|0x56AF36,
10139+ (0x07<<24)|0xCE0207,
10140+ (0x08<<24)|0x6EBC08,
10141+ (0x09<<24)|0x221BB9,
10142+ (0x0A<<24)|0xE0000A,
10143+ (0x0B<<24)|0x08071B,
10144+ (0x0C<<24)|0x000A3C,
10145+ (0x0D<<24)|0xFFFFFD,
10146+ (0x0E<<24)|0x00000E,
10147+ (0x0F<<24)|0x1ABA8F
10148+};
10149+
10150+u32 al7230_channel_data_24[][2] =
10151+{
10152+ {(0x00<<24)|0x003790, (0x01<<24)|0x133331}, // channe1 01
10153+ {(0x00<<24)|0x003790, (0x01<<24)|0x1B3331}, // channe1 02
10154+ {(0x00<<24)|0x003790, (0x01<<24)|0x033331}, // channe1 03
10155+ {(0x00<<24)|0x003790, (0x01<<24)|0x0B3331}, // channe1 04
10156+ {(0x00<<24)|0x0037A0, (0x01<<24)|0x133331}, // channe1 05
10157+ {(0x00<<24)|0x0037A0, (0x01<<24)|0x1B3331}, // channe1 06
10158+ {(0x00<<24)|0x0037A0, (0x01<<24)|0x033331}, // channe1 07
10159+ {(0x00<<24)|0x0037A0, (0x01<<24)|0x0B3331}, // channe1 08
10160+ {(0x00<<24)|0x0037B0, (0x01<<24)|0x133331}, // channe1 09
10161+ {(0x00<<24)|0x0037B0, (0x01<<24)|0x1B3331}, // channe1 10
10162+ {(0x00<<24)|0x0037B0, (0x01<<24)|0x033331}, // channe1 11
10163+ {(0x00<<24)|0x0037B0, (0x01<<24)|0x0B3331}, // channe1 12
10164+ {(0x00<<24)|0x0037C0, (0x01<<24)|0x133331}, // channe1 13
10165+ {(0x00<<24)|0x0037C0, (0x01<<24)|0x066661} // channel 14
10166+};
10167+
10168+//channel independent registers:
10169+u32 al7230_rf_data_50[] =
10170+{
10171+ (0x00<<24)|0x0FF520,
10172+ (0x01<<24)|0x000001,
10173+ (0x02<<24)|0x451FE2,
10174+ (0x03<<24)|0x5FDFA3,
10175+ (0x04<<24)|0x6FD784,
10176+ (0x05<<24)|0x853F55,
10177+ (0x06<<24)|0x56AF36,
10178+ (0x07<<24)|0xCE0207,
10179+ (0x08<<24)|0x6EBC08,
10180+ (0x09<<24)|0x221BB9,
10181+ (0x0A<<24)|0xE0600A,
10182+ (0x0B<<24)|0x08044B,
10183+ (0x0C<<24)|0x00143C,
10184+ (0x0D<<24)|0xFFFFFD,
10185+ (0x0E<<24)|0x00000E,
10186+ (0x0F<<24)|0x12BACF //5Ghz default state
10187+};
10188+
10189+u32 al7230_channel_data_5[][4] =
10190+{
10191+ //channel dependent registers: 0x00, 0x01 and 0x04
10192+ //11J ===========
10193+ {184, (0x00<<24)|0x0FF520, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 184
10194+ {188, (0x00<<24)|0x0FF520, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 188
10195+ {192, (0x00<<24)|0x0FF530, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 192
10196+ {196, (0x00<<24)|0x0FF530, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 196
10197+ {8, (0x00<<24)|0x0FF540, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 008
10198+ {12, (0x00<<24)|0x0FF540, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 012
10199+ {16, (0x00<<24)|0x0FF550, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 016
10200+ {34, (0x00<<24)|0x0FF560, (0x01<<24)|0x055551, (0x04<<24)|0x77F784}, // channel 034
10201+ {38, (0x00<<24)|0x0FF570, (0x01<<24)|0x100001, (0x04<<24)|0x77F784}, // channel 038
10202+ {42, (0x00<<24)|0x0FF570, (0x01<<24)|0x1AAAA1, (0x04<<24)|0x77F784}, // channel 042
10203+ {46, (0x00<<24)|0x0FF570, (0x01<<24)|0x055551, (0x04<<24)|0x77F784}, // channel 046
10204+ //11 A/H =========
10205+ {36, (0x00<<24)|0x0FF560, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 036
10206+ {40, (0x00<<24)|0x0FF570, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 040
10207+ {44, (0x00<<24)|0x0FF570, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 044
10208+ {48, (0x00<<24)|0x0FF570, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 048
10209+ {52, (0x00<<24)|0x0FF580, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 052
10210+ {56, (0x00<<24)|0x0FF580, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 056
10211+ {60, (0x00<<24)|0x0FF580, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 060
10212+ {64, (0x00<<24)|0x0FF590, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 064
10213+ {100, (0x00<<24)|0x0FF5C0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 100
10214+ {104, (0x00<<24)|0x0FF5C0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 104
10215+ {108, (0x00<<24)|0x0FF5C0, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 108
10216+ {112, (0x00<<24)|0x0FF5D0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 112
10217+ {116, (0x00<<24)|0x0FF5D0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 116
10218+ {120, (0x00<<24)|0x0FF5D0, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 120
10219+ {124, (0x00<<24)|0x0FF5E0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 124
10220+ {128, (0x00<<24)|0x0FF5E0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 128
10221+ {132, (0x00<<24)|0x0FF5E0, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 132
10222+ {136, (0x00<<24)|0x0FF5F0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 136
10223+ {140, (0x00<<24)|0x0FF5F0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 140
10224+ {149, (0x00<<24)|0x0FF600, (0x01<<24)|0x180001, (0x04<<24)|0x77F784}, // channel 149
10225+ {153, (0x00<<24)|0x0FF600, (0x01<<24)|0x02AAA1, (0x04<<24)|0x77F784}, // channel 153
10226+ {157, (0x00<<24)|0x0FF600, (0x01<<24)|0x0D5551, (0x04<<24)|0x77F784}, // channel 157
10227+ {161, (0x00<<24)|0x0FF610, (0x01<<24)|0x180001, (0x04<<24)|0x77F784}, // channel 161
10228+ {165, (0x00<<24)|0x0FF610, (0x01<<24)|0x02AAA1, (0x04<<24)|0x77F784} // channel 165
10229+};
10230+
10231+//; RF Calibration <=== Register 0x0F
10232+//0x0F 0x1ABA8F; start from 2.4Ghz default state
10233+//0x0F 0x9ABA8F; TXDC compensation
10234+//0x0F 0x3ABA8F; RXFIL adjustment
10235+//0x0F 0x1ABA8F; restore 2.4Ghz default state
10236+
10237+//;TXVGA Mapping Table <=== Register 0x0B
10238+u32 al7230_txvga_data[][2] =
10239+{
10240+ {0x08040B, 0}, //TXVGA=0;
10241+ {0x08041B, 1}, //TXVGA=1;
10242+ {0x08042B, 2}, //TXVGA=2;
10243+ {0x08043B, 3}, //TXVGA=3;
10244+ {0x08044B, 4}, //TXVGA=4;
10245+ {0x08045B, 5}, //TXVGA=5;
10246+ {0x08046B, 6}, //TXVGA=6;
10247+ {0x08047B, 7}, //TXVGA=7;
10248+ {0x08048B, 8}, //TXVGA=8;
10249+ {0x08049B, 9}, //TXVGA=9;
10250+ {0x0804AB, 10}, //TXVGA=10;
10251+ {0x0804BB, 11}, //TXVGA=11;
10252+ {0x0804CB, 12}, //TXVGA=12;
10253+ {0x0804DB, 13}, //TXVGA=13;
10254+ {0x0804EB, 14}, //TXVGA=14;
10255+ {0x0804FB, 15}, //TXVGA=15;
10256+ {0x08050B, 16}, //TXVGA=16;
10257+ {0x08051B, 17}, //TXVGA=17;
10258+ {0x08052B, 18}, //TXVGA=18;
10259+ {0x08053B, 19}, //TXVGA=19;
10260+ {0x08054B, 20}, //TXVGA=20;
10261+ {0x08055B, 21}, //TXVGA=21;
10262+ {0x08056B, 22}, //TXVGA=22;
10263+ {0x08057B, 23}, //TXVGA=23;
10264+ {0x08058B, 24}, //TXVGA=24;
10265+ {0x08059B, 25}, //TXVGA=25;
10266+ {0x0805AB, 26}, //TXVGA=26;
10267+ {0x0805BB, 27}, //TXVGA=27;
10268+ {0x0805CB, 28}, //TXVGA=28;
10269+ {0x0805DB, 29}, //TXVGA=29;
10270+ {0x0805EB, 30}, //TXVGA=30;
10271+ {0x0805FB, 31}, //TXVGA=31;
10272+ {0x08060B, 32}, //TXVGA=32;
10273+ {0x08061B, 33}, //TXVGA=33;
10274+ {0x08062B, 34}, //TXVGA=34;
10275+ {0x08063B, 35}, //TXVGA=35;
10276+ {0x08064B, 36}, //TXVGA=36;
10277+ {0x08065B, 37}, //TXVGA=37;
10278+ {0x08066B, 38}, //TXVGA=38;
10279+ {0x08067B, 39}, //TXVGA=39;
10280+ {0x08068B, 40}, //TXVGA=40;
10281+ {0x08069B, 41}, //TXVGA=41;
10282+ {0x0806AB, 42}, //TXVGA=42;
10283+ {0x0806BB, 43}, //TXVGA=43;
10284+ {0x0806CB, 44}, //TXVGA=44;
10285+ {0x0806DB, 45}, //TXVGA=45;
10286+ {0x0806EB, 46}, //TXVGA=46;
10287+ {0x0806FB, 47}, //TXVGA=47;
10288+ {0x08070B, 48}, //TXVGA=48;
10289+ {0x08071B, 49}, //TXVGA=49;
10290+ {0x08072B, 50}, //TXVGA=50;
10291+ {0x08073B, 51}, //TXVGA=51;
10292+ {0x08074B, 52}, //TXVGA=52;
10293+ {0x08075B, 53}, //TXVGA=53;
10294+ {0x08076B, 54}, //TXVGA=54;
10295+ {0x08077B, 55}, //TXVGA=55;
10296+ {0x08078B, 56}, //TXVGA=56;
10297+ {0x08079B, 57}, //TXVGA=57;
10298+ {0x0807AB, 58}, //TXVGA=58;
10299+ {0x0807BB, 59}, //TXVGA=59;
10300+ {0x0807CB, 60}, //TXVGA=60;
10301+ {0x0807DB, 61}, //TXVGA=61;
10302+ {0x0807EB, 62}, //TXVGA=62;
10303+ {0x0807FB, 63}, //TXVGA=63;
10304+};
10305+//--------------------------------
10306+
10307+
10308+//; W89RF242 RFIC SPI programming initial data
10309+//; Winbond WLAN 11g RFIC BB-SPI register -- version FA5976A rev 1.3b
10310+//; Update Date: Ocotber 3, 2005 by PP10 Hsiang-Te Ho
10311+//;
10312+//; Version 1.3b revision items: (Oct. 1, 2005 by HTHo) for FA5976A
10313+u32 w89rf242_rf_data[] =
10314+{
10315+ (0x00<<24)|0xF86100, // 20060721 0xF86100, //; 3E184; MODA (0x00) -- Normal mode ; calibration off
10316+ (0x01<<24)|0xEFFFC2, //; 3BFFF; MODB (0x01) -- turn off RSSI, and other circuits are turned on
10317+ (0x02<<24)|0x102504, //; 04094; FSET (0x02) -- default 20MHz crystal ; Icmp=1.5mA
10318+ (0x03<<24)|0x026286, //; 0098A; FCHN (0x03) -- default CH7, 2442MHz
10319+ (0x04<<24)|0x000208, // 20060612.1.a 0x0002C8, // 20050818 // 20050816 0x000388
10320+ //; 02008; FCAL (0x04) -- XTAL Freq Trim=001000 (socket board#1); FA5976AYG_v1.3C
10321+ (0x05<<24)|0x24C60A, // 20060612.1.a 0x24C58A, // 941003 0x24C48A, // 20050818.2 0x24848A, // 20050818 // 20050816 0x24C48A
10322+ //; 09316; GANA (0x05) -- TX VGA default (TXVGA=0x18(12)) & TXGPK=110 ; FA5976A_1.3D
10323+ (0x06<<24)|0x3432CC, // 941003 0x26C34C, // 20050818 0x06B40C
10324+ //; 0D0CB; GANB (0x06) -- RXDC(DC offset) on; LNA=11; RXVGA=001011(11) ; RXFLSW=11(010001); RXGPK=00; RXGCF=00; -50dBm input
10325+ (0x07<<24)|0x0C68CE, // 20050818.2 0x0C66CE, // 20050818 // 20050816 0x0C68CE
10326+ //; 031A3; FILT (0x07) -- TX/RX filter with auto-tuning; TFLBW=011; RFLBW=100
10327+ (0x08<<24)|0x100010, //; 04000; TCAL (0x08) -- //for LO
10328+ (0x09<<24)|0x004012, // 20060612.1.a 0x6E4012, // 0x004012,
10329+ //; 1B900; RCALA (0x09) -- FASTS=11; HPDE=01 (100nsec); SEHP=1 (select B0 pin=RXHP); RXHP=1 (Turn on RXHP function)(FA5976A_1.3C)
10330+ (0x0A<<24)|0x704014, //; 1C100; RCALB (0x0A)
10331+ (0x0B<<24)|0x18BDD6, // 941003 0x1805D6, // 20050818.2 0x1801D6, // 20050818 // 20050816 0x1805D6
10332+ //; 062F7; IQCAL (0x0B) -- Turn on LO phase tuner=0111 & RX-LO phase = 0111; FA5976A_1.3B (2005/09/29)
10333+ (0x0C<<24)|0x575558, // 20050818.2 0x555558, // 20050818 // 20050816 0x575558
10334+ //; 15D55 ; IBSA (0x0C) -- IFPre =11 ; TC5376A_v1.3A for corner
10335+ (0x0D<<24)|0x55545A, // 20060612.1.a 0x55555A,
10336+ //; 15555 ; IBSB (0x0D)
10337+ (0x0E<<24)|0x5557DC, // 20060612.1.a 0x55555C, // 941003 0x5557DC,
10338+ //; 1555F ; IBSC (0x0E) -- IRLNA & IRLNB (PTAT & Const current)=01/01; FA5976B_1.3F (2005/11/25)
10339+ (0x10<<24)|0x000C20, // 941003 0x000020, // 20050818
10340+ //; 00030 ; TMODA (0x10) -- LNA_gain_step=0011 ; LNA=15/16dB
10341+ (0x11<<24)|0x0C0022, // 941003 0x030022 // 20050818.2 0x030022 // 20050818 // 20050816 0x0C0022
10342+ //; 03000 ; TMODB (0x11) -- Turn ON RX-Q path Test Switch; To improve IQ path group delay (FA5976A_1.3C)
10343+ (0x12<<24)|0x000024 // 20060612.1.a 0x001824 // 941003 add
10344+ //; TMODC (0x12) -- Turn OFF Tempearure sensor
10345+};
10346+
10347+u32 w89rf242_channel_data_24[][2] =
10348+{
10349+ {(0x03<<24)|0x025B06, (0x04<<24)|0x080408}, // channe1 01
10350+ {(0x03<<24)|0x025C46, (0x04<<24)|0x080408}, // channe1 02
10351+ {(0x03<<24)|0x025D86, (0x04<<24)|0x080408}, // channe1 03
10352+ {(0x03<<24)|0x025EC6, (0x04<<24)|0x080408}, // channe1 04
10353+ {(0x03<<24)|0x026006, (0x04<<24)|0x080408}, // channe1 05
10354+ {(0x03<<24)|0x026146, (0x04<<24)|0x080408}, // channe1 06
10355+ {(0x03<<24)|0x026286, (0x04<<24)|0x080408}, // channe1 07
10356+ {(0x03<<24)|0x0263C6, (0x04<<24)|0x080408}, // channe1 08
10357+ {(0x03<<24)|0x026506, (0x04<<24)|0x080408}, // channe1 09
10358+ {(0x03<<24)|0x026646, (0x04<<24)|0x080408}, // channe1 10
10359+ {(0x03<<24)|0x026786, (0x04<<24)|0x080408}, // channe1 11
10360+ {(0x03<<24)|0x0268C6, (0x04<<24)|0x080408}, // channe1 12
10361+ {(0x03<<24)|0x026A06, (0x04<<24)|0x080408}, // channe1 13
10362+ {(0x03<<24)|0x026D06, (0x04<<24)|0x080408} // channe1 14
10363+};
10364+
10365+u32 w89rf242_power_data_24[] = {(0x05<<24)|0x24C48A, (0x05<<24)|0x24C48A, (0x05<<24)|0x24C48A};
10366+
10367+// 20060315.6 Enlarge for new scale
10368+// 20060316.6 20060619.2.a add mapping array
10369+u32 w89rf242_txvga_old_mapping[][2] =
10370+{
10371+ {0, 0} , // New <-> Old
10372+ {1, 1} ,
10373+ {2, 2} ,
10374+ {3, 3} ,
10375+ {4, 4} ,
10376+ {6, 5} ,
10377+ {8, 6 },
10378+ {10, 7 },
10379+ {12, 8 },
10380+ {14, 9 },
10381+ {16, 10},
10382+ {18, 11},
10383+ {20, 12},
10384+ {22, 13},
10385+ {24, 14},
10386+ {26, 15},
10387+ {28, 16},
10388+ {30, 17},
10389+ {32, 18},
10390+ {34, 19},
10391+
10392+
10393+};
10394+
10395+// 20060619.3 modify from Bruce's mail
10396+u32 w89rf242_txvga_data[][5] =
10397+{
10398+ //low gain mode
10399+ { (0x05<<24)|0x24C00A, 0, 0x00292315, 0x0800FEFF, 0x52523131 },// ; min gain
10400+ { (0x05<<24)|0x24C80A, 1, 0x00292315, 0x0800FEFF, 0x52523131 },
10401+ { (0x05<<24)|0x24C04A, 2, 0x00292315, 0x0800FEFF, 0x52523131 },// (default) +14dBm (ANT)
10402+ { (0x05<<24)|0x24C84A, 3, 0x00292315, 0x0800FEFF, 0x52523131 },
10403+
10404+ //TXVGA=0x10
10405+ { (0x05<<24)|0x24C40A, 4, 0x00292315, 0x0800FEFF, 0x60603838 },
10406+ { (0x05<<24)|0x24C40A, 5, 0x00262114, 0x0700FEFF, 0x65653B3B },
10407+
10408+ //TXVGA=0x11
10409+ { (0x05<<24)|0x24C44A, 6, 0x00241F13, 0x0700FFFF, 0x58583333 },
10410+ { (0x05<<24)|0x24C44A, 7, 0x00292315, 0x0800FEFF, 0x5E5E3737 },
10411+
10412+ //TXVGA=0x12
10413+ { (0x05<<24)|0x24C48A, 8, 0x00262114, 0x0700FEFF, 0x53533030 },
10414+ { (0x05<<24)|0x24C48A, 9, 0x00241F13, 0x0700FFFF, 0x59593434 },
10415+
10416+ //TXVGA=0x13
10417+ { (0x05<<24)|0x24C4CA, 10, 0x00292315, 0x0800FEFF, 0x52523030 },
10418+ { (0x05<<24)|0x24C4CA, 11, 0x00262114, 0x0700FEFF, 0x56563232 },
10419+
10420+ //TXVGA=0x14
10421+ { (0x05<<24)|0x24C50A, 12, 0x00292315, 0x0800FEFF, 0x54543131 },
10422+ { (0x05<<24)|0x24C50A, 13, 0x00262114, 0x0700FEFF, 0x58583434 },
10423+
10424+ //TXVGA=0x15
10425+ { (0x05<<24)|0x24C54A, 14, 0x00292315, 0x0800FEFF, 0x54543131 },
10426+ { (0x05<<24)|0x24C54A, 15, 0x00262114, 0x0700FEFF, 0x59593434 },
10427+
10428+ //TXVGA=0x16
10429+ { (0x05<<24)|0x24C58A, 16, 0x00292315, 0x0800FEFF, 0x55553131 },
10430+ { (0x05<<24)|0x24C58A, 17, 0x00292315, 0x0800FEFF, 0x5B5B3535 },
10431+
10432+ //TXVGA=0x17
10433+ { (0x05<<24)|0x24C5CA, 18, 0x00262114, 0x0700FEFF, 0x51512F2F },
10434+ { (0x05<<24)|0x24C5CA, 19, 0x00241F13, 0x0700FFFF, 0x55553131 },
10435+
10436+ //TXVGA=0x18
10437+ { (0x05<<24)|0x24C60A, 20, 0x00292315, 0x0800FEFF, 0x4F4F2E2E },
10438+ { (0x05<<24)|0x24C60A, 21, 0x00262114, 0x0700FEFF, 0x53533030 },
10439+
10440+ //TXVGA=0x19
10441+ { (0x05<<24)|0x24C64A, 22, 0x00292315, 0x0800FEFF, 0x4E4E2D2D },
10442+ { (0x05<<24)|0x24C64A, 23, 0x00262114, 0x0700FEFF, 0x53533030 },
10443+
10444+ //TXVGA=0x1A
10445+ { (0x05<<24)|0x24C68A, 24, 0x00292315, 0x0800FEFF, 0x50502E2E },
10446+ { (0x05<<24)|0x24C68A, 25, 0x00262114, 0x0700FEFF, 0x55553131 },
10447+
10448+ //TXVGA=0x1B
10449+ { (0x05<<24)|0x24C6CA, 26, 0x00262114, 0x0700FEFF, 0x53533030 },
10450+ { (0x05<<24)|0x24C6CA, 27, 0x00292315, 0x0800FEFF, 0x5A5A3434 },
10451+
10452+ //TXVGA=0x1C
10453+ { (0x05<<24)|0x24C70A, 28, 0x00292315, 0x0800FEFF, 0x55553131 },
10454+ { (0x05<<24)|0x24C70A, 29, 0x00292315, 0x0800FEFF, 0x5D5D3636 },
10455+
10456+ //TXVGA=0x1D
10457+ { (0x05<<24)|0x24C74A, 30, 0x00292315, 0x0800FEFF, 0x5F5F3737 },
10458+ { (0x05<<24)|0x24C74A, 31, 0x00262114, 0x0700FEFF, 0x65653B3B },
10459+
10460+ //TXVGA=0x1E
10461+ { (0x05<<24)|0x24C78A, 32, 0x00292315, 0x0800FEFF, 0x66663B3B },
10462+ { (0x05<<24)|0x24C78A, 33, 0x00262114, 0x0700FEFF, 0x70704141 },
10463+
10464+ //TXVGA=0x1F
10465+ { (0x05<<24)|0x24C7CA, 34, 0x00292315, 0x0800FEFF, 0x72724242 }
10466+};
10467+
10468+///////////////////////////////////////////////////////////////////////////////////////////////////
10469+///////////////////////////////////////////////////////////////////////////////////////////////////
10470+///////////////////////////////////////////////////////////////////////////////////////////////////
10471+
10472+
10473+
10474+//=============================================================================================================
10475+// Uxx_ReadEthernetAddress --
10476+//
10477+// Routine Description:
10478+// Reads in the Ethernet address from the IC.
10479+//
10480+// Arguments:
10481+// pHwData - The pHwData structure
10482+//
10483+// Return Value:
10484+//
10485+// The address is stored in EthernetIDAddr.
10486+//=============================================================================================================
10487+void
10488+Uxx_ReadEthernetAddress( phw_data_t pHwData )
10489+{
10490+ u32 ltmp;
10491+
10492+ // Reading Ethernet address from EEPROM and set into hardware due to MAC address maybe change.
10493+ // Only unplug and plug again can make hardware read EEPROM again. 20060727
10494+ Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08000000 ); // Start EEPROM access + Read + address(0x0d)
10495+ Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp );
10496+ *(PUSHORT)pHwData->PermanentMacAddress = cpu_to_le16((u16)ltmp); //20060926 anson's endian
10497+ Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08010000 ); // Start EEPROM access + Read + address(0x0d)
10498+ Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp );
10499+ *(PUSHORT)(pHwData->PermanentMacAddress + 2) = cpu_to_le16((u16)ltmp); //20060926 anson's endian
10500+ Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08020000 ); // Start EEPROM access + Read + address(0x0d)
10501+ Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp );
10502+ *(PUSHORT)(pHwData->PermanentMacAddress + 4) = cpu_to_le16((u16)ltmp); //20060926 anson's endian
10503+ *(PUSHORT)(pHwData->PermanentMacAddress + 6) = 0;
10504+ Wb35Reg_WriteSync( pHwData, 0x03e8, cpu_to_le32(*(PULONG)pHwData->PermanentMacAddress) ); //20060926 anson's endian
10505+ Wb35Reg_WriteSync( pHwData, 0x03ec, cpu_to_le32(*(PULONG)(pHwData->PermanentMacAddress+4)) ); //20060926 anson's endian
10506+}
10507+
10508+
10509+//===============================================================================================================
10510+// CardGetMulticastBit --
10511+// Description:
10512+// For a given multicast address, returns the byte and bit in the card multicast registers that it hashes to.
10513+// Calls CardComputeCrc() to determine the CRC value.
10514+// Arguments:
10515+// Address - the address
10516+// Byte - the byte that it hashes to
10517+// Value - will have a 1 in the relevant bit
10518+// Return Value:
10519+// None.
10520+//==============================================================================================================
10521+void CardGetMulticastBit( u8 Address[ETH_LENGTH_OF_ADDRESS],
10522+ u8 *Byte, u8 *Value )
10523+{
10524+ u32 Crc;
10525+ u32 BitNumber;
10526+
10527+ // First compute the CRC.
10528+ Crc = CardComputeCrc(Address, ETH_LENGTH_OF_ADDRESS);
10529+
10530+ // The computed CRC is bit0~31 from left to right
10531+ //At first we should do right shift 25bits, and read 7bits by using '&', 2^7=128
10532+ BitNumber = (u32) ((Crc >> 26) & 0x3f);
10533+
10534+ *Byte = (u8) (BitNumber >> 3);// 900514 original (BitNumber / 8)
10535+ *Value = (u8) ((u8)1 << (BitNumber % 8));
10536+}
10537+
10538+void Uxx_power_on_procedure( phw_data_t pHwData )
10539+{
10540+ u32 ltmp, loop;
10541+
10542+ if( pHwData->phy_type <= RF_MAXIM_V1 )
10543+ Wb35Reg_WriteSync( pHwData, 0x03d4, 0xffffff38 );
10544+ else
10545+ {
10546+ Wb35Reg_WriteSync( pHwData, 0x03f4, 0xFF5807FF );// 20060721 For NEW IC 0xFF5807FF
10547+
10548+ // 20060511.1 Fix the following 4 steps for Rx of RF 2230 initial fail
10549+ Wb35Reg_WriteSync( pHwData, 0x03d4, 0x80 );// regulator on only
10550+ OS_SLEEP(10000); // Modify 20051221.1.b
10551+ Wb35Reg_WriteSync( pHwData, 0x03d4, 0xb8 );// REG_ON RF_RSTN on, and
10552+ OS_SLEEP(10000); // Modify 20051221.1.b
10553+
10554+ ltmp = 0x4968;
10555+ if( (pHwData->phy_type == RF_WB_242) ||
10556+ (RF_WB_242_1 == pHwData->phy_type) ) // 20060619.5 Add
10557+ ltmp = 0x4468;
10558+ Wb35Reg_WriteSync( pHwData, 0x03d0, ltmp );
10559+
10560+ Wb35Reg_WriteSync( pHwData, 0x03d4, 0xa0 );// PLL_PD REF_PD set to 0
10561+
10562+ OS_SLEEP(20000); // Modify 20051221.1.b
10563+ Wb35Reg_ReadSync( pHwData, 0x03d0, &ltmp );
10564+ loop = 500; // Wait for 5 second 20061101
10565+ while( !(ltmp & 0x20) && loop-- )
10566+ {
10567+ OS_SLEEP(10000); // Modify 20051221.1.b
10568+ if( !Wb35Reg_ReadSync( pHwData, 0x03d0, &ltmp ) )
10569+ break;
10570+ }
10571+
10572+ Wb35Reg_WriteSync( pHwData, 0x03d4, 0xe0 );// MLK_EN
10573+ }
10574+
10575+ Wb35Reg_WriteSync( pHwData, 0x03b0, 1 );// Reset hardware first
10576+ OS_SLEEP(10000); // Add this 20051221.1.b
10577+
10578+ // Set burst write delay
10579+ Wb35Reg_WriteSync( pHwData, 0x03f8, 0x7ff );
10580+}
10581+
10582+void Set_ChanIndep_RfData_al7230_24( phw_data_t pHwData, u32 *pltmp ,char number)
10583+{
10584+ u8 i;
10585+
10586+ for( i=0; i<number; i++ )
10587+ {
10588+ pHwData->phy_para[i] = al7230_rf_data_24[i];
10589+ pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_24[i]&0xffffff);
10590+ }
10591+}
10592+
10593+void Set_ChanIndep_RfData_al7230_50( phw_data_t pHwData, u32 *pltmp, char number)
10594+{
10595+ u8 i;
10596+
10597+ for( i=0; i<number; i++ )
10598+ {
10599+ pHwData->phy_para[i] = al7230_rf_data_50[i];
10600+ pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_50[i]&0xffffff);
10601+ }
10602+}
10603+
10604+
10605+//=============================================================================================================
10606+// RFSynthesizer_initial --
10607+//=============================================================================================================
10608+void
10609+RFSynthesizer_initial(phw_data_t pHwData)
10610+{
10611+ u32 altmp[32];
10612+ PULONG pltmp = altmp;
10613+ u32 ltmp;
10614+ u8 number=0x00; // The number of register vale
10615+ u8 i;
10616+
10617+ //
10618+ // bit[31] SPI Enable.
10619+ // 1=perform synthesizer program operation. This bit will
10620+ // cleared automatically after the operation is completed.
10621+ // bit[30] SPI R/W Control
10622+ // 0=write, 1=read
10623+ // bit[29:24] SPI Data Format Length
10624+ // bit[17:4 ] RF Data bits.
10625+ // bit[3 :0 ] RF address.
10626+ switch( pHwData->phy_type )
10627+ {
10628+ case RF_MAXIM_2825:
10629+ case RF_MAXIM_V1: // 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331)
10630+ number = sizeof(max2825_rf_data)/sizeof(max2825_rf_data[0]);
10631+ for( i=0; i<number; i++ )
10632+ {
10633+ pHwData->phy_para[i] = max2825_rf_data[i];// Backup Rf parameter
10634+ pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2825_rf_data[i], 18);
10635+ }
10636+ break;
10637+
10638+ case RF_MAXIM_2827:
10639+ number = sizeof(max2827_rf_data)/sizeof(max2827_rf_data[0]);
10640+ for( i=0; i<number; i++ )
10641+ {
10642+ pHwData->phy_para[i] = max2827_rf_data[i];
10643+ pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_rf_data[i], 18);
10644+ }
10645+ break;
10646+
10647+ case RF_MAXIM_2828:
10648+ number = sizeof(max2828_rf_data)/sizeof(max2828_rf_data[0]);
10649+ for( i=0; i<number; i++ )
10650+ {
10651+ pHwData->phy_para[i] = max2828_rf_data[i];
10652+ pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_rf_data[i], 18);
10653+ }
10654+ break;
10655+
10656+ case RF_MAXIM_2829:
10657+ number = sizeof(max2829_rf_data)/sizeof(max2829_rf_data[0]);
10658+ for( i=0; i<number; i++ )
10659+ {
10660+ pHwData->phy_para[i] = max2829_rf_data[i];
10661+ pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2829_rf_data[i], 18);
10662+ }
10663+ break;
10664+
10665+ case RF_AIROHA_2230:
10666+ number = sizeof(al2230_rf_data)/sizeof(al2230_rf_data[0]);
10667+ for( i=0; i<number; i++ )
10668+ {
10669+ pHwData->phy_para[i] = al2230_rf_data[i];
10670+ pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_rf_data[i], 20);
10671+ }
10672+ break;
10673+
10674+ case RF_AIROHA_2230S:
10675+ number = sizeof(al2230s_rf_data)/sizeof(al2230s_rf_data[0]);
10676+ for( i=0; i<number; i++ )
10677+ {
10678+ pHwData->phy_para[i] = al2230s_rf_data[i];
10679+ pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230s_rf_data[i], 20);
10680+ }
10681+ break;
10682+
10683+ case RF_AIROHA_7230:
10684+
10685+ //Start to fill RF parameters, PLL_ON should be pulled low.
10686+ Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000000 );
10687+#ifdef _PE_STATE_DUMP_
10688+ WBDEBUG(("* PLL_ON low\n"));
10689+#endif
10690+
10691+ number = sizeof(al7230_rf_data_24)/sizeof(al7230_rf_data_24[0]);
10692+ Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number);
10693+ break;
10694+
10695+ case RF_WB_242:
10696+ case RF_WB_242_1: // 20060619.5 Add
10697+ number = sizeof(w89rf242_rf_data)/sizeof(w89rf242_rf_data[0]);
10698+ for( i=0; i<number; i++ )
10699+ {
10700+ ltmp = w89rf242_rf_data[i];
10701+ if( i == 4 ) // Update the VCO trim from EEPROM
10702+ {
10703+ ltmp &= ~0xff0; // Mask bit4 ~bit11
10704+ ltmp |= pHwData->VCO_trim<<4;
10705+ }
10706+
10707+ pHwData->phy_para[i] = ltmp;
10708+ pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( ltmp, 24);
10709+ }
10710+ break;
10711+ }
10712+
10713+ pHwData->phy_number = number;
10714+
10715+ // The 16 is the maximum capability of hardware. Here use 12
10716+ if( number > 12 ) {
10717+ //Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 12, NO_INCREMENT );
10718+ for( i=0; i<12; i++ ) // For Al2230
10719+ Wb35Reg_WriteSync( pHwData, 0x0864, pltmp[i] );
10720+
10721+ pltmp += 12;
10722+ number -= 12;
10723+ }
10724+
10725+ // Write to register. number must less and equal than 16
10726+ for( i=0; i<number; i++ )
10727+ Wb35Reg_WriteSync( pHwData, 0x864, pltmp[i] );
10728+
10729+ // 20060630.1 Calibration only 1 time
10730+ if( pHwData->CalOneTime )
10731+ return;
10732+ pHwData->CalOneTime = 1;
10733+
10734+ switch( pHwData->phy_type )
10735+ {
10736+ case RF_AIROHA_2230:
10737+
10738+ // 20060511.1 --- Modifying the follow step for Rx issue-----------------
10739+ ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x07<<20)|0xE168E, 20);
10740+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10741+ OS_SLEEP(10000);
10742+ ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_rf_data[7], 20);
10743+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10744+ OS_SLEEP(10000);
10745+
10746+ case RF_AIROHA_2230S: // 20060420 Add this
10747+
10748+ // 20060511.1 --- Modifying the follow step for Rx issue-----------------
10749+ Wb35Reg_WriteSync( pHwData, 0x03d4, 0x80 );// regulator on only
10750+ OS_SLEEP(10000); // Modify 20051221.1.b
10751+
10752+ Wb35Reg_WriteSync( pHwData, 0x03d4, 0xa0 );// PLL_PD REF_PD set to 0
10753+ OS_SLEEP(10000); // Modify 20051221.1.b
10754+
10755+ Wb35Reg_WriteSync( pHwData, 0x03d4, 0xe0 );// MLK_EN
10756+ Wb35Reg_WriteSync( pHwData, 0x03b0, 1 );// Reset hardware first
10757+ OS_SLEEP(10000); // Add this 20051221.1.b
10758+ //------------------------------------------------------------------------
10759+
10760+ // The follow code doesn't use the burst-write mode
10761+ //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01A0); //Raise Initial Setting
10762+ ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01A0, 20);
10763+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10764+
10765+ ltmp = pHwData->Wb35Reg.BB5C & 0xfffff000;
10766+ Wb35Reg_WriteSync( pHwData, 0x105c, ltmp );
10767+ pHwData->Wb35Reg.BB50 |= 0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START);//20060315.1 modify
10768+ Wb35Reg_WriteSync( pHwData, 0x1050, pHwData->Wb35Reg.BB50);
10769+ OS_SLEEP(5000);
10770+
10771+ //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01B0); //Activate Filter Cal.
10772+ ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01B0, 20);
10773+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10774+ OS_SLEEP(5000);
10775+
10776+ //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01e0); //Activate TX DCC
10777+ ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01E0, 20);
10778+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10779+ OS_SLEEP(5000);
10780+
10781+ //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01A0); //Resotre Initial Setting
10782+ ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01A0, 20);
10783+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10784+
10785+// //Force TXI(Q)P(N) to normal control
10786+ Wb35Reg_WriteSync( pHwData, 0x105c, pHwData->Wb35Reg.BB5C );
10787+ pHwData->Wb35Reg.BB50 &= ~0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START);
10788+ Wb35Reg_WriteSync( pHwData, 0x1050, pHwData->Wb35Reg.BB50);
10789+ break;
10790+
10791+ case RF_AIROHA_7230:
10792+
10793+ //RF parameters have filled completely, PLL_ON should be
10794+ //pulled high
10795+ Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000080 );
10796+ #ifdef _PE_STATE_DUMP_
10797+ WBDEBUG(("* PLL_ON high\n"));
10798+ #endif
10799+
10800+ //2.4GHz
10801+ //ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x1ABA8F;
10802+ //Wb35Reg_WriteSync pHwData, 0x0864, ltmp );
10803+ //OS_SLEEP(1000); // Sleep 1 ms
10804+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F;
10805+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10806+ OS_SLEEP(5000);
10807+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F;
10808+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10809+ OS_SLEEP(5000);
10810+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x1ABA8F;
10811+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10812+ OS_SLEEP(5000);
10813+
10814+ //5GHz
10815+ Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000000 );
10816+ #ifdef _PE_STATE_DUMP_
10817+ WBDEBUG(("* PLL_ON low\n"));
10818+ #endif
10819+
10820+ number = sizeof(al7230_rf_data_50)/sizeof(al7230_rf_data_50[0]);
10821+ Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number);
10822+ // Write to register. number must less and equal than 16
10823+ for( i=0; i<number; i++ )
10824+ Wb35Reg_WriteSync( pHwData, 0x0864, pltmp[i] );
10825+ OS_SLEEP(5000);
10826+
10827+ Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000080 );
10828+ #ifdef _PE_STATE_DUMP_
10829+ WBDEBUG(("* PLL_ON high\n"));
10830+ #endif
10831+
10832+ //ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x12BACF;
10833+ //Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10834+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F;
10835+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10836+ OS_SLEEP(5000);
10837+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F;
10838+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10839+ OS_SLEEP(5000);
10840+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x12BACF;
10841+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10842+ OS_SLEEP(5000);
10843+
10844+ //Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000080 );
10845+ //WBDEBUG(("* PLL_ON high\n"));
10846+ break;
10847+
10848+ case RF_WB_242:
10849+ case RF_WB_242_1: // 20060619.5 Add
10850+
10851+ //
10852+ // ; Version 1.3B revision items: for FA5976A , October 3, 2005 by HTHo
10853+ //
10854+ ltmp = pHwData->Wb35Reg.BB5C & 0xfffff000;
10855+ Wb35Reg_WriteSync( pHwData, 0x105c, ltmp );
10856+ Wb35Reg_WriteSync( pHwData, 0x1058, 0 );
10857+ pHwData->Wb35Reg.BB50 |= 0x3;//(MASK_IQCAL_MODE|MASK_CALIB_START);//20060630
10858+ Wb35Reg_WriteSync( pHwData, 0x1050, pHwData->Wb35Reg.BB50);
10859+
10860+ //----- Calibration (1). VCO frequency calibration
10861+ //Calibration (1a.0). Synthesizer reset (HTHo corrected 2005/05/10)
10862+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x0F<<24) | 0x00101E, 24);
10863+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10864+ OS_SLEEP( 5000 ); // Sleep 5ms
10865+ //Calibration (1a). VCO frequency calibration mode ; waiting 2msec VCO calibration time
10866+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFE69c0, 24);
10867+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10868+ OS_SLEEP( 2000 ); // Sleep 2ms
10869+
10870+ //----- Calibration (2). TX baseband Gm-C filter auto-tuning
10871+ //Calibration (2a). turn off ENCAL signal
10872+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xF8EBC0, 24);
10873+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10874+ //Calibration (2b.0). TX filter auto-tuning BW: TFLBW=101 (TC5376A default)
10875+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x07<<24) | 0x0C68CE, 24);
10876+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10877+ //Calibration (2b). send TX reset signal (HTHo corrected May 10, 2005)
10878+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x0F<<24) | 0x00201E, 24);
10879+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10880+ //Calibration (2c). turn-on TX Gm-C filter auto-tuning
10881+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFCEBC0, 24);
10882+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10883+ OS_SLEEP( 150 ); // Sleep 150 us
10884+ //turn off ENCAL signal
10885+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xF8EBC0, 24);
10886+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10887+
10888+ //----- Calibration (3). RX baseband Gm-C filter auto-tuning
10889+ //Calibration (3a). turn off ENCAL signal
10890+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
10891+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10892+ //Calibration (3b.0). RX filter auto-tuning BW: RFLBW=100 (TC5376A+corner default; July 26, 2005)
10893+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x07<<24) | 0x0C68CE, 24);
10894+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10895+ //Calibration (3b). send RX reset signal (HTHo corrected May 10, 2005)
10896+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x0F<<24) | 0x00401E, 24);
10897+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10898+ //Calibration (3c). turn-on RX Gm-C filter auto-tuning
10899+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFEEDC0, 24);
10900+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10901+ OS_SLEEP( 150 ); // Sleep 150 us
10902+ //Calibration (3e). turn off ENCAL signal
10903+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
10904+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10905+
10906+ //----- Calibration (4). TX LO leakage calibration
10907+ //Calibration (4a). TX LO leakage calibration
10908+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFD6BC0, 24);
10909+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10910+ OS_SLEEP( 150 ); // Sleep 150 us
10911+
10912+ //----- Calibration (5). RX DC offset calibration
10913+ //Calibration (5a). turn off ENCAL signal and set to RX SW DC caliration mode
10914+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
10915+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10916+ //Calibration (5b). turn off AGC servo-loop & RSSI
10917+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x01<<24) | 0xEBFFC2, 24);
10918+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10919+
10920+ //; for LNA=11 --------
10921+ //Calibration (5c-h). RX DC offset current bias ON; & LNA=11; RXVGA=111111
10922+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x343FCC, 24);
10923+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10924+ //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time
10925+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24);
10926+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10927+ OS_SLEEP(2000); // Sleep 2ms
10928+ //Calibration (5f). turn off ENCAL signal
10929+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
10930+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10931+
10932+ //; for LNA=10 --------
10933+ //Calibration (5c-m). RX DC offset current bias ON; & LNA=10; RXVGA=111111
10934+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x342FCC, 24);
10935+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10936+ //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time
10937+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24);
10938+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10939+ OS_SLEEP(2000); // Sleep 2ms
10940+ //Calibration (5f). turn off ENCAL signal
10941+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
10942+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10943+
10944+ //; for LNA=01 --------
10945+ //Calibration (5c-m). RX DC offset current bias ON; & LNA=01; RXVGA=111111
10946+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x341FCC, 24);
10947+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10948+ //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time
10949+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24);
10950+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10951+ OS_SLEEP(2000); // Sleep 2ms
10952+ //Calibration (5f). turn off ENCAL signal
10953+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
10954+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10955+
10956+ //; for LNA=00 --------
10957+ //Calibration (5c-l). RX DC offset current bias ON; & LNA=00; RXVGA=111111
10958+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x340FCC, 24);
10959+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10960+ //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time
10961+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24);
10962+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10963+ OS_SLEEP(2000); // Sleep 2ms
10964+ //Calibration (5f). turn off ENCAL signal
10965+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
10966+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10967+ //Calibration (5g). turn on AGC servo-loop
10968+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x01<<24) | 0xEFFFC2, 24);
10969+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10970+
10971+ //; ----- Calibration (7). Switch RF chip to normal mode
10972+ //0x00 0xF86100 ; 3E184 ; Switch RF chip to normal mode
10973+// OS_SLEEP(10000); // @@ 20060721
10974+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xF86100, 24);
10975+ Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
10976+ OS_SLEEP(5000); // Sleep 5 ms
10977+
10978+// //write back
10979+// Wb35Reg_WriteSync( pHwData, 0x105c, pHwData->Wb35Reg.BB5C );
10980+// pHwData->Wb35Reg.BB50 &= ~0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START); // 20060315.1 fix
10981+// Wb35Reg_WriteSync( pHwData, 0x1050, pHwData->Wb35Reg.BB50);
10982+// OS_SLEEP(1000); // Sleep 1 ms
10983+ break;
10984+ }
10985+}
10986+
10987+void BBProcessor_AL7230_2400( phw_data_t pHwData)
10988+{
10989+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
10990+ u32 pltmp[12];
10991+
10992+ pltmp[0] = 0x16A8337A; // 0x16a5215f; // 0x1000 AGC_Ctrl1
10993+ pltmp[1] = 0x9AFF9AA6; // 0x9aff9ca6; // 0x1004 AGC_Ctrl2
10994+ pltmp[2] = 0x55D00A04; // 0x55d00a04; // 0x1008 AGC_Ctrl3
10995+ pltmp[3] = 0xFFF72031; // 0xFfFf2138; // 0x100c AGC_Ctrl4
10996+ pWb35Reg->BB0C = 0xFFF72031;
10997+ pltmp[4] = 0x0FacDCC5; // 0x1010 AGC_Ctrl5 // 20050927 0x0FacDCB7
10998+ pltmp[5] = 0x00CAA333; // 0x00eaa333; // 0x1014 AGC_Ctrl6
10999+ pltmp[6] = 0xF2211111; // 0x11111111; // 0x1018 AGC_Ctrl7
11000+ pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
11001+ pltmp[8] = 0x06443440; // 0x1020 AGC_Ctrl9
11002+ pltmp[9] = 0xA8002A79; // 0xa9002A79; // 0x1024 AGC_Ctrl10
11003+ pltmp[10] = 0x40000528; // 20050927 0x40000228
11004+ pltmp[11] = 0x232D7F30; // 0x23457f30;// 0x102c A_ACQ_Ctrl
11005+ pWb35Reg->BB2C = 0x232D7F30;
11006+ Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
11007+
11008+ pltmp[0] = 0x00002c54; // 0x1030 B_ACQ_Ctrl
11009+ pWb35Reg->BB30 = 0x00002c54;
11010+ pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
11011+ pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl
11012+ pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
11013+ pWb35Reg->BB3C = 0x00000000;
11014+ pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
11015+ pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
11016+ pltmp[6] = 0x00332C1B; // 0x00453B24; // 0x1048 11b TX RC filter
11017+ pltmp[7] = 0x0A00FEFF; // 0x0E00FEFF; // 0x104c 11b TX RC filter
11018+ pltmp[8] = 0x2B106208; // 0x1050 MODE_Ctrl
11019+ pWb35Reg->BB50 = 0x2B106208;
11020+ pltmp[9] = 0; // 0x1054
11021+ pWb35Reg->BB54 = 0x00000000;
11022+ pltmp[10] = 0x52524242; // 0x64645252; // 0x1058 IQ_Alpha
11023+ pWb35Reg->BB58 = 0x52524242;
11024+ pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
11025+ Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
11026+
11027+}
11028+
11029+void BBProcessor_AL7230_5000( phw_data_t pHwData)
11030+{
11031+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
11032+ u32 pltmp[12];
11033+
11034+ pltmp[0] = 0x16AA6678; // 0x1000 AGC_Ctrl1
11035+ pltmp[1] = 0x9AFFA0B2; // 0x1004 AGC_Ctrl2
11036+ pltmp[2] = 0x55D00A04; // 0x1008 AGC_Ctrl3
11037+ pltmp[3] = 0xEFFF233E; // 0x100c AGC_Ctrl4
11038+ pWb35Reg->BB0C = 0xEFFF233E;
11039+ pltmp[4] = 0x0FacDCC5; // 0x1010 AGC_Ctrl5 // 20050927 0x0FacDCB7
11040+ pltmp[5] = 0x00CAA333; // 0x1014 AGC_Ctrl6
11041+ pltmp[6] = 0xF2432111; // 0x1018 AGC_Ctrl7
11042+ pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
11043+ pltmp[8] = 0x05C43440; // 0x1020 AGC_Ctrl9
11044+ pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
11045+ pltmp[10] = 0x40000528; // 20050927 0x40000228
11046+ pltmp[11] = 0x232FDF30;// 0x102c A_ACQ_Ctrl
11047+ pWb35Reg->BB2C = 0x232FDF30;
11048+ Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
11049+
11050+ pltmp[0] = 0x80002C7C; // 0x1030 B_ACQ_Ctrl
11051+ pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
11052+ pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl
11053+ pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
11054+ pWb35Reg->BB3C = 0x00000000;
11055+ pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
11056+ pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
11057+ pltmp[6] = 0x00332C1B; // 0x1048 11b TX RC filter
11058+ pltmp[7] = 0x0A00FEFF; // 0x104c 11b TX RC filter
11059+ pltmp[8] = 0x2B107208; // 0x1050 MODE_Ctrl
11060+ pWb35Reg->BB50 = 0x2B107208;
11061+ pltmp[9] = 0; // 0x1054
11062+ pWb35Reg->BB54 = 0x00000000;
11063+ pltmp[10] = 0x52524242; // 0x1058 IQ_Alpha
11064+ pWb35Reg->BB58 = 0x52524242;
11065+ pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
11066+ Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
11067+
11068+}
11069+
11070+//=============================================================================================================
11071+// BBProcessorPowerupInit --
11072+//
11073+// Description:
11074+// Initialize the Baseband processor.
11075+//
11076+// Arguments:
11077+// pHwData - Handle of the USB Device.
11078+//
11079+// Return values:
11080+// None.
11081+//=============================================================================================================
11082+void
11083+BBProcessor_initial( phw_data_t pHwData )
11084+{
11085+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
11086+ u32 i, pltmp[12];
11087+
11088+ switch( pHwData->phy_type )
11089+ {
11090+ case RF_MAXIM_V1: // Initializng the Winbond 2nd BB(with Phy board (v1) + Maxim 331)
11091+
11092+ pltmp[0] = 0x16F47E77; // 0x1000 AGC_Ctrl1
11093+ pltmp[1] = 0x9AFFAEA4; // 0x1004 AGC_Ctrl2
11094+ pltmp[2] = 0x55D00A04; // 0x1008 AGC_Ctrl3
11095+ pltmp[3] = 0xEFFF1A34; // 0x100c AGC_Ctrl4
11096+ pWb35Reg->BB0C = 0xEFFF1A34;
11097+ pltmp[4] = 0x0FABE0B7; // 0x1010 AGC_Ctrl5
11098+ pltmp[5] = 0x00CAA332; // 0x1014 AGC_Ctrl6
11099+ pltmp[6] = 0xF6632111; // 0x1018 AGC_Ctrl7
11100+ pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
11101+ pltmp[8] = 0x04CC3640; // 0x1020 AGC_Ctrl9
11102+ pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
11103+ pltmp[10] = (pHwData->phy_type==3) ? 0x40000a28 : 0x40000228; // 0x1028 MAXIM_331(b31=0) + WBRF_V1(b11=1) : MAXIM_331(b31=0) + WBRF_V2(b11=0)
11104+ pltmp[11] = 0x232FDF30; // 0x102c A_ACQ_Ctrl
11105+ pWb35Reg->BB2C = 0x232FDF30; //Modify for 33's 1.0.95.xxx version, antenna 1
11106+ Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
11107+
11108+ pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
11109+ pWb35Reg->BB30 = 0x00002C54;
11110+ pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
11111+ pltmp[2] = 0x5B6C8769; // 0x1038 B_TXRX_Ctrl
11112+ pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
11113+ pWb35Reg->BB3C = 0x00000000;
11114+ pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
11115+ pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
11116+ pltmp[6] = 0x00453B24; // 0x1048 11b TX RC filter
11117+ pltmp[7] = 0x0E00FEFF; // 0x104c 11b TX RC filter
11118+ pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl
11119+ pWb35Reg->BB50 = 0x27106208;
11120+ pltmp[9] = 0; // 0x1054
11121+ pWb35Reg->BB54 = 0x00000000;
11122+ pltmp[10] = 0x64646464; // 0x1058 IQ_Alpha
11123+ pWb35Reg->BB58 = 0x64646464;
11124+ pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
11125+ Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
11126+
11127+ Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
11128+ break;
11129+
11130+ //------------------------------------------------------------------
11131+ //[20040722 WK]
11132+ //Only for baseband version 2
11133+// case RF_MAXIM_317:
11134+ case RF_MAXIM_2825:
11135+ case RF_MAXIM_2827:
11136+ case RF_MAXIM_2828:
11137+
11138+ pltmp[0] = 0x16b47e77; // 0x1000 AGC_Ctrl1
11139+ pltmp[1] = 0x9affaea4; // 0x1004 AGC_Ctrl2
11140+ pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3
11141+ pltmp[3] = 0xefff1a34; // 0x100c AGC_Ctrl4
11142+ pWb35Reg->BB0C = 0xefff1a34;
11143+ pltmp[4] = 0x0fabe0b7; // 0x1010 AGC_Ctrl5
11144+ pltmp[5] = 0x00caa332; // 0x1014 AGC_Ctrl6
11145+ pltmp[6] = 0xf6632111; // 0x1018 AGC_Ctrl7
11146+ pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
11147+ pltmp[8] = 0x04CC3640; // 0x1020 AGC_Ctrl9
11148+ pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
11149+ pltmp[10] = 0x40000528; // 0x40000128; Modify for 33's 1.0.95
11150+ pltmp[11] = 0x232fdf30; // 0x102c A_ACQ_Ctrl
11151+ pWb35Reg->BB2C = 0x232fdf30; //Modify for 33's 1.0.95.xxx version, antenna 1
11152+ Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
11153+
11154+ pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
11155+ pWb35Reg->BB30 = 0x00002C54;
11156+ pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
11157+ pltmp[2] = 0x5B6C8769; // 0x1038 B_TXRX_Ctrl
11158+ pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
11159+ pWb35Reg->BB3C = 0x00000000;
11160+ pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
11161+ pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
11162+ pltmp[6] = 0x00453B24; // 0x1048 11b TX RC filter
11163+ pltmp[7] = 0x0D00FDFF; // 0x104c 11b TX RC filter
11164+ pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl
11165+ pWb35Reg->BB50 = 0x27106208;
11166+ pltmp[9] = 0; // 0x1054
11167+ pWb35Reg->BB54 = 0x00000000;
11168+ pltmp[10] = 0x64646464; // 0x1058 IQ_Alpha
11169+ pWb35Reg->BB58 = 0x64646464;
11170+ pltmp[11] = 0xAA28C000; // 0x105c DC_Cancel
11171+ Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
11172+
11173+ Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
11174+ break;
11175+
11176+ case RF_MAXIM_2829:
11177+
11178+ pltmp[0] = 0x16b47e77; // 0x1000 AGC_Ctrl1
11179+ pltmp[1] = 0x9affaea4; // 0x1004 AGC_Ctrl2
11180+ pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3
11181+ pltmp[3] = 0xf4ff1632; // 0xefff1a34; // 0x100c AGC_Ctrl4 Modify for 33's 1.0.95
11182+ pWb35Reg->BB0C = 0xf4ff1632; // 0xefff1a34; Modify for 33's 1.0.95
11183+ pltmp[4] = 0x0fabe0b7; // 0x1010 AGC_Ctrl5
11184+ pltmp[5] = 0x00caa332; // 0x1014 AGC_Ctrl6
11185+ pltmp[6] = 0xf8632112; // 0xf6632111; // 0x1018 AGC_Ctrl7 Modify for 33's 1.0.95
11186+ pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
11187+ pltmp[8] = 0x04CC3640; // 0x1020 AGC_Ctrl9
11188+ pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
11189+ pltmp[10] = 0x40000528; // 0x40000128; modify for 33's 1.0.95
11190+ pltmp[11] = 0x232fdf30; // 0x102c A_ACQ_Ctrl
11191+ pWb35Reg->BB2C = 0x232fdf30; //Modify for 33's 1.0.95.xxx version, antenna 1
11192+ Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
11193+
11194+ pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
11195+ pWb35Reg->BB30 = 0x00002C54;
11196+ pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
11197+ pltmp[2] = 0x5b2c8769; // 0x5B6C8769; // 0x1038 B_TXRX_Ctrl Modify for 33's 1.0.95
11198+ pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
11199+ pWb35Reg->BB3C = 0x00000000;
11200+ pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
11201+ pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
11202+ pltmp[6] = 0x002c2617; // 0x00453B24; // 0x1048 11b TX RC filter Modify for 33's 1.0.95
11203+ pltmp[7] = 0x0800feff; // 0x0D00FDFF; // 0x104c 11b TX RC filter Modify for 33's 1.0.95
11204+ pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl
11205+ pWb35Reg->BB50 = 0x27106208;
11206+ pltmp[9] = 0; // 0x1054
11207+ pWb35Reg->BB54 = 0x00000000;
11208+ pltmp[10] = 0x64644a4a; // 0x64646464; // 0x1058 IQ_Alpha Modify for 33's 1.0.95
11209+ pWb35Reg->BB58 = 0x64646464;
11210+ pltmp[11] = 0xAA28C000; // 0x105c DC_Cancel
11211+ Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
11212+
11213+ Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
11214+ break;
11215+
11216+ case RF_AIROHA_2230:
11217+
11218+ pltmp[0] = 0X16764A77; // 0x1000 AGC_Ctrl1 //0x16765A77
11219+ pltmp[1] = 0x9affafb2; // 0x1004 AGC_Ctrl2
11220+ pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3
11221+ pltmp[3] = 0xFFFd203c; // 0xFFFb203a; // 0x100c AGC_Ctrl4 Modify for 33's 1.0.95.xxx version
11222+ pWb35Reg->BB0C = 0xFFFd203c;
11223+ pltmp[4] = 0X0FBFDCc5; // 0X0FBFDCA0; // 0x1010 AGC_Ctrl5 //0x0FB2E0B7 Modify for 33's 1.0.95.xxx version
11224+ pltmp[5] = 0x00caa332; // 0x00caa333; // 0x1014 AGC_Ctrl6 Modify for 33's 1.0.95.xxx version
11225+ pltmp[6] = 0XF6632111; // 0XF1632112; // 0x1018 AGC_Ctrl7 //0xf6632112 Modify for 33's 1.0.95.xxx version
11226+ pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
11227+ pltmp[8] = 0x04C43640; // 0x1020 AGC_Ctrl9
11228+ pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
11229+ pltmp[10] = 0X40000528; //0x40000228
11230+ pltmp[11] = 0x232dfF30; // 0x232A9F30; // 0x102c A_ACQ_Ctrl //0x232a9730
11231+ pWb35Reg->BB2C = 0x232dfF30; //Modify for 33's 1.0.95.xxx version, antenna 1
11232+ Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
11233+
11234+ pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
11235+ pWb35Reg->BB30 = 0x00002C54;
11236+ pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
11237+ pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl //0x5B6C8769
11238+ pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
11239+ pWb35Reg->BB3C = 0x00000000;
11240+ pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
11241+ pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
11242+ pltmp[6] = BB48_DEFAULT_AL2230_11G; // 0x1048 11b TX RC filter 20060613.2
11243+ pWb35Reg->BB48 = BB48_DEFAULT_AL2230_11G; // 20051221 ch14 20060613.2
11244+ pltmp[7] = BB4C_DEFAULT_AL2230_11G; // 0x104c 11b TX RC filter 20060613.2
11245+ pWb35Reg->BB4C = BB4C_DEFAULT_AL2230_11G; // 20060613.1 20060613.2
11246+ pltmp[8] = 0x27106200; // 0x1050 MODE_Ctrl
11247+ pWb35Reg->BB50 = 0x27106200;
11248+ pltmp[9] = 0; // 0x1054
11249+ pWb35Reg->BB54 = 0x00000000;
11250+ pltmp[10] = 0x52524242; // 0x1058 IQ_Alpha
11251+ pWb35Reg->BB58 = 0x52524242;
11252+ pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
11253+ Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
11254+
11255+ Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
11256+ break;
11257+
11258+ case RF_AIROHA_2230S: // 20060420 Add this
11259+
11260+ pltmp[0] = 0X16764A77; // 0x1000 AGC_Ctrl1 //0x16765A77
11261+ pltmp[1] = 0x9affafb2; // 0x1004 AGC_Ctrl2
11262+ pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3
11263+ pltmp[3] = 0xFFFd203c; // 0xFFFb203a; // 0x100c AGC_Ctrl4 Modify for 33's 1.0.95.xxx version
11264+ pWb35Reg->BB0C = 0xFFFd203c;
11265+ pltmp[4] = 0X0FBFDCc5; // 0X0FBFDCA0; // 0x1010 AGC_Ctrl5 //0x0FB2E0B7 Modify for 33's 1.0.95.xxx version
11266+ pltmp[5] = 0x00caa332; // 0x00caa333; // 0x1014 AGC_Ctrl6 Modify for 33's 1.0.95.xxx version
11267+ pltmp[6] = 0XF6632111; // 0XF1632112; // 0x1018 AGC_Ctrl7 //0xf6632112 Modify for 33's 1.0.95.xxx version
11268+ pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
11269+ pltmp[8] = 0x04C43640; // 0x1020 AGC_Ctrl9
11270+ pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
11271+ pltmp[10] = 0X40000528; //0x40000228
11272+ pltmp[11] = 0x232dfF30; // 0x232A9F30; // 0x102c A_ACQ_Ctrl //0x232a9730
11273+ pWb35Reg->BB2C = 0x232dfF30; //Modify for 33's 1.0.95.xxx version, antenna 1
11274+ Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
11275+
11276+ pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
11277+ pWb35Reg->BB30 = 0x00002C54;
11278+ pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
11279+ pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl //0x5B6C8769
11280+ pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
11281+ pWb35Reg->BB3C = 0x00000000;
11282+ pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
11283+ pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
11284+ pltmp[6] = BB48_DEFAULT_AL2230_11G; // 0x1048 11b TX RC filter 20060613.2
11285+ pWb35Reg->BB48 = BB48_DEFAULT_AL2230_11G; // 20051221 ch14 20060613.2
11286+ pltmp[7] = BB4C_DEFAULT_AL2230_11G; // 0x104c 11b TX RC filter 20060613.2
11287+ pWb35Reg->BB4C = BB4C_DEFAULT_AL2230_11G; // 20060613.1
11288+ pltmp[8] = 0x27106200; // 0x1050 MODE_Ctrl
11289+ pWb35Reg->BB50 = 0x27106200;
11290+ pltmp[9] = 0; // 0x1054
11291+ pWb35Reg->BB54 = 0x00000000;
11292+ pltmp[10] = 0x52523232; // 20060419 0x52524242; // 0x1058 IQ_Alpha
11293+ pWb35Reg->BB58 = 0x52523232; // 20060419 0x52524242;
11294+ pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
11295+ Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
11296+
11297+ Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
11298+ break;
11299+
11300+ case RF_AIROHA_7230:
11301+/*
11302+ pltmp[0] = 0x16a84a77; // 0x1000 AGC_Ctrl1
11303+ pltmp[1] = 0x9affafb2; // 0x1004 AGC_Ctrl2
11304+ pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3
11305+ pltmp[3] = 0xFFFb203a; // 0x100c AGC_Ctrl4
11306+ pWb35Reg->BB0c = 0xFFFb203a;
11307+ pltmp[4] = 0x0FBFDCB7; // 0x1010 AGC_Ctrl5
11308+ pltmp[5] = 0x00caa333; // 0x1014 AGC_Ctrl6
11309+ pltmp[6] = 0xf6632112; // 0x1018 AGC_Ctrl7
11310+ pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
11311+ pltmp[8] = 0x04C43640; // 0x1020 AGC_Ctrl9
11312+ pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
11313+ pltmp[10] = 0x40000228;
11314+ pltmp[11] = 0x232A9F30;// 0x102c A_ACQ_Ctrl
11315+ pWb35Reg->BB2c = 0x232A9F30;
11316+ Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
11317+
11318+ pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
11319+ pWb35Reg->BB30 = 0x00002C54;
11320+ pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
11321+ pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl
11322+ pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
11323+ pWb35Reg->BB3c = 0x00000000;
11324+ pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
11325+ pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
11326+ pltmp[6] = 0x00453B24; // 0x1048 11b TX RC filter
11327+ pltmp[7] = 0x0E00FEFF; // 0x104c 11b TX RC filter
11328+ pltmp[8] = 0x27106200; // 0x1050 MODE_Ctrl
11329+ pWb35Reg->BB50 = 0x27106200;
11330+ pltmp[9] = 0; // 0x1054
11331+ pWb35Reg->BB54 = 0x00000000;
11332+ pltmp[10] = 0x64645252; // 0x1058 IQ_Alpha
11333+ pWb35Reg->BB58 = 0x64645252;
11334+ pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
11335+ Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
11336+*/
11337+ BBProcessor_AL7230_2400( pHwData );
11338+
11339+ Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
11340+ break;
11341+
11342+ case RF_WB_242:
11343+ case RF_WB_242_1: // 20060619.5 Add
11344+
11345+ pltmp[0] = 0x16A8525D; // 0x1000 AGC_Ctrl1
11346+ pltmp[1] = 0x9AFF9ABA; // 0x1004 AGC_Ctrl2
11347+ pltmp[2] = 0x55D00A04; // 0x1008 AGC_Ctrl3
11348+ pltmp[3] = 0xEEE91C32; // 0x100c AGC_Ctrl4
11349+ pWb35Reg->BB0C = 0xEEE91C32;
11350+ pltmp[4] = 0x0FACDCC5; // 0x1010 AGC_Ctrl5
11351+ pltmp[5] = 0x000AA344; // 0x1014 AGC_Ctrl6
11352+ pltmp[6] = 0x22222221; // 0x1018 AGC_Ctrl7
11353+ pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
11354+ pltmp[8] = 0x04CC3440; // 20051018 0x03CB3440; // 0x1020 AGC_Ctrl9 20051014 0x03C33440
11355+ pltmp[9] = 0xA9002A79; // 0x1024 AGC_Ctrl10
11356+ pltmp[10] = 0x40000528; // 0x1028
11357+ pltmp[11] = 0x23457F30; // 0x102c A_ACQ_Ctrl
11358+ pWb35Reg->BB2C = 0x23457F30;
11359+ Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
11360+
11361+ pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
11362+ pWb35Reg->BB30 = 0x00002C54;
11363+ pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
11364+ pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl
11365+ pltmp[3] = pHwData->BB3c_cal; // 0x103c 11a TX LS filter
11366+ pWb35Reg->BB3C = pHwData->BB3c_cal;
11367+ pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
11368+ pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
11369+ pltmp[6] = BB48_DEFAULT_WB242_11G; // 0x1048 11b TX RC filter 20060613.2
11370+ pWb35Reg->BB48 = BB48_DEFAULT_WB242_11G; // 20060613.1 20060613.2
11371+ pltmp[7] = BB4C_DEFAULT_WB242_11G; // 0x104c 11b TX RC filter 20060613.2
11372+ pWb35Reg->BB4C = BB4C_DEFAULT_WB242_11G; // 20060613.1 20060613.2
11373+ pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl
11374+ pWb35Reg->BB50 = 0x27106208;
11375+ pltmp[9] = pHwData->BB54_cal; // 0x1054
11376+ pWb35Reg->BB54 = pHwData->BB54_cal;
11377+ pltmp[10] = 0x52523131; // 0x1058 IQ_Alpha
11378+ pWb35Reg->BB58 = 0x52523131;
11379+ pltmp[11] = 0xAA0AC000; // 20060825 0xAA2AC000; // 0x105c DC_Cancel
11380+ Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
11381+
11382+ Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
11383+ break;
11384+ }
11385+
11386+ // Fill the LNA table
11387+ pWb35Reg->LNAValue[0] = (u8)(pWb35Reg->BB0C & 0xff);
11388+ pWb35Reg->LNAValue[1] = 0;
11389+ pWb35Reg->LNAValue[2] = (u8)((pWb35Reg->BB0C & 0xff00)>>8);
11390+ pWb35Reg->LNAValue[3] = 0;
11391+
11392+ // Fill SQ3 table
11393+ for( i=0; i<MAX_SQ3_FILTER_SIZE; i++ )
11394+ pWb35Reg->SQ3_filter[i] = 0x2f; // half of Bit 0 ~ 6
11395+}
11396+
11397+void set_tx_power_per_channel_max2829( phw_data_t pHwData, ChanInfo Channel)
11398+{
11399+ RFSynthesizer_SetPowerIndex( pHwData, 100 ); // 20060620.1 Modify
11400+}
11401+
11402+void set_tx_power_per_channel_al2230( phw_data_t pHwData, ChanInfo Channel )
11403+{
11404+ u8 index = 100;
11405+
11406+ if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff) // 20060620.1 Add
11407+ index = pHwData->TxVgaFor24[Channel.ChanNo - 1];
11408+
11409+ RFSynthesizer_SetPowerIndex( pHwData, index );
11410+}
11411+
11412+void set_tx_power_per_channel_al7230( phw_data_t pHwData, ChanInfo Channel)
11413+{
11414+ u8 i, index = 100;
11415+
11416+ switch ( Channel.band )
11417+ {
11418+ case BAND_TYPE_DSSS:
11419+ case BAND_TYPE_OFDM_24:
11420+ {
11421+ if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff)
11422+ index = pHwData->TxVgaFor24[Channel.ChanNo - 1];
11423+ }
11424+ break;
11425+ case BAND_TYPE_OFDM_5:
11426+ {
11427+ for (i =0; i<35; i++)
11428+ {
11429+ if (Channel.ChanNo == pHwData->TxVgaFor50[i].ChanNo)
11430+ {
11431+ if (pHwData->TxVgaFor50[i].TxVgaValue != 0xff)
11432+ index = pHwData->TxVgaFor50[i].TxVgaValue;
11433+ break;
11434+ }
11435+ }
11436+ }
11437+ break;
11438+ }
11439+ RFSynthesizer_SetPowerIndex( pHwData, index );
11440+}
11441+
11442+void set_tx_power_per_channel_wb242( phw_data_t pHwData, ChanInfo Channel)
11443+{
11444+ u8 index = 100;
11445+
11446+ switch ( Channel.band )
11447+ {
11448+ case BAND_TYPE_DSSS:
11449+ case BAND_TYPE_OFDM_24:
11450+ {
11451+ if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff)
11452+ index = pHwData->TxVgaFor24[Channel.ChanNo - 1];
11453+ }
11454+ break;
11455+ case BAND_TYPE_OFDM_5:
11456+ break;
11457+ }
11458+ RFSynthesizer_SetPowerIndex( pHwData, index );
11459+}
11460+
11461+//=============================================================================================================
11462+// RFSynthesizer_SwitchingChannel --
11463+//
11464+// Description:
11465+// Swithch the RF channel.
11466+//
11467+// Arguments:
11468+// pHwData - Handle of the USB Device.
11469+// Channel - The channel no.
11470+//
11471+// Return values:
11472+// None.
11473+//=============================================================================================================
11474+void
11475+RFSynthesizer_SwitchingChannel( phw_data_t pHwData, ChanInfo Channel )
11476+{
11477+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
11478+ u32 pltmp[16]; // The 16 is the maximum capability of hardware
11479+ u32 count, ltmp;
11480+ u8 i, j, number;
11481+ u8 ChnlTmp;
11482+
11483+ switch( pHwData->phy_type )
11484+ {
11485+ case RF_MAXIM_2825:
11486+ case RF_MAXIM_V1: // 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331)
11487+
11488+ if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 13
11489+ {
11490+ for( i=0; i<3; i++ )
11491+ pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2825_channel_data_24[Channel.ChanNo-1][i], 18);
11492+ Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
11493+ }
11494+ RFSynthesizer_SetPowerIndex( pHwData, 100 );
11495+ break;
11496+
11497+ case RF_MAXIM_2827:
11498+
11499+ if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 13
11500+ {
11501+ for( i=0; i<3; i++ )
11502+ pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_channel_data_24[Channel.ChanNo-1][i], 18);
11503+ Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
11504+ }
11505+ else if( Channel.band == BAND_TYPE_OFDM_5 ) // channel 36 ~ 64
11506+ {
11507+ ChnlTmp = (Channel.ChanNo - 36) / 4;
11508+ for( i=0; i<3; i++ )
11509+ pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_channel_data_50[ChnlTmp][i], 18);
11510+ Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
11511+ }
11512+ RFSynthesizer_SetPowerIndex( pHwData, 100 );
11513+ break;
11514+
11515+ case RF_MAXIM_2828:
11516+
11517+ if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 13
11518+ {
11519+ for( i=0; i<3; i++ )
11520+ pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_channel_data_24[Channel.ChanNo-1][i], 18);
11521+ Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
11522+ }
11523+ else if( Channel.band == BAND_TYPE_OFDM_5 ) // channel 36 ~ 64
11524+ {
11525+ ChnlTmp = (Channel.ChanNo - 36) / 4;
11526+ for ( i = 0; i < 3; i++)
11527+ pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_channel_data_50[ChnlTmp][i], 18);
11528+ Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
11529+ }
11530+ RFSynthesizer_SetPowerIndex( pHwData, 100 );
11531+ break;
11532+
11533+ case RF_MAXIM_2829:
11534+
11535+ if( Channel.band <= BAND_TYPE_OFDM_24)
11536+ {
11537+ for( i=0; i<3; i++ )
11538+ pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2829_channel_data_24[Channel.ChanNo-1][i], 18);
11539+ Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
11540+ }
11541+ else if( Channel.band == BAND_TYPE_OFDM_5 )
11542+ {
11543+ count = sizeof(max2829_channel_data_50) / sizeof(max2829_channel_data_50[0]);
11544+
11545+ for( i=0; i<count; i++ )
11546+ {
11547+ if( max2829_channel_data_50[i][0] == Channel.ChanNo )
11548+ {
11549+ for( j=0; j<3; j++ )
11550+ pltmp[j] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2829_channel_data_50[i][j+1], 18);
11551+ Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
11552+
11553+ if( (max2829_channel_data_50[i][3] & 0x3FFFF) == 0x2A946 )
11554+ {
11555+ ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( (5<<18)|0x2A906, 18);
11556+ Wb35Reg_Write( pHwData, 0x0864, ltmp );
11557+ }
11558+ else // 0x2A9C6
11559+ {
11560+ ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( (5<<18)|0x2A986, 18);
11561+ Wb35Reg_Write( pHwData, 0x0864, ltmp );
11562+ }
11563+ }
11564+ }
11565+ }
11566+ set_tx_power_per_channel_max2829( pHwData, Channel );
11567+ break;
11568+
11569+ case RF_AIROHA_2230:
11570+ case RF_AIROHA_2230S: // 20060420 Add this
11571+
11572+ if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 14
11573+ {
11574+ for( i=0; i<2; i++ )
11575+ pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_channel_data_24[Channel.ChanNo-1][i], 20);
11576+ Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 2, NO_INCREMENT );
11577+ }
11578+ set_tx_power_per_channel_al2230( pHwData, Channel );
11579+ break;
11580+
11581+ case RF_AIROHA_7230:
11582+
11583+ //Start to fill RF parameters, PLL_ON should be pulled low.
11584+ //Wb35Reg_Write( pHwData, 0x03dc, 0x00000000 );
11585+ //WBDEBUG(("* PLL_ON low\n"));
11586+
11587+ //Channel independent registers
11588+ if( Channel.band != pHwData->band)
11589+ {
11590+ if (Channel.band <= BAND_TYPE_OFDM_24)
11591+ {
11592+ //Update BB register
11593+ BBProcessor_AL7230_2400(pHwData);
11594+
11595+ number = sizeof(al7230_rf_data_24)/sizeof(al7230_rf_data_24[0]);
11596+ Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number);
11597+ }
11598+ else
11599+ {
11600+ //Update BB register
11601+ BBProcessor_AL7230_5000(pHwData);
11602+
11603+ number = sizeof(al7230_rf_data_50)/sizeof(al7230_rf_data_50[0]);
11604+ Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number);
11605+ }
11606+
11607+ // Write to register. number must less and equal than 16
11608+ Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, number, NO_INCREMENT );
11609+ #ifdef _PE_STATE_DUMP_
11610+ WBDEBUG(("Band changed\n"));
11611+ #endif
11612+ }
11613+
11614+ if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 14
11615+ {
11616+ for( i=0; i<2; i++ )
11617+ pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_channel_data_24[Channel.ChanNo-1][i]&0xffffff);
11618+ Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 2, NO_INCREMENT );
11619+ }
11620+ else if( Channel.band == BAND_TYPE_OFDM_5 )
11621+ {
11622+ //Update Reg12
11623+ if ((Channel.ChanNo > 64) && (Channel.ChanNo <= 165))
11624+ {
11625+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x00143c;
11626+ Wb35Reg_Write( pHwData, 0x0864, ltmp );
11627+ }
11628+ else //reg12 = 0x00147c at Channel 4920 ~ 5320
11629+ {
11630+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x00147c;
11631+ Wb35Reg_Write( pHwData, 0x0864, ltmp );
11632+ }
11633+
11634+ count = sizeof(al7230_channel_data_5) / sizeof(al7230_channel_data_5[0]);
11635+
11636+ for (i=0; i<count; i++)
11637+ {
11638+ if (al7230_channel_data_5[i][0] == Channel.ChanNo)
11639+ {
11640+ for( j=0; j<3; j++ )
11641+ pltmp[j] = (1 << 31) | (0 << 30) | (24 << 24) | ( al7230_channel_data_5[i][j+1]&0xffffff);
11642+ Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
11643+ }
11644+ }
11645+ }
11646+ set_tx_power_per_channel_al7230(pHwData, Channel);
11647+ break;
11648+
11649+ case RF_WB_242:
11650+ case RF_WB_242_1: // 20060619.5 Add
11651+
11652+ if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 14
11653+ {
11654+ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( w89rf242_channel_data_24[Channel.ChanNo-1][0], 24);
11655+ Wb35Reg_Write( pHwData, 0x864, ltmp );
11656+ }
11657+ set_tx_power_per_channel_wb242(pHwData, Channel);
11658+ break;
11659+ }
11660+
11661+ if( Channel.band <= BAND_TYPE_OFDM_24 )
11662+ {
11663+ // BB: select 2.4 GHz, bit[12-11]=00
11664+ pWb35Reg->BB50 &= ~(BIT(11)|BIT(12));
11665+ Wb35Reg_Write( pHwData, 0x1050, pWb35Reg->BB50 ); // MODE_Ctrl
11666+ // MAC: select 2.4 GHz, bit[5]=0
11667+ pWb35Reg->M78_ERPInformation &= ~BIT(5);
11668+ Wb35Reg_Write( pHwData, 0x0878, pWb35Reg->M78_ERPInformation );
11669+ // enable 11b Baseband
11670+ pWb35Reg->BB30 &= ~BIT(31);
11671+ Wb35Reg_Write( pHwData, 0x1030, pWb35Reg->BB30 );
11672+ }
11673+ else if( (Channel.band == BAND_TYPE_OFDM_5) )
11674+ {
11675+ // BB: select 5 GHz
11676+ pWb35Reg->BB50 &= ~(BIT(11)|BIT(12));
11677+ if (Channel.ChanNo <=64 )
11678+ pWb35Reg->BB50 |= BIT(12); // 10-5.25GHz
11679+ else if ((Channel.ChanNo >= 100) && (Channel.ChanNo <= 124))
11680+ pWb35Reg->BB50 |= BIT(11); // 01-5.48GHz
11681+ else if ((Channel.ChanNo >=128) && (Channel.ChanNo <= 161))
11682+ pWb35Reg->BB50 |= (BIT(12)|BIT(11)); // 11-5.775GHz
11683+ else //Chan 184 ~ 196 will use bit[12-11] = 10 in version sh-src-1.2.25
11684+ pWb35Reg->BB50 |= BIT(12);
11685+ Wb35Reg_Write( pHwData, 0x1050, pWb35Reg->BB50 ); // MODE_Ctrl
11686+
11687+ //(1) M78 should alway use 2.4G setting when using RF_AIROHA_7230
11688+ //(2) BB30 has been updated previously.
11689+ if (pHwData->phy_type != RF_AIROHA_7230)
11690+ {
11691+ // MAC: select 5 GHz, bit[5]=1
11692+ pWb35Reg->M78_ERPInformation |= BIT(5);
11693+ Wb35Reg_Write( pHwData, 0x0878, pWb35Reg->M78_ERPInformation );
11694+
11695+ // disable 11b Baseband
11696+ pWb35Reg->BB30 |= BIT(31);
11697+ Wb35Reg_Write( pHwData, 0x1030, pWb35Reg->BB30 );
11698+ }
11699+ }
11700+}
11701+
11702+//Set the tx power directly from DUT GUI, not from the EEPROM. Return the current setting
11703+u8 RFSynthesizer_SetPowerIndex( phw_data_t pHwData, u8 PowerIndex )
11704+{
11705+ u32 Band = pHwData->band;
11706+ u8 index=0;
11707+
11708+ if( pHwData->power_index == PowerIndex ) // 20060620.1 Add
11709+ return PowerIndex;
11710+
11711+ if (RF_MAXIM_2825 == pHwData->phy_type)
11712+ {
11713+ // Channel 1 - 13
11714+ index = RFSynthesizer_SetMaxim2825Power( pHwData, PowerIndex );
11715+ }
11716+ else if (RF_MAXIM_2827 == pHwData->phy_type)
11717+ {
11718+ if( Band <= BAND_TYPE_OFDM_24 ) // Channel 1 - 13
11719+ index = RFSynthesizer_SetMaxim2827_24Power( pHwData, PowerIndex );
11720+ else// if( Band == BAND_TYPE_OFDM_5 ) // Channel 36 - 64
11721+ index = RFSynthesizer_SetMaxim2827_50Power( pHwData, PowerIndex );
11722+ }
11723+ else if (RF_MAXIM_2828 == pHwData->phy_type)
11724+ {
11725+ if( Band <= BAND_TYPE_OFDM_24 ) // Channel 1 - 13
11726+ index = RFSynthesizer_SetMaxim2828_24Power( pHwData, PowerIndex );
11727+ else// if( Band == BAND_TYPE_OFDM_5 ) // Channel 36 - 64
11728+ index = RFSynthesizer_SetMaxim2828_50Power( pHwData, PowerIndex );
11729+ }
11730+ else if( RF_AIROHA_2230 == pHwData->phy_type )
11731+ {
11732+ //Power index: 0 ~ 63 // Channel 1 - 14
11733+ index = RFSynthesizer_SetAiroha2230Power( pHwData, PowerIndex );
11734+ index = (u8)al2230_txvga_data[index][1];
11735+ }
11736+ else if( RF_AIROHA_2230S == pHwData->phy_type ) // 20060420 Add this
11737+ {
11738+ //Power index: 0 ~ 63 // Channel 1 - 14
11739+ index = RFSynthesizer_SetAiroha2230Power( pHwData, PowerIndex );
11740+ index = (u8)al2230_txvga_data[index][1];
11741+ }
11742+ else if( RF_AIROHA_7230 == pHwData->phy_type )
11743+ {
11744+ //Power index: 0 ~ 63
11745+ index = RFSynthesizer_SetAiroha7230Power( pHwData, PowerIndex );
11746+ index = (u8)al7230_txvga_data[index][1];
11747+ }
11748+ else if( (RF_WB_242 == pHwData->phy_type) ||
11749+ (RF_WB_242_1 == pHwData->phy_type) ) // 20060619.5 Add
11750+ {
11751+ //Power index: 0 ~ 19 for original. New range is 0 ~ 33
11752+ index = RFSynthesizer_SetWinbond242Power( pHwData, PowerIndex );
11753+ index = (u8)w89rf242_txvga_data[index][1];
11754+ }
11755+
11756+ pHwData->power_index = index; // Backup current
11757+ return index;
11758+}
11759+
11760+//-- Sub function
11761+u8 RFSynthesizer_SetMaxim2828_24Power( phw_data_t pHwData, u8 index )
11762+{
11763+ u32 PowerData;
11764+ if( index > 1 ) index = 1;
11765+ PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_power_data_24[index], 18);
11766+ Wb35Reg_Write( pHwData, 0x0864, PowerData );
11767+ return index;
11768+}
11769+//--
11770+u8 RFSynthesizer_SetMaxim2828_50Power( phw_data_t pHwData, u8 index )
11771+{
11772+ u32 PowerData;
11773+ if( index > 1 ) index = 1;
11774+ PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_power_data_50[index], 18);
11775+ Wb35Reg_Write( pHwData, 0x0864, PowerData );
11776+ return index;
11777+}
11778+//--
11779+u8 RFSynthesizer_SetMaxim2827_24Power( phw_data_t pHwData, u8 index )
11780+{
11781+ u32 PowerData;
11782+ if( index > 1 ) index = 1;
11783+ PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_power_data_24[index], 18);
11784+ Wb35Reg_Write( pHwData, 0x0864, PowerData );
11785+ return index;
11786+}
11787+//--
11788+u8 RFSynthesizer_SetMaxim2827_50Power( phw_data_t pHwData, u8 index )
11789+{
11790+ u32 PowerData;
11791+ if( index > 1 ) index = 1;
11792+ PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_power_data_50[index], 18);
11793+ Wb35Reg_Write( pHwData, 0x0864, PowerData );
11794+ return index;
11795+}
11796+//--
11797+u8 RFSynthesizer_SetMaxim2825Power( phw_data_t pHwData, u8 index )
11798+{
11799+ u32 PowerData;
11800+ if( index > 1 ) index = 1;
11801+ PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2825_power_data_24[index], 18);
11802+ Wb35Reg_Write( pHwData, 0x0864, PowerData );
11803+ return index;
11804+}
11805+//--
11806+u8 RFSynthesizer_SetAiroha2230Power( phw_data_t pHwData, u8 index )
11807+{
11808+ u32 PowerData;
11809+ u8 i,count;
11810+
11811+ count = sizeof(al2230_txvga_data) / sizeof(al2230_txvga_data[0]);
11812+ for (i=0; i<count; i++)
11813+ {
11814+ if (al2230_txvga_data[i][1] >= index)
11815+ break;
11816+ }
11817+ if (i == count)
11818+ i--;
11819+
11820+ PowerData = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_txvga_data[i][0], 20);
11821+ Wb35Reg_Write( pHwData, 0x0864, PowerData );
11822+ return i;
11823+}
11824+//--
11825+u8 RFSynthesizer_SetAiroha7230Power( phw_data_t pHwData, u8 index )
11826+{
11827+ u32 PowerData;
11828+ u8 i,count;
11829+
11830+ //PowerData = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( airoha_power_data_24[index], 20);
11831+ count = sizeof(al7230_txvga_data) / sizeof(al7230_txvga_data[0]);
11832+ for (i=0; i<count; i++)
11833+ {
11834+ if (al7230_txvga_data[i][1] >= index)
11835+ break;
11836+ }
11837+ if (i == count)
11838+ i--;
11839+ PowerData = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_txvga_data[i][0]&0xffffff);
11840+ Wb35Reg_Write( pHwData, 0x0864, PowerData );
11841+ return i;
11842+}
11843+
11844+u8 RFSynthesizer_SetWinbond242Power( phw_data_t pHwData, u8 index )
11845+{
11846+ u32 PowerData;
11847+ u8 i,count;
11848+
11849+ count = sizeof(w89rf242_txvga_data) / sizeof(w89rf242_txvga_data[0]);
11850+ for (i=0; i<count; i++)
11851+ {
11852+ if (w89rf242_txvga_data[i][1] >= index)
11853+ break;
11854+ }
11855+ if (i == count)
11856+ i--;
11857+
11858+ // Set TxVga into RF
11859+ PowerData = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( w89rf242_txvga_data[i][0], 24);
11860+ Wb35Reg_Write( pHwData, 0x0864, PowerData );
11861+
11862+ // Update BB48 BB4C BB58 for high precision txvga
11863+ Wb35Reg_Write( pHwData, 0x1048, w89rf242_txvga_data[i][2] );
11864+ Wb35Reg_Write( pHwData, 0x104c, w89rf242_txvga_data[i][3] );
11865+ Wb35Reg_Write( pHwData, 0x1058, w89rf242_txvga_data[i][4] );
11866+
11867+// Rf vga 0 ~ 3 for temperature compensate. It will affect the scan Bss.
11868+// The i value equals to 8 or 7 usually. So It's not necessary to setup this RF register.
11869+// if( i <= 3 )
11870+// PowerData = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( 0x000024, 24 );
11871+// else
11872+// PowerData = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( 0x001824, 24 );
11873+// Wb35Reg_Write( pHwData, 0x0864, PowerData );
11874+ return i;
11875+}
11876+
11877+//===========================================================================================================
11878+// Dxx_initial --
11879+// Mxx_initial --
11880+ //
11881+// Routine Description:
11882+// Initial the hardware setting and module variable
11883+ //
11884+//===========================================================================================================
11885+void Dxx_initial( phw_data_t pHwData )
11886+{
11887+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
11888+
11889+ // Old IC:Single mode only.
11890+ // New IC: operation decide by Software set bit[4]. 1:multiple 0: single
11891+ pWb35Reg->D00_DmaControl = 0xc0000004; //Txon, Rxon, multiple Rx for new 4k DMA
11892+ //Txon, Rxon, single Rx for old 8k ASIC
11893+ if( !HAL_USB_MODE_BURST( pHwData ) )
11894+ pWb35Reg->D00_DmaControl = 0xc0000000;//Txon, Rxon, single Rx for new 4k DMA
11895+
11896+ Wb35Reg_WriteSync( pHwData, 0x0400, pWb35Reg->D00_DmaControl );
11897+}
11898+
11899+void Mxx_initial( phw_data_t pHwData )
11900+{
11901+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
11902+ u32 tmp;
11903+ u32 pltmp[11];
11904+ u16 i;
11905+
11906+
11907+ //======================================================
11908+ // Initial Mxx register
11909+ //======================================================
11910+
11911+ // M00 bit set
11912+#ifdef _IBSS_BEACON_SEQ_STICK_
11913+ pWb35Reg->M00_MacControl = 0; // Solve beacon sequence number stop by software
11914+#else
11915+ pWb35Reg->M00_MacControl = 0x80000000; // Solve beacon sequence number stop by hardware
11916+#endif
11917+
11918+ // M24 disable enter power save, BB RxOn and enable NAV attack
11919+ pWb35Reg->M24_MacControl = 0x08040042;
11920+ pltmp[0] = pWb35Reg->M24_MacControl;
11921+
11922+ pltmp[1] = 0; // Skip M28, because no initialize value is required.
11923+
11924+ // M2C CWmin and CWmax setting
11925+ pHwData->cwmin = DEFAULT_CWMIN;
11926+ pHwData->cwmax = DEFAULT_CWMAX;
11927+ pWb35Reg->M2C_MacControl = DEFAULT_CWMIN << 10;
11928+ pWb35Reg->M2C_MacControl |= DEFAULT_CWMAX;
11929+ pltmp[2] = pWb35Reg->M2C_MacControl;
11930+
11931+ // M30 BSSID
11932+ pltmp[3] = *(PULONG)pHwData->bssid;
11933+
11934+ // M34
11935+ pHwData->AID = DEFAULT_AID;
11936+ tmp = *(PUSHORT)(pHwData->bssid+4);
11937+ tmp |= DEFAULT_AID << 16;
11938+ pltmp[4] = tmp;
11939+
11940+ // M38
11941+ pWb35Reg->M38_MacControl = (DEFAULT_RATE_RETRY_LIMIT<<8) | (DEFAULT_LONG_RETRY_LIMIT << 4) | DEFAULT_SHORT_RETRY_LIMIT;
11942+ pltmp[5] = pWb35Reg->M38_MacControl;
11943+
11944+ // M3C
11945+ tmp = (DEFAULT_PIFST << 26) | (DEFAULT_EIFST << 16) | (DEFAULT_DIFST << 8) | (DEFAULT_SIFST << 4) | DEFAULT_OSIFST ;
11946+ pWb35Reg->M3C_MacControl = tmp;
11947+ pltmp[6] = tmp;
11948+
11949+ // M40
11950+ pHwData->slot_time_select = DEFAULT_SLOT_TIME;
11951+ tmp = (DEFAULT_ATIMWD << 16) | DEFAULT_SLOT_TIME;
11952+ pWb35Reg->M40_MacControl = tmp;
11953+ pltmp[7] = tmp;
11954+
11955+ // M44
11956+ tmp = DEFAULT_MAX_TX_MSDU_LIFE_TIME << 10; // *1024
11957+ pWb35Reg->M44_MacControl = tmp;
11958+ pltmp[8] = tmp;
11959+
11960+ // M48
11961+ pHwData->BeaconPeriod = DEFAULT_BEACON_INTERVAL;
11962+ pHwData->ProbeDelay = DEFAULT_PROBE_DELAY_TIME;
11963+ tmp = (DEFAULT_BEACON_INTERVAL << 16) | DEFAULT_PROBE_DELAY_TIME;
11964+ pWb35Reg->M48_MacControl = tmp;
11965+ pltmp[9] = tmp;
11966+
11967+ //M4C
11968+ pWb35Reg->M4C_MacStatus = (DEFAULT_PROTOCOL_VERSION << 30) | (DEFAULT_MAC_POWER_STATE << 28) | (DEFAULT_DTIM_ALERT_TIME << 24);
11969+ pltmp[10] = pWb35Reg->M4C_MacStatus;
11970+
11971+ // Burst write
11972+ //Wb35Reg_BurstWrite( pHwData, 0x0824, pltmp, 11, AUTO_INCREMENT );
11973+ for( i=0; i<11; i++ )
11974+ Wb35Reg_WriteSync( pHwData, 0x0824 + i*4, pltmp[i] );
11975+
11976+ // M60
11977+ Wb35Reg_WriteSync( pHwData, 0x0860, 0x12481248 );
11978+ pWb35Reg->M60_MacControl = 0x12481248;
11979+
11980+ // M68
11981+ Wb35Reg_WriteSync( pHwData, 0x0868, 0x00050900 ); // 20051018 0x000F0F00 ); // 940930 0x00131300
11982+ pWb35Reg->M68_MacControl = 0x00050900;
11983+
11984+ // M98
11985+ Wb35Reg_WriteSync( pHwData, 0x0898, 0xffff8888 );
11986+ pWb35Reg->M98_MacControl = 0xffff8888;
11987+}
11988+
11989+
11990+void Uxx_power_off_procedure( phw_data_t pHwData )
11991+{
11992+ // SW, PMU reset and turn off clock
11993+ Wb35Reg_WriteSync( pHwData, 0x03b0, 3 );
11994+ Wb35Reg_WriteSync( pHwData, 0x03f0, 0xf9 );
11995+}
11996+
11997+//Decide the TxVga of every channel
11998+void GetTxVgaFromEEPROM( phw_data_t pHwData )
11999+{
12000+ u32 i, j, ltmp;
12001+ u16 Value[MAX_TXVGA_EEPROM];
12002+ PUCHAR pctmp;
12003+ u8 ctmp=0;
12004+
12005+ // Get the entire TxVga setting in EEPROM
12006+ for( i=0; i<MAX_TXVGA_EEPROM; i++ )
12007+ {
12008+ Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08100000 + 0x00010000*i );
12009+ Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp );
12010+ Value[i] = (u16)( ltmp & 0xffff ); // Get 16 bit available
12011+ Value[i] = cpu_to_le16( Value[i] ); // [7:0]2412 [7:0]2417 ....
12012+ }
12013+
12014+ // Adjust the filed which fills with reserved value.
12015+ pctmp = (PUCHAR)Value;
12016+ for( i=0; i<(MAX_TXVGA_EEPROM*2); i++ )
12017+ {
12018+ if( pctmp[i] != 0xff )
12019+ ctmp = pctmp[i];
12020+ else
12021+ pctmp[i] = ctmp;
12022+ }
12023+
12024+ // Adjust WB_242 to WB_242_1 TxVga scale
12025+ if( pHwData->phy_type == RF_WB_242 )
12026+ {
12027+ for( i=0; i<4; i++ ) // Only 2412 2437 2462 2484 case must be modified
12028+ {
12029+ for( j=0; j<(sizeof(w89rf242_txvga_old_mapping)/sizeof(w89rf242_txvga_old_mapping[0])); j++ )
12030+ {
12031+ if( pctmp[i] < (u8)w89rf242_txvga_old_mapping[j][1] )
12032+ {
12033+ pctmp[i] = (u8)w89rf242_txvga_old_mapping[j][0];
12034+ break;
12035+ }
12036+ }
12037+
12038+ if( j == (sizeof(w89rf242_txvga_old_mapping)/sizeof(w89rf242_txvga_old_mapping[0])) )
12039+ pctmp[i] = (u8)w89rf242_txvga_old_mapping[j-1][0];
12040+ }
12041+ }
12042+
12043+ // 20060621 Add
12044+ memcpy( pHwData->TxVgaSettingInEEPROM, pctmp, MAX_TXVGA_EEPROM*2 ); //MAX_TXVGA_EEPROM is u16 count
12045+ EEPROMTxVgaAdjust( pHwData );
12046+}
12047+
12048+// This function will affect the TxVga parameter in HAL. If hal_set_current_channel
12049+// or RFSynthesizer_SetPowerIndex be called, new TxVga will take effect.
12050+// TxVgaSettingInEEPROM of sHwData is an u8 array point to EEPROM contain for IS89C35
12051+// This function will use default TxVgaSettingInEEPROM data to calculate new TxVga.
12052+void EEPROMTxVgaAdjust( phw_data_t pHwData ) // 20060619.5 Add
12053+{
12054+ PUCHAR pTxVga = pHwData->TxVgaSettingInEEPROM;
12055+ s16 i, stmp;
12056+
12057+ //-- 2.4G -- 20060704.2 Request from Tiger
12058+ //channel 1 ~ 5
12059+ stmp = pTxVga[1] - pTxVga[0];
12060+ for( i=0; i<5; i++ )
12061+ pHwData->TxVgaFor24[i] = pTxVga[0] + stmp*i/4;
12062+ //channel 6 ~ 10
12063+ stmp = pTxVga[2] - pTxVga[1];
12064+ for( i=5; i<10; i++ )
12065+ pHwData->TxVgaFor24[i] = pTxVga[1] + stmp*(i-5)/4;
12066+ //channel 11 ~ 13
12067+ stmp = pTxVga[3] - pTxVga[2];
12068+ for( i=10; i<13; i++ )
12069+ pHwData->TxVgaFor24[i] = pTxVga[2] + stmp*(i-10)/2;
12070+ //channel 14
12071+ pHwData->TxVgaFor24[13] = pTxVga[3];
12072+
12073+ //-- 5G --
12074+ if( pHwData->phy_type == RF_AIROHA_7230 )
12075+ {
12076+ //channel 184
12077+ pHwData->TxVgaFor50[0].ChanNo = 184;
12078+ pHwData->TxVgaFor50[0].TxVgaValue = pTxVga[4];
12079+ //channel 196
12080+ pHwData->TxVgaFor50[3].ChanNo = 196;
12081+ pHwData->TxVgaFor50[3].TxVgaValue = pTxVga[5];
12082+ //interpolate
12083+ pHwData->TxVgaFor50[1].ChanNo = 188;
12084+ pHwData->TxVgaFor50[2].ChanNo = 192;
12085+ stmp = pTxVga[5] - pTxVga[4];
12086+ pHwData->TxVgaFor50[2].TxVgaValue = pTxVga[5] - stmp/3;
12087+ pHwData->TxVgaFor50[1].TxVgaValue = pTxVga[5] - stmp*2/3;
12088+
12089+ //channel 16
12090+ pHwData->TxVgaFor50[6].ChanNo = 16;
12091+ pHwData->TxVgaFor50[6].TxVgaValue = pTxVga[6];
12092+ pHwData->TxVgaFor50[4].ChanNo = 8;
12093+ pHwData->TxVgaFor50[4].TxVgaValue = pTxVga[6];
12094+ pHwData->TxVgaFor50[5].ChanNo = 12;
12095+ pHwData->TxVgaFor50[5].TxVgaValue = pTxVga[6];
12096+
12097+ //channel 36
12098+ pHwData->TxVgaFor50[8].ChanNo = 36;
12099+ pHwData->TxVgaFor50[8].TxVgaValue = pTxVga[7];
12100+ pHwData->TxVgaFor50[7].ChanNo = 34;
12101+ pHwData->TxVgaFor50[7].TxVgaValue = pTxVga[7];
12102+ pHwData->TxVgaFor50[9].ChanNo = 38;
12103+ pHwData->TxVgaFor50[9].TxVgaValue = pTxVga[7];
12104+
12105+ //channel 40
12106+ pHwData->TxVgaFor50[10].ChanNo = 40;
12107+ pHwData->TxVgaFor50[10].TxVgaValue = pTxVga[8];
12108+ //channel 48
12109+ pHwData->TxVgaFor50[14].ChanNo = 48;
12110+ pHwData->TxVgaFor50[14].TxVgaValue = pTxVga[9];
12111+ //interpolate
12112+ pHwData->TxVgaFor50[11].ChanNo = 42;
12113+ pHwData->TxVgaFor50[12].ChanNo = 44;
12114+ pHwData->TxVgaFor50[13].ChanNo = 46;
12115+ stmp = pTxVga[9] - pTxVga[8];
12116+ pHwData->TxVgaFor50[13].TxVgaValue = pTxVga[9] - stmp/4;
12117+ pHwData->TxVgaFor50[12].TxVgaValue = pTxVga[9] - stmp*2/4;
12118+ pHwData->TxVgaFor50[11].TxVgaValue = pTxVga[9] - stmp*3/4;
12119+
12120+ //channel 52
12121+ pHwData->TxVgaFor50[15].ChanNo = 52;
12122+ pHwData->TxVgaFor50[15].TxVgaValue = pTxVga[10];
12123+ //channel 64
12124+ pHwData->TxVgaFor50[18].ChanNo = 64;
12125+ pHwData->TxVgaFor50[18].TxVgaValue = pTxVga[11];
12126+ //interpolate
12127+ pHwData->TxVgaFor50[16].ChanNo = 56;
12128+ pHwData->TxVgaFor50[17].ChanNo = 60;
12129+ stmp = pTxVga[11] - pTxVga[10];
12130+ pHwData->TxVgaFor50[17].TxVgaValue = pTxVga[11] - stmp/3;
12131+ pHwData->TxVgaFor50[16].TxVgaValue = pTxVga[11] - stmp*2/3;
12132+
12133+ //channel 100
12134+ pHwData->TxVgaFor50[19].ChanNo = 100;
12135+ pHwData->TxVgaFor50[19].TxVgaValue = pTxVga[12];
12136+ //channel 112
12137+ pHwData->TxVgaFor50[22].ChanNo = 112;
12138+ pHwData->TxVgaFor50[22].TxVgaValue = pTxVga[13];
12139+ //interpolate
12140+ pHwData->TxVgaFor50[20].ChanNo = 104;
12141+ pHwData->TxVgaFor50[21].ChanNo = 108;
12142+ stmp = pTxVga[13] - pTxVga[12];
12143+ pHwData->TxVgaFor50[21].TxVgaValue = pTxVga[13] - stmp/3;
12144+ pHwData->TxVgaFor50[20].TxVgaValue = pTxVga[13] - stmp*2/3;
12145+
12146+ //channel 128
12147+ pHwData->TxVgaFor50[26].ChanNo = 128;
12148+ pHwData->TxVgaFor50[26].TxVgaValue = pTxVga[14];
12149+ //interpolate
12150+ pHwData->TxVgaFor50[23].ChanNo = 116;
12151+ pHwData->TxVgaFor50[24].ChanNo = 120;
12152+ pHwData->TxVgaFor50[25].ChanNo = 124;
12153+ stmp = pTxVga[14] - pTxVga[13];
12154+ pHwData->TxVgaFor50[25].TxVgaValue = pTxVga[14] - stmp/4;
12155+ pHwData->TxVgaFor50[24].TxVgaValue = pTxVga[14] - stmp*2/4;
12156+ pHwData->TxVgaFor50[23].TxVgaValue = pTxVga[14] - stmp*3/4;
12157+
12158+ //channel 140
12159+ pHwData->TxVgaFor50[29].ChanNo = 140;
12160+ pHwData->TxVgaFor50[29].TxVgaValue = pTxVga[15];
12161+ //interpolate
12162+ pHwData->TxVgaFor50[27].ChanNo = 132;
12163+ pHwData->TxVgaFor50[28].ChanNo = 136;
12164+ stmp = pTxVga[15] - pTxVga[14];
12165+ pHwData->TxVgaFor50[28].TxVgaValue = pTxVga[15] - stmp/3;
12166+ pHwData->TxVgaFor50[27].TxVgaValue = pTxVga[15] - stmp*2/3;
12167+
12168+ //channel 149
12169+ pHwData->TxVgaFor50[30].ChanNo = 149;
12170+ pHwData->TxVgaFor50[30].TxVgaValue = pTxVga[16];
12171+ //channel 165
12172+ pHwData->TxVgaFor50[34].ChanNo = 165;
12173+ pHwData->TxVgaFor50[34].TxVgaValue = pTxVga[17];
12174+ //interpolate
12175+ pHwData->TxVgaFor50[31].ChanNo = 153;
12176+ pHwData->TxVgaFor50[32].ChanNo = 157;
12177+ pHwData->TxVgaFor50[33].ChanNo = 161;
12178+ stmp = pTxVga[17] - pTxVga[16];
12179+ pHwData->TxVgaFor50[33].TxVgaValue = pTxVga[17] - stmp/4;
12180+ pHwData->TxVgaFor50[32].TxVgaValue = pTxVga[17] - stmp*2/4;
12181+ pHwData->TxVgaFor50[31].TxVgaValue = pTxVga[17] - stmp*3/4;
12182+ }
12183+
12184+ #ifdef _PE_STATE_DUMP_
12185+ WBDEBUG((" TxVgaFor24 : \n"));
12186+ DataDmp((u8 *)pHwData->TxVgaFor24, 14 ,0);
12187+ WBDEBUG((" TxVgaFor50 : \n"));
12188+ DataDmp((u8 *)pHwData->TxVgaFor50, 70 ,0);
12189+ #endif
12190+}
12191+
12192+void BBProcessor_RateChanging( phw_data_t pHwData, u8 rate ) // 20060613.1
12193+{
12194+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
12195+ unsigned char Is11bRate;
12196+
12197+ Is11bRate = (rate % 6) ? 1 : 0;
12198+ switch( pHwData->phy_type )
12199+ {
12200+ case RF_AIROHA_2230:
12201+ case RF_AIROHA_2230S: // 20060420 Add this
12202+ if( Is11bRate )
12203+ {
12204+ if( (pWb35Reg->BB48 != BB48_DEFAULT_AL2230_11B) &&
12205+ (pWb35Reg->BB4C != BB4C_DEFAULT_AL2230_11B) )
12206+ {
12207+ Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_AL2230_11B );
12208+ Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_AL2230_11B );
12209+ }
12210+ }
12211+ else
12212+ {
12213+ if( (pWb35Reg->BB48 != BB48_DEFAULT_AL2230_11G) &&
12214+ (pWb35Reg->BB4C != BB4C_DEFAULT_AL2230_11G) )
12215+ {
12216+ Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_AL2230_11G );
12217+ Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_AL2230_11G );
12218+ }
12219+ }
12220+ break;
12221+
12222+ case RF_WB_242: // 20060623 The fix only for old TxVGA setting
12223+ if( Is11bRate )
12224+ {
12225+ if( (pWb35Reg->BB48 != BB48_DEFAULT_WB242_11B) &&
12226+ (pWb35Reg->BB4C != BB4C_DEFAULT_WB242_11B) )
12227+ {
12228+ pWb35Reg->BB48 = BB48_DEFAULT_WB242_11B;
12229+ pWb35Reg->BB4C = BB4C_DEFAULT_WB242_11B;
12230+ Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_WB242_11B );
12231+ Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_WB242_11B );
12232+ }
12233+ }
12234+ else
12235+ {
12236+ if( (pWb35Reg->BB48 != BB48_DEFAULT_WB242_11G) &&
12237+ (pWb35Reg->BB4C != BB4C_DEFAULT_WB242_11G) )
12238+ {
12239+ pWb35Reg->BB48 = BB48_DEFAULT_WB242_11G;
12240+ pWb35Reg->BB4C = BB4C_DEFAULT_WB242_11G;
12241+ Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_WB242_11G );
12242+ Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_WB242_11G );
12243+ }
12244+ }
12245+ break;
12246+ }
12247+}
12248+
12249+
12250+
12251+
12252+
12253+
12254+
12255diff --git a/drivers/staging/winbond/rxisr.c b/drivers/staging/winbond/rxisr.c
12256new file mode 100644
12257index 0000000..18e942c
12258--- /dev/null
12259+++ b/drivers/staging/winbond/rxisr.c
12260@@ -0,0 +1,30 @@
12261+#include "os_common.h"
12262+
12263+void vRxTimerInit(PWB32_ADAPTER Adapter)
12264+{
12265+ OS_TIMER_INITIAL(&(Adapter->Mds.nTimer), (void*) RxTimerHandler, (void*) Adapter);
12266+}
12267+
12268+void vRxTimerStart(PWB32_ADAPTER Adapter, int timeout_value)
12269+{
12270+ if (timeout_value<MIN_TIMEOUT_VAL)
12271+ timeout_value=MIN_TIMEOUT_VAL;
12272+
12273+ OS_TIMER_SET( &(Adapter->Mds.nTimer), timeout_value );
12274+}
12275+
12276+void vRxTimerStop(PWB32_ADAPTER Adapter)
12277+{
12278+ OS_TIMER_CANCEL( &(Adapter->Mds.nTimer), 0 );
12279+}
12280+
12281+void RxTimerHandler_1a( PADAPTER Adapter)
12282+{
12283+ RxTimerHandler(NULL, Adapter, NULL, NULL);
12284+}
12285+
12286+void RxTimerHandler(void* SystemSpecific1, PWB32_ADAPTER Adapter,
12287+ void* SystemSpecific2, void* SystemSpecific3)
12288+{
12289+ WARN_ON(1);
12290+}
12291diff --git a/drivers/staging/winbond/scan_s.h b/drivers/staging/winbond/scan_s.h
12292new file mode 100644
12293index 0000000..1d1b0c4
12294--- /dev/null
12295+++ b/drivers/staging/winbond/scan_s.h
12296@@ -0,0 +1,115 @@
12297+//
12298+// SCAN task global CONSTANTS, STRUCTURES, variables
12299+//
12300+
12301+//////////////////////////////////////////////////////////////////////////
12302+//define the msg type of SCAN module
12303+#define SCANMSG_SCAN_REQ 0x01
12304+#define SCANMSG_BEACON 0x02
12305+#define SCANMSG_PROBE_RESPONSE 0x03
12306+#define SCANMSG_TIMEOUT 0x04
12307+#define SCANMSG_TXPROBE_FAIL 0x05
12308+#define SCANMSG_ENABLE_BGSCAN 0x06
12309+#define SCANMSG_STOP_SCAN 0x07
12310+
12311+// BSS Type =>conform to
12312+// IBSS : ToDS/FromDS = 00
12313+// Infrastructure : ToDS/FromDS = 01
12314+#define IBSS_NET 0
12315+#define ESS_NET 1
12316+#define ANYBSS_NET 2
12317+
12318+// Scan Type
12319+#define ACTIVE_SCAN 0
12320+#define PASSIVE_SCAN 1
12321+
12322+///////////////////////////////////////////////////////////////////////////
12323+//Global data structures, Initial Scan & Background Scan
12324+typedef struct _SCAN_REQ_PARA //mandatory parameters for SCAN request
12325+{
12326+ u32 ScanType; //passive/active scan
12327+
12328+ CHAN_LIST sChannelList; // 86B
12329+ u8 reserved_1[2];
12330+
12331+ struct SSID_Element sSSID; // 34B. scan only for this SSID
12332+ u8 reserved_2[2];
12333+
12334+} SCAN_REQ_PARA, *psSCAN_REQ_PARA;
12335+
12336+typedef struct _SCAN_PARAMETERS
12337+{
12338+ u16 wState;
12339+ u16 iCurrentChannelIndex;
12340+
12341+ SCAN_REQ_PARA sScanReq;
12342+
12343+ u8 BSSID[MAC_ADDR_LENGTH + 2]; //scan only for this BSSID
12344+
12345+ u32 BssType; //scan only for this BSS type
12346+
12347+ //struct SSID_Element sSSID; //scan only for this SSID
12348+ u16 ProbeDelay;
12349+ u16 MinChannelTime;
12350+
12351+ u16 MaxChannelTime;
12352+ u16 reserved_1;
12353+
12354+ s32 iBgScanPeriod; // XP: 5 sec
12355+
12356+ u8 boBgScan; // Wb: enable BG scan, For XP, this value must be FALSE
12357+ u8 boFastScan; // Wb: reserved
12358+ u8 boCCAbusy; // Wb: HWMAC CCA busy status
12359+ u8 reserved_2;
12360+
12361+ //NDIS_MINIPORT_TIMER nTimer;
12362+ OS_TIMER nTimer;
12363+
12364+ u32 ScanTimeStamp; //Increase 1 per background scan(1 minute)
12365+ u32 BssTimeStamp; //Increase 1 per connect status check
12366+ u32 RxNumPerAntenna[2]; //
12367+
12368+ u8 AntennaToggle; //
12369+ u8 boInTimerHandler;
12370+ u8 boTimerActive; // Wb: reserved
12371+ u8 boSave;
12372+
12373+ u32 BScanEnable; // Background scan enable. Default is On
12374+
12375+} SCAN_PARAMETERS, *psSCAN_PARAMETERS;
12376+
12377+// Encapsulate 'Adapter' data structure
12378+#define psSCAN (&(Adapter->sScanPara))
12379+#define psSCANREQ (&(Adapter->sScanPara.sScanReq))
12380+
12381+//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
12382+// scan.h
12383+// Define the related definitions of scan module
12384+// history -- 01/14/03' created
12385+//
12386+//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
12387+
12388+//Define the state of scan module
12389+#define SCAN_INACTIVE 0
12390+#define WAIT_PROBE_DELAY 1
12391+#define WAIT_RESPONSE_MIN 2
12392+#define WAIT_RESPONSE_MAX_ACTIVE 3
12393+#define WAIT_BEACON_MAX_PASSIVE 4
12394+#define SCAN_COMPLETE 5
12395+#define BG_SCAN 6
12396+#define BG_SCANNING 7
12397+
12398+
12399+// The value will load from EEPROM
12400+// If 0xff is set in EEPOM, the driver will use SCAN_MAX_CHNL_TIME instead.
12401+// The definition is in WbHal.h
12402+// #define SCAN_MAX_CHNL_TIME (50)
12403+
12404+
12405+
12406+// static functions
12407+
12408+//static void ScanTimerHandler(PWB32_ADAPTER Adapter);
12409+//static void vScanTimerStart(PWB32_ADAPTER Adapter, int timeout_value);
12410+//static void vScanTimerStop(PWB32_ADAPTER Adapter);
12411+
12412diff --git a/drivers/staging/winbond/sme_api.c b/drivers/staging/winbond/sme_api.c
12413new file mode 100644
12414index 0000000..40e93b7
12415--- /dev/null
12416+++ b/drivers/staging/winbond/sme_api.c
12417@@ -0,0 +1,13 @@
12418+//------------------------------------------------------------------------------------
12419+// sme_api.c
12420+//
12421+// Copyright(C) 2002 Winbond Electronics Corp.
12422+//
12423+//
12424+//------------------------------------------------------------------------------------
12425+#include "os_common.h"
12426+
12427+s8 sme_get_rssi(void *pcore_data, s32 *prssi)
12428+{
12429+ BUG();
12430+}
12431diff --git a/drivers/staging/winbond/sme_api.h b/drivers/staging/winbond/sme_api.h
12432new file mode 100644
12433index 0000000..016b225
12434--- /dev/null
12435+++ b/drivers/staging/winbond/sme_api.h
12436@@ -0,0 +1,265 @@
12437+/*
12438+ * sme_api.h
12439+ *
12440+ * Copyright(C) 2002 Winbond Electronics Corp.
12441+ *
12442+ * modification history
12443+ * ---------------------------------------------------------------------------
12444+ * 1.00.001, 2003-04-21, Kevin created
12445+ * 1.00.002, 2003-05-14, PD43 & PE20 modified
12446+ *
12447+ */
12448+
12449+#ifndef __SME_API_H__
12450+#define __SME_API_H__
12451+
12452+/****************** INCLUDE FILES SECTION ***********************************/
12453+//#include "GL\gl_core.h"
12454+
12455+/****************** CONSTANT AND MACRO SECTION ******************************/
12456+#define _INLINE __inline
12457+
12458+#define MEDIA_STATE_DISCONNECTED 0
12459+#define MEDIA_STATE_CONNECTED 1
12460+
12461+//ARRAY CHECK
12462+#define MAX_POWER_TO_DB 32
12463+
12464+/****************** TYPE DEFINITION SECTION *********************************/
12465+
12466+/****************** EXPORTED FUNCTION DECLARATION SECTION *******************/
12467+
12468+// OID_802_11_BSSID
12469+s8 sme_get_bssid(void *pcore_data, u8 *pbssid);
12470+s8 sme_get_desired_bssid(void *pcore_data, u8 *pbssid);//Not use
12471+s8 sme_set_desired_bssid(void *pcore_data, u8 *pbssid);
12472+
12473+// OID_802_11_SSID
12474+s8 sme_get_ssid(void *pcore_data, u8 *pssid, u8 *pssid_len);
12475+s8 sme_get_desired_ssid(void *pcore_data, u8 *pssid, u8 *pssid_len);// Not use
12476+s8 sme_set_desired_ssid(void *pcore_data, u8 *pssid, u8 ssid_len);
12477+
12478+// OID_802_11_INFRASTRUCTURE_MODE
12479+s8 sme_get_bss_type(void *pcore_data, u8 *pbss_type);
12480+s8 sme_get_desired_bss_type(void *pcore_data, u8 *pbss_type);//Not use
12481+s8 sme_set_desired_bss_type(void *pcore_data, u8 bss_type);
12482+
12483+// OID_802_11_FRAGMENTATION_THRESHOLD
12484+s8 sme_get_fragment_threshold(void *pcore_data, u32 *pthreshold);
12485+s8 sme_set_fragment_threshold(void *pcore_data, u32 threshold);
12486+
12487+// OID_802_11_RTS_THRESHOLD
12488+s8 sme_get_rts_threshold(void *pcore_data, u32 *pthreshold);
12489+s8 sme_set_rts_threshold(void *pcore_data, u32 threshold);
12490+
12491+// OID_802_11_RSSI
12492+s8 sme_get_rssi(void *pcore_data, s32 *prssi);
12493+
12494+// OID_802_11_CONFIGURATION
12495+s8 sme_get_beacon_period(void *pcore_data, u16 *pbeacon_period);
12496+s8 sme_set_beacon_period(void *pcore_data, u16 beacon_period);
12497+
12498+s8 sme_get_atim_window(void *pcore_data, u16 *patim_window);
12499+s8 sme_set_atim_window(void *pcore_data, u16 atim_window);
12500+
12501+s8 sme_get_current_channel(void *pcore_data, u8 *pcurrent_channel);
12502+s8 sme_get_current_band(void *pcore_data, u8 *pcurrent_band);
12503+s8 sme_set_current_channel(void *pcore_data, u8 current_channel);
12504+
12505+// OID_802_11_BSSID_LIST
12506+s8 sme_get_scan_bss_count(void *pcore_data, u8 *pcount);
12507+s8 sme_get_scan_bss(void *pcore_data, u8 index, void **ppbss);
12508+
12509+s8 sme_get_connected_bss(void *pcore_data, void **ppbss_now);
12510+
12511+// OID_802_11_AUTHENTICATION_MODE
12512+s8 sme_get_auth_mode(void *pcore_data, u8 *pauth_mode);
12513+s8 sme_set_auth_mode(void *pcore_data, u8 auth_mode);
12514+
12515+// OID_802_11_WEP_STATUS / OID_802_11_ENCRYPTION_STATUS
12516+s8 sme_get_wep_mode(void *pcore_data, u8 *pwep_mode);
12517+s8 sme_set_wep_mode(void *pcore_data, u8 wep_mode);
12518+//s8 sme_get_encryption_status(void *pcore_data, u8 *pstatus);
12519+//s8 sme_set_encryption_status(void *pcore_data, u8 status);
12520+
12521+// ???????????????????????????????????????
12522+
12523+// OID_GEN_VENDOR_ID
12524+// OID_802_3_PERMANENT_ADDRESS
12525+s8 sme_get_permanent_mac_addr(void *pcore_data, u8 *pmac_addr);
12526+
12527+// OID_802_3_CURRENT_ADDRESS
12528+s8 sme_get_current_mac_addr(void *pcore_data, u8 *pmac_addr);
12529+
12530+// OID_802_11_NETWORK_TYPE_IN_USE
12531+s8 sme_get_network_type_in_use(void *pcore_data, u8 *ptype);
12532+s8 sme_set_network_type_in_use(void *pcore_data, u8 type);
12533+
12534+// OID_802_11_SUPPORTED_RATES
12535+s8 sme_get_supported_rate(void *pcore_data, u8 *prates);
12536+
12537+// OID_802_11_ADD_WEP
12538+//12/29/03' wkchen
12539+s8 sme_set_add_wep(void *pcore_data, u32 key_index, u32 key_len,
12540+ u8 *Address, u8 *key);
12541+
12542+// OID_802_11_REMOVE_WEP
12543+s8 sme_set_remove_wep(void *pcre_data, u32 key_index);
12544+
12545+// OID_802_11_DISASSOCIATE
12546+s8 sme_set_disassociate(void *pcore_data);
12547+
12548+// OID_802_11_POWER_MODE
12549+s8 sme_get_power_mode(void *pcore_data, u8 *pmode);
12550+s8 sme_set_power_mode(void *pcore_data, u8 mode);
12551+
12552+// OID_802_11_BSSID_LIST_SCAN
12553+s8 sme_set_bssid_list_scan(void *pcore_data, void *pscan_para);
12554+
12555+// OID_802_11_RELOAD_DEFAULTS
12556+s8 sme_set_reload_defaults(void *pcore_data, u8 reload_type);
12557+
12558+
12559+// The following SME API functions are used for WPA
12560+//
12561+// Mandatory OIDs for WPA
12562+//
12563+
12564+// OID_802_11_ADD_KEY
12565+//s8 sme_set_add_key(void *pcore_data, NDIS_802_11_KEY *pkey);
12566+
12567+// OID_802_11_REMOVE_KEY
12568+//s8 sme_set_remove_key(void *pcore_data, NDIS_802_11_REMOVE_KEY *pkey);
12569+
12570+// OID_802_11_ASSOCIATION_INFORMATION
12571+//s8 sme_set_association_information(void *pcore_data,
12572+// NDIS_802_11_ASSOCIATION_INFORMATION *pinfo);
12573+
12574+// OID_802_11_TEST
12575+//s8 sme_set_test(void *pcore_data, NDIS_802_11_TEST *ptest_data);
12576+
12577+//--------------------------------------------------------------------------//
12578+/*
12579+// The left OIDs
12580+
12581+// OID_802_11_NETWORK_TYPES_SUPPORTED
12582+// OID_802_11_TX_POWER_LEVEL
12583+// OID_802_11_RSSI_TRIGGER
12584+// OID_802_11_NUMBER_OF_ANTENNAS
12585+// OID_802_11_RX_ANTENNA_SELECTED
12586+// OID_802_11_TX_ANTENNA_SELECTED
12587+// OID_802_11_STATISTICS
12588+// OID_802_11_DESIRED_RATES
12589+// OID_802_11_PRIVACY_FILTER
12590+
12591+*/
12592+
12593+/*------------------------- none-standard ----------------------------------*/
12594+s8 sme_get_connect_status(void *pcore_data, u8 *pstatus);
12595+
12596+/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
12597+//s8 sme_get_scan_type(void *pcore_data, u8 *pscan_type);
12598+//s8 sme_set_scan_type(void *pcore_data, u8 scan_type);
12599+
12600+//s8 sme_get_scan_channel_list(void *pcore_data, u8 *pscan_type);
12601+//s8 sme_set_scan_channel_list(void *pcore_data, u8 scan_type);
12602+
12603+
12604+void sme_get_encryption_status(void *pcore_data, u8 *EncryptStatus);
12605+void sme_set_encryption_status(void *pcore_data, u8 EncryptStatus);
12606+s8 sme_add_key(void *pcore_data,
12607+ u32 key_index,
12608+ u8 key_len,
12609+ u8 key_type,
12610+ u8 *key_bssid,
12611+ //u8 *key_rsc,
12612+ u8 *ptx_tsc,
12613+ u8 *prx_tsc,
12614+ u8 *key_material);
12615+void sme_remove_default_key(void *pcore_data, int index);
12616+void sme_remove_mapping_key(void *pcore_data, u8 *pmac_addr);
12617+void sme_clear_all_mapping_key(void *pcore_data);
12618+void sme_clear_all_default_key(void *pcore_data);
12619+
12620+
12621+
12622+s8 sme_set_preamble_mode(void *pcore_data, u8 mode);
12623+s8 sme_get_preamble_mode(void *pcore_data, u8 *mode);
12624+s8 sme_get_preamble_type(void *pcore_data, u8 *type);
12625+s8 sme_set_slottime_mode(void *pcore_data, u8 mode);
12626+s8 sme_get_slottime_mode(void *pcore_data, u8 *mode);
12627+s8 sme_get_slottime_type(void *pcore_data, u8 *type);
12628+s8 sme_set_txrate_policy(void *pcore_data, u8 policy);
12629+s8 sme_get_txrate_policy(void *pcore_data, u8 *policy);
12630+s8 sme_get_cwmin_value(void *pcore_data, u8 *cwmin);
12631+s8 sme_get_cwmax_value(void *pcore_data, u16 *cwmax);
12632+s8 sme_get_ms_radio_mode(void *pcore_data, u8 * pMsRadioOff);
12633+s8 sme_set_ms_radio_mode(void *pcore_data, u8 boMsRadioOff);
12634+s8 sme_get_radio_mode(void *pcore_data, psRadioOff pRadioOffData);
12635+s8 sme_set_radio_mode(void *pcore_data, RadioOff RadioOffData);
12636+
12637+void sme_get_tx_power_level(void *pcore_data, u32 *TxPower);
12638+u8 sme_set_tx_power_level(void *pcore_data, u32 TxPower);
12639+void sme_get_antenna_count(void *pcore_data, u32 *AntennaCount);
12640+void sme_get_rx_antenna(void *pcore_data, u32 *RxAntenna);
12641+u8 sme_set_rx_antenna(void *pcore_data, u32 RxAntenna);
12642+void sme_get_tx_antenna(void *pcore_data, u32 *TxAntenna);
12643+s8 sme_set_tx_antenna(void *pcore_data, u32 TxAntenna);
12644+s8 sme_set_IBSS_chan(void *pcore_data, ChanInfo chan);
12645+
12646+//20061108 WPS
12647+s8 sme_set_IE_append(void *pcore_data, PUCHAR buffer, u16 buf_len);
12648+
12649+
12650+
12651+
12652+//================== Local functions ======================
12653+//#ifdef _HSINCHU
12654+//void drv_translate_rssi(); // HW RSSI bit -> NDIS RSSI representation
12655+//void drv_translate_bss_description(); // Local bss desc -> NDIS bss desc
12656+//void drv_translate_channel(u8 NetworkType, u8 ChannelNumber, u32 *freq); // channel number -> channel /freq.
12657+//#endif _HSINCHU
12658+//
12659+static const u32 PowerDbToMw[] =
12660+{
12661+ 56, //mW, MAX - 0, 17.5 dbm
12662+ 40, //mW, MAX - 1, 16.0 dbm
12663+ 30, //mW, MAX - 2, 14.8 dbm
12664+ 20, //mW, MAX - 3, 13.0 dbm
12665+ 15, //mW, MAX - 4, 11.8 dbm
12666+ 12, //mW, MAX - 5, 10.6 dbm
12667+ 9, //mW, MAX - 6, 9.4 dbm
12668+ 7, //mW, MAX - 7, 8.3 dbm
12669+ 5, //mW, MAX - 8, 6.4 dbm
12670+ 4, //mW, MAX - 9, 5.3 dbm
12671+ 3, //mW, MAX - 10, 4.0 dbm
12672+ 2, //mW, MAX - 11, ? dbm
12673+ 2, //mW, MAX - 12, ? dbm
12674+ 2, //mW, MAX - 13, ? dbm
12675+ 2, //mW, MAX - 14, ? dbm
12676+ 2, //mW, MAX - 15, ? dbm
12677+ 2, //mW, MAX - 16, ? dbm
12678+ 2, //mW, MAX - 17, ? dbm
12679+ 2, //mW, MAX - 18, ? dbm
12680+ 1, //mW, MAX - 19, ? dbm
12681+ 1, //mW, MAX - 20, ? dbm
12682+ 1, //mW, MAX - 21, ? dbm
12683+ 1, //mW, MAX - 22, ? dbm
12684+ 1, //mW, MAX - 23, ? dbm
12685+ 1, //mW, MAX - 24, ? dbm
12686+ 1, //mW, MAX - 25, ? dbm
12687+ 1, //mW, MAX - 26, ? dbm
12688+ 1, //mW, MAX - 27, ? dbm
12689+ 1, //mW, MAX - 28, ? dbm
12690+ 1, //mW, MAX - 29, ? dbm
12691+ 1, //mW, MAX - 30, ? dbm
12692+ 1 //mW, MAX - 31, ? dbm
12693+};
12694+
12695+
12696+
12697+
12698+
12699+#endif /* __SME_API_H__ */
12700+
12701+
12702diff --git a/drivers/staging/winbond/sme_s.h b/drivers/staging/winbond/sme_s.h
12703new file mode 100644
12704index 0000000..dfd2fbc
12705--- /dev/null
12706+++ b/drivers/staging/winbond/sme_s.h
12707@@ -0,0 +1,228 @@
12708+//
12709+// SME_S.H -
12710+// SME task global CONSTANTS, STRUCTURES, variables
12711+//
12712+
12713+//////////////////////////////////////////////////////////////////////////
12714+//define the msg type of SME module
12715+// 0x00~0x1F : MSG from GUI dispatch
12716+// 0x20~0x3F : MSG from MLME
12717+// 0x40~0x5F : MSG from SCAN
12718+// 0x60~0x6F : MSG from TX/RX
12719+// 0x70~0x7F : MSG from ROAMING
12720+// 0x80~0x8F : MSG from ISR
12721+// 0x90 : MSG TimeOut
12722+
12723+// from GUI
12724+#define SMEMSG_SCAN_REQ 0x01
12725+//#define SMEMSG_PASSIVE_SCAN_REQ 0x02
12726+#define SMEMSG_JOIN_REQ 0x03
12727+#define SMEMSG_START_IBSS 0x04
12728+#define SMEMSG_DISCONNECT_REQ 0x05
12729+#define SMEMSG_AUTHEN_REQ 0x06
12730+#define SMEMSG_DEAUTHEN_REQ 0x07
12731+#define SMEMSG_ASSOC_REQ 0x08
12732+#define SMEMSG_REASSOC_REQ 0x09
12733+#define SMEMSG_DISASSOC_REQ 0x0a
12734+#define SMEMSG_POWERSAVE_REQ 0x0b
12735+
12736+
12737+// from MLME
12738+#define SMEMSG_AUTHEN_CFM 0x21
12739+#define SMEMSG_AUTHEN_IND 0x22
12740+#define SMEMSG_ASSOC_CFM 0x23
12741+#define SMEMSG_DEAUTHEN_IND 0x24
12742+#define SMEMSG_DISASSOC_IND 0x25
12743+// from SCAN
12744+#define SMEMSG_SCAN_CFM 0x41
12745+#define SMEMSG_START_IBSS_CFM 0x42
12746+// from MTO, function call to set SME parameters
12747+
12748+// 0x60~0x6F : MSG from TX/RX
12749+//#define SMEMSG_IBSS_JOIN_UPDATE_BSSID 0x61
12750+#define SMEMSG_COUNTERMEASURE_MICFAIL_TIMEOUT 0x62
12751+#define SMEMSG_COUNTERMEASURE_BLOCK_TIMEOUT 0x63
12752+// from ROAMING
12753+#define SMEMSG_HANDOVER_JOIN_REQ 0x71
12754+#define SMEMSG_END_ROAMING 0x72
12755+#define SMEMSG_SCAN_JOIN_REQ 0x73
12756+// from ISR
12757+#define SMEMSG_TSF_SYNC_IND 0x81
12758+// from TimeOut
12759+#define SMEMSG_TIMEOUT 0x91
12760+
12761+
12762+
12763+#define MAX_PMKID_Accunt 16
12764+//@added by ws 04/22/05
12765+#define Cipher_Disabled 0
12766+#define Cipher_Wep 1
12767+#define Cipher_Tkip 2
12768+#define Cipher_Ccmp 4
12769+
12770+
12771+///////////////////////////////////////////////////////////////////////////
12772+//Constants
12773+
12774+///////////////////////////////////////////////////////////////////////////
12775+//Global data structures
12776+
12777+#define NUMOFWEPENTRIES 64
12778+
12779+typedef enum _WEPKeyMode
12780+{
12781+ WEPKEY_DISABLED = 0,
12782+ WEPKEY_64 = 1,
12783+ WEPKEY_128 = 2
12784+
12785+} WEPKEYMODE, *pWEPKEYMODE;
12786+
12787+#ifdef _WPA2_
12788+
12789+typedef struct _BSSInfo
12790+{
12791+ u8 PreAuthBssID[6];
12792+ PMKID pmkid_value;
12793+}BSSID_Info;
12794+
12795+typedef struct _PMKID_Table //added by ws 05/05/04
12796+{
12797+ u32 Length;
12798+ u32 BSSIDInfoCount;
12799+ BSSID_Info BSSIDInfo[16];
12800+
12801+} PMKID_Table;
12802+
12803+#endif //end def _WPA2_
12804+
12805+#define MAX_BASIC_RATE_SET 15
12806+#define MAX_OPT_RATE_SET MAX_BASIC_RATE_SET
12807+
12808+
12809+typedef struct _SME_PARAMETERS
12810+{
12811+ u16 wState;
12812+ u8 boDUTmode;
12813+ u8 bDesiredPowerSave;
12814+
12815+ // SME timer and timeout value
12816+ //NDIS_MINIPORT_TIMER nTimer;
12817+ OS_TIMER nTimer;
12818+
12819+ u8 boInTimerHandler;
12820+ u8 boAuthRetryActive;
12821+ u8 reserved_0[2];
12822+
12823+ u32 AuthenRetryTimerVal; // NOTE: Assoc don't fail timeout
12824+ u32 JoinFailTimerVal; // 10*Beacon-Interval
12825+
12826+ //Rates
12827+ u8 BSSBasicRateSet[(MAX_BASIC_RATE_SET + 3) & ~0x03 ]; // BSS basic rate set
12828+ u8 OperationalRateSet[(MAX_OPT_RATE_SET + 3) & ~0x03 ]; // Operational rate set
12829+
12830+ u8 NumOfBSSBasicRate;
12831+ u8 NumOfOperationalRate;
12832+ u8 reserved_1[2];
12833+
12834+ u32 BasicRateBitmap;
12835+ u32 OpRateBitmap;
12836+
12837+ // System parameters Set by GUI
12838+ //-------------------- start IBSS parameter ---------------------------//
12839+ u32 boStartIBSS; //Start IBSS toggle
12840+
12841+ u16 wBeaconPeriod;
12842+ u16 wATIM_Window;
12843+
12844+ ChanInfo IbssChan; // 2B //channel setting when start IBSS
12845+ u8 reserved_2[2];
12846+
12847+ // Join related
12848+ u16 wDesiredJoinBSS; // BSS index which desire to join
12849+ u8 boJoinReq; //Join request toggle
12850+ u8 bDesiredBSSType; //for Join request
12851+
12852+ u16 wCapabilityInfo; // Used when invoking the MLME_Associate_request().
12853+ u16 wNonERPcapabilityInfo;
12854+
12855+ struct SSID_Element sDesiredSSID; // 34 B
12856+ u8 reserved_3[2];
12857+
12858+ u8 abDesiredBSSID[MAC_ADDR_LENGTH + 2];
12859+
12860+ u8 bJoinScanCount; // the time of scan-join action need to do
12861+ u8 bDesiredAuthMode; // AUTH_OPEN_SYSTEM or AUTH_SHARED_KEY
12862+ u8 reserved_4[2];
12863+
12864+ // Encryption parameters
12865+ u8 _dot11PrivacyInvoked;
12866+ u8 _dot11PrivacyOptionImplemented;
12867+ u8 reserved_5[2];
12868+
12869+ //@ ws added
12870+ u8 DesiredEncrypt;
12871+ u8 encrypt_status; //ENCRYPT_DISABLE, ENCRYPT_WEP, ENCRYPT_WEP_NOKEY, ENCRYPT_TKIP, ...
12872+ u8 key_length;
12873+ u8 pairwise_key_ok;
12874+
12875+ u8 group_key_ok;
12876+ u8 wpa_ok; // indicate the control port of 802.1x is open or close
12877+ u8 pairwise_key_type;
12878+ u8 group_key_type;
12879+
12880+ u32 _dot11WEPDefaultKeyID;
12881+
12882+ u8 tx_mic_key[8]; // TODO: 0627 kevin-TKIP
12883+ u8 rx_mic_key[8]; // TODO: 0627 kevin-TKIP
12884+ u8 group_tx_mic_key[8];
12885+ u8 group_rx_mic_key[8];
12886+
12887+// #ifdef _WPA_
12888+ u8 AssocReqVarIE[200];
12889+ u8 AssocRespVarIE[200];
12890+
12891+ u16 AssocReqVarLen;
12892+ u16 AssocRespVarLen;
12893+ u8 boReassoc; //use assoc. or reassoc.
12894+ u8 reserved_6[3];
12895+ u16 AssocRespCapability;
12896+ u16 AssocRespStatus;
12897+// #endif
12898+
12899+ #ifdef _WPA2_
12900+ u8 PmkIdTable[256];
12901+ u32 PmkidTableIndex;
12902+ #endif //end def _WPA2_
12903+
12904+} SME_PARAMETERS, *PSME_PARAMETERS;
12905+
12906+#define psSME (&(Adapter->sSmePara))
12907+
12908+#define wSMEGetCurrentSTAState(Adapter) ((u16)(Adapter)->sSmePara.wState)
12909+
12910+
12911+
12912+//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
12913+// SmeModule.h
12914+// Define the related definitions of SME module
12915+// history -- 01/14/03' created
12916+//
12917+//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
12918+
12919+//Define the state of SME module
12920+#define DISABLED 0
12921+#define INIT_SCAN 1
12922+#define SCAN_READY 2
12923+#define START_IBSS 3
12924+#define JOIN_PENDING 4
12925+#define JOIN_CFM 5
12926+#define AUTHENTICATE_PENDING 6
12927+#define AUTHENTICATED 7
12928+#define CONNECTED 8
12929+//#define EAP_STARTING 9
12930+//#define EAPOL_AUTHEN_PENDING 10
12931+//#define SECURE_CONNECTED 11
12932+
12933+
12934+// Static function
12935+
12936diff --git a/drivers/staging/winbond/wb35_ver.h b/drivers/staging/winbond/wb35_ver.h
12937new file mode 100644
12938index 0000000..2433bc0
12939--- /dev/null
12940+++ b/drivers/staging/winbond/wb35_ver.h
12941@@ -0,0 +1,30 @@
12942+//
12943+// Only define one of follow
12944+//
12945+
12946+#ifdef WB_WIN
12947+ #define VER_FILEVERSION 1,00,47,00
12948+ #define VER_FILEVERSION_STR "1.00.47.00"
12949+ #define WB32_DRIVER_MAJOR_VERSION 0x0100
12950+ #define WB32_DRIVER_MINOR_VERSION 0x4700
12951+#endif
12952+
12953+#ifdef WB_CE
12954+ #define VER_FILEVERSION 2,00,47,00
12955+ #define VER_FILEVERSION_STR "2.00.47.00"
12956+ #define WB32_DRIVER_MAJOR_VERSION 0x0200
12957+ #define WB32_DRIVER_MINOR_VERSION 0x4700
12958+#endif
12959+
12960+#ifdef WB_LINUX
12961+ #define VER_FILEVERSION 3,00,47,00
12962+ #define VER_FILEVERSION_STR "3.00.47.00"
12963+ #define WB32_DRIVER_MAJOR_VERSION 0x0300
12964+ #define WB32_DRIVER_MINOR_VERSION 0x4700
12965+#endif
12966+
12967+
12968+
12969+
12970+
12971+
12972diff --git a/drivers/staging/winbond/wbhal.c b/drivers/staging/winbond/wbhal.c
12973new file mode 100644
12974index 0000000..daf4422
12975--- /dev/null
12976+++ b/drivers/staging/winbond/wbhal.c
12977@@ -0,0 +1,878 @@
12978+#include "os_common.h"
12979+
12980+void hal_get_ethernet_address( phw_data_t pHwData, PUCHAR current_address )
12981+{
12982+ if( pHwData->SurpriseRemove ) return;
12983+
12984+ memcpy( current_address, pHwData->CurrentMacAddress, ETH_LENGTH_OF_ADDRESS );
12985+}
12986+
12987+void hal_set_ethernet_address( phw_data_t pHwData, PUCHAR current_address )
12988+{
12989+ u32 ltmp[2];
12990+
12991+ if( pHwData->SurpriseRemove ) return;
12992+
12993+ memcpy( pHwData->CurrentMacAddress, current_address, ETH_LENGTH_OF_ADDRESS );
12994+
12995+ ltmp[0]= cpu_to_le32( *(PULONG)pHwData->CurrentMacAddress );
12996+ ltmp[1]= cpu_to_le32( *(PULONG)(pHwData->CurrentMacAddress + 4) ) & 0xffff;
12997+
12998+ Wb35Reg_BurstWrite( pHwData, 0x03e8, ltmp, 2, AUTO_INCREMENT );
12999+}
13000+
13001+void hal_get_permanent_address( phw_data_t pHwData, PUCHAR pethernet_address )
13002+{
13003+ if( pHwData->SurpriseRemove ) return;
13004+
13005+ memcpy( pethernet_address, pHwData->PermanentMacAddress, 6 );
13006+}
13007+
13008+u8 hal_init_hardware(phw_data_t pHwData, PWB32_ADAPTER Adapter)
13009+{
13010+ u16 SoftwareSet;
13011+ pHwData->Adapter = Adapter;
13012+
13013+ // Initial the variable
13014+ pHwData->MaxReceiveLifeTime = DEFAULT_MSDU_LIFE_TIME; // Setting Rx maximum MSDU life time
13015+ pHwData->FragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD; // Setting default fragment threshold
13016+
13017+ if (WbUsb_initial(pHwData)) {
13018+ pHwData->InitialResource = 1;
13019+ if( Wb35Reg_initial(pHwData)) {
13020+ pHwData->InitialResource = 2;
13021+ if (Wb35Tx_initial(pHwData)) {
13022+ pHwData->InitialResource = 3;
13023+ if (Wb35Rx_initial(pHwData)) {
13024+ pHwData->InitialResource = 4;
13025+ OS_TIMER_INITIAL( &pHwData->LEDTimer, hal_led_control, pHwData );
13026+ OS_TIMER_SET( &pHwData->LEDTimer, 1000 ); // 20060623
13027+
13028+ //
13029+ // For restrict to vendor's hardware
13030+ //
13031+ SoftwareSet = hal_software_set( pHwData );
13032+
13033+ #ifdef Vendor2
13034+ // Try to make sure the EEPROM contain
13035+ SoftwareSet >>= 8;
13036+ if( SoftwareSet != 0x82 )
13037+ return FALSE;
13038+ #endif
13039+
13040+ Wb35Rx_start( pHwData );
13041+ Wb35Tx_EP2VM_start( pHwData );
13042+
13043+ return TRUE;
13044+ }
13045+ }
13046+ }
13047+ }
13048+
13049+ pHwData->SurpriseRemove = 1;
13050+ return FALSE;
13051+}
13052+
13053+
13054+void hal_halt(phw_data_t pHwData, void *ppa_data)
13055+{
13056+ switch( pHwData->InitialResource )
13057+ {
13058+ case 4:
13059+ case 3: OS_TIMER_CANCEL( &pHwData->LEDTimer, &cancel );
13060+ OS_SLEEP(100000); // Wait for Timer DPC exit 940623.2
13061+ Wb35Rx_destroy( pHwData ); // Release the Rx
13062+ case 2: Wb35Tx_destroy( pHwData ); // Release the Tx
13063+ case 1: Wb35Reg_destroy( pHwData ); // Release the Wb35 Regisster resources
13064+ WbUsb_destroy( pHwData );// Release the WbUsb
13065+ }
13066+}
13067+
13068+//---------------------------------------------------------------------------------------------------
13069+void hal_set_rates(phw_data_t pHwData, PUCHAR pbss_rates,
13070+ u8 length, unsigned char basic_rate_set)
13071+{
13072+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
13073+ u32 tmp, tmp1;
13074+ u8 Rate[12]={ 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 };
13075+ u8 SupportedRate[16];
13076+ u8 i, j, k, Count1, Count2, Byte;
13077+
13078+ if( pHwData->SurpriseRemove ) return;
13079+
13080+ if (basic_rate_set) {
13081+ pWb35Reg->M28_MacControl &= ~0x000fff00;
13082+ tmp1 = 0x00000100;
13083+ } else {
13084+ pWb35Reg->M28_MacControl &= ~0xfff00000;
13085+ tmp1 = 0x00100000;
13086+ }
13087+
13088+ tmp = 0;
13089+ for (i=0; i<length; i++) {
13090+ Byte = pbss_rates[i] & 0x7f;
13091+ for (j=0; j<12; j++) {
13092+ if( Byte == Rate[j] )
13093+ break;
13094+ }
13095+
13096+ if (j < 12)
13097+ tmp |= (tmp1<<j);
13098+ }
13099+
13100+ pWb35Reg->M28_MacControl |= tmp;
13101+ Wb35Reg_Write( pHwData, 0x0828, pWb35Reg->M28_MacControl );
13102+
13103+ // 930206.2.c M78 setting
13104+ j = k = Count1 = Count2 = 0;
13105+ memset( SupportedRate, 0, 16 );
13106+ tmp = 0x00100000;
13107+ tmp1 = 0x00000100;
13108+ for (i=0; i<12; i++) { // Get the supported rate
13109+ if (tmp & pWb35Reg->M28_MacControl) {
13110+ SupportedRate[j] = Rate[i];
13111+
13112+ if (tmp1 & pWb35Reg->M28_MacControl)
13113+ SupportedRate[j] |= 0x80;
13114+
13115+ if (k)
13116+ Count2++;
13117+ else
13118+ Count1++;
13119+
13120+ j++;
13121+ }
13122+
13123+ if (i==4 && k==0) {
13124+ if( !(pWb35Reg->M28_MacControl & 0x000ff000) ) // if basic rate in 11g domain)
13125+ {
13126+ k = 1;
13127+ j = 8;
13128+ }
13129+ }
13130+
13131+ tmp <<= 1;
13132+ tmp1 <<= 1;
13133+ }
13134+
13135+ // Fill data into support rate until buffer full
13136+ //---20060926 add by anson's endian
13137+ for (i=0; i<4; i++)
13138+ *(PULONG)(SupportedRate+(i<<2)) = cpu_to_le32( *(PULONG)(SupportedRate+(i<<2)) );
13139+ //--- end 20060926 add by anson's endian
13140+ Wb35Reg_BurstWrite( pHwData,0x087c, (PULONG)SupportedRate, 4, AUTO_INCREMENT );
13141+ pWb35Reg->M7C_MacControl = ((PULONG)SupportedRate)[0];
13142+ pWb35Reg->M80_MacControl = ((PULONG)SupportedRate)[1];
13143+ pWb35Reg->M84_MacControl = ((PULONG)SupportedRate)[2];
13144+ pWb35Reg->M88_MacControl = ((PULONG)SupportedRate)[3];
13145+
13146+ // Fill length
13147+ tmp = Count1<<28 | Count2<<24;
13148+ pWb35Reg->M78_ERPInformation &= ~0xff000000;
13149+ pWb35Reg->M78_ERPInformation |= tmp;
13150+ Wb35Reg_Write( pHwData, 0x0878, pWb35Reg->M78_ERPInformation );
13151+}
13152+
13153+
13154+//---------------------------------------------------------------------------------------------------
13155+void hal_set_beacon_period( phw_data_t pHwData, u16 beacon_period )
13156+{
13157+ u32 tmp;
13158+
13159+ if( pHwData->SurpriseRemove ) return;
13160+
13161+ pHwData->BeaconPeriod = beacon_period;
13162+ tmp = pHwData->BeaconPeriod << 16;
13163+ tmp |= pHwData->ProbeDelay;
13164+ Wb35Reg_Write( pHwData, 0x0848, tmp );
13165+}
13166+
13167+
13168+void hal_set_current_channel_ex( phw_data_t pHwData, ChanInfo channel )
13169+{
13170+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
13171+
13172+ if( pHwData->SurpriseRemove )
13173+ return;
13174+
13175+ printk("Going to channel: %d/%d\n", channel.band, channel.ChanNo);
13176+
13177+ RFSynthesizer_SwitchingChannel( pHwData, channel );// Switch channel
13178+ pHwData->Channel = channel.ChanNo;
13179+ pHwData->band = channel.band;
13180+ #ifdef _PE_STATE_DUMP_
13181+ WBDEBUG(("Set channel is %d, band =%d\n", pHwData->Channel, pHwData->band));
13182+ #endif
13183+ pWb35Reg->M28_MacControl &= ~0xff; // Clean channel information field
13184+ pWb35Reg->M28_MacControl |= channel.ChanNo;
13185+ Wb35Reg_WriteWithCallbackValue( pHwData, 0x0828, pWb35Reg->M28_MacControl,
13186+ (PCHAR)&channel, sizeof(ChanInfo));
13187+}
13188+//---------------------------------------------------------------------------------------------------
13189+void hal_set_current_channel( phw_data_t pHwData, ChanInfo channel )
13190+{
13191+ hal_set_current_channel_ex( pHwData, channel );
13192+}
13193+//---------------------------------------------------------------------------------------------------
13194+void hal_get_current_channel( phw_data_t pHwData, ChanInfo *channel )
13195+{
13196+ channel->ChanNo = pHwData->Channel;
13197+ channel->band = pHwData->band;
13198+}
13199+//---------------------------------------------------------------------------------------------------
13200+void hal_set_accept_broadcast( phw_data_t pHwData, u8 enable )
13201+{
13202+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
13203+
13204+ if( pHwData->SurpriseRemove ) return;
13205+
13206+ pWb35Reg->M00_MacControl &= ~0x02000000;//The HW value
13207+
13208+ if (enable)
13209+ pWb35Reg->M00_MacControl |= 0x02000000;//The HW value
13210+
13211+ Wb35Reg_Write( pHwData, 0x0800, pWb35Reg->M00_MacControl );
13212+}
13213+
13214+//for wep key error detection, we need to accept broadcast packets to be received temporary.
13215+void hal_set_accept_promiscuous( phw_data_t pHwData, u8 enable)
13216+{
13217+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
13218+
13219+ if (pHwData->SurpriseRemove) return;
13220+ if (enable) {
13221+ pWb35Reg->M00_MacControl |= 0x00400000;
13222+ Wb35Reg_Write( pHwData, 0x0800, pWb35Reg->M00_MacControl );
13223+ } else {
13224+ pWb35Reg->M00_MacControl&=~0x00400000;
13225+ Wb35Reg_Write( pHwData, 0x0800, pWb35Reg->M00_MacControl );
13226+ }
13227+}
13228+
13229+void hal_set_accept_multicast( phw_data_t pHwData, u8 enable )
13230+{
13231+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
13232+
13233+ if( pHwData->SurpriseRemove ) return;
13234+
13235+ pWb35Reg->M00_MacControl &= ~0x01000000;//The HW value
13236+ if (enable) pWb35Reg->M00_MacControl |= 0x01000000;//The HW value
13237+ Wb35Reg_Write( pHwData, 0x0800, pWb35Reg->M00_MacControl );
13238+}
13239+
13240+void hal_set_accept_beacon( phw_data_t pHwData, u8 enable )
13241+{
13242+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
13243+
13244+ if( pHwData->SurpriseRemove ) return;
13245+
13246+ // 20040108 debug
13247+ if( !enable )//Due to SME and MLME are not suitable for 35
13248+ return;
13249+
13250+ pWb35Reg->M00_MacControl &= ~0x04000000;//The HW value
13251+ if( enable )
13252+ pWb35Reg->M00_MacControl |= 0x04000000;//The HW value
13253+
13254+ Wb35Reg_Write( pHwData, 0x0800, pWb35Reg->M00_MacControl );
13255+}
13256+//---------------------------------------------------------------------------------------------------
13257+void hal_set_multicast_address( phw_data_t pHwData, PUCHAR address, u8 number )
13258+{
13259+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
13260+ u8 Byte, Bit;
13261+
13262+ if( pHwData->SurpriseRemove ) return;
13263+
13264+ //Erases and refills the card multicast registers. Used when an address
13265+ // has been deleted and all bits must be recomputed.
13266+ pWb35Reg->M04_MulticastAddress1 = 0;
13267+ pWb35Reg->M08_MulticastAddress2 = 0;
13268+
13269+ while( number )
13270+ {
13271+ number--;
13272+ CardGetMulticastBit( (address+(number*ETH_LENGTH_OF_ADDRESS)), &Byte, &Bit);
13273+ pWb35Reg->Multicast[Byte] |= Bit;
13274+ }
13275+
13276+ // Updating register
13277+ Wb35Reg_BurstWrite( pHwData, 0x0804, (PULONG)pWb35Reg->Multicast, 2, AUTO_INCREMENT );
13278+}
13279+//---------------------------------------------------------------------------------------------------
13280+u8 hal_get_accept_beacon( phw_data_t pHwData )
13281+{
13282+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
13283+
13284+ if( pHwData->SurpriseRemove ) return 0;
13285+
13286+ if( pWb35Reg->M00_MacControl & 0x04000000 )
13287+ return 1;
13288+ else
13289+ return 0;
13290+}
13291+
13292+unsigned char hal_reset_hardware( phw_data_t pHwData, void* ppa )
13293+{
13294+ // Not implement yet
13295+ return TRUE;
13296+}
13297+
13298+void hal_stop( phw_data_t pHwData )
13299+{
13300+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
13301+
13302+ pHwData->Wb35Rx.rx_halt = 1;
13303+ Wb35Rx_stop( pHwData );
13304+
13305+ pHwData->Wb35Tx.tx_halt = 1;
13306+ Wb35Tx_stop( pHwData );
13307+
13308+ pWb35Reg->D00_DmaControl &= ~0xc0000000;//Tx Off, Rx Off
13309+ Wb35Reg_Write( pHwData, 0x0400, pWb35Reg->D00_DmaControl );
13310+
13311+ WbUsb_Stop( pHwData ); // 20051230 Add.4
13312+}
13313+
13314+unsigned char hal_idle(phw_data_t pHwData)
13315+{
13316+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
13317+ PWBUSB pWbUsb = &pHwData->WbUsb;
13318+
13319+ if( !pHwData->SurpriseRemove && ( pWbUsb->DetectCount || pWb35Reg->EP0vm_state!=VM_STOP ) )
13320+ return FALSE;
13321+
13322+ return TRUE;
13323+}
13324+//---------------------------------------------------------------------------------------------------
13325+void hal_set_cwmin( phw_data_t pHwData, u8 cwin_min )
13326+{
13327+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
13328+
13329+ if( pHwData->SurpriseRemove ) return;
13330+
13331+ pHwData->cwmin = cwin_min;
13332+ pWb35Reg->M2C_MacControl &= ~0x7c00; //bit 10 ~ 14
13333+ pWb35Reg->M2C_MacControl |= (pHwData->cwmin<<10);
13334+ Wb35Reg_Write( pHwData, 0x082c, pWb35Reg->M2C_MacControl );
13335+}
13336+
13337+s32 hal_get_rssi( phw_data_t pHwData, u32 *HalRssiArry, u8 Count )
13338+{
13339+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
13340+ R01_DESCRIPTOR r01;
13341+ s32 ltmp = 0, tmp;
13342+ u8 i;
13343+
13344+ if( pHwData->SurpriseRemove ) return -200;
13345+ if( Count > MAX_ACC_RSSI_COUNT ) // Because the TS may use this funtion
13346+ Count = MAX_ACC_RSSI_COUNT;
13347+
13348+ // RSSI = C1 + C2 * (agc_state[7:0] + offset_map(lna_state[1:0]))
13349+ // C1 = -195, C2 = 0.66 = 85/128
13350+ for (i=0; i<Count; i++)
13351+ {
13352+ r01.value = HalRssiArry[i];
13353+ tmp = ((( r01.R01_AGC_state + pWb35Reg->LNAValue[r01.R01_LNA_state]) * 85 ) >>7 ) - 195;
13354+ ltmp += tmp;
13355+ }
13356+ ltmp /= Count;
13357+ if( pHwData->phy_type == RF_AIROHA_2230 ) ltmp -= 5; // 10;
13358+ if( pHwData->phy_type == RF_AIROHA_2230S ) ltmp -= 5; // 10; 20060420 Add this
13359+
13360+ //if( ltmp < -200 ) ltmp = -200;
13361+ if( ltmp < -110 ) ltmp = -110;// 1.0.24.0 For NJRC
13362+
13363+ return ltmp;
13364+}
13365+//----------------------------------------------------------------------------------------------------
13366+s32 hal_get_rssi_bss( phw_data_t pHwData, u16 idx, u8 Count )
13367+{
13368+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
13369+ R01_DESCRIPTOR r01;
13370+ s32 ltmp = 0, tmp;
13371+ u8 i, j;
13372+ PADAPTER Adapter = pHwData->Adapter;
13373+// u32 *HalRssiArry = psBSS(idx)->HalRssi;
13374+
13375+ if( pHwData->SurpriseRemove ) return -200;
13376+ if( Count > MAX_ACC_RSSI_COUNT ) // Because the TS may use this funtion
13377+ Count = MAX_ACC_RSSI_COUNT;
13378+
13379+ // RSSI = C1 + C2 * (agc_state[7:0] + offset_map(lna_state[1:0]))
13380+ // C1 = -195, C2 = 0.66 = 85/128
13381+#if 0
13382+ for (i=0; i<Count; i++)
13383+ {
13384+ r01.value = HalRssiArry[i];
13385+ tmp = ((( r01.R01_AGC_state + pWb35Reg->LNAValue[r01.R01_LNA_state]) * 85 ) >>7 ) - 195;
13386+ ltmp += tmp;
13387+ }
13388+#else
13389+ if (psBSS(idx)->HalRssiIndex == 0)
13390+ psBSS(idx)->HalRssiIndex = MAX_ACC_RSSI_COUNT;
13391+ j = (u8)psBSS(idx)->HalRssiIndex-1;
13392+
13393+ for (i=0; i<Count; i++)
13394+ {
13395+ r01.value = psBSS(idx)->HalRssi[j];
13396+ tmp = ((( r01.R01_AGC_state + pWb35Reg->LNAValue[r01.R01_LNA_state]) * 85 ) >>7 ) - 195;
13397+ ltmp += tmp;
13398+ if (j == 0)
13399+ {
13400+ j = MAX_ACC_RSSI_COUNT;
13401+ }
13402+ j--;
13403+ }
13404+#endif
13405+ ltmp /= Count;
13406+ if( pHwData->phy_type == RF_AIROHA_2230 ) ltmp -= 5; // 10;
13407+ if( pHwData->phy_type == RF_AIROHA_2230S ) ltmp -= 5; // 10; 20060420 Add this
13408+
13409+ //if( ltmp < -200 ) ltmp = -200;
13410+ if( ltmp < -110 ) ltmp = -110;// 1.0.24.0 For NJRC
13411+
13412+ return ltmp;
13413+}
13414+
13415+//---------------------------------------------------------------------------
13416+void hal_led_control_1a( phw_data_t pHwData )
13417+{
13418+ hal_led_control( NULL, pHwData, NULL, NULL );
13419+}
13420+
13421+void hal_led_control( void* S1, phw_data_t pHwData, void* S3, void* S4 )
13422+{
13423+ PADAPTER Adapter = pHwData->Adapter;
13424+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
13425+ u32 LEDSet = (pHwData->SoftwareSet & HAL_LED_SET_MASK) >> HAL_LED_SET_SHIFT;
13426+ u8 LEDgray[20] = { 0,3,4,6,8,10,11,12,13,14,15,14,13,12,11,10,8,6,4,2 };
13427+ u8 LEDgray2[30] = { 7,8,9,10,11,12,13,14,15,0,0,0,0,0,0,0,0,0,0,0,0,0,15,14,13,12,11,10,9,8 };
13428+ u32 TimeInterval = 500, ltmp, ltmp2;
13429+ ltmp=0;
13430+
13431+ if( pHwData->SurpriseRemove ) return;
13432+
13433+ if( pHwData->LED_control ) {
13434+ ltmp2 = pHwData->LED_control & 0xff;
13435+ if( ltmp2 == 5 ) // 5 is WPS mode
13436+ {
13437+ TimeInterval = 100;
13438+ ltmp2 = (pHwData->LED_control>>8) & 0xff;
13439+ switch( ltmp2 )
13440+ {
13441+ case 1: // [0.2 On][0.1 Off]...
13442+ pHwData->LED_Blinking %= 3;
13443+ ltmp = 0x1010; // Led 1 & 0 Green and Red
13444+ if( pHwData->LED_Blinking == 2 ) // Turn off
13445+ ltmp = 0;
13446+ break;
13447+ case 2: // [0.1 On][0.1 Off]...
13448+ pHwData->LED_Blinking %= 2;
13449+ ltmp = 0x0010; // Led 0 red color
13450+ if( pHwData->LED_Blinking ) // Turn off
13451+ ltmp = 0;
13452+ break;
13453+ case 3: // [0.1 On][0.1 Off][0.1 On][0.1 Off][0.1 On][0.1 Off][0.1 On][0.1 Off][0.1 On][0.1 Off][0.5 Off]...
13454+ pHwData->LED_Blinking %= 15;
13455+ ltmp = 0x0010; // Led 0 red color
13456+ if( (pHwData->LED_Blinking >= 9) || (pHwData->LED_Blinking%2) ) // Turn off 0.6 sec
13457+ ltmp = 0;
13458+ break;
13459+ case 4: // [300 On][ off ]
13460+ ltmp = 0x1000; // Led 1 Green color
13461+ if( pHwData->LED_Blinking >= 3000 )
13462+ ltmp = 0; // led maybe on after 300sec * 32bit counter overlap.
13463+ break;
13464+ }
13465+ pHwData->LED_Blinking++;
13466+
13467+ pWb35Reg->U1BC_LEDConfigure = ltmp;
13468+ if( LEDSet != 7 ) // Only 111 mode has 2 LEDs on PCB.
13469+ {
13470+ pWb35Reg->U1BC_LEDConfigure |= (ltmp &0xff)<<8; // Copy LED result to each LED control register
13471+ pWb35Reg->U1BC_LEDConfigure |= (ltmp &0xff00)>>8;
13472+ }
13473+ Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure );
13474+ }
13475+ }
13476+ else if( pHwData->CurrentRadioSw || pHwData->CurrentRadioHw ) // If radio off
13477+ {
13478+ if( pWb35Reg->U1BC_LEDConfigure & 0x1010 )
13479+ {
13480+ pWb35Reg->U1BC_LEDConfigure &= ~0x1010;
13481+ Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure );
13482+ }
13483+ }
13484+ else
13485+ {
13486+ switch( LEDSet )
13487+ {
13488+ case 4: // [100] Only 1 Led be placed on PCB and use pin 21 of IC. Use LED_0 for showing
13489+ if( !pHwData->LED_LinkOn ) // Blink only if not Link On
13490+ {
13491+ // Blinking if scanning is on progress
13492+ if( pHwData->LED_Scanning )
13493+ {
13494+ if( pHwData->LED_Blinking == 0 )
13495+ {
13496+ pWb35Reg->U1BC_LEDConfigure |= 0x10;
13497+ Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 On
13498+ pHwData->LED_Blinking = 1;
13499+ TimeInterval = 300;
13500+ }
13501+ else
13502+ {
13503+ pWb35Reg->U1BC_LEDConfigure &= ~0x10;
13504+ Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 Off
13505+ pHwData->LED_Blinking = 0;
13506+ TimeInterval = 300;
13507+ }
13508+ }
13509+ else
13510+ {
13511+ //Turn Off LED_0
13512+ if( pWb35Reg->U1BC_LEDConfigure & 0x10 )
13513+ {
13514+ pWb35Reg->U1BC_LEDConfigure &= ~0x10;
13515+ Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 Off
13516+ }
13517+ }
13518+ }
13519+ else
13520+ {
13521+ // Turn On LED_0
13522+ if( (pWb35Reg->U1BC_LEDConfigure & 0x10) == 0 )
13523+ {
13524+ pWb35Reg->U1BC_LEDConfigure |= 0x10;
13525+ Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 Off
13526+ }
13527+ }
13528+ break;
13529+
13530+ case 6: // [110] Only 1 Led be placed on PCB and use pin 21 of IC. Use LED_0 for showing
13531+ if( !pHwData->LED_LinkOn ) // Blink only if not Link On
13532+ {
13533+ // Blinking if scanning is on progress
13534+ if( pHwData->LED_Scanning )
13535+ {
13536+ if( pHwData->LED_Blinking == 0 )
13537+ {
13538+ pWb35Reg->U1BC_LEDConfigure &= ~0xf;
13539+ pWb35Reg->U1BC_LEDConfigure |= 0x10;
13540+ Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 On
13541+ pHwData->LED_Blinking = 1;
13542+ TimeInterval = 300;
13543+ }
13544+ else
13545+ {
13546+ pWb35Reg->U1BC_LEDConfigure &= ~0x1f;
13547+ Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 Off
13548+ pHwData->LED_Blinking = 0;
13549+ TimeInterval = 300;
13550+ }
13551+ }
13552+ else
13553+ {
13554+ // 20060901 Gray blinking if in disconnect state and not scanning
13555+ ltmp = pWb35Reg->U1BC_LEDConfigure;
13556+ pWb35Reg->U1BC_LEDConfigure &= ~0x1f;
13557+ if( LEDgray2[(pHwData->LED_Blinking%30)] )
13558+ {
13559+ pWb35Reg->U1BC_LEDConfigure |= 0x10;
13560+ pWb35Reg->U1BC_LEDConfigure |= LEDgray2[ (pHwData->LED_Blinking%30) ];
13561+ }
13562+ pHwData->LED_Blinking++;
13563+ if( pWb35Reg->U1BC_LEDConfigure != ltmp )
13564+ Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 Off
13565+ TimeInterval = 100;
13566+ }
13567+ }
13568+ else
13569+ {
13570+ // Turn On LED_0
13571+ if( (pWb35Reg->U1BC_LEDConfigure & 0x10) == 0 )
13572+ {
13573+ pWb35Reg->U1BC_LEDConfigure |= 0x10;
13574+ Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 Off
13575+ }
13576+ }
13577+ break;
13578+
13579+ case 5: // [101] Only 1 Led be placed on PCB and use LED_1 for showing
13580+ if( !pHwData->LED_LinkOn ) // Blink only if not Link On
13581+ {
13582+ // Blinking if scanning is on progress
13583+ if( pHwData->LED_Scanning )
13584+ {
13585+ if( pHwData->LED_Blinking == 0 )
13586+ {
13587+ pWb35Reg->U1BC_LEDConfigure |= 0x1000;
13588+ Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_1 On
13589+ pHwData->LED_Blinking = 1;
13590+ TimeInterval = 300;
13591+ }
13592+ else
13593+ {
13594+ pWb35Reg->U1BC_LEDConfigure &= ~0x1000;
13595+ Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_1 Off
13596+ pHwData->LED_Blinking = 0;
13597+ TimeInterval = 300;
13598+ }
13599+ }
13600+ else
13601+ {
13602+ //Turn Off LED_1
13603+ if( pWb35Reg->U1BC_LEDConfigure & 0x1000 )
13604+ {
13605+ pWb35Reg->U1BC_LEDConfigure &= ~0x1000;
13606+ Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_1 Off
13607+ }
13608+ }
13609+ }
13610+ else
13611+ {
13612+ // Is transmitting/receiving ??
13613+ if( (OS_CURRENT_RX_BYTE( Adapter ) != pHwData->RxByteCountLast ) ||
13614+ (OS_CURRENT_TX_BYTE( Adapter ) != pHwData->TxByteCountLast ) )
13615+ {
13616+ if( (pWb35Reg->U1BC_LEDConfigure & 0x3000) != 0x3000 )
13617+ {
13618+ pWb35Reg->U1BC_LEDConfigure |= 0x3000;
13619+ Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_1 On
13620+ }
13621+
13622+ // Update variable
13623+ pHwData->RxByteCountLast = OS_CURRENT_RX_BYTE( Adapter );
13624+ pHwData->TxByteCountLast = OS_CURRENT_TX_BYTE( Adapter );
13625+ TimeInterval = 200;
13626+ }
13627+ else
13628+ {
13629+ // Turn On LED_1 and blinking if transmitting/receiving
13630+ if( (pWb35Reg->U1BC_LEDConfigure & 0x3000) != 0x1000 )
13631+ {
13632+ pWb35Reg->U1BC_LEDConfigure &= ~0x3000;
13633+ pWb35Reg->U1BC_LEDConfigure |= 0x1000;
13634+ Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_1 On
13635+ }
13636+ }
13637+ }
13638+ break;
13639+
13640+ default: // Default setting. 2 LED be placed on PCB. LED_0: Link On LED_1 Active
13641+ if( (pWb35Reg->U1BC_LEDConfigure & 0x3000) != 0x3000 )
13642+ {
13643+ pWb35Reg->U1BC_LEDConfigure |= 0x3000;// LED_1 is always on and event enable
13644+ Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure );
13645+ }
13646+
13647+ if( pHwData->LED_Blinking )
13648+ {
13649+ // Gray blinking
13650+ pWb35Reg->U1BC_LEDConfigure &= ~0x0f;
13651+ pWb35Reg->U1BC_LEDConfigure |= 0x10;
13652+ pWb35Reg->U1BC_LEDConfigure |= LEDgray[ (pHwData->LED_Blinking-1)%20 ];
13653+ Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure );
13654+
13655+ pHwData->LED_Blinking += 2;
13656+ if( pHwData->LED_Blinking < 40 )
13657+ TimeInterval = 100;
13658+ else
13659+ {
13660+ pHwData->LED_Blinking = 0; // Stop blinking
13661+ pWb35Reg->U1BC_LEDConfigure &= ~0x0f;
13662+ Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure );
13663+ }
13664+ break;
13665+ }
13666+
13667+ if( pHwData->LED_LinkOn )
13668+ {
13669+ if( !(pWb35Reg->U1BC_LEDConfigure & 0x10) ) // Check the LED_0
13670+ {
13671+ //Try to turn ON LED_0 after gray blinking
13672+ pWb35Reg->U1BC_LEDConfigure |= 0x10;
13673+ pHwData->LED_Blinking = 1; //Start blinking
13674+ TimeInterval = 50;
13675+ }
13676+ }
13677+ else
13678+ {
13679+ if( pWb35Reg->U1BC_LEDConfigure & 0x10 ) // Check the LED_0
13680+ {
13681+ pWb35Reg->U1BC_LEDConfigure &= ~0x10;
13682+ Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure );
13683+ }
13684+ }
13685+ break;
13686+ }
13687+
13688+ //20060828.1 Active send null packet to avoid AP disconnect
13689+ if( pHwData->LED_LinkOn )
13690+ {
13691+ pHwData->NullPacketCount += TimeInterval;
13692+ if( pHwData->NullPacketCount >= DEFAULT_NULL_PACKET_COUNT )
13693+ {
13694+ pHwData->NullPacketCount = 0;
13695+ }
13696+ }
13697+ }
13698+
13699+ pHwData->time_count += TimeInterval;
13700+ Wb35Tx_CurrentTime( pHwData, pHwData->time_count ); // 20060928 add
13701+ OS_TIMER_SET( &pHwData->LEDTimer, TimeInterval ); // 20060623.1
13702+}
13703+
13704+
13705+void hal_set_phy_type( phw_data_t pHwData, u8 PhyType )
13706+{
13707+ pHwData->phy_type = PhyType;
13708+}
13709+
13710+void hal_get_phy_type( phw_data_t pHwData, u8 *PhyType )
13711+{
13712+ *PhyType = pHwData->phy_type;
13713+}
13714+
13715+void hal_reset_counter( phw_data_t pHwData )
13716+{
13717+ pHwData->dto_tx_retry_count = 0;
13718+ pHwData->dto_tx_frag_count = 0;
13719+ memset( pHwData->tx_retry_count, 0, 8);
13720+}
13721+
13722+void hal_set_radio_mode( phw_data_t pHwData, unsigned char radio_off)
13723+{
13724+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
13725+
13726+ if( pHwData->SurpriseRemove ) return;
13727+
13728+ if (radio_off) //disable Baseband receive off
13729+ {
13730+ pHwData->CurrentRadioSw = 1; // off
13731+ pWb35Reg->M24_MacControl &= 0xffffffbf;
13732+ }
13733+ else
13734+ {
13735+ pHwData->CurrentRadioSw = 0; // on
13736+ pWb35Reg->M24_MacControl |= 0x00000040;
13737+ }
13738+ Wb35Reg_Write( pHwData, 0x0824, pWb35Reg->M24_MacControl );
13739+}
13740+
13741+u8 hal_get_antenna_number( phw_data_t pHwData )
13742+{
13743+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
13744+
13745+ if ((pWb35Reg->BB2C & BIT(11)) == 0)
13746+ return 0;
13747+ else
13748+ return 1;
13749+}
13750+
13751+void hal_set_antenna_number( phw_data_t pHwData, u8 number )
13752+{
13753+
13754+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
13755+
13756+ if (number == 1) {
13757+ pWb35Reg->BB2C |= BIT(11);
13758+ } else {
13759+ pWb35Reg->BB2C &= ~BIT(11);
13760+ }
13761+ Wb35Reg_Write( pHwData, 0x102c, pWb35Reg->BB2C );
13762+#ifdef _PE_STATE_DUMP_
13763+ WBDEBUG(("Current antenna number : %d\n", number));
13764+#endif
13765+}
13766+
13767+//----------------------------------------------------------------------------------------------------
13768+//0 : radio on; 1: radio off
13769+u8 hal_get_hw_radio_off( phw_data_t pHwData )
13770+{
13771+ PWB35REG pWb35Reg = &pHwData->Wb35Reg;
13772+
13773+ if( pHwData->SurpriseRemove ) return 1;
13774+
13775+ //read the bit16 of register U1B0
13776+ Wb35Reg_Read( pHwData, 0x3b0, &pWb35Reg->U1B0 );
13777+ if ((pWb35Reg->U1B0 & 0x00010000)) {
13778+ pHwData->CurrentRadioHw = 1;
13779+ return 1;
13780+ } else {
13781+ pHwData->CurrentRadioHw = 0;
13782+ return 0;
13783+ }
13784+}
13785+
13786+unsigned char hal_get_dxx_reg( phw_data_t pHwData, u16 number, PULONG pValue )
13787+{
13788+ if( number < 0x1000 )
13789+ number += 0x1000;
13790+ return Wb35Reg_ReadSync( pHwData, number, pValue );
13791+}
13792+
13793+unsigned char hal_set_dxx_reg( phw_data_t pHwData, u16 number, u32 value )
13794+{
13795+ unsigned char ret;
13796+
13797+ if( number < 0x1000 )
13798+ number += 0x1000;
13799+ ret = Wb35Reg_WriteSync( pHwData, number, value );
13800+ return ret;
13801+}
13802+
13803+void hal_scan_status_indicate(phw_data_t pHwData, unsigned char IsOnProgress)
13804+{
13805+ if( pHwData->SurpriseRemove ) return;
13806+ pHwData->LED_Scanning = IsOnProgress ? 1 : 0;
13807+}
13808+
13809+void hal_system_power_change(phw_data_t pHwData, u32 PowerState)
13810+{
13811+ if( PowerState != 0 )
13812+ {
13813+ pHwData->SurpriseRemove = 1;
13814+ if( pHwData->WbUsb.IsUsb20 )
13815+ hal_stop( pHwData );
13816+ }
13817+ else
13818+ {
13819+ if( !pHwData->WbUsb.IsUsb20 )
13820+ hal_stop( pHwData );
13821+ }
13822+}
13823+
13824+void hal_surprise_remove( phw_data_t pHwData )
13825+{
13826+ PADAPTER Adapter = pHwData->Adapter;
13827+ if (OS_ATOMIC_INC( Adapter, &pHwData->SurpriseRemoveCount ) == 1) {
13828+ #ifdef _PE_STATE_DUMP_
13829+ WBDEBUG(("Calling hal_surprise_remove\n"));
13830+ #endif
13831+ OS_STOP( Adapter );
13832+ }
13833+}
13834+
13835+void hal_rate_change( phw_data_t pHwData ) // Notify the HAL rate is changing 20060613.1
13836+{
13837+ PADAPTER Adapter = pHwData->Adapter;
13838+ u8 rate = CURRENT_TX_RATE;
13839+
13840+ BBProcessor_RateChanging( pHwData, rate );
13841+}
13842+
13843+void hal_set_rf_power(phw_data_t pHwData, u8 PowerIndex)
13844+{
13845+ RFSynthesizer_SetPowerIndex( pHwData, PowerIndex );
13846+}
13847+
13848+unsigned char hal_set_LED(phw_data_t pHwData, u32 Mode) // 20061108 for WPS led control
13849+{
13850+ pHwData->LED_Blinking = 0;
13851+ pHwData->LED_control = Mode;
13852+ OS_TIMER_SET( &pHwData->LEDTimer, 10 ); // 20060623
13853+ return TRUE;
13854+}
13855+
13856diff --git a/drivers/staging/winbond/wbhal_f.h b/drivers/staging/winbond/wbhal_f.h
13857new file mode 100644
13858index 0000000..fe25f97
13859--- /dev/null
13860+++ b/drivers/staging/winbond/wbhal_f.h
13861@@ -0,0 +1,122 @@
13862+//=====================================================================
13863+// Device related include
13864+//=====================================================================
13865+#ifdef WB_LINUX
13866+ #include "linux/wbusb_f.h"
13867+ #include "linux/wb35reg_f.h"
13868+ #include "linux/wb35tx_f.h"
13869+ #include "linux/wb35rx_f.h"
13870+#else
13871+ #include "wbusb_f.h"
13872+ #include "wb35reg_f.h"
13873+ #include "wb35tx_f.h"
13874+ #include "wb35rx_f.h"
13875+#endif
13876+
13877+//====================================================================================
13878+// Function declaration
13879+//====================================================================================
13880+void hal_remove_mapping_key( phw_data_t pHwData, PUCHAR pmac_addr );
13881+void hal_remove_default_key( phw_data_t pHwData, u32 index );
13882+unsigned char hal_set_mapping_key( phw_data_t Adapter, PUCHAR pmac_addr, u8 null_key, u8 wep_on, PUCHAR ptx_tsc, PUCHAR prx_tsc, u8 key_type, u8 key_len, PUCHAR pkey_data );
13883+unsigned char hal_set_default_key( phw_data_t Adapter, u8 index, u8 null_key, u8 wep_on, PUCHAR ptx_tsc, PUCHAR prx_tsc, u8 key_type, u8 key_len, PUCHAR pkey_data );
13884+void hal_clear_all_default_key( phw_data_t pHwData );
13885+void hal_clear_all_group_key( phw_data_t pHwData );
13886+void hal_clear_all_mapping_key( phw_data_t pHwData );
13887+void hal_clear_all_key( phw_data_t pHwData );
13888+void hal_get_ethernet_address( phw_data_t pHwData, PUCHAR current_address );
13889+void hal_set_ethernet_address( phw_data_t pHwData, PUCHAR current_address );
13890+void hal_get_permanent_address( phw_data_t pHwData, PUCHAR pethernet_address );
13891+unsigned char hal_init_hardware( phw_data_t pHwData, PADAPTER Adapter );
13892+void hal_set_power_save_mode( phw_data_t pHwData, unsigned char power_save, unsigned char wakeup, unsigned char dtim );
13893+void hal_get_power_save_mode( phw_data_t pHwData, PBOOLEAN pin_pwr_save );
13894+void hal_set_slot_time( phw_data_t pHwData, u8 type );
13895+#define hal_set_atim_window( _A, _ATM )
13896+void hal_set_rates( phw_data_t pHwData, PUCHAR pbss_rates, u8 length, unsigned char basic_rate_set );
13897+#define hal_set_basic_rates( _A, _R, _L ) hal_set_rates( _A, _R, _L, TRUE )
13898+#define hal_set_op_rates( _A, _R, _L ) hal_set_rates( _A, _R, _L, FALSE )
13899+void hal_start_bss( phw_data_t pHwData, u8 mac_op_mode );
13900+void hal_join_request( phw_data_t pHwData, u8 bss_type ); // 0:BSS STA 1:IBSS STA//
13901+void hal_stop_sync_bss( phw_data_t pHwData );
13902+void hal_resume_sync_bss( phw_data_t pHwData);
13903+void hal_set_aid( phw_data_t pHwData, u16 aid );
13904+void hal_set_bssid( phw_data_t pHwData, PUCHAR pbssid );
13905+void hal_get_bssid( phw_data_t pHwData, PUCHAR pbssid );
13906+void hal_set_beacon_period( phw_data_t pHwData, u16 beacon_period );
13907+void hal_set_listen_interval( phw_data_t pHwData, u16 listen_interval );
13908+void hal_set_cap_info( phw_data_t pHwData, u16 capability_info );
13909+void hal_set_ssid( phw_data_t pHwData, PUCHAR pssid, u8 ssid_len );
13910+void hal_set_current_channel( phw_data_t pHwData, ChanInfo channel );
13911+void hal_set_current_channel_ex( phw_data_t pHwData, ChanInfo channel );
13912+void hal_get_current_channel( phw_data_t pHwData, ChanInfo *channel );
13913+void hal_set_accept_broadcast( phw_data_t pHwData, u8 enable );
13914+void hal_set_accept_multicast( phw_data_t pHwData, u8 enable );
13915+void hal_set_accept_beacon( phw_data_t pHwData, u8 enable );
13916+void hal_set_multicast_address( phw_data_t pHwData, PUCHAR address, u8 number );
13917+u8 hal_get_accept_beacon( phw_data_t pHwData );
13918+void hal_stop( phw_data_t pHwData );
13919+void hal_halt( phw_data_t pHwData, void *ppa_data );
13920+void hal_start_tx0( phw_data_t pHwData );
13921+void hal_set_phy_type( phw_data_t pHwData, u8 PhyType );
13922+void hal_get_phy_type( phw_data_t pHwData, u8 *PhyType );
13923+unsigned char hal_reset_hardware( phw_data_t pHwData, void* ppa );
13924+void hal_set_cwmin( phw_data_t pHwData, u8 cwin_min );
13925+#define hal_get_cwmin( _A ) ( (_A)->cwmin )
13926+void hal_set_cwmax( phw_data_t pHwData, u16 cwin_max );
13927+#define hal_get_cwmax( _A ) ( (_A)->cwmax )
13928+void hal_set_rsn_wpa( phw_data_t pHwData, u32 * RSN_IE_Bitmap , u32 * RSN_OUI_type , unsigned char bDesiredAuthMode);
13929+//s32 hal_get_rssi( phw_data_t pHwData, u32 HalRssi );
13930+s32 hal_get_rssi( phw_data_t pHwData, u32 *HalRssiArry, u8 Count );
13931+s32 hal_get_rssi_bss( phw_data_t pHwData, u16 idx, u8 Count );
13932+void hal_set_connect_info( phw_data_t pHwData, unsigned char boConnect );
13933+u8 hal_get_est_sq3( phw_data_t pHwData, u8 Count );
13934+void hal_led_control_1a( phw_data_t pHwData );
13935+void hal_led_control( void* S1, phw_data_t pHwData, void* S3, void* S4 );
13936+void hal_set_rf_power( phw_data_t pHwData, u8 PowerIndex ); // 20060621 Modify
13937+void hal_reset_counter( phw_data_t pHwData );
13938+void hal_set_radio_mode( phw_data_t pHwData, unsigned char boValue);
13939+void hal_descriptor_indicate( phw_data_t pHwData, PDESCRIPTOR pDes );
13940+u8 hal_get_antenna_number( phw_data_t pHwData );
13941+void hal_set_antenna_number( phw_data_t pHwData, u8 number );
13942+u32 hal_get_bss_pk_cnt( phw_data_t pHwData );
13943+#define hal_get_region_from_EEPROM( _A ) ( (_A)->Wb35Reg.EEPROMRegion )
13944+void hal_set_accept_promiscuous ( phw_data_t pHwData, u8 enable);
13945+#define hal_get_tx_buffer( _A, _B ) Wb35Tx_get_tx_buffer( _A, _B )
13946+u8 hal_get_hw_radio_off ( phw_data_t pHwData );
13947+#define hal_software_set( _A ) (_A->SoftwareSet)
13948+#define hal_driver_init_OK( _A ) (_A->IsInitOK)
13949+#define hal_rssi_boundary_high( _A ) (_A->RSSI_high)
13950+#define hal_rssi_boundary_low( _A ) (_A->RSSI_low)
13951+#define hal_scan_interval( _A ) (_A->Scan_Interval)
13952+void hal_scan_status_indicate( phw_data_t pHwData, u8 status); // 0: complete, 1: in progress
13953+void hal_system_power_change( phw_data_t pHwData, u32 PowerState ); // 20051230 -=D0 1=D1 ..
13954+void hal_surprise_remove( phw_data_t pHwData );
13955+
13956+#define PHY_DEBUG( msg, args... )
13957+
13958+
13959+
13960+void hal_rate_change( phw_data_t pHwData ); // Notify the HAL rate is changing 20060613.1
13961+unsigned char hal_get_dxx_reg( phw_data_t pHwData, u16 number, PULONG pValue );
13962+unsigned char hal_set_dxx_reg( phw_data_t pHwData, u16 number, u32 value );
13963+#define hal_get_time_count( _P ) (_P->time_count/10) // return 100ms count
13964+#define hal_detect_error( _P ) (_P->WbUsb.DetectCount)
13965+unsigned char hal_set_LED( phw_data_t pHwData, u32 Mode ); // 20061108 for WPS led control
13966+
13967+//-------------------------------------------------------------------------
13968+// The follow function is unused for IS89C35
13969+//-------------------------------------------------------------------------
13970+#define hal_disable_interrupt(_A)
13971+#define hal_enable_interrupt(_A)
13972+#define hal_get_interrupt_type( _A)
13973+#define hal_get_clear_interrupt(_A)
13974+#define hal_ibss_disconnect(_A) hal_stop_sync_bss(_A)
13975+#define hal_join_request_stop(_A)
13976+unsigned char hal_idle( phw_data_t pHwData );
13977+#define pa_stall_execution( _A ) //OS_SLEEP( 1 )
13978+#define hw_get_cxx_reg( _A, _B, _C )
13979+#define hw_set_cxx_reg( _A, _B, _C )
13980+#define hw_get_dxx_reg( _A, _B, _C ) hal_get_dxx_reg( _A, _B, (PULONG)_C )
13981+#define hw_set_dxx_reg( _A, _B, _C ) hal_set_dxx_reg( _A, _B, (u32)_C )
13982+
13983+
13984diff --git a/drivers/staging/winbond/wbhal_s.h b/drivers/staging/winbond/wbhal_s.h
13985new file mode 100644
13986index 0000000..5b862ff
13987--- /dev/null
13988+++ b/drivers/staging/winbond/wbhal_s.h
13989@@ -0,0 +1,615 @@
13990+//[20040722 WK]
13991+#define HAL_LED_SET_MASK 0x001c //20060901 Extend
13992+#define HAL_LED_SET_SHIFT 2
13993+
13994+//supported RF type
13995+#define RF_MAXIM_2825 0
13996+#define RF_MAXIM_2827 1
13997+#define RF_MAXIM_2828 2
13998+#define RF_MAXIM_2829 3
13999+#define RF_MAXIM_V1 15
14000+#define RF_AIROHA_2230 16
14001+#define RF_AIROHA_7230 17
14002+#define RF_AIROHA_2230S 18 // 20060420 Add this
14003+// #define RF_RFMD_2959 32 // 20060626 Remove all about RFMD
14004+#define RF_WB_242 33
14005+#define RF_WB_242_1 34 // 20060619.5 Add
14006+#define RF_DECIDE_BY_INF 255
14007+
14008+//----------------------------------------------------------------
14009+// The follow define connect to upper layer
14010+// User must modify for connection between HAL and upper layer
14011+//----------------------------------------------------------------
14012+
14013+
14014+
14015+
14016+/////////////////////////////////////////////////////////////////////////////////////////////////////
14017+//================================================================================================
14018+// Common define
14019+//================================================================================================
14020+#define HAL_USB_MODE_BURST( _H ) (_H->SoftwareSet & 0x20 ) // Bit 5 20060901 Modify
14021+
14022+// Scan interval
14023+#define SCAN_MAX_CHNL_TIME (50)
14024+
14025+// For TxL2 Frame typr recognise
14026+#define FRAME_TYPE_802_3_DATA 0
14027+#define FRAME_TYPE_802_11_MANAGEMENT 1
14028+#define FRAME_TYPE_802_11_MANAGEMENT_CHALLENGE 2
14029+#define FRAME_TYPE_802_11_CONTROL 3
14030+#define FRAME_TYPE_802_11_DATA 4
14031+#define FRAME_TYPE_PROMISCUOUS 5
14032+
14033+// The follow definition is used for convert the frame--------------------
14034+#define DOT_11_SEQUENCE_OFFSET 22 //Sequence control offset
14035+#define DOT_3_TYPE_OFFSET 12
14036+#define DOT_11_MAC_HEADER_SIZE 24
14037+#define DOT_11_SNAP_SIZE 6
14038+#define DOT_11_TYPE_OFFSET 30 //The start offset of 802.11 Frame. Type encapsulatuin.
14039+#define DEFAULT_SIFSTIME 10
14040+#define DEFAULT_FRAGMENT_THRESHOLD 2346 // No fragment
14041+#define DEFAULT_MSDU_LIFE_TIME 0xffff
14042+
14043+#define LONG_PREAMBLE_PLUS_PLCPHEADER_TIME (144+48)
14044+#define SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME (72+24)
14045+#define PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION (16+4+6)
14046+#define Tsym 4
14047+
14048+// Frame Type of Bits (2, 3)---------------------------------------------
14049+#define MAC_TYPE_MANAGEMENT 0x00
14050+#define MAC_TYPE_CONTROL 0x04
14051+#define MAC_TYPE_DATA 0x08
14052+#define MASK_FRAGMENT_NUMBER 0x000F
14053+#define SEQUENCE_NUMBER_SHIFT 4
14054+
14055+#define HAL_WOL_TYPE_WAKEUP_FRAME 0x01
14056+#define HAL_WOL_TYPE_MAGIC_PACKET 0x02
14057+
14058+// 20040106 ADDED
14059+#define HAL_KEYTYPE_WEP40 0
14060+#define HAL_KEYTYPE_WEP104 1
14061+#define HAL_KEYTYPE_TKIP 2 // 128 bit key
14062+#define HAL_KEYTYPE_AES_CCMP 3 // 128 bit key
14063+
14064+// For VM state
14065+enum {
14066+ VM_STOP = 0,
14067+ VM_RUNNING,
14068+ VM_COMPLETED
14069+};
14070+
14071+// Be used for 802.11 mac header
14072+typedef struct _MAC_FRAME_CONTROL {
14073+ u8 mac_frame_info; // this is a combination of the protovl version, type and subtype
14074+ u8 to_ds:1;
14075+ u8 from_ds:1;
14076+ u8 more_frag:1;
14077+ u8 retry:1;
14078+ u8 pwr_mgt:1;
14079+ u8 more_data:1;
14080+ u8 WEP:1;
14081+ u8 order:1;
14082+} MAC_FRAME_CONTROL, *PMAC_FRAME_CONTROL;
14083+
14084+//-----------------------------------------------------
14085+// Normal Key table format
14086+//-----------------------------------------------------
14087+// The order of KEY index is MAPPING_KEY_START_INDEX > GROUP_KEY_START_INDEX
14088+#define MAX_KEY_TABLE 24 // 24 entry for storing key data
14089+#define GROUP_KEY_START_INDEX 4
14090+#define MAPPING_KEY_START_INDEX 8
14091+typedef struct _KEY_TABLE
14092+{
14093+ u32 DW0_Valid:1;
14094+ u32 DW0_NullKey:1;
14095+ u32 DW0_Security_Mode:2;//0:WEP 40 bit 1:WEP 104 bit 2:TKIP 128 bit 3:CCMP 128 bit
14096+ u32 DW0_WEPON:1;
14097+ u32 DW0_RESERVED:11;
14098+ u32 DW0_Address1:16;
14099+
14100+ u32 DW1_Address2;
14101+
14102+ u32 DW2_RxSequenceCount1;
14103+
14104+ u32 DW3_RxSequenceCount2:16;
14105+ u32 DW3_RESERVED:16;
14106+
14107+ u32 DW4_TxSequenceCount1;
14108+
14109+ u32 DW5_TxSequenceCount2:16;
14110+ u32 DW5_RESERVED:16;
14111+
14112+} KEY_TABLE, *PKEY_TABLE;
14113+
14114+//--------------------------------------------------------
14115+// Descriptor
14116+//--------------------------------------------------------
14117+#define MAX_DESCRIPTOR_BUFFER_INDEX 8 // Have to multiple of 2
14118+//#define FLAG_ERROR_TX_MASK cpu_to_le32(0x000000bf) //20061009 marked by anson's endian
14119+#define FLAG_ERROR_TX_MASK 0x000000bf //20061009 anson's endian
14120+//#define FLAG_ERROR_RX_MASK 0x00000c3f
14121+//#define FLAG_ERROR_RX_MASK cpu_to_le32(0x0000083f) //20061009 marked by anson's endian
14122+ //Don't care replay error,
14123+ //it is handled by S/W
14124+#define FLAG_ERROR_RX_MASK 0x0000083f //20060926 anson's endian
14125+
14126+#define FLAG_BAND_RX_MASK 0x10000000 //Bit 28
14127+
14128+typedef struct _R00_DESCRIPTOR
14129+{
14130+ union
14131+ {
14132+ u32 value;
14133+ #ifdef _BIG_ENDIAN_ //20060926 anson's endian
14134+ struct
14135+ {
14136+ u32 R00_packet_or_buffer_status:1;
14137+ u32 R00_packet_in_fifo:1;
14138+ u32 R00_RESERVED:2;
14139+ u32 R00_receive_byte_count:12;
14140+ u32 R00_receive_time_index:16;
14141+ };
14142+ #else
14143+ struct
14144+ {
14145+ u32 R00_receive_time_index:16;
14146+ u32 R00_receive_byte_count:12;
14147+ u32 R00_RESERVED:2;
14148+ u32 R00_packet_in_fifo:1;
14149+ u32 R00_packet_or_buffer_status:1;
14150+ };
14151+ #endif
14152+ };
14153+} R00_DESCRIPTOR, *PR00_DESCRIPTOR;
14154+
14155+typedef struct _T00_DESCRIPTOR
14156+{
14157+ union
14158+ {
14159+ u32 value;
14160+ #ifdef _BIG_ENDIAN_ //20061009 anson's endian
14161+ struct
14162+ {
14163+ u32 T00_first_mpdu:1; // for hardware use
14164+ u32 T00_last_mpdu:1; // for hardware use
14165+ u32 T00_IsLastMpdu:1;// 0: not 1:Yes for software used
14166+ u32 T00_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
14167+ u32 T00_RESERVED_ID:2;//3 bit ID reserved
14168+ u32 T00_tx_packet_id:4;//930519.4.e 930810.3.c
14169+ u32 T00_RESERVED:4;
14170+ u32 T00_header_length:6;
14171+ u32 T00_frame_length:12;
14172+ };
14173+ #else
14174+ struct
14175+ {
14176+ u32 T00_frame_length:12;
14177+ u32 T00_header_length:6;
14178+ u32 T00_RESERVED:4;
14179+ u32 T00_tx_packet_id:4;//930519.4.e 930810.3.c
14180+ u32 T00_RESERVED_ID:2;//3 bit ID reserved
14181+ u32 T00_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
14182+ u32 T00_IsLastMpdu:1;// 0: not 1:Yes for software used
14183+ u32 T00_last_mpdu:1; // for hardware use
14184+ u32 T00_first_mpdu:1; // for hardware use
14185+ };
14186+ #endif
14187+ };
14188+} T00_DESCRIPTOR, *PT00_DESCRIPTOR;
14189+
14190+typedef struct _R01_DESCRIPTOR
14191+{
14192+ union
14193+ {
14194+ u32 value;
14195+ #ifdef _BIG_ENDIAN_ //20060926 add by anson's endian
14196+ struct
14197+ {
14198+ u32 R01_RESERVED:3;
14199+ u32 R01_mod_type:1;
14200+ u32 R01_pre_type:1;
14201+ u32 R01_data_rate:3;
14202+ u32 R01_AGC_state:8;
14203+ u32 R01_LNA_state:2;
14204+ u32 R01_decryption_method:2;
14205+ u32 R01_mic_error:1;
14206+ u32 R01_replay:1;
14207+ u32 R01_broadcast_frame:1;
14208+ u32 R01_multicast_frame:1;
14209+ u32 R01_directed_frame:1;
14210+ u32 R01_receive_frame_antenna_selection:1;
14211+ u32 R01_frame_receive_during_atim_window:1;
14212+ u32 R01_protocol_version_error:1;
14213+ u32 R01_authentication_frame_icv_error:1;
14214+ u32 R01_null_key_to_authentication_frame:1;
14215+ u32 R01_icv_error:1;
14216+ u32 R01_crc_error:1;
14217+ };
14218+ #else
14219+ struct
14220+ {
14221+ u32 R01_crc_error:1;
14222+ u32 R01_icv_error:1;
14223+ u32 R01_null_key_to_authentication_frame:1;
14224+ u32 R01_authentication_frame_icv_error:1;
14225+ u32 R01_protocol_version_error:1;
14226+ u32 R01_frame_receive_during_atim_window:1;
14227+ u32 R01_receive_frame_antenna_selection:1;
14228+ u32 R01_directed_frame:1;
14229+ u32 R01_multicast_frame:1;
14230+ u32 R01_broadcast_frame:1;
14231+ u32 R01_replay:1;
14232+ u32 R01_mic_error:1;
14233+ u32 R01_decryption_method:2;
14234+ u32 R01_LNA_state:2;
14235+ u32 R01_AGC_state:8;
14236+ u32 R01_data_rate:3;
14237+ u32 R01_pre_type:1;
14238+ u32 R01_mod_type:1;
14239+ u32 R01_RESERVED:3;
14240+ };
14241+ #endif
14242+ };
14243+} R01_DESCRIPTOR, *PR01_DESCRIPTOR;
14244+
14245+typedef struct _T01_DESCRIPTOR
14246+{
14247+ union
14248+ {
14249+ u32 value;
14250+ #ifdef _BIG_ENDIAN_ //20061009 anson's endian
14251+ struct
14252+ {
14253+ u32 T01_rts_cts_duration:16;
14254+ u32 T01_fall_back_rate:3;
14255+ u32 T01_add_rts:1;
14256+ u32 T01_add_cts:1;
14257+ u32 T01_modulation_type:1;
14258+ u32 T01_plcp_header_length:1;
14259+ u32 T01_transmit_rate:3;
14260+ u32 T01_wep_id:2;
14261+ u32 T01_add_challenge_text:1;
14262+ u32 T01_inhibit_crc:1;
14263+ u32 T01_loop_back_wep_mode:1;
14264+ u32 T01_retry_abort_ebable:1;
14265+ };
14266+ #else
14267+ struct
14268+ {
14269+ u32 T01_retry_abort_ebable:1;
14270+ u32 T01_loop_back_wep_mode:1;
14271+ u32 T01_inhibit_crc:1;
14272+ u32 T01_add_challenge_text:1;
14273+ u32 T01_wep_id:2;
14274+ u32 T01_transmit_rate:3;
14275+ u32 T01_plcp_header_length:1;
14276+ u32 T01_modulation_type:1;
14277+ u32 T01_add_cts:1;
14278+ u32 T01_add_rts:1;
14279+ u32 T01_fall_back_rate:3;
14280+ u32 T01_rts_cts_duration:16;
14281+ };
14282+ #endif
14283+ };
14284+} T01_DESCRIPTOR, *PT01_DESCRIPTOR;
14285+
14286+typedef struct _T02_DESCRIPTOR
14287+{
14288+ union
14289+ {
14290+ u32 value;
14291+ #ifdef _BIG_ENDIAN_ //20061009 add by anson's endian
14292+ struct
14293+ {
14294+ u32 T02_IsLastMpdu:1;// The same mechanism with T00 setting
14295+ u32 T02_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
14296+ u32 T02_RESERVED_ID:2;// The same mechanism with T00 setting
14297+ u32 T02_Tx_PktID:4;
14298+ u32 T02_MPDU_Cnt:4;
14299+ u32 T02_RTS_Cnt:4;
14300+ u32 T02_RESERVED:7;
14301+ u32 T02_transmit_complete:1;
14302+ u32 T02_transmit_abort_due_to_TBTT:1;
14303+ u32 T02_effective_transmission_rate:1;
14304+ u32 T02_transmit_without_encryption_due_to_wep_on_false:1;
14305+ u32 T02_discard_due_to_null_wep_key:1;
14306+ u32 T02_RESERVED_1:1;
14307+ u32 T02_out_of_MaxTxMSDULiftTime:1;
14308+ u32 T02_transmit_abort:1;
14309+ u32 T02_transmit_fail:1;
14310+ };
14311+ #else
14312+ struct
14313+ {
14314+ u32 T02_transmit_fail:1;
14315+ u32 T02_transmit_abort:1;
14316+ u32 T02_out_of_MaxTxMSDULiftTime:1;
14317+ u32 T02_RESERVED_1:1;
14318+ u32 T02_discard_due_to_null_wep_key:1;
14319+ u32 T02_transmit_without_encryption_due_to_wep_on_false:1;
14320+ u32 T02_effective_transmission_rate:1;
14321+ u32 T02_transmit_abort_due_to_TBTT:1;
14322+ u32 T02_transmit_complete:1;
14323+ u32 T02_RESERVED:7;
14324+ u32 T02_RTS_Cnt:4;
14325+ u32 T02_MPDU_Cnt:4;
14326+ u32 T02_Tx_PktID:4;
14327+ u32 T02_RESERVED_ID:2;// The same mechanism with T00 setting
14328+ u32 T02_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
14329+ u32 T02_IsLastMpdu:1;// The same mechanism with T00 setting
14330+ };
14331+ #endif
14332+ };
14333+} T02_DESCRIPTOR, *PT02_DESCRIPTOR;
14334+
14335+typedef struct _DESCRIPTOR { // Skip length = 8 DWORD
14336+ // ID for descriptor ---, The field doesn't be cleard in the operation of Descriptor definition
14337+ u8 Descriptor_ID;
14338+ //----------------------The above region doesn't be cleared by DESCRIPTOR_RESET------
14339+ u8 RESERVED[3];
14340+
14341+ u16 FragmentThreshold;
14342+ u8 InternalUsed;//Only can be used by operation of descriptor definition
14343+ u8 Type;// 0: 802.3 1:802.11 data frame 2:802.11 management frame
14344+
14345+ u8 PreambleMode;// 0: short 1:long
14346+ u8 TxRate;
14347+ u8 FragmentCount;
14348+ u8 EapFix; // For speed up key install
14349+
14350+ // For R00 and T00 ----------------------------------------------
14351+ union
14352+ {
14353+ R00_DESCRIPTOR R00;
14354+ T00_DESCRIPTOR T00;
14355+ };
14356+
14357+ // For R01 and T01 ----------------------------------------------
14358+ union
14359+ {
14360+ R01_DESCRIPTOR R01;
14361+ T01_DESCRIPTOR T01;
14362+ };
14363+
14364+ // For R02 and T02 ----------------------------------------------
14365+ union
14366+ {
14367+ u32 R02;
14368+ T02_DESCRIPTOR T02;
14369+ };
14370+
14371+ // For R03 and T03 ----------------------------------------------
14372+ // For software used
14373+ union
14374+ {
14375+ u32 R03;
14376+ u32 T03;
14377+ struct
14378+ {
14379+ u8 buffer_number;
14380+ u8 buffer_start_index;
14381+ u16 buffer_total_size;
14382+ };
14383+ };
14384+
14385+ // For storing the buffer
14386+ u16 buffer_size[ MAX_DESCRIPTOR_BUFFER_INDEX ];
14387+ void* buffer_address[ MAX_DESCRIPTOR_BUFFER_INDEX ];//931130.4.q
14388+
14389+} DESCRIPTOR, *PDESCRIPTOR;
14390+
14391+
14392+#define DEFAULT_NULL_PACKET_COUNT 180000 //20060828.1 Add. 180 seconds
14393+
14394+#define MAX_TXVGA_EEPROM 9 //How many word(u16) of EEPROM will be used for TxVGA
14395+#define MAX_RF_PARAMETER 32
14396+
14397+typedef struct _TXVGA_FOR_50 {
14398+ u8 ChanNo;
14399+ u8 TxVgaValue;
14400+} TXVGA_FOR_50;
14401+
14402+
14403+//=====================================================================
14404+// Device related include
14405+//=====================================================================
14406+
14407+#include "linux/wbusb_s.h"
14408+#include "linux/wb35reg_s.h"
14409+#include "linux/wb35tx_s.h"
14410+#include "linux/wb35rx_s.h"
14411+
14412+
14413+// For Hal using ==================================================================
14414+typedef struct _HW_DATA_T
14415+{
14416+ // For compatible with 33
14417+ u32 revision;
14418+ u32 BB3c_cal; // The value for Tx calibration comes from EEPROM
14419+ u32 BB54_cal; // The value for Rx calibration comes from EEPROM
14420+
14421+
14422+ // For surprise remove
14423+ u32 SurpriseRemove; // 0: Normal 1: Surprise remove
14424+ u8 InitialResource;
14425+ u8 IsKeyPreSet;
14426+ u8 CalOneTime; // 20060630.1
14427+
14428+ u8 VCO_trim;
14429+
14430+ // For Fix 1'st DMA bug
14431+ u32 FragCount;
14432+ u32 DMAFix; //V1_DMA_FIX The variable can be removed if driver want to save mem space for V2.
14433+
14434+ //=======================================================================================
14435+ // For USB driver, hal need more variables. Due to
14436+ // 1. NDIS-WDM operation
14437+ // 2. The SME, MLME and OLD MDS need Adapter structure, but the driver under HAL doesn't
14438+ // have that parameter when receiving and indicating packet.
14439+ // The MDS must input the Adapter pointer as the second parameter of hal_init_hardware.
14440+ // The function usage is different than PCI driver.
14441+ //=======================================================================================
14442+ void* Adapter;
14443+
14444+ //===============================================
14445+ // Definition for MAC address
14446+ //===============================================
14447+ u8 PermanentMacAddress[ETH_LENGTH_OF_ADDRESS + 2]; // The Enthernet addr that are stored in EEPROM. + 2 to 8-byte alignment
14448+ u8 CurrentMacAddress[ETH_LENGTH_OF_ADDRESS + 2]; // The Enthernet addr that are in used. + 2 to 8-byte alignment
14449+
14450+ //=====================================================================
14451+ // Definition for 802.11
14452+ //=====================================================================
14453+ PUCHAR bssid_pointer; // Used by hal_get_bssid for return value
14454+ u8 bssid[8];// Only 6 byte will be used. 8 byte is required for read buffer
14455+ u8 ssid[32];// maximum ssid length is 32 byte
14456+
14457+ u16 AID;
14458+ u8 ssid_length;
14459+ u8 Channel;
14460+
14461+ u16 ListenInterval;
14462+ u16 CapabilityInformation;
14463+
14464+ u16 BeaconPeriod;
14465+ u16 ProbeDelay;
14466+
14467+ u8 bss_type;// 0: IBSS_NET or 1:ESS_NET
14468+ u8 preamble;// 0: short preamble, 1: long preamble
14469+ u8 slot_time_select;// 9 or 20 value
14470+ u8 phy_type;// Phy select
14471+
14472+ u32 phy_para[MAX_RF_PARAMETER];
14473+ u32 phy_number;
14474+
14475+ u32 CurrentRadioSw; // 20060320.2 0:On 1:Off
14476+ u32 CurrentRadioHw; // 20060825 0:On 1:Off
14477+
14478+ PUCHAR power_save_point; // Used by hal_get_power_save_mode for return value
14479+ u8 cwmin;
14480+ u8 desired_power_save;
14481+ u8 dtim;// Is running dtim
14482+ u8 mapping_key_replace_index;//In Key table, the next index be replaced 931130.4.r
14483+
14484+ u16 MaxReceiveLifeTime;
14485+ u16 FragmentThreshold;
14486+ u16 FragmentThreshold_tmp;
14487+ u16 cwmax;
14488+
14489+ u8 Key_slot[MAX_KEY_TABLE][8]; //Ownership record for key slot. For Alignment
14490+ u32 Key_content[MAX_KEY_TABLE][12]; // 10DW for each entry + 2 for burst command( Off and On valid bit)
14491+ u8 CurrentDefaultKeyIndex;
14492+ u32 CurrentDefaultKeyLength;
14493+
14494+ //========================================================================
14495+ // Variable for each module
14496+ //========================================================================
14497+ WBUSB WbUsb; // Need WbUsb.h
14498+ WB35REG Wb35Reg; // Need Wb35Reg.h
14499+ WB35TX Wb35Tx; // Need Wb35Tx.h
14500+ WB35RX Wb35Rx; // Need Wb35Rx.h
14501+
14502+ OS_TIMER LEDTimer;// For LED
14503+
14504+ u32 LEDpoint;// For LED
14505+
14506+ u32 dto_tx_retry_count; // LA20040210_DTO kevin
14507+ u32 dto_tx_frag_count; // LA20040210_DTO kevin
14508+ u32 rx_ok_count[13]; // index=0: total rx ok
14509+ //u32 rx_ok_bytes[13]; // index=0, total rx ok bytes
14510+ u32 rx_err_count[13]; // index=0: total rx err
14511+
14512+ //for Tx debug
14513+ u32 tx_TBTT_start_count;
14514+ u32 tx_ETR_count;
14515+ u32 tx_WepOn_false_count;
14516+ u32 tx_Null_key_count;
14517+ u32 tx_retry_count[8];
14518+
14519+ u8 PowerIndexFromEEPROM; // For 2412MHz
14520+ u8 power_index;
14521+ u8 IsWaitJoinComplete; // TRUE: set join request
14522+ u8 band;
14523+
14524+ u16 SoftwareSet;
14525+ u16 Reserved_s;
14526+
14527+ u32 IsInitOK; // 0: Driver starting 1: Driver init OK
14528+
14529+ // For Phy calibration
14530+ s32 iq_rsdl_gain_tx_d2;
14531+ s32 iq_rsdl_phase_tx_d2;
14532+ u32 txvga_setting_for_cal; // 20060703.1 Add
14533+
14534+ u8 TxVgaSettingInEEPROM[ (((MAX_TXVGA_EEPROM*2)+3) & ~0x03) ]; // 20060621 For backup EEPROM value
14535+ u8 TxVgaFor24[16]; // Max is 14, 2 for alignment
14536+ TXVGA_FOR_50 TxVgaFor50[36]; // 35 channels in 5G. 35x2 = 70 byte. 2 for alignments
14537+
14538+ u16 Scan_Interval;
14539+ u16 RESERVED6;
14540+
14541+ // LED control
14542+ u32 LED_control;
14543+ // LED_control 4 byte: Gray_Led_1[3] Gray_Led_0[2] Led[1] Led[0]
14544+ // Gray_Led
14545+ // For Led gray setting
14546+ // Led
14547+ // 0: normal control, LED behavior will decide by EEPROM setting
14548+ // 1: Turn off specific LED
14549+ // 2: Always on specific LED
14550+ // 3: slow blinking specific LED
14551+ // 4: fast blinking specific LED
14552+ // 5: WPS led control is set. Led0 is Red, Led1 id Green
14553+ // Led[1] is parameter for WPS LED mode
14554+ // // 1:InProgress 2: Error 3: Session overlap 4: Success 20061108 control
14555+
14556+ u32 LED_LinkOn; //Turn LED on control
14557+ u32 LED_Scanning; // Let LED in scan process control
14558+ u32 LED_Blinking; // Temp variable for shining
14559+ u32 RxByteCountLast;
14560+ u32 TxByteCountLast;
14561+
14562+ s32 SurpriseRemoveCount;
14563+
14564+ // For global timer
14565+ u32 time_count;//TICK_TIME_100ms 1 = 100ms
14566+
14567+ // For error recover
14568+ u32 HwStop;
14569+
14570+ // 20060828.1 for avoid AP disconnect
14571+ u32 NullPacketCount;
14572+
14573+} hw_data_t, *phw_data_t;
14574+
14575+// The mapping of Rx and Tx descriptor field
14576+typedef struct _HAL_RATE
14577+{
14578+ // DSSS
14579+ u32 RESERVED_0;
14580+ u32 NumRate2MS;
14581+ u32 NumRate55MS;
14582+ u32 NumRate11MS;
14583+
14584+ u32 RESERVED_1[4];
14585+
14586+ u32 NumRate1M;
14587+ u32 NumRate2ML;
14588+ u32 NumRate55ML;
14589+ u32 NumRate11ML;
14590+
14591+ u32 RESERVED_2[4];
14592+
14593+ // OFDM
14594+ u32 NumRate6M;
14595+ u32 NumRate9M;
14596+ u32 NumRate12M;
14597+ u32 NumRate18M;
14598+ u32 NumRate24M;
14599+ u32 NumRate36M;
14600+ u32 NumRate48M;
14601+ u32 NumRate54M;
14602+} HAL_RATE, *PHAL_RATE;
14603+
14604+
14605diff --git a/drivers/staging/winbond/wblinux.c b/drivers/staging/winbond/wblinux.c
14606new file mode 100644
14607index 0000000..2eade5a
14608--- /dev/null
14609+++ b/drivers/staging/winbond/wblinux.c
14610@@ -0,0 +1,277 @@
14611+//============================================================================
14612+// Copyright (c) 1996-2005 Winbond Electronic Corporation
14613+//
14614+// Module Name:
14615+// wblinux.c
14616+//
14617+// Abstract:
14618+// Linux releated routines
14619+//
14620+//============================================================================
14621+#include "os_common.h"
14622+
14623+u32
14624+WBLINUX_MemoryAlloc(void* *VirtualAddress, u32 Length)
14625+{
14626+ *VirtualAddress = kzalloc( Length, GFP_ATOMIC ); //GFP_KERNEL is not suitable
14627+
14628+ if (*VirtualAddress == NULL)
14629+ return 0;
14630+ return 1;
14631+}
14632+
14633+s32
14634+EncapAtomicInc(PADAPTER Adapter, void* pAtomic)
14635+{
14636+ PWBLINUX pWbLinux = &Adapter->WbLinux;
14637+ u32 ltmp;
14638+ PULONG pltmp = (PULONG)pAtomic;
14639+ OS_SPIN_LOCK_ACQUIRED( &pWbLinux->AtomicSpinLock );
14640+ (*pltmp)++;
14641+ ltmp = (*pltmp);
14642+ OS_SPIN_LOCK_RELEASED( &pWbLinux->AtomicSpinLock );
14643+ return ltmp;
14644+}
14645+
14646+s32
14647+EncapAtomicDec(PADAPTER Adapter, void* pAtomic)
14648+{
14649+ PWBLINUX pWbLinux = &Adapter->WbLinux;
14650+ u32 ltmp;
14651+ PULONG pltmp = (PULONG)pAtomic;
14652+ OS_SPIN_LOCK_ACQUIRED( &pWbLinux->AtomicSpinLock );
14653+ (*pltmp)--;
14654+ ltmp = (*pltmp);
14655+ OS_SPIN_LOCK_RELEASED( &pWbLinux->AtomicSpinLock );
14656+ return ltmp;
14657+}
14658+
14659+unsigned char
14660+WBLINUX_Initial(PADAPTER Adapter)
14661+{
14662+ PWBLINUX pWbLinux = &Adapter->WbLinux;
14663+
14664+ OS_SPIN_LOCK_ALLOCATE( &pWbLinux->SpinLock );
14665+ OS_SPIN_LOCK_ALLOCATE( &pWbLinux->AtomicSpinLock );
14666+ return TRUE;
14667+}
14668+
14669+void
14670+WBLinux_ReceivePacket(PADAPTER Adapter, PRXLAYER1 pRxLayer1)
14671+{
14672+ BUG();
14673+}
14674+
14675+
14676+void
14677+WBLINUX_GetNextPacket(PADAPTER Adapter, PDESCRIPTOR pDes)
14678+{
14679+ BUG();
14680+}
14681+
14682+void
14683+WBLINUX_GetNextPacketCompleted(PADAPTER Adapter, PDESCRIPTOR pDes)
14684+{
14685+ BUG();
14686+}
14687+
14688+void
14689+WBLINUX_Destroy(PADAPTER Adapter)
14690+{
14691+ WBLINUX_stop( Adapter );
14692+ OS_SPIN_LOCK_FREE( &pWbNdis->SpinLock );
14693+#ifdef _PE_USB_INI_DUMP_
14694+ WBDEBUG(("[w35und] unregister_netdev!\n"));
14695+#endif
14696+}
14697+
14698+void
14699+WBLINUX_stop( PADAPTER Adapter )
14700+{
14701+ PWBLINUX pWbLinux = &Adapter->WbLinux;
14702+ struct sk_buff *pSkb;
14703+
14704+ if (OS_ATOMIC_INC( Adapter, &pWbLinux->ThreadCount ) == 1) {
14705+ // Shutdown module immediately
14706+ pWbLinux->shutdown = 1;
14707+
14708+ while (pWbLinux->skb_array[ pWbLinux->skb_GetIndex ]) {
14709+ // Trying to free the un-sending packet
14710+ pSkb = pWbLinux->skb_array[ pWbLinux->skb_GetIndex ];
14711+ pWbLinux->skb_array[ pWbLinux->skb_GetIndex ] = NULL;
14712+ if( in_irq() )
14713+ dev_kfree_skb_irq( pSkb );
14714+ else
14715+ dev_kfree_skb( pSkb );
14716+
14717+ pWbLinux->skb_GetIndex++;
14718+ pWbLinux->skb_GetIndex %= WBLINUX_PACKET_ARRAY_SIZE;
14719+ }
14720+
14721+#ifdef _PE_STATE_DUMP_
14722+ WBDEBUG(( "[w35und] SKB_RELEASE OK\n" ));
14723+#endif
14724+ }
14725+
14726+ OS_ATOMIC_DEC( Adapter, &pWbLinux->ThreadCount );
14727+}
14728+
14729+void
14730+WbWlanHalt( PADAPTER Adapter )
14731+{
14732+ //---------------------
14733+ Adapter->sLocalPara.ShutDowned = TRUE;
14734+
14735+ Mds_Destroy( Adapter );
14736+
14737+ // Turn off Rx and Tx hardware ability
14738+ hal_stop( &Adapter->sHwData );
14739+#ifdef _PE_USB_INI_DUMP_
14740+ WBDEBUG(("[w35und] Hal_stop O.K.\n"));
14741+#endif
14742+ OS_SLEEP(100000);// Waiting Irp completed
14743+
14744+ // Destroy the NDIS module
14745+ WBLINUX_Destroy( Adapter );
14746+
14747+ // Halt the HAL
14748+ hal_halt(&Adapter->sHwData, NULL);
14749+}
14750+
14751+unsigned char
14752+WbWLanInitialize(PADAPTER Adapter)
14753+{
14754+ phw_data_t pHwData;
14755+ PUCHAR pMacAddr, pMacAddr2;
14756+ u32 InitStep = 0;
14757+ u8 EEPROM_region;
14758+ u8 HwRadioOff;
14759+
14760+ do {
14761+ //
14762+ // Setting default value for Linux
14763+ //
14764+ Adapter->sLocalPara.region_INF = REGION_AUTO;
14765+ Adapter->sLocalPara.TxRateMode = RATE_AUTO;
14766+ psLOCAL->bMacOperationMode = MODE_802_11_BG; // B/G mode
14767+ Adapter->Mds.TxRTSThreshold = DEFAULT_RTSThreshold;
14768+ Adapter->Mds.TxFragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD;
14769+ hal_set_phy_type( &Adapter->sHwData, RF_WB_242_1 );
14770+ Adapter->sLocalPara.MTUsize = MAX_ETHERNET_PACKET_SIZE;
14771+ psLOCAL->bPreambleMode = AUTO_MODE;
14772+ Adapter->sLocalPara.RadioOffStatus.boSwRadioOff = FALSE;
14773+ pHwData = &Adapter->sHwData;
14774+ hal_set_phy_type( pHwData, RF_DECIDE_BY_INF );
14775+
14776+ //
14777+ // Initial each module and variable
14778+ //
14779+ if (!WBLINUX_Initial(Adapter)) {
14780+#ifdef _PE_USB_INI_DUMP_
14781+ WBDEBUG(("[w35und]WBNDIS initialization failed\n"));
14782+#endif
14783+ break;
14784+ }
14785+
14786+ // Initial Software variable
14787+ Adapter->sLocalPara.ShutDowned = FALSE;
14788+
14789+ //added by ws for wep key error detection
14790+ Adapter->sLocalPara.bWepKeyError= FALSE;
14791+ Adapter->sLocalPara.bToSelfPacketReceived = FALSE;
14792+ Adapter->sLocalPara.WepKeyDetectTimerCount= 2 * 100; /// 2 seconds
14793+
14794+ // Initial USB hal
14795+ InitStep = 1;
14796+ pHwData = &Adapter->sHwData;
14797+ if (!hal_init_hardware(pHwData, Adapter))
14798+ break;
14799+
14800+ EEPROM_region = hal_get_region_from_EEPROM( pHwData );
14801+ if (EEPROM_region != REGION_AUTO)
14802+ psLOCAL->region = EEPROM_region;
14803+ else {
14804+ if (psLOCAL->region_INF != REGION_AUTO)
14805+ psLOCAL->region = psLOCAL->region_INF;
14806+ else
14807+ psLOCAL->region = REGION_USA; //default setting
14808+ }
14809+
14810+ // Get Software setting flag from hal
14811+ Adapter->sLocalPara.boAntennaDiversity = FALSE;
14812+ if (hal_software_set(pHwData) & 0x00000001)
14813+ Adapter->sLocalPara.boAntennaDiversity = TRUE;
14814+
14815+ //
14816+ // For TS module
14817+ //
14818+ InitStep = 2;
14819+
14820+ // For MDS module
14821+ InitStep = 3;
14822+ Mds_initial(Adapter);
14823+
14824+ //=======================================
14825+ // Initialize the SME, SCAN, MLME, ROAM
14826+ //=======================================
14827+ InitStep = 4;
14828+ InitStep = 5;
14829+ InitStep = 6;
14830+
14831+ // If no user-defined address in the registry, use the addresss "burned" on the NIC instead.
14832+ pMacAddr = Adapter->sLocalPara.ThisMacAddress;
14833+ pMacAddr2 = Adapter->sLocalPara.PermanentAddress;
14834+ hal_get_permanent_address( pHwData, Adapter->sLocalPara.PermanentAddress );// Reading ethernet address from EEPROM
14835+ if (OS_MEMORY_COMPARE(pMacAddr, "\x00\x00\x00\x00\x00\x00", MAC_ADDR_LENGTH )) // Is equal
14836+ {
14837+ memcpy( pMacAddr, pMacAddr2, MAC_ADDR_LENGTH );
14838+ } else {
14839+ // Set the user define MAC address
14840+ hal_set_ethernet_address( pHwData, Adapter->sLocalPara.ThisMacAddress );
14841+ }
14842+
14843+ //get current antenna
14844+ psLOCAL->bAntennaNo = hal_get_antenna_number(pHwData);
14845+#ifdef _PE_STATE_DUMP_
14846+ WBDEBUG(("Driver init, antenna no = %d\n", psLOCAL->bAntennaNo));
14847+#endif
14848+ hal_get_hw_radio_off( pHwData );
14849+
14850+ // Waiting for HAL setting OK
14851+ while (!hal_idle(pHwData))
14852+ OS_SLEEP(10000);
14853+
14854+ MTO_Init(Adapter);
14855+
14856+ HwRadioOff = hal_get_hw_radio_off( pHwData );
14857+ psLOCAL->RadioOffStatus.boHwRadioOff = !!HwRadioOff;
14858+
14859+ hal_set_radio_mode( pHwData, (unsigned char)(psLOCAL->RadioOffStatus.boSwRadioOff || psLOCAL->RadioOffStatus.boHwRadioOff) );
14860+
14861+ hal_driver_init_OK(pHwData) = 1; // Notify hal that the driver is ready now.
14862+ //set a tx power for reference.....
14863+// sme_set_tx_power_level(Adapter, 12); FIXME?
14864+ return TRUE;
14865+ }
14866+ while(FALSE);
14867+
14868+ switch (InitStep) {
14869+ case 5:
14870+ case 4:
14871+ case 3: Mds_Destroy( Adapter );
14872+ case 2:
14873+ case 1: WBLINUX_Destroy( Adapter );
14874+ hal_halt( pHwData, NULL );
14875+ case 0: break;
14876+ }
14877+
14878+ return FALSE;
14879+}
14880+
14881+void WBLINUX_ConnectStatus(PADAPTER Adapter, u32 flag)
14882+{
14883+ PWBLINUX pWbLinux = &Adapter->WbLinux;
14884+
14885+ pWbLinux->LinkStatus = flag; // OS_DISCONNECTED or OS_CONNECTED
14886+}
14887+
14888diff --git a/drivers/staging/winbond/wblinux_f.h b/drivers/staging/winbond/wblinux_f.h
14889new file mode 100644
14890index 0000000..68240c5
14891--- /dev/null
14892+++ b/drivers/staging/winbond/wblinux_f.h
14893@@ -0,0 +1,23 @@
14894+//=========================================================================
14895+// Copyright (c) 1996-2004 Winbond Electronic Corporation
14896+//
14897+// wblinux_f.h
14898+//
14899+u32 WBLINUX_MemoryAlloc( void* *VirtualAddress, u32 Length );
14900+s32 EncapAtomicInc( PADAPTER Adapter, void* pAtomic );
14901+s32 EncapAtomicDec( PADAPTER Adapter, void* pAtomic );
14902+void WBLinux_ReceivePacket( PADAPTER Adapter, PRXLAYER1 pRxLayer1 );
14903+unsigned char WBLINUX_Initial( PADAPTER Adapter );
14904+int wb35_start_xmit(struct sk_buff *skb, struct net_device *netdev );
14905+void WBLINUX_GetNextPacket( PADAPTER Adapter, PDESCRIPTOR pDes );
14906+void WBLINUX_GetNextPacketCompleted( PADAPTER Adapter, PDESCRIPTOR pDes );
14907+void WBLINUX_stop( PADAPTER Adapter );
14908+void WBLINUX_Destroy( PADAPTER Adapter );
14909+void wb35_set_multicast( struct net_device *netdev );
14910+struct net_device_stats * wb35_netdev_stats( struct net_device *netdev );
14911+void WBLINUX_stop( PADAPTER Adapter );
14912+void WbWlanHalt( PADAPTER Adapter );
14913+void WBLINUX_ConnectStatus( PADAPTER Adapter, u32 flag );
14914+
14915+
14916+
14917diff --git a/drivers/staging/winbond/wblinux_s.h b/drivers/staging/winbond/wblinux_s.h
14918new file mode 100644
14919index 0000000..97e9167
14920--- /dev/null
14921+++ b/drivers/staging/winbond/wblinux_s.h
14922@@ -0,0 +1,45 @@
14923+//============================================================
14924+// wblinux_s.h
14925+//
14926+#define OS_MEMORY_ALLOC( _V, _S ) WBLINUX_MemoryAlloc( _V, _S )
14927+#define OS_LINK_STATUS (Adapter->WbLinux.LinkStatus == OS_CONNECTED)
14928+#define OS_SET_SHUTDOWN( _A ) _A->WbLinux.shutdown=1
14929+#define OS_SET_RESUME( _A ) _A->WbLinux.shutdown=0
14930+#define OS_CONNECT_STATUS_INDICATE( _A, _F ) WBLINUX_ConnectStatus( _A, _F )
14931+#define OS_DISCONNECTED 0
14932+#define OS_CONNECTED 1
14933+#define OS_STOP( _A ) WBLINUX_stop( _A )
14934+
14935+#define OS_CURRENT_RX_BYTE( _A ) _A->WbLinux.RxByteCount
14936+#define OS_CURRENT_TX_BYTE( _A ) _A->WbLinux.TxByteCount
14937+#define OS_EVENT_INDICATE( _A, _B, _F )
14938+#define OS_PMKID_STATUS_EVENT( _A )
14939+#define OS_RECEIVE_PACKET_INDICATE( _A, _D ) WBLinux_ReceivePacket( _A, _D )
14940+#define OS_RECEIVE_802_1X_PACKET_INDICATE( _A, _D ) EAP_ReceivePacket( _A, _D )
14941+#define OS_GET_PACKET( _A, _D ) WBLINUX_GetNextPacket( _A, _D )
14942+#define OS_GET_PACKET_COMPLETE( _A, _D ) WBLINUX_GetNextPacketCompleted( _A, _D )
14943+#define OS_SEND_RESULT( _A, _ID, _R )
14944+
14945+#define WBLINUX_PACKET_ARRAY_SIZE (ETHERNET_TX_DESCRIPTORS*4)
14946+
14947+typedef struct _WBLINUX
14948+{
14949+ OS_SPIN_LOCK AtomicSpinLock;
14950+ OS_SPIN_LOCK SpinLock;
14951+ u32 shutdown;
14952+
14953+ OS_ATOMIC ThreadCount;
14954+
14955+ u32 LinkStatus; // OS_DISCONNECTED or OS_CONNECTED
14956+
14957+ u32 RxByteCount;
14958+ u32 TxByteCount;
14959+
14960+ struct sk_buff *skb_array[ WBLINUX_PACKET_ARRAY_SIZE ];
14961+ struct sk_buff *packet_return;
14962+ s32 skb_SetIndex;
14963+ s32 skb_GetIndex;
14964+ s32 netif_state_stop; // 1: stop 0: normal
14965+} WBLINUX, *PWBLINUX;
14966+
14967+
14968--
149691.6.0.2
14970
Peter's tree of IPFire 2.x