projects / people / pmueller / ipfire-2.x.git / blame
| Commit | Line | Data |
|---|---|---|
| 2cb7cef9 BS |
1 | From: John Ronciak <john.ronciak@intel.com> |
| 2 | Acked-by: Karsten Keil <kkeil@novell.com> | |
| 3 | Subject: e1000e: enable ECC | |
| 4 | Bugzilla: bnc#445829 | |
| 5 | ||
| 6 | Small fix accepted upstream to enable ECC in Ophir HW in the e1000e driver. | |
| 7 | I'll attach the patch next. IBM is asking for us to get this fix into the | |
| 8 | disti releases. | |
| 9 | ||
| 10 | drivers/net/e1000e/82571.c | 6 ++++++ | |
| 11 | drivers/net/e1000e/defines.h | 7 +++++++ | |
| 12 | drivers/net/e1000e/hw.h | 1 + | |
| 13 | 3 files changed, 14 insertions(+), 0 deletions(-) | |
| 14 | ||
| 15 | ||
| 16 | Index: linux-2.6.27/drivers/net/e1000e/82571.c | |
| 17 | =================================================================== | |
| 18 | --- linux-2.6.27.orig/drivers/net/e1000e/82571.c | |
| 19 | +++ linux-2.6.27/drivers/net/e1000e/82571.c | |
| 20 | @@ -973,6 +973,12 @@ static void e1000_initialize_hw_bits_825 | |
| 21 | ew32(CTRL_EXT, reg); | |
| 22 | } | |
| 23 | ||
| 24 | + if (hw->mac.type == e1000_82571) { | |
| 25 | + reg = er32(PBA_ECC); | |
| 26 | + reg |= E1000_PBA_ECC_CORR_EN; | |
| 27 | + ew32(PBA_ECC, reg); | |
| 28 | + } | |
| 29 | + | |
| 30 | /* PCI-Ex Control Register */ | |
| 31 | if (hw->mac.type == e1000_82574) { | |
| 32 | reg = er32(GCR); | |
| 33 | Index: linux-2.6.27/drivers/net/e1000e/defines.h | |
| 34 | =================================================================== | |
| 35 | --- linux-2.6.27.orig/drivers/net/e1000e/defines.h | |
| 36 | +++ linux-2.6.27/drivers/net/e1000e/defines.h | |
| 37 | @@ -372,6 +372,13 @@ | |
| 38 | #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ | |
| 39 | #define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */ | |
| 40 | ||
| 41 | +/* PBA ECC Register */ | |
| 42 | +#define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ | |
| 43 | +#define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ | |
| 44 | +#define E1000_PBA_ECC_CORR_EN 0x00000001 /* ECC correction enable */ | |
| 45 | +#define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ | |
| 46 | +#define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 for ECC */ | |
| 47 | + | |
| 48 | /* | |
| 49 | * This defines the bits that are set in the Interrupt Mask | |
| 50 | * Set/Read Register. Each bit is documented below: | |
| 51 | Index: linux-2.6.27/drivers/net/e1000e/hw.h | |
| 52 | =================================================================== | |
| 53 | --- linux-2.6.27.orig/drivers/net/e1000e/hw.h | |
| 54 | +++ linux-2.6.27/drivers/net/e1000e/hw.h | |
| 55 | @@ -87,6 +87,7 @@ enum e1e_registers { | |
| 56 | E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */ | |
| 57 | E1000_EEWR = 0x0102C, /* EEPROM Write Register - RW */ | |
| 58 | E1000_FLOP = 0x0103C, /* FLASH Opcode Register */ | |
| 59 | + E1000_PBA_ECC = 0x01100, /* PBA ECC Register */ | |
| 60 | E1000_ERT = 0x02008, /* Early Rx Threshold - RW */ | |
| 61 | E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */ | |
| 62 | E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */ |