]> git.ipfire.org Git - people/pmueller/ipfire-2.x.git/blob - src/et131x/et1310_address_map.h
projects / people / pmueller / ipfire-2.x.git / blob
? search:


3c85999d64dbc81dd055210e7659b597a430bebe
[people/pmueller/ipfire-2.x.git] / src / et131x / et1310_address_map.h
1 /*
2 * Agere Systems Inc.
3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
4 *
5 * Copyright © 2005 Agere Systems Inc.
6 * All rights reserved.
7 * http://www.agere.com
8 *
9 *------------------------------------------------------------------------------
10 *
11 * et1310_address_map.h - Contains the register mapping for the ET1310
12 *
13 *------------------------------------------------------------------------------
14 *
15 * SOFTWARE LICENSE
16 *
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
21 *
22 * Copyright © 2005 Agere Systems Inc.
23 * All rights reserved.
24 *
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
27 *
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
31 * distribution.
32 *
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
36 *
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
40 *
41 * Disclaimer
42 *
43 * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
47 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
48 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
49 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
51 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
54 * DAMAGE.
55 *
56 */
57
58 #ifndef _ET1310_ADDRESS_MAP_H_
59 #define _ET1310_ADDRESS_MAP_H_
60
61
62 /* START OF GLOBAL REGISTER ADDRESS MAP */
63
64 typedef union _Q_ADDR_t {
65 u32 value;
66 struct {
67 #ifdef _BIT_FIELDS_HTOL
68 u32 unused:22; // bits 10-31
69 u32 addr:10; // bits 0-9
70 #else
71 u32 addr:10; // bits 0-9
72 u32 unused:22; // bits 10-31
73 #endif
74 } bits;
75 } Q_ADDR_t, *PQ_ADDR_t;
76
77 /*
78 * structure for tx queue start address reg in global address map
79 * located at address 0x0000
80 * Defined earlier (Q_ADDR_t)
81 */
82
83 /*
84 * structure for tx queue end address reg in global address map
85 * located at address 0x0004
86 * Defined earlier (Q_ADDR_t)
87 */
88
89 /*
90 * structure for rx queue start address reg in global address map
91 * located at address 0x0008
92 * Defined earlier (Q_ADDR_t)
93 */
94
95 /*
96 * structure for rx queue end address reg in global address map
97 * located at address 0x000C
98 * Defined earlier (Q_ADDR_t)
99 */
100
101 /*
102 * structure for power management control status reg in global address map
103 * located at address 0x0010
104 */
105 typedef union _PM_CSR_t {
106 u32 value;
107 struct {
108 #ifdef _BIT_FIELDS_HTOL
109 u32 unused:22; // bits 10-31
110 u32 pm_jagcore_rx_rdy:1; // bit 9
111 u32 pm_jagcore_tx_rdy:1; // bit 8
112 u32 pm_phy_lped_en:1; // bit 7
113 u32 pm_phy_sw_coma:1; // bit 6
114 u32 pm_rxclk_gate:1; // bit 5
115 u32 pm_txclk_gate:1; // bit 4
116 u32 pm_sysclk_gate:1; // bit 3
117 u32 pm_jagcore_rx_en:1; // bit 2
118 u32 pm_jagcore_tx_en:1; // bit 1
119 u32 pm_gigephy_en:1; // bit 0
120 #else
121 u32 pm_gigephy_en:1; // bit 0
122 u32 pm_jagcore_tx_en:1; // bit 1
123 u32 pm_jagcore_rx_en:1; // bit 2
124 u32 pm_sysclk_gate:1; // bit 3
125 u32 pm_txclk_gate:1; // bit 4
126 u32 pm_rxclk_gate:1; // bit 5
127 u32 pm_phy_sw_coma:1; // bit 6
128 u32 pm_phy_lped_en:1; // bit 7
129 u32 pm_jagcore_tx_rdy:1; // bit 8
130 u32 pm_jagcore_rx_rdy:1; // bit 9
131 u32 unused:22; // bits 10-31
132 #endif
133 } bits;
134 } PM_CSR_t, *PPM_CSR_t;
135
136 /*
137 * structure for interrupt status reg in global address map
138 * located at address 0x0018
139 */
140 typedef union _INTERRUPT_t {
141 u32 value;
142 struct {
143 #ifdef _BIT_FIELDS_HTOL
144 u32 unused5:11; // bits 21-31
145 u32 slv_timeout:1; // bit 20
146 u32 mac_stat_interrupt:1; // bit 19
147 u32 rxmac_interrupt:1; // bit 18
148 u32 txmac_interrupt:1; // bit 17
149 u32 phy_interrupt:1; // bit 16
150 u32 wake_on_lan:1; // bit 15
151 u32 watchdog_interrupt:1; // bit 14
152 u32 unused4:4; // bits 10-13
153 u32 rxdma_err:1; // bit 9
154 u32 rxdma_pkt_stat_ring_low:1; // bit 8
155 u32 rxdma_fb_ring1_low:1; // bit 7
156 u32 rxdma_fb_ring0_low:1; // bit 6
157 u32 rxdma_xfr_done:1; // bit 5
158 u32 txdma_err:1; // bit 4
159 u32 txdma_isr:1; // bit 3
160 u32 unused3:1; // bit 2
161 u32 unused2:1; // bit 1
162 u32 unused1:1; // bit 0
163 #else
164 u32 unused1:1; // bit 0
165 u32 unused2:1; // bit 1
166 u32 unused3:1; // bit 2
167 u32 txdma_isr:1; // bit 3
168 u32 txdma_err:1; // bit 4
169 u32 rxdma_xfr_done:1; // bit 5
170 u32 rxdma_fb_ring0_low:1; // bit 6
171 u32 rxdma_fb_ring1_low:1; // bit 7
172 u32 rxdma_pkt_stat_ring_low:1; // bit 8
173 u32 rxdma_err:1; // bit 9
174 u32 unused4:4; // bits 10-13
175 u32 watchdog_interrupt:1; // bit 14
176 u32 wake_on_lan:1; // bit 15
177 u32 phy_interrupt:1; // bit 16
178 u32 txmac_interrupt:1; // bit 17
179 u32 rxmac_interrupt:1; // bit 18
180 u32 mac_stat_interrupt:1; // bit 19
181 u32 slv_timeout:1; // bit 20
182 u32 unused5:11; // bits 21-31
183 #endif
184 } bits;
185 } INTERRUPT_t, *PINTERRUPT_t;
186
187 /*
188 * structure for interrupt mask reg in global address map
189 * located at address 0x001C
190 * Defined earlier (INTERRUPT_t), but 'watchdog_interrupt' is not used.
191 */
192
193 /*
194 * structure for interrupt alias clear mask reg in global address map
195 * located at address 0x0020
196 * Defined earlier (INTERRUPT_t)
197 */
198
199 /*
200 * structure for interrupt status alias reg in global address map
201 * located at address 0x0024
202 * Defined earlier (INTERRUPT_t)
203 */
204
205 /*
206 * structure for software reset reg in global address map
207 * located at address 0x0028
208 */
209 typedef union _SW_RESET_t {
210 u32 value;
211 struct {
212 #ifdef _BIT_FIELDS_HTOL
213 u32 selfclr_disable:1; // bit 31
214 u32 unused:24; // bits 7-30
215 u32 mmc_sw_reset:1; // bit 6
216 u32 mac_stat_sw_reset:1; // bit 5
217 u32 mac_sw_reset:1; // bit 4
218 u32 rxmac_sw_reset:1; // bit 3
219 u32 txmac_sw_reset:1; // bit 2
220 u32 rxdma_sw_reset:1; // bit 1
221 u32 txdma_sw_reset:1; // bit 0
222 #else
223 u32 txdma_sw_reset:1; // bit 0
224 u32 rxdma_sw_reset:1; // bit 1
225 u32 txmac_sw_reset:1; // bit 2
226 u32 rxmac_sw_reset:1; // bit 3
227 u32 mac_sw_reset:1; // bit 4
228 u32 mac_stat_sw_reset:1; // bit 5
229 u32 mmc_sw_reset:1; // bit 6
230 u32 unused:24; // bits 7-30
231 u32 selfclr_disable:1; // bit 31
232 #endif
233 } bits;
234 } SW_RESET_t, *PSW_RESET_t;
235
236 /*
237 * structure for SLV Timer reg in global address map
238 * located at address 0x002C
239 */
240 typedef union _SLV_TIMER_t {
241 u32 value;
242 struct {
243 #ifdef _BIT_FIELDS_HTOL
244 u32 unused:8; // bits 24-31
245 u32 timer_ini:24; // bits 0-23
246 #else
247 u32 timer_ini:24; // bits 0-23
248 u32 unused:8; // bits 24-31
249 #endif
250 } bits;
251 } SLV_TIMER_t, *PSLV_TIMER_t;
252
253 /*
254 * structure for MSI Configuration reg in global address map
255 * located at address 0x0030
256 */
257 typedef union _MSI_CONFIG_t {
258 u32 value;
259 struct {
260 #ifdef _BIT_FIELDS_HTOL
261 u32 unused1:13; // bits 19-31
262 u32 msi_tc:3; // bits 16-18
263 u32 unused2:11; // bits 5-15
264 u32 msi_vector:5; // bits 0-4
265 #else
266 u32 msi_vector:5; // bits 0-4
267 u32 unused2:11; // bits 5-15
268 u32 msi_tc:3; // bits 16-18
269 u32 unused1:13; // bits 19-31
270 #endif
271 } bits;
272 } MSI_CONFIG_t, *PMSI_CONFIG_t;
273
274 /*
275 * structure for Loopback reg in global address map
276 * located at address 0x0034
277 */
278 typedef union _LOOPBACK_t {
279 u32 value;
280 struct {
281 #ifdef _BIT_FIELDS_HTOL
282 u32 unused:30; // bits 2-31
283 u32 dma_loopback:1; // bit 1
284 u32 mac_loopback:1; // bit 0
285 #else
286 u32 mac_loopback:1; // bit 0
287 u32 dma_loopback:1; // bit 1
288 u32 unused:30; // bits 2-31
289 #endif
290 } bits;
291 } LOOPBACK_t, *PLOOPBACK_t;
292
293 /*
294 * GLOBAL Module of JAGCore Address Mapping
295 * Located at address 0x0000
296 */
297 typedef struct _GLOBAL_t { // Location:
298 Q_ADDR_t txq_start_addr; // 0x0000
299 Q_ADDR_t txq_end_addr; // 0x0004
300 Q_ADDR_t rxq_start_addr; // 0x0008
301 Q_ADDR_t rxq_end_addr; // 0x000C
302 PM_CSR_t pm_csr; // 0x0010
303 u32 unused; // 0x0014
304 INTERRUPT_t int_status; // 0x0018
305 INTERRUPT_t int_mask; // 0x001C
306 INTERRUPT_t int_alias_clr_en; // 0x0020
307 INTERRUPT_t int_status_alias; // 0x0024
308 SW_RESET_t sw_reset; // 0x0028
309 SLV_TIMER_t slv_timer; // 0x002C
310 MSI_CONFIG_t msi_config; // 0x0030
311 LOOPBACK_t loopback; // 0x0034
312 u32 watchdog_timer; // 0x0038
313 } GLOBAL_t, *PGLOBAL_t;
314
315 /* END OF GLOBAL REGISTER ADDRESS MAP */
316
317
318 /* START OF TXDMA REGISTER ADDRESS MAP */
319
320 /*
321 * structure for txdma control status reg in txdma address map
322 * located at address 0x1000
323 */
324 typedef union _TXDMA_CSR_t {
325 u32 value;
326 struct {
327 #ifdef _BIT_FIELDS_HTOL
328 u32 unused2:19; // bits 13-31
329 u32 traffic_class:4; // bits 9-12
330 u32 sngl_epkt_mode:1; // bit 8
331 u32 cache_thrshld:4; // bits 4-7
332 u32 unused1:2; // bits 2-3
333 u32 drop_TLP_disable:1; // bit 1
334 u32 halt:1; // bit 0
335 #else
336 u32 halt:1; // bit 0
337 u32 drop_TLP_disable:1; // bit 1
338 u32 unused1:2; // bits 2-3
339 u32 cache_thrshld:4; // bits 4-7
340 u32 sngl_epkt_mode:1; // bit 8
341 u32 traffic_class:4; // bits 9-12
342 u32 unused2:19; // bits 13-31
343 #endif
344 } bits;
345 } TXDMA_CSR_t, *PTXDMA_CSR_t;
346
347 /*
348 * structure for txdma packet ring base address hi reg in txdma address map
349 * located at address 0x1004
350 * Defined earlier (u32)
351 */
352
353 /*
354 * structure for txdma packet ring base address low reg in txdma address map
355 * located at address 0x1008
356 * Defined earlier (u32)
357 */
358
359 /*
360 * structure for txdma packet ring number of descriptor reg in txdma address
361 * map. Located at address 0x100C
362 */
363 typedef union _TXDMA_PR_NUM_DES_t {
364 u32 value;
365 struct {
366 #ifdef _BIT_FIELDS_HTOL
367 u32 unused:22; // bits 10-31
368 u32 pr_ndes:10; // bits 0-9
369 #else
370 u32 pr_ndes:10; // bits 0-9
371 u32 unused:22; // bits 10-31
372 #endif
373 } bits;
374 } TXDMA_PR_NUM_DES_t, *PTXDMA_PR_NUM_DES_t;
375
376
377 typedef union _DMA10W_t {
378 u32 value;
379 struct {
380 #ifdef _BIT_FIELDS_HTOL
381 u32 unused:21; // bits 11-31
382 u32 wrap:1; // bit 10
383 u32 val:10; // bits 0-9
384 #else
385 u32 val:10; // bits 0-9
386 u32 wrap:1; // bit 10
387 u32 unused:21; // bits 11-31
388 #endif
389 } bits;
390 } DMA10W_t, *PDMA10W_t;
391
392 /*
393 * structure for txdma tx queue write address reg in txdma address map
394 * located at address 0x1010
395 * Defined earlier (DMA10W_t)
396 */
397
398 /*
399 * structure for txdma tx queue write address external reg in txdma address map
400 * located at address 0x1014
401 * Defined earlier (DMA10W_t)
402 */
403
404 /*
405 * structure for txdma tx queue read address reg in txdma address map
406 * located at address 0x1018
407 * Defined earlier (DMA10W_t)
408 */
409
410 /*
411 * structure for txdma status writeback address hi reg in txdma address map
412 * located at address 0x101C
413 * Defined earlier (u32)
414 */
415
416 /*
417 * structure for txdma status writeback address lo reg in txdma address map
418 * located at address 0x1020
419 * Defined earlier (u32)
420 */
421
422 /*
423 * structure for txdma service request reg in txdma address map
424 * located at address 0x1024
425 * Defined earlier (DMA10W_t)
426 */
427
428 /*
429 * structure for txdma service complete reg in txdma address map
430 * located at address 0x1028
431 * Defined earlier (DMA10W_t)
432 */
433
434 typedef union _DMA4W_t {
435 u32 value;
436 struct {
437 #ifdef _BIT_FIELDS_HTOL
438 u32 unused:27; // bits 5-31
439 u32 wrap:1; // bit 4
440 u32 val:4; // bit 0-3
441 #else
442 u32 val:4; // bits 0-3
443 u32 wrap:1; // bit 4
444 u32 unused:27; // bits 5-31
445 #endif
446 } bits;
447 } DMA4W_t, *PDMA4W_t;
448
449 /*
450 * structure for txdma tx descriptor cache read index reg in txdma address map
451 * located at address 0x102C
452 * Defined earlier (DMA4W_t)
453 */
454
455 /*
456 * structure for txdma tx descriptor cache write index reg in txdma address map
457 * located at address 0x1030
458 * Defined earlier (DMA4W_t)
459 */
460
461 /*
462 * structure for txdma error reg in txdma address map
463 * located at address 0x1034
464 */
465 typedef union _TXDMA_ERROR_t {
466 u32 value;
467 struct {
468 #ifdef _BIT_FIELDS_HTOL
469 u32 unused3:22; // bits 10-31
470 u32 WrbkRewind:1; // bit 9
471 u32 WrbkResend:1; // bit 8
472 u32 unused2:2; // bits 6-7
473 u32 DescrRewind:1; // bit 5
474 u32 DescrResend:1; // bit 4
475 u32 unused1:2; // bits 2-3
476 u32 PyldRewind:1; // bit 1
477 u32 PyldResend:1; // bit 0
478 #else
479 u32 PyldResend:1; // bit 0
480 u32 PyldRewind:1; // bit 1
481 u32 unused1:2; // bits 2-3
482 u32 DescrResend:1; // bit 4
483 u32 DescrRewind:1; // bit 5
484 u32 unused2:2; // bits 6-7
485 u32 WrbkResend:1; // bit 8
486 u32 WrbkRewind:1; // bit 9
487 u32 unused3:22; // bits 10-31
488 #endif
489 } bits;
490 } TXDMA_ERROR_t, *PTXDMA_ERROR_t;
491
492 /*
493 * Tx DMA Module of JAGCore Address Mapping
494 * Located at address 0x1000
495 */
496 typedef struct _TXDMA_t { // Location:
497 TXDMA_CSR_t csr; // 0x1000
498 u32 pr_base_hi; // 0x1004
499 u32 pr_base_lo; // 0x1008
500 TXDMA_PR_NUM_DES_t pr_num_des; // 0x100C
501 DMA10W_t txq_wr_addr; // 0x1010
502 DMA10W_t txq_wr_addr_ext; // 0x1014
503 DMA10W_t txq_rd_addr; // 0x1018
504 u32 dma_wb_base_hi; // 0x101C
505 u32 dma_wb_base_lo; // 0x1020
506 DMA10W_t service_request; // 0x1024
507 DMA10W_t service_complete; // 0x1028
508 DMA4W_t cache_rd_index; // 0x102C
509 DMA4W_t cache_wr_index; // 0x1030
510 TXDMA_ERROR_t TxDmaError; // 0x1034
511 u32 DescAbortCount; // 0x1038
512 u32 PayloadAbortCnt; // 0x103c
513 u32 WriteBackAbortCnt; // 0x1040
514 u32 DescTimeoutCnt; // 0x1044
515 u32 PayloadTimeoutCnt; // 0x1048
516 u32 WriteBackTimeoutCnt; // 0x104c
517 u32 DescErrorCount; // 0x1050
518 u32 PayloadErrorCnt; // 0x1054
519 u32 WriteBackErrorCnt; // 0x1058
520 u32 DroppedTLPCount; // 0x105c
521 DMA10W_t NewServiceComplete; // 0x1060
522 u32 EthernetPacketCount; // 0x1064
523 } TXDMA_t, *PTXDMA_t;
524
525 /* END OF TXDMA REGISTER ADDRESS MAP */
526
527
528 /* START OF RXDMA REGISTER ADDRESS MAP */
529
530 /*
531 * structure for control status reg in rxdma address map
532 * Located at address 0x2000
533 */
534 typedef union _RXDMA_CSR_t {
535 u32 value;
536 struct {
537 #ifdef _BIT_FIELDS_HTOL
538 u32 unused2:14; // bits 18-31
539 u32 halt_status:1; // bit 17
540 u32 pkt_done_flush:1; // bit 16
541 u32 pkt_drop_disable:1; // bit 15
542 u32 unused1:1; // bit 14
543 u32 fbr1_enable:1; // bit 13
544 u32 fbr1_size:2; // bits 11-12
545 u32 fbr0_enable:1; // bit 10
546 u32 fbr0_size:2; // bits 8-9
547 u32 dma_big_endian:1; // bit 7
548 u32 pkt_big_endian:1; // bit 6
549 u32 psr_big_endian:1; // bit 5
550 u32 fbr_big_endian:1; // bit 4
551 u32 tc:3; // bits 1-3
552 u32 halt:1; // bit 0
553 #else
554 u32 halt:1; // bit 0
555 u32 tc:3; // bits 1-3
556 u32 fbr_big_endian:1; // bit 4
557 u32 psr_big_endian:1; // bit 5
558 u32 pkt_big_endian:1; // bit 6
559 u32 dma_big_endian:1; // bit 7
560 u32 fbr0_size:2; // bits 8-9
561 u32 fbr0_enable:1; // bit 10
562 u32 fbr1_size:2; // bits 11-12
563 u32 fbr1_enable:1; // bit 13
564 u32 unused1:1; // bit 14
565 u32 pkt_drop_disable:1; // bit 15
566 u32 pkt_done_flush:1; // bit 16
567 u32 halt_status:1; // bit 17
568 u32 unused2:14; // bits 18-31
569 #endif
570 } bits;
571 } RXDMA_CSR_t, *PRXDMA_CSR_t;
572
573 /*
574 * structure for dma writeback lo reg in rxdma address map
575 * located at address 0x2004
576 * Defined earlier (u32)
577 */
578
579 /*
580 * structure for dma writeback hi reg in rxdma address map
581 * located at address 0x2008
582 * Defined earlier (u32)
583 */
584
585 /*
586 * structure for number of packets done reg in rxdma address map
587 * located at address 0x200C
588 */
589 typedef union _RXDMA_NUM_PKT_DONE_t {
590 u32 value;
591 struct {
592 #ifdef _BIT_FIELDS_HTOL
593 u32 unused:24; // bits 8-31
594 u32 num_done:8; // bits 0-7
595 #else
596 u32 num_done:8; // bits 0-7
597 u32 unused:24; // bits 8-31
598 #endif
599 } bits;
600 } RXDMA_NUM_PKT_DONE_t, *PRXDMA_NUM_PKT_DONE_t;
601
602 /*
603 * structure for max packet time reg in rxdma address map
604 * located at address 0x2010
605 */
606 typedef union _RXDMA_MAX_PKT_TIME_t {
607 u32 value;
608 struct {
609 #ifdef _BIT_FIELDS_HTOL
610 u32 unused:14; // bits 18-31
611 u32 time_done:18; // bits 0-17
612 #else
613 u32 time_done:18; // bits 0-17
614 u32 unused:14; // bits 18-31
615 #endif
616 } bits;
617 } RXDMA_MAX_PKT_TIME_t, *PRXDMA_MAX_PKT_TIME_t;
618
619 /*
620 * structure for rx queue read address reg in rxdma address map
621 * located at address 0x2014
622 * Defined earlier (DMA10W_t)
623 */
624
625 /*
626 * structure for rx queue read address external reg in rxdma address map
627 * located at address 0x2018
628 * Defined earlier (DMA10W_t)
629 */
630
631 /*
632 * structure for rx queue write address reg in rxdma address map
633 * located at address 0x201C
634 * Defined earlier (DMA10W_t)
635 */
636
637 /*
638 * structure for packet status ring base address lo reg in rxdma address map
639 * located at address 0x2020
640 * Defined earlier (u32)
641 */
642
643 /*
644 * structure for packet status ring base address hi reg in rxdma address map
645 * located at address 0x2024
646 * Defined earlier (u32)
647 */
648
649 /*
650 * structure for packet status ring number of descriptors reg in rxdma address
651 * map. Located at address 0x2028
652 */
653 typedef union _RXDMA_PSR_NUM_DES_t {
654 u32 value;
655 struct {
656 #ifdef _BIT_FIELDS_HTOL
657 u32 unused:20; // bits 12-31
658 u32 psr_ndes:12; // bit 0-11
659 #else
660 u32 psr_ndes:12; // bit 0-11
661 u32 unused:20; // bits 12-31
662 #endif
663 } bits;
664 } RXDMA_PSR_NUM_DES_t, *PRXDMA_PSR_NUM_DES_t;
665
666 /*
667 * structure for packet status ring available offset reg in rxdma address map
668 * located at address 0x202C
669 */
670 typedef union _RXDMA_PSR_AVAIL_OFFSET_t {
671 u32 value;
672 struct {
673 #ifdef _BIT_FIELDS_HTOL
674 u32 unused:19; // bits 13-31
675 u32 psr_avail_wrap:1; // bit 12
676 u32 psr_avail:12; // bit 0-11
677 #else
678 u32 psr_avail:12; // bit 0-11
679 u32 psr_avail_wrap:1; // bit 12
680 u32 unused:19; // bits 13-31
681 #endif
682 } bits;
683 } RXDMA_PSR_AVAIL_OFFSET_t, *PRXDMA_PSR_AVAIL_OFFSET_t;
684
685 /*
686 * structure for packet status ring full offset reg in rxdma address map
687 * located at address 0x2030
688 */
689 typedef union _RXDMA_PSR_FULL_OFFSET_t {
690 u32 value;
691 struct {
692 #ifdef _BIT_FIELDS_HTOL
693 u32 unused:19; // bits 13-31
694 u32 psr_full_wrap:1; // bit 12
695 u32 psr_full:12; // bit 0-11
696 #else
697 u32 psr_full:12; // bit 0-11
698 u32 psr_full_wrap:1; // bit 12
699 u32 unused:19; // bits 13-31
700 #endif
701 } bits;
702 } RXDMA_PSR_FULL_OFFSET_t, *PRXDMA_PSR_FULL_OFFSET_t;
703
704 /*
705 * structure for packet status ring access index reg in rxdma address map
706 * located at address 0x2034
707 */
708 typedef union _RXDMA_PSR_ACCESS_INDEX_t {
709 u32 value;
710 struct {
711 #ifdef _BIT_FIELDS_HTOL
712 u32 unused:27; // bits 5-31
713 u32 psr_ai:5; // bits 0-4
714 #else
715 u32 psr_ai:5; // bits 0-4
716 u32 unused:27; // bits 5-31
717 #endif
718 } bits;
719 } RXDMA_PSR_ACCESS_INDEX_t, *PRXDMA_PSR_ACCESS_INDEX_t;
720
721 /*
722 * structure for packet status ring minimum descriptors reg in rxdma address
723 * map. Located at address 0x2038
724 */
725 typedef union _RXDMA_PSR_MIN_DES_t {
726 u32 value;
727 struct {
728 #ifdef _BIT_FIELDS_HTOL
729 u32 unused:20; // bits 12-31
730 u32 psr_min:12; // bits 0-11
731 #else
732 u32 psr_min:12; // bits 0-11
733 u32 unused:20; // bits 12-31
734 #endif
735 } bits;
736 } RXDMA_PSR_MIN_DES_t, *PRXDMA_PSR_MIN_DES_t;
737
738 /*
739 * structure for free buffer ring base lo address reg in rxdma address map
740 * located at address 0x203C
741 * Defined earlier (u32)
742 */
743
744 /*
745 * structure for free buffer ring base hi address reg in rxdma address map
746 * located at address 0x2040
747 * Defined earlier (u32)
748 */
749
750 /*
751 * structure for free buffer ring number of descriptors reg in rxdma address
752 * map. Located at address 0x2044
753 */
754 typedef union _RXDMA_FBR_NUM_DES_t {
755 u32 value;
756 struct {
757 #ifdef _BIT_FIELDS_HTOL
758 u32 unused:22; // bits 10-31
759 u32 fbr_ndesc:10; // bits 0-9
760 #else
761 u32 fbr_ndesc:10; // bits 0-9
762 u32 unused:22; // bits 10-31
763 #endif
764 } bits;
765 } RXDMA_FBR_NUM_DES_t, *PRXDMA_FBR_NUM_DES_t;
766
767 /*
768 * structure for free buffer ring 0 available offset reg in rxdma address map
769 * located at address 0x2048
770 * Defined earlier (DMA10W_t)
771 */
772
773 /*
774 * structure for free buffer ring 0 full offset reg in rxdma address map
775 * located at address 0x204C
776 * Defined earlier (DMA10W_t)
777 */
778
779 /*
780 * structure for free buffer cache 0 full offset reg in rxdma address map
781 * located at address 0x2050
782 */
783 typedef union _RXDMA_FBC_RD_INDEX_t {
784 u32 value;
785 struct {
786 #ifdef _BIT_FIELDS_HTOL
787 u32 unused:27; // bits 5-31
788 u32 fbc_rdi:5; // bit 0-4
789 #else
790 u32 fbc_rdi:5; // bit 0-4
791 u32 unused:27; // bits 5-31
792 #endif
793 } bits;
794 } RXDMA_FBC_RD_INDEX_t, *PRXDMA_FBC_RD_INDEX_t;
795
796 /*
797 * structure for free buffer ring 0 minimum descriptor reg in rxdma address map
798 * located at address 0x2054
799 */
800 typedef union _RXDMA_FBR_MIN_DES_t {
801 u32 value;
802 struct {
803 #ifdef _BIT_FIELDS_HTOL
804 u32 unused:22; // bits 10-31
805 u32 fbr_min:10; // bits 0-9
806 #else
807 u32 fbr_min:10; // bits 0-9
808 u32 unused:22; // bits 10-31
809 #endif
810 } bits;
811 } RXDMA_FBR_MIN_DES_t, *PRXDMA_FBR_MIN_DES_t;
812
813 /*
814 * structure for free buffer ring 1 base address lo reg in rxdma address map
815 * located at address 0x2058 - 0x205C
816 * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
817 */
818
819 /*
820 * structure for free buffer ring 1 number of descriptors reg in rxdma address
821 * map. Located at address 0x2060
822 * Defined earlier (RXDMA_FBR_NUM_DES_t)
823 */
824
825 /*
826 * structure for free buffer ring 1 available offset reg in rxdma address map
827 * located at address 0x2064
828 * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
829 */
830
831 /*
832 * structure for free buffer ring 1 full offset reg in rxdma address map
833 * located at address 0x2068
834 * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
835 */
836
837 /*
838 * structure for free buffer cache 1 read index reg in rxdma address map
839 * located at address 0x206C
840 * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
841 */
842
843 /*
844 * structure for free buffer ring 1 minimum descriptor reg in rxdma address map
845 * located at address 0x2070
846 * Defined Earlier (RXDMA_FBR_MIN_DES_t)
847 */
848
849 /*
850 * Rx DMA Module of JAGCore Address Mapping
851 * Located at address 0x2000
852 */
853 typedef struct _RXDMA_t { // Location:
854 RXDMA_CSR_t csr; // 0x2000
855 u32 dma_wb_base_lo; // 0x2004
856 u32 dma_wb_base_hi; // 0x2008
857 RXDMA_NUM_PKT_DONE_t num_pkt_done; // 0x200C
858 RXDMA_MAX_PKT_TIME_t max_pkt_time; // 0x2010
859 DMA10W_t rxq_rd_addr; // 0x2014
860 DMA10W_t rxq_rd_addr_ext; // 0x2018
861 DMA10W_t rxq_wr_addr; // 0x201C
862 u32 psr_base_lo; // 0x2020
863 u32 psr_base_hi; // 0x2024
864 RXDMA_PSR_NUM_DES_t psr_num_des; // 0x2028
865 RXDMA_PSR_AVAIL_OFFSET_t psr_avail_offset; // 0x202C
866 RXDMA_PSR_FULL_OFFSET_t psr_full_offset; // 0x2030
867 RXDMA_PSR_ACCESS_INDEX_t psr_access_index; // 0x2034
868 RXDMA_PSR_MIN_DES_t psr_min_des; // 0x2038
869 u32 fbr0_base_lo; // 0x203C
870 u32 fbr0_base_hi; // 0x2040
871 RXDMA_FBR_NUM_DES_t fbr0_num_des; // 0x2044
872 DMA10W_t fbr0_avail_offset; // 0x2048
873 DMA10W_t fbr0_full_offset; // 0x204C
874 RXDMA_FBC_RD_INDEX_t fbr0_rd_index; // 0x2050
875 RXDMA_FBR_MIN_DES_t fbr0_min_des; // 0x2054
876 u32 fbr1_base_lo; // 0x2058
877 u32 fbr1_base_hi; // 0x205C
878 RXDMA_FBR_NUM_DES_t fbr1_num_des; // 0x2060
879 DMA10W_t fbr1_avail_offset; // 0x2064
880 DMA10W_t fbr1_full_offset; // 0x2068
881 RXDMA_FBC_RD_INDEX_t fbr1_rd_index; // 0x206C
882 RXDMA_FBR_MIN_DES_t fbr1_min_des; // 0x2070
883 } RXDMA_t, *PRXDMA_t;
884
885 /* END OF RXDMA REGISTER ADDRESS MAP */
886
887
888 /* START OF TXMAC REGISTER ADDRESS MAP */
889
890 /*
891 * structure for control reg in txmac address map
892 * located at address 0x3000
893 */
894 typedef union _TXMAC_CTL_t {
895 u32 value;
896 struct {
897 #ifdef _BIT_FIELDS_HTOL
898 u32 unused:24; // bits 8-31
899 u32 cklseg_diable:1; // bit 7
900 u32 ckbcnt_disable:1; // bit 6
901 u32 cksegnum:1; // bit 5
902 u32 async_disable:1; // bit 4
903 u32 fc_disable:1; // bit 3
904 u32 mcif_disable:1; // bit 2
905 u32 mif_disable:1; // bit 1
906 u32 txmac_en:1; // bit 0
907 #else
908 u32 txmac_en:1; // bit 0
909 u32 mif_disable:1; // bit 1 mac interface
910 u32 mcif_disable:1; // bit 2 mem. contr. interface
911 u32 fc_disable:1; // bit 3
912 u32 async_disable:1; // bit 4
913 u32 cksegnum:1; // bit 5
914 u32 ckbcnt_disable:1; // bit 6
915 u32 cklseg_diable:1; // bit 7
916 u32 unused:24; // bits 8-31
917 #endif
918 } bits;
919 } TXMAC_CTL_t, *PTXMAC_CTL_t;
920
921 /*
922 * structure for shadow pointer reg in txmac address map
923 * located at address 0x3004
924 */
925 typedef union _TXMAC_SHADOW_PTR_t {
926 u32 value;
927 struct {
928 #ifdef _BIT_FIELDS_HTOL
929 u32 reserved2:5; // bits 27-31
930 u32 txq_rd_ptr:11; // bits 16-26
931 u32 reserved:5; // bits 11-15
932 u32 txq_wr_ptr:11; // bits 0-10
933 #else
934 u32 txq_wr_ptr:11; // bits 0-10
935 u32 reserved:5; // bits 11-15
936 u32 txq_rd_ptr:11; // bits 16-26
937 u32 reserved2:5; // bits 27-31
938 #endif
939 } bits;
940 } TXMAC_SHADOW_PTR_t, *PTXMAC_SHADOW_PTR_t;
941
942 /*
943 * structure for error count reg in txmac address map
944 * located at address 0x3008
945 */
946 typedef union _TXMAC_ERR_CNT_t {
947 u32 value;
948 struct {
949 #ifdef _BIT_FIELDS_HTOL
950 u32 unused:20; // bits 12-31
951 u32 reserved:4; // bits 8-11
952 u32 txq_underrun:4; // bits 4-7
953 u32 fifo_underrun:4; // bits 0-3
954 #else
955 u32 fifo_underrun:4; // bits 0-3
956 u32 txq_underrun:4; // bits 4-7
957 u32 reserved:4; // bits 8-11
958 u32 unused:20; // bits 12-31
959 #endif
960 } bits;
961 } TXMAC_ERR_CNT_t, *PTXMAC_ERR_CNT_t;
962
963 /*
964 * structure for max fill reg in txmac address map
965 * located at address 0x300C
966 */
967 typedef union _TXMAC_MAX_FILL_t {
968 u32 value;
969 struct {
970 #ifdef _BIT_FIELDS_HTOL
971 u32 unused:20; // bits 12-31
972 u32 max_fill:12; // bits 0-11
973 #else
974 u32 max_fill:12; // bits 0-11
975 u32 unused:20; // bits 12-31
976 #endif
977 } bits;
978 } TXMAC_MAX_FILL_t, *PTXMAC_MAX_FILL_t;
979
980 /*
981 * structure for cf parameter reg in txmac address map
982 * located at address 0x3010
983 */
984 typedef union _TXMAC_CF_PARAM_t {
985 u32 value;
986 struct {
987 #ifdef _BIT_FIELDS_HTOL
988 u32 cfep:16; // bits 16-31
989 u32 cfpt:16; // bits 0-15
990 #else
991 u32 cfpt:16; // bits 0-15
992 u32 cfep:16; // bits 16-31
993 #endif
994 } bits;
995 } TXMAC_CF_PARAM_t, *PTXMAC_CF_PARAM_t;
996
997 /*
998 * structure for tx test reg in txmac address map
999 * located at address 0x3014
1000 */
1001 typedef union _TXMAC_TXTEST_t {
1002 u32 value;
1003 struct {
1004 #ifdef _BIT_FIELDS_HTOL
1005 u32 unused2:15; // bits 17-31
1006 u32 reserved1:1; // bit 16
1007 u32 txtest_en:1; // bit 15
1008 u32 unused1:4; // bits 11-14
1009 u32 txqtest_ptr:11; // bits 0-11
1010 #else
1011 u32 txqtest_ptr:11; // bits 0-10
1012 u32 unused1:4; // bits 11-14
1013 u32 txtest_en:1; // bit 15
1014 u32 reserved1:1; // bit 16
1015 u32 unused2:15; // bits 17-31
1016 #endif
1017 } bits;
1018 } TXMAC_TXTEST_t, *PTXMAC_TXTEST_t;
1019
1020 /*
1021 * structure for error reg in txmac address map
1022 * located at address 0x3018
1023 */
1024 typedef union _TXMAC_ERR_t {
1025 u32 value;
1026 struct {
1027 #ifdef _BIT_FIELDS_HTOL
1028 u32 unused2:23; // bits 9-31
1029 u32 fifo_underrun:1; // bit 8
1030 u32 unused1:2; // bits 6-7
1031 u32 ctrl2_err:1; // bit 5
1032 u32 txq_underrun:1; // bit 4
1033 u32 bcnt_err:1; // bit 3
1034 u32 lseg_err:1; // bit 2
1035 u32 segnum_err:1; // bit 1
1036 u32 seg0_err:1; // bit 0
1037 #else
1038 u32 seg0_err:1; // bit 0
1039 u32 segnum_err:1; // bit 1
1040 u32 lseg_err:1; // bit 2
1041 u32 bcnt_err:1; // bit 3
1042 u32 txq_underrun:1; // bit 4
1043 u32 ctrl2_err:1; // bit 5
1044 u32 unused1:2; // bits 6-7
1045 u32 fifo_underrun:1; // bit 8
1046 u32 unused2:23; // bits 9-31
1047 #endif
1048 } bits;
1049 } TXMAC_ERR_t, *PTXMAC_ERR_t;
1050
1051 /*
1052 * structure for error interrupt reg in txmac address map
1053 * located at address 0x301C
1054 */
1055 typedef union _TXMAC_ERR_INT_t {
1056 u32 value;
1057 struct {
1058 #ifdef _BIT_FIELDS_HTOL
1059 u32 unused2:23; // bits 9-31
1060 u32 fifo_underrun:1; // bit 8
1061 u32 unused1:2; // bits 6-7
1062 u32 ctrl2_err:1; // bit 5
1063 u32 txq_underrun:1; // bit 4
1064 u32 bcnt_err:1; // bit 3
1065 u32 lseg_err:1; // bit 2
1066 u32 segnum_err:1; // bit 1
1067 u32 seg0_err:1; // bit 0
1068 #else
1069 u32 seg0_err:1; // bit 0
1070 u32 segnum_err:1; // bit 1
1071 u32 lseg_err:1; // bit 2
1072 u32 bcnt_err:1; // bit 3
1073 u32 txq_underrun:1; // bit 4
1074 u32 ctrl2_err:1; // bit 5
1075 u32 unused1:2; // bits 6-7
1076 u32 fifo_underrun:1; // bit 8
1077 u32 unused2:23; // bits 9-31
1078 #endif
1079 } bits;
1080 } TXMAC_ERR_INT_t, *PTXMAC_ERR_INT_t;
1081
1082 /*
1083 * structure for error interrupt reg in txmac address map
1084 * located at address 0x3020
1085 */
1086 typedef union _TXMAC_CP_CTRL_t {
1087 u32 value;
1088 struct {
1089 #ifdef _BIT_FIELDS_HTOL
1090 u32 unused:30; // bits 2-31
1091 u32 bp_req:1; // bit 1
1092 u32 bp_xonxoff:1; // bit 0
1093 #else
1094 u32 bp_xonxoff:1; // bit 0
1095 u32 bp_req:1; // bit 1
1096 u32 unused:30; // bits 2-31
1097 #endif
1098 } bits;
1099 } TXMAC_BP_CTRL_t, *PTXMAC_BP_CTRL_t;
1100
1101 /*
1102 * Tx MAC Module of JAGCore Address Mapping
1103 */
1104 typedef struct _TXMAC_t { // Location:
1105 TXMAC_CTL_t ctl; // 0x3000
1106 TXMAC_SHADOW_PTR_t shadow_ptr; // 0x3004
1107 TXMAC_ERR_CNT_t err_cnt; // 0x3008
1108 TXMAC_MAX_FILL_t max_fill; // 0x300C
1109 TXMAC_CF_PARAM_t cf_param; // 0x3010
1110 TXMAC_TXTEST_t tx_test; // 0x3014
1111 TXMAC_ERR_t err; // 0x3018
1112 TXMAC_ERR_INT_t err_int; // 0x301C
1113 TXMAC_BP_CTRL_t bp_ctrl; // 0x3020
1114 } TXMAC_t, *PTXMAC_t;
1115
1116 /* END OF TXMAC REGISTER ADDRESS MAP */
1117
1118 /* START OF RXMAC REGISTER ADDRESS MAP */
1119
1120 /*
1121 * structure for rxmac control reg in rxmac address map
1122 * located at address 0x4000
1123 */
1124 typedef union _RXMAC_CTRL_t {
1125 u32 value;
1126 struct {
1127 #ifdef _BIT_FIELDS_HTOL
1128 u32 reserved:25; // bits 7-31
1129 u32 rxmac_int_disable:1; // bit 6
1130 u32 async_disable:1; // bit 5
1131 u32 mif_disable:1; // bit 4
1132 u32 wol_disable:1; // bit 3
1133 u32 pkt_filter_disable:1; // bit 2
1134 u32 mcif_disable:1; // bit 1
1135 u32 rxmac_en:1; // bit 0
1136 #else
1137 u32 rxmac_en:1; // bit 0
1138 u32 mcif_disable:1; // bit 1
1139 u32 pkt_filter_disable:1; // bit 2
1140 u32 wol_disable:1; // bit 3
1141 u32 mif_disable:1; // bit 4
1142 u32 async_disable:1; // bit 5
1143 u32 rxmac_int_disable:1; // bit 6
1144 u32 reserved:25; // bits 7-31
1145 #endif
1146 } bits;
1147 } RXMAC_CTRL_t, *PRXMAC_CTRL_t;
1148
1149 /*
1150 * structure for Wake On Lan Control and CRC 0 reg in rxmac address map
1151 * located at address 0x4004
1152 */
1153 typedef union _RXMAC_WOL_CTL_CRC0_t {
1154 u32 value;
1155 struct {
1156 #ifdef _BIT_FIELDS_HTOL
1157 u32 crc0:16; // bits 16-31
1158 u32 reserve:4; // bits 12-15
1159 u32 ignore_pp:1; // bit 11
1160 u32 ignore_mp:1; // bit 10
1161 u32 clr_intr:1; // bit 9
1162 u32 ignore_link_chg:1; // bit 8
1163 u32 ignore_uni:1; // bit 7
1164 u32 ignore_multi:1; // bit 6
1165 u32 ignore_broad:1; // bit 5
1166 u32 valid_crc4:1; // bit 4
1167 u32 valid_crc3:1; // bit 3
1168 u32 valid_crc2:1; // bit 2
1169 u32 valid_crc1:1; // bit 1
1170 u32 valid_crc0:1; // bit 0
1171 #else
1172 u32 valid_crc0:1; // bit 0
1173 u32 valid_crc1:1; // bit 1
1174 u32 valid_crc2:1; // bit 2
1175 u32 valid_crc3:1; // bit 3
1176 u32 valid_crc4:1; // bit 4
1177 u32 ignore_broad:1; // bit 5
1178 u32 ignore_multi:1; // bit 6
1179 u32 ignore_uni:1; // bit 7
1180 u32 ignore_link_chg:1; // bit 8
1181 u32 clr_intr:1; // bit 9
1182 u32 ignore_mp:1; // bit 10
1183 u32 ignore_pp:1; // bit 11
1184 u32 reserve:4; // bits 12-15
1185 u32 crc0:16; // bits 16-31
1186 #endif
1187 } bits;
1188 } RXMAC_WOL_CTL_CRC0_t, *PRXMAC_WOL_CTL_CRC0_t;
1189
1190 /*
1191 * structure for CRC 1 and CRC 2 reg in rxmac address map
1192 * located at address 0x4008
1193 */
1194 typedef union _RXMAC_WOL_CRC12_t {
1195 u32 value;
1196 struct {
1197 #ifdef _BIT_FIELDS_HTOL
1198 u32 crc2:16; // bits 16-31
1199 u32 crc1:16; // bits 0-15
1200 #else
1201 u32 crc1:16; // bits 0-15
1202 u32 crc2:16; // bits 16-31
1203 #endif
1204 } bits;
1205 } RXMAC_WOL_CRC12_t, *PRXMAC_WOL_CRC12_t;
1206
1207 /*
1208 * structure for CRC 3 and CRC 4 reg in rxmac address map
1209 * located at address 0x400C
1210 */
1211 typedef union _RXMAC_WOL_CRC34_t {
1212 u32 value;
1213 struct {
1214 #ifdef _BIT_FIELDS_HTOL
1215 u32 crc4:16; // bits 16-31
1216 u32 crc3:16; // bits 0-15
1217 #else
1218 u32 crc3:16; // bits 0-15
1219 u32 crc4:16; // bits 16-31
1220 #endif
1221 } bits;
1222 } RXMAC_WOL_CRC34_t, *PRXMAC_WOL_CRC34_t;
1223
1224 /*
1225 * structure for Wake On Lan Source Address Lo reg in rxmac address map
1226 * located at address 0x4010
1227 */
1228 typedef union _RXMAC_WOL_SA_LO_t {
1229 u32 value;
1230 struct {
1231 #ifdef _BIT_FIELDS_HTOL
1232 u32 sa3:8; // bits 24-31
1233 u32 sa4:8; // bits 16-23
1234 u32 sa5:8; // bits 8-15
1235 u32 sa6:8; // bits 0-7
1236 #else
1237 u32 sa6:8; // bits 0-7
1238 u32 sa5:8; // bits 8-15
1239 u32 sa4:8; // bits 16-23
1240 u32 sa3:8; // bits 24-31
1241 #endif
1242 } bits;
1243 } RXMAC_WOL_SA_LO_t, *PRXMAC_WOL_SA_LO_t;
1244
1245 /*
1246 * structure for Wake On Lan Source Address Hi reg in rxmac address map
1247 * located at address 0x4014
1248 */
1249 typedef union _RXMAC_WOL_SA_HI_t {
1250 u32 value;
1251 struct {
1252 #ifdef _BIT_FIELDS_HTOL
1253 u32 reserved:16; // bits 16-31
1254 u32 sa1:8; // bits 8-15
1255 u32 sa2:8; // bits 0-7
1256 #else
1257 u32 sa2:8; // bits 0-7
1258 u32 sa1:8; // bits 8-15
1259 u32 reserved:16; // bits 16-31
1260 #endif
1261 } bits;
1262 } RXMAC_WOL_SA_HI_t, *PRXMAC_WOL_SA_HI_t;
1263
1264 /*
1265 * structure for Wake On Lan mask reg in rxmac address map
1266 * located at address 0x4018 - 0x4064
1267 * Defined earlier (u32)
1268 */
1269
1270 /*
1271 * structure for Unicast Paket Filter Address 1 reg in rxmac address map
1272 * located at address 0x4068
1273 */
1274 typedef union _RXMAC_UNI_PF_ADDR1_t {
1275 u32 value;
1276 struct {
1277 #ifdef _BIT_FIELDS_HTOL
1278 u32 addr1_3:8; // bits 24-31
1279 u32 addr1_4:8; // bits 16-23
1280 u32 addr1_5:8; // bits 8-15
1281 u32 addr1_6:8; // bits 0-7
1282 #else
1283 u32 addr1_6:8; // bits 0-7
1284 u32 addr1_5:8; // bits 8-15
1285 u32 addr1_4:8; // bits 16-23
1286 u32 addr1_3:8; // bits 24-31
1287 #endif
1288 } bits;
1289 } RXMAC_UNI_PF_ADDR1_t, *PRXMAC_UNI_PF_ADDR1_t;
1290
1291 /*
1292 * structure for Unicast Paket Filter Address 2 reg in rxmac address map
1293 * located at address 0x406C
1294 */
1295 typedef union _RXMAC_UNI_PF_ADDR2_t {
1296 u32 value;
1297 struct {
1298 #ifdef _BIT_FIELDS_HTOL
1299 u32 addr2_3:8; // bits 24-31
1300 u32 addr2_4:8; // bits 16-23
1301 u32 addr2_5:8; // bits 8-15
1302 u32 addr2_6:8; // bits 0-7
1303 #else
1304 u32 addr2_6:8; // bits 0-7
1305 u32 addr2_5:8; // bits 8-15
1306 u32 addr2_4:8; // bits 16-23
1307 u32 addr2_3:8; // bits 24-31
1308 #endif
1309 } bits;
1310 } RXMAC_UNI_PF_ADDR2_t, *PRXMAC_UNI_PF_ADDR2_t;
1311
1312 /*
1313 * structure for Unicast Paket Filter Address 1 & 2 reg in rxmac address map
1314 * located at address 0x4070
1315 */
1316 typedef union _RXMAC_UNI_PF_ADDR3_t {
1317 u32 value;
1318 struct {
1319 #ifdef _BIT_FIELDS_HTOL
1320 u32 addr2_1:8; // bits 24-31
1321 u32 addr2_2:8; // bits 16-23
1322 u32 addr1_1:8; // bits 8-15
1323 u32 addr1_2:8; // bits 0-7
1324 #else
1325 u32 addr1_2:8; // bits 0-7
1326 u32 addr1_1:8; // bits 8-15
1327 u32 addr2_2:8; // bits 16-23
1328 u32 addr2_1:8; // bits 24-31
1329 #endif
1330 } bits;
1331 } RXMAC_UNI_PF_ADDR3_t, *PRXMAC_UNI_PF_ADDR3_t;
1332
1333 /*
1334 * structure for Multicast Hash reg in rxmac address map
1335 * located at address 0x4074 - 0x4080
1336 * Defined earlier (u32)
1337 */
1338
1339 /*
1340 * structure for Packet Filter Control reg in rxmac address map
1341 * located at address 0x4084
1342 */
1343 typedef union _RXMAC_PF_CTRL_t {
1344 u32 value;
1345 struct {
1346 #ifdef _BIT_FIELDS_HTOL
1347 u32 unused2:9; // bits 23-31
1348 u32 min_pkt_size:7; // bits 16-22
1349 u32 unused1:12; // bits 4-15
1350 u32 filter_frag_en:1; // bit 3
1351 u32 filter_uni_en:1; // bit 2
1352 u32 filter_multi_en:1; // bit 1
1353 u32 filter_broad_en:1; // bit 0
1354 #else
1355 u32 filter_broad_en:1; // bit 0
1356 u32 filter_multi_en:1; // bit 1
1357 u32 filter_uni_en:1; // bit 2
1358 u32 filter_frag_en:1; // bit 3
1359 u32 unused1:12; // bits 4-15
1360 u32 min_pkt_size:7; // bits 16-22
1361 u32 unused2:9; // bits 23-31
1362 #endif
1363 } bits;
1364 } RXMAC_PF_CTRL_t, *PRXMAC_PF_CTRL_t;
1365
1366 /*
1367 * structure for Memory Controller Interface Control Max Segment reg in rxmac
1368 * address map. Located at address 0x4088
1369 */
1370 typedef union _RXMAC_MCIF_CTRL_MAX_SEG_t {
1371 u32 value;
1372 struct {
1373 #ifdef _BIT_FIELDS_HTOL
1374 u32 reserved:22; // bits 10-31
1375 u32 max_size:8; // bits 2-9
1376 u32 fc_en:1; // bit 1
1377 u32 seg_en:1; // bit 0
1378 #else
1379 u32 seg_en:1; // bit 0
1380 u32 fc_en:1; // bit 1
1381 u32 max_size:8; // bits 2-9
1382 u32 reserved:22; // bits 10-31
1383 #endif
1384 } bits;
1385 } RXMAC_MCIF_CTRL_MAX_SEG_t, *PRXMAC_MCIF_CTRL_MAX_SEG_t;
1386
1387 /*
1388 * structure for Memory Controller Interface Water Mark reg in rxmac address
1389 * map. Located at address 0x408C
1390 */
1391 typedef union _RXMAC_MCIF_WATER_MARK_t {
1392 u32 value;
1393 struct {
1394 #ifdef _BIT_FIELDS_HTOL
1395 u32 reserved2:6; // bits 26-31
1396 u32 mark_hi:10; // bits 16-25
1397 u32 reserved1:6; // bits 10-15
1398 u32 mark_lo:10; // bits 0-9
1399 #else
1400 u32 mark_lo:10; // bits 0-9
1401 u32 reserved1:6; // bits 10-15
1402 u32 mark_hi:10; // bits 16-25
1403 u32 reserved2:6; // bits 26-31
1404 #endif
1405 } bits;
1406 } RXMAC_MCIF_WATER_MARK_t, *PRXMAC_MCIF_WATER_MARK_t;
1407
1408 /*
1409 * structure for Rx Queue Dialog reg in rxmac address map.
1410 * located at address 0x4090
1411 */
1412 typedef union _RXMAC_RXQ_DIAG_t {
1413 u32 value;
1414 struct {
1415 #ifdef _BIT_FIELDS_HTOL
1416 u32 reserved2:6; // bits 26-31
1417 u32 rd_ptr:10; // bits 16-25
1418 u32 reserved1:6; // bits 10-15
1419 u32 wr_ptr:10; // bits 0-9
1420 #else
1421 u32 wr_ptr:10; // bits 0-9
1422 u32 reserved1:6; // bits 10-15
1423 u32 rd_ptr:10; // bits 16-25
1424 u32 reserved2:6; // bits 26-31
1425 #endif
1426 } bits;
1427 } RXMAC_RXQ_DIAG_t, *PRXMAC_RXQ_DIAG_t;
1428
1429 /*
1430 * structure for space availiable reg in rxmac address map.
1431 * located at address 0x4094
1432 */
1433 typedef union _RXMAC_SPACE_AVAIL_t {
1434 u32 value;
1435 struct {
1436 #ifdef _BIT_FIELDS_HTOL
1437 u32 reserved2:15; // bits 17-31
1438 u32 space_avail_en:1; // bit 16
1439 u32 reserved1:6; // bits 10-15
1440 u32 space_avail:10; // bits 0-9
1441 #else
1442 u32 space_avail:10; // bits 0-9
1443 u32 reserved1:6; // bits 10-15
1444 u32 space_avail_en:1; // bit 16
1445 u32 reserved2:15; // bits 17-31
1446 #endif
1447 } bits;
1448 } RXMAC_SPACE_AVAIL_t, *PRXMAC_SPACE_AVAIL_t;
1449
1450 /*
1451 * structure for management interface reg in rxmac address map.
1452 * located at address 0x4098
1453 */
1454 typedef union _RXMAC_MIF_CTL_t {
1455 u32 value;
1456 struct {
1457 #ifdef _BIT_FIELDS_HTOL
1458 u32 reserve:14; // bits 18-31
1459 u32 drop_pkt_en:1; // bit 17
1460 u32 drop_pkt_mask:17; // bits 0-16
1461 #else
1462 u32 drop_pkt_mask:17; // bits 0-16
1463 u32 drop_pkt_en:1; // bit 17
1464 u32 reserve:14; // bits 18-31
1465 #endif
1466 } bits;
1467 } RXMAC_MIF_CTL_t, *PRXMAC_MIF_CTL_t;
1468
1469 /*
1470 * structure for Error reg in rxmac address map.
1471 * located at address 0x409C
1472 */
1473 typedef union _RXMAC_ERROR_REG_t {
1474 u32 value;
1475 struct {
1476 #ifdef _BIT_FIELDS_HTOL
1477 u32 reserve:28; // bits 4-31
1478 u32 mif:1; // bit 3
1479 u32 async:1; // bit 2
1480 u32 pkt_filter:1; // bit 1
1481 u32 mcif:1; // bit 0
1482 #else
1483 u32 mcif:1; // bit 0
1484 u32 pkt_filter:1; // bit 1
1485 u32 async:1; // bit 2
1486 u32 mif:1; // bit 3
1487 u32 reserve:28; // bits 4-31
1488 #endif
1489 } bits;
1490 } RXMAC_ERROR_REG_t, *PRXMAC_ERROR_REG_t;
1491
1492 /*
1493 * Rx MAC Module of JAGCore Address Mapping
1494 */
1495 typedef struct _RXMAC_t { // Location:
1496 RXMAC_CTRL_t ctrl; // 0x4000
1497 RXMAC_WOL_CTL_CRC0_t crc0; // 0x4004
1498 RXMAC_WOL_CRC12_t crc12; // 0x4008
1499 RXMAC_WOL_CRC34_t crc34; // 0x400C
1500 RXMAC_WOL_SA_LO_t sa_lo; // 0x4010
1501 RXMAC_WOL_SA_HI_t sa_hi; // 0x4014
1502 u32 mask0_word0; // 0x4018
1503 u32 mask0_word1; // 0x401C
1504 u32 mask0_word2; // 0x4020
1505 u32 mask0_word3; // 0x4024
1506 u32 mask1_word0; // 0x4028
1507 u32 mask1_word1; // 0x402C
1508 u32 mask1_word2; // 0x4030
1509 u32 mask1_word3; // 0x4034
1510 u32 mask2_word0; // 0x4038
1511 u32 mask2_word1; // 0x403C
1512 u32 mask2_word2; // 0x4040
1513 u32 mask2_word3; // 0x4044
1514 u32 mask3_word0; // 0x4048
1515 u32 mask3_word1; // 0x404C
1516 u32 mask3_word2; // 0x4050
1517 u32 mask3_word3; // 0x4054
1518 u32 mask4_word0; // 0x4058
1519 u32 mask4_word1; // 0x405C
1520 u32 mask4_word2; // 0x4060
1521 u32 mask4_word3; // 0x4064
1522 RXMAC_UNI_PF_ADDR1_t uni_pf_addr1; // 0x4068
1523 RXMAC_UNI_PF_ADDR2_t uni_pf_addr2; // 0x406C
1524 RXMAC_UNI_PF_ADDR3_t uni_pf_addr3; // 0x4070
1525 u32 multi_hash1; // 0x4074
1526 u32 multi_hash2; // 0x4078
1527 u32 multi_hash3; // 0x407C
1528 u32 multi_hash4; // 0x4080
1529 RXMAC_PF_CTRL_t pf_ctrl; // 0x4084
1530 RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg; // 0x4088
1531 RXMAC_MCIF_WATER_MARK_t mcif_water_mark; // 0x408C
1532 RXMAC_RXQ_DIAG_t rxq_diag; // 0x4090
1533 RXMAC_SPACE_AVAIL_t space_avail; // 0x4094
1534
1535 RXMAC_MIF_CTL_t mif_ctrl; // 0x4098
1536 RXMAC_ERROR_REG_t err_reg; // 0x409C
1537 } RXMAC_t, *PRXMAC_t;
1538
1539 /* END OF TXMAC REGISTER ADDRESS MAP */
1540
1541
1542 /* START OF MAC REGISTER ADDRESS MAP */
1543
1544 /*
1545 * structure for configuration #1 reg in mac address map.
1546 * located at address 0x5000
1547 */
1548 typedef union _MAC_CFG1_t {
1549 u32 value;
1550 struct {
1551 #ifdef _BIT_FIELDS_HTOL
1552 u32 soft_reset:1; // bit 31
1553 u32 sim_reset:1; // bit 30
1554 u32 reserved3:10; // bits 20-29
1555 u32 reset_rx_mc:1; // bit 19
1556 u32 reset_tx_mc:1; // bit 18
1557 u32 reset_rx_fun:1; // bit 17
1558 u32 reset_tx_fun:1; // bit 16
1559 u32 reserved2:7; // bits 9-15
1560 u32 loop_back:1; // bit 8
1561 u32 reserved1:2; // bits 6-7
1562 u32 rx_flow:1; // bit 5
1563 u32 tx_flow:1; // bit 4
1564 u32 syncd_rx_en:1; // bit 3
1565 u32 rx_enable:1; // bit 2
1566 u32 syncd_tx_en:1; // bit 1
1567 u32 tx_enable:1; // bit 0
1568 #else
1569 u32 tx_enable:1; // bit 0
1570 u32 syncd_tx_en:1; // bit 1
1571 u32 rx_enable:1; // bit 2
1572 u32 syncd_rx_en:1; // bit 3
1573 u32 tx_flow:1; // bit 4
1574 u32 rx_flow:1; // bit 5
1575 u32 reserved1:2; // bits 6-7
1576 u32 loop_back:1; // bit 8
1577 u32 reserved2:7; // bits 9-15
1578 u32 reset_tx_fun:1; // bit 16
1579 u32 reset_rx_fun:1; // bit 17
1580 u32 reset_tx_mc:1; // bit 18
1581 u32 reset_rx_mc:1; // bit 19
1582 u32 reserved3:10; // bits 20-29
1583 u32 sim_reset:1; // bit 30
1584 u32 soft_reset:1; // bit 31
1585 #endif
1586 } bits;
1587 } MAC_CFG1_t, *PMAC_CFG1_t;
1588
1589 /*
1590 * structure for configuration #2 reg in mac address map.
1591 * located at address 0x5004
1592 */
1593 typedef union _MAC_CFG2_t {
1594 u32 value;
1595 struct {
1596 #ifdef _BIT_FIELDS_HTOL
1597 u32 reserved3:16; // bits 16-31
1598 u32 preamble_len:4; // bits 12-15
1599 u32 reserved2:2; // bits 10-11
1600 u32 if_mode:2; // bits 8-9
1601 u32 reserved1:2; // bits 6-7
1602 u32 huge_frame:1; // bit 5
1603 u32 len_check:1; // bit 4
1604 u32 undefined:1; // bit 3
1605 u32 pad_crc:1; // bit 2
1606 u32 crc_enable:1; // bit 1
1607 u32 full_duplex:1; // bit 0
1608 #else
1609 u32 full_duplex:1; // bit 0
1610 u32 crc_enable:1; // bit 1
1611 u32 pad_crc:1; // bit 2
1612 u32 undefined:1; // bit 3
1613 u32 len_check:1; // bit 4
1614 u32 huge_frame:1; // bit 5
1615 u32 reserved1:2; // bits 6-7
1616 u32 if_mode:2; // bits 8-9
1617 u32 reserved2:2; // bits 10-11
1618 u32 preamble_len:4; // bits 12-15
1619 u32 reserved3:16; // bits 16-31
1620 #endif
1621 } bits;
1622 } MAC_CFG2_t, *PMAC_CFG2_t;
1623
1624 /*
1625 * structure for Interpacket gap reg in mac address map.
1626 * located at address 0x5008
1627 */
1628 typedef union _MAC_IPG_t {
1629 u32 value;
1630 struct {
1631 #ifdef _BIT_FIELDS_HTOL
1632 u32 reserved:1; // bit 31
1633 u32 non_B2B_ipg_1:7; // bits 24-30
1634 u32 undefined2:1; // bit 23
1635 u32 non_B2B_ipg_2:7; // bits 16-22
1636 u32 min_ifg_enforce:8; // bits 8-15
1637 u32 undefined1:1; // bit 7
1638 u32 B2B_ipg:7; // bits 0-6
1639 #else
1640 u32 B2B_ipg:7; // bits 0-6
1641 u32 undefined1:1; // bit 7
1642 u32 min_ifg_enforce:8; // bits 8-15
1643 u32 non_B2B_ipg_2:7; // bits 16-22
1644 u32 undefined2:1; // bit 23
1645 u32 non_B2B_ipg_1:7; // bits 24-30
1646 u32 reserved:1; // bit 31
1647 #endif
1648 } bits;
1649 } MAC_IPG_t, *PMAC_IPG_t;
1650
1651 /*
1652 * structure for half duplex reg in mac address map.
1653 * located at address 0x500C
1654 */
1655 typedef union _MAC_HFDP_t {
1656 u32 value;
1657 struct {
1658 #ifdef _BIT_FIELDS_HTOL
1659 u32 reserved2:8; // bits 24-31
1660 u32 alt_beb_trunc:4; // bits 23-20
1661 u32 alt_beb_enable:1; // bit 19
1662 u32 bp_no_backoff:1; // bit 18
1663 u32 no_backoff:1; // bit 17
1664 u32 excess_defer:1; // bit 16
1665 u32 rexmit_max:4; // bits 12-15
1666 u32 reserved1:2; // bits 10-11
1667 u32 coll_window:10; // bits 0-9
1668 #else
1669 u32 coll_window:10; // bits 0-9
1670 u32 reserved1:2; // bits 10-11
1671 u32 rexmit_max:4; // bits 12-15
1672 u32 excess_defer:1; // bit 16
1673 u32 no_backoff:1; // bit 17
1674 u32 bp_no_backoff:1; // bit 18
1675 u32 alt_beb_enable:1; // bit 19
1676 u32 alt_beb_trunc:4; // bits 23-20
1677 u32 reserved2:8; // bits 24-31
1678 #endif
1679 } bits;
1680 } MAC_HFDP_t, *PMAC_HFDP_t;
1681
1682 /*
1683 * structure for Maximum Frame Length reg in mac address map.
1684 * located at address 0x5010
1685 */
1686 typedef union _MAC_MAX_FM_LEN_t {
1687 u32 value;
1688 struct {
1689 #ifdef _BIT_FIELDS_HTOL
1690 u32 reserved:16; // bits 16-31
1691 u32 max_len:16; // bits 0-15
1692 #else
1693 u32 max_len:16; // bits 0-15
1694 u32 reserved:16; // bits 16-31
1695 #endif
1696 } bits;
1697 } MAC_MAX_FM_LEN_t, *PMAC_MAX_FM_LEN_t;
1698
1699 /*
1700 * structure for Reserve 1 reg in mac address map.
1701 * located at address 0x5014 - 0x5018
1702 * Defined earlier (u32)
1703 */
1704
1705 /*
1706 * structure for Test reg in mac address map.
1707 * located at address 0x501C
1708 */
1709 typedef union _MAC_TEST_t {
1710 u32 value;
1711 struct {
1712 #ifdef _BIT_FIELDS_HTOL
1713 u32 unused:29; // bits 3-31
1714 u32 mac_test:3; // bits 0-2
1715 #else
1716 u32 mac_test:3; // bits 0-2
1717 u32 unused:29; // bits 3-31
1718 #endif
1719 } bits;
1720 } MAC_TEST_t, *PMAC_TEST_t;
1721
1722 /*
1723 * structure for MII Management Configuration reg in mac address map.
1724 * located at address 0x5020
1725 */
1726 typedef union _MII_MGMT_CFG_t {
1727 u32 value;
1728 struct {
1729 #ifdef _BIT_FIELDS_HTOL
1730 u32 reset_mii_mgmt:1; // bit 31
1731 u32 reserved:25; // bits 6-30
1732 u32 scan_auto_incremt:1; // bit 5
1733 u32 preamble_suppress:1; // bit 4
1734 u32 undefined:1; // bit 3
1735 u32 mgmt_clk_reset:3; // bits 0-2
1736 #else
1737 u32 mgmt_clk_reset:3; // bits 0-2
1738 u32 undefined:1; // bit 3
1739 u32 preamble_suppress:1; // bit 4
1740 u32 scan_auto_incremt:1; // bit 5
1741 u32 reserved:25; // bits 6-30
1742 u32 reset_mii_mgmt:1; // bit 31
1743 #endif
1744 } bits;
1745 } MII_MGMT_CFG_t, *PMII_MGMT_CFG_t;
1746
1747 /*
1748 * structure for MII Management Command reg in mac address map.
1749 * located at address 0x5024
1750 */
1751 typedef union _MII_MGMT_CMD_t {
1752 u32 value;
1753 struct {
1754 #ifdef _BIT_FIELDS_HTOL
1755 u32 reserved:30; // bits 2-31
1756 u32 scan_cycle:1; // bit 1
1757 u32 read_cycle:1; // bit 0
1758 #else
1759 u32 read_cycle:1; // bit 0
1760 u32 scan_cycle:1; // bit 1
1761 u32 reserved:30; // bits 2-31
1762 #endif
1763 } bits;
1764 } MII_MGMT_CMD_t, *PMII_MGMT_CMD_t;
1765
1766 /*
1767 * structure for MII Management Address reg in mac address map.
1768 * located at address 0x5028
1769 */
1770 typedef union _MII_MGMT_ADDR_t {
1771 u32 value;
1772 struct {
1773 #ifdef _BIT_FIELDS_HTOL
1774 u32 reserved2:19; // bit 13-31
1775 u32 phy_addr:5; // bits 8-12
1776 u32 reserved1:3; // bits 5-7
1777 u32 reg_addr:5; // bits 0-4
1778 #else
1779 u32 reg_addr:5; // bits 0-4
1780 u32 reserved1:3; // bits 5-7
1781 u32 phy_addr:5; // bits 8-12
1782 u32 reserved2:19; // bit 13-31
1783 #endif
1784 } bits;
1785 } MII_MGMT_ADDR_t, *PMII_MGMT_ADDR_t;
1786
1787 /*
1788 * structure for MII Management Control reg in mac address map.
1789 * located at address 0x502C
1790 */
1791 typedef union _MII_MGMT_CTRL_t {
1792 u32 value;
1793 struct {
1794 #ifdef _BIT_FIELDS_HTOL
1795 u32 reserved:16; // bits 16-31
1796 u32 phy_ctrl:16; // bits 0-15
1797 #else
1798 u32 phy_ctrl:16; // bits 0-15
1799 u32 reserved:16; // bits 16-31
1800 #endif
1801 } bits;
1802 } MII_MGMT_CTRL_t, *PMII_MGMT_CTRL_t;
1803
1804 /*
1805 * structure for MII Management Status reg in mac address map.
1806 * located at address 0x5030
1807 */
1808 typedef union _MII_MGMT_STAT_t {
1809 u32 value;
1810 struct {
1811 #ifdef _BIT_FIELDS_HTOL
1812 u32 reserved:16; // bits 16-31
1813 u32 phy_stat:16; // bits 0-15
1814 #else
1815 u32 phy_stat:16; // bits 0-15
1816 u32 reserved:16; // bits 16-31
1817 #endif
1818 } bits;
1819 } MII_MGMT_STAT_t, *PMII_MGMT_STAT_t;
1820
1821 /*
1822 * structure for MII Management Indicators reg in mac address map.
1823 * located at address 0x5034
1824 */
1825 typedef union _MII_MGMT_INDICATOR_t {
1826 u32 value;
1827 struct {
1828 #ifdef _BIT_FIELDS_HTOL
1829 u32 reserved:29; // bits 3-31
1830 u32 not_valid:1; // bit 2
1831 u32 scanning:1; // bit 1
1832 u32 busy:1; // bit 0
1833 #else
1834 u32 busy:1; // bit 0
1835 u32 scanning:1; // bit 1
1836 u32 not_valid:1; // bit 2
1837 u32 reserved:29; // bits 3-31
1838 #endif
1839 } bits;
1840 } MII_MGMT_INDICATOR_t, *PMII_MGMT_INDICATOR_t;
1841
1842 /*
1843 * structure for Interface Control reg in mac address map.
1844 * located at address 0x5038
1845 */
1846 typedef union _MAC_IF_CTRL_t {
1847 u32 value;
1848 struct {
1849 #ifdef _BIT_FIELDS_HTOL
1850 u32 reset_if_module:1; // bit 31
1851 u32 reserved4:3; // bit 28-30
1852 u32 tbi_mode:1; // bit 27
1853 u32 ghd_mode:1; // bit 26
1854 u32 lhd_mode:1; // bit 25
1855 u32 phy_mode:1; // bit 24
1856 u32 reset_per_mii:1; // bit 23
1857 u32 reserved3:6; // bits 17-22
1858 u32 speed:1; // bit 16
1859 u32 reset_pe100x:1; // bit 15
1860 u32 reserved2:4; // bits 11-14
1861 u32 force_quiet:1; // bit 10
1862 u32 no_cipher:1; // bit 9
1863 u32 disable_link_fail:1; // bit 8
1864 u32 reset_gpsi:1; // bit 7
1865 u32 reserved1:6; // bits 1-6
1866 u32 enab_jab_protect:1; // bit 0
1867 #else
1868 u32 enab_jab_protect:1; // bit 0
1869 u32 reserved1:6; // bits 1-6
1870 u32 reset_gpsi:1; // bit 7
1871 u32 disable_link_fail:1; // bit 8
1872 u32 no_cipher:1; // bit 9
1873 u32 force_quiet:1; // bit 10
1874 u32 reserved2:4; // bits 11-14
1875 u32 reset_pe100x:1; // bit 15
1876 u32 speed:1; // bit 16
1877 u32 reserved3:6; // bits 17-22
1878 u32 reset_per_mii:1; // bit 23
1879 u32 phy_mode:1; // bit 24
1880 u32 lhd_mode:1; // bit 25
1881 u32 ghd_mode:1; // bit 26
1882 u32 tbi_mode:1; // bit 27
1883 u32 reserved4:3; // bit 28-30
1884 u32 reset_if_module:1; // bit 31
1885 #endif
1886 } bits;
1887 } MAC_IF_CTRL_t, *PMAC_IF_CTRL_t;
1888
1889 /*
1890 * structure for Interface Status reg in mac address map.
1891 * located at address 0x503C
1892 */
1893 typedef union _MAC_IF_STAT_t {
1894 u32 value;
1895 struct {
1896 #ifdef _BIT_FIELDS_HTOL
1897 u32 reserved:22; // bits 10-31
1898 u32 excess_defer:1; // bit 9
1899 u32 clash:1; // bit 8
1900 u32 phy_jabber:1; // bit 7
1901 u32 phy_link_ok:1; // bit 6
1902 u32 phy_full_duplex:1; // bit 5
1903 u32 phy_speed:1; // bit 4
1904 u32 pe100x_link_fail:1; // bit 3
1905 u32 pe10t_loss_carrie:1; // bit 2
1906 u32 pe10t_sqe_error:1; // bit 1
1907 u32 pe10t_jabber:1; // bit 0
1908 #else
1909 u32 pe10t_jabber:1; // bit 0
1910 u32 pe10t_sqe_error:1; // bit 1
1911 u32 pe10t_loss_carrie:1; // bit 2
1912 u32 pe100x_link_fail:1; // bit 3
1913 u32 phy_speed:1; // bit 4
1914 u32 phy_full_duplex:1; // bit 5
1915 u32 phy_link_ok:1; // bit 6
1916 u32 phy_jabber:1; // bit 7
1917 u32 clash:1; // bit 8
1918 u32 excess_defer:1; // bit 9
1919 u32 reserved:22; // bits 10-31
1920 #endif
1921 } bits;
1922 } MAC_IF_STAT_t, *PMAC_IF_STAT_t;
1923
1924 /*
1925 * structure for Mac Station Address, Part 1 reg in mac address map.
1926 * located at address 0x5040
1927 */
1928 typedef union _MAC_STATION_ADDR1_t {
1929 u32 value;
1930 struct {
1931 #ifdef _BIT_FIELDS_HTOL
1932 u32 Octet6:8; // bits 24-31
1933 u32 Octet5:8; // bits 16-23
1934 u32 Octet4:8; // bits 8-15
1935 u32 Octet3:8; // bits 0-7
1936 #else
1937 u32 Octet3:8; // bits 0-7
1938 u32 Octet4:8; // bits 8-15
1939 u32 Octet5:8; // bits 16-23
1940 u32 Octet6:8; // bits 24-31
1941 #endif
1942 } bits;
1943 } MAC_STATION_ADDR1_t, *PMAC_STATION_ADDR1_t;
1944
1945 /*
1946 * structure for Mac Station Address, Part 2 reg in mac address map.
1947 * located at address 0x5044
1948 */
1949 typedef union _MAC_STATION_ADDR2_t {
1950 u32 value;
1951 struct {
1952 #ifdef _BIT_FIELDS_HTOL
1953 u32 Octet2:8; // bits 24-31
1954 u32 Octet1:8; // bits 16-23
1955 u32 reserved:16; // bits 0-15
1956 #else
1957 u32 reserved:16; // bit 0-15
1958 u32 Octet1:8; // bits 16-23
1959 u32 Octet2:8; // bits 24-31
1960 #endif
1961 } bits;
1962 } MAC_STATION_ADDR2_t, *PMAC_STATION_ADDR2_t;
1963
1964 /*
1965 * MAC Module of JAGCore Address Mapping
1966 */
1967 typedef struct _MAC_t { // Location:
1968 MAC_CFG1_t cfg1; // 0x5000
1969 MAC_CFG2_t cfg2; // 0x5004
1970 MAC_IPG_t ipg; // 0x5008
1971 MAC_HFDP_t hfdp; // 0x500C
1972 MAC_MAX_FM_LEN_t max_fm_len; // 0x5010
1973 u32 rsv1; // 0x5014
1974 u32 rsv2; // 0x5018
1975 MAC_TEST_t mac_test; // 0x501C
1976 MII_MGMT_CFG_t mii_mgmt_cfg; // 0x5020
1977 MII_MGMT_CMD_t mii_mgmt_cmd; // 0x5024
1978 MII_MGMT_ADDR_t mii_mgmt_addr; // 0x5028
1979 MII_MGMT_CTRL_t mii_mgmt_ctrl; // 0x502C
1980 MII_MGMT_STAT_t mii_mgmt_stat; // 0x5030
1981 MII_MGMT_INDICATOR_t mii_mgmt_indicator; // 0x5034
1982 MAC_IF_CTRL_t if_ctrl; // 0x5038
1983 MAC_IF_STAT_t if_stat; // 0x503C
1984 MAC_STATION_ADDR1_t station_addr_1; // 0x5040
1985 MAC_STATION_ADDR2_t station_addr_2; // 0x5044
1986 } MAC_t, *PMAC_t;
1987
1988 /* END OF MAC REGISTER ADDRESS MAP */
1989
1990 /* START OF MAC STAT REGISTER ADDRESS MAP */
1991
1992 /*
1993 * structure for Carry Register One and it's Mask Register reg located in mac
1994 * stat address map address 0x6130 and 0x6138.
1995 */
1996 typedef union _MAC_STAT_REG_1_t {
1997 u32 value;
1998 struct {
1999 #ifdef _BIT_FIELDS_HTOL
2000 u32 tr64:1; // bit 31
2001 u32 tr127:1; // bit 30
2002 u32 tr255:1; // bit 29
2003 u32 tr511:1; // bit 28
2004 u32 tr1k:1; // bit 27
2005 u32 trmax:1; // bit 26
2006 u32 trmgv:1; // bit 25
2007 u32 unused:8; // bits 17-24
2008 u32 rbyt:1; // bit 16
2009 u32 rpkt:1; // bit 15
2010 u32 rfcs:1; // bit 14
2011 u32 rmca:1; // bit 13
2012 u32 rbca:1; // bit 12
2013 u32 rxcf:1; // bit 11
2014 u32 rxpf:1; // bit 10
2015 u32 rxuo:1; // bit 9
2016 u32 raln:1; // bit 8
2017 u32 rflr:1; // bit 7
2018 u32 rcde:1; // bit 6
2019 u32 rcse:1; // bit 5
2020 u32 rund:1; // bit 4
2021 u32 rovr:1; // bit 3
2022 u32 rfrg:1; // bit 2
2023 u32 rjbr:1; // bit 1
2024 u32 rdrp:1; // bit 0
2025 #else
2026 u32 rdrp:1; // bit 0
2027 u32 rjbr:1; // bit 1
2028 u32 rfrg:1; // bit 2
2029 u32 rovr:1; // bit 3
2030 u32 rund:1; // bit 4
2031 u32 rcse:1; // bit 5
2032 u32 rcde:1; // bit 6
2033 u32 rflr:1; // bit 7
2034 u32 raln:1; // bit 8
2035 u32 rxuo:1; // bit 9
2036 u32 rxpf:1; // bit 10
2037 u32 rxcf:1; // bit 11
2038 u32 rbca:1; // bit 12
2039 u32 rmca:1; // bit 13
2040 u32 rfcs:1; // bit 14
2041 u32 rpkt:1; // bit 15
2042 u32 rbyt:1; // bit 16
2043 u32 unused:8; // bits 17-24
2044 u32 trmgv:1; // bit 25
2045 u32 trmax:1; // bit 26
2046 u32 tr1k:1; // bit 27
2047 u32 tr511:1; // bit 28
2048 u32 tr255:1; // bit 29
2049 u32 tr127:1; // bit 30
2050 u32 tr64:1; // bit 31
2051 #endif
2052 } bits;
2053 } MAC_STAT_REG_1_t, *PMAC_STAT_REG_1_t;
2054
2055 /*
2056 * structure for Carry Register Two Mask Register reg in mac stat address map.
2057 * located at address 0x613C
2058 */
2059 typedef union _MAC_STAT_REG_2_t {
2060 u32 value;
2061 struct {
2062 #ifdef _BIT_FIELDS_HTOL
2063 u32 unused:12; // bit 20-31
2064 u32 tjbr:1; // bit 19
2065 u32 tfcs:1; // bit 18
2066 u32 txcf:1; // bit 17
2067 u32 tovr:1; // bit 16
2068 u32 tund:1; // bit 15
2069 u32 tfrg:1; // bit 14
2070 u32 tbyt:1; // bit 13
2071 u32 tpkt:1; // bit 12
2072 u32 tmca:1; // bit 11
2073 u32 tbca:1; // bit 10
2074 u32 txpf:1; // bit 9
2075 u32 tdfr:1; // bit 8
2076 u32 tedf:1; // bit 7
2077 u32 tscl:1; // bit 6
2078 u32 tmcl:1; // bit 5
2079 u32 tlcl:1; // bit 4
2080 u32 txcl:1; // bit 3
2081 u32 tncl:1; // bit 2
2082 u32 tpfh:1; // bit 1
2083 u32 tdrp:1; // bit 0
2084 #else
2085 u32 tdrp:1; // bit 0
2086 u32 tpfh:1; // bit 1
2087 u32 tncl:1; // bit 2
2088 u32 txcl:1; // bit 3
2089 u32 tlcl:1; // bit 4
2090 u32 tmcl:1; // bit 5
2091 u32 tscl:1; // bit 6
2092 u32 tedf:1; // bit 7
2093 u32 tdfr:1; // bit 8
2094 u32 txpf:1; // bit 9
2095 u32 tbca:1; // bit 10
2096 u32 tmca:1; // bit 11
2097 u32 tpkt:1; // bit 12
2098 u32 tbyt:1; // bit 13
2099 u32 tfrg:1; // bit 14
2100 u32 tund:1; // bit 15
2101 u32 tovr:1; // bit 16
2102 u32 txcf:1; // bit 17
2103 u32 tfcs:1; // bit 18
2104 u32 tjbr:1; // bit 19
2105 u32 unused:12; // bit 20-31
2106 #endif
2107 } bits;
2108 } MAC_STAT_REG_2_t, *PMAC_STAT_REG_2_t;
2109
2110 /*
2111 * MAC STATS Module of JAGCore Address Mapping
2112 */
2113 typedef struct _MAC_STAT_t { // Location:
2114 u32 pad[32]; // 0x6000 - 607C
2115
2116 // Tx/Rx 0-64 Byte Frame Counter
2117 u32 TR64; // 0x6080
2118
2119 // Tx/Rx 65-127 Byte Frame Counter
2120 u32 TR127; // 0x6084
2121
2122 // Tx/Rx 128-255 Byte Frame Counter
2123 u32 TR255; // 0x6088
2124
2125 // Tx/Rx 256-511 Byte Frame Counter
2126 u32 TR511; // 0x608C
2127
2128 // Tx/Rx 512-1023 Byte Frame Counter
2129 u32 TR1K; // 0x6090
2130
2131 // Tx/Rx 1024-1518 Byte Frame Counter
2132 u32 TRMax; // 0x6094
2133
2134 // Tx/Rx 1519-1522 Byte Good VLAN Frame Count
2135 u32 TRMgv; // 0x6098
2136
2137 // Rx Byte Counter
2138 u32 RByt; // 0x609C
2139
2140 // Rx Packet Counter
2141 u32 RPkt; // 0x60A0
2142
2143 // Rx FCS Error Counter
2144 u32 RFcs; // 0x60A4
2145
2146 // Rx Multicast Packet Counter
2147 u32 RMca; // 0x60A8
2148
2149 // Rx Broadcast Packet Counter
2150 u32 RBca; // 0x60AC
2151
2152 // Rx Control Frame Packet Counter
2153 u32 RxCf; // 0x60B0
2154
2155 // Rx Pause Frame Packet Counter
2156 u32 RxPf; // 0x60B4
2157
2158 // Rx Unknown OP Code Counter
2159 u32 RxUo; // 0x60B8
2160
2161 // Rx Alignment Error Counter
2162 u32 RAln; // 0x60BC
2163
2164 // Rx Frame Length Error Counter
2165 u32 RFlr; // 0x60C0
2166
2167 // Rx Code Error Counter
2168 u32 RCde; // 0x60C4
2169
2170 // Rx Carrier Sense Error Counter
2171 u32 RCse; // 0x60C8
2172
2173 // Rx Undersize Packet Counter
2174 u32 RUnd; // 0x60CC
2175
2176 // Rx Oversize Packet Counter
2177 u32 ROvr; // 0x60D0
2178
2179 // Rx Fragment Counter
2180 u32 RFrg; // 0x60D4
2181
2182 // Rx Jabber Counter
2183 u32 RJbr; // 0x60D8
2184
2185 // Rx Drop
2186 u32 RDrp; // 0x60DC
2187
2188 // Tx Byte Counter
2189 u32 TByt; // 0x60E0
2190
2191 // Tx Packet Counter
2192 u32 TPkt; // 0x60E4
2193
2194 // Tx Multicast Packet Counter
2195 u32 TMca; // 0x60E8
2196
2197 // Tx Broadcast Packet Counter
2198 u32 TBca; // 0x60EC
2199
2200 // Tx Pause Control Frame Counter
2201 u32 TxPf; // 0x60F0
2202
2203 // Tx Deferral Packet Counter
2204 u32 TDfr; // 0x60F4
2205
2206 // Tx Excessive Deferral Packet Counter
2207 u32 TEdf; // 0x60F8
2208
2209 // Tx Single Collision Packet Counter
2210 u32 TScl; // 0x60FC
2211
2212 // Tx Multiple Collision Packet Counter
2213 u32 TMcl; // 0x6100
2214
2215 // Tx Late Collision Packet Counter
2216 u32 TLcl; // 0x6104
2217
2218 // Tx Excessive Collision Packet Counter
2219 u32 TXcl; // 0x6108
2220
2221 // Tx Total Collision Packet Counter
2222 u32 TNcl; // 0x610C
2223
2224 // Tx Pause Frame Honored Counter
2225 u32 TPfh; // 0x6110
2226
2227 // Tx Drop Frame Counter
2228 u32 TDrp; // 0x6114
2229
2230 // Tx Jabber Frame Counter
2231 u32 TJbr; // 0x6118
2232
2233 // Tx FCS Error Counter
2234 u32 TFcs; // 0x611C
2235
2236 // Tx Control Frame Counter
2237 u32 TxCf; // 0x6120
2238
2239 // Tx Oversize Frame Counter
2240 u32 TOvr; // 0x6124
2241
2242 // Tx Undersize Frame Counter
2243 u32 TUnd; // 0x6128
2244
2245 // Tx Fragments Frame Counter
2246 u32 TFrg; // 0x612C
2247
2248 // Carry Register One Register
2249 MAC_STAT_REG_1_t Carry1; // 0x6130
2250
2251 // Carry Register Two Register
2252 MAC_STAT_REG_2_t Carry2; // 0x6134
2253
2254 // Carry Register One Mask Register
2255 MAC_STAT_REG_1_t Carry1M; // 0x6138
2256
2257 // Carry Register Two Mask Register
2258 MAC_STAT_REG_2_t Carry2M; // 0x613C
2259 } MAC_STAT_t, *PMAC_STAT_t;
2260
2261 /* END OF MAC STAT REGISTER ADDRESS MAP */
2262
2263
2264 /* START OF MMC REGISTER ADDRESS MAP */
2265
2266 /*
2267 * structure for Main Memory Controller Control reg in mmc address map.
2268 * located at address 0x7000
2269 */
2270 typedef union _MMC_CTRL_t {
2271 u32 value;
2272 struct {
2273 #ifdef _BIT_FIELDS_HTOL
2274 u32 reserved:25; // bits 7-31
2275 u32 force_ce:1; // bit 6
2276 u32 rxdma_disable:1; // bit 5
2277 u32 txdma_disable:1; // bit 4
2278 u32 txmac_disable:1; // bit 3
2279 u32 rxmac_disable:1; // bit 2
2280 u32 arb_disable:1; // bit 1
2281 u32 mmc_enable:1; // bit 0
2282 #else
2283 u32 mmc_enable:1; // bit 0
2284 u32 arb_disable:1; // bit 1
2285 u32 rxmac_disable:1; // bit 2
2286 u32 txmac_disable:1; // bit 3
2287 u32 txdma_disable:1; // bit 4
2288 u32 rxdma_disable:1; // bit 5
2289 u32 force_ce:1; // bit 6
2290 u32 reserved:25; // bits 7-31
2291 #endif
2292 } bits;
2293 } MMC_CTRL_t, *PMMC_CTRL_t;
2294
2295 /*
2296 * structure for Main Memory Controller Host Memory Access Address reg in mmc
2297 * address map. Located at address 0x7004
2298 */
2299 typedef union _MMC_SRAM_ACCESS_t {
2300 u32 value;
2301 struct {
2302 #ifdef _BIT_FIELDS_HTOL
2303 u32 byte_enable:16; // bits 16-31
2304 u32 reserved2:2; // bits 14-15
2305 u32 req_addr:10; // bits 4-13
2306 u32 reserved1:1; // bit 3
2307 u32 is_ctrl_word:1; // bit 2
2308 u32 wr_access:1; // bit 1
2309 u32 req_access:1; // bit 0
2310 #else
2311 u32 req_access:1; // bit 0
2312 u32 wr_access:1; // bit 1
2313 u32 is_ctrl_word:1; // bit 2
2314 u32 reserved1:1; // bit 3
2315 u32 req_addr:10; // bits 4-13
2316 u32 reserved2:2; // bits 14-15
2317 u32 byte_enable:16; // bits 16-31
2318 #endif
2319 } bits;
2320 } MMC_SRAM_ACCESS_t, *PMMC_SRAM_ACCESS_t;
2321
2322 /*
2323 * structure for Main Memory Controller Host Memory Access Data reg in mmc
2324 * address map. Located at address 0x7008 - 0x7014
2325 * Defined earlier (u32)
2326 */
2327
2328 /*
2329 * Memory Control Module of JAGCore Address Mapping
2330 */
2331 typedef struct _MMC_t { // Location:
2332 MMC_CTRL_t mmc_ctrl; // 0x7000
2333 MMC_SRAM_ACCESS_t sram_access; // 0x7004
2334 u32 sram_word1; // 0x7008
2335 u32 sram_word2; // 0x700C
2336 u32 sram_word3; // 0x7010
2337 u32 sram_word4; // 0x7014
2338 } MMC_t, *PMMC_t;
2339
2340 /* END OF MMC REGISTER ADDRESS MAP */
2341
2342
2343 /* START OF EXP ROM REGISTER ADDRESS MAP */
2344
2345 /*
2346 * Expansion ROM Module of JAGCore Address Mapping
2347 */
2348
2349 /* Take this out until it is not empty */
2350 #if 0
2351 typedef struct _EXP_ROM_t {
2352
2353 } EXP_ROM_t, *PEXP_ROM_t;
2354 #endif
2355
2356 /* END OF EXP ROM REGISTER ADDRESS MAP */
2357
2358
2359 /*
2360 * JAGCore Address Mapping
2361 */
2362 typedef struct _ADDRESS_MAP_t {
2363 GLOBAL_t global;
2364 // unused section of global address map
2365 u8 unused_global[4096 - sizeof(GLOBAL_t)];
2366 TXDMA_t txdma;
2367 // unused section of txdma address map
2368 u8 unused_txdma[4096 - sizeof(TXDMA_t)];
2369 RXDMA_t rxdma;
2370 // unused section of rxdma address map
2371 u8 unused_rxdma[4096 - sizeof(RXDMA_t)];
2372 TXMAC_t txmac;
2373 // unused section of txmac address map
2374 u8 unused_txmac[4096 - sizeof(TXMAC_t)];
2375 RXMAC_t rxmac;
2376 // unused section of rxmac address map
2377 u8 unused_rxmac[4096 - sizeof(RXMAC_t)];
2378 MAC_t mac;
2379 // unused section of mac address map
2380 u8 unused_mac[4096 - sizeof(MAC_t)];
2381 MAC_STAT_t macStat;
2382 // unused section of mac stat address map
2383 u8 unused_mac_stat[4096 - sizeof(MAC_STAT_t)];
2384 MMC_t mmc;
2385 // unused section of mmc address map
2386 u8 unused_mmc[4096 - sizeof(MMC_t)];
2387 // unused section of address map
2388 u8 unused_[1015808];
2389
2390 /* Take this out until it is not empty */
2391 #if 0
2392 EXP_ROM_t exp_rom;
2393 #endif
2394
2395 u8 unused_exp_rom[4096]; // MGS-size TBD
2396 u8 unused__[524288]; // unused section of address map
2397 } ADDRESS_MAP_t, *PADDRESS_MAP_t;
2398
2399 #endif /* _ET1310_ADDRESS_MAP_H_ */
Peter's tree of IPFire 2.x