Add ET131x ethernet driver.
[people/pmueller/ipfire-2.x.git] / src / et131x / et1310_jagcore.c
1 /*
2 * Agere Systems Inc.
3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
4 *
5 * Copyright © 2005 Agere Systems Inc.
6 * All rights reserved.
7 * http://www.agere.com
8 *
9 *------------------------------------------------------------------------------
10 *
11 * et1310_jagcore.c - All code pertaining to the ET1301/ET131x's JAGcore
12 *
13 *------------------------------------------------------------------------------
14 *
15 * SOFTWARE LICENSE
16 *
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
21 *
22 * Copyright © 2005 Agere Systems Inc.
23 * All rights reserved.
24 *
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
27 *
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
31 * distribution.
32 *
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
36 *
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
40 *
41 * Disclaimer
42 *
43 * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
47 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
48 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
49 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
51 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
54 * DAMAGE.
55 *
56 */
57
58 #include "et131x_version.h"
59 #include "et131x_debug.h"
60 #include "et131x_defs.h"
61
62 #include <linux/init.h>
63 #include <linux/module.h>
64 #include <linux/types.h>
65 #include <linux/kernel.h>
66
67 #include <linux/sched.h>
68 #include <linux/ptrace.h>
69 #include <linux/slab.h>
70 #include <linux/ctype.h>
71 #include <linux/string.h>
72 #include <linux/timer.h>
73 #include <linux/interrupt.h>
74 #include <linux/in.h>
75 #include <linux/delay.h>
76 #include <asm/io.h>
77 #include <asm/system.h>
78 #include <asm/bitops.h>
79
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/skbuff.h>
83 #include <linux/if_arp.h>
84 #include <linux/ioport.h>
85
86 #include "et1310_phy.h"
87 #include "et1310_pm.h"
88 #include "et1310_jagcore.h"
89
90 #include "et131x_adapter.h"
91 #include "et131x_initpci.h"
92
93 /* Data for debugging facilities */
94 #ifdef CONFIG_ET131X_DEBUG
95 extern dbg_info_t *et131x_dbginfo;
96 #endif /* CONFIG_ET131X_DEBUG */
97
98 /**
99 * ConfigGlobalRegs - Used to configure the global registers on the JAGCore
100 * @pAdpater: pointer to our adapter structure
101 */
102 void ConfigGlobalRegs(struct et131x_adapter *pAdapter)
103 {
104 struct _GLOBAL_t __iomem *pGbl = &pAdapter->CSRAddress->global;
105
106 DBG_ENTER(et131x_dbginfo);
107
108 if (pAdapter->RegistryPhyLoopbk == false) {
109 if (pAdapter->RegistryJumboPacket < 2048) {
110 /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
111 * block of RAM that the driver can split between Tx
112 * and Rx as it desires. Our default is to split it
113 * 50/50:
114 */
115 writel(0, &pGbl->rxq_start_addr.value);
116 writel(pAdapter->RegistryRxMemEnd,
117 &pGbl->rxq_end_addr.value);
118 writel(pAdapter->RegistryRxMemEnd + 1,
119 &pGbl->txq_start_addr.value);
120 writel(INTERNAL_MEM_SIZE - 1,
121 &pGbl->txq_end_addr.value);
122 } else if (pAdapter->RegistryJumboPacket < 8192) {
123 /* For jumbo packets > 2k but < 8k, split 50-50. */
124 writel(0, &pGbl->rxq_start_addr.value);
125 writel(INTERNAL_MEM_RX_OFFSET,
126 &pGbl->rxq_end_addr.value);
127 writel(INTERNAL_MEM_RX_OFFSET + 1,
128 &pGbl->txq_start_addr.value);
129 writel(INTERNAL_MEM_SIZE - 1,
130 &pGbl->txq_end_addr.value);
131 } else {
132 /* 9216 is the only packet size greater than 8k that
133 * is available. The Tx buffer has to be big enough
134 * for one whole packet on the Tx side. We'll make
135 * the Tx 9408, and give the rest to Rx
136 */
137 writel(0x0000, &pGbl->rxq_start_addr.value);
138 writel(0x01b3, &pGbl->rxq_end_addr.value);
139 writel(0x01b4, &pGbl->txq_start_addr.value);
140 writel(INTERNAL_MEM_SIZE - 1,
141 &pGbl->txq_end_addr.value);
142 }
143
144 /* Initialize the loopback register. Disable all loopbacks. */
145 writel(0, &pGbl->loopback.value);
146 } else {
147 /* For PHY Line loopback, the memory is configured as if Tx
148 * and Rx both have all the memory. This is because the
149 * RxMAC will write data into the space, and the TxMAC will
150 * read it out.
151 */
152 writel(0, &pGbl->rxq_start_addr.value);
153 writel(INTERNAL_MEM_SIZE - 1, &pGbl->rxq_end_addr.value);
154 writel(0, &pGbl->txq_start_addr.value);
155 writel(INTERNAL_MEM_SIZE - 1, &pGbl->txq_end_addr.value);
156
157 /* Initialize the loopback register (MAC loopback). */
158 writel(1, &pGbl->loopback.value);
159 }
160
161 /* MSI Register */
162 writel(0, &pGbl->msi_config.value);
163
164 /* By default, disable the watchdog timer. It will be enabled when
165 * a packet is queued.
166 */
167 writel(0, &pGbl->watchdog_timer);
168
169 DBG_LEAVE(et131x_dbginfo);
170 }
171
172 /**
173 * ConfigMMCRegs - Used to configure the main memory registers in the JAGCore
174 * @pAdapter: pointer to our adapter structure
175 */
176 void ConfigMMCRegs(struct et131x_adapter *pAdapter)
177 {
178 MMC_CTRL_t mmc_ctrl = { 0 };
179
180 DBG_ENTER(et131x_dbginfo);
181
182 /* All we need to do is initialize the Memory Control Register */
183 mmc_ctrl.bits.force_ce = 0x0;
184 mmc_ctrl.bits.rxdma_disable = 0x0;
185 mmc_ctrl.bits.txdma_disable = 0x0;
186 mmc_ctrl.bits.txmac_disable = 0x0;
187 mmc_ctrl.bits.rxmac_disable = 0x0;
188 mmc_ctrl.bits.arb_disable = 0x0;
189 mmc_ctrl.bits.mmc_enable = 0x1;
190
191 writel(mmc_ctrl.value, &pAdapter->CSRAddress->mmc.mmc_ctrl.value);
192
193 DBG_LEAVE(et131x_dbginfo);
194 }
195
196 void et131x_enable_interrupts(struct et131x_adapter *adapter)
197 {
198 uint32_t MaskValue;
199
200 /* Enable all global interrupts */
201 if ((adapter->FlowControl == TxOnly) || (adapter->FlowControl == Both)) {
202 MaskValue = INT_MASK_ENABLE;
203 } else {
204 MaskValue = INT_MASK_ENABLE_NO_FLOW;
205 }
206
207 if (adapter->DriverNoPhyAccess) {
208 MaskValue |= 0x10000;
209 }
210
211 adapter->CachedMaskValue.value = MaskValue;
212 writel(MaskValue, &adapter->CSRAddress->global.int_mask.value);
213 }
214
215 void et131x_disable_interrupts(struct et131x_adapter * adapter)
216 {
217 /* Disable all global interrupts */
218 adapter->CachedMaskValue.value = INT_MASK_DISABLE;
219 writel(INT_MASK_DISABLE, &adapter->CSRAddress->global.int_mask.value);
220 }