src/et131x/et1310_jagcore.h

   1 /*
   2  * Agere Systems Inc.
   3  * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
   4  *
   5  * Copyright © 2005 Agere Systems Inc.
   6  * All rights reserved.
   7  *   http://www.agere.com
   8  *
   9  *------------------------------------------------------------------------------
  10  *
  11  * et1310_jagcore.h - Defines, structs, enums, prototypes, etc. pertaining to
  12  *                    the JAGCore
  13  *
  14  *------------------------------------------------------------------------------
  15  *
  16  * SOFTWARE LICENSE
  17  *
  18  * This software is provided subject to the following terms and conditions,
  19  * which you should read carefully before using the software.  Using this
  20  * software indicates your acceptance of these terms and conditions.  If you do
  21  * not agree with these terms and conditions, do not use the software.
  22  *
  23  * Copyright © 2005 Agere Systems Inc.
  24  * All rights reserved.
  25  *
  26  * Redistribution and use in source or binary forms, with or without
  27  * modifications, are permitted provided that the following conditions are met:
  28  *
  29  * . Redistributions of source code must retain the above copyright notice, this
  30  *    list of conditions and the following Disclaimer as comments in the code as
  31  *    well as in the documentation and/or other materials provided with the
  32  *    distribution.
  33  *
  34  * . Redistributions in binary form must reproduce the above copyright notice,
  35  *    this list of conditions and the following Disclaimer in the documentation
  36  *    and/or other materials provided with the distribution.
  37  *
  38  * . Neither the name of Agere Systems Inc. nor the names of the contributors
  39  *    may be used to endorse or promote products derived from this software
  40  *    without specific prior written permission.
  41  *
  42  * Disclaimer
  43  *
  44  * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
  45  * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
  46  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
  47  * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
  48  * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
  49  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  50  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  51  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  52  * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
  53  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  54  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  55  * DAMAGE.
  56  *
  57  */
  58
  59 #ifndef __ET1310_JAGCORE_H__
  60 #define __ET1310_JAGCORE_H__
  61
  62 #include "et1310_address_map.h"
  63
  64
  65 #define INTERNAL_MEM_SIZE       0x400   //1024 of internal memory
  66 #define INTERNAL_MEM_RX_OFFSET  0x1FF   //50%   Tx, 50%   Rx
  67
  68 #define REGS_MAX_ARRAY          4096
  69
  70 /*
  71  * For interrupts, normal running is:
  72  *       rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
  73  *       watchdog_interrupt & txdma_xfer_done
  74  *
  75  * In both cases, when flow control is enabled for either Tx or bi-direction,
  76  * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
  77  * buffer rings are running low.
  78  */
  79 #define INT_MASK_DISABLE            0xffffffff
  80
  81 // NOTE: Masking out MAC_STAT Interrupt for now...
  82 //#define INT_MASK_ENABLE             0xfff6bf17
  83 //#define INT_MASK_ENABLE_NO_FLOW     0xfff6bfd7
  84 #define INT_MASK_ENABLE             0xfffebf17
  85 #define INT_MASK_ENABLE_NO_FLOW     0xfffebfd7
  86
  87 /* DATA STRUCTURES FOR DIRECT REGISTER ACCESS */
  88
  89 typedef struct {
  90         u8 bReadWrite;
  91         u32 nRegCount;
  92         u32 nData[REGS_MAX_ARRAY];
  93         u32 nOffsets[REGS_MAX_ARRAY];
  94 } JAGCORE_ACCESS_REGS, *PJAGCORE_ACCESS_REGS;
  95
  96 typedef struct {
  97         u8 bReadWrite;
  98         u32 nDataWidth;
  99         u32 nRegCount;
 100         u32 nOffsets[REGS_MAX_ARRAY];
 101         u32 nData[REGS_MAX_ARRAY];
 102 } PCI_CFG_SPACE_REGS, *PPCI_CFG_SPACE_REGS;
 103
 104 /* Forward declaration of the private adapter structure */
 105 struct et131x_adapter;
 106
 107 void ConfigGlobalRegs(struct et131x_adapter *pAdapter);
 108 void ConfigMMCRegs(struct et131x_adapter *pAdapter);
 109 void et131x_enable_interrupts(struct et131x_adapter *adapter);
 110 void et131x_disable_interrupts(struct et131x_adapter *adapter);
 111
 112 #endif /* __ET1310_JAGCORE_H__ */