3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et1310_phy.c - Routines for configuring and accessing the PHY
13 *------------------------------------------------------------------------------
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
22 * Copyright © 2005 Agere Systems Inc.
23 * All rights reserved.
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
43 * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
47 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
48 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
49 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
51 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
58 #include "et131x_version.h"
59 #include "et131x_debug.h"
60 #include "et131x_defs.h"
62 #include <linux/pci.h>
63 #include <linux/init.h>
64 #include <linux/module.h>
65 #include <linux/types.h>
66 #include <linux/kernel.h>
68 #include <linux/sched.h>
69 #include <linux/ptrace.h>
70 #include <linux/slab.h>
71 #include <linux/ctype.h>
72 #include <linux/string.h>
73 #include <linux/timer.h>
74 #include <linux/interrupt.h>
76 #include <linux/delay.h>
78 #include <asm/system.h>
79 #include <asm/bitops.h>
81 #include <linux/netdevice.h>
82 #include <linux/etherdevice.h>
83 #include <linux/skbuff.h>
84 #include <linux/if_arp.h>
85 #include <linux/ioport.h>
86 #include <linux/random.h>
87 #include <linux/delay.h>
89 #include "et1310_phy.h"
90 #include "et1310_pm.h"
91 #include "et1310_jagcore.h"
93 #include "et131x_adapter.h"
94 #include "et131x_netdev.h"
95 #include "et131x_initpci.h"
97 #include "et1310_address_map.h"
98 #include "et1310_jagcore.h"
99 #include "et1310_tx.h"
100 #include "et1310_rx.h"
101 #include "et1310_mac.h"
103 /* Data for debugging facilities */
104 #ifdef CONFIG_ET131X_DEBUG
105 extern dbg_info_t
*et131x_dbginfo
;
106 #endif /* CONFIG_ET131X_DEBUG */
108 /* Prototypes for functions with local scope */
109 static int et131x_xcvr_init(struct et131x_adapter
*adapter
);
112 * PhyMiRead - Read from the PHY through the MII Interface on the MAC
113 * @adapter: pointer to our private adapter structure
114 * @xcvrAddr: the address of the transciever
115 * @xcvrReg: the register to read
116 * @value: pointer to a 16-bit value in which the value will be stored
118 * Returns 0 on success, errno on failure (as defined in errno.h)
120 int PhyMiRead(struct et131x_adapter
*adapter
, uint8_t xcvrAddr
,
121 uint8_t xcvrReg
, uint16_t *value
)
123 struct _MAC_t __iomem
*mac
= &adapter
->CSRAddress
->mac
;
126 MII_MGMT_ADDR_t miiAddr
;
127 MII_MGMT_CMD_t miiCmd
;
128 MII_MGMT_INDICATOR_t miiIndicator
;
130 /* Save a local copy of the registers we are dealing with so we can
133 miiAddr
.value
= readl(&mac
->mii_mgmt_addr
.value
);
134 miiCmd
.value
= readl(&mac
->mii_mgmt_cmd
.value
);
136 /* Stop the current operation */
137 writel(0, &mac
->mii_mgmt_cmd
.value
);
139 /* Set up the register we need to read from on the correct PHY */
141 MII_MGMT_ADDR_t mii_mgmt_addr
= { 0 };
143 mii_mgmt_addr
.bits
.phy_addr
= xcvrAddr
;
144 mii_mgmt_addr
.bits
.reg_addr
= xcvrReg
;
145 writel(mii_mgmt_addr
.value
, &mac
->mii_mgmt_addr
.value
);
148 /* Kick the read cycle off */
151 writel(0x1, &mac
->mii_mgmt_cmd
.value
);
156 miiIndicator
.value
= readl(&mac
->mii_mgmt_indicator
.value
);
157 } while ((miiIndicator
.bits
.not_valid
|| miiIndicator
.bits
.busy
) &&
160 /* If we hit the max delay, we could not read the register */
162 DBG_WARNING(et131x_dbginfo
,
163 "xcvrReg 0x%08x could not be read\n", xcvrReg
);
164 DBG_WARNING(et131x_dbginfo
, "status is 0x%08x\n",
170 /* If we hit here we were able to read the register and we need to
171 * return the value to the caller
173 /* TODO: make this stuff a simple readw()?! */
175 MII_MGMT_STAT_t mii_mgmt_stat
;
177 mii_mgmt_stat
.value
= readl(&mac
->mii_mgmt_stat
.value
);
178 *value
= (uint16_t) mii_mgmt_stat
.bits
.phy_stat
;
181 /* Stop the read operation */
182 writel(0, &mac
->mii_mgmt_cmd
.value
);
184 DBG_VERBOSE(et131x_dbginfo
, " xcvr_addr = 0x%02x, "
185 "xcvr_reg = 0x%02x, "
186 "value = 0x%04x.\n", xcvrAddr
, xcvrReg
, *value
);
188 /* set the registers we touched back to the state at which we entered
191 writel(miiAddr
.value
, &mac
->mii_mgmt_addr
.value
);
192 writel(miiCmd
.value
, &mac
->mii_mgmt_cmd
.value
);
198 * MiWrite - Write to a PHY register through the MII interface of the MAC
199 * @adapter: pointer to our private adapter structure
200 * @xcvrReg: the register to read
201 * @value: 16-bit value to write
203 * Return 0 on success, errno on failure (as defined in errno.h)
205 int MiWrite(struct et131x_adapter
*adapter
, uint8_t xcvrReg
, uint16_t value
)
207 struct _MAC_t __iomem
*mac
= &adapter
->CSRAddress
->mac
;
209 uint8_t xcvrAddr
= adapter
->Stats
.xcvr_addr
;
211 MII_MGMT_ADDR_t miiAddr
;
212 MII_MGMT_CMD_t miiCmd
;
213 MII_MGMT_INDICATOR_t miiIndicator
;
215 /* Save a local copy of the registers we are dealing with so we can
218 miiAddr
.value
= readl(&mac
->mii_mgmt_addr
.value
);
219 miiCmd
.value
= readl(&mac
->mii_mgmt_cmd
.value
);
221 /* Stop the current operation */
222 writel(0, &mac
->mii_mgmt_cmd
.value
);
224 /* Set up the register we need to write to on the correct PHY */
226 MII_MGMT_ADDR_t mii_mgmt_addr
;
228 mii_mgmt_addr
.bits
.phy_addr
= xcvrAddr
;
229 mii_mgmt_addr
.bits
.reg_addr
= xcvrReg
;
230 writel(mii_mgmt_addr
.value
, &mac
->mii_mgmt_addr
.value
);
233 /* Add the value to write to the registers to the mac */
234 writel(value
, &mac
->mii_mgmt_ctrl
.value
);
240 miiIndicator
.value
= readl(&mac
->mii_mgmt_indicator
.value
);
241 } while (miiIndicator
.bits
.busy
&& delay
< 100);
243 /* If we hit the max delay, we could not write the register */
247 DBG_WARNING(et131x_dbginfo
,
248 "xcvrReg 0x%08x could not be written", xcvrReg
);
249 DBG_WARNING(et131x_dbginfo
, "status is 0x%08x\n",
251 DBG_WARNING(et131x_dbginfo
, "command is 0x%08x\n",
252 readl(&mac
->mii_mgmt_cmd
.value
));
254 MiRead(adapter
, xcvrReg
, &TempValue
);
259 /* Stop the write operation */
260 writel(0, &mac
->mii_mgmt_cmd
.value
);
262 /* set the registers we touched back to the state at which we entered
265 writel(miiAddr
.value
, &mac
->mii_mgmt_addr
.value
);
266 writel(miiCmd
.value
, &mac
->mii_mgmt_cmd
.value
);
268 DBG_VERBOSE(et131x_dbginfo
, " xcvr_addr = 0x%02x, "
269 "xcvr_reg = 0x%02x, "
270 "value = 0x%04x.\n", xcvrAddr
, xcvrReg
, value
);
276 * et131x_xcvr_find - Find the PHY ID
277 * @adapter: pointer to our private adapter structure
279 * Returns 0 on success, errno on failure (as defined in errno.h)
281 int et131x_xcvr_find(struct et131x_adapter
*adapter
)
283 int status
= -ENODEV
;
289 DBG_ENTER(et131x_dbginfo
);
291 /* We need to get xcvr id and address we just get the first one */
292 for (xcvr_addr
= 0; xcvr_addr
< 32; xcvr_addr
++) {
293 /* Read the ID from the PHY */
294 PhyMiRead(adapter
, xcvr_addr
,
295 (uint8_t) offsetof(MI_REGS_t
, idr1
),
297 PhyMiRead(adapter
, xcvr_addr
,
298 (uint8_t) offsetof(MI_REGS_t
, idr2
),
301 xcvr_id
= (uint32_t) ((idr1
.value
<< 16) | idr2
.value
);
303 if ((idr1
.value
!= 0) && (idr1
.value
!= 0xffff)) {
304 DBG_TRACE(et131x_dbginfo
,
305 "Xcvr addr: 0x%02x\tXcvr_id: 0x%08x\n",
308 adapter
->Stats
.xcvr_id
= xcvr_id
;
309 adapter
->Stats
.xcvr_addr
= xcvr_addr
;
316 DBG_LEAVE(et131x_dbginfo
);
321 * et131x_setphy_normal - Set PHY for normal operation.
322 * @adapter: pointer to our private adapter structure
324 * Used by Power Management to force the PHY into 10 Base T half-duplex mode,
325 * when going to D3 in WOL mode. Also used during initialization to set the
326 * PHY for normal operation.
328 int et131x_setphy_normal(struct et131x_adapter
*adapter
)
332 DBG_ENTER(et131x_dbginfo
);
334 /* Make sure the PHY is powered up */
335 ET1310_PhyPowerDown(adapter
, 0);
336 status
= et131x_xcvr_init(adapter
);
338 DBG_LEAVE(et131x_dbginfo
);
343 * et131x_xcvr_init - Init the phy if we are setting it into force mode
344 * @adapter: pointer to our private adapter structure
346 * Returns 0 on success, errno on failure (as defined in errno.h)
348 static int et131x_xcvr_init(struct et131x_adapter
*adapter
)
355 DBG_ENTER(et131x_dbginfo
);
357 /* Zero out the adapter structure variable representing BMSR */
358 adapter
->Bmsr
.value
= 0;
360 MiRead(adapter
, (uint8_t) offsetof(MI_REGS_t
, isr
), &isr
.value
);
362 MiRead(adapter
, (uint8_t) offsetof(MI_REGS_t
, imr
), &imr
.value
);
364 /* Set the link status interrupt only. Bad behavior when link status
365 * and auto neg are set, we run into a nested interrupt problem
367 imr
.bits
.int_en
= 0x1;
368 imr
.bits
.link_status
= 0x1;
369 imr
.bits
.autoneg_status
= 0x1;
371 MiWrite(adapter
, (uint8_t) offsetof(MI_REGS_t
, imr
), imr
.value
);
373 /* Set the LED behavior such that LED 1 indicates speed (off =
374 * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
375 * link and activity (on for link, blink off for activity).
377 * NOTE: Some customizations have been added here for specific
378 * vendors; The LED behavior is now determined by vendor data in the
379 * EEPROM. However, the above description is the default.
381 if ((adapter
->eepromData
[1] & 0x4) == 0) {
382 MiRead(adapter
, (uint8_t) offsetof(MI_REGS_t
, lcr2
),
384 if ((adapter
->eepromData
[1] & 0x8) == 0)
385 lcr2
.bits
.led_tx_rx
= 0x3;
387 lcr2
.bits
.led_tx_rx
= 0x4;
388 lcr2
.bits
.led_link
= 0xa;
389 MiWrite(adapter
, (uint8_t) offsetof(MI_REGS_t
, lcr2
),
393 /* Determine if we need to go into a force mode and set it */
394 if (adapter
->AiForceSpeed
== 0 && adapter
->AiForceDpx
== 0) {
395 if ((adapter
->RegistryFlowControl
== TxOnly
) ||
396 (adapter
->RegistryFlowControl
== Both
)) {
397 ET1310_PhyAccessMiBit(adapter
,
398 TRUEPHY_BIT_SET
, 4, 11, NULL
);
400 ET1310_PhyAccessMiBit(adapter
,
401 TRUEPHY_BIT_CLEAR
, 4, 11, NULL
);
404 if (adapter
->RegistryFlowControl
== Both
) {
405 ET1310_PhyAccessMiBit(adapter
,
406 TRUEPHY_BIT_SET
, 4, 10, NULL
);
408 ET1310_PhyAccessMiBit(adapter
,
409 TRUEPHY_BIT_CLEAR
, 4, 10, NULL
);
412 /* Set the phy to autonegotiation */
413 ET1310_PhyAutoNeg(adapter
, true);
415 /* NOTE - Do we need this? */
416 ET1310_PhyAccessMiBit(adapter
, TRUEPHY_BIT_SET
, 0, 9, NULL
);
418 DBG_LEAVE(et131x_dbginfo
);
421 ET1310_PhyAutoNeg(adapter
, false);
423 /* Set to the correct force mode. */
424 if (adapter
->AiForceDpx
!= 1) {
425 if ((adapter
->RegistryFlowControl
== TxOnly
) ||
426 (adapter
->RegistryFlowControl
== Both
)) {
427 ET1310_PhyAccessMiBit(adapter
,
428 TRUEPHY_BIT_SET
, 4, 11,
431 ET1310_PhyAccessMiBit(adapter
,
432 TRUEPHY_BIT_CLEAR
, 4, 11,
436 if (adapter
->RegistryFlowControl
== Both
) {
437 ET1310_PhyAccessMiBit(adapter
,
438 TRUEPHY_BIT_SET
, 4, 10,
441 ET1310_PhyAccessMiBit(adapter
,
442 TRUEPHY_BIT_CLEAR
, 4, 10,
446 ET1310_PhyAccessMiBit(adapter
,
447 TRUEPHY_BIT_CLEAR
, 4, 10, NULL
);
448 ET1310_PhyAccessMiBit(adapter
,
449 TRUEPHY_BIT_CLEAR
, 4, 11, NULL
);
452 switch (adapter
->AiForceSpeed
) {
454 if (adapter
->AiForceDpx
== 1) {
455 TPAL_SetPhy10HalfDuplex(adapter
);
456 } else if (adapter
->AiForceDpx
== 2) {
457 TPAL_SetPhy10FullDuplex(adapter
);
459 TPAL_SetPhy10Force(adapter
);
463 if (adapter
->AiForceDpx
== 1) {
464 TPAL_SetPhy100HalfDuplex(adapter
);
465 } else if (adapter
->AiForceDpx
== 2) {
466 TPAL_SetPhy100FullDuplex(adapter
);
468 TPAL_SetPhy100Force(adapter
);
472 TPAL_SetPhy1000FullDuplex(adapter
);
476 DBG_LEAVE(et131x_dbginfo
);
481 void et131x_Mii_check(struct et131x_adapter
*pAdapter
,
482 MI_BMSR_t bmsr
, MI_BMSR_t bmsr_ints
)
484 uint8_t ucLinkStatus
;
485 uint32_t uiAutoNegStatus
;
489 uint32_t uiMasterSlave
;
491 unsigned long lockflags
;
493 DBG_ENTER(et131x_dbginfo
);
495 if (bmsr_ints
.bits
.link_status
) {
496 if (bmsr
.bits
.link_status
) {
497 pAdapter
->PoMgmt
.TransPhyComaModeOnBoot
= 20;
499 /* Update our state variables and indicate the
502 spin_lock_irqsave(&pAdapter
->Lock
, lockflags
);
504 pAdapter
->MediaState
= NETIF_STATUS_MEDIA_CONNECT
;
505 MP_CLEAR_FLAG(pAdapter
, fMP_ADAPTER_LINK_DETECTION
);
507 spin_unlock_irqrestore(&pAdapter
->Lock
, lockflags
);
509 /* Don't indicate state if we're in loopback mode */
510 if (pAdapter
->RegistryPhyLoopbk
== false) {
511 netif_carrier_on(pAdapter
->netdev
);
514 DBG_WARNING(et131x_dbginfo
,
515 "Link down cable problem\n");
517 if (pAdapter
->uiLinkSpeed
== TRUEPHY_SPEED_10MBPS
) {
518 // NOTE - Is there a way to query this without TruePHY?
519 // && TRU_QueryCoreType(pAdapter->hTruePhy, 0) == EMI_TRUEPHY_A13O) {
522 MiRead(pAdapter
, 0x12, &Register18
);
523 MiWrite(pAdapter
, 0x12, Register18
| 0x4);
524 MiWrite(pAdapter
, 0x10, Register18
| 0x8402);
525 MiWrite(pAdapter
, 0x11, Register18
| 511);
526 MiWrite(pAdapter
, 0x12, Register18
);
529 /* For the first N seconds of life, we are in "link
530 * detection" When we are in this state, we should
531 * only report "connected". When the LinkDetection
532 * Timer expires, we can report disconnected (handled
533 * in the LinkDetectionDPC).
535 if ((MP_IS_FLAG_CLEAR
536 (pAdapter
, fMP_ADAPTER_LINK_DETECTION
))
537 || (pAdapter
->MediaState
==
538 NETIF_STATUS_MEDIA_DISCONNECT
)) {
539 spin_lock_irqsave(&pAdapter
->Lock
, lockflags
);
540 pAdapter
->MediaState
=
541 NETIF_STATUS_MEDIA_DISCONNECT
;
542 spin_unlock_irqrestore(&pAdapter
->Lock
,
545 /* Only indicate state if we're in loopback
548 if (pAdapter
->RegistryPhyLoopbk
== false) {
549 netif_carrier_off(pAdapter
->netdev
);
553 pAdapter
->uiLinkSpeed
= 0;
554 pAdapter
->uiDuplexMode
= 0;
556 /* Free the packets being actively sent & stopped */
557 et131x_free_busy_send_packets(pAdapter
);
559 /* Re-initialize the send structures */
560 et131x_init_send(pAdapter
);
562 /* Reset the RFD list and re-start RU */
563 et131x_reset_recv(pAdapter
);
566 * Bring the device back to the state it was during
567 * init prior to autonegotiation being complete. This
568 * way, when we get the auto-neg complete interrupt,
569 * we can complete init by calling ConfigMacREGS2.
571 et131x_soft_reset(pAdapter
);
573 /* Setup ET1310 as per the documentation */
574 et131x_adapter_setup(pAdapter
);
576 /* Setup the PHY into coma mode until the cable is
579 if (pAdapter
->RegistryPhyComa
== 1) {
580 EnablePhyComa(pAdapter
);
585 if (bmsr_ints
.bits
.auto_neg_complete
||
586 ((pAdapter
->AiForceDpx
== 3) && (bmsr_ints
.bits
.link_status
))) {
587 if (bmsr
.bits
.auto_neg_complete
|| (pAdapter
->AiForceDpx
== 3)) {
588 ET1310_PhyLinkStatus(pAdapter
,
589 &ucLinkStatus
, &uiAutoNegStatus
,
590 &uiSpeed
, &uiDuplex
, &uiMdiMdix
,
591 &uiMasterSlave
, &uiPolarity
);
593 pAdapter
->uiLinkSpeed
= uiSpeed
;
594 pAdapter
->uiDuplexMode
= uiDuplex
;
596 DBG_TRACE(et131x_dbginfo
,
597 "pAdapter->uiLinkSpeed 0x%04x, pAdapter->uiDuplex 0x%08x\n",
598 pAdapter
->uiLinkSpeed
,
599 pAdapter
->uiDuplexMode
);
601 pAdapter
->PoMgmt
.TransPhyComaModeOnBoot
= 20;
603 if (pAdapter
->uiLinkSpeed
== TRUEPHY_SPEED_10MBPS
) {
604 // NOTE - Is there a way to query this without TruePHY?
605 // && TRU_QueryCoreType(pAdapter->hTruePhy, 0) == EMI_TRUEPHY_A13O) {
608 MiRead(pAdapter
, 0x12, &Register18
);
609 MiWrite(pAdapter
, 0x12, Register18
| 0x4);
610 MiWrite(pAdapter
, 0x10, Register18
| 0x8402);
611 MiWrite(pAdapter
, 0x11, Register18
| 511);
612 MiWrite(pAdapter
, 0x12, Register18
);
615 ConfigFlowControl(pAdapter
);
617 if ((pAdapter
->uiLinkSpeed
== TRUEPHY_SPEED_1000MBPS
) &&
618 (pAdapter
->RegistryJumboPacket
> 2048))
620 ET1310_PhyAndOrReg(pAdapter
, 0x16, 0xcfff,
624 SetRxDmaTimer(pAdapter
);
625 ConfigMACRegs2(pAdapter
);
629 DBG_LEAVE(et131x_dbginfo
);
633 * TPAL_SetPhy10HalfDuplex - Force the phy into 10 Base T Half Duplex mode.
634 * @pAdapter: pointer to the adapter structure
636 * Also sets the MAC so it is syncd up properly
638 void TPAL_SetPhy10HalfDuplex(struct et131x_adapter
*pAdapter
)
640 DBG_ENTER(et131x_dbginfo
);
643 ET1310_PhyPowerDown(pAdapter
, 1);
645 /* First we need to turn off all other advertisement */
646 ET1310_PhyAdvertise1000BaseT(pAdapter
, TRUEPHY_ADV_DUPLEX_NONE
);
648 ET1310_PhyAdvertise100BaseT(pAdapter
, TRUEPHY_ADV_DUPLEX_NONE
);
650 /* Set our advertise values accordingly */
651 ET1310_PhyAdvertise10BaseT(pAdapter
, TRUEPHY_ADV_DUPLEX_HALF
);
654 ET1310_PhyPowerDown(pAdapter
, 0);
656 DBG_LEAVE(et131x_dbginfo
);
660 * TPAL_SetPhy10FullDuplex - Force the phy into 10 Base T Full Duplex mode.
661 * @pAdapter: pointer to the adapter structure
663 * Also sets the MAC so it is syncd up properly
665 void TPAL_SetPhy10FullDuplex(struct et131x_adapter
*pAdapter
)
667 DBG_ENTER(et131x_dbginfo
);
670 ET1310_PhyPowerDown(pAdapter
, 1);
672 /* First we need to turn off all other advertisement */
673 ET1310_PhyAdvertise1000BaseT(pAdapter
, TRUEPHY_ADV_DUPLEX_NONE
);
675 ET1310_PhyAdvertise100BaseT(pAdapter
, TRUEPHY_ADV_DUPLEX_NONE
);
677 /* Set our advertise values accordingly */
678 ET1310_PhyAdvertise10BaseT(pAdapter
, TRUEPHY_ADV_DUPLEX_FULL
);
681 ET1310_PhyPowerDown(pAdapter
, 0);
683 DBG_LEAVE(et131x_dbginfo
);
687 * TPAL_SetPhy10Force - Force Base-T FD mode WITHOUT using autonegotiation
688 * @pAdapter: pointer to the adapter structure
690 void TPAL_SetPhy10Force(struct et131x_adapter
*pAdapter
)
692 DBG_ENTER(et131x_dbginfo
);
695 ET1310_PhyPowerDown(pAdapter
, 1);
697 /* Disable autoneg */
698 ET1310_PhyAutoNeg(pAdapter
, false);
700 /* Disable all advertisement */
701 ET1310_PhyAdvertise1000BaseT(pAdapter
, TRUEPHY_ADV_DUPLEX_NONE
);
702 ET1310_PhyAdvertise10BaseT(pAdapter
, TRUEPHY_ADV_DUPLEX_NONE
);
703 ET1310_PhyAdvertise100BaseT(pAdapter
, TRUEPHY_ADV_DUPLEX_NONE
);
706 ET1310_PhySpeedSelect(pAdapter
, TRUEPHY_SPEED_10MBPS
);
708 /* Force Full duplex */
709 ET1310_PhyDuplexMode(pAdapter
, TRUEPHY_DUPLEX_FULL
);
712 ET1310_PhyPowerDown(pAdapter
, 0);
714 DBG_LEAVE(et131x_dbginfo
);
718 * TPAL_SetPhy100HalfDuplex - Force 100 Base T Half Duplex mode.
719 * @pAdapter: pointer to the adapter structure
721 * Also sets the MAC so it is syncd up properly.
723 void TPAL_SetPhy100HalfDuplex(struct et131x_adapter
*pAdapter
)
725 DBG_ENTER(et131x_dbginfo
);
728 ET1310_PhyPowerDown(pAdapter
, 1);
730 /* first we need to turn off all other advertisement */
731 ET1310_PhyAdvertise1000BaseT(pAdapter
, TRUEPHY_ADV_DUPLEX_NONE
);
733 ET1310_PhyAdvertise10BaseT(pAdapter
, TRUEPHY_ADV_DUPLEX_NONE
);
735 /* Set our advertise values accordingly */
736 ET1310_PhyAdvertise100BaseT(pAdapter
, TRUEPHY_ADV_DUPLEX_HALF
);
739 ET1310_PhySpeedSelect(pAdapter
, TRUEPHY_SPEED_100MBPS
);
742 ET1310_PhyPowerDown(pAdapter
, 0);
744 DBG_LEAVE(et131x_dbginfo
);
748 * TPAL_SetPhy100FullDuplex - Force 100 Base T Full Duplex mode.
749 * @pAdapter: pointer to the adapter structure
751 * Also sets the MAC so it is syncd up properly
753 void TPAL_SetPhy100FullDuplex(struct et131x_adapter
*pAdapter
)
755 DBG_ENTER(et131x_dbginfo
);
758 ET1310_PhyPowerDown(pAdapter
, 1);
760 /* First we need to turn off all other advertisement */
761 ET1310_PhyAdvertise1000BaseT(pAdapter
, TRUEPHY_ADV_DUPLEX_NONE
);
763 ET1310_PhyAdvertise10BaseT(pAdapter
, TRUEPHY_ADV_DUPLEX_NONE
);
765 /* Set our advertise values accordingly */
766 ET1310_PhyAdvertise100BaseT(pAdapter
, TRUEPHY_ADV_DUPLEX_FULL
);
769 ET1310_PhyPowerDown(pAdapter
, 0);
771 DBG_LEAVE(et131x_dbginfo
);
775 * TPAL_SetPhy100Force - Force 100 BaseT FD mode WITHOUT using autonegotiation
776 * @pAdapter: pointer to the adapter structure
778 void TPAL_SetPhy100Force(struct et131x_adapter
*pAdapter
)
780 DBG_ENTER(et131x_dbginfo
);
783 ET1310_PhyPowerDown(pAdapter
, 1);
785 /* Disable autoneg */
786 ET1310_PhyAutoNeg(pAdapter
, false);
788 /* Disable all advertisement */
789 ET1310_PhyAdvertise1000BaseT(pAdapter
, TRUEPHY_ADV_DUPLEX_NONE
);
790 ET1310_PhyAdvertise10BaseT(pAdapter
, TRUEPHY_ADV_DUPLEX_NONE
);
791 ET1310_PhyAdvertise100BaseT(pAdapter
, TRUEPHY_ADV_DUPLEX_NONE
);
794 ET1310_PhySpeedSelect(pAdapter
, TRUEPHY_SPEED_100MBPS
);
796 /* Force Full duplex */
797 ET1310_PhyDuplexMode(pAdapter
, TRUEPHY_DUPLEX_FULL
);
800 ET1310_PhyPowerDown(pAdapter
, 0);
802 DBG_LEAVE(et131x_dbginfo
);
806 * TPAL_SetPhy1000FullDuplex - Force 1000 Base T Full Duplex mode
807 * @pAdapter: pointer to the adapter structure
809 * Also sets the MAC so it is syncd up properly.
811 void TPAL_SetPhy1000FullDuplex(struct et131x_adapter
*pAdapter
)
813 DBG_ENTER(et131x_dbginfo
);
816 ET1310_PhyPowerDown(pAdapter
, 1);
818 /* first we need to turn off all other advertisement */
819 ET1310_PhyAdvertise100BaseT(pAdapter
, TRUEPHY_ADV_DUPLEX_NONE
);
821 ET1310_PhyAdvertise10BaseT(pAdapter
, TRUEPHY_ADV_DUPLEX_NONE
);
823 /* set our advertise values accordingly */
824 ET1310_PhyAdvertise1000BaseT(pAdapter
, TRUEPHY_ADV_DUPLEX_FULL
);
827 ET1310_PhyPowerDown(pAdapter
, 0);
829 DBG_LEAVE(et131x_dbginfo
);
833 * TPAL_SetPhyAutoNeg - Set phy to autonegotiation mode.
834 * @pAdapter: pointer to the adapter structure
836 void TPAL_SetPhyAutoNeg(struct et131x_adapter
*pAdapter
)
838 DBG_ENTER(et131x_dbginfo
);
841 ET1310_PhyPowerDown(pAdapter
, 1);
843 /* Turn on advertisement of all capabilities */
844 ET1310_PhyAdvertise10BaseT(pAdapter
, TRUEPHY_ADV_DUPLEX_BOTH
);
846 ET1310_PhyAdvertise100BaseT(pAdapter
, TRUEPHY_ADV_DUPLEX_BOTH
);
848 if (pAdapter
->DeviceID
!= ET131X_PCI_DEVICE_ID_FAST
) {
849 ET1310_PhyAdvertise1000BaseT(pAdapter
, TRUEPHY_ADV_DUPLEX_FULL
);
851 ET1310_PhyAdvertise1000BaseT(pAdapter
, TRUEPHY_ADV_DUPLEX_NONE
);
854 /* Make sure auto-neg is ON (it is disabled in FORCE modes) */
855 ET1310_PhyAutoNeg(pAdapter
, true);
858 ET1310_PhyPowerDown(pAdapter
, 0);
860 DBG_LEAVE(et131x_dbginfo
);
865 * The routines which follow provide low-level access to the PHY, and are used
866 * primarily by the routines above (although there are a few places elsewhere
867 * in the driver where this level of access is required).
870 static const uint16_t ConfigPhy
[25][2] = {
871 /* Reg Value Register */
873 {0x880B, 0x0926}, /* AfeIfCreg4B1000Msbs */
874 {0x880C, 0x0926}, /* AfeIfCreg4B100Msbs */
875 {0x880D, 0x0926}, /* AfeIfCreg4B10Msbs */
877 {0x880E, 0xB4D3}, /* AfeIfCreg4B1000Lsbs */
878 {0x880F, 0xB4D3}, /* AfeIfCreg4B100Lsbs */
879 {0x8810, 0xB4D3}, /* AfeIfCreg4B10Lsbs */
881 {0x8805, 0xB03E}, /* AfeIfCreg3B1000Msbs */
882 {0x8806, 0xB03E}, /* AfeIfCreg3B100Msbs */
883 {0x8807, 0xFF00}, /* AfeIfCreg3B10Msbs */
885 {0x8808, 0xE090}, /* AfeIfCreg3B1000Lsbs */
886 {0x8809, 0xE110}, /* AfeIfCreg3B100Lsbs */
887 {0x880A, 0x0000}, /* AfeIfCreg3B10Lsbs */
889 {0x300D, 1}, /* DisableNorm */
891 {0x280C, 0x0180}, /* LinkHoldEnd */
893 {0x1C21, 0x0002}, /* AlphaM */
895 {0x3821, 6}, /* FfeLkgTx0 */
896 {0x381D, 1}, /* FfeLkg1g4 */
897 {0x381E, 1}, /* FfeLkg1g5 */
898 {0x381F, 1}, /* FfeLkg1g6 */
899 {0x3820, 1}, /* FfeLkg1g7 */
901 {0x8402, 0x01F0}, /* Btinact */
902 {0x800E, 20}, /* LftrainTime */
903 {0x800F, 24}, /* DvguardTime */
904 {0x8010, 46}, /* IdlguardTime */
910 /* condensed version of the phy initialization routine */
911 void ET1310_PhyInit(struct et131x_adapter
*pAdapter
)
913 uint16_t usData
, usIndex
;
915 if (pAdapter
== NULL
) {
919 // get the identity (again ?)
920 MiRead(pAdapter
, PHY_ID_1
, &usData
);
921 MiRead(pAdapter
, PHY_ID_2
, &usData
);
923 // what does this do/achieve ?
924 MiRead(pAdapter
, PHY_MPHY_CONTROL_REG
, &usData
); // should read 0002
925 MiWrite(pAdapter
, PHY_MPHY_CONTROL_REG
, 0x0006);
927 // read modem register 0402, should I do something with the return data ?
928 MiWrite(pAdapter
, PHY_INDEX_REG
, 0x0402);
929 MiRead(pAdapter
, PHY_DATA_REG
, &usData
);
931 // what does this do/achieve ?
932 MiWrite(pAdapter
, PHY_MPHY_CONTROL_REG
, 0x0002);
934 // get the identity (again ?)
935 MiRead(pAdapter
, PHY_ID_1
, &usData
);
936 MiRead(pAdapter
, PHY_ID_2
, &usData
);
938 // what does this achieve ?
939 MiRead(pAdapter
, PHY_MPHY_CONTROL_REG
, &usData
); // should read 0002
940 MiWrite(pAdapter
, PHY_MPHY_CONTROL_REG
, 0x0006);
942 // read modem register 0402, should I do something with the return data?
943 MiWrite(pAdapter
, PHY_INDEX_REG
, 0x0402);
944 MiRead(pAdapter
, PHY_DATA_REG
, &usData
);
946 MiWrite(pAdapter
, PHY_MPHY_CONTROL_REG
, 0x0002);
948 // what does this achieve (should return 0x1040)
949 MiRead(pAdapter
, PHY_CONTROL
, &usData
);
950 MiRead(pAdapter
, PHY_MPHY_CONTROL_REG
, &usData
); // should read 0002
951 MiWrite(pAdapter
, PHY_CONTROL
, 0x1840);
953 MiWrite(pAdapter
, PHY_MPHY_CONTROL_REG
, 0x0007);
955 // here the writing of the array starts....
957 while (ConfigPhy
[usIndex
][0] != 0x0000) {
959 MiWrite(pAdapter
, PHY_INDEX_REG
, ConfigPhy
[usIndex
][0]);
960 MiWrite(pAdapter
, PHY_DATA_REG
, ConfigPhy
[usIndex
][1]);
963 MiWrite(pAdapter
, PHY_INDEX_REG
, ConfigPhy
[usIndex
][0]);
964 MiRead(pAdapter
, PHY_DATA_REG
, &usData
);
966 // do a check on the value read back ?
969 // here the writing of the array ends...
971 MiRead(pAdapter
, PHY_CONTROL
, &usData
); // 0x1840
972 MiRead(pAdapter
, PHY_MPHY_CONTROL_REG
, &usData
); // should read 0007
973 MiWrite(pAdapter
, PHY_CONTROL
, 0x1040);
974 MiWrite(pAdapter
, PHY_MPHY_CONTROL_REG
, 0x0002);
977 void ET1310_PhyReset(struct et131x_adapter
*pAdapter
)
979 MiWrite(pAdapter
, PHY_CONTROL
, 0x8000);
982 void ET1310_PhyPowerDown(struct et131x_adapter
*pAdapter
, bool down
)
986 MiRead(pAdapter
, PHY_CONTROL
, &usData
);
991 MiWrite(pAdapter
, PHY_CONTROL
, usData
);
995 MiWrite(pAdapter
, PHY_CONTROL
, usData
);
999 void ET1310_PhyAutoNeg(struct et131x_adapter
*pAdapter
, bool enable
)
1003 MiRead(pAdapter
, PHY_CONTROL
, &usData
);
1005 if (enable
== true) {
1006 // Autonegotiation ON
1008 MiWrite(pAdapter
, PHY_CONTROL
, usData
);
1010 // Autonegotiation OFF
1012 MiWrite(pAdapter
, PHY_CONTROL
, usData
);
1016 void ET1310_PhyDuplexMode(struct et131x_adapter
*pAdapter
, uint16_t duplex
)
1020 MiRead(pAdapter
, PHY_CONTROL
, &usData
);
1022 if (duplex
== TRUEPHY_DUPLEX_FULL
) {
1025 MiWrite(pAdapter
, PHY_CONTROL
, usData
);
1029 MiWrite(pAdapter
, PHY_CONTROL
, usData
);
1033 void ET1310_PhySpeedSelect(struct et131x_adapter
*pAdapter
, uint16_t speed
)
1037 // Read the PHY control register
1038 MiRead(pAdapter
, PHY_CONTROL
, &usData
);
1040 // Clear all Speed settings (Bits 6, 13)
1043 // Reset the speed bits based on user selection
1045 case TRUEPHY_SPEED_10MBPS
:
1046 // Bits already cleared above, do nothing
1049 case TRUEPHY_SPEED_100MBPS
:
1050 // 100M == Set bit 13
1054 case TRUEPHY_SPEED_1000MBPS
:
1060 // Write back the new speed
1061 MiWrite(pAdapter
, PHY_CONTROL
, usData
);
1064 void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter
*pAdapter
,
1069 // Read the PHY 1000 Base-T Control Register
1070 MiRead(pAdapter
, PHY_1000_CONTROL
, &usData
);
1076 case TRUEPHY_ADV_DUPLEX_NONE
:
1077 // Duplex already cleared, do nothing
1080 case TRUEPHY_ADV_DUPLEX_FULL
:
1085 case TRUEPHY_ADV_DUPLEX_HALF
:
1090 case TRUEPHY_ADV_DUPLEX_BOTH
:
1096 // Write back advertisement
1097 MiWrite(pAdapter
, PHY_1000_CONTROL
, usData
);
1100 void ET1310_PhyAdvertise100BaseT(struct et131x_adapter
*pAdapter
,
1105 // Read the Autonegotiation Register (10/100)
1106 MiRead(pAdapter
, PHY_AUTO_ADVERTISEMENT
, &usData
);
1112 case TRUEPHY_ADV_DUPLEX_NONE
:
1113 // Duplex already cleared, do nothing
1116 case TRUEPHY_ADV_DUPLEX_FULL
:
1121 case TRUEPHY_ADV_DUPLEX_HALF
:
1126 case TRUEPHY_ADV_DUPLEX_BOTH
:
1133 // Write back advertisement
1134 MiWrite(pAdapter
, PHY_AUTO_ADVERTISEMENT
, usData
);
1137 void ET1310_PhyAdvertise10BaseT(struct et131x_adapter
*pAdapter
,
1142 // Read the Autonegotiation Register (10/100)
1143 MiRead(pAdapter
, PHY_AUTO_ADVERTISEMENT
, &usData
);
1149 case TRUEPHY_ADV_DUPLEX_NONE
:
1150 // Duplex already cleared, do nothing
1153 case TRUEPHY_ADV_DUPLEX_FULL
:
1158 case TRUEPHY_ADV_DUPLEX_HALF
:
1163 case TRUEPHY_ADV_DUPLEX_BOTH
:
1170 // Write back advertisement
1171 MiWrite(pAdapter
, PHY_AUTO_ADVERTISEMENT
, usData
);
1174 void ET1310_PhyLinkStatus(struct et131x_adapter
*pAdapter
,
1175 uint8_t *ucLinkStatus
,
1176 uint32_t *uiAutoNeg
,
1177 uint32_t *uiLinkSpeed
,
1178 uint32_t *uiDuplexMode
,
1179 uint32_t *uiMdiMdix
,
1180 uint32_t *uiMasterSlave
, uint32_t *uiPolarity
)
1182 uint16_t usMiStatus
= 0;
1183 uint16_t us1000BaseT
= 0;
1184 uint16_t usVmiPhyStatus
= 0;
1185 uint16_t usControl
= 0;
1187 MiRead(pAdapter
, PHY_STATUS
, &usMiStatus
);
1188 MiRead(pAdapter
, PHY_1000_STATUS
, &us1000BaseT
);
1189 MiRead(pAdapter
, PHY_PHY_STATUS
, &usVmiPhyStatus
);
1190 MiRead(pAdapter
, PHY_CONTROL
, &usControl
);
1194 (unsigned char)((usVmiPhyStatus
& 0x0040) ? 1 : 0);
1199 (usControl
& 0x1000) ? ((usVmiPhyStatus
& 0x0020) ?
1200 TRUEPHY_ANEG_COMPLETE
:
1201 TRUEPHY_ANEG_NOT_COMPLETE
) :
1202 TRUEPHY_ANEG_DISABLED
;
1206 *uiLinkSpeed
= (usVmiPhyStatus
& 0x0300) >> 8;
1210 *uiDuplexMode
= (usVmiPhyStatus
& 0x0080) >> 7;
1214 /* NOTE: Need to complete this */
1218 if (uiMasterSlave
) {
1220 (us1000BaseT
& 0x4000) ? TRUEPHY_CFG_MASTER
:
1226 (usVmiPhyStatus
& 0x0400) ? TRUEPHY_POLARITY_INVERTED
:
1227 TRUEPHY_POLARITY_NORMAL
;
1231 void ET1310_PhyAndOrReg(struct et131x_adapter
*pAdapter
,
1232 uint16_t regnum
, uint16_t andMask
, uint16_t orMask
)
1236 // Read the requested register
1237 MiRead(pAdapter
, regnum
, ®
);
1239 // Apply the AND mask
1242 // Apply the OR mask
1245 // Write the value back to the register
1246 MiWrite(pAdapter
, regnum
, reg
);
1249 void ET1310_PhyAccessMiBit(struct et131x_adapter
*pAdapter
, uint16_t action
,
1250 uint16_t regnum
, uint16_t bitnum
, uint8_t *value
)
1255 // Create a mask to isolate the requested bit
1256 mask
= 0x0001 << bitnum
;
1258 // Read the requested register
1259 MiRead(pAdapter
, regnum
, ®
);
1262 case TRUEPHY_BIT_READ
:
1263 if (value
!= NULL
) {
1264 *value
= (reg
& mask
) >> bitnum
;
1268 case TRUEPHY_BIT_SET
:
1270 MiWrite(pAdapter
, regnum
, reg
);
1273 case TRUEPHY_BIT_CLEAR
:
1275 MiWrite(pAdapter
, regnum
, reg
);