3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et1310_phy.h - Defines, structs, enums, prototypes, etc. pertaining to the
14 *------------------------------------------------------------------------------
18 * This software is provided subject to the following terms and conditions,
19 * which you should read carefully before using the software. Using this
20 * software indicates your acceptance of these terms and conditions. If you do
21 * not agree with these terms and conditions, do not use the software.
23 * Copyright © 2005 Agere Systems Inc.
24 * All rights reserved.
26 * Redistribution and use in source or binary forms, with or without
27 * modifications, are permitted provided that the following conditions are met:
29 * . Redistributions of source code must retain the above copyright notice, this
30 * list of conditions and the following Disclaimer as comments in the code as
31 * well as in the documentation and/or other materials provided with the
34 * . Redistributions in binary form must reproduce the above copyright notice,
35 * this list of conditions and the following Disclaimer in the documentation
36 * and/or other materials provided with the distribution.
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39 * may be used to endorse or promote products derived from this software
40 * without specific prior written permission.
44 * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
45 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
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47 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
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49 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
50 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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59 #ifndef _ET1310_PHY_H_
60 #define _ET1310_PHY_H_
62 #include "et1310_address_map.h"
64 #define TRUEPHY_SUCCESS 0
65 #define TRUEPHY_FAILURE 1
66 typedef void *TRUEPHY_HANDLE
;
67 typedef void *TRUEPHY_PLATFORM_HANDLE
;
68 typedef void *TRUEPHY_OSAL_HANDLE
;
70 /* MI Register Addresses */
71 #define MI_CONTROL_REG 0
72 #define MI_STATUS_REG 1
73 #define MI_PHY_IDENTIFIER_1_REG 2
74 #define MI_PHY_IDENTIFIER_2_REG 3
75 #define MI_AUTONEG_ADVERTISEMENT_REG 4
76 #define MI_AUTONEG_LINK_PARTNER_ABILITY_REG 5
77 #define MI_AUTONEG_EXPANSION_REG 6
78 #define MI_AUTONEG_NEXT_PAGE_TRANSMIT_REG 7
79 #define MI_LINK_PARTNER_NEXT_PAGE_REG 8
80 #define MI_1000BASET_CONTROL_REG 9
81 #define MI_1000BASET_STATUS_REG 10
82 #define MI_RESERVED11_REG 11
83 #define MI_RESERVED12_REG 12
84 #define MI_RESERVED13_REG 13
85 #define MI_RESERVED14_REG 14
86 #define MI_EXTENDED_STATUS_REG 15
88 /* VMI Register Addresses */
89 #define VMI_RESERVED16_REG 16
90 #define VMI_RESERVED17_REG 17
91 #define VMI_RESERVED18_REG 18
92 #define VMI_LOOPBACK_CONTROL_REG 19
93 #define VMI_RESERVED20_REG 20
94 #define VMI_MI_CONTROL_REG 21
95 #define VMI_PHY_CONFIGURATION_REG 22
96 #define VMI_PHY_CONTROL_REG 23
97 #define VMI_INTERRUPT_MASK_REG 24
98 #define VMI_INTERRUPT_STATUS_REG 25
99 #define VMI_PHY_STATUS_REG 26
100 #define VMI_LED_CONTROL_1_REG 27
101 #define VMI_LED_CONTROL_2_REG 28
102 #define VMI_RESERVED29_REG 29
103 #define VMI_RESERVED30_REG 30
104 #define VMI_RESERVED31_REG 31
106 /* PHY Register Mapping(MI) Management Interface Regs */
107 typedef struct _MI_REGS_t
{
108 u8 bmcr
; // Basic mode control reg(Reg 0x00)
109 u8 bmsr
; // Basic mode status reg(Reg 0x01)
110 u8 idr1
; // Phy identifier reg 1(Reg 0x02)
111 u8 idr2
; // Phy identifier reg 2(Reg 0x03)
112 u8 anar
; // Auto-Negotiation advertisement(Reg 0x04)
113 u8 anlpar
; // Auto-Negotiation link Partner Ability(Reg 0x05)
114 u8 aner
; // Auto-Negotiation expansion reg(Reg 0x06)
115 u8 annptr
; // Auto-Negotiation next page transmit reg(Reg 0x07)
116 u8 lpnpr
; // link partner next page reg(Reg 0x08)
117 u8 gcr
; // Gigabit basic mode control reg(Reg 0x09)
118 u8 gsr
; // Gigabit basic mode status reg(Reg 0x0A)
119 u8 mi_res1
[4]; // Future use by MI working group(Reg 0x0B - 0x0E)
120 u8 esr
; // Extended status reg(Reg 0x0F)
121 u8 mi_res2
[3]; // Future use by MI working group(Reg 0x10 - 0x12)
122 u8 loop_ctl
; // Loopback Control Reg(Reg 0x13)
123 u8 mi_res3
; // Future use by MI working group(Reg 0x14)
124 u8 mcr
; // MI Control Reg(Reg 0x15)
125 u8 pcr
; // Configuration Reg(Reg 0x16)
126 u8 phy_ctl
; // PHY Control Reg(Reg 0x17)
127 u8 imr
; // Interrupt Mask Reg(Reg 0x18)
128 u8 isr
; // Interrupt Status Reg(Reg 0x19)
129 u8 psr
; // PHY Status Reg(Reg 0x1A)
130 u8 lcr1
; // LED Control 1 Reg(Reg 0x1B)
131 u8 lcr2
; // LED Control 2 Reg(Reg 0x1C)
132 u8 mi_res4
[3]; // Future use by MI working group(Reg 0x1D - 0x1F)
133 } MI_REGS_t
, *PMI_REGS_t
;
135 /* MI Register 0: Basic mode control register */
136 typedef union _MI_BMCR_t
{
139 #ifdef _BIT_FIELDS_HTOL
140 u16 reset
:1; // bit 15
141 u16 loopback
:1; // bit 14
142 u16 speed_sel
:1; // bit 13
143 u16 enable_autoneg
:1; // bit 12
144 u16 power_down
:1; // bit 11
145 u16 isolate
:1; // bit 10
146 u16 restart_autoneg
:1; // bit 9
147 u16 duplex_mode
:1; // bit 8
148 u16 col_test
:1; // bit 7
149 u16 speed_1000_sel
:1; // bit 6
150 u16 res1
:6; // bits 0-5
152 u16 res1
:6; // bits 0-5
153 u16 speed_1000_sel
:1; // bit 6
154 u16 col_test
:1; // bit 7
155 u16 duplex_mode
:1; // bit 8
156 u16 restart_autoneg
:1; // bit 9
157 u16 isolate
:1; // bit 10
158 u16 power_down
:1; // bit 11
159 u16 enable_autoneg
:1; // bit 12
160 u16 speed_sel
:1; // bit 13
161 u16 loopback
:1; // bit 14
162 u16 reset
:1; // bit 15
165 } MI_BMCR_t
, *PMI_BMCR_t
;
167 /* MI Register 1: Basic mode status register */
168 typedef union _MI_BMSR_t
{
171 #ifdef _BIT_FIELDS_HTOL
172 u16 link_100T4
:1; // bit 15
173 u16 link_100fdx
:1; // bit 14
174 u16 link_100hdx
:1; // bit 13
175 u16 link_10fdx
:1; // bit 12
176 u16 link_10hdx
:1; // bit 11
177 u16 link_100T2fdx
:1; // bit 10
178 u16 link_100T2hdx
:1; // bit 9
179 u16 extend_status
:1; // bit 8
181 u16 preamble_supress
:1; // bit 6
182 u16 auto_neg_complete
:1; // bit 5
183 u16 remote_fault
:1; // bit 4
184 u16 auto_neg_able
:1; // bit 3
185 u16 link_status
:1; // bit 2
186 u16 jabber_detect
:1; // bit 1
187 u16 ext_cap
:1; // bit 0
189 u16 ext_cap
:1; // bit 0
190 u16 jabber_detect
:1; // bit 1
191 u16 link_status
:1; // bit 2
192 u16 auto_neg_able
:1; // bit 3
193 u16 remote_fault
:1; // bit 4
194 u16 auto_neg_complete
:1; // bit 5
195 u16 preamble_supress
:1; // bit 6
197 u16 extend_status
:1; // bit 8
198 u16 link_100T2hdx
:1; // bit 9
199 u16 link_100T2fdx
:1; // bit 10
200 u16 link_10hdx
:1; // bit 11
201 u16 link_10fdx
:1; // bit 12
202 u16 link_100hdx
:1; // bit 13
203 u16 link_100fdx
:1; // bit 14
204 u16 link_100T4
:1; // bit 15
207 } MI_BMSR_t
, *PMI_BMSR_t
;
209 /* MI Register 2: Physical Identifier 1 */
210 typedef union _MI_IDR1_t
{
213 u16 ieee_address
:16; // 0x0282 default(bits 0-15)
215 } MI_IDR1_t
, *PMI_IDR1_t
;
217 /* MI Register 3: Physical Identifier 2 */
218 typedef union _MI_IDR2_t
{
221 #ifdef _BIT_FIELDS_HTOL
222 u16 ieee_address
:6; // 111100 default(bits 10-15)
223 u16 model_no
:6; // 000001 default(bits 4-9)
224 u16 rev_no
:4; // 0010 default(bits 0-3)
226 u16 rev_no
:4; // 0010 default(bits 0-3)
227 u16 model_no
:6; // 000001 default(bits 4-9)
228 u16 ieee_address
:6; // 111100 default(bits 10-15)
231 } MI_IDR2_t
, *PMI_IDR2_t
;
233 /* MI Register 4: Auto-negotiation advertisement register */
234 typedef union _MI_ANAR_t
{
237 #ifdef _BIT_FIELDS_HTOL
238 u16 np_indication
:1; // bit 15
239 u16 res2
:1; // bit 14
240 u16 remote_fault
:1; // bit 13
241 u16 res1
:1; // bit 12
242 u16 cap_asmpause
:1; // bit 11
243 u16 cap_pause
:1; // bit 10
244 u16 cap_100T4
:1; // bit 9
245 u16 cap_100fdx
:1; // bit 8
246 u16 cap_100hdx
:1; // bit 7
247 u16 cap_10fdx
:1; // bit 6
248 u16 cap_10hdx
:1; // bit 5
249 u16 selector
:5; // bits 0-4
251 u16 selector
:5; // bits 0-4
252 u16 cap_10hdx
:1; // bit 5
253 u16 cap_10fdx
:1; // bit 6
254 u16 cap_100hdx
:1; // bit 7
255 u16 cap_100fdx
:1; // bit 8
256 u16 cap_100T4
:1; // bit 9
257 u16 cap_pause
:1; // bit 10
258 u16 cap_asmpause
:1; // bit 11
259 u16 res1
:1; // bit 12
260 u16 remote_fault
:1; // bit 13
261 u16 res2
:1; // bit 14
262 u16 np_indication
:1; // bit 15
265 } MI_ANAR_t
, *PMI_ANAR_t
;
267 /* MI Register 5: Auto-negotiation link partner advertisement register */
268 typedef struct _MI_ANLPAR_t
{
271 #ifdef _BIT_FIELDS_HTOL
272 u16 np_indication
:1; // bit 15
273 u16 acknowledge
:1; // bit 14
274 u16 remote_fault
:1; // bit 13
275 u16 res1
:1; // bit 12
276 u16 cap_asmpause
:1; // bit 11
277 u16 cap_pause
:1; // bit 10
278 u16 cap_100T4
:1; // bit 9
279 u16 cap_100fdx
:1; // bit 8
280 u16 cap_100hdx
:1; // bit 7
281 u16 cap_10fdx
:1; // bit 6
282 u16 cap_10hdx
:1; // bit 5
283 u16 selector
:5; // bits 0-4
285 u16 selector
:5; // bits 0-4
286 u16 cap_10hdx
:1; // bit 5
287 u16 cap_10fdx
:1; // bit 6
288 u16 cap_100hdx
:1; // bit 7
289 u16 cap_100fdx
:1; // bit 8
290 u16 cap_100T4
:1; // bit 9
291 u16 cap_pause
:1; // bit 10
292 u16 cap_asmpause
:1; // bit 11
293 u16 res1
:1; // bit 12
294 u16 remote_fault
:1; // bit 13
295 u16 acknowledge
:1; // bit 14
296 u16 np_indication
:1; // bit 15
299 } MI_ANLPAR_t
, *PMI_ANLPAR_t
;
301 /* MI Register 6: Auto-negotiation expansion register */
302 typedef union _MI_ANER_t
{
305 #ifdef _BIT_FIELDS_HTOL
306 u16 res
:11; // bits 5-15
308 u16 lp_np_able
:1; // bit 3
309 u16 np_able
:1; // bit 2
310 u16 page_rx
:1; // bit 1
311 u16 lp_an_able
:1; // bit 0
313 u16 lp_an_able
:1; // bit 0
314 u16 page_rx
:1; // bit 1
315 u16 np_able
:1; // bit 2
316 u16 lp_np_able
:1; // bit 3
318 u16 res
:11; // bits 5-15
321 } MI_ANER_t
, *PMI_ANER_t
;
323 /* MI Register 7: Auto-negotiation next page transmit reg(0x07) */
324 typedef union _MI_ANNPTR_t
{
327 #ifdef _BIT_FIELDS_HTOL
329 u16 res1
:1; // bit 14
330 u16 msg_page
:1; // bit 13
331 u16 ack2
:1; // bit 12
332 u16 toggle
:1; // bit 11
333 u16 msg
:11; // bits 0-10
335 u16 msg
:11; // bits 0-10
336 u16 toggle
:1; // bit 11
337 u16 ack2
:1; // bit 12
338 u16 msg_page
:1; // bit 13
339 u16 res1
:1; // bit 14
343 } MI_ANNPTR_t
, *PMI_ANNPTR_t
;
345 /* MI Register 8: Link Partner Next Page Reg(0x08) */
346 typedef union _MI_LPNPR_t
{
349 #ifdef _BIT_FIELDS_HTOL
352 u16 msg_page
:1; // bit 13
353 u16 ack2
:1; // bit 12
354 u16 toggle
:1; // bit 11
355 u16 msg
:11; // bits 0-10
357 u16 msg
:11; // bits 0-10
358 u16 toggle
:1; // bit 11
359 u16 ack2
:1; // bit 12
360 u16 msg_page
:1; // bit 13
365 } MI_LPNPR_t
, *PMI_LPNPR_t
;
367 /* MI Register 9: 1000BaseT Control Reg(0x09) */
368 typedef union _MI_GCR_t
{
371 #ifdef _BIT_FIELDS_HTOL
372 u16 test_mode
:3; // bits 13-15
373 u16 ms_config_en
:1; // bit 12
374 u16 ms_value
:1; // bit 11
375 u16 port_type
:1; // bit 10
376 u16 link_1000fdx
:1; // bit 9
377 u16 link_1000hdx
:1; // bit 8
378 u16 res
:8; // bit 0-7
380 u16 res
:8; // bit 0-7
381 u16 link_1000hdx
:1; // bit 8
382 u16 link_1000fdx
:1; // bit 9
383 u16 port_type
:1; // bit 10
384 u16 ms_value
:1; // bit 11
385 u16 ms_config_en
:1; // bit 12
386 u16 test_mode
:3; // bits 13-15
389 } MI_GCR_t
, *PMI_GCR_t
;
391 /* MI Register 10: 1000BaseT Status Reg(0x0A) */
392 typedef union _MI_GSR_t
{
395 #ifdef _BIT_FIELDS_HTOL
396 u16 ms_config_fault
:1; // bit 15
397 u16 ms_resolve
:1; // bit 14
398 u16 local_rx_status
:1; // bit 13
399 u16 remote_rx_status
:1; // bit 12
400 u16 link_1000fdx
:1; // bit 11
401 u16 link_1000hdx
:1; // bit 10
402 u16 res
:2; // bits 8-9
403 u16 idle_err_cnt
:8; // bits 0-7
405 u16 idle_err_cnt
:8; // bits 0-7
406 u16 res
:2; // bits 8-9
407 u16 link_1000hdx
:1; // bit 10
408 u16 link_1000fdx
:1; // bit 11
409 u16 remote_rx_status
:1; // bit 12
410 u16 local_rx_status
:1; // bit 13
411 u16 ms_resolve
:1; // bit 14
412 u16 ms_config_fault
:1; // bit 15
415 } MI_GSR_t
, *PMI_GSR_t
;
417 /* MI Register 11 - 14: Reserved Regs(0x0B - 0x0E) */
418 typedef union _MI_RES_t
{
421 #ifdef _BIT_FIELDS_HTOL
422 u16 res15
:1; // bit 15
423 u16 res14
:1; // bit 14
424 u16 res13
:1; // bit 13
425 u16 res12
:1; // bit 12
426 u16 res11
:1; // bit 11
427 u16 res10
:1; // bit 10
449 u16 res10
:1; // bit 10
450 u16 res11
:1; // bit 11
451 u16 res12
:1; // bit 12
452 u16 res13
:1; // bit 13
453 u16 res14
:1; // bit 14
454 u16 res15
:1; // bit 15
457 } MI_RES_t
, *PMI_RES_t
;
459 /* MI Register 15: Extended status Reg(0x0F) */
460 typedef union _MI_ESR_t
{
463 #ifdef _BIT_FIELDS_HTOL
464 u16 link_1000Xfdx
:1; // bit 15
465 u16 link_1000Xhdx
:1; // bit 14
466 u16 link_1000fdx
:1; // bit 13
467 u16 link_1000hdx
:1; // bit 12
468 u16 res
:12; // bit 0-11
470 u16 res
:12; // bit 0-11
471 u16 link_1000hdx
:1; // bit 12
472 u16 link_1000fdx
:1; // bit 13
473 u16 link_1000Xhdx
:1; // bit 14
474 u16 link_1000Xfdx
:1; // bit 15
477 } MI_ESR_t
, *PMI_ESR_t
;
479 /* MI Register 16 - 18: Reserved Reg(0x10-0x12) */
481 /* MI Register 19: Loopback Control Reg(0x13) */
482 typedef union _MI_LCR_t
{
485 #ifdef _BIT_FIELDS_HTOL
486 u16 mii_en
:1; // bit 15
487 u16 pcs_en
:1; // bit 14
488 u16 pmd_en
:1; // bit 13
489 u16 all_digital_en
:1; // bit 12
490 u16 replica_en
:1; // bit 11
491 u16 line_driver_en
:1; // bit 10
492 u16 res
:10; // bit 0-9
494 u16 res
:10; // bit 0-9
495 u16 line_driver_en
:1; // bit 10
496 u16 replica_en
:1; // bit 11
497 u16 all_digital_en
:1; // bit 12
498 u16 pmd_en
:1; // bit 13
499 u16 pcs_en
:1; // bit 14
500 u16 mii_en
:1; // bit 15
503 } MI_LCR_t
, *PMI_LCR_t
;
505 /* MI Register 20: Reserved Reg(0x14) */
507 /* MI Register 21: Management Interface Control Reg(0x15) */
508 typedef union _MI_MICR_t
{
511 #ifdef _BIT_FIELDS_HTOL
512 u16 res1
:5; // bits 11-15
513 u16 mi_error_count
:7; // bits 4-10
515 u16 ignore_10g_fr
:1; // bit 2
517 u16 preamble_supress_en
:1; // bit 0
519 u16 preamble_supress_en
:1; // bit 0
521 u16 ignore_10g_fr
:1; // bit 2
523 u16 mi_error_count
:7; // bits 4-10
524 u16 res1
:5; // bits 11-15
527 } MI_MICR_t
, *PMI_MICR_t
;
529 /* MI Register 22: PHY Configuration Reg(0x16) */
530 typedef union _MI_PHY_CONFIG_t
{
533 #ifdef _BIT_FIELDS_HTOL
534 u16 crs_tx_en
:1; // bit 15
535 u16 res1
:1; // bit 14
536 u16 tx_fifo_depth
:2; // bits 12-13
537 u16 speed_downshift
:2; // bits 10-11
538 u16 pbi_detect
:1; // bit 9
539 u16 tbi_rate
:1; // bit 8
540 u16 alternate_np
:1; // bit 7
541 u16 group_mdio_en
:1; // bit 6
542 u16 tx_clock_en
:1; // bit 5
543 u16 sys_clock_en
:1; // bit 4
545 u16 mac_if_mode
:3; // bits 0-2
547 u16 mac_if_mode
:3; // bits 0-2
549 u16 sys_clock_en
:1; // bit 4
550 u16 tx_clock_en
:1; // bit 5
551 u16 group_mdio_en
:1; // bit 6
552 u16 alternate_np
:1; // bit 7
553 u16 tbi_rate
:1; // bit 8
554 u16 pbi_detect
:1; // bit 9
555 u16 speed_downshift
:2; // bits 10-11
556 u16 tx_fifo_depth
:2; // bits 12-13
557 u16 res1
:1; // bit 14
558 u16 crs_tx_en
:1; // bit 15
561 } MI_PHY_CONFIG_t
, *PMI_PHY_CONFIG_t
;
563 /* MI Register 23: PHY CONTROL Reg(0x17) */
564 typedef union _MI_PHY_CONTROL_t
{
567 #ifdef _BIT_FIELDS_HTOL
568 u16 res1
:1; // bit 15
569 u16 tdr_en
:1; // bit 14
570 u16 res2
:1; // bit 13
571 u16 downshift_attempts
:2; // bits 11-12
572 u16 res3
:5; // bit 6-10
573 u16 jabber_10baseT
:1; // bit 5
574 u16 sqe_10baseT
:1; // bit 4
575 u16 tp_loopback_10baseT
:1; // bit 3
576 u16 preamble_gen_en
:1; // bit 2
578 u16 force_int
:1; // bit 0
580 u16 force_int
:1; // bit 0
582 u16 preamble_gen_en
:1; // bit 2
583 u16 tp_loopback_10baseT
:1; // bit 3
584 u16 sqe_10baseT
:1; // bit 4
585 u16 jabber_10baseT
:1; // bit 5
586 u16 res3
:5; // bit 6-10
587 u16 downshift_attempts
:2; // bits 11-12
588 u16 res2
:1; // bit 13
589 u16 tdr_en
:1; // bit 14
590 u16 res1
:1; // bit 15
593 } MI_PHY_CONTROL_t
, *PMI_PHY_CONTROL_t
;
595 /* MI Register 24: Interrupt Mask Reg(0x18) */
596 typedef union _MI_IMR_t
{
599 #ifdef _BIT_FIELDS_HTOL
600 u16 res1
:6; // bits 10-15
601 u16 mdio_sync_lost
:1; // bit 9
602 u16 autoneg_status
:1; // bit 8
603 u16 hi_bit_err
:1; // bit 7
604 u16 np_rx
:1; // bit 6
605 u16 err_counter_full
:1; // bit 5
606 u16 fifo_over_underflow
:1; // bit 4
607 u16 rx_status
:1; // bit 3
608 u16 link_status
:1; // bit 2
609 u16 automatic_speed
:1; // bit 1
610 u16 int_en
:1; // bit 0
612 u16 int_en
:1; // bit 0
613 u16 automatic_speed
:1; // bit 1
614 u16 link_status
:1; // bit 2
615 u16 rx_status
:1; // bit 3
616 u16 fifo_over_underflow
:1; // bit 4
617 u16 err_counter_full
:1; // bit 5
618 u16 np_rx
:1; // bit 6
619 u16 hi_bit_err
:1; // bit 7
620 u16 autoneg_status
:1; // bit 8
621 u16 mdio_sync_lost
:1; // bit 9
622 u16 res1
:6; // bits 10-15
625 } MI_IMR_t
, *PMI_IMR_t
;
627 /* MI Register 25: Interrupt Status Reg(0x19) */
628 typedef union _MI_ISR_t
{
631 #ifdef _BIT_FIELDS_HTOL
632 u16 res1
:6; // bits 10-15
633 u16 mdio_sync_lost
:1; // bit 9
634 u16 autoneg_status
:1; // bit 8
635 u16 hi_bit_err
:1; // bit 7
636 u16 np_rx
:1; // bit 6
637 u16 err_counter_full
:1; // bit 5
638 u16 fifo_over_underflow
:1; // bit 4
639 u16 rx_status
:1; // bit 3
640 u16 link_status
:1; // bit 2
641 u16 automatic_speed
:1; // bit 1
642 u16 int_en
:1; // bit 0
644 u16 int_en
:1; // bit 0
645 u16 automatic_speed
:1; // bit 1
646 u16 link_status
:1; // bit 2
647 u16 rx_status
:1; // bit 3
648 u16 fifo_over_underflow
:1; // bit 4
649 u16 err_counter_full
:1; // bit 5
650 u16 np_rx
:1; // bit 6
651 u16 hi_bit_err
:1; // bit 7
652 u16 autoneg_status
:1; // bit 8
653 u16 mdio_sync_lost
:1; // bit 9
654 u16 res1
:6; // bits 10-15
657 } MI_ISR_t
, *PMI_ISR_t
;
659 /* MI Register 26: PHY Status Reg(0x1A) */
660 typedef union _MI_PSR_t
{
663 #ifdef _BIT_FIELDS_HTOL
664 u16 res1
:1; // bit 15
665 u16 autoneg_fault
:2; // bit 13-14
666 u16 autoneg_status
:1; // bit 12
667 u16 mdi_x_status
:1; // bit 11
668 u16 polarity_status
:1; // bit 10
669 u16 speed_status
:2; // bits 8-9
670 u16 duplex_status
:1; // bit 7
671 u16 link_status
:1; // bit 6
672 u16 tx_status
:1; // bit 5
673 u16 rx_status
:1; // bit 4
674 u16 collision_status
:1; // bit 3
675 u16 autoneg_en
:1; // bit 2
676 u16 pause_en
:1; // bit 1
677 u16 asymmetric_dir
:1; // bit 0
679 u16 asymmetric_dir
:1; // bit 0
680 u16 pause_en
:1; // bit 1
681 u16 autoneg_en
:1; // bit 2
682 u16 collision_status
:1; // bit 3
683 u16 rx_status
:1; // bit 4
684 u16 tx_status
:1; // bit 5
685 u16 link_status
:1; // bit 6
686 u16 duplex_status
:1; // bit 7
687 u16 speed_status
:2; // bits 8-9
688 u16 polarity_status
:1; // bit 10
689 u16 mdi_x_status
:1; // bit 11
690 u16 autoneg_status
:1; // bit 12
691 u16 autoneg_fault
:2; // bit 13-14
692 u16 res1
:1; // bit 15
695 } MI_PSR_t
, *PMI_PSR_t
;
697 /* MI Register 27: LED Control Reg 1(0x1B) */
698 typedef union _MI_LCR1_t
{
701 #ifdef _BIT_FIELDS_HTOL
702 u16 res1
:2; // bits 14-15
703 u16 led_dup_indicate
:2; // bits 12-13
704 u16 led_10baseT
:2; // bits 10-11
705 u16 led_collision
:2; // bits 8-9
706 u16 res2
:2; // bits 6-7
707 u16 res3
:2; // bits 4-5
708 u16 pulse_dur
:2; // bits 2-3
709 u16 pulse_stretch1
:1; // bit 1
710 u16 pulse_stretch0
:1; // bit 0
712 u16 pulse_stretch0
:1; // bit 0
713 u16 pulse_stretch1
:1; // bit 1
714 u16 pulse_dur
:2; // bits 2-3
715 u16 res3
:2; // bits 4-5
716 u16 res2
:2; // bits 6-7
717 u16 led_collision
:2; // bits 8-9
718 u16 led_10baseT
:2; // bits 10-11
719 u16 led_dup_indicate
:2; // bits 12-13
720 u16 res1
:2; // bits 14-15
723 } MI_LCR1_t
, *PMI_LCR1_t
;
725 /* MI Register 28: LED Control Reg 2(0x1C) */
726 typedef union _MI_LCR2_t
{
729 #ifdef _BIT_FIELDS_HTOL
730 u16 led_link
:4; // bits 12-15
731 u16 led_tx_rx
:4; // bits 8-11
732 u16 led_100BaseTX
:4; // bits 4-7
733 u16 led_1000BaseT
:4; // bits 0-3
735 u16 led_1000BaseT
:4; // bits 0-3
736 u16 led_100BaseTX
:4; // bits 4-7
737 u16 led_tx_rx
:4; // bits 8-11
738 u16 led_link
:4; // bits 12-15
741 } MI_LCR2_t
, *PMI_LCR2_t
;
743 /* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */
745 /* TruePHY headers */
746 typedef struct _TRUEPHY_ACCESS_MI_REGS_
{
747 TRUEPHY_HANDLE hTruePhy
;
753 } TRUEPHY_ACCESS_MI_REGS
, *PTRUEPHY_ACCESS_MI_REGS
;
755 /* TruePHY headers */
756 typedef struct _TAG_TPAL_ACCESS_MI_REGS_
{
762 } TPAL_ACCESS_MI_REGS
, *PTPAL_ACCESS_MI_REGS
;
765 typedef TRUEPHY_HANDLE TPAL_HANDLE
;
767 /* Forward declaration of the private adapter structure */
768 struct et131x_adapter
;
770 /* OS Specific Functions*/
771 void TPAL_SetPhy10HalfDuplex(struct et131x_adapter
*adapter
);
772 void TPAL_SetPhy10FullDuplex(struct et131x_adapter
*adapter
);
773 void TPAL_SetPhy10Force(struct et131x_adapter
*pAdapter
);
774 void TPAL_SetPhy100HalfDuplex(struct et131x_adapter
*adapter
);
775 void TPAL_SetPhy100FullDuplex(struct et131x_adapter
*adapter
);
776 void TPAL_SetPhy100Force(struct et131x_adapter
*pAdapter
);
777 void TPAL_SetPhy1000FullDuplex(struct et131x_adapter
*adapter
);
778 void TPAL_SetPhyAutoNeg(struct et131x_adapter
*adapter
);
780 /* Prototypes for ET1310_phy.c */
781 int et131x_xcvr_find(struct et131x_adapter
*adapter
);
782 int et131x_setphy_normal(struct et131x_adapter
*adapter
);
783 int32_t PhyMiRead(struct et131x_adapter
*adapter
,
784 u8 xcvrAddr
, u8 xcvrReg
, u16
*value
);
786 /* static inline function does not work because et131x_adapter is not always
789 #define MiRead(adapter, xcvrReg, value) \
790 PhyMiRead((adapter), (adapter)->Stats.xcvr_addr, (xcvrReg), (value))
792 int32_t MiWrite(struct et131x_adapter
*adapter
,
793 u8 xcvReg
, u16 value
);
794 void et131x_Mii_check(struct et131x_adapter
*pAdapter
,
795 MI_BMSR_t bmsr
, MI_BMSR_t bmsr_ints
);
797 /* This last is not strictly required (the driver could call the TPAL
798 * version instead), but this sets the adapter up correctly, and calls the
799 * access routine indirectly. This protects the driver from changes in TPAL.
801 void SetPhy_10BaseTHalfDuplex(struct et131x_adapter
*adapter
);
803 /* Defines for PHY access routines */
805 // Define bit operation flags
806 #define TRUEPHY_BIT_CLEAR 0
807 #define TRUEPHY_BIT_SET 1
808 #define TRUEPHY_BIT_READ 2
810 // Define read/write operation flags
812 #define TRUEPHY_READ 0
813 #define TRUEPHY_WRITE 1
814 #define TRUEPHY_MASK 2
818 #define TRUEPHY_SPEED_10MBPS 0
819 #define TRUEPHY_SPEED_100MBPS 1
820 #define TRUEPHY_SPEED_1000MBPS 2
822 // Define duplex modes
823 #define TRUEPHY_DUPLEX_HALF 0
824 #define TRUEPHY_DUPLEX_FULL 1
826 // Define master/slave configuration values
827 #define TRUEPHY_CFG_SLAVE 0
828 #define TRUEPHY_CFG_MASTER 1
830 // Define MDI/MDI-X settings
831 #define TRUEPHY_MDI 0
832 #define TRUEPHY_MDIX 1
833 #define TRUEPHY_AUTO_MDI_MDIX 2
835 // Define 10Base-T link polarities
836 #define TRUEPHY_POLARITY_NORMAL 0
837 #define TRUEPHY_POLARITY_INVERTED 1
839 // Define auto-negotiation results
840 #define TRUEPHY_ANEG_NOT_COMPLETE 0
841 #define TRUEPHY_ANEG_COMPLETE 1
842 #define TRUEPHY_ANEG_DISABLED 2
844 /* Define duplex advertisment flags */
845 #define TRUEPHY_ADV_DUPLEX_NONE 0x00
846 #define TRUEPHY_ADV_DUPLEX_FULL 0x01
847 #define TRUEPHY_ADV_DUPLEX_HALF 0x02
848 #define TRUEPHY_ADV_DUPLEX_BOTH \
849 (TRUEPHY_ADV_DUPLEX_FULL | TRUEPHY_ADV_DUPLEX_HALF)
851 #define PHY_CONTROL 0x00 //#define TRU_MI_CONTROL_REGISTER 0
852 #define PHY_STATUS 0x01 //#define TRU_MI_STATUS_REGISTER 1
853 #define PHY_ID_1 0x02 //#define TRU_MI_PHY_IDENTIFIER_1_REGISTER 2
854 #define PHY_ID_2 0x03 //#define TRU_MI_PHY_IDENTIFIER_2_REGISTER 3
855 #define PHY_AUTO_ADVERTISEMENT 0x04 //#define TRU_MI_ADVERTISEMENT_REGISTER 4
856 #define PHY_AUTO_LINK_PARTNER 0x05 //#define TRU_MI_LINK_PARTNER_ABILITY_REGISTER 5
857 #define PHY_AUTO_EXPANSION 0x06 //#define TRU_MI_EXPANSION_REGISTER 6
858 #define PHY_AUTO_NEXT_PAGE_TX 0x07 //#define TRU_MI_NEXT_PAGE_TRANSMIT_REGISTER 7
859 #define PHY_LINK_PARTNER_NEXT_PAGE 0x08 //#define TRU_MI_LINK_PARTNER_NEXT_PAGE_REGISTER 8
860 #define PHY_1000_CONTROL 0x09 //#define TRU_MI_1000BASET_CONTROL_REGISTER 9
861 #define PHY_1000_STATUS 0x0A //#define TRU_MI_1000BASET_STATUS_REGISTER 10
863 #define PHY_EXTENDED_STATUS 0x0F //#define TRU_MI_EXTENDED_STATUS_REGISTER 15
865 // some defines for modem registers that seem to be 'reserved'
866 #define PHY_INDEX_REG 0x10
867 #define PHY_DATA_REG 0x11
869 #define PHY_MPHY_CONTROL_REG 0x12 //#define TRU_VMI_MPHY_CONTROL_REGISTER 18
871 #define PHY_LOOPBACK_CONTROL 0x13 //#define TRU_VMI_LOOPBACK_CONTROL_1_REGISTER 19
872 //#define TRU_VMI_LOOPBACK_CONTROL_2_REGISTER 20
873 #define PHY_REGISTER_MGMT_CONTROL 0x15 //#define TRU_VMI_MI_SEQ_CONTROL_REGISTER 21
874 #define PHY_CONFIG 0x16 //#define TRU_VMI_CONFIGURATION_REGISTER 22
875 #define PHY_PHY_CONTROL 0x17 //#define TRU_VMI_PHY_CONTROL_REGISTER 23
876 #define PHY_INTERRUPT_MASK 0x18 //#define TRU_VMI_INTERRUPT_MASK_REGISTER 24
877 #define PHY_INTERRUPT_STATUS 0x19 //#define TRU_VMI_INTERRUPT_STATUS_REGISTER 25
878 #define PHY_PHY_STATUS 0x1A //#define TRU_VMI_PHY_STATUS_REGISTER 26
879 #define PHY_LED_1 0x1B //#define TRU_VMI_LED_CONTROL_1_REGISTER 27
880 #define PHY_LED_2 0x1C //#define TRU_VMI_LED_CONTROL_2_REGISTER 28
881 //#define TRU_VMI_LINK_CONTROL_REGISTER 29
882 //#define TRU_VMI_TIMING_CONTROL_REGISTER
884 /* Prototypes for PHY access routines */
885 void ET1310_PhyInit(struct et131x_adapter
*adapter
);
886 void ET1310_PhyReset(struct et131x_adapter
*adapter
);
887 void ET1310_PhyPowerDown(struct et131x_adapter
*adapter
, bool down
);
888 void ET1310_PhyAutoNeg(struct et131x_adapter
*adapter
, bool enable
);
889 void ET1310_PhyDuplexMode(struct et131x_adapter
*adapter
, u16 duplex
);
890 void ET1310_PhySpeedSelect(struct et131x_adapter
*adapter
, u16 speed
);
891 void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter
*adapter
,
893 void ET1310_PhyAdvertise100BaseT(struct et131x_adapter
*adapter
,
895 void ET1310_PhyAdvertise10BaseT(struct et131x_adapter
*adapter
,
897 void ET1310_PhyLinkStatus(struct et131x_adapter
*adapter
,
903 u32
*uiMasterSlave
, u32
*uiPolarity
);
904 void ET1310_PhyAndOrReg(struct et131x_adapter
*adapter
,
905 u16 regnum
, u16 andMask
, u16 orMask
);
906 void ET1310_PhyAccessMiBit(struct et131x_adapter
*adapter
,
908 u16 regnum
, u16 bitnum
, u8
*value
);
910 #endif /* _ET1310_PHY_H_ */