Add ET131x ethernet driver.
[people/pmueller/ipfire-2.x.git] / src / et131x / et131x_adapter.h
1 /*
2 * Agere Systems Inc.
3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
4 *
5 * Copyright © 2005 Agere Systems Inc.
6 * All rights reserved.
7 * http://www.agere.com
8 *
9 *------------------------------------------------------------------------------
10 *
11 * et131x_adapter.h - Header which includes the private adapter structure, along
12 * with related support structures, macros, definitions, etc.
13 *
14 *------------------------------------------------------------------------------
15 *
16 * SOFTWARE LICENSE
17 *
18 * This software is provided subject to the following terms and conditions,
19 * which you should read carefully before using the software. Using this
20 * software indicates your acceptance of these terms and conditions. If you do
21 * not agree with these terms and conditions, do not use the software.
22 *
23 * Copyright © 2005 Agere Systems Inc.
24 * All rights reserved.
25 *
26 * Redistribution and use in source or binary forms, with or without
27 * modifications, are permitted provided that the following conditions are met:
28 *
29 * . Redistributions of source code must retain the above copyright notice, this
30 * list of conditions and the following Disclaimer as comments in the code as
31 * well as in the documentation and/or other materials provided with the
32 * distribution.
33 *
34 * . Redistributions in binary form must reproduce the above copyright notice,
35 * this list of conditions and the following Disclaimer in the documentation
36 * and/or other materials provided with the distribution.
37 *
38 * . Neither the name of Agere Systems Inc. nor the names of the contributors
39 * may be used to endorse or promote products derived from this software
40 * without specific prior written permission.
41 *
42 * Disclaimer
43 *
44 * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
45 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
46 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
47 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
48 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
49 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
50 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
51 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
52 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
54 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
55 * DAMAGE.
56 *
57 */
58
59 #ifndef __ET131X_ADAPTER_H__
60 #define __ET131X_ADAPTER_H__
61
62 #include "et1310_address_map.h"
63 #include "et1310_tx.h"
64 #include "et1310_rx.h"
65
66 /*
67 * Do not change these values: if changed, then change also in respective
68 * TXdma and Rxdma engines
69 */
70 #define NUM_DESC_PER_RING_TX 512 // TX Do not change these values
71 #define NUM_TCB 64
72
73 /*
74 * These values are all superseded by registry entries to facilitate tuning.
75 * Once the desired performance has been achieved, the optimal registry values
76 * should be re-populated to these #defines:
77 */
78 #define NUM_TRAFFIC_CLASSES 1
79
80 /*
81 * There are three ways of counting errors - if there are more than X errors
82 * in Y packets (represented by the "SAMPLE" macros), if there are more than
83 * N errors in a S mSec time period (the "PERIOD" macros), or if there are
84 * consecutive packets with errors (CONSEC_ERRORED_THRESH). This last covers
85 * for "Bursty" errors, and the errored packets may well not be contiguous,
86 * but several errors where the packet counter has changed by less than a
87 * small amount will cause this count to increment.
88 */
89 #define TX_PACKETS_IN_SAMPLE 10000
90 #define TX_MAX_ERRORS_IN_SAMPLE 50
91
92 #define TX_ERROR_PERIOD 1000
93 #define TX_MAX_ERRORS_IN_PERIOD 10
94
95 #define LINK_DETECTION_TIMER 5000
96
97 #define TX_CONSEC_RANGE 5
98 #define TX_CONSEC_ERRORED_THRESH 10
99
100 #define LO_MARK_PERCENT_FOR_PSR 15
101 #define LO_MARK_PERCENT_FOR_RX 15
102
103 /* Macros for flag and ref count operations */
104 #define MP_SET_FLAG(_M, _F) ((_M)->Flags |= (_F))
105 #define MP_CLEAR_FLAG(_M, _F) ((_M)->Flags &= ~(_F))
106 #define MP_CLEAR_FLAGS(_M) ((_M)->Flags = 0)
107 #define MP_TEST_FLAG(_M, _F) (((_M)->Flags & (_F)) != 0)
108 #define MP_TEST_FLAGS(_M, _F) (((_M)->Flags & (_F)) == (_F))
109 #define MP_IS_FLAG_CLEAR(_M, _F) (((_M)->Flags & (_F)) == 0)
110
111 #define MP_INC_RCV_REF(_A) atomic_inc(&(_A)->RcvRefCount)
112 #define MP_DEC_RCV_REF(_A) atomic_dec(&(_A)->RcvRefCount)
113 #define MP_GET_RCV_REF(_A) atomic_read(&(_A)->RcvRefCount)
114
115 /* Macros specific to the private adapter structure */
116 #define MP_TCB_RESOURCES_AVAILABLE(_M) ((_M)->TxRing.nBusySend < NUM_TCB)
117 #define MP_TCB_RESOURCES_NOT_AVAILABLE(_M) ((_M)->TxRing.nBusySend >= NUM_TCB)
118
119 #define MP_SHOULD_FAIL_SEND(_M) ((_M)->Flags & fMP_ADAPTER_FAIL_SEND_MASK)
120 #define MP_IS_NOT_READY(_M) ((_M)->Flags & fMP_ADAPTER_NOT_READY_MASK)
121 #define MP_IS_READY(_M) !((_M)->Flags & fMP_ADAPTER_NOT_READY_MASK)
122
123 #define MP_HAS_CABLE(_M) !((_M)->Flags & fMP_ADAPTER_NO_CABLE)
124 #define MP_LINK_DETECTED(_M) !((_M)->Flags & fMP_ADAPTER_LINK_DETECTION)
125
126 /* Counters for error rate monitoring */
127 typedef struct _MP_ERR_COUNTERS {
128 u32 PktCountTxPackets;
129 u32 PktCountTxErrors;
130 u32 TimerBasedTxErrors;
131 u32 PktCountLastError;
132 u32 ErredConsecPackets;
133 } MP_ERR_COUNTERS, *PMP_ERR_COUNTERS;
134
135 /* RFD (Receive Frame Descriptor) */
136 typedef struct _MP_RFD {
137 struct list_head list_node;
138 struct sk_buff *Packet;
139 u32 PacketSize; // total size of receive frame
140 u16 iBufferIndex;
141 u8 iRingIndex;
142 } MP_RFD, *PMP_RFD;
143
144 /* Enum for Flow Control */
145 typedef enum _eflow_control_t {
146 Both = 0,
147 TxOnly = 1,
148 RxOnly = 2,
149 None = 3
150 } eFLOW_CONTROL_t, *PeFLOW_CONTROL_t;
151
152 /* Struct to define some device statistics */
153 typedef struct _ce_stats_t {
154 /* Link Input/Output stats */
155 uint64_t ipackets; // # of in packets
156 uint64_t opackets; // # of out packets
157
158 /* MIB II variables
159 *
160 * NOTE: atomic_t types are only guaranteed to store 24-bits; if we
161 * MUST have 32, then we'll need another way to perform atomic
162 * operations
163 */
164 u32 unircv; // # multicast packets received
165 atomic_t unixmt; // # multicast packets for Tx
166 u32 multircv; // # multicast packets received
167 atomic_t multixmt; // # multicast packets for Tx
168 u32 brdcstrcv; // # broadcast packets received
169 atomic_t brdcstxmt; // # broadcast packets for Tx
170 u32 norcvbuf; // # Rx packets discarded
171 u32 noxmtbuf; // # Tx packets discarded
172
173 /* Transciever state informations. */
174 u8 xcvr_addr;
175 u32 xcvr_id;
176
177 /* Tx Statistics. */
178 u32 tx_uflo; // Tx Underruns
179
180 u32 collisions;
181 u32 excessive_collisions;
182 u32 first_collision;
183 u32 late_collisions;
184 u32 max_pkt_error;
185 u32 tx_deferred;
186
187 /* Rx Statistics. */
188 u32 rx_ov_flow; // Rx Over Flow
189
190 u32 length_err;
191 u32 alignment_err;
192 u32 crc_err;
193 u32 code_violations;
194 u32 other_errors;
195
196 #ifdef CONFIG_ET131X_DEBUG
197 u32 UnhandledInterruptsPerSec;
198 u32 RxDmaInterruptsPerSec;
199 u32 TxDmaInterruptsPerSec;
200 u32 WatchDogInterruptsPerSec;
201 #endif /* CONFIG_ET131X_DEBUG */
202
203 u32 SynchrounousIterations;
204 INTERRUPT_t InterruptStatus;
205 } CE_STATS_t, *PCE_STATS_t;
206
207 /* The private adapter structure */
208 struct et131x_adapter {
209 struct net_device *netdev;
210 struct pci_dev *pdev;
211
212 struct work_struct task;
213
214 /* Flags that indicate current state of the adapter */
215 u32 Flags;
216 u32 HwErrCount;
217
218 /* Configuration */
219 u8 PermanentAddress[ETH_ALEN];
220 u8 CurrentAddress[ETH_ALEN];
221 bool bOverrideAddress;
222 bool bEepromPresent;
223 u8 eepromData[2];
224
225 /* Spinlocks */
226 spinlock_t Lock;
227
228 spinlock_t TCBSendQLock;
229 spinlock_t TCBReadyQLock;
230 spinlock_t SendHWLock;
231 spinlock_t SendWaitLock;
232
233 spinlock_t RcvLock;
234 spinlock_t RcvPendLock;
235 spinlock_t FbrLock;
236
237 spinlock_t PHYLock;
238
239 /* Packet Filter and look ahead size */
240 u32 PacketFilter;
241 u32 ulLookAhead;
242 u32 uiLinkSpeed;
243 u32 uiDuplexMode;
244 u32 uiAutoNegStatus;
245 u8 ucLinkStatus;
246
247 /* multicast list */
248 u32 MCAddressCount;
249 u8 MCList[NIC_MAX_MCAST_LIST][ETH_ALEN];
250
251 /* MAC test */
252 TXMAC_TXTEST_t TxMacTest;
253
254 /* Pointer to the device's PCI register space */
255 ADDRESS_MAP_t __iomem *CSRAddress;
256
257 /* PCI config space info, for debug purposes only. */
258 u8 RevisionID;
259 u16 VendorID;
260 u16 DeviceID;
261 u16 SubVendorID;
262 u16 SubSystemID;
263 u32 CacheFillSize;
264 u16 PciXDevCtl;
265 u8 pci_lat_timer;
266 u8 pci_hdr_type;
267 u8 pci_bist;
268 u32 pci_cfg_state[64 / sizeof(u32)];
269
270 /* Registry parameters */
271 u8 SpeedDuplex; // speed/duplex
272 eFLOW_CONTROL_t RegistryFlowControl; // for 802.3x flow control
273 u8 RegistryWOLMatch; // Enable WOL pattern-matching
274 u8 RegistryWOLLink; // Link state change is independant
275 u8 RegistryPhyComa; // Phy Coma mode enable/disable
276
277 u32 RegistryRxMemEnd; // Size of internal rx memory
278 u8 RegistryMACStat; // If set, read MACSTAT, else don't
279 u32 RegistryVlanTag; // 802.1q Vlan TAG
280 u32 RegistryJumboPacket; // Max supported ethernet packet size
281
282 u32 RegistryTxNumBuffers;
283 u32 RegistryTxTimeInterval;
284
285 u32 RegistryRxNumBuffers;
286 u32 RegistryRxTimeInterval;
287
288 /* Validation helpers */
289 u8 RegistryPMWOL;
290 u8 RegistryNMIDisable;
291 u32 RegistryDMACache;
292 u32 RegistrySCGain;
293 u8 RegistryPhyLoopbk; // Enable Phy loopback
294
295 /* Derived from the registry: */
296 u8 AiForceDpx; // duplex setting
297 u16 AiForceSpeed; // 'Speed', user over-ride of line speed
298 eFLOW_CONTROL_t FlowControl; // flow control validated by the far-end
299 enum {
300 NETIF_STATUS_INVALID = 0,
301 NETIF_STATUS_MEDIA_CONNECT,
302 NETIF_STATUS_MEDIA_DISCONNECT,
303 NETIF_STATUS_MAX
304 } MediaState;
305 u8 DriverNoPhyAccess;
306
307 /* Minimize init-time */
308 bool bQueryPending;
309 bool bSetPending;
310 bool bResetPending;
311 struct timer_list ErrorTimer;
312 bool bLinkTimerActive;
313 MP_POWER_MGMT PoMgmt;
314 INTERRUPT_t CachedMaskValue;
315
316 atomic_t RcvRefCount; // Num packets not yet returned
317
318 /* Xcvr status at last poll */
319 MI_BMSR_t Bmsr;
320
321 /* Tx Memory Variables */
322 TX_RING_t TxRing;
323
324 /* Rx Memory Variables */
325 RX_RING_t RxRing;
326
327 /* ET1310 register Access */
328 JAGCORE_ACCESS_REGS JagCoreRegs;
329 PCI_CFG_SPACE_REGS PciCfgRegs;
330
331 /* Loopback specifics */
332 u8 ReplicaPhyLoopbk; // Replica Enable
333 u8 ReplicaPhyLoopbkPF; // Replica Enable Pass/Fail
334
335 /* Stats */
336 CE_STATS_t Stats;
337
338 struct net_device_stats net_stats;
339 struct net_device_stats net_stats_prev;
340 };
341
342 #define MPSendPacketsHandler MPSendPackets
343 #define MP_FREE_SEND_PACKET_FUN(Adapter, pMpTcb) \
344 et131x_free_send_packet(Adapter, pMpTcb)
345 #define MpSendPacketFun(Adapter, Packet) MpSendPacket(Adapter, Packet)
346
347 #endif /* __ET131X_ADAPTER_H__ */