Add ET131x ethernet driver.
[people/pmueller/ipfire-2.x.git] / src / et131x / et131x_initpci.c
1 /*
2 * Agere Systems Inc.
3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
4 *
5 * Copyright © 2005 Agere Systems Inc.
6 * All rights reserved.
7 * http://www.agere.com
8 *
9 *------------------------------------------------------------------------------
10 *
11 * et131x_initpci.c - Routines and data used to register the driver with the
12 * PCI (and PCI Express) subsystem, as well as basic driver
13 * init and startup.
14 *
15 *------------------------------------------------------------------------------
16 *
17 * SOFTWARE LICENSE
18 *
19 * This software is provided subject to the following terms and conditions,
20 * which you should read carefully before using the software. Using this
21 * software indicates your acceptance of these terms and conditions. If you do
22 * not agree with these terms and conditions, do not use the software.
23 *
24 * Copyright © 2005 Agere Systems Inc.
25 * All rights reserved.
26 *
27 * Redistribution and use in source or binary forms, with or without
28 * modifications, are permitted provided that the following conditions are met:
29 *
30 * . Redistributions of source code must retain the above copyright notice, this
31 * list of conditions and the following Disclaimer as comments in the code as
32 * well as in the documentation and/or other materials provided with the
33 * distribution.
34 *
35 * . Redistributions in binary form must reproduce the above copyright notice,
36 * this list of conditions and the following Disclaimer in the documentation
37 * and/or other materials provided with the distribution.
38 *
39 * . Neither the name of Agere Systems Inc. nor the names of the contributors
40 * may be used to endorse or promote products derived from this software
41 * without specific prior written permission.
42 *
43 * Disclaimer
44 *
45 * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
46 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
47 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
48 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
49 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
50 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
51 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
52 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
53 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
55 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
56 * DAMAGE.
57 *
58 */
59
60 #include "et131x_version.h"
61 #include "et131x_debug.h"
62 #include "et131x_defs.h"
63
64 #include <linux/pci.h>
65 #include <linux/init.h>
66 #include <linux/module.h>
67 #include <linux/types.h>
68 #include <linux/kernel.h>
69
70 #include <linux/sched.h>
71 #include <linux/ptrace.h>
72 #include <linux/slab.h>
73 #include <linux/ctype.h>
74 #include <linux/string.h>
75 #include <linux/timer.h>
76 #include <linux/interrupt.h>
77 #include <linux/in.h>
78 #include <linux/delay.h>
79 #include <asm/io.h>
80 #include <asm/system.h>
81 #include <asm/bitops.h>
82
83 #include <linux/netdevice.h>
84 #include <linux/etherdevice.h>
85 #include <linux/skbuff.h>
86 #include <linux/if_arp.h>
87 #include <linux/ioport.h>
88 #include <linux/random.h>
89
90 #include "et1310_phy.h"
91 #include "et1310_pm.h"
92 #include "et1310_jagcore.h"
93
94 #include "et131x_adapter.h"
95 #include "et131x_netdev.h"
96 #include "et131x_config.h"
97 #include "et131x_isr.h"
98
99 #include "et1310_address_map.h"
100 #include "et1310_jagcore.h"
101 #include "et1310_tx.h"
102 #include "et1310_rx.h"
103 #include "et1310_mac.h"
104 #include "et1310_eeprom.h"
105
106
107 int __devinit et131x_pci_setup(struct pci_dev *pdev,
108 const struct pci_device_id *ent);
109 void __devexit et131x_pci_remove(struct pci_dev *pdev);
110
111
112 /* Modinfo parameters (filled out using defines from et131x_version.h) */
113 MODULE_AUTHOR(DRIVER_AUTHOR);
114 MODULE_DESCRIPTION(DRIVER_INFO);
115 MODULE_LICENSE(DRIVER_LICENSE);
116
117 /* Module Parameters and related data for debugging facilities */
118 #ifdef CONFIG_ET131X_DEBUG
119 static u32 et131x_debug_level = DBG_LVL;
120 static u32 et131x_debug_flags = DBG_DEFAULTS;
121
122 /*
123 et131x_debug_level :
124 Level of debugging desired (0-7)
125 7 : DBG_RX_ON | DBG_TX_ON
126 6 : DBG_PARAM_ON
127 5 : DBG_VERBOSE_ON
128 4 : DBG_TRACE_ON
129 3 : DBG_NOTICE_ON
130 2 : no debug info
131 1 : no debug info
132 0 : no debug info
133 */
134
135 module_param(et131x_debug_level, uint, 0);
136 module_param(et131x_debug_flags, uint, 0);
137
138 MODULE_PARM_DESC(et131x_debug_level, "Level of debugging desired (0-7)");
139
140 static dbg_info_t et131x_info = { DRIVER_NAME_EXT, 0, 0 };
141 dbg_info_t *et131x_dbginfo = &et131x_info;
142 #endif /* CONFIG_ET131X_DEBUG */
143
144 static struct pci_device_id et131x_pci_table[] __devinitdata = {
145 {ET131X_PCI_VENDOR_ID, ET131X_PCI_DEVICE_ID_GIG, PCI_ANY_ID,
146 PCI_ANY_ID, 0, 0, 0UL},
147 {ET131X_PCI_VENDOR_ID, ET131X_PCI_DEVICE_ID_FAST, PCI_ANY_ID,
148 PCI_ANY_ID, 0, 0, 0UL},
149 {0,}
150 };
151
152 MODULE_DEVICE_TABLE(pci, et131x_pci_table);
153
154 static struct pci_driver et131x_driver = {
155 .name = DRIVER_NAME,
156 .id_table = et131x_pci_table,
157 .probe = et131x_pci_setup,
158 .remove = __devexit_p(et131x_pci_remove),
159 .suspend = NULL, //et131x_pci_suspend,
160 .resume = NULL, //et131x_pci_resume,
161 };
162
163
164 /**
165 * et131x_init_module - The "main" entry point called on driver initialization
166 *
167 * Returns 0 on success, errno on failure (as defined in errno.h)
168 */
169 int et131x_init_module(void)
170 {
171 int result;
172
173 #ifdef CONFIG_ET131X_DEBUG
174 /* Set the level of debug messages displayed using the module
175 * parameter
176 */
177 et131x_dbginfo->dbgFlags = et131x_debug_flags;
178
179 switch (et131x_debug_level) {
180 case 7:
181 et131x_dbginfo->dbgFlags |= (DBG_RX_ON | DBG_TX_ON);
182
183 case 6:
184 et131x_dbginfo->dbgFlags |= DBG_PARAM_ON;
185
186 case 5:
187 et131x_dbginfo->dbgFlags |= DBG_VERBOSE_ON;
188
189 case 4:
190 et131x_dbginfo->dbgFlags |= DBG_TRACE_ON;
191
192 case 3:
193 et131x_dbginfo->dbgFlags |= DBG_NOTICE_ON;
194
195 case 2:
196 case 1:
197 case 0:
198 default:
199 break;
200 }
201 #endif /* CONFIG_ET131X_DEBUG */
202
203 DBG_ENTER(et131x_dbginfo);
204 DBG_PRINT("%s\n", DRIVER_INFO);
205
206 result = pci_register_driver(&et131x_driver);
207
208 DBG_LEAVE(et131x_dbginfo);
209 return result;
210 }
211
212 /**
213 * et131x_cleanup_module - The entry point called on driver cleanup
214 */
215 void et131x_cleanup_module(void)
216 {
217 DBG_ENTER(et131x_dbginfo);
218
219 pci_unregister_driver(&et131x_driver);
220
221 DBG_LEAVE(et131x_dbginfo);
222 }
223
224 /*
225 * These macros map the driver-specific init_module() and cleanup_module()
226 * routines so they can be called by the kernel.
227 */
228 module_init(et131x_init_module);
229 module_exit(et131x_cleanup_module);
230
231
232 /**
233 * et131x_find_adapter - Find the adapter and get all the assigned resources
234 * @adapter: pointer to our private adapter structure
235 *
236 * Returns 0 on success, errno on failure (as defined in errno.h)
237 */
238 int et131x_find_adapter(struct et131x_adapter *adapter, struct pci_dev *pdev)
239 {
240 int result;
241 uint8_t eepromStat;
242 uint8_t maxPayload = 0;
243 uint8_t read_size_reg;
244
245 DBG_ENTER(et131x_dbginfo);
246
247 /* Allow disabling of Non-Maskable Interrupts in I/O space, to
248 * support validation.
249 */
250 if (adapter->RegistryNMIDisable) {
251 uint8_t RegisterVal;
252
253 RegisterVal = inb(ET1310_NMI_DISABLE);
254 RegisterVal &= 0xf3;
255
256 if (adapter->RegistryNMIDisable == 2) {
257 RegisterVal |= 0xc;
258 }
259
260 outb(ET1310_NMI_DISABLE, RegisterVal);
261 }
262
263 /* We first need to check the EEPROM Status code located at offset
264 * 0xB2 of config space
265 */
266 result = pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS,
267 &eepromStat);
268
269 /* THIS IS A WORKAROUND:
270 * I need to call this function twice to get my card in a
271 * LG M1 Express Dual running. I tried also a msleep before this
272 * function, because I thougth there could be some time condidions
273 * but it didn't work. Call the whole function twice also work.
274 */
275 result = pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS,
276 &eepromStat);
277 if (result != PCIBIOS_SUCCESSFUL) {
278 DBG_ERROR(et131x_dbginfo, "Could not read PCI config space for "
279 "EEPROM Status\n");
280 DBG_LEAVE(et131x_dbginfo);
281 return -EIO;
282 }
283
284 /* Determine if the error(s) we care about are present. If they are
285 * present, we need to fail.
286 */
287 if (eepromStat & 0x4C) {
288 result = pci_read_config_byte(pdev, PCI_REVISION_ID,
289 &adapter->RevisionID);
290 if (result != PCIBIOS_SUCCESSFUL) {
291 DBG_ERROR(et131x_dbginfo,
292 "Could not read PCI config space for "
293 "Revision ID\n");
294 DBG_LEAVE(et131x_dbginfo);
295 return -EIO;
296 } else if (adapter->RevisionID == 0x01) {
297 int32_t nLoop;
298 uint8_t ucTemp[4] = { 0xFE, 0x13, 0x10, 0xFF };
299
300 /* Re-write the first 4 bytes if we have an eeprom
301 * present and the revision id is 1, this fixes the
302 * corruption seen with 1310 B Silicon
303 */
304 for (nLoop = 0; nLoop < 3; nLoop++) {
305 EepromWriteByte(adapter, nLoop, ucTemp[nLoop],
306 0, SINGLE_BYTE);
307 }
308 }
309
310 DBG_ERROR(et131x_dbginfo,
311 "Fatal EEPROM Status Error - 0x%04x\n", eepromStat);
312
313 /* This error could mean that there was an error reading the
314 * eeprom or that the eeprom doesn't exist. We will treat
315 * each case the same and not try to gather additional
316 * information that normally would come from the eeprom, like
317 * MAC Address
318 */
319 adapter->bEepromPresent = false;
320
321 DBG_LEAVE(et131x_dbginfo);
322 return -EIO;
323 } else {
324 DBG_TRACE(et131x_dbginfo, "EEPROM Status Code - 0x%04x\n",
325 eepromStat);
326 adapter->bEepromPresent = true;
327 }
328
329 /* Read the EEPROM for information regarding LED behavior. Refer to
330 * ET1310_phy.c, et131x_xcvr_init(), for its use.
331 */
332 EepromReadByte(adapter, 0x70, &adapter->eepromData[0], 0, SINGLE_BYTE);
333 EepromReadByte(adapter, 0x71, &adapter->eepromData[1], 0, SINGLE_BYTE);
334
335 if (adapter->eepromData[0] != 0xcd) {
336 adapter->eepromData[1] = 0x00; // Disable all optional features
337 }
338
339 /* Let's set up the PORT LOGIC Register. First we need to know what
340 * the max_payload_size is
341 */
342 result = pci_read_config_byte(pdev, ET1310_PCI_MAX_PYLD, &maxPayload);
343 if (result != PCIBIOS_SUCCESSFUL) {
344 DBG_ERROR(et131x_dbginfo, "Could not read PCI config space for "
345 "Max Payload Size\n");
346 DBG_LEAVE(et131x_dbginfo);
347 return -EIO;
348 }
349
350 /* Program the Ack/Nak latency and replay timers */
351 maxPayload &= 0x07; // Only the lower 3 bits are valid
352
353 if (maxPayload < 2) {
354 const uint16_t AckNak[2] = { 0x76, 0xD0 };
355 const uint16_t Replay[2] = { 0x1E0, 0x2ED };
356
357 result = pci_write_config_word(pdev, ET1310_PCI_ACK_NACK,
358 AckNak[maxPayload]);
359 if (result != PCIBIOS_SUCCESSFUL) {
360 DBG_ERROR(et131x_dbginfo,
361 "Could not write PCI config space "
362 "for ACK/NAK\n");
363 DBG_LEAVE(et131x_dbginfo);
364 return -EIO;
365 }
366
367 result = pci_write_config_word(pdev, ET1310_PCI_REPLAY,
368 Replay[maxPayload]);
369 if (result != PCIBIOS_SUCCESSFUL) {
370 DBG_ERROR(et131x_dbginfo,
371 "Could not write PCI config space "
372 "for Replay Timer\n");
373 DBG_LEAVE(et131x_dbginfo);
374 return -EIO;
375 }
376 }
377
378 /* l0s and l1 latency timers. We are using default values.
379 * Representing 001 for L0s and 010 for L1
380 */
381 result = pci_write_config_byte(pdev, ET1310_PCI_L0L1LATENCY, 0x11);
382 if (result != PCIBIOS_SUCCESSFUL) {
383 DBG_ERROR(et131x_dbginfo,
384 "Could not write PCI config space for "
385 "Latency Timers\n");
386 DBG_LEAVE(et131x_dbginfo);
387 return -EIO;
388 }
389
390 /* Change the max read size to 2k */
391 result = pci_read_config_byte(pdev, 0x51, &read_size_reg);
392 if (result != PCIBIOS_SUCCESSFUL) {
393 DBG_ERROR(et131x_dbginfo,
394 "Could not read PCI config space for Max read size\n");
395 DBG_LEAVE(et131x_dbginfo);
396 return -EIO;
397 }
398
399 read_size_reg &= 0x8f;
400 read_size_reg |= 0x40;
401
402 result = pci_write_config_byte(pdev, 0x51, read_size_reg);
403 if (result != PCIBIOS_SUCCESSFUL) {
404 DBG_ERROR(et131x_dbginfo,
405 "Could not write PCI config space for Max read size\n");
406 DBG_LEAVE(et131x_dbginfo);
407 return -EIO;
408 }
409
410 /* PCI Express Configuration registers 0x48-0x5B (Device Control) */
411 result = pci_read_config_word(pdev, ET1310_PCI_DEV_CTRL,
412 &adapter->PciXDevCtl);
413 if (result != PCIBIOS_SUCCESSFUL) {
414 DBG_ERROR(et131x_dbginfo,
415 "Could not read PCI config space for PCI Express Dev Ctl\n");
416 DBG_LEAVE(et131x_dbginfo);
417 return -EIO;
418 }
419
420 /* Get MAC address from config space if an eeprom exists, otherwise
421 * the MAC address there will not be valid
422 */
423 if (adapter->bEepromPresent) {
424 int i;
425
426 for (i = 0; i < ETH_ALEN; i++) {
427 result = pci_read_config_byte(
428 pdev, ET1310_PCI_MAC_ADDRESS + i,
429 adapter->PermanentAddress + i);
430 if (result != PCIBIOS_SUCCESSFUL) {
431 DBG_ERROR(et131x_dbginfo,
432 "Could not read PCI config space for MAC address\n");
433 DBG_LEAVE(et131x_dbginfo);
434 return -EIO;
435 }
436 }
437 }
438
439 DBG_LEAVE(et131x_dbginfo);
440 return 0;
441 }
442
443 /**
444 * et131x_error_timer_handler
445 * @data: timer-specific variable; here a pointer to our adapter structure
446 *
447 * The routine called when the error timer expires, to track the number of
448 * recurring errors.
449 */
450 void et131x_error_timer_handler(unsigned long data)
451 {
452 struct et131x_adapter *pAdapter = (struct et131x_adapter *) data;
453 PM_CSR_t pm_csr;
454
455 pm_csr.value = readl(&pAdapter->CSRAddress->global.pm_csr.value);
456
457 if (pm_csr.bits.pm_phy_sw_coma == 0) {
458 if (pAdapter->RegistryMACStat) {
459 UpdateMacStatHostCounters(pAdapter);
460 }
461 } else {
462 DBG_VERBOSE(et131x_dbginfo,
463 "No interrupts, in PHY coma, pm_csr = 0x%x\n",
464 pm_csr.value);
465 }
466
467 if (!pAdapter->Bmsr.bits.link_status &&
468 pAdapter->RegistryPhyComa &&
469 pAdapter->PoMgmt.TransPhyComaModeOnBoot < 11) {
470 pAdapter->PoMgmt.TransPhyComaModeOnBoot++;
471 }
472
473 if (pAdapter->PoMgmt.TransPhyComaModeOnBoot == 10) {
474 if (!pAdapter->Bmsr.bits.link_status
475 && pAdapter->RegistryPhyComa) {
476 if (pm_csr.bits.pm_phy_sw_coma == 0) {
477 // NOTE - This was originally a 'sync with interrupt'. How
478 // to do that under Linux?
479 et131x_enable_interrupts(pAdapter);
480 EnablePhyComa(pAdapter);
481 }
482 }
483 }
484
485 /* This is a periodic timer, so reschedule */
486 mod_timer(&pAdapter->ErrorTimer, jiffies +
487 TX_ERROR_PERIOD * HZ / 1000);
488 }
489
490 /**
491 * et131x_link_detection_handler
492 *
493 * Timer function for link up at driver load time
494 */
495 void et131x_link_detection_handler(unsigned long data)
496 {
497 struct et131x_adapter *pAdapter = (struct et131x_adapter *) data;
498 unsigned long lockflags;
499
500 /* Let everyone know that we have run */
501 pAdapter->bLinkTimerActive = false;
502
503 if (pAdapter->MediaState == 0) {
504 spin_lock_irqsave(&pAdapter->Lock, lockflags);
505
506 pAdapter->MediaState = NETIF_STATUS_MEDIA_DISCONNECT;
507 MP_CLEAR_FLAG(pAdapter, fMP_ADAPTER_LINK_DETECTION);
508
509 spin_unlock_irqrestore(&pAdapter->Lock, lockflags);
510
511 netif_carrier_off(pAdapter->netdev);
512
513 pAdapter->bSetPending = false;
514 }
515 }
516
517 /**
518 * et131x_adapter_setup - Set the adapter up as per cassini+ documentation
519 * @adapter: pointer to our private adapter structure
520 *
521 * Returns 0 on success, errno on failure (as defined in errno.h)
522 */
523 int et131x_adapter_setup(struct et131x_adapter *pAdapter)
524 {
525 int status = 0;
526
527 DBG_ENTER(et131x_dbginfo);
528
529 /* Configure the JAGCore */
530 ConfigGlobalRegs(pAdapter);
531
532 ConfigMACRegs1(pAdapter);
533 ConfigMMCRegs(pAdapter);
534
535 ConfigRxMacRegs(pAdapter);
536 ConfigTxMacRegs(pAdapter);
537
538 ConfigRxDmaRegs(pAdapter);
539 ConfigTxDmaRegs(pAdapter);
540
541 ConfigMacStatRegs(pAdapter);
542
543 /* Move the following code to Timer function?? */
544 status = et131x_xcvr_find(pAdapter);
545
546 if (status != 0) {
547 DBG_WARNING(et131x_dbginfo, "Could not find the xcvr\n");
548 }
549
550 /* Prepare the TRUEPHY library. */
551 ET1310_PhyInit(pAdapter);
552
553 /* Reset the phy now so changes take place */
554 ET1310_PhyReset(pAdapter);
555
556 /* Power down PHY */
557 ET1310_PhyPowerDown(pAdapter, 1);
558
559 /*
560 * We need to turn off 1000 base half dulplex, the mac does not
561 * support it. For the 10/100 part, turn off all gig advertisement
562 */
563 if (pAdapter->DeviceID != ET131X_PCI_DEVICE_ID_FAST) {
564 ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_FULL);
565 } else {
566 ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
567 }
568
569 /* Power up PHY */
570 ET1310_PhyPowerDown(pAdapter, 0);
571
572 et131x_setphy_normal(pAdapter);
573
574 DBG_LEAVE(et131x_dbginfo);
575 return status;
576 }
577
578 /**
579 * et131x_setup_hardware_properties - set up the MAC Address on the ET1310
580 * @adapter: pointer to our private adapter structure
581 */
582 void et131x_setup_hardware_properties(struct et131x_adapter *adapter)
583 {
584 DBG_ENTER(et131x_dbginfo);
585
586 /* If have our default mac from registry and no mac address from
587 * EEPROM then we need to generate the last octet and set it on the
588 * device
589 */
590 if (!adapter->bOverrideAddress) {
591 if (adapter->PermanentAddress[0] == 0x00 &&
592 adapter->PermanentAddress[1] == 0x00 &&
593 adapter->PermanentAddress[2] == 0x00 &&
594 adapter->PermanentAddress[3] == 0x00 &&
595 adapter->PermanentAddress[4] == 0x00 &&
596 adapter->PermanentAddress[5] == 0x00) {
597 /*
598 * We need to randomly generate the last octet so we
599 * decrease our chances of setting the mac address to
600 * same as another one of our cards in the system
601 */
602 get_random_bytes(&adapter->CurrentAddress[5], 1);
603
604 /*
605 * We have the default value in the register we are
606 * working with so we need to copy the current
607 * address into the permanent address
608 */
609 memcpy(adapter->PermanentAddress,
610 adapter->CurrentAddress, ETH_ALEN);
611 } else {
612 /* We do not have an override address, so set the
613 * current address to the permanent address and add
614 * it to the device
615 */
616 memcpy(adapter->CurrentAddress,
617 adapter->PermanentAddress, ETH_ALEN);
618 }
619 }
620
621 DBG_LEAVE(et131x_dbginfo);
622 }
623
624 /**
625 * et131x_soft_reset - Issue a soft reset to the hardware, complete for ET1310
626 * @adapter: pointer to our private adapter structure
627 */
628 void et131x_soft_reset(struct et131x_adapter *adapter)
629 {
630 DBG_ENTER(et131x_dbginfo);
631
632 /* Disable MAC Core */
633 writel(0xc00f0000, &adapter->CSRAddress->mac.cfg1.value);
634
635 /* Set everything to a reset value */
636 writel(0x7F, &adapter->CSRAddress->global.sw_reset.value);
637 writel(0x000f0000, &adapter->CSRAddress->mac.cfg1.value);
638 writel(0x00000000, &adapter->CSRAddress->mac.cfg1.value);
639
640 DBG_LEAVE(et131x_dbginfo);
641 }
642
643 /**
644 * et131x_align_allocated_memory - Align allocated memory on a given boundary
645 * @adapter: pointer to our adapter structure
646 * @phys_addr: pointer to Physical address
647 * @offset: pointer to the offset variable
648 * @mask: correct mask
649 */
650 void et131x_align_allocated_memory(struct et131x_adapter *adapter,
651 uint64_t *phys_addr,
652 uint64_t *offset, uint64_t mask)
653 {
654 uint64_t new_addr;
655
656 DBG_ENTER(et131x_dbginfo);
657
658 *offset = 0;
659
660 new_addr = *phys_addr & ~mask;
661
662 if (new_addr != *phys_addr) {
663 /* Move to next aligned block */
664 new_addr += mask + 1;
665 /* Return offset for adjusting virt addr */
666 *offset = new_addr - *phys_addr;
667 /* Return new physical address */
668 *phys_addr = new_addr;
669 }
670
671 DBG_LEAVE(et131x_dbginfo);
672 }
673
674 /**
675 * et131x_adapter_memory_alloc
676 * @adapter: pointer to our private adapter structure
677 *
678 * Returns 0 on success, errno on failure (as defined in errno.h).
679 *
680 * Allocate all the memory blocks for send, receive and others.
681 */
682 int et131x_adapter_memory_alloc(struct et131x_adapter *adapter)
683 {
684 int status = 0;
685
686 DBG_ENTER(et131x_dbginfo);
687
688 do {
689 /* Allocate memory for the Tx Ring */
690 status = et131x_tx_dma_memory_alloc(adapter);
691 if (status != 0) {
692 DBG_ERROR(et131x_dbginfo,
693 "et131x_tx_dma_memory_alloc FAILED\n");
694 break;
695 }
696
697 /* Receive buffer memory allocation */
698 status = et131x_rx_dma_memory_alloc(adapter);
699 if (status != 0) {
700 DBG_ERROR(et131x_dbginfo,
701 "et131x_rx_dma_memory_alloc FAILED\n");
702 et131x_tx_dma_memory_free(adapter);
703 break;
704 }
705
706 /* Init receive data structures */
707 status = et131x_init_recv(adapter);
708 if (status != 0) {
709 DBG_ERROR(et131x_dbginfo, "et131x_init_recv FAILED\n");
710 et131x_tx_dma_memory_free(adapter);
711 et131x_rx_dma_memory_free(adapter);
712 break;
713 }
714 } while (0);
715
716 DBG_LEAVE(et131x_dbginfo);
717 return status;
718 }
719
720 /**
721 * et131x_adapter_memory_free - Free all memory allocated for use by Tx & Rx
722 * @adapter: pointer to our private adapter structure
723 */
724 void et131x_adapter_memory_free(struct et131x_adapter *adapter)
725 {
726 DBG_ENTER(et131x_dbginfo);
727
728 /* Free DMA memory */
729 et131x_tx_dma_memory_free(adapter);
730 et131x_rx_dma_memory_free(adapter);
731
732 DBG_LEAVE(et131x_dbginfo);
733 }
734
735 /**
736 * et131x_pci_remove
737 * @pdev: a pointer to the device's pci_dev structure
738 *
739 * Registered in the pci_driver structure, this function is called when the
740 * PCI subsystem detects that a PCI device which matches the information
741 * contained in the pci_device_id table has been removed.
742 */
743 void __devexit et131x_pci_remove(struct pci_dev *pdev)
744 {
745 struct net_device *netdev;
746 struct et131x_adapter *adapter;
747
748 DBG_ENTER(et131x_dbginfo);
749
750 /* Retrieve the net_device pointer from the pci_dev struct, as well
751 * as the private adapter struct
752 */
753 netdev = (struct net_device *) pci_get_drvdata(pdev);
754 adapter = netdev_priv(netdev);
755
756 /* Perform device cleanup */
757 unregister_netdev(netdev);
758 et131x_adapter_memory_free(adapter);
759 iounmap(adapter->CSRAddress);
760 free_netdev(netdev);
761 pci_release_regions(pdev);
762 pci_disable_device(pdev);
763
764 DBG_LEAVE(et131x_dbginfo);
765 }
766
767 /**
768 * et131x_pci_setup - Perform device initialization
769 * @pdev: a pointer to the device's pci_dev structure
770 * @ent: this device's entry in the pci_device_id table
771 *
772 * Returns 0 on success, errno on failure (as defined in errno.h)
773 *
774 * Registered in the pci_driver structure, this function is called when the
775 * PCI subsystem finds a new PCI device which matches the information
776 * contained in the pci_device_id table. This routine is the equivalent to
777 * a device insertion routine.
778 */
779 int __devinit et131x_pci_setup(struct pci_dev *pdev,
780 const struct pci_device_id *ent)
781 {
782 int result = 0;
783 int pm_cap;
784 bool pci_using_dac;
785 struct net_device *netdev = NULL;
786 struct et131x_adapter *adapter = NULL;
787
788 DBG_ENTER(et131x_dbginfo);
789
790 /* Enable the device via the PCI subsystem */
791 result = pci_enable_device(pdev);
792 if (result != 0) {
793 DBG_ERROR(et131x_dbginfo, "pci_enable_device() failed\n");
794 goto out;
795 }
796
797 /* Perform some basic PCI checks */
798 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
799 DBG_ERROR(et131x_dbginfo,
800 "Can't find PCI device's base address\n");
801 result = -ENODEV;
802 goto out;
803 }
804
805 result = pci_request_regions(pdev, DRIVER_NAME);
806 if (result != 0) {
807 DBG_ERROR(et131x_dbginfo, "Can't get PCI resources\n");
808 goto err_disable;
809 }
810
811 /* Enable PCI bus mastering */
812 DBG_TRACE(et131x_dbginfo, "Setting PCI Bus Mastering...\n");
813 pci_set_master(pdev);
814
815 /* Query PCI for Power Mgmt Capabilities
816 *
817 * NOTE: Now reading PowerMgmt in another location; is this still
818 * needed?
819 */
820 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
821 if (pm_cap == 0) {
822 DBG_ERROR(et131x_dbginfo,
823 "Cannot find Power Management capabilities\n");
824 result = -EIO;
825 goto err_release_res;
826 }
827
828 /* Check the DMA addressing support of this device */
829 if (!pci_set_dma_mask(pdev, 0xffffffffffffffffULL)) {
830 DBG_TRACE(et131x_dbginfo, "64-bit DMA addressing supported\n");
831 pci_using_dac = true;
832
833 result =
834 pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL);
835 if (result != 0) {
836 DBG_ERROR(et131x_dbginfo,
837 "Unable to obtain 64 bit DMA for consistent allocations\n");
838 goto err_release_res;
839 }
840 } else if (!pci_set_dma_mask(pdev, 0xffffffffULL)) {
841 DBG_TRACE(et131x_dbginfo,
842 "64-bit DMA addressing NOT supported\n");
843 DBG_TRACE(et131x_dbginfo,
844 "32-bit DMA addressing will be used\n");
845 pci_using_dac = false;
846 } else {
847 DBG_ERROR(et131x_dbginfo, "No usable DMA addressing method\n");
848 result = -EIO;
849 goto err_release_res;
850 }
851
852 /* Allocate netdev and private adapter structs */
853 DBG_TRACE(et131x_dbginfo,
854 "Allocate netdev and private adapter structs...\n");
855 netdev = et131x_device_alloc();
856 if (netdev == NULL) {
857 DBG_ERROR(et131x_dbginfo, "Couldn't alloc netdev struct\n");
858 result = -ENOMEM;
859 goto err_release_res;
860 }
861
862 /* Setup the fundamental net_device and private adapter structure elements */
863 DBG_TRACE(et131x_dbginfo, "Setting fundamental net_device info...\n");
864 SET_NETDEV_DEV(netdev, &pdev->dev);
865 if (pci_using_dac) {
866 //netdev->features |= NETIF_F_HIGHDMA;
867 }
868
869 /*
870 * NOTE - Turn this on when we're ready to deal with SG-DMA
871 *
872 * NOTE: According to "Linux Device Drivers", 3rd ed, Rubini et al,
873 * if checksumming is not performed in HW, then the kernel will not
874 * use SG.
875 * From pp 510-511:
876 *
877 * "Note that the kernel does not perform scatter/gather I/O to your
878 * device if it does not also provide some form of checksumming as
879 * well. The reason is that, if the kernel has to make a pass over a
880 * fragmented ("nonlinear") packet to calculate the checksum, it
881 * might as well copy the data and coalesce the packet at the same
882 * time."
883 *
884 * This has been verified by setting the flags below and still not
885 * receiving a scattered buffer from the network stack, so leave it
886 * off until checksums are calculated in HW.
887 */
888 //netdev->features |= NETIF_F_SG;
889 //netdev->features |= NETIF_F_NO_CSUM;
890 //netdev->features |= NETIF_F_LLTX;
891
892 /* Allocate private adapter struct and copy in relevant information */
893 adapter = netdev_priv(netdev);
894 adapter->pdev = pdev;
895 adapter->netdev = netdev;
896 adapter->VendorID = pdev->vendor;
897 adapter->DeviceID = pdev->device;
898
899 /* Do the same for the netdev struct */
900 netdev->irq = pdev->irq;
901 netdev->base_addr = pdev->resource[0].start;
902
903 /* Initialize spinlocks here */
904 DBG_TRACE(et131x_dbginfo, "Initialize spinlocks...\n");
905
906 spin_lock_init(&adapter->Lock);
907 spin_lock_init(&adapter->TCBSendQLock);
908 spin_lock_init(&adapter->TCBReadyQLock);
909 spin_lock_init(&adapter->SendHWLock);
910 spin_lock_init(&adapter->SendWaitLock);
911 spin_lock_init(&adapter->RcvLock);
912 spin_lock_init(&adapter->RcvPendLock);
913 spin_lock_init(&adapter->FbrLock);
914 spin_lock_init(&adapter->PHYLock);
915
916 /* Parse configuration parameters into the private adapter struct */
917 et131x_config_parse(adapter);
918
919 /* Find the physical adapter
920 *
921 * NOTE: This is the equivalent of the MpFindAdapter() routine; can we
922 * lump it's init with the device specific init below into a
923 * single init function?
924 */
925 //while (et131x_find_adapter(adapter, pdev) != 0);
926 et131x_find_adapter(adapter, pdev);
927
928 /* Map the bus-relative registers to system virtual memory */
929 DBG_TRACE(et131x_dbginfo,
930 "Mapping bus-relative registers to virtual memory...\n");
931
932 adapter->CSRAddress = ioremap_nocache(pci_resource_start(pdev, 0),
933 pci_resource_len(pdev, 0));
934 if (adapter->CSRAddress == NULL) {
935 DBG_ERROR(et131x_dbginfo, "Cannot map device registers\n");
936 result = -ENOMEM;
937 goto err_free_dev;
938 }
939
940 /* Perform device-specific initialization here (See code below) */
941
942 /* If Phy COMA mode was enabled when we went down, disable it here. */
943 {
944 PM_CSR_t GlobalPmCSR = { 0 };
945
946 GlobalPmCSR.bits.pm_sysclk_gate = 1;
947 GlobalPmCSR.bits.pm_txclk_gate = 1;
948 GlobalPmCSR.bits.pm_rxclk_gate = 1;
949 writel(GlobalPmCSR.value,
950 &adapter->CSRAddress->global.pm_csr.value);
951 }
952
953 /* Issue a global reset to the et1310 */
954 DBG_TRACE(et131x_dbginfo, "Issuing soft reset...\n");
955 et131x_soft_reset(adapter);
956
957 /* Disable all interrupts (paranoid) */
958 DBG_TRACE(et131x_dbginfo, "Disable device interrupts...\n");
959 et131x_disable_interrupts(adapter);
960
961 /* Allocate DMA memory */
962 result = et131x_adapter_memory_alloc(adapter);
963 if (result != 0) {
964 DBG_ERROR(et131x_dbginfo,
965 "Could not alloc adapater memory (DMA)\n");
966 goto err_iounmap;
967 }
968
969 /* Init send data structures */
970 DBG_TRACE(et131x_dbginfo, "Init send data structures...\n");
971 et131x_init_send(adapter);
972
973 adapter->PoMgmt.PowerState = NdisDeviceStateD0;
974
975 /* Register the interrupt
976 *
977 * NOTE - This is being done in the open routine, where most other
978 * Linux drivers setup IRQ handlers. Make sure device
979 * interrupts are not turned on before the IRQ is registered!!
980 *
981 * What we will do here is setup the task structure for the
982 * ISR's deferred handler
983 */
984 INIT_WORK(&adapter->task, et131x_isr_handler);
985
986 /* Determine MAC Address, and copy into the net_device struct */
987 DBG_TRACE(et131x_dbginfo, "Retrieve MAC address...\n");
988 et131x_setup_hardware_properties(adapter);
989
990 memcpy(netdev->dev_addr, adapter->CurrentAddress, ETH_ALEN);
991
992 /* Setup et1310 as per the documentation */
993 DBG_TRACE(et131x_dbginfo, "Setup the adapter...\n");
994 et131x_adapter_setup(adapter);
995
996 /* Create a timer to count errors received by the NIC */
997 init_timer(&adapter->ErrorTimer);
998
999 adapter->ErrorTimer.expires = jiffies + TX_ERROR_PERIOD * HZ / 1000;
1000 adapter->ErrorTimer.function = et131x_error_timer_handler;
1001 adapter->ErrorTimer.data = (unsigned long)adapter;
1002
1003 /* Initialize link state */
1004 et131x_link_detection_handler((unsigned long)adapter);
1005
1006 /* Intialize variable for counting how long we do not have link status */
1007 adapter->PoMgmt.TransPhyComaModeOnBoot = 0;
1008
1009 /* We can enable interrupts now
1010 *
1011 * NOTE - Because registration of interrupt handler is done in the
1012 * device's open(), defer enabling device interrupts to that
1013 * point
1014 */
1015
1016 /* Register the net_device struct with the Linux network layer */
1017 DBG_TRACE(et131x_dbginfo, "Registering net_device...\n");
1018 if ((result = register_netdev(netdev)) != 0) {
1019 DBG_ERROR(et131x_dbginfo, "register_netdev() failed\n");
1020 goto err_mem_free;
1021 }
1022
1023 /* Register the net_device struct with the PCI subsystem. Save a copy
1024 * of the PCI config space for this device now that the device has
1025 * been initialized, just in case it needs to be quickly restored.
1026 */
1027 pci_set_drvdata(pdev, netdev);
1028
1029 pci_save_state(adapter->pdev);
1030
1031 out:
1032 DBG_LEAVE(et131x_dbginfo);
1033 return result;
1034
1035 err_mem_free:
1036 et131x_adapter_memory_free(adapter);
1037 err_iounmap:
1038 iounmap(adapter->CSRAddress);
1039 err_free_dev:
1040 free_netdev(netdev);
1041 err_release_res:
1042 pci_release_regions(pdev);
1043 err_disable:
1044 pci_disable_device(pdev);
1045 goto out;
1046 }