src/patches/suse-2.6.27.25/patches.drivers/e1000e_add_LOM_devices.patch

   1 From: Bruce Allan <bruce.w.allan@intel.com>
   2 Acked-by: Karsten Keil <kkeil@novell.com>
   3 Subject: e1000e: add support for 82567LM-3 and 82567LF-3 (ICH10D)
   4 Reference: fate 303916,303898
   5
   6 Add support for new LOM devices on the latest generation ICHx platforms.
   7 ---
   8
   9  drivers/net/e1000e/defines.h |    2
  10  drivers/net/e1000e/e1000.h   |    3
  11  drivers/net/e1000e/ethtool.c |   22 +++++-
  12  drivers/net/e1000e/hw.h      |    3
  13  drivers/net/e1000e/ich8lan.c |  154 ++++++++++++++++++++++++++++++++++++++++---
  14  drivers/net/e1000e/netdev.c  |   25 ++++++
  15  drivers/net/e1000e/phy.c     |   85 +++++++++++++++++++++++
  16  7 files changed, 280 insertions(+), 14 deletions(-)
  17
  18 --- a/drivers/net/e1000e/defines.h
  19 +++ b/drivers/net/e1000e/defines.h
  20 @@ -518,6 +518,7 @@
  21  #define NWAY_LPAR_ASM_DIR        0x0800 /* LP Asymmetric Pause Direction bit */
  22
  23  /* Autoneg Expansion Register */
  24 +#define NWAY_ER_LP_NWAY_CAPS     0x0001 /* LP has Auto Neg Capability */
  25
  26  /* 1000BASE-T Control Register */
  27  #define CR_1000T_HD_CAPS         0x0100 /* Advertise 1000T HD capability */
  28 @@ -553,6 +554,7 @@
  29  #define E1000_EECD_DO        0x00000008 /* NVM Data Out */
  30  #define E1000_EECD_REQ       0x00000040 /* NVM Access Request */
  31  #define E1000_EECD_GNT       0x00000080 /* NVM Access Grant */
  32 +#define E1000_EECD_PRES      0x00000100 /* NVM Present */
  33  #define E1000_EECD_SIZE      0x00000200 /* NVM Size (0=64 word 1=256 word) */
  34  /* NVM Addressing bits based on type (0-small, 1-large) */
  35  #define E1000_EECD_ADDR_BITS 0x00000400
  36 --- a/drivers/net/e1000e/e1000.h
  37 +++ b/drivers/net/e1000e/e1000.h
  38 @@ -104,6 +104,7 @@ enum e1000_boards {
  39         board_80003es2lan,
  40         board_ich8lan,
  41         board_ich9lan,
  42 +       board_ich10lan,
  43  };
  44
  45  struct e1000_queue_stats {
  46 @@ -400,6 +401,7 @@ extern struct e1000_info e1000_82573_inf
  47  extern struct e1000_info e1000_82574_info;
  48  extern struct e1000_info e1000_ich8_info;
  49  extern struct e1000_info e1000_ich9_info;
  50 +extern struct e1000_info e1000_ich10_info;
  51  extern struct e1000_info e1000_es2_info;
  52
  53  extern s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num);
  54 @@ -473,6 +475,7 @@ extern s32 e1000e_get_cable_length_m88(s
  55  extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
  56  extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
  57  extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
  58 +extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
  59  extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
  60  extern s32 e1000e_determine_phy_address(struct e1000_hw *hw);
  61  extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
  62 --- a/drivers/net/e1000e/ethtool.c
  63 +++ b/drivers/net/e1000e/ethtool.c
  64 @@ -790,6 +790,7 @@ static int e1000_reg_test(struct e1000_a
  65         case e1000_82574:
  66         case e1000_ich8lan:
  67         case e1000_ich9lan:
  68 +       case e1000_ich10lan:
  69                 toggle = 0x7FFFF033;
  70                 break;
  71         default:
  72 @@ -842,7 +843,9 @@ static int e1000_reg_test(struct e1000_a
  73         REG_PATTERN_TEST(E1000_TIDV, 0x0000FFFF, 0x0000FFFF);
  74         for (i = 0; i < mac->rar_entry_count; i++)
  75                 REG_PATTERN_TEST_ARRAY(E1000_RA, ((i << 1) + 1),
  76 -                                      0x8003FFFF, 0xFFFFFFFF);
  77 +                                      ((mac->type == e1000_ich10lan) ?
  78 +                                          0x8007FFFF : 0x8003FFFF),
  79 +                                      0xFFFFFFFF);
  80
  81         for (i = 0; i < mac->mta_reg_count; i++)
  82                 REG_PATTERN_TEST_ARRAY(E1000_MTA, i, 0xFFFFFFFF, 0xFFFFFFFF);
  83 @@ -923,12 +926,23 @@ static int e1000_intr_test(struct e1000_
  84
  85         /* Test each interrupt */
  86         for (i = 0; i < 10; i++) {
  87 -               if ((adapter->flags & FLAG_IS_ICH) && (i == 8))
  88 -                       continue;
  89 -
  90                 /* Interrupt to test */
  91                 mask = 1 << i;
  92
  93 +               if (adapter->flags & FLAG_IS_ICH) {
  94 +                       switch (mask) {
  95 +                       case E1000_ICR_RXSEQ:
  96 +                               continue;
  97 +                       case 0x00000100:
  98 +                               if (adapter->hw.mac.type == e1000_ich8lan ||
  99 +                                   adapter->hw.mac.type == e1000_ich9lan)
 100 +                                       continue;
 101 +                               break;
 102 +                       default:
 103 +                               break;
 104 +                       }
 105 +               }
 106 +
 107                 if (!shared_int) {
 108                         /*
 109                          * Disable the interrupt to be reported in
 110 --- a/drivers/net/e1000e/hw.h
 111 +++ b/drivers/net/e1000e/hw.h
 112 @@ -362,6 +362,8 @@ enum e1e_registers {
 113  #define E1000_DEV_ID_ICH10_R_BM_LM             0x10CC
 114  #define E1000_DEV_ID_ICH10_R_BM_LF             0x10CD
 115  #define E1000_DEV_ID_ICH10_R_BM_V              0x10CE
 116 +#define E1000_DEV_ID_ICH10_D_BM_LM             0x10DE
 117 +#define E1000_DEV_ID_ICH10_D_BM_LF             0x10DF
 118
 119  #define E1000_REVISION_4 4
 120
 121 @@ -375,6 +377,7 @@ enum e1000_mac_type {
 122         e1000_80003es2lan,
 123         e1000_ich8lan,
 124         e1000_ich9lan,
 125 +       e1000_ich10lan,
 126  };
 127
 128  enum e1000_media_type {
 129 --- a/drivers/net/e1000e/ich8lan.c
 130 +++ b/drivers/net/e1000e/ich8lan.c
 131 @@ -43,7 +43,8 @@
 132   * 82567LM-2 Gigabit Network Connection
 133   * 82567LF-2 Gigabit Network Connection
 134   * 82567V-2 Gigabit Network Connection
 135 - * 82562GT-3 10/100 Network Connection
 136 + * 82567LF-3 Gigabit Network Connection
 137 + * 82567LM-3 Gigabit Network Connection
 138   * 82567LM-4 Gigabit Network Connection
 139   */
 140
 141 @@ -172,12 +173,15 @@ static s32 e1000_check_polarity_ife_ich8
 142  static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 143  static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 144                                                 u32 offset, u8 byte);
 145 +static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 146 +                                        u8 *data);
 147  static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 148                                          u16 *data);
 149  static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 150                                          u8 size, u16 *data);
 151  static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 152  static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 153 +static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 154
 155  static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 156  {
 157 @@ -945,6 +949,56 @@ static s32 e1000_set_d3_lplu_state_ich8l
 158  }
 159
 160  /**
 161 + *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
 162 + *  @hw: pointer to the HW structure
 163 + *  @bank:  pointer to the variable that returns the active bank
 164 + *
 165 + *  Reads signature byte from the NVM using the flash access registers.
 166 + **/
 167 +static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
 168 +{
 169 +       struct e1000_nvm_info *nvm = &hw->nvm;
 170 +       /* flash bank size is in words */
 171 +       u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
 172 +       u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
 173 +       u8 bank_high_byte = 0;
 174 +
 175 +       if (hw->mac.type != e1000_ich10lan) {
 176 +               if (er32(EECD) & E1000_EECD_SEC1VAL)
 177 +                       *bank = 1;
 178 +               else
 179 +                       *bank = 0;
 180 +       } else {
 181 +               /*
 182 +                * Make sure the signature for bank 0 is valid,
 183 +                * if not check for bank1
 184 +                */
 185 +               e1000_read_flash_byte_ich8lan(hw, act_offset, &bank_high_byte);
 186 +               if ((bank_high_byte & 0xC0) == 0x80) {
 187 +                       *bank = 0;
 188 +               } else {
 189 +                       /*
 190 +                        * find if segment 1 is valid by verifying
 191 +                        * bit 15:14 = 10b in word 0x13
 192 +                        */
 193 +                       e1000_read_flash_byte_ich8lan(hw,
 194 +                                                     act_offset + bank1_offset,
 195 +                                                     &bank_high_byte);
 196 +
 197 +                       /* bank1 has a valid signature equivalent to SEC1V */
 198 +                       if ((bank_high_byte & 0xC0) == 0x80) {
 199 +                               *bank = 1;
 200 +                       } else {
 201 +                               hw_dbg(hw, "ERROR: EEPROM not present\n");
 202 +                               return -E1000_ERR_NVM;
 203 +                       }
 204 +               }
 205 +       }
 206 +
 207 +       return 0;
 208 +}
 209 +
 210 +/**
 211   *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
 212   *  @hw: pointer to the HW structure
 213   *  @offset: The offset (in bytes) of the word(s) to read.
 214 @@ -960,6 +1014,7 @@ static s32 e1000_read_nvm_ich8lan(struct
 215         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 216         u32 act_offset;
 217         s32 ret_val;
 218 +       u32 bank = 0;
 219         u16 i, word;
 220
 221         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
 222 @@ -972,10 +1027,11 @@ static s32 e1000_read_nvm_ich8lan(struct
 223         if (ret_val)
 224                 return ret_val;
 225
 226 -       /* Start with the bank offset, then add the relative offset. */
 227 -       act_offset = (er32(EECD) & E1000_EECD_SEC1VAL)
 228 -                    ? nvm->flash_bank_size
 229 -                    : 0;
 230 +       ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
 231 +       if (ret_val)
 232 +               return ret_val;
 233 +
 234 +       act_offset = (bank) ? nvm->flash_bank_size : 0;
 235         act_offset += offset;
 236
 237         for (i = 0; i < words; i++) {
 238 @@ -1123,6 +1179,29 @@ static s32 e1000_read_flash_word_ich8lan
 239  }
 240
 241  /**
 242 + *  e1000_read_flash_byte_ich8lan - Read byte from flash
 243 + *  @hw: pointer to the HW structure
 244 + *  @offset: The offset of the byte to read.
 245 + *  @data: Pointer to a byte to store the value read.
 246 + *
 247 + *  Reads a single byte from the NVM using the flash access registers.
 248 + **/
 249 +static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 250 +                                        u8 *data)
 251 +{
 252 +       s32 ret_val;
 253 +       u16 word = 0;
 254 +
 255 +       ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
 256 +       if (ret_val)
 257 +               return ret_val;
 258 +
 259 +       *data = (u8)word;
 260 +
 261 +       return 0;
 262 +}
 263 +
 264 +/**
 265   *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
 266   *  @hw: pointer to the HW structure
 267   *  @offset: The offset (in bytes) of the byte or word to read.
 268 @@ -1253,7 +1332,7 @@ static s32 e1000_update_nvm_checksum_ich
 269  {
 270         struct e1000_nvm_info *nvm = &hw->nvm;
 271         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 272 -       u32 i, act_offset, new_bank_offset, old_bank_offset;
 273 +       u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
 274         s32 ret_val;
 275         u16 data;
 276
 277 @@ -1273,7 +1352,11 @@ static s32 e1000_update_nvm_checksum_ich
 278          * write to bank 0 etc.  We also need to erase the segment that
 279          * is going to be written
 280          */
 281 -       if (!(er32(EECD) & E1000_EECD_SEC1VAL)) {
 282 +       ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
 283 +       if (ret_val)
 284 +               return ret_val;
 285 +
 286 +       if (bank == 0) {
 287                 new_bank_offset = nvm->flash_bank_size;
 288                 old_bank_offset = 0;
 289                 e1000_erase_flash_bank_ich8lan(hw, 1);
 290 @@ -2289,13 +2372,14 @@ void e1000e_gig_downshift_workaround_ich
 291   *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
 292   *  to a lower speed.
 293   *
 294 - *  Should only be called for ICH9 devices.
 295 + *  Should only be called for ICH9 and ICH10 devices.
 296   **/
 297  void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
 298  {
 299         u32 phy_ctrl;
 300
 301 -       if (hw->mac.type == e1000_ich9lan) {
 302 +       if ((hw->mac.type == e1000_ich10lan) ||
 303 +           (hw->mac.type == e1000_ich9lan)) {
 304                 phy_ctrl = er32(PHY_CTRL);
 305                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
 306                             E1000_PHY_CTRL_GBE_DISABLE;
 307 @@ -2353,6 +2437,39 @@ static s32 e1000_led_off_ich8lan(struct
 308  }
 309
 310  /**
 311 + *  e1000_get_cfg_done_ich8lan - Read config done bit
 312 + *  @hw: pointer to the HW structure
 313 + *
 314 + *  Read the management control register for the config done bit for
 315 + *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
 316 + *  to read the config done bit, so an error is *ONLY* logged and returns
 317 + *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
 318 + *  would not be able to be reset or change link.
 319 + **/
 320 +static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
 321 +{
 322 +       u32 bank = 0;
 323 +
 324 +       e1000e_get_cfg_done(hw);
 325 +
 326 +       /* If EEPROM is not marked present, init the IGP 3 PHY manually */
 327 +       if (hw->mac.type != e1000_ich10lan) {
 328 +               if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
 329 +                   (hw->phy.type == e1000_phy_igp_3)) {
 330 +                       e1000e_phy_init_script_igp3(hw);
 331 +               }
 332 +       } else {
 333 +               if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
 334 +                       /* Maybe we should do a basic PHY config */
 335 +                       hw_dbg(hw, "EEPROM not present\n");
 336 +                       return -E1000_ERR_CONFIG;
 337 +               }
 338 +       }
 339 +
 340 +       return 0;
 341 +}
 342 +
 343 +/**
 344   *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
 345   *  @hw: pointer to the HW structure
 346   *
 347 @@ -2402,7 +2519,7 @@ static struct e1000_phy_operations ich8_
 348         .check_reset_block      = e1000_check_reset_block_ich8lan,
 349         .commit_phy             = NULL,
 350         .force_speed_duplex     = e1000_phy_force_speed_duplex_ich8lan,
 351 -       .get_cfg_done           = e1000e_get_cfg_done,
 352 +       .get_cfg_done           = e1000_get_cfg_done_ich8lan,
 353         .get_cable_length       = e1000e_get_cable_length_igp_2,
 354         .get_phy_info           = e1000_get_phy_info_ich8lan,
 355         .read_phy_reg           = e1000e_read_phy_reg_igp,
 356 @@ -2457,3 +2574,20 @@ struct e1000_info e1000_ich9_info = {
 357         .nvm_ops                = &ich8_nvm_ops,
 358  };
 359
 360 +struct e1000_info e1000_ich10_info = {
 361 +       .mac                    = e1000_ich10lan,
 362 +       .flags                  = FLAG_HAS_JUMBO_FRAMES
 363 +                                 | FLAG_IS_ICH
 364 +                                 | FLAG_HAS_WOL
 365 +                                 | FLAG_RX_CSUM_ENABLED
 366 +                                 | FLAG_HAS_CTRLEXT_ON_LOAD
 367 +                                 | FLAG_HAS_AMT
 368 +                                 | FLAG_HAS_ERT
 369 +                                 | FLAG_HAS_FLASH
 370 +                                 | FLAG_APME_IN_WUC,
 371 +       .pba                    = 10,
 372 +       .get_variants           = e1000_get_variants_ich8lan,
 373 +       .mac_ops                = &ich8_mac_ops,
 374 +       .phy_ops                = &ich8_phy_ops,
 375 +       .nvm_ops                = &ich8_nvm_ops,
 376 +};
 377 --- a/drivers/net/e1000e/netdev.c
 378 +++ b/drivers/net/e1000e/netdev.c
 379 @@ -59,6 +59,7 @@ static const struct e1000_info *e1000_in
 380         [board_80003es2lan]     = &e1000_es2_info,
 381         [board_ich8lan]         = &e1000_ich8_info,
 382         [board_ich9lan]         = &e1000_ich9_info,
 383 +       [board_ich10lan]        = &e1000_ich10_info,
 384  };
 385
 386  #ifdef DEBUG
 387 @@ -3520,6 +3521,27 @@ static void e1000_watchdog_task(struct w
 388                                                    &adapter->link_duplex);
 389                         e1000_print_link_info(adapter);
 390                         /*
 391 +                        * On supported PHYs, check for duplex mismatch only
 392 +                        * if link has autonegotiated at 10/100 half
 393 +                        */
 394 +                       if ((hw->phy.type == e1000_phy_igp_3 ||
 395 +                            hw->phy.type == e1000_phy_bm) &&
 396 +                           (hw->mac.autoneg == true) &&
 397 +                           (adapter->link_speed == SPEED_10 ||
 398 +                            adapter->link_speed == SPEED_100) &&
 399 +                           (adapter->link_duplex == HALF_DUPLEX)) {
 400 +                               u16 autoneg_exp;
 401 +
 402 +                               e1e_rphy(hw, PHY_AUTONEG_EXP, &autoneg_exp);
 403 +
 404 +                               if (!(autoneg_exp & NWAY_ER_LP_NWAY_CAPS))
 405 +                                       e_info("Autonegotiated half duplex but"
 406 +                                              " link partner cannot autoneg. "
 407 +                                              " Try forcing full duplex if "
 408 +                                              "link gets many collisions.\n");
 409 +                       }
 410 +
 411 +                       /*
 412                          * tweak tx_queue_len according to speed/duplex
 413                          * and adjust the timeout factor
 414                          */
 415 @@ -5111,6 +5133,9 @@ static struct pci_device_id e1000_pci_tb
 416         { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
 417         { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
 418
 419 +       { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
 420 +       { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
 421 +
 422         { }     /* terminate list */
 423  };
 424  MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
 425 --- a/drivers/net/e1000e/phy.c
 426 +++ b/drivers/net/e1000e/phy.c
 427 @@ -1734,6 +1734,91 @@ s32 e1000e_get_cfg_done(struct e1000_hw
 428         return 0;
 429  }
 430
 431 +/**
 432 + *  e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
 433 + *  @hw: pointer to the HW structure
 434 + *
 435 + *  Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
 436 + **/
 437 +s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
 438 +{
 439 +       hw_dbg(hw, "Running IGP 3 PHY init script\n");
 440 +
 441 +       /* PHY init IGP 3 */
 442 +       /* Enable rise/fall, 10-mode work in class-A */
 443 +       e1e_wphy(hw, 0x2F5B, 0x9018);
 444 +       /* Remove all caps from Replica path filter */
 445 +       e1e_wphy(hw, 0x2F52, 0x0000);
 446 +       /* Bias trimming for ADC, AFE and Driver (Default) */
 447 +       e1e_wphy(hw, 0x2FB1, 0x8B24);
 448 +       /* Increase Hybrid poly bias */
 449 +       e1e_wphy(hw, 0x2FB2, 0xF8F0);
 450 +       /* Add 4% to Tx amplitude in Gig mode */
 451 +       e1e_wphy(hw, 0x2010, 0x10B0);
 452 +       /* Disable trimming (TTT) */
 453 +       e1e_wphy(hw, 0x2011, 0x0000);
 454 +       /* Poly DC correction to 94.6% + 2% for all channels */
 455 +       e1e_wphy(hw, 0x20DD, 0x249A);
 456 +       /* ABS DC correction to 95.9% */
 457 +       e1e_wphy(hw, 0x20DE, 0x00D3);
 458 +       /* BG temp curve trim */
 459 +       e1e_wphy(hw, 0x28B4, 0x04CE);
 460 +       /* Increasing ADC OPAMP stage 1 currents to max */
 461 +       e1e_wphy(hw, 0x2F70, 0x29E4);
 462 +       /* Force 1000 ( required for enabling PHY regs configuration) */
 463 +       e1e_wphy(hw, 0x0000, 0x0140);
 464 +       /* Set upd_freq to 6 */
 465 +       e1e_wphy(hw, 0x1F30, 0x1606);
 466 +       /* Disable NPDFE */
 467 +       e1e_wphy(hw, 0x1F31, 0xB814);
 468 +       /* Disable adaptive fixed FFE (Default) */
 469 +       e1e_wphy(hw, 0x1F35, 0x002A);
 470 +       /* Enable FFE hysteresis */
 471 +       e1e_wphy(hw, 0x1F3E, 0x0067);
 472 +       /* Fixed FFE for short cable lengths */
 473 +       e1e_wphy(hw, 0x1F54, 0x0065);
 474 +       /* Fixed FFE for medium cable lengths */
 475 +       e1e_wphy(hw, 0x1F55, 0x002A);
 476 +       /* Fixed FFE for long cable lengths */
 477 +       e1e_wphy(hw, 0x1F56, 0x002A);
 478 +       /* Enable Adaptive Clip Threshold */
 479 +       e1e_wphy(hw, 0x1F72, 0x3FB0);
 480 +       /* AHT reset limit to 1 */
 481 +       e1e_wphy(hw, 0x1F76, 0xC0FF);
 482 +       /* Set AHT master delay to 127 msec */
 483 +       e1e_wphy(hw, 0x1F77, 0x1DEC);
 484 +       /* Set scan bits for AHT */
 485 +       e1e_wphy(hw, 0x1F78, 0xF9EF);
 486 +       /* Set AHT Preset bits */
 487 +       e1e_wphy(hw, 0x1F79, 0x0210);
 488 +       /* Change integ_factor of channel A to 3 */
 489 +       e1e_wphy(hw, 0x1895, 0x0003);
 490 +       /* Change prop_factor of channels BCD to 8 */
 491 +       e1e_wphy(hw, 0x1796, 0x0008);
 492 +       /* Change cg_icount + enable integbp for channels BCD */
 493 +       e1e_wphy(hw, 0x1798, 0xD008);
 494 +       /*
 495 +        * Change cg_icount + enable integbp + change prop_factor_master
 496 +        * to 8 for channel A
 497 +        */
 498 +       e1e_wphy(hw, 0x1898, 0xD918);
 499 +       /* Disable AHT in Slave mode on channel A */
 500 +       e1e_wphy(hw, 0x187A, 0x0800);
 501 +       /*
 502 +        * Enable LPLU and disable AN to 1000 in non-D0a states,
 503 +        * Enable SPD+B2B
 504 +        */
 505 +       e1e_wphy(hw, 0x0019, 0x008D);
 506 +       /* Enable restart AN on an1000_dis change */
 507 +       e1e_wphy(hw, 0x001B, 0x2080);
 508 +       /* Enable wh_fifo read clock in 10/100 modes */
 509 +       e1e_wphy(hw, 0x0014, 0x0045);
 510 +       /* Restart AN, Speed selection is 1000 */
 511 +       e1e_wphy(hw, 0x0000, 0x1340);
 512 +
 513 +       return 0;
 514 +}
 515 +
 516  /* Internal function pointers */
 517
 518  /**