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Updated xen patches taken from suse.
[people/pmueller/ipfire-2.x.git] / src / patches / suse-2.6.27.25 / patches.suse / usb-move-ehci-reg-def.patch
1 From 0af36739af81f152cc24a0fdfa0754ef657afe3d Mon Sep 17 00:00:00 2001
2 From: Yinghai Lu <yhlu.kernel@gmail.com>
3 Date: Thu, 24 Jul 2008 17:27:57 -0700
4 Subject: usb: move ehci reg def
5 Patch-mainline: 2.6.28
6
7 From: Yinghai Lu <yhlu.kernel@gmail.com>
8
9 commit 0af36739af81f152cc24a0fdfa0754ef657afe3d upstream.
10
11 prepare x86: usb debug port early console
12
13 move ehci struct def to linux/usrb/ehci_def.h from host/ehci.h
14
15 Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com>
16 Acked-by: David Brownell <dbrownell@users.sourceforge.net>
17 Cc: Andrew Morton <akpm@linux-foundation.org>
18 Cc: Andi Kleen <andi@firstfloor.org>
19 Cc: "Arjan van de Ven" <arjan@infradead.org>
20 Cc: "Eric W. Biederman" <ebiederm@xmission.com>
21 Cc: "Greg KH" <greg@kroah.com>
22 Signed-off-by: Ingo Molnar <mingo@elte.hu>
23 Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
24
25 ---
26 drivers/usb/host/ehci.h | 138 -------------------------------------
27 include/linux/usb/ehci_def.h | 160 +++++++++++++++++++++++++++++++++++++++++++
28 2 files changed, 161 insertions(+), 137 deletions(-)
29
30 --- a/drivers/usb/host/ehci.h
31 +++ b/drivers/usb/host/ehci.h
32 @@ -216,143 +216,7 @@ static void free_cached_itd_list(struct
33
34 /*-------------------------------------------------------------------------*/
35
36 -/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
37 -
38 -/* Section 2.2 Host Controller Capability Registers */
39 -struct ehci_caps {
40 - /* these fields are specified as 8 and 16 bit registers,
41 - * but some hosts can't perform 8 or 16 bit PCI accesses.
42 - */
43 - u32 hc_capbase;
44 -#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
45 -#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
46 - u32 hcs_params; /* HCSPARAMS - offset 0x4 */
47 -#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
48 -#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
49 -#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
50 -#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */
51 -#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
52 -#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
53 -#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
54 -
55 - u32 hcc_params; /* HCCPARAMS - offset 0x8 */
56 -#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */
57 -#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
58 -#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
59 -#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
60 -#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
61 -#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
62 - u8 portroute [8]; /* nibbles for routing - offset 0xC */
63 -} __attribute__ ((packed));
64 -
65 -
66 -/* Section 2.3 Host Controller Operational Registers */
67 -struct ehci_regs {
68 -
69 - /* USBCMD: offset 0x00 */
70 - u32 command;
71 -/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
72 -#define CMD_PARK (1<<11) /* enable "park" on async qh */
73 -#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
74 -#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
75 -#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
76 -#define CMD_ASE (1<<5) /* async schedule enable */
77 -#define CMD_PSE (1<<4) /* periodic schedule enable */
78 -/* 3:2 is periodic frame list size */
79 -#define CMD_RESET (1<<1) /* reset HC not bus */
80 -#define CMD_RUN (1<<0) /* start/stop HC */
81 -
82 - /* USBSTS: offset 0x04 */
83 - u32 status;
84 -#define STS_ASS (1<<15) /* Async Schedule Status */
85 -#define STS_PSS (1<<14) /* Periodic Schedule Status */
86 -#define STS_RECL (1<<13) /* Reclamation */
87 -#define STS_HALT (1<<12) /* Not running (any reason) */
88 -/* some bits reserved */
89 - /* these STS_* flags are also intr_enable bits (USBINTR) */
90 -#define STS_IAA (1<<5) /* Interrupted on async advance */
91 -#define STS_FATAL (1<<4) /* such as some PCI access errors */
92 -#define STS_FLR (1<<3) /* frame list rolled over */
93 -#define STS_PCD (1<<2) /* port change detect */
94 -#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
95 -#define STS_INT (1<<0) /* "normal" completion (short, ...) */
96 -
97 - /* USBINTR: offset 0x08 */
98 - u32 intr_enable;
99 -
100 - /* FRINDEX: offset 0x0C */
101 - u32 frame_index; /* current microframe number */
102 - /* CTRLDSSEGMENT: offset 0x10 */
103 - u32 segment; /* address bits 63:32 if needed */
104 - /* PERIODICLISTBASE: offset 0x14 */
105 - u32 frame_list; /* points to periodic list */
106 - /* ASYNCLISTADDR: offset 0x18 */
107 - u32 async_next; /* address of next async queue head */
108 -
109 - u32 reserved [9];
110 -
111 - /* CONFIGFLAG: offset 0x40 */
112 - u32 configured_flag;
113 -#define FLAG_CF (1<<0) /* true: we'll support "high speed" */
114 -
115 - /* PORTSC: offset 0x44 */
116 - u32 port_status [0]; /* up to N_PORTS */
117 -/* 31:23 reserved */
118 -#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */
119 -#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */
120 -#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */
121 -/* 19:16 for port testing */
122 -#define PORT_LED_OFF (0<<14)
123 -#define PORT_LED_AMBER (1<<14)
124 -#define PORT_LED_GREEN (2<<14)
125 -#define PORT_LED_MASK (3<<14)
126 -#define PORT_OWNER (1<<13) /* true: companion hc owns this port */
127 -#define PORT_POWER (1<<12) /* true: has power (see PPC) */
128 -#define PORT_USB11(x) (((x)&(3<<10))==(1<<10)) /* USB 1.1 device */
129 -/* 11:10 for detecting lowspeed devices (reset vs release ownership) */
130 -/* 9 reserved */
131 -#define PORT_RESET (1<<8) /* reset port */
132 -#define PORT_SUSPEND (1<<7) /* suspend port */
133 -#define PORT_RESUME (1<<6) /* resume it */
134 -#define PORT_OCC (1<<5) /* over current change */
135 -#define PORT_OC (1<<4) /* over current active */
136 -#define PORT_PEC (1<<3) /* port enable change */
137 -#define PORT_PE (1<<2) /* port enable */
138 -#define PORT_CSC (1<<1) /* connect status change */
139 -#define PORT_CONNECT (1<<0) /* device connected */
140 -#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
141 -} __attribute__ ((packed));
142 -
143 -#define USBMODE 0x68 /* USB Device mode */
144 -#define USBMODE_SDIS (1<<3) /* Stream disable */
145 -#define USBMODE_BE (1<<2) /* BE/LE endianness select */
146 -#define USBMODE_CM_HC (3<<0) /* host controller mode */
147 -#define USBMODE_CM_IDLE (0<<0) /* idle state */
148 -
149 -/* Appendix C, Debug port ... intended for use with special "debug devices"
150 - * that can help if there's no serial console. (nonstandard enumeration.)
151 - */
152 -struct ehci_dbg_port {
153 - u32 control;
154 -#define DBGP_OWNER (1<<30)
155 -#define DBGP_ENABLED (1<<28)
156 -#define DBGP_DONE (1<<16)
157 -#define DBGP_INUSE (1<<10)
158 -#define DBGP_ERRCODE(x) (((x)>>7)&0x07)
159 -# define DBGP_ERR_BAD 1
160 -# define DBGP_ERR_SIGNAL 2
161 -#define DBGP_ERROR (1<<6)
162 -#define DBGP_GO (1<<5)
163 -#define DBGP_OUT (1<<4)
164 -#define DBGP_LEN(x) (((x)>>0)&0x0f)
165 - u32 pids;
166 -#define DBGP_PID_GET(x) (((x)>>16)&0xff)
167 -#define DBGP_PID_SET(data,tok) (((data)<<8)|(tok))
168 - u32 data03;
169 - u32 data47;
170 - u32 address;
171 -#define DBGP_EPADDR(dev,ep) (((dev)<<8)|(ep))
172 -} __attribute__ ((packed));
173 +#include <linux/usb/ehci_def.h>
174
175 /*-------------------------------------------------------------------------*/
176
177 --- /dev/null
178 +++ b/include/linux/usb/ehci_def.h
179 @@ -0,0 +1,160 @@
180 +/*
181 + * Copyright (c) 2001-2002 by David Brownell
182 + *
183 + * This program is free software; you can redistribute it and/or modify it
184 + * under the terms of the GNU General Public License as published by the
185 + * Free Software Foundation; either version 2 of the License, or (at your
186 + * option) any later version.
187 + *
188 + * This program is distributed in the hope that it will be useful, but
189 + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
190 + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
191 + * for more details.
192 + *
193 + * You should have received a copy of the GNU General Public License
194 + * along with this program; if not, write to the Free Software Foundation,
195 + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
196 + */
197 +
198 +#ifndef __LINUX_USB_EHCI_DEF_H
199 +#define __LINUX_USB_EHCI_DEF_H
200 +
201 +/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
202 +
203 +/* Section 2.2 Host Controller Capability Registers */
204 +struct ehci_caps {
205 + /* these fields are specified as 8 and 16 bit registers,
206 + * but some hosts can't perform 8 or 16 bit PCI accesses.
207 + */
208 + u32 hc_capbase;
209 +#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
210 +#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
211 + u32 hcs_params; /* HCSPARAMS - offset 0x4 */
212 +#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
213 +#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
214 +#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
215 +#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */
216 +#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
217 +#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
218 +#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
219 +
220 + u32 hcc_params; /* HCCPARAMS - offset 0x8 */
221 +#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */
222 +#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
223 +#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
224 +#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
225 +#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
226 +#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
227 + u8 portroute [8]; /* nibbles for routing - offset 0xC */
228 +} __attribute__ ((packed));
229 +
230 +
231 +/* Section 2.3 Host Controller Operational Registers */
232 +struct ehci_regs {
233 +
234 + /* USBCMD: offset 0x00 */
235 + u32 command;
236 +/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
237 +#define CMD_PARK (1<<11) /* enable "park" on async qh */
238 +#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
239 +#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
240 +#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
241 +#define CMD_ASE (1<<5) /* async schedule enable */
242 +#define CMD_PSE (1<<4) /* periodic schedule enable */
243 +/* 3:2 is periodic frame list size */
244 +#define CMD_RESET (1<<1) /* reset HC not bus */
245 +#define CMD_RUN (1<<0) /* start/stop HC */
246 +
247 + /* USBSTS: offset 0x04 */
248 + u32 status;
249 +#define STS_ASS (1<<15) /* Async Schedule Status */
250 +#define STS_PSS (1<<14) /* Periodic Schedule Status */
251 +#define STS_RECL (1<<13) /* Reclamation */
252 +#define STS_HALT (1<<12) /* Not running (any reason) */
253 +/* some bits reserved */
254 + /* these STS_* flags are also intr_enable bits (USBINTR) */
255 +#define STS_IAA (1<<5) /* Interrupted on async advance */
256 +#define STS_FATAL (1<<4) /* such as some PCI access errors */
257 +#define STS_FLR (1<<3) /* frame list rolled over */
258 +#define STS_PCD (1<<2) /* port change detect */
259 +#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
260 +#define STS_INT (1<<0) /* "normal" completion (short, ...) */
261 +
262 + /* USBINTR: offset 0x08 */
263 + u32 intr_enable;
264 +
265 + /* FRINDEX: offset 0x0C */
266 + u32 frame_index; /* current microframe number */
267 + /* CTRLDSSEGMENT: offset 0x10 */
268 + u32 segment; /* address bits 63:32 if needed */
269 + /* PERIODICLISTBASE: offset 0x14 */
270 + u32 frame_list; /* points to periodic list */
271 + /* ASYNCLISTADDR: offset 0x18 */
272 + u32 async_next; /* address of next async queue head */
273 +
274 + u32 reserved [9];
275 +
276 + /* CONFIGFLAG: offset 0x40 */
277 + u32 configured_flag;
278 +#define FLAG_CF (1<<0) /* true: we'll support "high speed" */
279 +
280 + /* PORTSC: offset 0x44 */
281 + u32 port_status [0]; /* up to N_PORTS */
282 +/* 31:23 reserved */
283 +#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */
284 +#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */
285 +#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */
286 +/* 19:16 for port testing */
287 +#define PORT_LED_OFF (0<<14)
288 +#define PORT_LED_AMBER (1<<14)
289 +#define PORT_LED_GREEN (2<<14)
290 +#define PORT_LED_MASK (3<<14)
291 +#define PORT_OWNER (1<<13) /* true: companion hc owns this port */
292 +#define PORT_POWER (1<<12) /* true: has power (see PPC) */
293 +#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */
294 +/* 11:10 for detecting lowspeed devices (reset vs release ownership) */
295 +/* 9 reserved */
296 +#define PORT_RESET (1<<8) /* reset port */
297 +#define PORT_SUSPEND (1<<7) /* suspend port */
298 +#define PORT_RESUME (1<<6) /* resume it */
299 +#define PORT_OCC (1<<5) /* over current change */
300 +#define PORT_OC (1<<4) /* over current active */
301 +#define PORT_PEC (1<<3) /* port enable change */
302 +#define PORT_PE (1<<2) /* port enable */
303 +#define PORT_CSC (1<<1) /* connect status change */
304 +#define PORT_CONNECT (1<<0) /* device connected */
305 +#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
306 +} __attribute__ ((packed));
307 +
308 +#define USBMODE 0x68 /* USB Device mode */
309 +#define USBMODE_SDIS (1<<3) /* Stream disable */
310 +#define USBMODE_BE (1<<2) /* BE/LE endianness select */
311 +#define USBMODE_CM_HC (3<<0) /* host controller mode */
312 +#define USBMODE_CM_IDLE (0<<0) /* idle state */
313 +
314 +/* Appendix C, Debug port ... intended for use with special "debug devices"
315 + * that can help if there's no serial console. (nonstandard enumeration.)
316 + */
317 +struct ehci_dbg_port {
318 + u32 control;
319 +#define DBGP_OWNER (1<<30)
320 +#define DBGP_ENABLED (1<<28)
321 +#define DBGP_DONE (1<<16)
322 +#define DBGP_INUSE (1<<10)
323 +#define DBGP_ERRCODE(x) (((x)>>7)&0x07)
324 +# define DBGP_ERR_BAD 1
325 +# define DBGP_ERR_SIGNAL 2
326 +#define DBGP_ERROR (1<<6)
327 +#define DBGP_GO (1<<5)
328 +#define DBGP_OUT (1<<4)
329 +#define DBGP_LEN(x) (((x)>>0)&0x0f)
330 + u32 pids;
331 +#define DBGP_PID_GET(x) (((x)>>16)&0xff)
332 +#define DBGP_PID_SET(data, tok) (((data)<<8)|(tok))
333 + u32 data03;
334 + u32 data47;
335 + u32 address;
336 +#define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep))
337 +} __attribute__ ((packed));
338 +
339 +#endif /* __LINUX_USB_EHCI_DEF_H */
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