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Add a patch to fix Intel E100 wake-on-lan problems.
[people/pmueller/ipfire-2.x.git] / src / patches / suse-2.6.27.39 / patches.drivers / 0005-Staging-add-et131x-network-driver.patch
1 From cfb739b459a4d982b75f5b92cbe7d2631999e206 Mon Sep 17 00:00:00 2001
2 From: Greg Kroah-Hartman <gregkh@suse.de>
3 Date: Thu, 3 Apr 2008 17:30:53 -0700
4 Subject: [PATCH 05/23] Staging: add et131x network driver
5 Patch-mainline: 2.6.28
6
7 This is a driver for the ET1310 network device.
8
9 Based on the driver found at https://sourceforge.net/projects/et131x/
10
11 Cleaned up immensely by Olaf Hartman <o.hartmann@telovital.com> and Christoph
12 Hellwig <hch@infradead.org>
13
14 Note, the powermanagement options were removed from the vendor provided
15 driver as they did not build properly at the time.
16
17 TODO:
18 - kernel coding style cleanups
19 - forward port for latest network driver changes
20 - kill useless typecasts (e.g. in et1310_phy.c)
21 - alloc_etherdev is initializing memory with zero?!?
22 - add_timer call in et131x_netdev.c is correct?
23 - Add power saving functionality (suspend, sleep, resume)
24 - Implement a few more kernel Parameter (set mac )
25
26 Cc: Olaf Hartmann <o.hartmann@telovital.com>
27 Cc: Christoph Hellwig <hch@infradead.org>
28 Cc: Dean Adams <dadams1969@gmail.com>
29 Cc: Victor Soriano <vjsoriano@agere.com>
30 Cc: Andre-Sebastian Liebe <andre@lianse.eu>
31 Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
32 ---
33 drivers/staging/Kconfig | 1 +
34 drivers/staging/Makefile | 1 +
35 drivers/staging/et131x/Kconfig | 18 +
36 drivers/staging/et131x/Makefile | 18 +
37 drivers/staging/et131x/README | 25 +
38 drivers/staging/et131x/et1310_address_map.h | 2399 +++++++++++++++++++++++++++
39 drivers/staging/et131x/et1310_eeprom.c | 480 ++++++
40 drivers/staging/et131x/et1310_eeprom.h | 89 +
41 drivers/staging/et131x/et1310_jagcore.c | 220 +++
42 drivers/staging/et131x/et1310_jagcore.h | 112 ++
43 drivers/staging/et131x/et1310_mac.c | 792 +++++++++
44 drivers/staging/et131x/et1310_mac.h | 93 +
45 drivers/staging/et131x/et1310_phy.c | 1281 ++++++++++++++
46 drivers/staging/et131x/et1310_phy.h | 910 ++++++++++
47 drivers/staging/et131x/et1310_pm.c | 207 +++
48 drivers/staging/et131x/et1310_pm.h | 125 ++
49 drivers/staging/et131x/et1310_rx.c | 1391 ++++++++++++++++
50 drivers/staging/et131x/et1310_rx.h | 373 +++++
51 drivers/staging/et131x/et1310_tx.c | 1525 +++++++++++++++++
52 drivers/staging/et131x/et1310_tx.h | 242 +++
53 drivers/staging/et131x/et131x_adapter.h | 347 ++++
54 drivers/staging/et131x/et131x_config.c | 325 ++++
55 drivers/staging/et131x/et131x_config.h | 67 +
56 drivers/staging/et131x/et131x_debug.c | 218 +++
57 drivers/staging/et131x/et131x_debug.h | 201 +++
58 drivers/staging/et131x/et131x_defs.h | 128 ++
59 drivers/staging/et131x/et131x_initpci.c | 1046 ++++++++++++
60 drivers/staging/et131x/et131x_initpci.h | 73 +
61 drivers/staging/et131x/et131x_isr.c | 488 ++++++
62 drivers/staging/et131x/et131x_isr.h | 65 +
63 drivers/staging/et131x/et131x_netdev.c | 856 ++++++++++
64 drivers/staging/et131x/et131x_netdev.h | 64 +
65 drivers/staging/et131x/et131x_version.h | 81 +
66 33 files changed, 14261 insertions(+), 0 deletions(-)
67 create mode 100644 drivers/staging/et131x/Kconfig
68 create mode 100644 drivers/staging/et131x/Makefile
69 create mode 100644 drivers/staging/et131x/README
70 create mode 100644 drivers/staging/et131x/et1310_address_map.h
71 create mode 100644 drivers/staging/et131x/et1310_eeprom.c
72 create mode 100644 drivers/staging/et131x/et1310_eeprom.h
73 create mode 100644 drivers/staging/et131x/et1310_jagcore.c
74 create mode 100644 drivers/staging/et131x/et1310_jagcore.h
75 create mode 100644 drivers/staging/et131x/et1310_mac.c
76 create mode 100644 drivers/staging/et131x/et1310_mac.h
77 create mode 100644 drivers/staging/et131x/et1310_phy.c
78 create mode 100644 drivers/staging/et131x/et1310_phy.h
79 create mode 100644 drivers/staging/et131x/et1310_pm.c
80 create mode 100644 drivers/staging/et131x/et1310_pm.h
81 create mode 100644 drivers/staging/et131x/et1310_rx.c
82 create mode 100644 drivers/staging/et131x/et1310_rx.h
83 create mode 100644 drivers/staging/et131x/et1310_tx.c
84 create mode 100644 drivers/staging/et131x/et1310_tx.h
85 create mode 100644 drivers/staging/et131x/et131x_adapter.h
86 create mode 100644 drivers/staging/et131x/et131x_config.c
87 create mode 100644 drivers/staging/et131x/et131x_config.h
88 create mode 100644 drivers/staging/et131x/et131x_debug.c
89 create mode 100644 drivers/staging/et131x/et131x_debug.h
90 create mode 100644 drivers/staging/et131x/et131x_defs.h
91 create mode 100644 drivers/staging/et131x/et131x_initpci.c
92 create mode 100644 drivers/staging/et131x/et131x_initpci.h
93 create mode 100644 drivers/staging/et131x/et131x_isr.c
94 create mode 100644 drivers/staging/et131x/et131x_isr.h
95 create mode 100644 drivers/staging/et131x/et131x_netdev.c
96 create mode 100644 drivers/staging/et131x/et131x_netdev.h
97 create mode 100644 drivers/staging/et131x/et131x_version.h
98
99 diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
100 index 84832fe..4c3789d 100644
101 --- a/drivers/staging/Kconfig
102 +++ b/drivers/staging/Kconfig
103 @@ -23,5 +23,6 @@ menuconfig STAGING
104
105 if STAGING
106
107 +source "drivers/staging/et131x/Kconfig"
108
109 endif # STAGING
110 diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
111 index ceb0328..933b984 100644
112 --- a/drivers/staging/Makefile
113 +++ b/drivers/staging/Makefile
114 @@ -1,2 +1,3 @@
115 # Makefile for staging directory
116
117 +obj-$(CONFIG_ET131X) += et131x/
118 diff --git a/drivers/staging/et131x/Kconfig b/drivers/staging/et131x/Kconfig
119 new file mode 100644
120 index 0000000..e11cf34
121 --- /dev/null
122 +++ b/drivers/staging/et131x/Kconfig
123 @@ -0,0 +1,18 @@
124 +config ET131X
125 + tristate "Agere ET-1310 Gigabit Ethernet support"
126 + depends on NETDEV_1000 && PCI
127 + default n
128 + ---help---
129 + This driver supports Agere ET-1310 ethernet adapters.
130 +
131 + To compile this driver as a module, choose M here. The module
132 + will be called et131x.
133 +
134 +config ET131X_DEBUG
135 + bool "Enable et131x debugging"
136 + depends on ET131X
137 + default n
138 + ---help---
139 + Say Y for detailed debug information.
140 +
141 + If in doubt, say N.
142 diff --git a/drivers/staging/et131x/Makefile b/drivers/staging/et131x/Makefile
143 new file mode 100644
144 index 0000000..3ad571d
145 --- /dev/null
146 +++ b/drivers/staging/et131x/Makefile
147 @@ -0,0 +1,18 @@
148 +#
149 +# Makefile for the Agere ET-131x ethernet driver
150 +#
151 +
152 +obj-$(CONFIG_ET131X) += et131x.o
153 +
154 +et131x-objs := et1310_eeprom.o \
155 + et1310_jagcore.o \
156 + et1310_mac.o \
157 + et1310_phy.o \
158 + et1310_pm.o \
159 + et1310_rx.o \
160 + et1310_tx.o \
161 + et131x_config.o \
162 + et131x_debug.o \
163 + et131x_initpci.o \
164 + et131x_isr.o \
165 + et131x_netdev.o
166 diff --git a/drivers/staging/et131x/README b/drivers/staging/et131x/README
167 new file mode 100644
168 index 0000000..28752a5
169 --- /dev/null
170 +++ b/drivers/staging/et131x/README
171 @@ -0,0 +1,25 @@
172 +This is a driver for the ET1310 network device.
173 +
174 +Based on the driver found at https://sourceforge.net/projects/et131x/
175 +
176 +Cleaned up immensely by Olaf Hartman <o.hartmann@telovital.com> and Christoph
177 +Hellwig <hch@infradead.org>
178 +
179 +Note, the powermanagement options were removed from the vendor provided
180 +driver as they did not build properly at the time.
181 +
182 +TODO:
183 + - kernel coding style cleanups
184 + - forward port for latest network driver changes
185 + - kill useless typecasts (e.g. in et1310_phy.c)
186 + - alloc_etherdev is initializing memory with zero?!?
187 + - add_timer call in et131x_netdev.c is correct?
188 + - Add power saving functionality (suspend, sleep, resume)
189 + - Implement a few more kernel Parameter (set mac )
190 +
191 +Please send patches to:
192 + Greg Kroah-Hartman <gregkh@suse.de>
193 +
194 +And Cc: Olaf Hartmann <o.hartmann@telovital.com> as he has this device and can
195 +test any changes.
196 +
197 diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h
198 new file mode 100644
199 index 0000000..3c85999
200 --- /dev/null
201 +++ b/drivers/staging/et131x/et1310_address_map.h
202 @@ -0,0 +1,2399 @@
203 +/*
204 + * Agere Systems Inc.
205 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
206 + *
207 + * Copyright © 2005 Agere Systems Inc.
208 + * All rights reserved.
209 + * http://www.agere.com
210 + *
211 + *------------------------------------------------------------------------------
212 + *
213 + * et1310_address_map.h - Contains the register mapping for the ET1310
214 + *
215 + *------------------------------------------------------------------------------
216 + *
217 + * SOFTWARE LICENSE
218 + *
219 + * This software is provided subject to the following terms and conditions,
220 + * which you should read carefully before using the software. Using this
221 + * software indicates your acceptance of these terms and conditions. If you do
222 + * not agree with these terms and conditions, do not use the software.
223 + *
224 + * Copyright © 2005 Agere Systems Inc.
225 + * All rights reserved.
226 + *
227 + * Redistribution and use in source or binary forms, with or without
228 + * modifications, are permitted provided that the following conditions are met:
229 + *
230 + * . Redistributions of source code must retain the above copyright notice, this
231 + * list of conditions and the following Disclaimer as comments in the code as
232 + * well as in the documentation and/or other materials provided with the
233 + * distribution.
234 + *
235 + * . Redistributions in binary form must reproduce the above copyright notice,
236 + * this list of conditions and the following Disclaimer in the documentation
237 + * and/or other materials provided with the distribution.
238 + *
239 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
240 + * may be used to endorse or promote products derived from this software
241 + * without specific prior written permission.
242 + *
243 + * Disclaimer
244 + *
245 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
246 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
247 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
248 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
249 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
250 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
251 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
252 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
253 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
254 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
255 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
256 + * DAMAGE.
257 + *
258 + */
259 +
260 +#ifndef _ET1310_ADDRESS_MAP_H_
261 +#define _ET1310_ADDRESS_MAP_H_
262 +
263 +
264 +/* START OF GLOBAL REGISTER ADDRESS MAP */
265 +
266 +typedef union _Q_ADDR_t {
267 + u32 value;
268 + struct {
269 +#ifdef _BIT_FIELDS_HTOL
270 + u32 unused:22; // bits 10-31
271 + u32 addr:10; // bits 0-9
272 +#else
273 + u32 addr:10; // bits 0-9
274 + u32 unused:22; // bits 10-31
275 +#endif
276 + } bits;
277 +} Q_ADDR_t, *PQ_ADDR_t;
278 +
279 +/*
280 + * structure for tx queue start address reg in global address map
281 + * located at address 0x0000
282 + * Defined earlier (Q_ADDR_t)
283 + */
284 +
285 +/*
286 + * structure for tx queue end address reg in global address map
287 + * located at address 0x0004
288 + * Defined earlier (Q_ADDR_t)
289 + */
290 +
291 +/*
292 + * structure for rx queue start address reg in global address map
293 + * located at address 0x0008
294 + * Defined earlier (Q_ADDR_t)
295 + */
296 +
297 +/*
298 + * structure for rx queue end address reg in global address map
299 + * located at address 0x000C
300 + * Defined earlier (Q_ADDR_t)
301 + */
302 +
303 +/*
304 + * structure for power management control status reg in global address map
305 + * located at address 0x0010
306 + */
307 +typedef union _PM_CSR_t {
308 + u32 value;
309 + struct {
310 +#ifdef _BIT_FIELDS_HTOL
311 + u32 unused:22; // bits 10-31
312 + u32 pm_jagcore_rx_rdy:1; // bit 9
313 + u32 pm_jagcore_tx_rdy:1; // bit 8
314 + u32 pm_phy_lped_en:1; // bit 7
315 + u32 pm_phy_sw_coma:1; // bit 6
316 + u32 pm_rxclk_gate:1; // bit 5
317 + u32 pm_txclk_gate:1; // bit 4
318 + u32 pm_sysclk_gate:1; // bit 3
319 + u32 pm_jagcore_rx_en:1; // bit 2
320 + u32 pm_jagcore_tx_en:1; // bit 1
321 + u32 pm_gigephy_en:1; // bit 0
322 +#else
323 + u32 pm_gigephy_en:1; // bit 0
324 + u32 pm_jagcore_tx_en:1; // bit 1
325 + u32 pm_jagcore_rx_en:1; // bit 2
326 + u32 pm_sysclk_gate:1; // bit 3
327 + u32 pm_txclk_gate:1; // bit 4
328 + u32 pm_rxclk_gate:1; // bit 5
329 + u32 pm_phy_sw_coma:1; // bit 6
330 + u32 pm_phy_lped_en:1; // bit 7
331 + u32 pm_jagcore_tx_rdy:1; // bit 8
332 + u32 pm_jagcore_rx_rdy:1; // bit 9
333 + u32 unused:22; // bits 10-31
334 +#endif
335 + } bits;
336 +} PM_CSR_t, *PPM_CSR_t;
337 +
338 +/*
339 + * structure for interrupt status reg in global address map
340 + * located at address 0x0018
341 + */
342 +typedef union _INTERRUPT_t {
343 + u32 value;
344 + struct {
345 +#ifdef _BIT_FIELDS_HTOL
346 + u32 unused5:11; // bits 21-31
347 + u32 slv_timeout:1; // bit 20
348 + u32 mac_stat_interrupt:1; // bit 19
349 + u32 rxmac_interrupt:1; // bit 18
350 + u32 txmac_interrupt:1; // bit 17
351 + u32 phy_interrupt:1; // bit 16
352 + u32 wake_on_lan:1; // bit 15
353 + u32 watchdog_interrupt:1; // bit 14
354 + u32 unused4:4; // bits 10-13
355 + u32 rxdma_err:1; // bit 9
356 + u32 rxdma_pkt_stat_ring_low:1; // bit 8
357 + u32 rxdma_fb_ring1_low:1; // bit 7
358 + u32 rxdma_fb_ring0_low:1; // bit 6
359 + u32 rxdma_xfr_done:1; // bit 5
360 + u32 txdma_err:1; // bit 4
361 + u32 txdma_isr:1; // bit 3
362 + u32 unused3:1; // bit 2
363 + u32 unused2:1; // bit 1
364 + u32 unused1:1; // bit 0
365 +#else
366 + u32 unused1:1; // bit 0
367 + u32 unused2:1; // bit 1
368 + u32 unused3:1; // bit 2
369 + u32 txdma_isr:1; // bit 3
370 + u32 txdma_err:1; // bit 4
371 + u32 rxdma_xfr_done:1; // bit 5
372 + u32 rxdma_fb_ring0_low:1; // bit 6
373 + u32 rxdma_fb_ring1_low:1; // bit 7
374 + u32 rxdma_pkt_stat_ring_low:1; // bit 8
375 + u32 rxdma_err:1; // bit 9
376 + u32 unused4:4; // bits 10-13
377 + u32 watchdog_interrupt:1; // bit 14
378 + u32 wake_on_lan:1; // bit 15
379 + u32 phy_interrupt:1; // bit 16
380 + u32 txmac_interrupt:1; // bit 17
381 + u32 rxmac_interrupt:1; // bit 18
382 + u32 mac_stat_interrupt:1; // bit 19
383 + u32 slv_timeout:1; // bit 20
384 + u32 unused5:11; // bits 21-31
385 +#endif
386 + } bits;
387 +} INTERRUPT_t, *PINTERRUPT_t;
388 +
389 +/*
390 + * structure for interrupt mask reg in global address map
391 + * located at address 0x001C
392 + * Defined earlier (INTERRUPT_t), but 'watchdog_interrupt' is not used.
393 + */
394 +
395 +/*
396 + * structure for interrupt alias clear mask reg in global address map
397 + * located at address 0x0020
398 + * Defined earlier (INTERRUPT_t)
399 + */
400 +
401 +/*
402 + * structure for interrupt status alias reg in global address map
403 + * located at address 0x0024
404 + * Defined earlier (INTERRUPT_t)
405 + */
406 +
407 +/*
408 + * structure for software reset reg in global address map
409 + * located at address 0x0028
410 + */
411 +typedef union _SW_RESET_t {
412 + u32 value;
413 + struct {
414 +#ifdef _BIT_FIELDS_HTOL
415 + u32 selfclr_disable:1; // bit 31
416 + u32 unused:24; // bits 7-30
417 + u32 mmc_sw_reset:1; // bit 6
418 + u32 mac_stat_sw_reset:1; // bit 5
419 + u32 mac_sw_reset:1; // bit 4
420 + u32 rxmac_sw_reset:1; // bit 3
421 + u32 txmac_sw_reset:1; // bit 2
422 + u32 rxdma_sw_reset:1; // bit 1
423 + u32 txdma_sw_reset:1; // bit 0
424 +#else
425 + u32 txdma_sw_reset:1; // bit 0
426 + u32 rxdma_sw_reset:1; // bit 1
427 + u32 txmac_sw_reset:1; // bit 2
428 + u32 rxmac_sw_reset:1; // bit 3
429 + u32 mac_sw_reset:1; // bit 4
430 + u32 mac_stat_sw_reset:1; // bit 5
431 + u32 mmc_sw_reset:1; // bit 6
432 + u32 unused:24; // bits 7-30
433 + u32 selfclr_disable:1; // bit 31
434 +#endif
435 + } bits;
436 +} SW_RESET_t, *PSW_RESET_t;
437 +
438 +/*
439 + * structure for SLV Timer reg in global address map
440 + * located at address 0x002C
441 + */
442 +typedef union _SLV_TIMER_t {
443 + u32 value;
444 + struct {
445 +#ifdef _BIT_FIELDS_HTOL
446 + u32 unused:8; // bits 24-31
447 + u32 timer_ini:24; // bits 0-23
448 +#else
449 + u32 timer_ini:24; // bits 0-23
450 + u32 unused:8; // bits 24-31
451 +#endif
452 + } bits;
453 +} SLV_TIMER_t, *PSLV_TIMER_t;
454 +
455 +/*
456 + * structure for MSI Configuration reg in global address map
457 + * located at address 0x0030
458 + */
459 +typedef union _MSI_CONFIG_t {
460 + u32 value;
461 + struct {
462 +#ifdef _BIT_FIELDS_HTOL
463 + u32 unused1:13; // bits 19-31
464 + u32 msi_tc:3; // bits 16-18
465 + u32 unused2:11; // bits 5-15
466 + u32 msi_vector:5; // bits 0-4
467 +#else
468 + u32 msi_vector:5; // bits 0-4
469 + u32 unused2:11; // bits 5-15
470 + u32 msi_tc:3; // bits 16-18
471 + u32 unused1:13; // bits 19-31
472 +#endif
473 + } bits;
474 +} MSI_CONFIG_t, *PMSI_CONFIG_t;
475 +
476 +/*
477 + * structure for Loopback reg in global address map
478 + * located at address 0x0034
479 + */
480 +typedef union _LOOPBACK_t {
481 + u32 value;
482 + struct {
483 +#ifdef _BIT_FIELDS_HTOL
484 + u32 unused:30; // bits 2-31
485 + u32 dma_loopback:1; // bit 1
486 + u32 mac_loopback:1; // bit 0
487 +#else
488 + u32 mac_loopback:1; // bit 0
489 + u32 dma_loopback:1; // bit 1
490 + u32 unused:30; // bits 2-31
491 +#endif
492 + } bits;
493 +} LOOPBACK_t, *PLOOPBACK_t;
494 +
495 +/*
496 + * GLOBAL Module of JAGCore Address Mapping
497 + * Located at address 0x0000
498 + */
499 +typedef struct _GLOBAL_t { // Location:
500 + Q_ADDR_t txq_start_addr; // 0x0000
501 + Q_ADDR_t txq_end_addr; // 0x0004
502 + Q_ADDR_t rxq_start_addr; // 0x0008
503 + Q_ADDR_t rxq_end_addr; // 0x000C
504 + PM_CSR_t pm_csr; // 0x0010
505 + u32 unused; // 0x0014
506 + INTERRUPT_t int_status; // 0x0018
507 + INTERRUPT_t int_mask; // 0x001C
508 + INTERRUPT_t int_alias_clr_en; // 0x0020
509 + INTERRUPT_t int_status_alias; // 0x0024
510 + SW_RESET_t sw_reset; // 0x0028
511 + SLV_TIMER_t slv_timer; // 0x002C
512 + MSI_CONFIG_t msi_config; // 0x0030
513 + LOOPBACK_t loopback; // 0x0034
514 + u32 watchdog_timer; // 0x0038
515 +} GLOBAL_t, *PGLOBAL_t;
516 +
517 +/* END OF GLOBAL REGISTER ADDRESS MAP */
518 +
519 +
520 +/* START OF TXDMA REGISTER ADDRESS MAP */
521 +
522 +/*
523 + * structure for txdma control status reg in txdma address map
524 + * located at address 0x1000
525 + */
526 +typedef union _TXDMA_CSR_t {
527 + u32 value;
528 + struct {
529 +#ifdef _BIT_FIELDS_HTOL
530 + u32 unused2:19; // bits 13-31
531 + u32 traffic_class:4; // bits 9-12
532 + u32 sngl_epkt_mode:1; // bit 8
533 + u32 cache_thrshld:4; // bits 4-7
534 + u32 unused1:2; // bits 2-3
535 + u32 drop_TLP_disable:1; // bit 1
536 + u32 halt:1; // bit 0
537 +#else
538 + u32 halt:1; // bit 0
539 + u32 drop_TLP_disable:1; // bit 1
540 + u32 unused1:2; // bits 2-3
541 + u32 cache_thrshld:4; // bits 4-7
542 + u32 sngl_epkt_mode:1; // bit 8
543 + u32 traffic_class:4; // bits 9-12
544 + u32 unused2:19; // bits 13-31
545 +#endif
546 + } bits;
547 +} TXDMA_CSR_t, *PTXDMA_CSR_t;
548 +
549 +/*
550 + * structure for txdma packet ring base address hi reg in txdma address map
551 + * located at address 0x1004
552 + * Defined earlier (u32)
553 + */
554 +
555 +/*
556 + * structure for txdma packet ring base address low reg in txdma address map
557 + * located at address 0x1008
558 + * Defined earlier (u32)
559 + */
560 +
561 +/*
562 + * structure for txdma packet ring number of descriptor reg in txdma address
563 + * map. Located at address 0x100C
564 + */
565 +typedef union _TXDMA_PR_NUM_DES_t {
566 + u32 value;
567 + struct {
568 +#ifdef _BIT_FIELDS_HTOL
569 + u32 unused:22; // bits 10-31
570 + u32 pr_ndes:10; // bits 0-9
571 +#else
572 + u32 pr_ndes:10; // bits 0-9
573 + u32 unused:22; // bits 10-31
574 +#endif
575 + } bits;
576 +} TXDMA_PR_NUM_DES_t, *PTXDMA_PR_NUM_DES_t;
577 +
578 +
579 +typedef union _DMA10W_t {
580 + u32 value;
581 + struct {
582 +#ifdef _BIT_FIELDS_HTOL
583 + u32 unused:21; // bits 11-31
584 + u32 wrap:1; // bit 10
585 + u32 val:10; // bits 0-9
586 +#else
587 + u32 val:10; // bits 0-9
588 + u32 wrap:1; // bit 10
589 + u32 unused:21; // bits 11-31
590 +#endif
591 + } bits;
592 +} DMA10W_t, *PDMA10W_t;
593 +
594 +/*
595 + * structure for txdma tx queue write address reg in txdma address map
596 + * located at address 0x1010
597 + * Defined earlier (DMA10W_t)
598 + */
599 +
600 +/*
601 + * structure for txdma tx queue write address external reg in txdma address map
602 + * located at address 0x1014
603 + * Defined earlier (DMA10W_t)
604 + */
605 +
606 +/*
607 + * structure for txdma tx queue read address reg in txdma address map
608 + * located at address 0x1018
609 + * Defined earlier (DMA10W_t)
610 + */
611 +
612 +/*
613 + * structure for txdma status writeback address hi reg in txdma address map
614 + * located at address 0x101C
615 + * Defined earlier (u32)
616 + */
617 +
618 +/*
619 + * structure for txdma status writeback address lo reg in txdma address map
620 + * located at address 0x1020
621 + * Defined earlier (u32)
622 + */
623 +
624 +/*
625 + * structure for txdma service request reg in txdma address map
626 + * located at address 0x1024
627 + * Defined earlier (DMA10W_t)
628 + */
629 +
630 +/*
631 + * structure for txdma service complete reg in txdma address map
632 + * located at address 0x1028
633 + * Defined earlier (DMA10W_t)
634 + */
635 +
636 +typedef union _DMA4W_t {
637 + u32 value;
638 + struct {
639 +#ifdef _BIT_FIELDS_HTOL
640 + u32 unused:27; // bits 5-31
641 + u32 wrap:1; // bit 4
642 + u32 val:4; // bit 0-3
643 +#else
644 + u32 val:4; // bits 0-3
645 + u32 wrap:1; // bit 4
646 + u32 unused:27; // bits 5-31
647 +#endif
648 + } bits;
649 +} DMA4W_t, *PDMA4W_t;
650 +
651 +/*
652 + * structure for txdma tx descriptor cache read index reg in txdma address map
653 + * located at address 0x102C
654 + * Defined earlier (DMA4W_t)
655 + */
656 +
657 +/*
658 + * structure for txdma tx descriptor cache write index reg in txdma address map
659 + * located at address 0x1030
660 + * Defined earlier (DMA4W_t)
661 + */
662 +
663 +/*
664 + * structure for txdma error reg in txdma address map
665 + * located at address 0x1034
666 + */
667 +typedef union _TXDMA_ERROR_t {
668 + u32 value;
669 + struct {
670 +#ifdef _BIT_FIELDS_HTOL
671 + u32 unused3:22; // bits 10-31
672 + u32 WrbkRewind:1; // bit 9
673 + u32 WrbkResend:1; // bit 8
674 + u32 unused2:2; // bits 6-7
675 + u32 DescrRewind:1; // bit 5
676 + u32 DescrResend:1; // bit 4
677 + u32 unused1:2; // bits 2-3
678 + u32 PyldRewind:1; // bit 1
679 + u32 PyldResend:1; // bit 0
680 +#else
681 + u32 PyldResend:1; // bit 0
682 + u32 PyldRewind:1; // bit 1
683 + u32 unused1:2; // bits 2-3
684 + u32 DescrResend:1; // bit 4
685 + u32 DescrRewind:1; // bit 5
686 + u32 unused2:2; // bits 6-7
687 + u32 WrbkResend:1; // bit 8
688 + u32 WrbkRewind:1; // bit 9
689 + u32 unused3:22; // bits 10-31
690 +#endif
691 + } bits;
692 +} TXDMA_ERROR_t, *PTXDMA_ERROR_t;
693 +
694 +/*
695 + * Tx DMA Module of JAGCore Address Mapping
696 + * Located at address 0x1000
697 + */
698 +typedef struct _TXDMA_t { // Location:
699 + TXDMA_CSR_t csr; // 0x1000
700 + u32 pr_base_hi; // 0x1004
701 + u32 pr_base_lo; // 0x1008
702 + TXDMA_PR_NUM_DES_t pr_num_des; // 0x100C
703 + DMA10W_t txq_wr_addr; // 0x1010
704 + DMA10W_t txq_wr_addr_ext; // 0x1014
705 + DMA10W_t txq_rd_addr; // 0x1018
706 + u32 dma_wb_base_hi; // 0x101C
707 + u32 dma_wb_base_lo; // 0x1020
708 + DMA10W_t service_request; // 0x1024
709 + DMA10W_t service_complete; // 0x1028
710 + DMA4W_t cache_rd_index; // 0x102C
711 + DMA4W_t cache_wr_index; // 0x1030
712 + TXDMA_ERROR_t TxDmaError; // 0x1034
713 + u32 DescAbortCount; // 0x1038
714 + u32 PayloadAbortCnt; // 0x103c
715 + u32 WriteBackAbortCnt; // 0x1040
716 + u32 DescTimeoutCnt; // 0x1044
717 + u32 PayloadTimeoutCnt; // 0x1048
718 + u32 WriteBackTimeoutCnt; // 0x104c
719 + u32 DescErrorCount; // 0x1050
720 + u32 PayloadErrorCnt; // 0x1054
721 + u32 WriteBackErrorCnt; // 0x1058
722 + u32 DroppedTLPCount; // 0x105c
723 + DMA10W_t NewServiceComplete; // 0x1060
724 + u32 EthernetPacketCount; // 0x1064
725 +} TXDMA_t, *PTXDMA_t;
726 +
727 +/* END OF TXDMA REGISTER ADDRESS MAP */
728 +
729 +
730 +/* START OF RXDMA REGISTER ADDRESS MAP */
731 +
732 +/*
733 + * structure for control status reg in rxdma address map
734 + * Located at address 0x2000
735 + */
736 +typedef union _RXDMA_CSR_t {
737 + u32 value;
738 + struct {
739 +#ifdef _BIT_FIELDS_HTOL
740 + u32 unused2:14; // bits 18-31
741 + u32 halt_status:1; // bit 17
742 + u32 pkt_done_flush:1; // bit 16
743 + u32 pkt_drop_disable:1; // bit 15
744 + u32 unused1:1; // bit 14
745 + u32 fbr1_enable:1; // bit 13
746 + u32 fbr1_size:2; // bits 11-12
747 + u32 fbr0_enable:1; // bit 10
748 + u32 fbr0_size:2; // bits 8-9
749 + u32 dma_big_endian:1; // bit 7
750 + u32 pkt_big_endian:1; // bit 6
751 + u32 psr_big_endian:1; // bit 5
752 + u32 fbr_big_endian:1; // bit 4
753 + u32 tc:3; // bits 1-3
754 + u32 halt:1; // bit 0
755 +#else
756 + u32 halt:1; // bit 0
757 + u32 tc:3; // bits 1-3
758 + u32 fbr_big_endian:1; // bit 4
759 + u32 psr_big_endian:1; // bit 5
760 + u32 pkt_big_endian:1; // bit 6
761 + u32 dma_big_endian:1; // bit 7
762 + u32 fbr0_size:2; // bits 8-9
763 + u32 fbr0_enable:1; // bit 10
764 + u32 fbr1_size:2; // bits 11-12
765 + u32 fbr1_enable:1; // bit 13
766 + u32 unused1:1; // bit 14
767 + u32 pkt_drop_disable:1; // bit 15
768 + u32 pkt_done_flush:1; // bit 16
769 + u32 halt_status:1; // bit 17
770 + u32 unused2:14; // bits 18-31
771 +#endif
772 + } bits;
773 +} RXDMA_CSR_t, *PRXDMA_CSR_t;
774 +
775 +/*
776 + * structure for dma writeback lo reg in rxdma address map
777 + * located at address 0x2004
778 + * Defined earlier (u32)
779 + */
780 +
781 +/*
782 + * structure for dma writeback hi reg in rxdma address map
783 + * located at address 0x2008
784 + * Defined earlier (u32)
785 + */
786 +
787 +/*
788 + * structure for number of packets done reg in rxdma address map
789 + * located at address 0x200C
790 + */
791 +typedef union _RXDMA_NUM_PKT_DONE_t {
792 + u32 value;
793 + struct {
794 +#ifdef _BIT_FIELDS_HTOL
795 + u32 unused:24; // bits 8-31
796 + u32 num_done:8; // bits 0-7
797 +#else
798 + u32 num_done:8; // bits 0-7
799 + u32 unused:24; // bits 8-31
800 +#endif
801 + } bits;
802 +} RXDMA_NUM_PKT_DONE_t, *PRXDMA_NUM_PKT_DONE_t;
803 +
804 +/*
805 + * structure for max packet time reg in rxdma address map
806 + * located at address 0x2010
807 + */
808 +typedef union _RXDMA_MAX_PKT_TIME_t {
809 + u32 value;
810 + struct {
811 +#ifdef _BIT_FIELDS_HTOL
812 + u32 unused:14; // bits 18-31
813 + u32 time_done:18; // bits 0-17
814 +#else
815 + u32 time_done:18; // bits 0-17
816 + u32 unused:14; // bits 18-31
817 +#endif
818 + } bits;
819 +} RXDMA_MAX_PKT_TIME_t, *PRXDMA_MAX_PKT_TIME_t;
820 +
821 +/*
822 + * structure for rx queue read address reg in rxdma address map
823 + * located at address 0x2014
824 + * Defined earlier (DMA10W_t)
825 + */
826 +
827 +/*
828 + * structure for rx queue read address external reg in rxdma address map
829 + * located at address 0x2018
830 + * Defined earlier (DMA10W_t)
831 + */
832 +
833 +/*
834 + * structure for rx queue write address reg in rxdma address map
835 + * located at address 0x201C
836 + * Defined earlier (DMA10W_t)
837 + */
838 +
839 +/*
840 + * structure for packet status ring base address lo reg in rxdma address map
841 + * located at address 0x2020
842 + * Defined earlier (u32)
843 + */
844 +
845 +/*
846 + * structure for packet status ring base address hi reg in rxdma address map
847 + * located at address 0x2024
848 + * Defined earlier (u32)
849 + */
850 +
851 +/*
852 + * structure for packet status ring number of descriptors reg in rxdma address
853 + * map. Located at address 0x2028
854 + */
855 +typedef union _RXDMA_PSR_NUM_DES_t {
856 + u32 value;
857 + struct {
858 +#ifdef _BIT_FIELDS_HTOL
859 + u32 unused:20; // bits 12-31
860 + u32 psr_ndes:12; // bit 0-11
861 +#else
862 + u32 psr_ndes:12; // bit 0-11
863 + u32 unused:20; // bits 12-31
864 +#endif
865 + } bits;
866 +} RXDMA_PSR_NUM_DES_t, *PRXDMA_PSR_NUM_DES_t;
867 +
868 +/*
869 + * structure for packet status ring available offset reg in rxdma address map
870 + * located at address 0x202C
871 + */
872 +typedef union _RXDMA_PSR_AVAIL_OFFSET_t {
873 + u32 value;
874 + struct {
875 +#ifdef _BIT_FIELDS_HTOL
876 + u32 unused:19; // bits 13-31
877 + u32 psr_avail_wrap:1; // bit 12
878 + u32 psr_avail:12; // bit 0-11
879 +#else
880 + u32 psr_avail:12; // bit 0-11
881 + u32 psr_avail_wrap:1; // bit 12
882 + u32 unused:19; // bits 13-31
883 +#endif
884 + } bits;
885 +} RXDMA_PSR_AVAIL_OFFSET_t, *PRXDMA_PSR_AVAIL_OFFSET_t;
886 +
887 +/*
888 + * structure for packet status ring full offset reg in rxdma address map
889 + * located at address 0x2030
890 + */
891 +typedef union _RXDMA_PSR_FULL_OFFSET_t {
892 + u32 value;
893 + struct {
894 +#ifdef _BIT_FIELDS_HTOL
895 + u32 unused:19; // bits 13-31
896 + u32 psr_full_wrap:1; // bit 12
897 + u32 psr_full:12; // bit 0-11
898 +#else
899 + u32 psr_full:12; // bit 0-11
900 + u32 psr_full_wrap:1; // bit 12
901 + u32 unused:19; // bits 13-31
902 +#endif
903 + } bits;
904 +} RXDMA_PSR_FULL_OFFSET_t, *PRXDMA_PSR_FULL_OFFSET_t;
905 +
906 +/*
907 + * structure for packet status ring access index reg in rxdma address map
908 + * located at address 0x2034
909 + */
910 +typedef union _RXDMA_PSR_ACCESS_INDEX_t {
911 + u32 value;
912 + struct {
913 +#ifdef _BIT_FIELDS_HTOL
914 + u32 unused:27; // bits 5-31
915 + u32 psr_ai:5; // bits 0-4
916 +#else
917 + u32 psr_ai:5; // bits 0-4
918 + u32 unused:27; // bits 5-31
919 +#endif
920 + } bits;
921 +} RXDMA_PSR_ACCESS_INDEX_t, *PRXDMA_PSR_ACCESS_INDEX_t;
922 +
923 +/*
924 + * structure for packet status ring minimum descriptors reg in rxdma address
925 + * map. Located at address 0x2038
926 + */
927 +typedef union _RXDMA_PSR_MIN_DES_t {
928 + u32 value;
929 + struct {
930 +#ifdef _BIT_FIELDS_HTOL
931 + u32 unused:20; // bits 12-31
932 + u32 psr_min:12; // bits 0-11
933 +#else
934 + u32 psr_min:12; // bits 0-11
935 + u32 unused:20; // bits 12-31
936 +#endif
937 + } bits;
938 +} RXDMA_PSR_MIN_DES_t, *PRXDMA_PSR_MIN_DES_t;
939 +
940 +/*
941 + * structure for free buffer ring base lo address reg in rxdma address map
942 + * located at address 0x203C
943 + * Defined earlier (u32)
944 + */
945 +
946 +/*
947 + * structure for free buffer ring base hi address reg in rxdma address map
948 + * located at address 0x2040
949 + * Defined earlier (u32)
950 + */
951 +
952 +/*
953 + * structure for free buffer ring number of descriptors reg in rxdma address
954 + * map. Located at address 0x2044
955 + */
956 +typedef union _RXDMA_FBR_NUM_DES_t {
957 + u32 value;
958 + struct {
959 +#ifdef _BIT_FIELDS_HTOL
960 + u32 unused:22; // bits 10-31
961 + u32 fbr_ndesc:10; // bits 0-9
962 +#else
963 + u32 fbr_ndesc:10; // bits 0-9
964 + u32 unused:22; // bits 10-31
965 +#endif
966 + } bits;
967 +} RXDMA_FBR_NUM_DES_t, *PRXDMA_FBR_NUM_DES_t;
968 +
969 +/*
970 + * structure for free buffer ring 0 available offset reg in rxdma address map
971 + * located at address 0x2048
972 + * Defined earlier (DMA10W_t)
973 + */
974 +
975 +/*
976 + * structure for free buffer ring 0 full offset reg in rxdma address map
977 + * located at address 0x204C
978 + * Defined earlier (DMA10W_t)
979 + */
980 +
981 +/*
982 + * structure for free buffer cache 0 full offset reg in rxdma address map
983 + * located at address 0x2050
984 + */
985 +typedef union _RXDMA_FBC_RD_INDEX_t {
986 + u32 value;
987 + struct {
988 +#ifdef _BIT_FIELDS_HTOL
989 + u32 unused:27; // bits 5-31
990 + u32 fbc_rdi:5; // bit 0-4
991 +#else
992 + u32 fbc_rdi:5; // bit 0-4
993 + u32 unused:27; // bits 5-31
994 +#endif
995 + } bits;
996 +} RXDMA_FBC_RD_INDEX_t, *PRXDMA_FBC_RD_INDEX_t;
997 +
998 +/*
999 + * structure for free buffer ring 0 minimum descriptor reg in rxdma address map
1000 + * located at address 0x2054
1001 + */
1002 +typedef union _RXDMA_FBR_MIN_DES_t {
1003 + u32 value;
1004 + struct {
1005 +#ifdef _BIT_FIELDS_HTOL
1006 + u32 unused:22; // bits 10-31
1007 + u32 fbr_min:10; // bits 0-9
1008 +#else
1009 + u32 fbr_min:10; // bits 0-9
1010 + u32 unused:22; // bits 10-31
1011 +#endif
1012 + } bits;
1013 +} RXDMA_FBR_MIN_DES_t, *PRXDMA_FBR_MIN_DES_t;
1014 +
1015 +/*
1016 + * structure for free buffer ring 1 base address lo reg in rxdma address map
1017 + * located at address 0x2058 - 0x205C
1018 + * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
1019 + */
1020 +
1021 +/*
1022 + * structure for free buffer ring 1 number of descriptors reg in rxdma address
1023 + * map. Located at address 0x2060
1024 + * Defined earlier (RXDMA_FBR_NUM_DES_t)
1025 + */
1026 +
1027 +/*
1028 + * structure for free buffer ring 1 available offset reg in rxdma address map
1029 + * located at address 0x2064
1030 + * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
1031 + */
1032 +
1033 +/*
1034 + * structure for free buffer ring 1 full offset reg in rxdma address map
1035 + * located at address 0x2068
1036 + * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
1037 + */
1038 +
1039 +/*
1040 + * structure for free buffer cache 1 read index reg in rxdma address map
1041 + * located at address 0x206C
1042 + * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
1043 + */
1044 +
1045 +/*
1046 + * structure for free buffer ring 1 minimum descriptor reg in rxdma address map
1047 + * located at address 0x2070
1048 + * Defined Earlier (RXDMA_FBR_MIN_DES_t)
1049 + */
1050 +
1051 +/*
1052 + * Rx DMA Module of JAGCore Address Mapping
1053 + * Located at address 0x2000
1054 + */
1055 +typedef struct _RXDMA_t { // Location:
1056 + RXDMA_CSR_t csr; // 0x2000
1057 + u32 dma_wb_base_lo; // 0x2004
1058 + u32 dma_wb_base_hi; // 0x2008
1059 + RXDMA_NUM_PKT_DONE_t num_pkt_done; // 0x200C
1060 + RXDMA_MAX_PKT_TIME_t max_pkt_time; // 0x2010
1061 + DMA10W_t rxq_rd_addr; // 0x2014
1062 + DMA10W_t rxq_rd_addr_ext; // 0x2018
1063 + DMA10W_t rxq_wr_addr; // 0x201C
1064 + u32 psr_base_lo; // 0x2020
1065 + u32 psr_base_hi; // 0x2024
1066 + RXDMA_PSR_NUM_DES_t psr_num_des; // 0x2028
1067 + RXDMA_PSR_AVAIL_OFFSET_t psr_avail_offset; // 0x202C
1068 + RXDMA_PSR_FULL_OFFSET_t psr_full_offset; // 0x2030
1069 + RXDMA_PSR_ACCESS_INDEX_t psr_access_index; // 0x2034
1070 + RXDMA_PSR_MIN_DES_t psr_min_des; // 0x2038
1071 + u32 fbr0_base_lo; // 0x203C
1072 + u32 fbr0_base_hi; // 0x2040
1073 + RXDMA_FBR_NUM_DES_t fbr0_num_des; // 0x2044
1074 + DMA10W_t fbr0_avail_offset; // 0x2048
1075 + DMA10W_t fbr0_full_offset; // 0x204C
1076 + RXDMA_FBC_RD_INDEX_t fbr0_rd_index; // 0x2050
1077 + RXDMA_FBR_MIN_DES_t fbr0_min_des; // 0x2054
1078 + u32 fbr1_base_lo; // 0x2058
1079 + u32 fbr1_base_hi; // 0x205C
1080 + RXDMA_FBR_NUM_DES_t fbr1_num_des; // 0x2060
1081 + DMA10W_t fbr1_avail_offset; // 0x2064
1082 + DMA10W_t fbr1_full_offset; // 0x2068
1083 + RXDMA_FBC_RD_INDEX_t fbr1_rd_index; // 0x206C
1084 + RXDMA_FBR_MIN_DES_t fbr1_min_des; // 0x2070
1085 +} RXDMA_t, *PRXDMA_t;
1086 +
1087 +/* END OF RXDMA REGISTER ADDRESS MAP */
1088 +
1089 +
1090 +/* START OF TXMAC REGISTER ADDRESS MAP */
1091 +
1092 +/*
1093 + * structure for control reg in txmac address map
1094 + * located at address 0x3000
1095 + */
1096 +typedef union _TXMAC_CTL_t {
1097 + u32 value;
1098 + struct {
1099 +#ifdef _BIT_FIELDS_HTOL
1100 + u32 unused:24; // bits 8-31
1101 + u32 cklseg_diable:1; // bit 7
1102 + u32 ckbcnt_disable:1; // bit 6
1103 + u32 cksegnum:1; // bit 5
1104 + u32 async_disable:1; // bit 4
1105 + u32 fc_disable:1; // bit 3
1106 + u32 mcif_disable:1; // bit 2
1107 + u32 mif_disable:1; // bit 1
1108 + u32 txmac_en:1; // bit 0
1109 +#else
1110 + u32 txmac_en:1; // bit 0
1111 + u32 mif_disable:1; // bit 1 mac interface
1112 + u32 mcif_disable:1; // bit 2 mem. contr. interface
1113 + u32 fc_disable:1; // bit 3
1114 + u32 async_disable:1; // bit 4
1115 + u32 cksegnum:1; // bit 5
1116 + u32 ckbcnt_disable:1; // bit 6
1117 + u32 cklseg_diable:1; // bit 7
1118 + u32 unused:24; // bits 8-31
1119 +#endif
1120 + } bits;
1121 +} TXMAC_CTL_t, *PTXMAC_CTL_t;
1122 +
1123 +/*
1124 + * structure for shadow pointer reg in txmac address map
1125 + * located at address 0x3004
1126 + */
1127 +typedef union _TXMAC_SHADOW_PTR_t {
1128 + u32 value;
1129 + struct {
1130 +#ifdef _BIT_FIELDS_HTOL
1131 + u32 reserved2:5; // bits 27-31
1132 + u32 txq_rd_ptr:11; // bits 16-26
1133 + u32 reserved:5; // bits 11-15
1134 + u32 txq_wr_ptr:11; // bits 0-10
1135 +#else
1136 + u32 txq_wr_ptr:11; // bits 0-10
1137 + u32 reserved:5; // bits 11-15
1138 + u32 txq_rd_ptr:11; // bits 16-26
1139 + u32 reserved2:5; // bits 27-31
1140 +#endif
1141 + } bits;
1142 +} TXMAC_SHADOW_PTR_t, *PTXMAC_SHADOW_PTR_t;
1143 +
1144 +/*
1145 + * structure for error count reg in txmac address map
1146 + * located at address 0x3008
1147 + */
1148 +typedef union _TXMAC_ERR_CNT_t {
1149 + u32 value;
1150 + struct {
1151 +#ifdef _BIT_FIELDS_HTOL
1152 + u32 unused:20; // bits 12-31
1153 + u32 reserved:4; // bits 8-11
1154 + u32 txq_underrun:4; // bits 4-7
1155 + u32 fifo_underrun:4; // bits 0-3
1156 +#else
1157 + u32 fifo_underrun:4; // bits 0-3
1158 + u32 txq_underrun:4; // bits 4-7
1159 + u32 reserved:4; // bits 8-11
1160 + u32 unused:20; // bits 12-31
1161 +#endif
1162 + } bits;
1163 +} TXMAC_ERR_CNT_t, *PTXMAC_ERR_CNT_t;
1164 +
1165 +/*
1166 + * structure for max fill reg in txmac address map
1167 + * located at address 0x300C
1168 + */
1169 +typedef union _TXMAC_MAX_FILL_t {
1170 + u32 value;
1171 + struct {
1172 +#ifdef _BIT_FIELDS_HTOL
1173 + u32 unused:20; // bits 12-31
1174 + u32 max_fill:12; // bits 0-11
1175 +#else
1176 + u32 max_fill:12; // bits 0-11
1177 + u32 unused:20; // bits 12-31
1178 +#endif
1179 + } bits;
1180 +} TXMAC_MAX_FILL_t, *PTXMAC_MAX_FILL_t;
1181 +
1182 +/*
1183 + * structure for cf parameter reg in txmac address map
1184 + * located at address 0x3010
1185 + */
1186 +typedef union _TXMAC_CF_PARAM_t {
1187 + u32 value;
1188 + struct {
1189 +#ifdef _BIT_FIELDS_HTOL
1190 + u32 cfep:16; // bits 16-31
1191 + u32 cfpt:16; // bits 0-15
1192 +#else
1193 + u32 cfpt:16; // bits 0-15
1194 + u32 cfep:16; // bits 16-31
1195 +#endif
1196 + } bits;
1197 +} TXMAC_CF_PARAM_t, *PTXMAC_CF_PARAM_t;
1198 +
1199 +/*
1200 + * structure for tx test reg in txmac address map
1201 + * located at address 0x3014
1202 + */
1203 +typedef union _TXMAC_TXTEST_t {
1204 + u32 value;
1205 + struct {
1206 +#ifdef _BIT_FIELDS_HTOL
1207 + u32 unused2:15; // bits 17-31
1208 + u32 reserved1:1; // bit 16
1209 + u32 txtest_en:1; // bit 15
1210 + u32 unused1:4; // bits 11-14
1211 + u32 txqtest_ptr:11; // bits 0-11
1212 +#else
1213 + u32 txqtest_ptr:11; // bits 0-10
1214 + u32 unused1:4; // bits 11-14
1215 + u32 txtest_en:1; // bit 15
1216 + u32 reserved1:1; // bit 16
1217 + u32 unused2:15; // bits 17-31
1218 +#endif
1219 + } bits;
1220 +} TXMAC_TXTEST_t, *PTXMAC_TXTEST_t;
1221 +
1222 +/*
1223 + * structure for error reg in txmac address map
1224 + * located at address 0x3018
1225 + */
1226 +typedef union _TXMAC_ERR_t {
1227 + u32 value;
1228 + struct {
1229 +#ifdef _BIT_FIELDS_HTOL
1230 + u32 unused2:23; // bits 9-31
1231 + u32 fifo_underrun:1; // bit 8
1232 + u32 unused1:2; // bits 6-7
1233 + u32 ctrl2_err:1; // bit 5
1234 + u32 txq_underrun:1; // bit 4
1235 + u32 bcnt_err:1; // bit 3
1236 + u32 lseg_err:1; // bit 2
1237 + u32 segnum_err:1; // bit 1
1238 + u32 seg0_err:1; // bit 0
1239 +#else
1240 + u32 seg0_err:1; // bit 0
1241 + u32 segnum_err:1; // bit 1
1242 + u32 lseg_err:1; // bit 2
1243 + u32 bcnt_err:1; // bit 3
1244 + u32 txq_underrun:1; // bit 4
1245 + u32 ctrl2_err:1; // bit 5
1246 + u32 unused1:2; // bits 6-7
1247 + u32 fifo_underrun:1; // bit 8
1248 + u32 unused2:23; // bits 9-31
1249 +#endif
1250 + } bits;
1251 +} TXMAC_ERR_t, *PTXMAC_ERR_t;
1252 +
1253 +/*
1254 + * structure for error interrupt reg in txmac address map
1255 + * located at address 0x301C
1256 + */
1257 +typedef union _TXMAC_ERR_INT_t {
1258 + u32 value;
1259 + struct {
1260 +#ifdef _BIT_FIELDS_HTOL
1261 + u32 unused2:23; // bits 9-31
1262 + u32 fifo_underrun:1; // bit 8
1263 + u32 unused1:2; // bits 6-7
1264 + u32 ctrl2_err:1; // bit 5
1265 + u32 txq_underrun:1; // bit 4
1266 + u32 bcnt_err:1; // bit 3
1267 + u32 lseg_err:1; // bit 2
1268 + u32 segnum_err:1; // bit 1
1269 + u32 seg0_err:1; // bit 0
1270 +#else
1271 + u32 seg0_err:1; // bit 0
1272 + u32 segnum_err:1; // bit 1
1273 + u32 lseg_err:1; // bit 2
1274 + u32 bcnt_err:1; // bit 3
1275 + u32 txq_underrun:1; // bit 4
1276 + u32 ctrl2_err:1; // bit 5
1277 + u32 unused1:2; // bits 6-7
1278 + u32 fifo_underrun:1; // bit 8
1279 + u32 unused2:23; // bits 9-31
1280 +#endif
1281 + } bits;
1282 +} TXMAC_ERR_INT_t, *PTXMAC_ERR_INT_t;
1283 +
1284 +/*
1285 + * structure for error interrupt reg in txmac address map
1286 + * located at address 0x3020
1287 + */
1288 +typedef union _TXMAC_CP_CTRL_t {
1289 + u32 value;
1290 + struct {
1291 +#ifdef _BIT_FIELDS_HTOL
1292 + u32 unused:30; // bits 2-31
1293 + u32 bp_req:1; // bit 1
1294 + u32 bp_xonxoff:1; // bit 0
1295 +#else
1296 + u32 bp_xonxoff:1; // bit 0
1297 + u32 bp_req:1; // bit 1
1298 + u32 unused:30; // bits 2-31
1299 +#endif
1300 + } bits;
1301 +} TXMAC_BP_CTRL_t, *PTXMAC_BP_CTRL_t;
1302 +
1303 +/*
1304 + * Tx MAC Module of JAGCore Address Mapping
1305 + */
1306 +typedef struct _TXMAC_t { // Location:
1307 + TXMAC_CTL_t ctl; // 0x3000
1308 + TXMAC_SHADOW_PTR_t shadow_ptr; // 0x3004
1309 + TXMAC_ERR_CNT_t err_cnt; // 0x3008
1310 + TXMAC_MAX_FILL_t max_fill; // 0x300C
1311 + TXMAC_CF_PARAM_t cf_param; // 0x3010
1312 + TXMAC_TXTEST_t tx_test; // 0x3014
1313 + TXMAC_ERR_t err; // 0x3018
1314 + TXMAC_ERR_INT_t err_int; // 0x301C
1315 + TXMAC_BP_CTRL_t bp_ctrl; // 0x3020
1316 +} TXMAC_t, *PTXMAC_t;
1317 +
1318 +/* END OF TXMAC REGISTER ADDRESS MAP */
1319 +
1320 +/* START OF RXMAC REGISTER ADDRESS MAP */
1321 +
1322 +/*
1323 + * structure for rxmac control reg in rxmac address map
1324 + * located at address 0x4000
1325 + */
1326 +typedef union _RXMAC_CTRL_t {
1327 + u32 value;
1328 + struct {
1329 +#ifdef _BIT_FIELDS_HTOL
1330 + u32 reserved:25; // bits 7-31
1331 + u32 rxmac_int_disable:1; // bit 6
1332 + u32 async_disable:1; // bit 5
1333 + u32 mif_disable:1; // bit 4
1334 + u32 wol_disable:1; // bit 3
1335 + u32 pkt_filter_disable:1; // bit 2
1336 + u32 mcif_disable:1; // bit 1
1337 + u32 rxmac_en:1; // bit 0
1338 +#else
1339 + u32 rxmac_en:1; // bit 0
1340 + u32 mcif_disable:1; // bit 1
1341 + u32 pkt_filter_disable:1; // bit 2
1342 + u32 wol_disable:1; // bit 3
1343 + u32 mif_disable:1; // bit 4
1344 + u32 async_disable:1; // bit 5
1345 + u32 rxmac_int_disable:1; // bit 6
1346 + u32 reserved:25; // bits 7-31
1347 +#endif
1348 + } bits;
1349 +} RXMAC_CTRL_t, *PRXMAC_CTRL_t;
1350 +
1351 +/*
1352 + * structure for Wake On Lan Control and CRC 0 reg in rxmac address map
1353 + * located at address 0x4004
1354 + */
1355 +typedef union _RXMAC_WOL_CTL_CRC0_t {
1356 + u32 value;
1357 + struct {
1358 +#ifdef _BIT_FIELDS_HTOL
1359 + u32 crc0:16; // bits 16-31
1360 + u32 reserve:4; // bits 12-15
1361 + u32 ignore_pp:1; // bit 11
1362 + u32 ignore_mp:1; // bit 10
1363 + u32 clr_intr:1; // bit 9
1364 + u32 ignore_link_chg:1; // bit 8
1365 + u32 ignore_uni:1; // bit 7
1366 + u32 ignore_multi:1; // bit 6
1367 + u32 ignore_broad:1; // bit 5
1368 + u32 valid_crc4:1; // bit 4
1369 + u32 valid_crc3:1; // bit 3
1370 + u32 valid_crc2:1; // bit 2
1371 + u32 valid_crc1:1; // bit 1
1372 + u32 valid_crc0:1; // bit 0
1373 +#else
1374 + u32 valid_crc0:1; // bit 0
1375 + u32 valid_crc1:1; // bit 1
1376 + u32 valid_crc2:1; // bit 2
1377 + u32 valid_crc3:1; // bit 3
1378 + u32 valid_crc4:1; // bit 4
1379 + u32 ignore_broad:1; // bit 5
1380 + u32 ignore_multi:1; // bit 6
1381 + u32 ignore_uni:1; // bit 7
1382 + u32 ignore_link_chg:1; // bit 8
1383 + u32 clr_intr:1; // bit 9
1384 + u32 ignore_mp:1; // bit 10
1385 + u32 ignore_pp:1; // bit 11
1386 + u32 reserve:4; // bits 12-15
1387 + u32 crc0:16; // bits 16-31
1388 +#endif
1389 + } bits;
1390 +} RXMAC_WOL_CTL_CRC0_t, *PRXMAC_WOL_CTL_CRC0_t;
1391 +
1392 +/*
1393 + * structure for CRC 1 and CRC 2 reg in rxmac address map
1394 + * located at address 0x4008
1395 + */
1396 +typedef union _RXMAC_WOL_CRC12_t {
1397 + u32 value;
1398 + struct {
1399 +#ifdef _BIT_FIELDS_HTOL
1400 + u32 crc2:16; // bits 16-31
1401 + u32 crc1:16; // bits 0-15
1402 +#else
1403 + u32 crc1:16; // bits 0-15
1404 + u32 crc2:16; // bits 16-31
1405 +#endif
1406 + } bits;
1407 +} RXMAC_WOL_CRC12_t, *PRXMAC_WOL_CRC12_t;
1408 +
1409 +/*
1410 + * structure for CRC 3 and CRC 4 reg in rxmac address map
1411 + * located at address 0x400C
1412 + */
1413 +typedef union _RXMAC_WOL_CRC34_t {
1414 + u32 value;
1415 + struct {
1416 +#ifdef _BIT_FIELDS_HTOL
1417 + u32 crc4:16; // bits 16-31
1418 + u32 crc3:16; // bits 0-15
1419 +#else
1420 + u32 crc3:16; // bits 0-15
1421 + u32 crc4:16; // bits 16-31
1422 +#endif
1423 + } bits;
1424 +} RXMAC_WOL_CRC34_t, *PRXMAC_WOL_CRC34_t;
1425 +
1426 +/*
1427 + * structure for Wake On Lan Source Address Lo reg in rxmac address map
1428 + * located at address 0x4010
1429 + */
1430 +typedef union _RXMAC_WOL_SA_LO_t {
1431 + u32 value;
1432 + struct {
1433 +#ifdef _BIT_FIELDS_HTOL
1434 + u32 sa3:8; // bits 24-31
1435 + u32 sa4:8; // bits 16-23
1436 + u32 sa5:8; // bits 8-15
1437 + u32 sa6:8; // bits 0-7
1438 +#else
1439 + u32 sa6:8; // bits 0-7
1440 + u32 sa5:8; // bits 8-15
1441 + u32 sa4:8; // bits 16-23
1442 + u32 sa3:8; // bits 24-31
1443 +#endif
1444 + } bits;
1445 +} RXMAC_WOL_SA_LO_t, *PRXMAC_WOL_SA_LO_t;
1446 +
1447 +/*
1448 + * structure for Wake On Lan Source Address Hi reg in rxmac address map
1449 + * located at address 0x4014
1450 + */
1451 +typedef union _RXMAC_WOL_SA_HI_t {
1452 + u32 value;
1453 + struct {
1454 +#ifdef _BIT_FIELDS_HTOL
1455 + u32 reserved:16; // bits 16-31
1456 + u32 sa1:8; // bits 8-15
1457 + u32 sa2:8; // bits 0-7
1458 +#else
1459 + u32 sa2:8; // bits 0-7
1460 + u32 sa1:8; // bits 8-15
1461 + u32 reserved:16; // bits 16-31
1462 +#endif
1463 + } bits;
1464 +} RXMAC_WOL_SA_HI_t, *PRXMAC_WOL_SA_HI_t;
1465 +
1466 +/*
1467 + * structure for Wake On Lan mask reg in rxmac address map
1468 + * located at address 0x4018 - 0x4064
1469 + * Defined earlier (u32)
1470 + */
1471 +
1472 +/*
1473 + * structure for Unicast Paket Filter Address 1 reg in rxmac address map
1474 + * located at address 0x4068
1475 + */
1476 +typedef union _RXMAC_UNI_PF_ADDR1_t {
1477 + u32 value;
1478 + struct {
1479 +#ifdef _BIT_FIELDS_HTOL
1480 + u32 addr1_3:8; // bits 24-31
1481 + u32 addr1_4:8; // bits 16-23
1482 + u32 addr1_5:8; // bits 8-15
1483 + u32 addr1_6:8; // bits 0-7
1484 +#else
1485 + u32 addr1_6:8; // bits 0-7
1486 + u32 addr1_5:8; // bits 8-15
1487 + u32 addr1_4:8; // bits 16-23
1488 + u32 addr1_3:8; // bits 24-31
1489 +#endif
1490 + } bits;
1491 +} RXMAC_UNI_PF_ADDR1_t, *PRXMAC_UNI_PF_ADDR1_t;
1492 +
1493 +/*
1494 + * structure for Unicast Paket Filter Address 2 reg in rxmac address map
1495 + * located at address 0x406C
1496 + */
1497 +typedef union _RXMAC_UNI_PF_ADDR2_t {
1498 + u32 value;
1499 + struct {
1500 +#ifdef _BIT_FIELDS_HTOL
1501 + u32 addr2_3:8; // bits 24-31
1502 + u32 addr2_4:8; // bits 16-23
1503 + u32 addr2_5:8; // bits 8-15
1504 + u32 addr2_6:8; // bits 0-7
1505 +#else
1506 + u32 addr2_6:8; // bits 0-7
1507 + u32 addr2_5:8; // bits 8-15
1508 + u32 addr2_4:8; // bits 16-23
1509 + u32 addr2_3:8; // bits 24-31
1510 +#endif
1511 + } bits;
1512 +} RXMAC_UNI_PF_ADDR2_t, *PRXMAC_UNI_PF_ADDR2_t;
1513 +
1514 +/*
1515 + * structure for Unicast Paket Filter Address 1 & 2 reg in rxmac address map
1516 + * located at address 0x4070
1517 + */
1518 +typedef union _RXMAC_UNI_PF_ADDR3_t {
1519 + u32 value;
1520 + struct {
1521 +#ifdef _BIT_FIELDS_HTOL
1522 + u32 addr2_1:8; // bits 24-31
1523 + u32 addr2_2:8; // bits 16-23
1524 + u32 addr1_1:8; // bits 8-15
1525 + u32 addr1_2:8; // bits 0-7
1526 +#else
1527 + u32 addr1_2:8; // bits 0-7
1528 + u32 addr1_1:8; // bits 8-15
1529 + u32 addr2_2:8; // bits 16-23
1530 + u32 addr2_1:8; // bits 24-31
1531 +#endif
1532 + } bits;
1533 +} RXMAC_UNI_PF_ADDR3_t, *PRXMAC_UNI_PF_ADDR3_t;
1534 +
1535 +/*
1536 + * structure for Multicast Hash reg in rxmac address map
1537 + * located at address 0x4074 - 0x4080
1538 + * Defined earlier (u32)
1539 + */
1540 +
1541 +/*
1542 + * structure for Packet Filter Control reg in rxmac address map
1543 + * located at address 0x4084
1544 + */
1545 +typedef union _RXMAC_PF_CTRL_t {
1546 + u32 value;
1547 + struct {
1548 +#ifdef _BIT_FIELDS_HTOL
1549 + u32 unused2:9; // bits 23-31
1550 + u32 min_pkt_size:7; // bits 16-22
1551 + u32 unused1:12; // bits 4-15
1552 + u32 filter_frag_en:1; // bit 3
1553 + u32 filter_uni_en:1; // bit 2
1554 + u32 filter_multi_en:1; // bit 1
1555 + u32 filter_broad_en:1; // bit 0
1556 +#else
1557 + u32 filter_broad_en:1; // bit 0
1558 + u32 filter_multi_en:1; // bit 1
1559 + u32 filter_uni_en:1; // bit 2
1560 + u32 filter_frag_en:1; // bit 3
1561 + u32 unused1:12; // bits 4-15
1562 + u32 min_pkt_size:7; // bits 16-22
1563 + u32 unused2:9; // bits 23-31
1564 +#endif
1565 + } bits;
1566 +} RXMAC_PF_CTRL_t, *PRXMAC_PF_CTRL_t;
1567 +
1568 +/*
1569 + * structure for Memory Controller Interface Control Max Segment reg in rxmac
1570 + * address map. Located at address 0x4088
1571 + */
1572 +typedef union _RXMAC_MCIF_CTRL_MAX_SEG_t {
1573 + u32 value;
1574 + struct {
1575 +#ifdef _BIT_FIELDS_HTOL
1576 + u32 reserved:22; // bits 10-31
1577 + u32 max_size:8; // bits 2-9
1578 + u32 fc_en:1; // bit 1
1579 + u32 seg_en:1; // bit 0
1580 +#else
1581 + u32 seg_en:1; // bit 0
1582 + u32 fc_en:1; // bit 1
1583 + u32 max_size:8; // bits 2-9
1584 + u32 reserved:22; // bits 10-31
1585 +#endif
1586 + } bits;
1587 +} RXMAC_MCIF_CTRL_MAX_SEG_t, *PRXMAC_MCIF_CTRL_MAX_SEG_t;
1588 +
1589 +/*
1590 + * structure for Memory Controller Interface Water Mark reg in rxmac address
1591 + * map. Located at address 0x408C
1592 + */
1593 +typedef union _RXMAC_MCIF_WATER_MARK_t {
1594 + u32 value;
1595 + struct {
1596 +#ifdef _BIT_FIELDS_HTOL
1597 + u32 reserved2:6; // bits 26-31
1598 + u32 mark_hi:10; // bits 16-25
1599 + u32 reserved1:6; // bits 10-15
1600 + u32 mark_lo:10; // bits 0-9
1601 +#else
1602 + u32 mark_lo:10; // bits 0-9
1603 + u32 reserved1:6; // bits 10-15
1604 + u32 mark_hi:10; // bits 16-25
1605 + u32 reserved2:6; // bits 26-31
1606 +#endif
1607 + } bits;
1608 +} RXMAC_MCIF_WATER_MARK_t, *PRXMAC_MCIF_WATER_MARK_t;
1609 +
1610 +/*
1611 + * structure for Rx Queue Dialog reg in rxmac address map.
1612 + * located at address 0x4090
1613 + */
1614 +typedef union _RXMAC_RXQ_DIAG_t {
1615 + u32 value;
1616 + struct {
1617 +#ifdef _BIT_FIELDS_HTOL
1618 + u32 reserved2:6; // bits 26-31
1619 + u32 rd_ptr:10; // bits 16-25
1620 + u32 reserved1:6; // bits 10-15
1621 + u32 wr_ptr:10; // bits 0-9
1622 +#else
1623 + u32 wr_ptr:10; // bits 0-9
1624 + u32 reserved1:6; // bits 10-15
1625 + u32 rd_ptr:10; // bits 16-25
1626 + u32 reserved2:6; // bits 26-31
1627 +#endif
1628 + } bits;
1629 +} RXMAC_RXQ_DIAG_t, *PRXMAC_RXQ_DIAG_t;
1630 +
1631 +/*
1632 + * structure for space availiable reg in rxmac address map.
1633 + * located at address 0x4094
1634 + */
1635 +typedef union _RXMAC_SPACE_AVAIL_t {
1636 + u32 value;
1637 + struct {
1638 +#ifdef _BIT_FIELDS_HTOL
1639 + u32 reserved2:15; // bits 17-31
1640 + u32 space_avail_en:1; // bit 16
1641 + u32 reserved1:6; // bits 10-15
1642 + u32 space_avail:10; // bits 0-9
1643 +#else
1644 + u32 space_avail:10; // bits 0-9
1645 + u32 reserved1:6; // bits 10-15
1646 + u32 space_avail_en:1; // bit 16
1647 + u32 reserved2:15; // bits 17-31
1648 +#endif
1649 + } bits;
1650 +} RXMAC_SPACE_AVAIL_t, *PRXMAC_SPACE_AVAIL_t;
1651 +
1652 +/*
1653 + * structure for management interface reg in rxmac address map.
1654 + * located at address 0x4098
1655 + */
1656 +typedef union _RXMAC_MIF_CTL_t {
1657 + u32 value;
1658 + struct {
1659 +#ifdef _BIT_FIELDS_HTOL
1660 + u32 reserve:14; // bits 18-31
1661 + u32 drop_pkt_en:1; // bit 17
1662 + u32 drop_pkt_mask:17; // bits 0-16
1663 +#else
1664 + u32 drop_pkt_mask:17; // bits 0-16
1665 + u32 drop_pkt_en:1; // bit 17
1666 + u32 reserve:14; // bits 18-31
1667 +#endif
1668 + } bits;
1669 +} RXMAC_MIF_CTL_t, *PRXMAC_MIF_CTL_t;
1670 +
1671 +/*
1672 + * structure for Error reg in rxmac address map.
1673 + * located at address 0x409C
1674 + */
1675 +typedef union _RXMAC_ERROR_REG_t {
1676 + u32 value;
1677 + struct {
1678 +#ifdef _BIT_FIELDS_HTOL
1679 + u32 reserve:28; // bits 4-31
1680 + u32 mif:1; // bit 3
1681 + u32 async:1; // bit 2
1682 + u32 pkt_filter:1; // bit 1
1683 + u32 mcif:1; // bit 0
1684 +#else
1685 + u32 mcif:1; // bit 0
1686 + u32 pkt_filter:1; // bit 1
1687 + u32 async:1; // bit 2
1688 + u32 mif:1; // bit 3
1689 + u32 reserve:28; // bits 4-31
1690 +#endif
1691 + } bits;
1692 +} RXMAC_ERROR_REG_t, *PRXMAC_ERROR_REG_t;
1693 +
1694 +/*
1695 + * Rx MAC Module of JAGCore Address Mapping
1696 + */
1697 +typedef struct _RXMAC_t { // Location:
1698 + RXMAC_CTRL_t ctrl; // 0x4000
1699 + RXMAC_WOL_CTL_CRC0_t crc0; // 0x4004
1700 + RXMAC_WOL_CRC12_t crc12; // 0x4008
1701 + RXMAC_WOL_CRC34_t crc34; // 0x400C
1702 + RXMAC_WOL_SA_LO_t sa_lo; // 0x4010
1703 + RXMAC_WOL_SA_HI_t sa_hi; // 0x4014
1704 + u32 mask0_word0; // 0x4018
1705 + u32 mask0_word1; // 0x401C
1706 + u32 mask0_word2; // 0x4020
1707 + u32 mask0_word3; // 0x4024
1708 + u32 mask1_word0; // 0x4028
1709 + u32 mask1_word1; // 0x402C
1710 + u32 mask1_word2; // 0x4030
1711 + u32 mask1_word3; // 0x4034
1712 + u32 mask2_word0; // 0x4038
1713 + u32 mask2_word1; // 0x403C
1714 + u32 mask2_word2; // 0x4040
1715 + u32 mask2_word3; // 0x4044
1716 + u32 mask3_word0; // 0x4048
1717 + u32 mask3_word1; // 0x404C
1718 + u32 mask3_word2; // 0x4050
1719 + u32 mask3_word3; // 0x4054
1720 + u32 mask4_word0; // 0x4058
1721 + u32 mask4_word1; // 0x405C
1722 + u32 mask4_word2; // 0x4060
1723 + u32 mask4_word3; // 0x4064
1724 + RXMAC_UNI_PF_ADDR1_t uni_pf_addr1; // 0x4068
1725 + RXMAC_UNI_PF_ADDR2_t uni_pf_addr2; // 0x406C
1726 + RXMAC_UNI_PF_ADDR3_t uni_pf_addr3; // 0x4070
1727 + u32 multi_hash1; // 0x4074
1728 + u32 multi_hash2; // 0x4078
1729 + u32 multi_hash3; // 0x407C
1730 + u32 multi_hash4; // 0x4080
1731 + RXMAC_PF_CTRL_t pf_ctrl; // 0x4084
1732 + RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg; // 0x4088
1733 + RXMAC_MCIF_WATER_MARK_t mcif_water_mark; // 0x408C
1734 + RXMAC_RXQ_DIAG_t rxq_diag; // 0x4090
1735 + RXMAC_SPACE_AVAIL_t space_avail; // 0x4094
1736 +
1737 + RXMAC_MIF_CTL_t mif_ctrl; // 0x4098
1738 + RXMAC_ERROR_REG_t err_reg; // 0x409C
1739 +} RXMAC_t, *PRXMAC_t;
1740 +
1741 +/* END OF TXMAC REGISTER ADDRESS MAP */
1742 +
1743 +
1744 +/* START OF MAC REGISTER ADDRESS MAP */
1745 +
1746 +/*
1747 + * structure for configuration #1 reg in mac address map.
1748 + * located at address 0x5000
1749 + */
1750 +typedef union _MAC_CFG1_t {
1751 + u32 value;
1752 + struct {
1753 +#ifdef _BIT_FIELDS_HTOL
1754 + u32 soft_reset:1; // bit 31
1755 + u32 sim_reset:1; // bit 30
1756 + u32 reserved3:10; // bits 20-29
1757 + u32 reset_rx_mc:1; // bit 19
1758 + u32 reset_tx_mc:1; // bit 18
1759 + u32 reset_rx_fun:1; // bit 17
1760 + u32 reset_tx_fun:1; // bit 16
1761 + u32 reserved2:7; // bits 9-15
1762 + u32 loop_back:1; // bit 8
1763 + u32 reserved1:2; // bits 6-7
1764 + u32 rx_flow:1; // bit 5
1765 + u32 tx_flow:1; // bit 4
1766 + u32 syncd_rx_en:1; // bit 3
1767 + u32 rx_enable:1; // bit 2
1768 + u32 syncd_tx_en:1; // bit 1
1769 + u32 tx_enable:1; // bit 0
1770 +#else
1771 + u32 tx_enable:1; // bit 0
1772 + u32 syncd_tx_en:1; // bit 1
1773 + u32 rx_enable:1; // bit 2
1774 + u32 syncd_rx_en:1; // bit 3
1775 + u32 tx_flow:1; // bit 4
1776 + u32 rx_flow:1; // bit 5
1777 + u32 reserved1:2; // bits 6-7
1778 + u32 loop_back:1; // bit 8
1779 + u32 reserved2:7; // bits 9-15
1780 + u32 reset_tx_fun:1; // bit 16
1781 + u32 reset_rx_fun:1; // bit 17
1782 + u32 reset_tx_mc:1; // bit 18
1783 + u32 reset_rx_mc:1; // bit 19
1784 + u32 reserved3:10; // bits 20-29
1785 + u32 sim_reset:1; // bit 30
1786 + u32 soft_reset:1; // bit 31
1787 +#endif
1788 + } bits;
1789 +} MAC_CFG1_t, *PMAC_CFG1_t;
1790 +
1791 +/*
1792 + * structure for configuration #2 reg in mac address map.
1793 + * located at address 0x5004
1794 + */
1795 +typedef union _MAC_CFG2_t {
1796 + u32 value;
1797 + struct {
1798 +#ifdef _BIT_FIELDS_HTOL
1799 + u32 reserved3:16; // bits 16-31
1800 + u32 preamble_len:4; // bits 12-15
1801 + u32 reserved2:2; // bits 10-11
1802 + u32 if_mode:2; // bits 8-9
1803 + u32 reserved1:2; // bits 6-7
1804 + u32 huge_frame:1; // bit 5
1805 + u32 len_check:1; // bit 4
1806 + u32 undefined:1; // bit 3
1807 + u32 pad_crc:1; // bit 2
1808 + u32 crc_enable:1; // bit 1
1809 + u32 full_duplex:1; // bit 0
1810 +#else
1811 + u32 full_duplex:1; // bit 0
1812 + u32 crc_enable:1; // bit 1
1813 + u32 pad_crc:1; // bit 2
1814 + u32 undefined:1; // bit 3
1815 + u32 len_check:1; // bit 4
1816 + u32 huge_frame:1; // bit 5
1817 + u32 reserved1:2; // bits 6-7
1818 + u32 if_mode:2; // bits 8-9
1819 + u32 reserved2:2; // bits 10-11
1820 + u32 preamble_len:4; // bits 12-15
1821 + u32 reserved3:16; // bits 16-31
1822 +#endif
1823 + } bits;
1824 +} MAC_CFG2_t, *PMAC_CFG2_t;
1825 +
1826 +/*
1827 + * structure for Interpacket gap reg in mac address map.
1828 + * located at address 0x5008
1829 + */
1830 +typedef union _MAC_IPG_t {
1831 + u32 value;
1832 + struct {
1833 +#ifdef _BIT_FIELDS_HTOL
1834 + u32 reserved:1; // bit 31
1835 + u32 non_B2B_ipg_1:7; // bits 24-30
1836 + u32 undefined2:1; // bit 23
1837 + u32 non_B2B_ipg_2:7; // bits 16-22
1838 + u32 min_ifg_enforce:8; // bits 8-15
1839 + u32 undefined1:1; // bit 7
1840 + u32 B2B_ipg:7; // bits 0-6
1841 +#else
1842 + u32 B2B_ipg:7; // bits 0-6
1843 + u32 undefined1:1; // bit 7
1844 + u32 min_ifg_enforce:8; // bits 8-15
1845 + u32 non_B2B_ipg_2:7; // bits 16-22
1846 + u32 undefined2:1; // bit 23
1847 + u32 non_B2B_ipg_1:7; // bits 24-30
1848 + u32 reserved:1; // bit 31
1849 +#endif
1850 + } bits;
1851 +} MAC_IPG_t, *PMAC_IPG_t;
1852 +
1853 +/*
1854 + * structure for half duplex reg in mac address map.
1855 + * located at address 0x500C
1856 + */
1857 +typedef union _MAC_HFDP_t {
1858 + u32 value;
1859 + struct {
1860 +#ifdef _BIT_FIELDS_HTOL
1861 + u32 reserved2:8; // bits 24-31
1862 + u32 alt_beb_trunc:4; // bits 23-20
1863 + u32 alt_beb_enable:1; // bit 19
1864 + u32 bp_no_backoff:1; // bit 18
1865 + u32 no_backoff:1; // bit 17
1866 + u32 excess_defer:1; // bit 16
1867 + u32 rexmit_max:4; // bits 12-15
1868 + u32 reserved1:2; // bits 10-11
1869 + u32 coll_window:10; // bits 0-9
1870 +#else
1871 + u32 coll_window:10; // bits 0-9
1872 + u32 reserved1:2; // bits 10-11
1873 + u32 rexmit_max:4; // bits 12-15
1874 + u32 excess_defer:1; // bit 16
1875 + u32 no_backoff:1; // bit 17
1876 + u32 bp_no_backoff:1; // bit 18
1877 + u32 alt_beb_enable:1; // bit 19
1878 + u32 alt_beb_trunc:4; // bits 23-20
1879 + u32 reserved2:8; // bits 24-31
1880 +#endif
1881 + } bits;
1882 +} MAC_HFDP_t, *PMAC_HFDP_t;
1883 +
1884 +/*
1885 + * structure for Maximum Frame Length reg in mac address map.
1886 + * located at address 0x5010
1887 + */
1888 +typedef union _MAC_MAX_FM_LEN_t {
1889 + u32 value;
1890 + struct {
1891 +#ifdef _BIT_FIELDS_HTOL
1892 + u32 reserved:16; // bits 16-31
1893 + u32 max_len:16; // bits 0-15
1894 +#else
1895 + u32 max_len:16; // bits 0-15
1896 + u32 reserved:16; // bits 16-31
1897 +#endif
1898 + } bits;
1899 +} MAC_MAX_FM_LEN_t, *PMAC_MAX_FM_LEN_t;
1900 +
1901 +/*
1902 + * structure for Reserve 1 reg in mac address map.
1903 + * located at address 0x5014 - 0x5018
1904 + * Defined earlier (u32)
1905 + */
1906 +
1907 +/*
1908 + * structure for Test reg in mac address map.
1909 + * located at address 0x501C
1910 + */
1911 +typedef union _MAC_TEST_t {
1912 + u32 value;
1913 + struct {
1914 +#ifdef _BIT_FIELDS_HTOL
1915 + u32 unused:29; // bits 3-31
1916 + u32 mac_test:3; // bits 0-2
1917 +#else
1918 + u32 mac_test:3; // bits 0-2
1919 + u32 unused:29; // bits 3-31
1920 +#endif
1921 + } bits;
1922 +} MAC_TEST_t, *PMAC_TEST_t;
1923 +
1924 +/*
1925 + * structure for MII Management Configuration reg in mac address map.
1926 + * located at address 0x5020
1927 + */
1928 +typedef union _MII_MGMT_CFG_t {
1929 + u32 value;
1930 + struct {
1931 +#ifdef _BIT_FIELDS_HTOL
1932 + u32 reset_mii_mgmt:1; // bit 31
1933 + u32 reserved:25; // bits 6-30
1934 + u32 scan_auto_incremt:1; // bit 5
1935 + u32 preamble_suppress:1; // bit 4
1936 + u32 undefined:1; // bit 3
1937 + u32 mgmt_clk_reset:3; // bits 0-2
1938 +#else
1939 + u32 mgmt_clk_reset:3; // bits 0-2
1940 + u32 undefined:1; // bit 3
1941 + u32 preamble_suppress:1; // bit 4
1942 + u32 scan_auto_incremt:1; // bit 5
1943 + u32 reserved:25; // bits 6-30
1944 + u32 reset_mii_mgmt:1; // bit 31
1945 +#endif
1946 + } bits;
1947 +} MII_MGMT_CFG_t, *PMII_MGMT_CFG_t;
1948 +
1949 +/*
1950 + * structure for MII Management Command reg in mac address map.
1951 + * located at address 0x5024
1952 + */
1953 +typedef union _MII_MGMT_CMD_t {
1954 + u32 value;
1955 + struct {
1956 +#ifdef _BIT_FIELDS_HTOL
1957 + u32 reserved:30; // bits 2-31
1958 + u32 scan_cycle:1; // bit 1
1959 + u32 read_cycle:1; // bit 0
1960 +#else
1961 + u32 read_cycle:1; // bit 0
1962 + u32 scan_cycle:1; // bit 1
1963 + u32 reserved:30; // bits 2-31
1964 +#endif
1965 + } bits;
1966 +} MII_MGMT_CMD_t, *PMII_MGMT_CMD_t;
1967 +
1968 +/*
1969 + * structure for MII Management Address reg in mac address map.
1970 + * located at address 0x5028
1971 + */
1972 +typedef union _MII_MGMT_ADDR_t {
1973 + u32 value;
1974 + struct {
1975 +#ifdef _BIT_FIELDS_HTOL
1976 + u32 reserved2:19; // bit 13-31
1977 + u32 phy_addr:5; // bits 8-12
1978 + u32 reserved1:3; // bits 5-7
1979 + u32 reg_addr:5; // bits 0-4
1980 +#else
1981 + u32 reg_addr:5; // bits 0-4
1982 + u32 reserved1:3; // bits 5-7
1983 + u32 phy_addr:5; // bits 8-12
1984 + u32 reserved2:19; // bit 13-31
1985 +#endif
1986 + } bits;
1987 +} MII_MGMT_ADDR_t, *PMII_MGMT_ADDR_t;
1988 +
1989 +/*
1990 + * structure for MII Management Control reg in mac address map.
1991 + * located at address 0x502C
1992 + */
1993 +typedef union _MII_MGMT_CTRL_t {
1994 + u32 value;
1995 + struct {
1996 +#ifdef _BIT_FIELDS_HTOL
1997 + u32 reserved:16; // bits 16-31
1998 + u32 phy_ctrl:16; // bits 0-15
1999 +#else
2000 + u32 phy_ctrl:16; // bits 0-15
2001 + u32 reserved:16; // bits 16-31
2002 +#endif
2003 + } bits;
2004 +} MII_MGMT_CTRL_t, *PMII_MGMT_CTRL_t;
2005 +
2006 +/*
2007 + * structure for MII Management Status reg in mac address map.
2008 + * located at address 0x5030
2009 + */
2010 +typedef union _MII_MGMT_STAT_t {
2011 + u32 value;
2012 + struct {
2013 +#ifdef _BIT_FIELDS_HTOL
2014 + u32 reserved:16; // bits 16-31
2015 + u32 phy_stat:16; // bits 0-15
2016 +#else
2017 + u32 phy_stat:16; // bits 0-15
2018 + u32 reserved:16; // bits 16-31
2019 +#endif
2020 + } bits;
2021 +} MII_MGMT_STAT_t, *PMII_MGMT_STAT_t;
2022 +
2023 +/*
2024 + * structure for MII Management Indicators reg in mac address map.
2025 + * located at address 0x5034
2026 + */
2027 +typedef union _MII_MGMT_INDICATOR_t {
2028 + u32 value;
2029 + struct {
2030 +#ifdef _BIT_FIELDS_HTOL
2031 + u32 reserved:29; // bits 3-31
2032 + u32 not_valid:1; // bit 2
2033 + u32 scanning:1; // bit 1
2034 + u32 busy:1; // bit 0
2035 +#else
2036 + u32 busy:1; // bit 0
2037 + u32 scanning:1; // bit 1
2038 + u32 not_valid:1; // bit 2
2039 + u32 reserved:29; // bits 3-31
2040 +#endif
2041 + } bits;
2042 +} MII_MGMT_INDICATOR_t, *PMII_MGMT_INDICATOR_t;
2043 +
2044 +/*
2045 + * structure for Interface Control reg in mac address map.
2046 + * located at address 0x5038
2047 + */
2048 +typedef union _MAC_IF_CTRL_t {
2049 + u32 value;
2050 + struct {
2051 +#ifdef _BIT_FIELDS_HTOL
2052 + u32 reset_if_module:1; // bit 31
2053 + u32 reserved4:3; // bit 28-30
2054 + u32 tbi_mode:1; // bit 27
2055 + u32 ghd_mode:1; // bit 26
2056 + u32 lhd_mode:1; // bit 25
2057 + u32 phy_mode:1; // bit 24
2058 + u32 reset_per_mii:1; // bit 23
2059 + u32 reserved3:6; // bits 17-22
2060 + u32 speed:1; // bit 16
2061 + u32 reset_pe100x:1; // bit 15
2062 + u32 reserved2:4; // bits 11-14
2063 + u32 force_quiet:1; // bit 10
2064 + u32 no_cipher:1; // bit 9
2065 + u32 disable_link_fail:1; // bit 8
2066 + u32 reset_gpsi:1; // bit 7
2067 + u32 reserved1:6; // bits 1-6
2068 + u32 enab_jab_protect:1; // bit 0
2069 +#else
2070 + u32 enab_jab_protect:1; // bit 0
2071 + u32 reserved1:6; // bits 1-6
2072 + u32 reset_gpsi:1; // bit 7
2073 + u32 disable_link_fail:1; // bit 8
2074 + u32 no_cipher:1; // bit 9
2075 + u32 force_quiet:1; // bit 10
2076 + u32 reserved2:4; // bits 11-14
2077 + u32 reset_pe100x:1; // bit 15
2078 + u32 speed:1; // bit 16
2079 + u32 reserved3:6; // bits 17-22
2080 + u32 reset_per_mii:1; // bit 23
2081 + u32 phy_mode:1; // bit 24
2082 + u32 lhd_mode:1; // bit 25
2083 + u32 ghd_mode:1; // bit 26
2084 + u32 tbi_mode:1; // bit 27
2085 + u32 reserved4:3; // bit 28-30
2086 + u32 reset_if_module:1; // bit 31
2087 +#endif
2088 + } bits;
2089 +} MAC_IF_CTRL_t, *PMAC_IF_CTRL_t;
2090 +
2091 +/*
2092 + * structure for Interface Status reg in mac address map.
2093 + * located at address 0x503C
2094 + */
2095 +typedef union _MAC_IF_STAT_t {
2096 + u32 value;
2097 + struct {
2098 +#ifdef _BIT_FIELDS_HTOL
2099 + u32 reserved:22; // bits 10-31
2100 + u32 excess_defer:1; // bit 9
2101 + u32 clash:1; // bit 8
2102 + u32 phy_jabber:1; // bit 7
2103 + u32 phy_link_ok:1; // bit 6
2104 + u32 phy_full_duplex:1; // bit 5
2105 + u32 phy_speed:1; // bit 4
2106 + u32 pe100x_link_fail:1; // bit 3
2107 + u32 pe10t_loss_carrie:1; // bit 2
2108 + u32 pe10t_sqe_error:1; // bit 1
2109 + u32 pe10t_jabber:1; // bit 0
2110 +#else
2111 + u32 pe10t_jabber:1; // bit 0
2112 + u32 pe10t_sqe_error:1; // bit 1
2113 + u32 pe10t_loss_carrie:1; // bit 2
2114 + u32 pe100x_link_fail:1; // bit 3
2115 + u32 phy_speed:1; // bit 4
2116 + u32 phy_full_duplex:1; // bit 5
2117 + u32 phy_link_ok:1; // bit 6
2118 + u32 phy_jabber:1; // bit 7
2119 + u32 clash:1; // bit 8
2120 + u32 excess_defer:1; // bit 9
2121 + u32 reserved:22; // bits 10-31
2122 +#endif
2123 + } bits;
2124 +} MAC_IF_STAT_t, *PMAC_IF_STAT_t;
2125 +
2126 +/*
2127 + * structure for Mac Station Address, Part 1 reg in mac address map.
2128 + * located at address 0x5040
2129 + */
2130 +typedef union _MAC_STATION_ADDR1_t {
2131 + u32 value;
2132 + struct {
2133 +#ifdef _BIT_FIELDS_HTOL
2134 + u32 Octet6:8; // bits 24-31
2135 + u32 Octet5:8; // bits 16-23
2136 + u32 Octet4:8; // bits 8-15
2137 + u32 Octet3:8; // bits 0-7
2138 +#else
2139 + u32 Octet3:8; // bits 0-7
2140 + u32 Octet4:8; // bits 8-15
2141 + u32 Octet5:8; // bits 16-23
2142 + u32 Octet6:8; // bits 24-31
2143 +#endif
2144 + } bits;
2145 +} MAC_STATION_ADDR1_t, *PMAC_STATION_ADDR1_t;
2146 +
2147 +/*
2148 + * structure for Mac Station Address, Part 2 reg in mac address map.
2149 + * located at address 0x5044
2150 + */
2151 +typedef union _MAC_STATION_ADDR2_t {
2152 + u32 value;
2153 + struct {
2154 +#ifdef _BIT_FIELDS_HTOL
2155 + u32 Octet2:8; // bits 24-31
2156 + u32 Octet1:8; // bits 16-23
2157 + u32 reserved:16; // bits 0-15
2158 +#else
2159 + u32 reserved:16; // bit 0-15
2160 + u32 Octet1:8; // bits 16-23
2161 + u32 Octet2:8; // bits 24-31
2162 +#endif
2163 + } bits;
2164 +} MAC_STATION_ADDR2_t, *PMAC_STATION_ADDR2_t;
2165 +
2166 +/*
2167 + * MAC Module of JAGCore Address Mapping
2168 + */
2169 +typedef struct _MAC_t { // Location:
2170 + MAC_CFG1_t cfg1; // 0x5000
2171 + MAC_CFG2_t cfg2; // 0x5004
2172 + MAC_IPG_t ipg; // 0x5008
2173 + MAC_HFDP_t hfdp; // 0x500C
2174 + MAC_MAX_FM_LEN_t max_fm_len; // 0x5010
2175 + u32 rsv1; // 0x5014
2176 + u32 rsv2; // 0x5018
2177 + MAC_TEST_t mac_test; // 0x501C
2178 + MII_MGMT_CFG_t mii_mgmt_cfg; // 0x5020
2179 + MII_MGMT_CMD_t mii_mgmt_cmd; // 0x5024
2180 + MII_MGMT_ADDR_t mii_mgmt_addr; // 0x5028
2181 + MII_MGMT_CTRL_t mii_mgmt_ctrl; // 0x502C
2182 + MII_MGMT_STAT_t mii_mgmt_stat; // 0x5030
2183 + MII_MGMT_INDICATOR_t mii_mgmt_indicator; // 0x5034
2184 + MAC_IF_CTRL_t if_ctrl; // 0x5038
2185 + MAC_IF_STAT_t if_stat; // 0x503C
2186 + MAC_STATION_ADDR1_t station_addr_1; // 0x5040
2187 + MAC_STATION_ADDR2_t station_addr_2; // 0x5044
2188 +} MAC_t, *PMAC_t;
2189 +
2190 +/* END OF MAC REGISTER ADDRESS MAP */
2191 +
2192 +/* START OF MAC STAT REGISTER ADDRESS MAP */
2193 +
2194 +/*
2195 + * structure for Carry Register One and it's Mask Register reg located in mac
2196 + * stat address map address 0x6130 and 0x6138.
2197 + */
2198 +typedef union _MAC_STAT_REG_1_t {
2199 + u32 value;
2200 + struct {
2201 +#ifdef _BIT_FIELDS_HTOL
2202 + u32 tr64:1; // bit 31
2203 + u32 tr127:1; // bit 30
2204 + u32 tr255:1; // bit 29
2205 + u32 tr511:1; // bit 28
2206 + u32 tr1k:1; // bit 27
2207 + u32 trmax:1; // bit 26
2208 + u32 trmgv:1; // bit 25
2209 + u32 unused:8; // bits 17-24
2210 + u32 rbyt:1; // bit 16
2211 + u32 rpkt:1; // bit 15
2212 + u32 rfcs:1; // bit 14
2213 + u32 rmca:1; // bit 13
2214 + u32 rbca:1; // bit 12
2215 + u32 rxcf:1; // bit 11
2216 + u32 rxpf:1; // bit 10
2217 + u32 rxuo:1; // bit 9
2218 + u32 raln:1; // bit 8
2219 + u32 rflr:1; // bit 7
2220 + u32 rcde:1; // bit 6
2221 + u32 rcse:1; // bit 5
2222 + u32 rund:1; // bit 4
2223 + u32 rovr:1; // bit 3
2224 + u32 rfrg:1; // bit 2
2225 + u32 rjbr:1; // bit 1
2226 + u32 rdrp:1; // bit 0
2227 +#else
2228 + u32 rdrp:1; // bit 0
2229 + u32 rjbr:1; // bit 1
2230 + u32 rfrg:1; // bit 2
2231 + u32 rovr:1; // bit 3
2232 + u32 rund:1; // bit 4
2233 + u32 rcse:1; // bit 5
2234 + u32 rcde:1; // bit 6
2235 + u32 rflr:1; // bit 7
2236 + u32 raln:1; // bit 8
2237 + u32 rxuo:1; // bit 9
2238 + u32 rxpf:1; // bit 10
2239 + u32 rxcf:1; // bit 11
2240 + u32 rbca:1; // bit 12
2241 + u32 rmca:1; // bit 13
2242 + u32 rfcs:1; // bit 14
2243 + u32 rpkt:1; // bit 15
2244 + u32 rbyt:1; // bit 16
2245 + u32 unused:8; // bits 17-24
2246 + u32 trmgv:1; // bit 25
2247 + u32 trmax:1; // bit 26
2248 + u32 tr1k:1; // bit 27
2249 + u32 tr511:1; // bit 28
2250 + u32 tr255:1; // bit 29
2251 + u32 tr127:1; // bit 30
2252 + u32 tr64:1; // bit 31
2253 +#endif
2254 + } bits;
2255 +} MAC_STAT_REG_1_t, *PMAC_STAT_REG_1_t;
2256 +
2257 +/*
2258 + * structure for Carry Register Two Mask Register reg in mac stat address map.
2259 + * located at address 0x613C
2260 + */
2261 +typedef union _MAC_STAT_REG_2_t {
2262 + u32 value;
2263 + struct {
2264 +#ifdef _BIT_FIELDS_HTOL
2265 + u32 unused:12; // bit 20-31
2266 + u32 tjbr:1; // bit 19
2267 + u32 tfcs:1; // bit 18
2268 + u32 txcf:1; // bit 17
2269 + u32 tovr:1; // bit 16
2270 + u32 tund:1; // bit 15
2271 + u32 tfrg:1; // bit 14
2272 + u32 tbyt:1; // bit 13
2273 + u32 tpkt:1; // bit 12
2274 + u32 tmca:1; // bit 11
2275 + u32 tbca:1; // bit 10
2276 + u32 txpf:1; // bit 9
2277 + u32 tdfr:1; // bit 8
2278 + u32 tedf:1; // bit 7
2279 + u32 tscl:1; // bit 6
2280 + u32 tmcl:1; // bit 5
2281 + u32 tlcl:1; // bit 4
2282 + u32 txcl:1; // bit 3
2283 + u32 tncl:1; // bit 2
2284 + u32 tpfh:1; // bit 1
2285 + u32 tdrp:1; // bit 0
2286 +#else
2287 + u32 tdrp:1; // bit 0
2288 + u32 tpfh:1; // bit 1
2289 + u32 tncl:1; // bit 2
2290 + u32 txcl:1; // bit 3
2291 + u32 tlcl:1; // bit 4
2292 + u32 tmcl:1; // bit 5
2293 + u32 tscl:1; // bit 6
2294 + u32 tedf:1; // bit 7
2295 + u32 tdfr:1; // bit 8
2296 + u32 txpf:1; // bit 9
2297 + u32 tbca:1; // bit 10
2298 + u32 tmca:1; // bit 11
2299 + u32 tpkt:1; // bit 12
2300 + u32 tbyt:1; // bit 13
2301 + u32 tfrg:1; // bit 14
2302 + u32 tund:1; // bit 15
2303 + u32 tovr:1; // bit 16
2304 + u32 txcf:1; // bit 17
2305 + u32 tfcs:1; // bit 18
2306 + u32 tjbr:1; // bit 19
2307 + u32 unused:12; // bit 20-31
2308 +#endif
2309 + } bits;
2310 +} MAC_STAT_REG_2_t, *PMAC_STAT_REG_2_t;
2311 +
2312 +/*
2313 + * MAC STATS Module of JAGCore Address Mapping
2314 + */
2315 +typedef struct _MAC_STAT_t { // Location:
2316 + u32 pad[32]; // 0x6000 - 607C
2317 +
2318 + // Tx/Rx 0-64 Byte Frame Counter
2319 + u32 TR64; // 0x6080
2320 +
2321 + // Tx/Rx 65-127 Byte Frame Counter
2322 + u32 TR127; // 0x6084
2323 +
2324 + // Tx/Rx 128-255 Byte Frame Counter
2325 + u32 TR255; // 0x6088
2326 +
2327 + // Tx/Rx 256-511 Byte Frame Counter
2328 + u32 TR511; // 0x608C
2329 +
2330 + // Tx/Rx 512-1023 Byte Frame Counter
2331 + u32 TR1K; // 0x6090
2332 +
2333 + // Tx/Rx 1024-1518 Byte Frame Counter
2334 + u32 TRMax; // 0x6094
2335 +
2336 + // Tx/Rx 1519-1522 Byte Good VLAN Frame Count
2337 + u32 TRMgv; // 0x6098
2338 +
2339 + // Rx Byte Counter
2340 + u32 RByt; // 0x609C
2341 +
2342 + // Rx Packet Counter
2343 + u32 RPkt; // 0x60A0
2344 +
2345 + // Rx FCS Error Counter
2346 + u32 RFcs; // 0x60A4
2347 +
2348 + // Rx Multicast Packet Counter
2349 + u32 RMca; // 0x60A8
2350 +
2351 + // Rx Broadcast Packet Counter
2352 + u32 RBca; // 0x60AC
2353 +
2354 + // Rx Control Frame Packet Counter
2355 + u32 RxCf; // 0x60B0
2356 +
2357 + // Rx Pause Frame Packet Counter
2358 + u32 RxPf; // 0x60B4
2359 +
2360 + // Rx Unknown OP Code Counter
2361 + u32 RxUo; // 0x60B8
2362 +
2363 + // Rx Alignment Error Counter
2364 + u32 RAln; // 0x60BC
2365 +
2366 + // Rx Frame Length Error Counter
2367 + u32 RFlr; // 0x60C0
2368 +
2369 + // Rx Code Error Counter
2370 + u32 RCde; // 0x60C4
2371 +
2372 + // Rx Carrier Sense Error Counter
2373 + u32 RCse; // 0x60C8
2374 +
2375 + // Rx Undersize Packet Counter
2376 + u32 RUnd; // 0x60CC
2377 +
2378 + // Rx Oversize Packet Counter
2379 + u32 ROvr; // 0x60D0
2380 +
2381 + // Rx Fragment Counter
2382 + u32 RFrg; // 0x60D4
2383 +
2384 + // Rx Jabber Counter
2385 + u32 RJbr; // 0x60D8
2386 +
2387 + // Rx Drop
2388 + u32 RDrp; // 0x60DC
2389 +
2390 + // Tx Byte Counter
2391 + u32 TByt; // 0x60E0
2392 +
2393 + // Tx Packet Counter
2394 + u32 TPkt; // 0x60E4
2395 +
2396 + // Tx Multicast Packet Counter
2397 + u32 TMca; // 0x60E8
2398 +
2399 + // Tx Broadcast Packet Counter
2400 + u32 TBca; // 0x60EC
2401 +
2402 + // Tx Pause Control Frame Counter
2403 + u32 TxPf; // 0x60F0
2404 +
2405 + // Tx Deferral Packet Counter
2406 + u32 TDfr; // 0x60F4
2407 +
2408 + // Tx Excessive Deferral Packet Counter
2409 + u32 TEdf; // 0x60F8
2410 +
2411 + // Tx Single Collision Packet Counter
2412 + u32 TScl; // 0x60FC
2413 +
2414 + // Tx Multiple Collision Packet Counter
2415 + u32 TMcl; // 0x6100
2416 +
2417 + // Tx Late Collision Packet Counter
2418 + u32 TLcl; // 0x6104
2419 +
2420 + // Tx Excessive Collision Packet Counter
2421 + u32 TXcl; // 0x6108
2422 +
2423 + // Tx Total Collision Packet Counter
2424 + u32 TNcl; // 0x610C
2425 +
2426 + // Tx Pause Frame Honored Counter
2427 + u32 TPfh; // 0x6110
2428 +
2429 + // Tx Drop Frame Counter
2430 + u32 TDrp; // 0x6114
2431 +
2432 + // Tx Jabber Frame Counter
2433 + u32 TJbr; // 0x6118
2434 +
2435 + // Tx FCS Error Counter
2436 + u32 TFcs; // 0x611C
2437 +
2438 + // Tx Control Frame Counter
2439 + u32 TxCf; // 0x6120
2440 +
2441 + // Tx Oversize Frame Counter
2442 + u32 TOvr; // 0x6124
2443 +
2444 + // Tx Undersize Frame Counter
2445 + u32 TUnd; // 0x6128
2446 +
2447 + // Tx Fragments Frame Counter
2448 + u32 TFrg; // 0x612C
2449 +
2450 + // Carry Register One Register
2451 + MAC_STAT_REG_1_t Carry1; // 0x6130
2452 +
2453 + // Carry Register Two Register
2454 + MAC_STAT_REG_2_t Carry2; // 0x6134
2455 +
2456 + // Carry Register One Mask Register
2457 + MAC_STAT_REG_1_t Carry1M; // 0x6138
2458 +
2459 + // Carry Register Two Mask Register
2460 + MAC_STAT_REG_2_t Carry2M; // 0x613C
2461 +} MAC_STAT_t, *PMAC_STAT_t;
2462 +
2463 +/* END OF MAC STAT REGISTER ADDRESS MAP */
2464 +
2465 +
2466 +/* START OF MMC REGISTER ADDRESS MAP */
2467 +
2468 +/*
2469 + * structure for Main Memory Controller Control reg in mmc address map.
2470 + * located at address 0x7000
2471 + */
2472 +typedef union _MMC_CTRL_t {
2473 + u32 value;
2474 + struct {
2475 +#ifdef _BIT_FIELDS_HTOL
2476 + u32 reserved:25; // bits 7-31
2477 + u32 force_ce:1; // bit 6
2478 + u32 rxdma_disable:1; // bit 5
2479 + u32 txdma_disable:1; // bit 4
2480 + u32 txmac_disable:1; // bit 3
2481 + u32 rxmac_disable:1; // bit 2
2482 + u32 arb_disable:1; // bit 1
2483 + u32 mmc_enable:1; // bit 0
2484 +#else
2485 + u32 mmc_enable:1; // bit 0
2486 + u32 arb_disable:1; // bit 1
2487 + u32 rxmac_disable:1; // bit 2
2488 + u32 txmac_disable:1; // bit 3
2489 + u32 txdma_disable:1; // bit 4
2490 + u32 rxdma_disable:1; // bit 5
2491 + u32 force_ce:1; // bit 6
2492 + u32 reserved:25; // bits 7-31
2493 +#endif
2494 + } bits;
2495 +} MMC_CTRL_t, *PMMC_CTRL_t;
2496 +
2497 +/*
2498 + * structure for Main Memory Controller Host Memory Access Address reg in mmc
2499 + * address map. Located at address 0x7004
2500 + */
2501 +typedef union _MMC_SRAM_ACCESS_t {
2502 + u32 value;
2503 + struct {
2504 +#ifdef _BIT_FIELDS_HTOL
2505 + u32 byte_enable:16; // bits 16-31
2506 + u32 reserved2:2; // bits 14-15
2507 + u32 req_addr:10; // bits 4-13
2508 + u32 reserved1:1; // bit 3
2509 + u32 is_ctrl_word:1; // bit 2
2510 + u32 wr_access:1; // bit 1
2511 + u32 req_access:1; // bit 0
2512 +#else
2513 + u32 req_access:1; // bit 0
2514 + u32 wr_access:1; // bit 1
2515 + u32 is_ctrl_word:1; // bit 2
2516 + u32 reserved1:1; // bit 3
2517 + u32 req_addr:10; // bits 4-13
2518 + u32 reserved2:2; // bits 14-15
2519 + u32 byte_enable:16; // bits 16-31
2520 +#endif
2521 + } bits;
2522 +} MMC_SRAM_ACCESS_t, *PMMC_SRAM_ACCESS_t;
2523 +
2524 +/*
2525 + * structure for Main Memory Controller Host Memory Access Data reg in mmc
2526 + * address map. Located at address 0x7008 - 0x7014
2527 + * Defined earlier (u32)
2528 + */
2529 +
2530 +/*
2531 + * Memory Control Module of JAGCore Address Mapping
2532 + */
2533 +typedef struct _MMC_t { // Location:
2534 + MMC_CTRL_t mmc_ctrl; // 0x7000
2535 + MMC_SRAM_ACCESS_t sram_access; // 0x7004
2536 + u32 sram_word1; // 0x7008
2537 + u32 sram_word2; // 0x700C
2538 + u32 sram_word3; // 0x7010
2539 + u32 sram_word4; // 0x7014
2540 +} MMC_t, *PMMC_t;
2541 +
2542 +/* END OF MMC REGISTER ADDRESS MAP */
2543 +
2544 +
2545 +/* START OF EXP ROM REGISTER ADDRESS MAP */
2546 +
2547 +/*
2548 + * Expansion ROM Module of JAGCore Address Mapping
2549 + */
2550 +
2551 +/* Take this out until it is not empty */
2552 +#if 0
2553 +typedef struct _EXP_ROM_t {
2554 +
2555 +} EXP_ROM_t, *PEXP_ROM_t;
2556 +#endif
2557 +
2558 +/* END OF EXP ROM REGISTER ADDRESS MAP */
2559 +
2560 +
2561 +/*
2562 + * JAGCore Address Mapping
2563 + */
2564 +typedef struct _ADDRESS_MAP_t {
2565 + GLOBAL_t global;
2566 + // unused section of global address map
2567 + u8 unused_global[4096 - sizeof(GLOBAL_t)];
2568 + TXDMA_t txdma;
2569 + // unused section of txdma address map
2570 + u8 unused_txdma[4096 - sizeof(TXDMA_t)];
2571 + RXDMA_t rxdma;
2572 + // unused section of rxdma address map
2573 + u8 unused_rxdma[4096 - sizeof(RXDMA_t)];
2574 + TXMAC_t txmac;
2575 + // unused section of txmac address map
2576 + u8 unused_txmac[4096 - sizeof(TXMAC_t)];
2577 + RXMAC_t rxmac;
2578 + // unused section of rxmac address map
2579 + u8 unused_rxmac[4096 - sizeof(RXMAC_t)];
2580 + MAC_t mac;
2581 + // unused section of mac address map
2582 + u8 unused_mac[4096 - sizeof(MAC_t)];
2583 + MAC_STAT_t macStat;
2584 + // unused section of mac stat address map
2585 + u8 unused_mac_stat[4096 - sizeof(MAC_STAT_t)];
2586 + MMC_t mmc;
2587 + // unused section of mmc address map
2588 + u8 unused_mmc[4096 - sizeof(MMC_t)];
2589 + // unused section of address map
2590 + u8 unused_[1015808];
2591 +
2592 +/* Take this out until it is not empty */
2593 +#if 0
2594 + EXP_ROM_t exp_rom;
2595 +#endif
2596 +
2597 + u8 unused_exp_rom[4096]; // MGS-size TBD
2598 + u8 unused__[524288]; // unused section of address map
2599 +} ADDRESS_MAP_t, *PADDRESS_MAP_t;
2600 +
2601 +#endif /* _ET1310_ADDRESS_MAP_H_ */
2602 diff --git a/drivers/staging/et131x/et1310_eeprom.c b/drivers/staging/et131x/et1310_eeprom.c
2603 new file mode 100644
2604 index 0000000..c2b194e
2605 --- /dev/null
2606 +++ b/drivers/staging/et131x/et1310_eeprom.c
2607 @@ -0,0 +1,480 @@
2608 +/*
2609 + * Agere Systems Inc.
2610 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
2611 + *
2612 + * Copyright © 2005 Agere Systems Inc.
2613 + * All rights reserved.
2614 + * http://www.agere.com
2615 + *
2616 + *------------------------------------------------------------------------------
2617 + *
2618 + * et1310_eeprom.c - Code used to access the device's EEPROM
2619 + *
2620 + *------------------------------------------------------------------------------
2621 + *
2622 + * SOFTWARE LICENSE
2623 + *
2624 + * This software is provided subject to the following terms and conditions,
2625 + * which you should read carefully before using the software. Using this
2626 + * software indicates your acceptance of these terms and conditions. If you do
2627 + * not agree with these terms and conditions, do not use the software.
2628 + *
2629 + * Copyright © 2005 Agere Systems Inc.
2630 + * All rights reserved.
2631 + *
2632 + * Redistribution and use in source or binary forms, with or without
2633 + * modifications, are permitted provided that the following conditions are met:
2634 + *
2635 + * . Redistributions of source code must retain the above copyright notice, this
2636 + * list of conditions and the following Disclaimer as comments in the code as
2637 + * well as in the documentation and/or other materials provided with the
2638 + * distribution.
2639 + *
2640 + * . Redistributions in binary form must reproduce the above copyright notice,
2641 + * this list of conditions and the following Disclaimer in the documentation
2642 + * and/or other materials provided with the distribution.
2643 + *
2644 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
2645 + * may be used to endorse or promote products derived from this software
2646 + * without specific prior written permission.
2647 + *
2648 + * Disclaimer
2649 + *
2650 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
2651 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
2652 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
2653 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
2654 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
2655 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
2656 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
2657 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
2658 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
2659 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
2660 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
2661 + * DAMAGE.
2662 + *
2663 + */
2664 +
2665 +#include "et131x_version.h"
2666 +#include "et131x_debug.h"
2667 +#include "et131x_defs.h"
2668 +
2669 +#include <linux/pci.h>
2670 +#include <linux/init.h>
2671 +#include <linux/module.h>
2672 +#include <linux/types.h>
2673 +#include <linux/kernel.h>
2674 +
2675 +#include <linux/sched.h>
2676 +#include <linux/ptrace.h>
2677 +#include <linux/slab.h>
2678 +#include <linux/ctype.h>
2679 +#include <linux/string.h>
2680 +#include <linux/timer.h>
2681 +#include <linux/interrupt.h>
2682 +#include <linux/in.h>
2683 +#include <linux/delay.h>
2684 +#include <asm/io.h>
2685 +#include <asm/system.h>
2686 +#include <asm/bitops.h>
2687 +
2688 +#include <linux/netdevice.h>
2689 +#include <linux/etherdevice.h>
2690 +#include <linux/skbuff.h>
2691 +#include <linux/if_arp.h>
2692 +#include <linux/ioport.h>
2693 +
2694 +#include "et1310_phy.h"
2695 +#include "et1310_pm.h"
2696 +#include "et1310_jagcore.h"
2697 +#include "et1310_eeprom.h"
2698 +
2699 +#include "et131x_adapter.h"
2700 +#include "et131x_initpci.h"
2701 +#include "et131x_isr.h"
2702 +
2703 +#include "et1310_tx.h"
2704 +
2705 +
2706 +/*
2707 + * EEPROM Defines
2708 + */
2709 +
2710 +/* LBCIF Register Groups (addressed via 32-bit offsets) */
2711 +#define LBCIF_DWORD0_GROUP_OFFSET 0xAC
2712 +#define LBCIF_DWORD1_GROUP_OFFSET 0xB0
2713 +
2714 +/* LBCIF Registers (addressed via 8-bit offsets) */
2715 +#define LBCIF_ADDRESS_REGISTER_OFFSET 0xAC
2716 +#define LBCIF_DATA_REGISTER_OFFSET 0xB0
2717 +#define LBCIF_CONTROL_REGISTER_OFFSET 0xB1
2718 +#define LBCIF_STATUS_REGISTER_OFFSET 0xB2
2719 +
2720 +/* LBCIF Control Register Bits */
2721 +#define LBCIF_CONTROL_SEQUENTIAL_READ 0x01
2722 +#define LBCIF_CONTROL_PAGE_WRITE 0x02
2723 +#define LBCIF_CONTROL_UNUSED1 0x04
2724 +#define LBCIF_CONTROL_EEPROM_RELOAD 0x08
2725 +#define LBCIF_CONTROL_UNUSED2 0x10
2726 +#define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20
2727 +#define LBCIF_CONTROL_I2C_WRITE 0x40
2728 +#define LBCIF_CONTROL_LBCIF_ENABLE 0x80
2729 +
2730 +/* LBCIF Status Register Bits */
2731 +#define LBCIF_STATUS_PHY_QUEUE_AVAIL 0x01
2732 +#define LBCIF_STATUS_I2C_IDLE 0x02
2733 +#define LBCIF_STATUS_ACK_ERROR 0x04
2734 +#define LBCIF_STATUS_GENERAL_ERROR 0x08
2735 +#define LBCIF_STATUS_UNUSED 0x30
2736 +#define LBCIF_STATUS_CHECKSUM_ERROR 0x40
2737 +#define LBCIF_STATUS_EEPROM_PRESENT 0x80
2738 +
2739 +/* Miscellaneous Constraints */
2740 +#define MAX_NUM_REGISTER_POLLS 1000
2741 +#define MAX_NUM_WRITE_RETRIES 2
2742 +
2743 +/*
2744 + * Define macros that allow individual register values to be extracted from a
2745 + * DWORD1 register grouping
2746 + */
2747 +#define EXTRACT_DATA_REGISTER(x) (uint8_t)(x & 0xFF)
2748 +#define EXTRACT_STATUS_REGISTER(x) (uint8_t)((x >> 16) & 0xFF)
2749 +#define EXTRACT_CONTROL_REG(x) (uint8_t)((x >> 8) & 0xFF)
2750 +
2751 +/**
2752 + * EepromWriteByte - Write a byte to the ET1310's EEPROM
2753 + * @pAdapter: pointer to our private adapter structure
2754 + * @unAddress: the address to write
2755 + * @bData: the value to write
2756 + * @unEepronId: the ID of the EEPROM
2757 + * @unAddressingMode: how the EEPROM is to be accessed
2758 + *
2759 + * Returns SUCCESS or FAILURE
2760 + */
2761 +int32_t EepromWriteByte(struct et131x_adapter *pAdapter, uint32_t unAddress,
2762 + uint8_t bData, uint32_t unEepromId,
2763 + uint32_t unAddressingMode)
2764 +{
2765 + struct pci_dev *pdev = pAdapter->pdev;
2766 + int32_t nIndex;
2767 + int32_t nRetries;
2768 + int32_t nError = false;
2769 + int32_t nI2CWriteActive = 0;
2770 + int32_t nWriteSuccessful = 0;
2771 + uint8_t bControl;
2772 + uint8_t bStatus = 0;
2773 + uint32_t unDword1 = 0;
2774 + uint32_t unData = 0;
2775 +
2776 + /*
2777 + * The following excerpt is from "Serial EEPROM HW Design
2778 + * Specification" Version 0.92 (9/20/2004):
2779 + *
2780 + * Single Byte Writes
2781 + *
2782 + * For an EEPROM, an I2C single byte write is defined as a START
2783 + * condition followed by the device address, EEPROM address, one byte
2784 + * of data and a STOP condition. The STOP condition will trigger the
2785 + * EEPROM's internally timed write cycle to the nonvolatile memory.
2786 + * All inputs are disabled during this write cycle and the EEPROM will
2787 + * not respond to any access until the internal write is complete.
2788 + * The steps to execute a single byte write are as follows:
2789 + *
2790 + * 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
2791 + * bits 7,1:0 both equal to 1, at least once after reset.
2792 + * Subsequent operations need only to check that bits 1:0 are
2793 + * equal to 1 prior to starting a single byte write.
2794 + *
2795 + * 2. Write to the LBCIF Control Register: bit 7=1, bit 6=1, bit 3=0,
2796 + * and bits 1:0 both =0. Bit 5 should be set according to the
2797 + * type of EEPROM being accessed (1=two byte addressing, 0=one
2798 + * byte addressing).
2799 + *
2800 + * 3. Write the address to the LBCIF Address Register.
2801 + *
2802 + * 4. Write the data to the LBCIF Data Register (the I2C write will
2803 + * begin).
2804 + *
2805 + * 5. Monitor bit 1:0 of the LBCIF Status Register. When bits 1:0 are
2806 + * both equal to 1, the I2C write has completed and the internal
2807 + * write cycle of the EEPROM is about to start. (bits 1:0 = 01 is
2808 + * a legal state while waiting from both equal to 1, but bits
2809 + * 1:0 = 10 is invalid and implies that something is broken).
2810 + *
2811 + * 6. Check bit 3 of the LBCIF Status Register. If equal to 1, an
2812 + * error has occurred.
2813 + *
2814 + * 7. Check bit 2 of the LBCIF Status Register. If equal to 1 an ACK
2815 + * error has occurred on the address phase of the write. This
2816 + * could be due to an actual hardware failure or the EEPROM may
2817 + * still be in its internal write cycle from a previous write.
2818 + * This write operation was ignored and must be repeated later.
2819 + *
2820 + * 8. Set bit 6 of the LBCIF Control Register = 0. If another write is
2821 + * required, go to step 1.
2822 + */
2823 +
2824 + /* Step 1: */
2825 + for (nIndex = 0; nIndex < MAX_NUM_REGISTER_POLLS; nIndex++) {
2826 + /* Read registers grouped in DWORD1 */
2827 + if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP_OFFSET,
2828 + &unDword1)) {
2829 + nError = 1;
2830 + break;
2831 + }
2832 +
2833 + bStatus = EXTRACT_STATUS_REGISTER(unDword1);
2834 +
2835 + if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL &&
2836 + bStatus & LBCIF_STATUS_I2C_IDLE) {
2837 + /* bits 1:0 are equal to 1 */
2838 + break;
2839 + }
2840 + }
2841 +
2842 + if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS)) {
2843 + return FAILURE;
2844 + }
2845 +
2846 + /* Step 2: */
2847 + bControl = 0;
2848 + bControl |= LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE;
2849 +
2850 + if (unAddressingMode == DUAL_BYTE) {
2851 + bControl |= LBCIF_CONTROL_TWO_BYTE_ADDR;
2852 + }
2853 +
2854 + if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER_OFFSET,
2855 + bControl)) {
2856 + return FAILURE;
2857 + }
2858 +
2859 + nI2CWriteActive = 1;
2860 +
2861 + /* Prepare EEPROM address for Step 3 */
2862 + unAddress |= (unAddressingMode == DUAL_BYTE) ?
2863 + (unEepromId << 16) : (unEepromId << 8);
2864 +
2865 + for (nRetries = 0; nRetries < MAX_NUM_WRITE_RETRIES; nRetries++) {
2866 + /* Step 3:*/
2867 + if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER_OFFSET,
2868 + unAddress)) {
2869 + break;
2870 + }
2871 +
2872 + /* Step 4: */
2873 + if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER_OFFSET,
2874 + bData)) {
2875 + break;
2876 + }
2877 +
2878 + /* Step 5: */
2879 + for (nIndex = 0; nIndex < MAX_NUM_REGISTER_POLLS; nIndex++) {
2880 + /* Read registers grouped in DWORD1 */
2881 + if (pci_read_config_dword(pdev,
2882 + LBCIF_DWORD1_GROUP_OFFSET,
2883 + &unDword1)) {
2884 + nError = 1;
2885 + break;
2886 + }
2887 +
2888 + bStatus = EXTRACT_STATUS_REGISTER(unDword1);
2889 +
2890 + if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL &&
2891 + bStatus & LBCIF_STATUS_I2C_IDLE) {
2892 + /* I2C write complete */
2893 + break;
2894 + }
2895 + }
2896 +
2897 + if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS)) {
2898 + break;
2899 + }
2900 +
2901 + /*
2902 + * Step 6: Don't break here if we are revision 1, this is
2903 + * so we do a blind write for load bug.
2904 + */
2905 + if (bStatus & LBCIF_STATUS_GENERAL_ERROR
2906 + && pAdapter->RevisionID == 0) {
2907 + break;
2908 + }
2909 +
2910 + /* Step 7 */
2911 + if (bStatus & LBCIF_STATUS_ACK_ERROR) {
2912 + /*
2913 + * This could be due to an actual hardware failure
2914 + * or the EEPROM may still be in its internal write
2915 + * cycle from a previous write. This write operation
2916 + * was ignored and must be repeated later.
2917 + */
2918 + udelay(10);
2919 + continue;
2920 + }
2921 +
2922 + nWriteSuccessful = 1;
2923 + break;
2924 + }
2925 +
2926 + /* Step 8: */
2927 + udelay(10);
2928 + nIndex = 0;
2929 + while (nI2CWriteActive) {
2930 + bControl &= ~LBCIF_CONTROL_I2C_WRITE;
2931 +
2932 + if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER_OFFSET,
2933 + bControl)) {
2934 + nWriteSuccessful = 0;
2935 + }
2936 +
2937 + /* Do read until internal ACK_ERROR goes away meaning write
2938 + * completed
2939 + */
2940 + do {
2941 + pci_write_config_dword(pdev,
2942 + LBCIF_ADDRESS_REGISTER_OFFSET,
2943 + unAddress);
2944 + do {
2945 + pci_read_config_dword(pdev,
2946 + LBCIF_DATA_REGISTER_OFFSET, &unData);
2947 + } while ((unData & 0x00010000) == 0);
2948 + } while (unData & 0x00040000);
2949 +
2950 + bControl = EXTRACT_CONTROL_REG(unData);
2951 +
2952 + if (bControl != 0xC0 || nIndex == 10000) {
2953 + break;
2954 + }
2955 +
2956 + nIndex++;
2957 + }
2958 +
2959 + return nWriteSuccessful ? SUCCESS : FAILURE;
2960 +}
2961 +
2962 +/**
2963 + * EepromReadByte - Read a byte from the ET1310's EEPROM
2964 + * @pAdapter: pointer to our private adapter structure
2965 + * @unAddress: the address from which to read
2966 + * @pbData: a pointer to a byte in which to store the value of the read
2967 + * @unEepronId: the ID of the EEPROM
2968 + * @unAddressingMode: how the EEPROM is to be accessed
2969 + *
2970 + * Returns SUCCESS or FAILURE
2971 + */
2972 +int32_t EepromReadByte(struct et131x_adapter *pAdapter, uint32_t unAddress,
2973 + uint8_t *pbData, uint32_t unEepromId,
2974 + uint32_t unAddressingMode)
2975 +{
2976 + struct pci_dev *pdev = pAdapter->pdev;
2977 + int32_t nIndex;
2978 + int32_t nError = 0;
2979 + uint8_t bControl;
2980 + uint8_t bStatus = 0;
2981 + uint32_t unDword1 = 0;
2982 +
2983 + /*
2984 + * The following excerpt is from "Serial EEPROM HW Design
2985 + * Specification" Version 0.92 (9/20/2004):
2986 + *
2987 + * Single Byte Reads
2988 + *
2989 + * A single byte read is similar to the single byte write, with the
2990 + * exception of the data flow:
2991 + *
2992 + * 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
2993 + * bits 7,1:0 both equal to 1, at least once after reset.
2994 + * Subsequent operations need only to check that bits 1:0 are equal
2995 + * to 1 prior to starting a single byte read.
2996 + *
2997 + * 2. Write to the LBCIF Control Register: bit 7=1, bit 6=0, bit 3=0,
2998 + * and bits 1:0 both =0. Bit 5 should be set according to the type
2999 + * of EEPROM being accessed (1=two byte addressing, 0=one byte
3000 + * addressing).
3001 + *
3002 + * 3. Write the address to the LBCIF Address Register (I2C read will
3003 + * begin).
3004 + *
3005 + * 4. Monitor bit 0 of the LBCIF Status Register. When =1, I2C read
3006 + * is complete. (if bit 1 =1 and bit 0 stays =0, a hardware failure
3007 + * has occurred).
3008 + *
3009 + * 5. Check bit 2 of the LBCIF Status Register. If =1, then an error
3010 + * has occurred. The data that has been returned from the PHY may
3011 + * be invalid.
3012 + *
3013 + * 6. Regardless of error status, read data byte from LBCIF Data
3014 + * Register. If another byte is required, go to step 1.
3015 + */
3016 +
3017 + /* Step 1: */
3018 + for (nIndex = 0; nIndex < MAX_NUM_REGISTER_POLLS; nIndex++) {
3019 + /* Read registers grouped in DWORD1 */
3020 + if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP_OFFSET,
3021 + &unDword1)) {
3022 + nError = 1;
3023 + break;
3024 + }
3025 +
3026 + bStatus = EXTRACT_STATUS_REGISTER(unDword1);
3027 +
3028 + if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL &&
3029 + bStatus & LBCIF_STATUS_I2C_IDLE) {
3030 + /* bits 1:0 are equal to 1 */
3031 + break;
3032 + }
3033 + }
3034 +
3035 + if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS)) {
3036 + return FAILURE;
3037 + }
3038 +
3039 + /* Step 2: */
3040 + bControl = 0;
3041 + bControl |= LBCIF_CONTROL_LBCIF_ENABLE;
3042 +
3043 + if (unAddressingMode == DUAL_BYTE) {
3044 + bControl |= LBCIF_CONTROL_TWO_BYTE_ADDR;
3045 + }
3046 +
3047 + if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER_OFFSET,
3048 + bControl)) {
3049 + return FAILURE;
3050 + }
3051 +
3052 + /* Step 3: */
3053 + unAddress |= (unAddressingMode == DUAL_BYTE) ?
3054 + (unEepromId << 16) : (unEepromId << 8);
3055 +
3056 + if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER_OFFSET,
3057 + unAddress)) {
3058 + return FAILURE;
3059 + }
3060 +
3061 + /* Step 4: */
3062 + for (nIndex = 0; nIndex < MAX_NUM_REGISTER_POLLS; nIndex++) {
3063 + /* Read registers grouped in DWORD1 */
3064 + if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP_OFFSET,
3065 + &unDword1)) {
3066 + nError = 1;
3067 + break;
3068 + }
3069 +
3070 + bStatus = EXTRACT_STATUS_REGISTER(unDword1);
3071 +
3072 + if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL
3073 + && bStatus & LBCIF_STATUS_I2C_IDLE) {
3074 + /* I2C read complete */
3075 + break;
3076 + }
3077 + }
3078 +
3079 + if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS)) {
3080 + return FAILURE;
3081 + }
3082 +
3083 + /* Step 6: */
3084 + *pbData = EXTRACT_DATA_REGISTER(unDword1);
3085 +
3086 + return (bStatus & LBCIF_STATUS_ACK_ERROR) ? FAILURE : SUCCESS;
3087 +}
3088 diff --git a/drivers/staging/et131x/et1310_eeprom.h b/drivers/staging/et131x/et1310_eeprom.h
3089 new file mode 100644
3090 index 0000000..9b6f8ad
3091 --- /dev/null
3092 +++ b/drivers/staging/et131x/et1310_eeprom.h
3093 @@ -0,0 +1,89 @@
3094 +/*
3095 + * Agere Systems Inc.
3096 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
3097 + *
3098 + * Copyright © 2005 Agere Systems Inc.
3099 + * All rights reserved.
3100 + * http://www.agere.com
3101 + *
3102 + *------------------------------------------------------------------------------
3103 + *
3104 + * et1310_eeprom.h - Defines, structs, enums, prototypes, etc. used for EEPROM
3105 + * access routines
3106 + *
3107 + *------------------------------------------------------------------------------
3108 + *
3109 + * SOFTWARE LICENSE
3110 + *
3111 + * This software is provided subject to the following terms and conditions,
3112 + * which you should read carefully before using the software. Using this
3113 + * software indicates your acceptance of these terms and conditions. If you do
3114 + * not agree with these terms and conditions, do not use the software.
3115 + *
3116 + * Copyright © 2005 Agere Systems Inc.
3117 + * All rights reserved.
3118 + *
3119 + * Redistribution and use in source or binary forms, with or without
3120 + * modifications, are permitted provided that the following conditions are met:
3121 + *
3122 + * . Redistributions of source code must retain the above copyright notice, this
3123 + * list of conditions and the following Disclaimer as comments in the code as
3124 + * well as in the documentation and/or other materials provided with the
3125 + * distribution.
3126 + *
3127 + * . Redistributions in binary form must reproduce the above copyright notice,
3128 + * this list of conditions and the following Disclaimer in the documentation
3129 + * and/or other materials provided with the distribution.
3130 + *
3131 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
3132 + * may be used to endorse or promote products derived from this software
3133 + * without specific prior written permission.
3134 + *
3135 + * Disclaimer
3136 + *
3137 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
3138 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
3139 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
3140 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
3141 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
3142 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
3143 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
3144 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
3145 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
3146 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
3147 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
3148 + * DAMAGE.
3149 + *
3150 + */
3151 +
3152 +#ifndef __ET1310_EEPROM_H__
3153 +#define __ET1310_EEPROM_H__
3154 +
3155 +#include "et1310_address_map.h"
3156 +
3157 +#ifndef SUCCESS
3158 +#define SUCCESS 0
3159 +#define FAILURE 1
3160 +#endif
3161 +
3162 +#ifndef READ
3163 +#define READ 0
3164 +#define WRITE 1
3165 +#endif
3166 +
3167 +#ifndef SINGLE_BYTE
3168 +#define SINGLE_BYTE 0
3169 +#define DUAL_BYTE 1
3170 +#endif
3171 +
3172 +/* Forward declaration of the private adapter structure */
3173 +struct et131x_adapter;
3174 +
3175 +int32_t EepromWriteByte(struct et131x_adapter *adapter, u32 unAddress,
3176 + u8 bData, u32 unEepromId,
3177 + u32 unAddressingMode);
3178 +int32_t EepromReadByte(struct et131x_adapter *adapter, u32 unAddress,
3179 + u8 *pbData, u32 unEepromId,
3180 + u32 unAddressingMode);
3181 +
3182 +#endif /* _ET1310_EEPROM_H_ */
3183 diff --git a/drivers/staging/et131x/et1310_jagcore.c b/drivers/staging/et131x/et1310_jagcore.c
3184 new file mode 100644
3185 index 0000000..993b30e
3186 --- /dev/null
3187 +++ b/drivers/staging/et131x/et1310_jagcore.c
3188 @@ -0,0 +1,220 @@
3189 +/*
3190 + * Agere Systems Inc.
3191 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
3192 + *
3193 + * Copyright © 2005 Agere Systems Inc.
3194 + * All rights reserved.
3195 + * http://www.agere.com
3196 + *
3197 + *------------------------------------------------------------------------------
3198 + *
3199 + * et1310_jagcore.c - All code pertaining to the ET1301/ET131x's JAGcore
3200 + *
3201 + *------------------------------------------------------------------------------
3202 + *
3203 + * SOFTWARE LICENSE
3204 + *
3205 + * This software is provided subject to the following terms and conditions,
3206 + * which you should read carefully before using the software. Using this
3207 + * software indicates your acceptance of these terms and conditions. If you do
3208 + * not agree with these terms and conditions, do not use the software.
3209 + *
3210 + * Copyright © 2005 Agere Systems Inc.
3211 + * All rights reserved.
3212 + *
3213 + * Redistribution and use in source or binary forms, with or without
3214 + * modifications, are permitted provided that the following conditions are met:
3215 + *
3216 + * . Redistributions of source code must retain the above copyright notice, this
3217 + * list of conditions and the following Disclaimer as comments in the code as
3218 + * well as in the documentation and/or other materials provided with the
3219 + * distribution.
3220 + *
3221 + * . Redistributions in binary form must reproduce the above copyright notice,
3222 + * this list of conditions and the following Disclaimer in the documentation
3223 + * and/or other materials provided with the distribution.
3224 + *
3225 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
3226 + * may be used to endorse or promote products derived from this software
3227 + * without specific prior written permission.
3228 + *
3229 + * Disclaimer
3230 + *
3231 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
3232 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
3233 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
3234 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
3235 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
3236 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
3237 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
3238 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
3239 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
3240 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
3241 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
3242 + * DAMAGE.
3243 + *
3244 + */
3245 +
3246 +#include "et131x_version.h"
3247 +#include "et131x_debug.h"
3248 +#include "et131x_defs.h"
3249 +
3250 +#include <linux/init.h>
3251 +#include <linux/module.h>
3252 +#include <linux/types.h>
3253 +#include <linux/kernel.h>
3254 +
3255 +#include <linux/sched.h>
3256 +#include <linux/ptrace.h>
3257 +#include <linux/slab.h>
3258 +#include <linux/ctype.h>
3259 +#include <linux/string.h>
3260 +#include <linux/timer.h>
3261 +#include <linux/interrupt.h>
3262 +#include <linux/in.h>
3263 +#include <linux/delay.h>
3264 +#include <asm/io.h>
3265 +#include <asm/system.h>
3266 +#include <asm/bitops.h>
3267 +
3268 +#include <linux/netdevice.h>
3269 +#include <linux/etherdevice.h>
3270 +#include <linux/skbuff.h>
3271 +#include <linux/if_arp.h>
3272 +#include <linux/ioport.h>
3273 +
3274 +#include "et1310_phy.h"
3275 +#include "et1310_pm.h"
3276 +#include "et1310_jagcore.h"
3277 +
3278 +#include "et131x_adapter.h"
3279 +#include "et131x_initpci.h"
3280 +
3281 +/* Data for debugging facilities */
3282 +#ifdef CONFIG_ET131X_DEBUG
3283 +extern dbg_info_t *et131x_dbginfo;
3284 +#endif /* CONFIG_ET131X_DEBUG */
3285 +
3286 +/**
3287 + * ConfigGlobalRegs - Used to configure the global registers on the JAGCore
3288 + * @pAdpater: pointer to our adapter structure
3289 + */
3290 +void ConfigGlobalRegs(struct et131x_adapter *pAdapter)
3291 +{
3292 + struct _GLOBAL_t __iomem *pGbl = &pAdapter->CSRAddress->global;
3293 +
3294 + DBG_ENTER(et131x_dbginfo);
3295 +
3296 + if (pAdapter->RegistryPhyLoopbk == false) {
3297 + if (pAdapter->RegistryJumboPacket < 2048) {
3298 + /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
3299 + * block of RAM that the driver can split between Tx
3300 + * and Rx as it desires. Our default is to split it
3301 + * 50/50:
3302 + */
3303 + writel(0, &pGbl->rxq_start_addr.value);
3304 + writel(pAdapter->RegistryRxMemEnd,
3305 + &pGbl->rxq_end_addr.value);
3306 + writel(pAdapter->RegistryRxMemEnd + 1,
3307 + &pGbl->txq_start_addr.value);
3308 + writel(INTERNAL_MEM_SIZE - 1,
3309 + &pGbl->txq_end_addr.value);
3310 + } else if (pAdapter->RegistryJumboPacket < 8192) {
3311 + /* For jumbo packets > 2k but < 8k, split 50-50. */
3312 + writel(0, &pGbl->rxq_start_addr.value);
3313 + writel(INTERNAL_MEM_RX_OFFSET,
3314 + &pGbl->rxq_end_addr.value);
3315 + writel(INTERNAL_MEM_RX_OFFSET + 1,
3316 + &pGbl->txq_start_addr.value);
3317 + writel(INTERNAL_MEM_SIZE - 1,
3318 + &pGbl->txq_end_addr.value);
3319 + } else {
3320 + /* 9216 is the only packet size greater than 8k that
3321 + * is available. The Tx buffer has to be big enough
3322 + * for one whole packet on the Tx side. We'll make
3323 + * the Tx 9408, and give the rest to Rx
3324 + */
3325 + writel(0x0000, &pGbl->rxq_start_addr.value);
3326 + writel(0x01b3, &pGbl->rxq_end_addr.value);
3327 + writel(0x01b4, &pGbl->txq_start_addr.value);
3328 + writel(INTERNAL_MEM_SIZE - 1,
3329 + &pGbl->txq_end_addr.value);
3330 + }
3331 +
3332 + /* Initialize the loopback register. Disable all loopbacks. */
3333 + writel(0, &pGbl->loopback.value);
3334 + } else {
3335 + /* For PHY Line loopback, the memory is configured as if Tx
3336 + * and Rx both have all the memory. This is because the
3337 + * RxMAC will write data into the space, and the TxMAC will
3338 + * read it out.
3339 + */
3340 + writel(0, &pGbl->rxq_start_addr.value);
3341 + writel(INTERNAL_MEM_SIZE - 1, &pGbl->rxq_end_addr.value);
3342 + writel(0, &pGbl->txq_start_addr.value);
3343 + writel(INTERNAL_MEM_SIZE - 1, &pGbl->txq_end_addr.value);
3344 +
3345 + /* Initialize the loopback register (MAC loopback). */
3346 + writel(1, &pGbl->loopback.value);
3347 + }
3348 +
3349 + /* MSI Register */
3350 + writel(0, &pGbl->msi_config.value);
3351 +
3352 + /* By default, disable the watchdog timer. It will be enabled when
3353 + * a packet is queued.
3354 + */
3355 + writel(0, &pGbl->watchdog_timer);
3356 +
3357 + DBG_LEAVE(et131x_dbginfo);
3358 +}
3359 +
3360 +/**
3361 + * ConfigMMCRegs - Used to configure the main memory registers in the JAGCore
3362 + * @pAdapter: pointer to our adapter structure
3363 + */
3364 +void ConfigMMCRegs(struct et131x_adapter *pAdapter)
3365 +{
3366 + MMC_CTRL_t mmc_ctrl = { 0 };
3367 +
3368 + DBG_ENTER(et131x_dbginfo);
3369 +
3370 + /* All we need to do is initialize the Memory Control Register */
3371 + mmc_ctrl.bits.force_ce = 0x0;
3372 + mmc_ctrl.bits.rxdma_disable = 0x0;
3373 + mmc_ctrl.bits.txdma_disable = 0x0;
3374 + mmc_ctrl.bits.txmac_disable = 0x0;
3375 + mmc_ctrl.bits.rxmac_disable = 0x0;
3376 + mmc_ctrl.bits.arb_disable = 0x0;
3377 + mmc_ctrl.bits.mmc_enable = 0x1;
3378 +
3379 + writel(mmc_ctrl.value, &pAdapter->CSRAddress->mmc.mmc_ctrl.value);
3380 +
3381 + DBG_LEAVE(et131x_dbginfo);
3382 +}
3383 +
3384 +void et131x_enable_interrupts(struct et131x_adapter *adapter)
3385 +{
3386 + uint32_t MaskValue;
3387 +
3388 + /* Enable all global interrupts */
3389 + if ((adapter->FlowControl == TxOnly) || (adapter->FlowControl == Both)) {
3390 + MaskValue = INT_MASK_ENABLE;
3391 + } else {
3392 + MaskValue = INT_MASK_ENABLE_NO_FLOW;
3393 + }
3394 +
3395 + if (adapter->DriverNoPhyAccess) {
3396 + MaskValue |= 0x10000;
3397 + }
3398 +
3399 + adapter->CachedMaskValue.value = MaskValue;
3400 + writel(MaskValue, &adapter->CSRAddress->global.int_mask.value);
3401 +}
3402 +
3403 +void et131x_disable_interrupts(struct et131x_adapter * adapter)
3404 +{
3405 + /* Disable all global interrupts */
3406 + adapter->CachedMaskValue.value = INT_MASK_DISABLE;
3407 + writel(INT_MASK_DISABLE, &adapter->CSRAddress->global.int_mask.value);
3408 +}
3409 diff --git a/drivers/staging/et131x/et1310_jagcore.h b/drivers/staging/et131x/et1310_jagcore.h
3410 new file mode 100644
3411 index 0000000..9fc8293
3412 --- /dev/null
3413 +++ b/drivers/staging/et131x/et1310_jagcore.h
3414 @@ -0,0 +1,112 @@
3415 +/*
3416 + * Agere Systems Inc.
3417 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
3418 + *
3419 + * Copyright © 2005 Agere Systems Inc.
3420 + * All rights reserved.
3421 + * http://www.agere.com
3422 + *
3423 + *------------------------------------------------------------------------------
3424 + *
3425 + * et1310_jagcore.h - Defines, structs, enums, prototypes, etc. pertaining to
3426 + * the JAGCore
3427 + *
3428 + *------------------------------------------------------------------------------
3429 + *
3430 + * SOFTWARE LICENSE
3431 + *
3432 + * This software is provided subject to the following terms and conditions,
3433 + * which you should read carefully before using the software. Using this
3434 + * software indicates your acceptance of these terms and conditions. If you do
3435 + * not agree with these terms and conditions, do not use the software.
3436 + *
3437 + * Copyright © 2005 Agere Systems Inc.
3438 + * All rights reserved.
3439 + *
3440 + * Redistribution and use in source or binary forms, with or without
3441 + * modifications, are permitted provided that the following conditions are met:
3442 + *
3443 + * . Redistributions of source code must retain the above copyright notice, this
3444 + * list of conditions and the following Disclaimer as comments in the code as
3445 + * well as in the documentation and/or other materials provided with the
3446 + * distribution.
3447 + *
3448 + * . Redistributions in binary form must reproduce the above copyright notice,
3449 + * this list of conditions and the following Disclaimer in the documentation
3450 + * and/or other materials provided with the distribution.
3451 + *
3452 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
3453 + * may be used to endorse or promote products derived from this software
3454 + * without specific prior written permission.
3455 + *
3456 + * Disclaimer
3457 + *
3458 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
3459 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
3460 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
3461 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
3462 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
3463 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
3464 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
3465 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
3466 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
3467 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
3468 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
3469 + * DAMAGE.
3470 + *
3471 + */
3472 +
3473 +#ifndef __ET1310_JAGCORE_H__
3474 +#define __ET1310_JAGCORE_H__
3475 +
3476 +#include "et1310_address_map.h"
3477 +
3478 +
3479 +#define INTERNAL_MEM_SIZE 0x400 //1024 of internal memory
3480 +#define INTERNAL_MEM_RX_OFFSET 0x1FF //50% Tx, 50% Rx
3481 +
3482 +#define REGS_MAX_ARRAY 4096
3483 +
3484 +/*
3485 + * For interrupts, normal running is:
3486 + * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
3487 + * watchdog_interrupt & txdma_xfer_done
3488 + *
3489 + * In both cases, when flow control is enabled for either Tx or bi-direction,
3490 + * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
3491 + * buffer rings are running low.
3492 + */
3493 +#define INT_MASK_DISABLE 0xffffffff
3494 +
3495 +// NOTE: Masking out MAC_STAT Interrupt for now...
3496 +//#define INT_MASK_ENABLE 0xfff6bf17
3497 +//#define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7
3498 +#define INT_MASK_ENABLE 0xfffebf17
3499 +#define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
3500 +
3501 +/* DATA STRUCTURES FOR DIRECT REGISTER ACCESS */
3502 +
3503 +typedef struct {
3504 + u8 bReadWrite;
3505 + u32 nRegCount;
3506 + u32 nData[REGS_MAX_ARRAY];
3507 + u32 nOffsets[REGS_MAX_ARRAY];
3508 +} JAGCORE_ACCESS_REGS, *PJAGCORE_ACCESS_REGS;
3509 +
3510 +typedef struct {
3511 + u8 bReadWrite;
3512 + u32 nDataWidth;
3513 + u32 nRegCount;
3514 + u32 nOffsets[REGS_MAX_ARRAY];
3515 + u32 nData[REGS_MAX_ARRAY];
3516 +} PCI_CFG_SPACE_REGS, *PPCI_CFG_SPACE_REGS;
3517 +
3518 +/* Forward declaration of the private adapter structure */
3519 +struct et131x_adapter;
3520 +
3521 +void ConfigGlobalRegs(struct et131x_adapter *pAdapter);
3522 +void ConfigMMCRegs(struct et131x_adapter *pAdapter);
3523 +void et131x_enable_interrupts(struct et131x_adapter *adapter);
3524 +void et131x_disable_interrupts(struct et131x_adapter *adapter);
3525 +
3526 +#endif /* __ET1310_JAGCORE_H__ */
3527 diff --git a/drivers/staging/et131x/et1310_mac.c b/drivers/staging/et131x/et1310_mac.c
3528 new file mode 100644
3529 index 0000000..1924968
3530 --- /dev/null
3531 +++ b/drivers/staging/et131x/et1310_mac.c
3532 @@ -0,0 +1,792 @@
3533 +/*
3534 + * Agere Systems Inc.
3535 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
3536 + *
3537 + * Copyright © 2005 Agere Systems Inc.
3538 + * All rights reserved.
3539 + * http://www.agere.com
3540 + *
3541 + *------------------------------------------------------------------------------
3542 + *
3543 + * et1310_mac.c - All code and routines pertaining to the MAC
3544 + *
3545 + *------------------------------------------------------------------------------
3546 + *
3547 + * SOFTWARE LICENSE
3548 + *
3549 + * This software is provided subject to the following terms and conditions,
3550 + * which you should read carefully before using the software. Using this
3551 + * software indicates your acceptance of these terms and conditions. If you do
3552 + * not agree with these terms and conditions, do not use the software.
3553 + *
3554 + * Copyright © 2005 Agere Systems Inc.
3555 + * All rights reserved.
3556 + *
3557 + * Redistribution and use in source or binary forms, with or without
3558 + * modifications, are permitted provided that the following conditions are met:
3559 + *
3560 + * . Redistributions of source code must retain the above copyright notice, this
3561 + * list of conditions and the following Disclaimer as comments in the code as
3562 + * well as in the documentation and/or other materials provided with the
3563 + * distribution.
3564 + *
3565 + * . Redistributions in binary form must reproduce the above copyright notice,
3566 + * this list of conditions and the following Disclaimer in the documentation
3567 + * and/or other materials provided with the distribution.
3568 + *
3569 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
3570 + * may be used to endorse or promote products derived from this software
3571 + * without specific prior written permission.
3572 + *
3573 + * Disclaimer
3574 + *
3575 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
3576 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
3577 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
3578 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
3579 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
3580 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
3581 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
3582 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
3583 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
3584 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
3585 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
3586 + * DAMAGE.
3587 + *
3588 + */
3589 +
3590 +#include "et131x_version.h"
3591 +#include "et131x_debug.h"
3592 +#include "et131x_defs.h"
3593 +
3594 +#include <linux/init.h>
3595 +#include <linux/module.h>
3596 +#include <linux/types.h>
3597 +#include <linux/kernel.h>
3598 +
3599 +#include <linux/sched.h>
3600 +#include <linux/ptrace.h>
3601 +#include <linux/slab.h>
3602 +#include <linux/ctype.h>
3603 +#include <linux/string.h>
3604 +#include <linux/timer.h>
3605 +#include <linux/interrupt.h>
3606 +#include <linux/in.h>
3607 +#include <linux/delay.h>
3608 +#include <asm/io.h>
3609 +#include <asm/system.h>
3610 +#include <asm/bitops.h>
3611 +
3612 +#include <linux/netdevice.h>
3613 +#include <linux/etherdevice.h>
3614 +#include <linux/skbuff.h>
3615 +#include <linux/if_arp.h>
3616 +#include <linux/ioport.h>
3617 +#include <linux/crc32.h>
3618 +
3619 +#include "et1310_phy.h"
3620 +#include "et1310_pm.h"
3621 +#include "et1310_jagcore.h"
3622 +#include "et1310_mac.h"
3623 +
3624 +#include "et131x_adapter.h"
3625 +#include "et131x_initpci.h"
3626 +
3627 +/* Data for debugging facilities */
3628 +#ifdef CONFIG_ET131X_DEBUG
3629 +extern dbg_info_t *et131x_dbginfo;
3630 +#endif /* CONFIG_ET131X_DEBUG */
3631 +
3632 +/**
3633 + * ConfigMacRegs1 - Initialize the first part of MAC regs
3634 + * @pAdpater: pointer to our adapter structure
3635 + */
3636 +void ConfigMACRegs1(struct et131x_adapter *pAdapter)
3637 +{
3638 + struct _MAC_t __iomem *pMac = &pAdapter->CSRAddress->mac;
3639 + MAC_STATION_ADDR1_t station1;
3640 + MAC_STATION_ADDR2_t station2;
3641 + MAC_IPG_t ipg;
3642 + MAC_HFDP_t hfdp;
3643 + MII_MGMT_CFG_t mii_mgmt_cfg;
3644 +
3645 + DBG_ENTER(et131x_dbginfo);
3646 +
3647 + /* First we need to reset everything. Write to MAC configuration
3648 + * register 1 to perform reset.
3649 + */
3650 + writel(0xC00F0000, &pMac->cfg1.value);
3651 +
3652 + /* Next lets configure the MAC Inter-packet gap register */
3653 + ipg.bits.non_B2B_ipg_1 = 0x38; // 58d
3654 + ipg.bits.non_B2B_ipg_2 = 0x58; // 88d
3655 + ipg.bits.min_ifg_enforce = 0x50; // 80d
3656 + ipg.bits.B2B_ipg = 0x60; // 96d
3657 + writel(ipg.value, &pMac->ipg.value);
3658 +
3659 + /* Next lets configure the MAC Half Duplex register */
3660 + hfdp.bits.alt_beb_trunc = 0xA;
3661 + hfdp.bits.alt_beb_enable = 0x0;
3662 + hfdp.bits.bp_no_backoff = 0x0;
3663 + hfdp.bits.no_backoff = 0x0;
3664 + hfdp.bits.excess_defer = 0x1;
3665 + hfdp.bits.rexmit_max = 0xF;
3666 + hfdp.bits.coll_window = 0x37; // 55d
3667 + writel(hfdp.value, &pMac->hfdp.value);
3668 +
3669 + /* Next lets configure the MAC Interface Control register */
3670 + writel(0, &pMac->if_ctrl.value);
3671 +
3672 + /* Let's move on to setting up the mii managment configuration */
3673 + mii_mgmt_cfg.bits.reset_mii_mgmt = 0;
3674 + mii_mgmt_cfg.bits.scan_auto_incremt = 0;
3675 + mii_mgmt_cfg.bits.preamble_suppress = 0;
3676 + mii_mgmt_cfg.bits.mgmt_clk_reset = 0x7;
3677 + writel(mii_mgmt_cfg.value, &pMac->mii_mgmt_cfg.value);
3678 +
3679 + /* Next lets configure the MAC Station Address register. These
3680 + * values are read from the EEPROM during initialization and stored
3681 + * in the adapter structure. We write what is stored in the adapter
3682 + * structure to the MAC Station Address registers high and low. This
3683 + * station address is used for generating and checking pause control
3684 + * packets.
3685 + */
3686 + station2.bits.Octet1 = pAdapter->CurrentAddress[0];
3687 + station2.bits.Octet2 = pAdapter->CurrentAddress[1];
3688 + station1.bits.Octet3 = pAdapter->CurrentAddress[2];
3689 + station1.bits.Octet4 = pAdapter->CurrentAddress[3];
3690 + station1.bits.Octet5 = pAdapter->CurrentAddress[4];
3691 + station1.bits.Octet6 = pAdapter->CurrentAddress[5];
3692 + writel(station1.value, &pMac->station_addr_1.value);
3693 + writel(station2.value, &pMac->station_addr_2.value);
3694 +
3695 + /* Max ethernet packet in bytes that will passed by the mac without
3696 + * being truncated. Allow the MAC to pass 4 more than our max packet
3697 + * size. This is 4 for the Ethernet CRC.
3698 + *
3699 + * Packets larger than (RegistryJumboPacket) that do not contain a
3700 + * VLAN ID will be dropped by the Rx function.
3701 + */
3702 + writel(pAdapter->RegistryJumboPacket + 4, &pMac->max_fm_len.value);
3703 +
3704 + /* clear out MAC config reset */
3705 + writel(0, &pMac->cfg1.value);
3706 +
3707 + DBG_LEAVE(et131x_dbginfo);
3708 +}
3709 +
3710 +/**
3711 + * ConfigMacRegs2 - Initialize the second part of MAC regs
3712 + * @pAdpater: pointer to our adapter structure
3713 + */
3714 +void ConfigMACRegs2(struct et131x_adapter *pAdapter)
3715 +{
3716 + int32_t delay = 0;
3717 + struct _MAC_t __iomem *pMac = &pAdapter->CSRAddress->mac;
3718 + MAC_CFG1_t cfg1;
3719 + MAC_CFG2_t cfg2;
3720 + MAC_IF_CTRL_t ifctrl;
3721 + TXMAC_CTL_t ctl;
3722 +
3723 + DBG_ENTER(et131x_dbginfo);
3724 +
3725 + ctl.value = readl(&pAdapter->CSRAddress->txmac.ctl.value);
3726 + cfg1.value = readl(&pMac->cfg1.value);
3727 + cfg2.value = readl(&pMac->cfg2.value);
3728 + ifctrl.value = readl(&pMac->if_ctrl.value);
3729 +
3730 + if (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
3731 + cfg2.bits.if_mode = 0x2;
3732 + ifctrl.bits.phy_mode = 0x0;
3733 + } else {
3734 + cfg2.bits.if_mode = 0x1;
3735 + ifctrl.bits.phy_mode = 0x1;
3736 + }
3737 +
3738 + /* We need to enable Rx/Tx */
3739 + cfg1.bits.rx_enable = 0x1;
3740 + cfg1.bits.tx_enable = 0x1;
3741 +
3742 + /* Set up flow control */
3743 + cfg1.bits.tx_flow = 0x1;
3744 +
3745 + if ((pAdapter->FlowControl == RxOnly) ||
3746 + (pAdapter->FlowControl == Both)) {
3747 + cfg1.bits.rx_flow = 0x1;
3748 + } else {
3749 + cfg1.bits.rx_flow = 0x0;
3750 + }
3751 +
3752 + /* Initialize loop back to off */
3753 + cfg1.bits.loop_back = 0;
3754 +
3755 + writel(cfg1.value, &pMac->cfg1.value);
3756 +
3757 + /* Now we need to initialize the MAC Configuration 2 register */
3758 + cfg2.bits.preamble_len = 0x7;
3759 + cfg2.bits.huge_frame = 0x0;
3760 + /* LENGTH FIELD CHECKING bit4: Set this bit to cause the MAC to check
3761 + * the frame's length field to ensure it matches the actual data
3762 + * field length. Clear this bit if no length field checking is
3763 + * desired. Its default is 0.
3764 + */
3765 + cfg2.bits.len_check = 0x1;
3766 +
3767 + if (pAdapter->RegistryPhyLoopbk == false) {
3768 + cfg2.bits.pad_crc = 0x1;
3769 + cfg2.bits.crc_enable = 0x1;
3770 + } else {
3771 + cfg2.bits.pad_crc = 0;
3772 + cfg2.bits.crc_enable = 0;
3773 + }
3774 +
3775 + /* 1 - full duplex, 0 - half-duplex */
3776 + cfg2.bits.full_duplex = pAdapter->uiDuplexMode;
3777 + ifctrl.bits.ghd_mode = !pAdapter->uiDuplexMode;
3778 +
3779 + writel(ifctrl.value, &pMac->if_ctrl.value);
3780 + writel(cfg2.value, &pMac->cfg2.value);
3781 +
3782 + do {
3783 + udelay(10);
3784 + delay++;
3785 + cfg1.value = readl(&pMac->cfg1.value);
3786 + } while ((!cfg1.bits.syncd_rx_en ||
3787 + !cfg1.bits.syncd_tx_en) &&
3788 + delay < 100);
3789 +
3790 + if (delay == 100) {
3791 + DBG_ERROR(et131x_dbginfo,
3792 + "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
3793 + cfg1.value);
3794 + }
3795 +
3796 + DBG_TRACE(et131x_dbginfo,
3797 + "Speed %d, Dup %d, CFG1 0x%08x, CFG2 0x%08x, if_ctrl 0x%08x\n",
3798 + pAdapter->uiLinkSpeed, pAdapter->uiDuplexMode,
3799 + readl(&pMac->cfg1.value), readl(&pMac->cfg2.value),
3800 + readl(&pMac->if_ctrl.value));
3801 +
3802 + /* Enable TXMAC */
3803 + ctl.bits.txmac_en = 0x1;
3804 + ctl.bits.fc_disable = 0x1;
3805 + writel(ctl.value, &pAdapter->CSRAddress->txmac.ctl.value);
3806 +
3807 + /* Ready to start the RXDMA/TXDMA engine */
3808 + if (!MP_TEST_FLAG(pAdapter, fMP_ADAPTER_LOWER_POWER)) {
3809 + et131x_rx_dma_enable(pAdapter);
3810 + et131x_tx_dma_enable(pAdapter);
3811 + } else {
3812 + DBG_WARNING(et131x_dbginfo,
3813 + "Didn't enable Rx/Tx due to low-power mode\n");
3814 + }
3815 +
3816 + DBG_LEAVE(et131x_dbginfo);
3817 +}
3818 +
3819 +void ConfigRxMacRegs(struct et131x_adapter *pAdapter)
3820 +{
3821 + struct _RXMAC_t __iomem *pRxMac = &pAdapter->CSRAddress->rxmac;
3822 + RXMAC_WOL_SA_LO_t sa_lo;
3823 + RXMAC_WOL_SA_HI_t sa_hi;
3824 + RXMAC_PF_CTRL_t pf_ctrl = { 0 };
3825 +
3826 + DBG_ENTER(et131x_dbginfo);
3827 +
3828 + /* Disable the MAC while it is being configured (also disable WOL) */
3829 + writel(0x8, &pRxMac->ctrl.value);
3830 +
3831 + /* Initialize WOL to disabled. */
3832 + writel(0, &pRxMac->crc0.value);
3833 + writel(0, &pRxMac->crc12.value);
3834 + writel(0, &pRxMac->crc34.value);
3835 +
3836 + /* We need to set the WOL mask0 - mask4 next. We initialize it to
3837 + * its default Values of 0x00000000 because there are not WOL masks
3838 + * as of this time.
3839 + */
3840 + writel(0, &pRxMac->mask0_word0);
3841 + writel(0, &pRxMac->mask0_word1);
3842 + writel(0, &pRxMac->mask0_word2);
3843 + writel(0, &pRxMac->mask0_word3);
3844 +
3845 + writel(0, &pRxMac->mask1_word0);
3846 + writel(0, &pRxMac->mask1_word1);
3847 + writel(0, &pRxMac->mask1_word2);
3848 + writel(0, &pRxMac->mask1_word3);
3849 +
3850 + writel(0, &pRxMac->mask2_word0);
3851 + writel(0, &pRxMac->mask2_word1);
3852 + writel(0, &pRxMac->mask2_word2);
3853 + writel(0, &pRxMac->mask2_word3);
3854 +
3855 + writel(0, &pRxMac->mask3_word0);
3856 + writel(0, &pRxMac->mask3_word1);
3857 + writel(0, &pRxMac->mask3_word2);
3858 + writel(0, &pRxMac->mask3_word3);
3859 +
3860 + writel(0, &pRxMac->mask4_word0);
3861 + writel(0, &pRxMac->mask4_word1);
3862 + writel(0, &pRxMac->mask4_word2);
3863 + writel(0, &pRxMac->mask4_word3);
3864 +
3865 + /* Lets setup the WOL Source Address */
3866 + sa_lo.bits.sa3 = pAdapter->CurrentAddress[2];
3867 + sa_lo.bits.sa4 = pAdapter->CurrentAddress[3];
3868 + sa_lo.bits.sa5 = pAdapter->CurrentAddress[4];
3869 + sa_lo.bits.sa6 = pAdapter->CurrentAddress[5];
3870 + writel(sa_lo.value, &pRxMac->sa_lo.value);
3871 +
3872 + sa_hi.bits.sa1 = pAdapter->CurrentAddress[0];
3873 + sa_hi.bits.sa2 = pAdapter->CurrentAddress[1];
3874 + writel(sa_hi.value, &pRxMac->sa_hi.value);
3875 +
3876 + /* Disable all Packet Filtering */
3877 + writel(0, &pRxMac->pf_ctrl.value);
3878 +
3879 + /* Let's initialize the Unicast Packet filtering address */
3880 + if (pAdapter->PacketFilter & ET131X_PACKET_TYPE_DIRECTED) {
3881 + SetupDeviceForUnicast(pAdapter);
3882 + pf_ctrl.bits.filter_uni_en = 1;
3883 + } else {
3884 + writel(0, &pRxMac->uni_pf_addr1.value);
3885 + writel(0, &pRxMac->uni_pf_addr2.value);
3886 + writel(0, &pRxMac->uni_pf_addr3.value);
3887 + }
3888 +
3889 + /* Let's initialize the Multicast hash */
3890 + if (pAdapter->PacketFilter & ET131X_PACKET_TYPE_ALL_MULTICAST) {
3891 + pf_ctrl.bits.filter_multi_en = 0;
3892 + } else {
3893 + pf_ctrl.bits.filter_multi_en = 1;
3894 + SetupDeviceForMulticast(pAdapter);
3895 + }
3896 +
3897 + /* Runt packet filtering. Didn't work in version A silicon. */
3898 + pf_ctrl.bits.min_pkt_size = NIC_MIN_PACKET_SIZE + 4;
3899 + pf_ctrl.bits.filter_frag_en = 1;
3900 +
3901 + if (pAdapter->RegistryJumboPacket > 8192) {
3902 + RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg;
3903 +
3904 + /* In order to transmit jumbo packets greater than 8k, the
3905 + * FIFO between RxMAC and RxDMA needs to be reduced in size
3906 + * to (16k - Jumbo packet size). In order to implement this,
3907 + * we must use "cut through" mode in the RxMAC, which chops
3908 + * packets down into segments which are (max_size * 16). In
3909 + * this case we selected 256 bytes, since this is the size of
3910 + * the PCI-Express TLP's that the 1310 uses.
3911 + */
3912 + mcif_ctrl_max_seg.bits.seg_en = 0x1;
3913 + mcif_ctrl_max_seg.bits.fc_en = 0x0;
3914 + mcif_ctrl_max_seg.bits.max_size = 0x10;
3915 +
3916 + writel(mcif_ctrl_max_seg.value,
3917 + &pRxMac->mcif_ctrl_max_seg.value);
3918 + } else {
3919 + writel(0, &pRxMac->mcif_ctrl_max_seg.value);
3920 + }
3921 +
3922 + /* Initialize the MCIF water marks */
3923 + writel(0, &pRxMac->mcif_water_mark.value);
3924 +
3925 + /* Initialize the MIF control */
3926 + writel(0, &pRxMac->mif_ctrl.value);
3927 +
3928 + /* Initialize the Space Available Register */
3929 + writel(0, &pRxMac->space_avail.value);
3930 +
3931 + /* Initialize the the mif_ctrl register
3932 + * bit 3: Receive code error. One or more nibbles were signaled as
3933 + * errors during the reception of the packet. Clear this
3934 + * bit in Gigabit, set it in 100Mbit. This was derived
3935 + * experimentally at UNH.
3936 + * bit 4: Receive CRC error. The packet's CRC did not match the
3937 + * internally generated CRC.
3938 + * bit 5: Receive length check error. Indicates that frame length
3939 + * field value in the packet does not match the actual data
3940 + * byte length and is not a type field.
3941 + * bit 16: Receive frame truncated.
3942 + * bit 17: Drop packet enable
3943 + */
3944 + if (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_100MBPS) {
3945 + writel(0x30038, &pRxMac->mif_ctrl.value);
3946 + } else {
3947 + writel(0x30030, &pRxMac->mif_ctrl.value);
3948 + }
3949 +
3950 + /* Finally we initialize RxMac to be enabled & WOL disabled. Packet
3951 + * filter is always enabled since it is where the runt packets are
3952 + * supposed to be dropped. For version A silicon, runt packet
3953 + * dropping doesn't work, so it is disabled in the pf_ctrl register,
3954 + * but we still leave the packet filter on.
3955 + */
3956 + writel(pf_ctrl.value, &pRxMac->pf_ctrl.value);
3957 + writel(0x9, &pRxMac->ctrl.value);
3958 +
3959 + DBG_LEAVE(et131x_dbginfo);
3960 +}
3961 +
3962 +void ConfigTxMacRegs(struct et131x_adapter *pAdapter)
3963 +{
3964 + struct _TXMAC_t __iomem *pTxMac = &pAdapter->CSRAddress->txmac;
3965 + TXMAC_CF_PARAM_t Local;
3966 +
3967 + DBG_ENTER(et131x_dbginfo);
3968 +
3969 + /* We need to update the Control Frame Parameters
3970 + * cfpt - control frame pause timer set to 64 (0x40)
3971 + * cfep - control frame extended pause timer set to 0x0
3972 + */
3973 + if (pAdapter->FlowControl == None) {
3974 + writel(0, &pTxMac->cf_param.value);
3975 + } else {
3976 + Local.bits.cfpt = 0x40;
3977 + Local.bits.cfep = 0x0;
3978 + writel(Local.value, &pTxMac->cf_param.value);
3979 + }
3980 +
3981 + DBG_LEAVE(et131x_dbginfo);
3982 +}
3983 +
3984 +void ConfigMacStatRegs(struct et131x_adapter *pAdapter)
3985 +{
3986 + struct _MAC_STAT_t __iomem *pDevMacStat =
3987 + &pAdapter->CSRAddress->macStat;
3988 +
3989 + DBG_ENTER(et131x_dbginfo);
3990 +
3991 + /* Next we need to initialize all the MAC_STAT registers to zero on
3992 + * the device.
3993 + */
3994 + writel(0, &pDevMacStat->RFcs);
3995 + writel(0, &pDevMacStat->RAln);
3996 + writel(0, &pDevMacStat->RFlr);
3997 + writel(0, &pDevMacStat->RDrp);
3998 + writel(0, &pDevMacStat->RCde);
3999 + writel(0, &pDevMacStat->ROvr);
4000 + writel(0, &pDevMacStat->RFrg);
4001 +
4002 + writel(0, &pDevMacStat->TScl);
4003 + writel(0, &pDevMacStat->TDfr);
4004 + writel(0, &pDevMacStat->TMcl);
4005 + writel(0, &pDevMacStat->TLcl);
4006 + writel(0, &pDevMacStat->TNcl);
4007 + writel(0, &pDevMacStat->TOvr);
4008 + writel(0, &pDevMacStat->TUnd);
4009 +
4010 + /* Unmask any counters that we want to track the overflow of.
4011 + * Initially this will be all counters. It may become clear later
4012 + * that we do not need to track all counters.
4013 + */
4014 + {
4015 + MAC_STAT_REG_1_t Carry1M = { 0xffffffff };
4016 +
4017 + Carry1M.bits.rdrp = 0;
4018 + Carry1M.bits.rjbr = 1;
4019 + Carry1M.bits.rfrg = 0;
4020 + Carry1M.bits.rovr = 0;
4021 + Carry1M.bits.rund = 1;
4022 + Carry1M.bits.rcse = 1;
4023 + Carry1M.bits.rcde = 0;
4024 + Carry1M.bits.rflr = 0;
4025 + Carry1M.bits.raln = 0;
4026 + Carry1M.bits.rxuo = 1;
4027 + Carry1M.bits.rxpf = 1;
4028 + Carry1M.bits.rxcf = 1;
4029 + Carry1M.bits.rbca = 1;
4030 + Carry1M.bits.rmca = 1;
4031 + Carry1M.bits.rfcs = 0;
4032 + Carry1M.bits.rpkt = 1;
4033 + Carry1M.bits.rbyt = 1;
4034 + Carry1M.bits.trmgv = 1;
4035 + Carry1M.bits.trmax = 1;
4036 + Carry1M.bits.tr1k = 1;
4037 + Carry1M.bits.tr511 = 1;
4038 + Carry1M.bits.tr255 = 1;
4039 + Carry1M.bits.tr127 = 1;
4040 + Carry1M.bits.tr64 = 1;
4041 +
4042 + writel(Carry1M.value, &pDevMacStat->Carry1M.value);
4043 + }
4044 +
4045 + {
4046 + MAC_STAT_REG_2_t Carry2M = { 0xffffffff };
4047 +
4048 + Carry2M.bits.tdrp = 1;
4049 + Carry2M.bits.tpfh = 1;
4050 + Carry2M.bits.tncl = 0;
4051 + Carry2M.bits.txcl = 1;
4052 + Carry2M.bits.tlcl = 0;
4053 + Carry2M.bits.tmcl = 0;
4054 + Carry2M.bits.tscl = 0;
4055 + Carry2M.bits.tedf = 1;
4056 + Carry2M.bits.tdfr = 0;
4057 + Carry2M.bits.txpf = 1;
4058 + Carry2M.bits.tbca = 1;
4059 + Carry2M.bits.tmca = 1;
4060 + Carry2M.bits.tpkt = 1;
4061 + Carry2M.bits.tbyt = 1;
4062 + Carry2M.bits.tfrg = 1;
4063 + Carry2M.bits.tund = 0;
4064 + Carry2M.bits.tovr = 0;
4065 + Carry2M.bits.txcf = 1;
4066 + Carry2M.bits.tfcs = 1;
4067 + Carry2M.bits.tjbr = 1;
4068 +
4069 + writel(Carry2M.value, &pDevMacStat->Carry2M.value);
4070 + }
4071 +
4072 + DBG_LEAVE(et131x_dbginfo);
4073 +}
4074 +
4075 +void ConfigFlowControl(struct et131x_adapter * pAdapter)
4076 +{
4077 + if (pAdapter->uiDuplexMode == 0) {
4078 + pAdapter->FlowControl = None;
4079 + } else {
4080 + char RemotePause, RemoteAsyncPause;
4081 +
4082 + ET1310_PhyAccessMiBit(pAdapter,
4083 + TRUEPHY_BIT_READ, 5, 10, &RemotePause);
4084 + ET1310_PhyAccessMiBit(pAdapter,
4085 + TRUEPHY_BIT_READ, 5, 11,
4086 + &RemoteAsyncPause);
4087 +
4088 + if ((RemotePause == TRUEPHY_BIT_SET) &&
4089 + (RemoteAsyncPause == TRUEPHY_BIT_SET)) {
4090 + pAdapter->FlowControl = pAdapter->RegistryFlowControl;
4091 + } else if ((RemotePause == TRUEPHY_BIT_SET) &&
4092 + (RemoteAsyncPause == TRUEPHY_BIT_CLEAR)) {
4093 + if (pAdapter->RegistryFlowControl == Both) {
4094 + pAdapter->FlowControl = Both;
4095 + } else {
4096 + pAdapter->FlowControl = None;
4097 + }
4098 + } else if ((RemotePause == TRUEPHY_BIT_CLEAR) &&
4099 + (RemoteAsyncPause == TRUEPHY_BIT_CLEAR)) {
4100 + pAdapter->FlowControl = None;
4101 + } else {/* if (RemotePause == TRUEPHY_CLEAR_BIT &&
4102 + RemoteAsyncPause == TRUEPHY_SET_BIT) */
4103 + if (pAdapter->RegistryFlowControl == Both) {
4104 + pAdapter->FlowControl = RxOnly;
4105 + } else {
4106 + pAdapter->FlowControl = None;
4107 + }
4108 + }
4109 + }
4110 +}
4111 +
4112 +/**
4113 + * UpdateMacStatHostCounters - Update the local copy of the statistics
4114 + * @pAdapter: pointer to the adapter structure
4115 + */
4116 +void UpdateMacStatHostCounters(struct et131x_adapter *pAdapter)
4117 +{
4118 + struct _ce_stats_t *stats = &pAdapter->Stats;
4119 + struct _MAC_STAT_t __iomem *pDevMacStat =
4120 + &pAdapter->CSRAddress->macStat;
4121 +
4122 + stats->collisions += readl(&pDevMacStat->TNcl);
4123 + stats->first_collision += readl(&pDevMacStat->TScl);
4124 + stats->tx_deferred += readl(&pDevMacStat->TDfr);
4125 + stats->excessive_collisions += readl(&pDevMacStat->TMcl);
4126 + stats->late_collisions += readl(&pDevMacStat->TLcl);
4127 + stats->tx_uflo += readl(&pDevMacStat->TUnd);
4128 + stats->max_pkt_error += readl(&pDevMacStat->TOvr);
4129 +
4130 + stats->alignment_err += readl(&pDevMacStat->RAln);
4131 + stats->crc_err += readl(&pDevMacStat->RCde);
4132 + stats->norcvbuf += readl(&pDevMacStat->RDrp);
4133 + stats->rx_ov_flow += readl(&pDevMacStat->ROvr);
4134 + stats->code_violations += readl(&pDevMacStat->RFcs);
4135 + stats->length_err += readl(&pDevMacStat->RFlr);
4136 +
4137 + stats->other_errors += readl(&pDevMacStat->RFrg);
4138 +}
4139 +
4140 +/**
4141 + * HandleMacStatInterrupt
4142 + * @pAdapter: pointer to the adapter structure
4143 + *
4144 + * One of the MACSTAT counters has wrapped. Update the local copy of
4145 + * the statistics held in the adapter structure, checking the "wrap"
4146 + * bit for each counter.
4147 + */
4148 +void HandleMacStatInterrupt(struct et131x_adapter *pAdapter)
4149 +{
4150 + MAC_STAT_REG_1_t Carry1;
4151 + MAC_STAT_REG_2_t Carry2;
4152 +
4153 + DBG_ENTER(et131x_dbginfo);
4154 +
4155 + /* Read the interrupt bits from the register(s). These are Clear On
4156 + * Write.
4157 + */
4158 + Carry1.value = readl(&pAdapter->CSRAddress->macStat.Carry1.value);
4159 + Carry2.value = readl(&pAdapter->CSRAddress->macStat.Carry2.value);
4160 +
4161 + writel(Carry1.value, &pAdapter->CSRAddress->macStat.Carry1.value);
4162 + writel(Carry2.value, &pAdapter->CSRAddress->macStat.Carry2.value);
4163 +
4164 + /* We need to do update the host copy of all the MAC_STAT counters.
4165 + * For each counter, check it's overflow bit. If the overflow bit is
4166 + * set, then increment the host version of the count by one complete
4167 + * revolution of the counter. This routine is called when the counter
4168 + * block indicates that one of the counters has wrapped.
4169 + */
4170 + if (Carry1.bits.rfcs) {
4171 + pAdapter->Stats.code_violations += COUNTER_WRAP_16_BIT;
4172 + }
4173 + if (Carry1.bits.raln) {
4174 + pAdapter->Stats.alignment_err += COUNTER_WRAP_12_BIT;
4175 + }
4176 + if (Carry1.bits.rflr) {
4177 + pAdapter->Stats.length_err += COUNTER_WRAP_16_BIT;
4178 + }
4179 + if (Carry1.bits.rfrg) {
4180 + pAdapter->Stats.other_errors += COUNTER_WRAP_16_BIT;
4181 + }
4182 + if (Carry1.bits.rcde) {
4183 + pAdapter->Stats.crc_err += COUNTER_WRAP_16_BIT;
4184 + }
4185 + if (Carry1.bits.rovr) {
4186 + pAdapter->Stats.rx_ov_flow += COUNTER_WRAP_16_BIT;
4187 + }
4188 + if (Carry1.bits.rdrp) {
4189 + pAdapter->Stats.norcvbuf += COUNTER_WRAP_16_BIT;
4190 + }
4191 + if (Carry2.bits.tovr) {
4192 + pAdapter->Stats.max_pkt_error += COUNTER_WRAP_12_BIT;
4193 + }
4194 + if (Carry2.bits.tund) {
4195 + pAdapter->Stats.tx_uflo += COUNTER_WRAP_12_BIT;
4196 + }
4197 + if (Carry2.bits.tscl) {
4198 + pAdapter->Stats.first_collision += COUNTER_WRAP_12_BIT;
4199 + }
4200 + if (Carry2.bits.tdfr) {
4201 + pAdapter->Stats.tx_deferred += COUNTER_WRAP_12_BIT;
4202 + }
4203 + if (Carry2.bits.tmcl) {
4204 + pAdapter->Stats.excessive_collisions += COUNTER_WRAP_12_BIT;
4205 + }
4206 + if (Carry2.bits.tlcl) {
4207 + pAdapter->Stats.late_collisions += COUNTER_WRAP_12_BIT;
4208 + }
4209 + if (Carry2.bits.tncl) {
4210 + pAdapter->Stats.collisions += COUNTER_WRAP_12_BIT;
4211 + }
4212 +
4213 + DBG_LEAVE(et131x_dbginfo);
4214 +}
4215 +
4216 +void SetupDeviceForMulticast(struct et131x_adapter *pAdapter)
4217 +{
4218 + struct _RXMAC_t __iomem *rxmac = &pAdapter->CSRAddress->rxmac;
4219 + uint32_t nIndex;
4220 + uint32_t result;
4221 + uint32_t hash1 = 0;
4222 + uint32_t hash2 = 0;
4223 + uint32_t hash3 = 0;
4224 + uint32_t hash4 = 0;
4225 + PM_CSR_t pm_csr;
4226 +
4227 + DBG_ENTER(et131x_dbginfo);
4228 +
4229 + /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
4230 + * the multi-cast LIST. If it is NOT specified, (and "ALL" is not
4231 + * specified) then we should pass NO multi-cast addresses to the
4232 + * driver.
4233 + */
4234 + if (pAdapter->PacketFilter & ET131X_PACKET_TYPE_MULTICAST) {
4235 + DBG_VERBOSE(et131x_dbginfo,
4236 + "MULTICAST flag is set, MCCount: %d\n",
4237 + pAdapter->MCAddressCount);
4238 +
4239 + /* Loop through our multicast array and set up the device */
4240 + for (nIndex = 0; nIndex < pAdapter->MCAddressCount; nIndex++) {
4241 + DBG_VERBOSE(et131x_dbginfo,
4242 + "MCList[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
4243 + nIndex,
4244 + pAdapter->MCList[nIndex][0],
4245 + pAdapter->MCList[nIndex][1],
4246 + pAdapter->MCList[nIndex][2],
4247 + pAdapter->MCList[nIndex][3],
4248 + pAdapter->MCList[nIndex][4],
4249 + pAdapter->MCList[nIndex][5]);
4250 +
4251 + result = ether_crc(6, pAdapter->MCList[nIndex]);
4252 +
4253 + result = (result & 0x3F800000) >> 23;
4254 +
4255 + if (result < 32) {
4256 + hash1 |= (1 << result);
4257 + } else if ((31 < result) && (result < 64)) {
4258 + result -= 32;
4259 + hash2 |= (1 << result);
4260 + } else if ((63 < result) && (result < 96)) {
4261 + result -= 64;
4262 + hash3 |= (1 << result);
4263 + } else {
4264 + result -= 96;
4265 + hash4 |= (1 << result);
4266 + }
4267 + }
4268 + }
4269 +
4270 + /* Write out the new hash to the device */
4271 + pm_csr.value = readl(&pAdapter->CSRAddress->global.pm_csr.value);
4272 + if (pm_csr.bits.pm_phy_sw_coma == 0) {
4273 + writel(hash1, &rxmac->multi_hash1);
4274 + writel(hash2, &rxmac->multi_hash2);
4275 + writel(hash3, &rxmac->multi_hash3);
4276 + writel(hash4, &rxmac->multi_hash4);
4277 + }
4278 +
4279 + DBG_LEAVE(et131x_dbginfo);
4280 +}
4281 +
4282 +void SetupDeviceForUnicast(struct et131x_adapter *pAdapter)
4283 +{
4284 + struct _RXMAC_t __iomem *rxmac = &pAdapter->CSRAddress->rxmac;
4285 + RXMAC_UNI_PF_ADDR1_t uni_pf1;
4286 + RXMAC_UNI_PF_ADDR2_t uni_pf2;
4287 + RXMAC_UNI_PF_ADDR3_t uni_pf3;
4288 + PM_CSR_t pm_csr;
4289 +
4290 + DBG_ENTER(et131x_dbginfo);
4291 +
4292 + /* Set up unicast packet filter reg 3 to be the first two octets of
4293 + * the MAC address for both address
4294 + *
4295 + * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
4296 + * MAC address for second address
4297 + *
4298 + * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
4299 + * MAC address for first address
4300 + */
4301 + uni_pf3.bits.addr1_1 = pAdapter->CurrentAddress[0];
4302 + uni_pf3.bits.addr1_2 = pAdapter->CurrentAddress[1];
4303 + uni_pf3.bits.addr2_1 = pAdapter->CurrentAddress[0];
4304 + uni_pf3.bits.addr2_2 = pAdapter->CurrentAddress[1];
4305 +
4306 + uni_pf2.bits.addr2_3 = pAdapter->CurrentAddress[2];
4307 + uni_pf2.bits.addr2_4 = pAdapter->CurrentAddress[3];
4308 + uni_pf2.bits.addr2_5 = pAdapter->CurrentAddress[4];
4309 + uni_pf2.bits.addr2_6 = pAdapter->CurrentAddress[5];
4310 +
4311 + uni_pf1.bits.addr1_3 = pAdapter->CurrentAddress[2];
4312 + uni_pf1.bits.addr1_4 = pAdapter->CurrentAddress[3];
4313 + uni_pf1.bits.addr1_5 = pAdapter->CurrentAddress[4];
4314 + uni_pf1.bits.addr1_6 = pAdapter->CurrentAddress[5];
4315 +
4316 + pm_csr.value = readl(&pAdapter->CSRAddress->global.pm_csr.value);
4317 + if (pm_csr.bits.pm_phy_sw_coma == 0) {
4318 + writel(uni_pf1.value, &rxmac->uni_pf_addr1.value);
4319 + writel(uni_pf2.value, &rxmac->uni_pf_addr2.value);
4320 + writel(uni_pf3.value, &rxmac->uni_pf_addr3.value);
4321 + }
4322 +
4323 + DBG_LEAVE(et131x_dbginfo);
4324 +}
4325 diff --git a/drivers/staging/et131x/et1310_mac.h b/drivers/staging/et131x/et1310_mac.h
4326 new file mode 100644
4327 index 0000000..bd26cd3
4328 --- /dev/null
4329 +++ b/drivers/staging/et131x/et1310_mac.h
4330 @@ -0,0 +1,93 @@
4331 +/*
4332 + * Agere Systems Inc.
4333 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
4334 + *
4335 + * Copyright © 2005 Agere Systems Inc.
4336 + * All rights reserved.
4337 + * http://www.agere.com
4338 + *
4339 + *------------------------------------------------------------------------------
4340 + *
4341 + * et1310_mac.h - Defines, structs, enums, prototypes, etc. pertaining to the
4342 + * MAC.
4343 + *
4344 + *------------------------------------------------------------------------------
4345 + *
4346 + * SOFTWARE LICENSE
4347 + *
4348 + * This software is provided subject to the following terms and conditions,
4349 + * which you should read carefully before using the software. Using this
4350 + * software indicates your acceptance of these terms and conditions. If you do
4351 + * not agree with these terms and conditions, do not use the software.
4352 + *
4353 + * Copyright © 2005 Agere Systems Inc.
4354 + * All rights reserved.
4355 + *
4356 + * Redistribution and use in source or binary forms, with or without
4357 + * modifications, are permitted provided that the following conditions are met:
4358 + *
4359 + * . Redistributions of source code must retain the above copyright notice, this
4360 + * list of conditions and the following Disclaimer as comments in the code as
4361 + * well as in the documentation and/or other materials provided with the
4362 + * distribution.
4363 + *
4364 + * . Redistributions in binary form must reproduce the above copyright notice,
4365 + * this list of conditions and the following Disclaimer in the documentation
4366 + * and/or other materials provided with the distribution.
4367 + *
4368 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
4369 + * may be used to endorse or promote products derived from this software
4370 + * without specific prior written permission.
4371 + *
4372 + * Disclaimer
4373 + *
4374 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
4375 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
4376 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
4377 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
4378 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
4379 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
4380 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
4381 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
4382 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
4383 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
4384 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
4385 + * DAMAGE.
4386 + *
4387 + */
4388 +
4389 +#ifndef _ET1310_MAC_H_
4390 +#define _ET1310_MAC_H_
4391 +
4392 +
4393 +#include "et1310_address_map.h"
4394 +
4395 +
4396 +#define COUNTER_WRAP_28_BIT 0x10000000
4397 +#define COUNTER_WRAP_22_BIT 0x400000
4398 +#define COUNTER_WRAP_16_BIT 0x10000
4399 +#define COUNTER_WRAP_12_BIT 0x1000
4400 +
4401 +#define COUNTER_MASK_28_BIT (COUNTER_WRAP_28_BIT - 1)
4402 +#define COUNTER_MASK_22_BIT (COUNTER_WRAP_22_BIT - 1)
4403 +#define COUNTER_MASK_16_BIT (COUNTER_WRAP_16_BIT - 1)
4404 +#define COUNTER_MASK_12_BIT (COUNTER_WRAP_12_BIT - 1)
4405 +
4406 +#define UPDATE_COUNTER(HostCnt,DevCnt) \
4407 + HostCnt = HostCnt + DevCnt;
4408 +
4409 +/* Forward declaration of the private adapter structure */
4410 +struct et131x_adapter;
4411 +
4412 +void ConfigMACRegs1(struct et131x_adapter *adapter);
4413 +void ConfigMACRegs2(struct et131x_adapter *adapter);
4414 +void ConfigRxMacRegs(struct et131x_adapter *adapter);
4415 +void ConfigTxMacRegs(struct et131x_adapter *adapter);
4416 +void ConfigMacStatRegs(struct et131x_adapter *adapter);
4417 +void ConfigFlowControl(struct et131x_adapter *adapter);
4418 +void UpdateMacStatHostCounters(struct et131x_adapter *adapter);
4419 +void HandleMacStatInterrupt(struct et131x_adapter *adapter);
4420 +void SetupDeviceForMulticast(struct et131x_adapter *adapter);
4421 +void SetupDeviceForUnicast(struct et131x_adapter *adapter);
4422 +
4423 +#endif /* _ET1310_MAC_H_ */
4424 diff --git a/drivers/staging/et131x/et1310_phy.c b/drivers/staging/et131x/et1310_phy.c
4425 new file mode 100644
4426 index 0000000..6c4fa54
4427 --- /dev/null
4428 +++ b/drivers/staging/et131x/et1310_phy.c
4429 @@ -0,0 +1,1281 @@
4430 +/*
4431 + * Agere Systems Inc.
4432 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
4433 + *
4434 + * Copyright © 2005 Agere Systems Inc.
4435 + * All rights reserved.
4436 + * http://www.agere.com
4437 + *
4438 + *------------------------------------------------------------------------------
4439 + *
4440 + * et1310_phy.c - Routines for configuring and accessing the PHY
4441 + *
4442 + *------------------------------------------------------------------------------
4443 + *
4444 + * SOFTWARE LICENSE
4445 + *
4446 + * This software is provided subject to the following terms and conditions,
4447 + * which you should read carefully before using the software. Using this
4448 + * software indicates your acceptance of these terms and conditions. If you do
4449 + * not agree with these terms and conditions, do not use the software.
4450 + *
4451 + * Copyright © 2005 Agere Systems Inc.
4452 + * All rights reserved.
4453 + *
4454 + * Redistribution and use in source or binary forms, with or without
4455 + * modifications, are permitted provided that the following conditions are met:
4456 + *
4457 + * . Redistributions of source code must retain the above copyright notice, this
4458 + * list of conditions and the following Disclaimer as comments in the code as
4459 + * well as in the documentation and/or other materials provided with the
4460 + * distribution.
4461 + *
4462 + * . Redistributions in binary form must reproduce the above copyright notice,
4463 + * this list of conditions and the following Disclaimer in the documentation
4464 + * and/or other materials provided with the distribution.
4465 + *
4466 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
4467 + * may be used to endorse or promote products derived from this software
4468 + * without specific prior written permission.
4469 + *
4470 + * Disclaimer
4471 + *
4472 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
4473 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
4474 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
4475 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
4476 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
4477 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
4478 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
4479 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
4480 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
4481 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
4482 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
4483 + * DAMAGE.
4484 + *
4485 + */
4486 +
4487 +#include "et131x_version.h"
4488 +#include "et131x_debug.h"
4489 +#include "et131x_defs.h"
4490 +
4491 +#include <linux/pci.h>
4492 +#include <linux/init.h>
4493 +#include <linux/module.h>
4494 +#include <linux/types.h>
4495 +#include <linux/kernel.h>
4496 +
4497 +#include <linux/sched.h>
4498 +#include <linux/ptrace.h>
4499 +#include <linux/slab.h>
4500 +#include <linux/ctype.h>
4501 +#include <linux/string.h>
4502 +#include <linux/timer.h>
4503 +#include <linux/interrupt.h>
4504 +#include <linux/in.h>
4505 +#include <linux/delay.h>
4506 +#include <asm/io.h>
4507 +#include <asm/system.h>
4508 +#include <asm/bitops.h>
4509 +
4510 +#include <linux/netdevice.h>
4511 +#include <linux/etherdevice.h>
4512 +#include <linux/skbuff.h>
4513 +#include <linux/if_arp.h>
4514 +#include <linux/ioport.h>
4515 +#include <linux/random.h>
4516 +#include <linux/delay.h>
4517 +
4518 +#include "et1310_phy.h"
4519 +#include "et1310_pm.h"
4520 +#include "et1310_jagcore.h"
4521 +
4522 +#include "et131x_adapter.h"
4523 +#include "et131x_netdev.h"
4524 +#include "et131x_initpci.h"
4525 +
4526 +#include "et1310_address_map.h"
4527 +#include "et1310_jagcore.h"
4528 +#include "et1310_tx.h"
4529 +#include "et1310_rx.h"
4530 +#include "et1310_mac.h"
4531 +
4532 +/* Data for debugging facilities */
4533 +#ifdef CONFIG_ET131X_DEBUG
4534 +extern dbg_info_t *et131x_dbginfo;
4535 +#endif /* CONFIG_ET131X_DEBUG */
4536 +
4537 +/* Prototypes for functions with local scope */
4538 +static int et131x_xcvr_init(struct et131x_adapter *adapter);
4539 +
4540 +/**
4541 + * PhyMiRead - Read from the PHY through the MII Interface on the MAC
4542 + * @adapter: pointer to our private adapter structure
4543 + * @xcvrAddr: the address of the transciever
4544 + * @xcvrReg: the register to read
4545 + * @value: pointer to a 16-bit value in which the value will be stored
4546 + *
4547 + * Returns 0 on success, errno on failure (as defined in errno.h)
4548 + */
4549 +int PhyMiRead(struct et131x_adapter *adapter, uint8_t xcvrAddr,
4550 + uint8_t xcvrReg, uint16_t *value)
4551 +{
4552 + struct _MAC_t __iomem *mac = &adapter->CSRAddress->mac;
4553 + int status = 0;
4554 + uint32_t delay;
4555 + MII_MGMT_ADDR_t miiAddr;
4556 + MII_MGMT_CMD_t miiCmd;
4557 + MII_MGMT_INDICATOR_t miiIndicator;
4558 +
4559 + /* Save a local copy of the registers we are dealing with so we can
4560 + * set them back
4561 + */
4562 + miiAddr.value = readl(&mac->mii_mgmt_addr.value);
4563 + miiCmd.value = readl(&mac->mii_mgmt_cmd.value);
4564 +
4565 + /* Stop the current operation */
4566 + writel(0, &mac->mii_mgmt_cmd.value);
4567 +
4568 + /* Set up the register we need to read from on the correct PHY */
4569 + {
4570 + MII_MGMT_ADDR_t mii_mgmt_addr = { 0 };
4571 +
4572 + mii_mgmt_addr.bits.phy_addr = xcvrAddr;
4573 + mii_mgmt_addr.bits.reg_addr = xcvrReg;
4574 + writel(mii_mgmt_addr.value, &mac->mii_mgmt_addr.value);
4575 + }
4576 +
4577 + /* Kick the read cycle off */
4578 + delay = 0;
4579 +
4580 + writel(0x1, &mac->mii_mgmt_cmd.value);
4581 +
4582 + do {
4583 + udelay(50);
4584 + delay++;
4585 + miiIndicator.value = readl(&mac->mii_mgmt_indicator.value);
4586 + } while ((miiIndicator.bits.not_valid || miiIndicator.bits.busy) &&
4587 + delay < 50);
4588 +
4589 + /* If we hit the max delay, we could not read the register */
4590 + if (delay >= 50) {
4591 + DBG_WARNING(et131x_dbginfo,
4592 + "xcvrReg 0x%08x could not be read\n", xcvrReg);
4593 + DBG_WARNING(et131x_dbginfo, "status is 0x%08x\n",
4594 + miiIndicator.value);
4595 +
4596 + status = -EIO;
4597 + }
4598 +
4599 + /* If we hit here we were able to read the register and we need to
4600 + * return the value to the caller
4601 + */
4602 + /* TODO: make this stuff a simple readw()?! */
4603 + {
4604 + MII_MGMT_STAT_t mii_mgmt_stat;
4605 +
4606 + mii_mgmt_stat.value = readl(&mac->mii_mgmt_stat.value);
4607 + *value = (uint16_t) mii_mgmt_stat.bits.phy_stat;
4608 + }
4609 +
4610 + /* Stop the read operation */
4611 + writel(0, &mac->mii_mgmt_cmd.value);
4612 +
4613 + DBG_VERBOSE(et131x_dbginfo, " xcvr_addr = 0x%02x, "
4614 + "xcvr_reg = 0x%02x, "
4615 + "value = 0x%04x.\n", xcvrAddr, xcvrReg, *value);
4616 +
4617 + /* set the registers we touched back to the state at which we entered
4618 + * this function
4619 + */
4620 + writel(miiAddr.value, &mac->mii_mgmt_addr.value);
4621 + writel(miiCmd.value, &mac->mii_mgmt_cmd.value);
4622 +
4623 + return status;
4624 +}
4625 +
4626 +/**
4627 + * MiWrite - Write to a PHY register through the MII interface of the MAC
4628 + * @adapter: pointer to our private adapter structure
4629 + * @xcvrReg: the register to read
4630 + * @value: 16-bit value to write
4631 + *
4632 + * Return 0 on success, errno on failure (as defined in errno.h)
4633 + */
4634 +int MiWrite(struct et131x_adapter *adapter, uint8_t xcvrReg, uint16_t value)
4635 +{
4636 + struct _MAC_t __iomem *mac = &adapter->CSRAddress->mac;
4637 + int status = 0;
4638 + uint8_t xcvrAddr = adapter->Stats.xcvr_addr;
4639 + uint32_t delay;
4640 + MII_MGMT_ADDR_t miiAddr;
4641 + MII_MGMT_CMD_t miiCmd;
4642 + MII_MGMT_INDICATOR_t miiIndicator;
4643 +
4644 + /* Save a local copy of the registers we are dealing with so we can
4645 + * set them back
4646 + */
4647 + miiAddr.value = readl(&mac->mii_mgmt_addr.value);
4648 + miiCmd.value = readl(&mac->mii_mgmt_cmd.value);
4649 +
4650 + /* Stop the current operation */
4651 + writel(0, &mac->mii_mgmt_cmd.value);
4652 +
4653 + /* Set up the register we need to write to on the correct PHY */
4654 + {
4655 + MII_MGMT_ADDR_t mii_mgmt_addr;
4656 +
4657 + mii_mgmt_addr.bits.phy_addr = xcvrAddr;
4658 + mii_mgmt_addr.bits.reg_addr = xcvrReg;
4659 + writel(mii_mgmt_addr.value, &mac->mii_mgmt_addr.value);
4660 + }
4661 +
4662 + /* Add the value to write to the registers to the mac */
4663 + writel(value, &mac->mii_mgmt_ctrl.value);
4664 + delay = 0;
4665 +
4666 + do {
4667 + udelay(50);
4668 + delay++;
4669 + miiIndicator.value = readl(&mac->mii_mgmt_indicator.value);
4670 + } while (miiIndicator.bits.busy && delay < 100);
4671 +
4672 + /* If we hit the max delay, we could not write the register */
4673 + if (delay == 100) {
4674 + uint16_t TempValue;
4675 +
4676 + DBG_WARNING(et131x_dbginfo,
4677 + "xcvrReg 0x%08x could not be written", xcvrReg);
4678 + DBG_WARNING(et131x_dbginfo, "status is 0x%08x\n",
4679 + miiIndicator.value);
4680 + DBG_WARNING(et131x_dbginfo, "command is 0x%08x\n",
4681 + readl(&mac->mii_mgmt_cmd.value));
4682 +
4683 + MiRead(adapter, xcvrReg, &TempValue);
4684 +
4685 + status = -EIO;
4686 + }
4687 +
4688 + /* Stop the write operation */
4689 + writel(0, &mac->mii_mgmt_cmd.value);
4690 +
4691 + /* set the registers we touched back to the state at which we entered
4692 + * this function
4693 + */
4694 + writel(miiAddr.value, &mac->mii_mgmt_addr.value);
4695 + writel(miiCmd.value, &mac->mii_mgmt_cmd.value);
4696 +
4697 + DBG_VERBOSE(et131x_dbginfo, " xcvr_addr = 0x%02x, "
4698 + "xcvr_reg = 0x%02x, "
4699 + "value = 0x%04x.\n", xcvrAddr, xcvrReg, value);
4700 +
4701 + return status;
4702 +}
4703 +
4704 +/**
4705 + * et131x_xcvr_find - Find the PHY ID
4706 + * @adapter: pointer to our private adapter structure
4707 + *
4708 + * Returns 0 on success, errno on failure (as defined in errno.h)
4709 + */
4710 +int et131x_xcvr_find(struct et131x_adapter *adapter)
4711 +{
4712 + int status = -ENODEV;
4713 + uint8_t xcvr_addr;
4714 + MI_IDR1_t idr1;
4715 + MI_IDR2_t idr2;
4716 + uint32_t xcvr_id;
4717 +
4718 + DBG_ENTER(et131x_dbginfo);
4719 +
4720 + /* We need to get xcvr id and address we just get the first one */
4721 + for (xcvr_addr = 0; xcvr_addr < 32; xcvr_addr++) {
4722 + /* Read the ID from the PHY */
4723 + PhyMiRead(adapter, xcvr_addr,
4724 + (uint8_t) offsetof(MI_REGS_t, idr1),
4725 + &idr1.value);
4726 + PhyMiRead(adapter, xcvr_addr,
4727 + (uint8_t) offsetof(MI_REGS_t, idr2),
4728 + &idr2.value);
4729 +
4730 + xcvr_id = (uint32_t) ((idr1.value << 16) | idr2.value);
4731 +
4732 + if ((idr1.value != 0) && (idr1.value != 0xffff)) {
4733 + DBG_TRACE(et131x_dbginfo,
4734 + "Xcvr addr: 0x%02x\tXcvr_id: 0x%08x\n",
4735 + xcvr_addr, xcvr_id);
4736 +
4737 + adapter->Stats.xcvr_id = xcvr_id;
4738 + adapter->Stats.xcvr_addr = xcvr_addr;
4739 +
4740 + status = 0;
4741 + break;
4742 + }
4743 + }
4744 +
4745 + DBG_LEAVE(et131x_dbginfo);
4746 + return status;
4747 +}
4748 +
4749 +/**
4750 + * et131x_setphy_normal - Set PHY for normal operation.
4751 + * @adapter: pointer to our private adapter structure
4752 + *
4753 + * Used by Power Management to force the PHY into 10 Base T half-duplex mode,
4754 + * when going to D3 in WOL mode. Also used during initialization to set the
4755 + * PHY for normal operation.
4756 + */
4757 +int et131x_setphy_normal(struct et131x_adapter *adapter)
4758 +{
4759 + int status;
4760 +
4761 + DBG_ENTER(et131x_dbginfo);
4762 +
4763 + /* Make sure the PHY is powered up */
4764 + ET1310_PhyPowerDown(adapter, 0);
4765 + status = et131x_xcvr_init(adapter);
4766 +
4767 + DBG_LEAVE(et131x_dbginfo);
4768 + return status;
4769 +}
4770 +
4771 +/**
4772 + * et131x_xcvr_init - Init the phy if we are setting it into force mode
4773 + * @adapter: pointer to our private adapter structure
4774 + *
4775 + * Returns 0 on success, errno on failure (as defined in errno.h)
4776 + */
4777 +static int et131x_xcvr_init(struct et131x_adapter *adapter)
4778 +{
4779 + int status = 0;
4780 + MI_IMR_t imr;
4781 + MI_ISR_t isr;
4782 + MI_LCR2_t lcr2;
4783 +
4784 + DBG_ENTER(et131x_dbginfo);
4785 +
4786 + /* Zero out the adapter structure variable representing BMSR */
4787 + adapter->Bmsr.value = 0;
4788 +
4789 + MiRead(adapter, (uint8_t) offsetof(MI_REGS_t, isr), &isr.value);
4790 +
4791 + MiRead(adapter, (uint8_t) offsetof(MI_REGS_t, imr), &imr.value);
4792 +
4793 + /* Set the link status interrupt only. Bad behavior when link status
4794 + * and auto neg are set, we run into a nested interrupt problem
4795 + */
4796 + imr.bits.int_en = 0x1;
4797 + imr.bits.link_status = 0x1;
4798 + imr.bits.autoneg_status = 0x1;
4799 +
4800 + MiWrite(adapter, (uint8_t) offsetof(MI_REGS_t, imr), imr.value);
4801 +
4802 + /* Set the LED behavior such that LED 1 indicates speed (off =
4803 + * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
4804 + * link and activity (on for link, blink off for activity).
4805 + *
4806 + * NOTE: Some customizations have been added here for specific
4807 + * vendors; The LED behavior is now determined by vendor data in the
4808 + * EEPROM. However, the above description is the default.
4809 + */
4810 + if ((adapter->eepromData[1] & 0x4) == 0) {
4811 + MiRead(adapter, (uint8_t) offsetof(MI_REGS_t, lcr2),
4812 + &lcr2.value);
4813 + if ((adapter->eepromData[1] & 0x8) == 0)
4814 + lcr2.bits.led_tx_rx = 0x3;
4815 + else
4816 + lcr2.bits.led_tx_rx = 0x4;
4817 + lcr2.bits.led_link = 0xa;
4818 + MiWrite(adapter, (uint8_t) offsetof(MI_REGS_t, lcr2),
4819 + lcr2.value);
4820 + }
4821 +
4822 + /* Determine if we need to go into a force mode and set it */
4823 + if (adapter->AiForceSpeed == 0 && adapter->AiForceDpx == 0) {
4824 + if ((adapter->RegistryFlowControl == TxOnly) ||
4825 + (adapter->RegistryFlowControl == Both)) {
4826 + ET1310_PhyAccessMiBit(adapter,
4827 + TRUEPHY_BIT_SET, 4, 11, NULL);
4828 + } else {
4829 + ET1310_PhyAccessMiBit(adapter,
4830 + TRUEPHY_BIT_CLEAR, 4, 11, NULL);
4831 + }
4832 +
4833 + if (adapter->RegistryFlowControl == Both) {
4834 + ET1310_PhyAccessMiBit(adapter,
4835 + TRUEPHY_BIT_SET, 4, 10, NULL);
4836 + } else {
4837 + ET1310_PhyAccessMiBit(adapter,
4838 + TRUEPHY_BIT_CLEAR, 4, 10, NULL);
4839 + }
4840 +
4841 + /* Set the phy to autonegotiation */
4842 + ET1310_PhyAutoNeg(adapter, true);
4843 +
4844 + /* NOTE - Do we need this? */
4845 + ET1310_PhyAccessMiBit(adapter, TRUEPHY_BIT_SET, 0, 9, NULL);
4846 +
4847 + DBG_LEAVE(et131x_dbginfo);
4848 + return status;
4849 + } else {
4850 + ET1310_PhyAutoNeg(adapter, false);
4851 +
4852 + /* Set to the correct force mode. */
4853 + if (adapter->AiForceDpx != 1) {
4854 + if ((adapter->RegistryFlowControl == TxOnly) ||
4855 + (adapter->RegistryFlowControl == Both)) {
4856 + ET1310_PhyAccessMiBit(adapter,
4857 + TRUEPHY_BIT_SET, 4, 11,
4858 + NULL);
4859 + } else {
4860 + ET1310_PhyAccessMiBit(adapter,
4861 + TRUEPHY_BIT_CLEAR, 4, 11,
4862 + NULL);
4863 + }
4864 +
4865 + if (adapter->RegistryFlowControl == Both) {
4866 + ET1310_PhyAccessMiBit(adapter,
4867 + TRUEPHY_BIT_SET, 4, 10,
4868 + NULL);
4869 + } else {
4870 + ET1310_PhyAccessMiBit(adapter,
4871 + TRUEPHY_BIT_CLEAR, 4, 10,
4872 + NULL);
4873 + }
4874 + } else {
4875 + ET1310_PhyAccessMiBit(adapter,
4876 + TRUEPHY_BIT_CLEAR, 4, 10, NULL);
4877 + ET1310_PhyAccessMiBit(adapter,
4878 + TRUEPHY_BIT_CLEAR, 4, 11, NULL);
4879 + }
4880 +
4881 + switch (adapter->AiForceSpeed) {
4882 + case 10:
4883 + if (adapter->AiForceDpx == 1) {
4884 + TPAL_SetPhy10HalfDuplex(adapter);
4885 + } else if (adapter->AiForceDpx == 2) {
4886 + TPAL_SetPhy10FullDuplex(adapter);
4887 + } else {
4888 + TPAL_SetPhy10Force(adapter);
4889 + }
4890 + break;
4891 + case 100:
4892 + if (adapter->AiForceDpx == 1) {
4893 + TPAL_SetPhy100HalfDuplex(adapter);
4894 + } else if (adapter->AiForceDpx == 2) {
4895 + TPAL_SetPhy100FullDuplex(adapter);
4896 + } else {
4897 + TPAL_SetPhy100Force(adapter);
4898 + }
4899 + break;
4900 + case 1000:
4901 + TPAL_SetPhy1000FullDuplex(adapter);
4902 + break;
4903 + }
4904 +
4905 + DBG_LEAVE(et131x_dbginfo);
4906 + return status;
4907 + }
4908 +}
4909 +
4910 +void et131x_Mii_check(struct et131x_adapter *pAdapter,
4911 + MI_BMSR_t bmsr, MI_BMSR_t bmsr_ints)
4912 +{
4913 + uint8_t ucLinkStatus;
4914 + uint32_t uiAutoNegStatus;
4915 + uint32_t uiSpeed;
4916 + uint32_t uiDuplex;
4917 + uint32_t uiMdiMdix;
4918 + uint32_t uiMasterSlave;
4919 + uint32_t uiPolarity;
4920 + unsigned long lockflags;
4921 +
4922 + DBG_ENTER(et131x_dbginfo);
4923 +
4924 + if (bmsr_ints.bits.link_status) {
4925 + if (bmsr.bits.link_status) {
4926 + pAdapter->PoMgmt.TransPhyComaModeOnBoot = 20;
4927 +
4928 + /* Update our state variables and indicate the
4929 + * connected state
4930 + */
4931 + spin_lock_irqsave(&pAdapter->Lock, lockflags);
4932 +
4933 + pAdapter->MediaState = NETIF_STATUS_MEDIA_CONNECT;
4934 + MP_CLEAR_FLAG(pAdapter, fMP_ADAPTER_LINK_DETECTION);
4935 +
4936 + spin_unlock_irqrestore(&pAdapter->Lock, lockflags);
4937 +
4938 + /* Don't indicate state if we're in loopback mode */
4939 + if (pAdapter->RegistryPhyLoopbk == false) {
4940 + netif_carrier_on(pAdapter->netdev);
4941 + }
4942 + } else {
4943 + DBG_WARNING(et131x_dbginfo,
4944 + "Link down cable problem\n");
4945 +
4946 + if (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_10MBPS) {
4947 + // NOTE - Is there a way to query this without TruePHY?
4948 + // && TRU_QueryCoreType(pAdapter->hTruePhy, 0) == EMI_TRUEPHY_A13O) {
4949 + uint16_t Register18;
4950 +
4951 + MiRead(pAdapter, 0x12, &Register18);
4952 + MiWrite(pAdapter, 0x12, Register18 | 0x4);
4953 + MiWrite(pAdapter, 0x10, Register18 | 0x8402);
4954 + MiWrite(pAdapter, 0x11, Register18 | 511);
4955 + MiWrite(pAdapter, 0x12, Register18);
4956 + }
4957 +
4958 + /* For the first N seconds of life, we are in "link
4959 + * detection" When we are in this state, we should
4960 + * only report "connected". When the LinkDetection
4961 + * Timer expires, we can report disconnected (handled
4962 + * in the LinkDetectionDPC).
4963 + */
4964 + if ((MP_IS_FLAG_CLEAR
4965 + (pAdapter, fMP_ADAPTER_LINK_DETECTION))
4966 + || (pAdapter->MediaState ==
4967 + NETIF_STATUS_MEDIA_DISCONNECT)) {
4968 + spin_lock_irqsave(&pAdapter->Lock, lockflags);
4969 + pAdapter->MediaState =
4970 + NETIF_STATUS_MEDIA_DISCONNECT;
4971 + spin_unlock_irqrestore(&pAdapter->Lock,
4972 + lockflags);
4973 +
4974 + /* Only indicate state if we're in loopback
4975 + * mode
4976 + */
4977 + if (pAdapter->RegistryPhyLoopbk == false) {
4978 + netif_carrier_off(pAdapter->netdev);
4979 + }
4980 + }
4981 +
4982 + pAdapter->uiLinkSpeed = 0;
4983 + pAdapter->uiDuplexMode = 0;
4984 +
4985 + /* Free the packets being actively sent & stopped */
4986 + et131x_free_busy_send_packets(pAdapter);
4987 +
4988 + /* Re-initialize the send structures */
4989 + et131x_init_send(pAdapter);
4990 +
4991 + /* Reset the RFD list and re-start RU */
4992 + et131x_reset_recv(pAdapter);
4993 +
4994 + /*
4995 + * Bring the device back to the state it was during
4996 + * init prior to autonegotiation being complete. This
4997 + * way, when we get the auto-neg complete interrupt,
4998 + * we can complete init by calling ConfigMacREGS2.
4999 + */
5000 + et131x_soft_reset(pAdapter);
5001 +
5002 + /* Setup ET1310 as per the documentation */
5003 + et131x_adapter_setup(pAdapter);
5004 +
5005 + /* Setup the PHY into coma mode until the cable is
5006 + * plugged back in
5007 + */
5008 + if (pAdapter->RegistryPhyComa == 1) {
5009 + EnablePhyComa(pAdapter);
5010 + }
5011 + }
5012 + }
5013 +
5014 + if (bmsr_ints.bits.auto_neg_complete ||
5015 + ((pAdapter->AiForceDpx == 3) && (bmsr_ints.bits.link_status))) {
5016 + if (bmsr.bits.auto_neg_complete || (pAdapter->AiForceDpx == 3)) {
5017 + ET1310_PhyLinkStatus(pAdapter,
5018 + &ucLinkStatus, &uiAutoNegStatus,
5019 + &uiSpeed, &uiDuplex, &uiMdiMdix,
5020 + &uiMasterSlave, &uiPolarity);
5021 +
5022 + pAdapter->uiLinkSpeed = uiSpeed;
5023 + pAdapter->uiDuplexMode = uiDuplex;
5024 +
5025 + DBG_TRACE(et131x_dbginfo,
5026 + "pAdapter->uiLinkSpeed 0x%04x, pAdapter->uiDuplex 0x%08x\n",
5027 + pAdapter->uiLinkSpeed,
5028 + pAdapter->uiDuplexMode);
5029 +
5030 + pAdapter->PoMgmt.TransPhyComaModeOnBoot = 20;
5031 +
5032 + if (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_10MBPS) {
5033 + // NOTE - Is there a way to query this without TruePHY?
5034 + // && TRU_QueryCoreType(pAdapter->hTruePhy, 0) == EMI_TRUEPHY_A13O) {
5035 + uint16_t Register18;
5036 +
5037 + MiRead(pAdapter, 0x12, &Register18);
5038 + MiWrite(pAdapter, 0x12, Register18 | 0x4);
5039 + MiWrite(pAdapter, 0x10, Register18 | 0x8402);
5040 + MiWrite(pAdapter, 0x11, Register18 | 511);
5041 + MiWrite(pAdapter, 0x12, Register18);
5042 + }
5043 +
5044 + ConfigFlowControl(pAdapter);
5045 +
5046 + if ((pAdapter->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) &&
5047 + (pAdapter->RegistryJumboPacket > 2048))
5048 + {
5049 + ET1310_PhyAndOrReg(pAdapter, 0x16, 0xcfff,
5050 + 0x2000);
5051 + }
5052 +
5053 + SetRxDmaTimer(pAdapter);
5054 + ConfigMACRegs2(pAdapter);
5055 + }
5056 + }
5057 +
5058 + DBG_LEAVE(et131x_dbginfo);
5059 +}
5060 +
5061 +/**
5062 + * TPAL_SetPhy10HalfDuplex - Force the phy into 10 Base T Half Duplex mode.
5063 + * @pAdapter: pointer to the adapter structure
5064 + *
5065 + * Also sets the MAC so it is syncd up properly
5066 + */
5067 +void TPAL_SetPhy10HalfDuplex(struct et131x_adapter *pAdapter)
5068 +{
5069 + DBG_ENTER(et131x_dbginfo);
5070 +
5071 + /* Power down PHY */
5072 + ET1310_PhyPowerDown(pAdapter, 1);
5073 +
5074 + /* First we need to turn off all other advertisement */
5075 + ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
5076 +
5077 + ET1310_PhyAdvertise100BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
5078 +
5079 + /* Set our advertise values accordingly */
5080 + ET1310_PhyAdvertise10BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_HALF);
5081 +
5082 + /* Power up PHY */
5083 + ET1310_PhyPowerDown(pAdapter, 0);
5084 +
5085 + DBG_LEAVE(et131x_dbginfo);
5086 +}
5087 +
5088 +/**
5089 + * TPAL_SetPhy10FullDuplex - Force the phy into 10 Base T Full Duplex mode.
5090 + * @pAdapter: pointer to the adapter structure
5091 + *
5092 + * Also sets the MAC so it is syncd up properly
5093 + */
5094 +void TPAL_SetPhy10FullDuplex(struct et131x_adapter *pAdapter)
5095 +{
5096 + DBG_ENTER(et131x_dbginfo);
5097 +
5098 + /* Power down PHY */
5099 + ET1310_PhyPowerDown(pAdapter, 1);
5100 +
5101 + /* First we need to turn off all other advertisement */
5102 + ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
5103 +
5104 + ET1310_PhyAdvertise100BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
5105 +
5106 + /* Set our advertise values accordingly */
5107 + ET1310_PhyAdvertise10BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_FULL);
5108 +
5109 + /* Power up PHY */
5110 + ET1310_PhyPowerDown(pAdapter, 0);
5111 +
5112 + DBG_LEAVE(et131x_dbginfo);
5113 +}
5114 +
5115 +/**
5116 + * TPAL_SetPhy10Force - Force Base-T FD mode WITHOUT using autonegotiation
5117 + * @pAdapter: pointer to the adapter structure
5118 + */
5119 +void TPAL_SetPhy10Force(struct et131x_adapter *pAdapter)
5120 +{
5121 + DBG_ENTER(et131x_dbginfo);
5122 +
5123 + /* Power down PHY */
5124 + ET1310_PhyPowerDown(pAdapter, 1);
5125 +
5126 + /* Disable autoneg */
5127 + ET1310_PhyAutoNeg(pAdapter, false);
5128 +
5129 + /* Disable all advertisement */
5130 + ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
5131 + ET1310_PhyAdvertise10BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
5132 + ET1310_PhyAdvertise100BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
5133 +
5134 + /* Force 10 Mbps */
5135 + ET1310_PhySpeedSelect(pAdapter, TRUEPHY_SPEED_10MBPS);
5136 +
5137 + /* Force Full duplex */
5138 + ET1310_PhyDuplexMode(pAdapter, TRUEPHY_DUPLEX_FULL);
5139 +
5140 + /* Power up PHY */
5141 + ET1310_PhyPowerDown(pAdapter, 0);
5142 +
5143 + DBG_LEAVE(et131x_dbginfo);
5144 +}
5145 +
5146 +/**
5147 + * TPAL_SetPhy100HalfDuplex - Force 100 Base T Half Duplex mode.
5148 + * @pAdapter: pointer to the adapter structure
5149 + *
5150 + * Also sets the MAC so it is syncd up properly.
5151 + */
5152 +void TPAL_SetPhy100HalfDuplex(struct et131x_adapter *pAdapter)
5153 +{
5154 + DBG_ENTER(et131x_dbginfo);
5155 +
5156 + /* Power down PHY */
5157 + ET1310_PhyPowerDown(pAdapter, 1);
5158 +
5159 + /* first we need to turn off all other advertisement */
5160 + ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
5161 +
5162 + ET1310_PhyAdvertise10BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
5163 +
5164 + /* Set our advertise values accordingly */
5165 + ET1310_PhyAdvertise100BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_HALF);
5166 +
5167 + /* Set speed */
5168 + ET1310_PhySpeedSelect(pAdapter, TRUEPHY_SPEED_100MBPS);
5169 +
5170 + /* Power up PHY */
5171 + ET1310_PhyPowerDown(pAdapter, 0);
5172 +
5173 + DBG_LEAVE(et131x_dbginfo);
5174 +}
5175 +
5176 +/**
5177 + * TPAL_SetPhy100FullDuplex - Force 100 Base T Full Duplex mode.
5178 + * @pAdapter: pointer to the adapter structure
5179 + *
5180 + * Also sets the MAC so it is syncd up properly
5181 + */
5182 +void TPAL_SetPhy100FullDuplex(struct et131x_adapter *pAdapter)
5183 +{
5184 + DBG_ENTER(et131x_dbginfo);
5185 +
5186 + /* Power down PHY */
5187 + ET1310_PhyPowerDown(pAdapter, 1);
5188 +
5189 + /* First we need to turn off all other advertisement */
5190 + ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
5191 +
5192 + ET1310_PhyAdvertise10BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
5193 +
5194 + /* Set our advertise values accordingly */
5195 + ET1310_PhyAdvertise100BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_FULL);
5196 +
5197 + /* Power up PHY */
5198 + ET1310_PhyPowerDown(pAdapter, 0);
5199 +
5200 + DBG_LEAVE(et131x_dbginfo);
5201 +}
5202 +
5203 +/**
5204 + * TPAL_SetPhy100Force - Force 100 BaseT FD mode WITHOUT using autonegotiation
5205 + * @pAdapter: pointer to the adapter structure
5206 + */
5207 +void TPAL_SetPhy100Force(struct et131x_adapter *pAdapter)
5208 +{
5209 + DBG_ENTER(et131x_dbginfo);
5210 +
5211 + /* Power down PHY */
5212 + ET1310_PhyPowerDown(pAdapter, 1);
5213 +
5214 + /* Disable autoneg */
5215 + ET1310_PhyAutoNeg(pAdapter, false);
5216 +
5217 + /* Disable all advertisement */
5218 + ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
5219 + ET1310_PhyAdvertise10BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
5220 + ET1310_PhyAdvertise100BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
5221 +
5222 + /* Force 100 Mbps */
5223 + ET1310_PhySpeedSelect(pAdapter, TRUEPHY_SPEED_100MBPS);
5224 +
5225 + /* Force Full duplex */
5226 + ET1310_PhyDuplexMode(pAdapter, TRUEPHY_DUPLEX_FULL);
5227 +
5228 + /* Power up PHY */
5229 + ET1310_PhyPowerDown(pAdapter, 0);
5230 +
5231 + DBG_LEAVE(et131x_dbginfo);
5232 +}
5233 +
5234 +/**
5235 + * TPAL_SetPhy1000FullDuplex - Force 1000 Base T Full Duplex mode
5236 + * @pAdapter: pointer to the adapter structure
5237 + *
5238 + * Also sets the MAC so it is syncd up properly.
5239 + */
5240 +void TPAL_SetPhy1000FullDuplex(struct et131x_adapter *pAdapter)
5241 +{
5242 + DBG_ENTER(et131x_dbginfo);
5243 +
5244 + /* Power down PHY */
5245 + ET1310_PhyPowerDown(pAdapter, 1);
5246 +
5247 + /* first we need to turn off all other advertisement */
5248 + ET1310_PhyAdvertise100BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
5249 +
5250 + ET1310_PhyAdvertise10BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
5251 +
5252 + /* set our advertise values accordingly */
5253 + ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_FULL);
5254 +
5255 + /* power up PHY */
5256 + ET1310_PhyPowerDown(pAdapter, 0);
5257 +
5258 + DBG_LEAVE(et131x_dbginfo);
5259 +}
5260 +
5261 +/**
5262 + * TPAL_SetPhyAutoNeg - Set phy to autonegotiation mode.
5263 + * @pAdapter: pointer to the adapter structure
5264 + */
5265 +void TPAL_SetPhyAutoNeg(struct et131x_adapter *pAdapter)
5266 +{
5267 + DBG_ENTER(et131x_dbginfo);
5268 +
5269 + /* Power down PHY */
5270 + ET1310_PhyPowerDown(pAdapter, 1);
5271 +
5272 + /* Turn on advertisement of all capabilities */
5273 + ET1310_PhyAdvertise10BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_BOTH);
5274 +
5275 + ET1310_PhyAdvertise100BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_BOTH);
5276 +
5277 + if (pAdapter->DeviceID != ET131X_PCI_DEVICE_ID_FAST) {
5278 + ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_FULL);
5279 + } else {
5280 + ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
5281 + }
5282 +
5283 + /* Make sure auto-neg is ON (it is disabled in FORCE modes) */
5284 + ET1310_PhyAutoNeg(pAdapter, true);
5285 +
5286 + /* Power up PHY */
5287 + ET1310_PhyPowerDown(pAdapter, 0);
5288 +
5289 + DBG_LEAVE(et131x_dbginfo);
5290 +}
5291 +
5292 +
5293 +/*
5294 + * The routines which follow provide low-level access to the PHY, and are used
5295 + * primarily by the routines above (although there are a few places elsewhere
5296 + * in the driver where this level of access is required).
5297 + */
5298 +
5299 +static const uint16_t ConfigPhy[25][2] = {
5300 + /* Reg Value Register */
5301 + /* Addr */
5302 + {0x880B, 0x0926}, /* AfeIfCreg4B1000Msbs */
5303 + {0x880C, 0x0926}, /* AfeIfCreg4B100Msbs */
5304 + {0x880D, 0x0926}, /* AfeIfCreg4B10Msbs */
5305 +
5306 + {0x880E, 0xB4D3}, /* AfeIfCreg4B1000Lsbs */
5307 + {0x880F, 0xB4D3}, /* AfeIfCreg4B100Lsbs */
5308 + {0x8810, 0xB4D3}, /* AfeIfCreg4B10Lsbs */
5309 +
5310 + {0x8805, 0xB03E}, /* AfeIfCreg3B1000Msbs */
5311 + {0x8806, 0xB03E}, /* AfeIfCreg3B100Msbs */
5312 + {0x8807, 0xFF00}, /* AfeIfCreg3B10Msbs */
5313 +
5314 + {0x8808, 0xE090}, /* AfeIfCreg3B1000Lsbs */
5315 + {0x8809, 0xE110}, /* AfeIfCreg3B100Lsbs */
5316 + {0x880A, 0x0000}, /* AfeIfCreg3B10Lsbs */
5317 +
5318 + {0x300D, 1}, /* DisableNorm */
5319 +
5320 + {0x280C, 0x0180}, /* LinkHoldEnd */
5321 +
5322 + {0x1C21, 0x0002}, /* AlphaM */
5323 +
5324 + {0x3821, 6}, /* FfeLkgTx0 */
5325 + {0x381D, 1}, /* FfeLkg1g4 */
5326 + {0x381E, 1}, /* FfeLkg1g5 */
5327 + {0x381F, 1}, /* FfeLkg1g6 */
5328 + {0x3820, 1}, /* FfeLkg1g7 */
5329 +
5330 + {0x8402, 0x01F0}, /* Btinact */
5331 + {0x800E, 20}, /* LftrainTime */
5332 + {0x800F, 24}, /* DvguardTime */
5333 + {0x8010, 46}, /* IdlguardTime */
5334 +
5335 + {0, 0}
5336 +
5337 +};
5338 +
5339 +/* condensed version of the phy initialization routine */
5340 +void ET1310_PhyInit(struct et131x_adapter *pAdapter)
5341 +{
5342 + uint16_t usData, usIndex;
5343 +
5344 + if (pAdapter == NULL) {
5345 + return;
5346 + }
5347 +
5348 + // get the identity (again ?)
5349 + MiRead(pAdapter, PHY_ID_1, &usData);
5350 + MiRead(pAdapter, PHY_ID_2, &usData);
5351 +
5352 + // what does this do/achieve ?
5353 + MiRead(pAdapter, PHY_MPHY_CONTROL_REG, &usData); // should read 0002
5354 + MiWrite(pAdapter, PHY_MPHY_CONTROL_REG, 0x0006);
5355 +
5356 + // read modem register 0402, should I do something with the return data ?
5357 + MiWrite(pAdapter, PHY_INDEX_REG, 0x0402);
5358 + MiRead(pAdapter, PHY_DATA_REG, &usData);
5359 +
5360 + // what does this do/achieve ?
5361 + MiWrite(pAdapter, PHY_MPHY_CONTROL_REG, 0x0002);
5362 +
5363 + // get the identity (again ?)
5364 + MiRead(pAdapter, PHY_ID_1, &usData);
5365 + MiRead(pAdapter, PHY_ID_2, &usData);
5366 +
5367 + // what does this achieve ?
5368 + MiRead(pAdapter, PHY_MPHY_CONTROL_REG, &usData); // should read 0002
5369 + MiWrite(pAdapter, PHY_MPHY_CONTROL_REG, 0x0006);
5370 +
5371 + // read modem register 0402, should I do something with the return data?
5372 + MiWrite(pAdapter, PHY_INDEX_REG, 0x0402);
5373 + MiRead(pAdapter, PHY_DATA_REG, &usData);
5374 +
5375 + MiWrite(pAdapter, PHY_MPHY_CONTROL_REG, 0x0002);
5376 +
5377 + // what does this achieve (should return 0x1040)
5378 + MiRead(pAdapter, PHY_CONTROL, &usData);
5379 + MiRead(pAdapter, PHY_MPHY_CONTROL_REG, &usData); // should read 0002
5380 + MiWrite(pAdapter, PHY_CONTROL, 0x1840);
5381 +
5382 + MiWrite(pAdapter, PHY_MPHY_CONTROL_REG, 0x0007);
5383 +
5384 + // here the writing of the array starts....
5385 + usIndex = 0;
5386 + while (ConfigPhy[usIndex][0] != 0x0000) {
5387 + // write value
5388 + MiWrite(pAdapter, PHY_INDEX_REG, ConfigPhy[usIndex][0]);
5389 + MiWrite(pAdapter, PHY_DATA_REG, ConfigPhy[usIndex][1]);
5390 +
5391 + // read it back
5392 + MiWrite(pAdapter, PHY_INDEX_REG, ConfigPhy[usIndex][0]);
5393 + MiRead(pAdapter, PHY_DATA_REG, &usData);
5394 +
5395 + // do a check on the value read back ?
5396 + usIndex++;
5397 + }
5398 + // here the writing of the array ends...
5399 +
5400 + MiRead(pAdapter, PHY_CONTROL, &usData); // 0x1840
5401 + MiRead(pAdapter, PHY_MPHY_CONTROL_REG, &usData); // should read 0007
5402 + MiWrite(pAdapter, PHY_CONTROL, 0x1040);
5403 + MiWrite(pAdapter, PHY_MPHY_CONTROL_REG, 0x0002);
5404 +}
5405 +
5406 +void ET1310_PhyReset(struct et131x_adapter *pAdapter)
5407 +{
5408 + MiWrite(pAdapter, PHY_CONTROL, 0x8000);
5409 +}
5410 +
5411 +void ET1310_PhyPowerDown(struct et131x_adapter *pAdapter, bool down)
5412 +{
5413 + uint16_t usData;
5414 +
5415 + MiRead(pAdapter, PHY_CONTROL, &usData);
5416 +
5417 + if (down == false) {
5418 + // Power UP
5419 + usData &= ~0x0800;
5420 + MiWrite(pAdapter, PHY_CONTROL, usData);
5421 + } else {
5422 + // Power DOWN
5423 + usData |= 0x0800;
5424 + MiWrite(pAdapter, PHY_CONTROL, usData);
5425 + }
5426 +}
5427 +
5428 +void ET1310_PhyAutoNeg(struct et131x_adapter *pAdapter, bool enable)
5429 +{
5430 + uint16_t usData;
5431 +
5432 + MiRead(pAdapter, PHY_CONTROL, &usData);
5433 +
5434 + if (enable == true) {
5435 + // Autonegotiation ON
5436 + usData |= 0x1000;
5437 + MiWrite(pAdapter, PHY_CONTROL, usData);
5438 + } else {
5439 + // Autonegotiation OFF
5440 + usData &= ~0x1000;
5441 + MiWrite(pAdapter, PHY_CONTROL, usData);
5442 + }
5443 +}
5444 +
5445 +void ET1310_PhyDuplexMode(struct et131x_adapter *pAdapter, uint16_t duplex)
5446 +{
5447 + uint16_t usData;
5448 +
5449 + MiRead(pAdapter, PHY_CONTROL, &usData);
5450 +
5451 + if (duplex == TRUEPHY_DUPLEX_FULL) {
5452 + // Set Full Duplex
5453 + usData |= 0x100;
5454 + MiWrite(pAdapter, PHY_CONTROL, usData);
5455 + } else {
5456 + // Set Half Duplex
5457 + usData &= ~0x100;
5458 + MiWrite(pAdapter, PHY_CONTROL, usData);
5459 + }
5460 +}
5461 +
5462 +void ET1310_PhySpeedSelect(struct et131x_adapter *pAdapter, uint16_t speed)
5463 +{
5464 + uint16_t usData;
5465 +
5466 + // Read the PHY control register
5467 + MiRead(pAdapter, PHY_CONTROL, &usData);
5468 +
5469 + // Clear all Speed settings (Bits 6, 13)
5470 + usData &= ~0x2040;
5471 +
5472 + // Reset the speed bits based on user selection
5473 + switch (speed) {
5474 + case TRUEPHY_SPEED_10MBPS:
5475 + // Bits already cleared above, do nothing
5476 + break;
5477 +
5478 + case TRUEPHY_SPEED_100MBPS:
5479 + // 100M == Set bit 13
5480 + usData |= 0x2000;
5481 + break;
5482 +
5483 + case TRUEPHY_SPEED_1000MBPS:
5484 + default:
5485 + usData |= 0x0040;
5486 + break;
5487 + }
5488 +
5489 + // Write back the new speed
5490 + MiWrite(pAdapter, PHY_CONTROL, usData);
5491 +}
5492 +
5493 +void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *pAdapter,
5494 + uint16_t duplex)
5495 +{
5496 + uint16_t usData;
5497 +
5498 + // Read the PHY 1000 Base-T Control Register
5499 + MiRead(pAdapter, PHY_1000_CONTROL, &usData);
5500 +
5501 + // Clear Bits 8,9
5502 + usData &= ~0x0300;
5503 +
5504 + switch (duplex) {
5505 + case TRUEPHY_ADV_DUPLEX_NONE:
5506 + // Duplex already cleared, do nothing
5507 + break;
5508 +
5509 + case TRUEPHY_ADV_DUPLEX_FULL:
5510 + // Set Bit 9
5511 + usData |= 0x0200;
5512 + break;
5513 +
5514 + case TRUEPHY_ADV_DUPLEX_HALF:
5515 + // Set Bit 8
5516 + usData |= 0x0100;
5517 + break;
5518 +
5519 + case TRUEPHY_ADV_DUPLEX_BOTH:
5520 + default:
5521 + usData |= 0x0300;
5522 + break;
5523 + }
5524 +
5525 + // Write back advertisement
5526 + MiWrite(pAdapter, PHY_1000_CONTROL, usData);
5527 +}
5528 +
5529 +void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *pAdapter,
5530 + uint16_t duplex)
5531 +{
5532 + uint16_t usData;
5533 +
5534 + // Read the Autonegotiation Register (10/100)
5535 + MiRead(pAdapter, PHY_AUTO_ADVERTISEMENT, &usData);
5536 +
5537 + // Clear bits 7,8
5538 + usData &= ~0x0180;
5539 +
5540 + switch (duplex) {
5541 + case TRUEPHY_ADV_DUPLEX_NONE:
5542 + // Duplex already cleared, do nothing
5543 + break;
5544 +
5545 + case TRUEPHY_ADV_DUPLEX_FULL:
5546 + // Set Bit 8
5547 + usData |= 0x0100;
5548 + break;
5549 +
5550 + case TRUEPHY_ADV_DUPLEX_HALF:
5551 + // Set Bit 7
5552 + usData |= 0x0080;
5553 + break;
5554 +
5555 + case TRUEPHY_ADV_DUPLEX_BOTH:
5556 + default:
5557 + // Set Bits 7,8
5558 + usData |= 0x0180;
5559 + break;
5560 + }
5561 +
5562 + // Write back advertisement
5563 + MiWrite(pAdapter, PHY_AUTO_ADVERTISEMENT, usData);
5564 +}
5565 +
5566 +void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *pAdapter,
5567 + uint16_t duplex)
5568 +{
5569 + uint16_t usData;
5570 +
5571 + // Read the Autonegotiation Register (10/100)
5572 + MiRead(pAdapter, PHY_AUTO_ADVERTISEMENT, &usData);
5573 +
5574 + // Clear bits 5,6
5575 + usData &= ~0x0060;
5576 +
5577 + switch (duplex) {
5578 + case TRUEPHY_ADV_DUPLEX_NONE:
5579 + // Duplex already cleared, do nothing
5580 + break;
5581 +
5582 + case TRUEPHY_ADV_DUPLEX_FULL:
5583 + // Set Bit 6
5584 + usData |= 0x0040;
5585 + break;
5586 +
5587 + case TRUEPHY_ADV_DUPLEX_HALF:
5588 + // Set Bit 5
5589 + usData |= 0x0020;
5590 + break;
5591 +
5592 + case TRUEPHY_ADV_DUPLEX_BOTH:
5593 + default:
5594 + // Set Bits 5,6
5595 + usData |= 0x0060;
5596 + break;
5597 + }
5598 +
5599 + // Write back advertisement
5600 + MiWrite(pAdapter, PHY_AUTO_ADVERTISEMENT, usData);
5601 +}
5602 +
5603 +void ET1310_PhyLinkStatus(struct et131x_adapter *pAdapter,
5604 + uint8_t *ucLinkStatus,
5605 + uint32_t *uiAutoNeg,
5606 + uint32_t *uiLinkSpeed,
5607 + uint32_t *uiDuplexMode,
5608 + uint32_t *uiMdiMdix,
5609 + uint32_t *uiMasterSlave, uint32_t *uiPolarity)
5610 +{
5611 + uint16_t usMiStatus = 0;
5612 + uint16_t us1000BaseT = 0;
5613 + uint16_t usVmiPhyStatus = 0;
5614 + uint16_t usControl = 0;
5615 +
5616 + MiRead(pAdapter, PHY_STATUS, &usMiStatus);
5617 + MiRead(pAdapter, PHY_1000_STATUS, &us1000BaseT);
5618 + MiRead(pAdapter, PHY_PHY_STATUS, &usVmiPhyStatus);
5619 + MiRead(pAdapter, PHY_CONTROL, &usControl);
5620 +
5621 + if (ucLinkStatus) {
5622 + *ucLinkStatus =
5623 + (unsigned char)((usVmiPhyStatus & 0x0040) ? 1 : 0);
5624 + }
5625 +
5626 + if (uiAutoNeg) {
5627 + *uiAutoNeg =
5628 + (usControl & 0x1000) ? ((usVmiPhyStatus & 0x0020) ?
5629 + TRUEPHY_ANEG_COMPLETE :
5630 + TRUEPHY_ANEG_NOT_COMPLETE) :
5631 + TRUEPHY_ANEG_DISABLED;
5632 + }
5633 +
5634 + if (uiLinkSpeed) {
5635 + *uiLinkSpeed = (usVmiPhyStatus & 0x0300) >> 8;
5636 + }
5637 +
5638 + if (uiDuplexMode) {
5639 + *uiDuplexMode = (usVmiPhyStatus & 0x0080) >> 7;
5640 + }
5641 +
5642 + if (uiMdiMdix) {
5643 + /* NOTE: Need to complete this */
5644 + *uiMdiMdix = 0;
5645 + }
5646 +
5647 + if (uiMasterSlave) {
5648 + *uiMasterSlave =
5649 + (us1000BaseT & 0x4000) ? TRUEPHY_CFG_MASTER :
5650 + TRUEPHY_CFG_SLAVE;
5651 + }
5652 +
5653 + if (uiPolarity) {
5654 + *uiPolarity =
5655 + (usVmiPhyStatus & 0x0400) ? TRUEPHY_POLARITY_INVERTED :
5656 + TRUEPHY_POLARITY_NORMAL;
5657 + }
5658 +}
5659 +
5660 +void ET1310_PhyAndOrReg(struct et131x_adapter *pAdapter,
5661 + uint16_t regnum, uint16_t andMask, uint16_t orMask)
5662 +{
5663 + uint16_t reg;
5664 +
5665 + // Read the requested register
5666 + MiRead(pAdapter, regnum, &reg);
5667 +
5668 + // Apply the AND mask
5669 + reg &= andMask;
5670 +
5671 + // Apply the OR mask
5672 + reg |= orMask;
5673 +
5674 + // Write the value back to the register
5675 + MiWrite(pAdapter, regnum, reg);
5676 +}
5677 +
5678 +void ET1310_PhyAccessMiBit(struct et131x_adapter *pAdapter, uint16_t action,
5679 + uint16_t regnum, uint16_t bitnum, uint8_t *value)
5680 +{
5681 + uint16_t reg;
5682 + uint16_t mask = 0;
5683 +
5684 + // Create a mask to isolate the requested bit
5685 + mask = 0x0001 << bitnum;
5686 +
5687 + // Read the requested register
5688 + MiRead(pAdapter, regnum, &reg);
5689 +
5690 + switch (action) {
5691 + case TRUEPHY_BIT_READ:
5692 + if (value != NULL) {
5693 + *value = (reg & mask) >> bitnum;
5694 + }
5695 + break;
5696 +
5697 + case TRUEPHY_BIT_SET:
5698 + reg |= mask;
5699 + MiWrite(pAdapter, regnum, reg);
5700 + break;
5701 +
5702 + case TRUEPHY_BIT_CLEAR:
5703 + reg &= ~mask;
5704 + MiWrite(pAdapter, regnum, reg);
5705 + break;
5706 +
5707 + default:
5708 + break;
5709 + }
5710 +}
5711 diff --git a/drivers/staging/et131x/et1310_phy.h b/drivers/staging/et131x/et1310_phy.h
5712 new file mode 100644
5713 index 0000000..d624cbb
5714 --- /dev/null
5715 +++ b/drivers/staging/et131x/et1310_phy.h
5716 @@ -0,0 +1,910 @@
5717 +/*
5718 + * Agere Systems Inc.
5719 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5720 + *
5721 + * Copyright © 2005 Agere Systems Inc.
5722 + * All rights reserved.
5723 + * http://www.agere.com
5724 + *
5725 + *------------------------------------------------------------------------------
5726 + *
5727 + * et1310_phy.h - Defines, structs, enums, prototypes, etc. pertaining to the
5728 + * PHY.
5729 + *
5730 + *------------------------------------------------------------------------------
5731 + *
5732 + * SOFTWARE LICENSE
5733 + *
5734 + * This software is provided subject to the following terms and conditions,
5735 + * which you should read carefully before using the software. Using this
5736 + * software indicates your acceptance of these terms and conditions. If you do
5737 + * not agree with these terms and conditions, do not use the software.
5738 + *
5739 + * Copyright © 2005 Agere Systems Inc.
5740 + * All rights reserved.
5741 + *
5742 + * Redistribution and use in source or binary forms, with or without
5743 + * modifications, are permitted provided that the following conditions are met:
5744 + *
5745 + * . Redistributions of source code must retain the above copyright notice, this
5746 + * list of conditions and the following Disclaimer as comments in the code as
5747 + * well as in the documentation and/or other materials provided with the
5748 + * distribution.
5749 + *
5750 + * . Redistributions in binary form must reproduce the above copyright notice,
5751 + * this list of conditions and the following Disclaimer in the documentation
5752 + * and/or other materials provided with the distribution.
5753 + *
5754 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
5755 + * may be used to endorse or promote products derived from this software
5756 + * without specific prior written permission.
5757 + *
5758 + * Disclaimer
5759 + *
5760 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
5761 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
5762 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
5763 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
5764 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
5765 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
5766 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
5767 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
5768 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
5769 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
5770 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
5771 + * DAMAGE.
5772 + *
5773 + */
5774 +
5775 +#ifndef _ET1310_PHY_H_
5776 +#define _ET1310_PHY_H_
5777 +
5778 +#include "et1310_address_map.h"
5779 +
5780 +#define TRUEPHY_SUCCESS 0
5781 +#define TRUEPHY_FAILURE 1
5782 +typedef void *TRUEPHY_HANDLE;
5783 +typedef void *TRUEPHY_PLATFORM_HANDLE;
5784 +typedef void *TRUEPHY_OSAL_HANDLE;
5785 +
5786 +/* MI Register Addresses */
5787 +#define MI_CONTROL_REG 0
5788 +#define MI_STATUS_REG 1
5789 +#define MI_PHY_IDENTIFIER_1_REG 2
5790 +#define MI_PHY_IDENTIFIER_2_REG 3
5791 +#define MI_AUTONEG_ADVERTISEMENT_REG 4
5792 +#define MI_AUTONEG_LINK_PARTNER_ABILITY_REG 5
5793 +#define MI_AUTONEG_EXPANSION_REG 6
5794 +#define MI_AUTONEG_NEXT_PAGE_TRANSMIT_REG 7
5795 +#define MI_LINK_PARTNER_NEXT_PAGE_REG 8
5796 +#define MI_1000BASET_CONTROL_REG 9
5797 +#define MI_1000BASET_STATUS_REG 10
5798 +#define MI_RESERVED11_REG 11
5799 +#define MI_RESERVED12_REG 12
5800 +#define MI_RESERVED13_REG 13
5801 +#define MI_RESERVED14_REG 14
5802 +#define MI_EXTENDED_STATUS_REG 15
5803 +
5804 +/* VMI Register Addresses */
5805 +#define VMI_RESERVED16_REG 16
5806 +#define VMI_RESERVED17_REG 17
5807 +#define VMI_RESERVED18_REG 18
5808 +#define VMI_LOOPBACK_CONTROL_REG 19
5809 +#define VMI_RESERVED20_REG 20
5810 +#define VMI_MI_CONTROL_REG 21
5811 +#define VMI_PHY_CONFIGURATION_REG 22
5812 +#define VMI_PHY_CONTROL_REG 23
5813 +#define VMI_INTERRUPT_MASK_REG 24
5814 +#define VMI_INTERRUPT_STATUS_REG 25
5815 +#define VMI_PHY_STATUS_REG 26
5816 +#define VMI_LED_CONTROL_1_REG 27
5817 +#define VMI_LED_CONTROL_2_REG 28
5818 +#define VMI_RESERVED29_REG 29
5819 +#define VMI_RESERVED30_REG 30
5820 +#define VMI_RESERVED31_REG 31
5821 +
5822 +/* PHY Register Mapping(MI) Management Interface Regs */
5823 +typedef struct _MI_REGS_t {
5824 + u8 bmcr; // Basic mode control reg(Reg 0x00)
5825 + u8 bmsr; // Basic mode status reg(Reg 0x01)
5826 + u8 idr1; // Phy identifier reg 1(Reg 0x02)
5827 + u8 idr2; // Phy identifier reg 2(Reg 0x03)
5828 + u8 anar; // Auto-Negotiation advertisement(Reg 0x04)
5829 + u8 anlpar; // Auto-Negotiation link Partner Ability(Reg 0x05)
5830 + u8 aner; // Auto-Negotiation expansion reg(Reg 0x06)
5831 + u8 annptr; // Auto-Negotiation next page transmit reg(Reg 0x07)
5832 + u8 lpnpr; // link partner next page reg(Reg 0x08)
5833 + u8 gcr; // Gigabit basic mode control reg(Reg 0x09)
5834 + u8 gsr; // Gigabit basic mode status reg(Reg 0x0A)
5835 + u8 mi_res1[4]; // Future use by MI working group(Reg 0x0B - 0x0E)
5836 + u8 esr; // Extended status reg(Reg 0x0F)
5837 + u8 mi_res2[3]; // Future use by MI working group(Reg 0x10 - 0x12)
5838 + u8 loop_ctl; // Loopback Control Reg(Reg 0x13)
5839 + u8 mi_res3; // Future use by MI working group(Reg 0x14)
5840 + u8 mcr; // MI Control Reg(Reg 0x15)
5841 + u8 pcr; // Configuration Reg(Reg 0x16)
5842 + u8 phy_ctl; // PHY Control Reg(Reg 0x17)
5843 + u8 imr; // Interrupt Mask Reg(Reg 0x18)
5844 + u8 isr; // Interrupt Status Reg(Reg 0x19)
5845 + u8 psr; // PHY Status Reg(Reg 0x1A)
5846 + u8 lcr1; // LED Control 1 Reg(Reg 0x1B)
5847 + u8 lcr2; // LED Control 2 Reg(Reg 0x1C)
5848 + u8 mi_res4[3]; // Future use by MI working group(Reg 0x1D - 0x1F)
5849 +} MI_REGS_t, *PMI_REGS_t;
5850 +
5851 +/* MI Register 0: Basic mode control register */
5852 +typedef union _MI_BMCR_t {
5853 + u16 value;
5854 + struct {
5855 +#ifdef _BIT_FIELDS_HTOL
5856 + u16 reset:1; // bit 15
5857 + u16 loopback:1; // bit 14
5858 + u16 speed_sel:1; // bit 13
5859 + u16 enable_autoneg:1; // bit 12
5860 + u16 power_down:1; // bit 11
5861 + u16 isolate:1; // bit 10
5862 + u16 restart_autoneg:1; // bit 9
5863 + u16 duplex_mode:1; // bit 8
5864 + u16 col_test:1; // bit 7
5865 + u16 speed_1000_sel:1; // bit 6
5866 + u16 res1:6; // bits 0-5
5867 +#else
5868 + u16 res1:6; // bits 0-5
5869 + u16 speed_1000_sel:1; // bit 6
5870 + u16 col_test:1; // bit 7
5871 + u16 duplex_mode:1; // bit 8
5872 + u16 restart_autoneg:1; // bit 9
5873 + u16 isolate:1; // bit 10
5874 + u16 power_down:1; // bit 11
5875 + u16 enable_autoneg:1; // bit 12
5876 + u16 speed_sel:1; // bit 13
5877 + u16 loopback:1; // bit 14
5878 + u16 reset:1; // bit 15
5879 +#endif
5880 + } bits;
5881 +} MI_BMCR_t, *PMI_BMCR_t;
5882 +
5883 +/* MI Register 1: Basic mode status register */
5884 +typedef union _MI_BMSR_t {
5885 + u16 value;
5886 + struct {
5887 +#ifdef _BIT_FIELDS_HTOL
5888 + u16 link_100T4:1; // bit 15
5889 + u16 link_100fdx:1; // bit 14
5890 + u16 link_100hdx:1; // bit 13
5891 + u16 link_10fdx:1; // bit 12
5892 + u16 link_10hdx:1; // bit 11
5893 + u16 link_100T2fdx:1; // bit 10
5894 + u16 link_100T2hdx:1; // bit 9
5895 + u16 extend_status:1; // bit 8
5896 + u16 res1:1; // bit 7
5897 + u16 preamble_supress:1; // bit 6
5898 + u16 auto_neg_complete:1; // bit 5
5899 + u16 remote_fault:1; // bit 4
5900 + u16 auto_neg_able:1; // bit 3
5901 + u16 link_status:1; // bit 2
5902 + u16 jabber_detect:1; // bit 1
5903 + u16 ext_cap:1; // bit 0
5904 +#else
5905 + u16 ext_cap:1; // bit 0
5906 + u16 jabber_detect:1; // bit 1
5907 + u16 link_status:1; // bit 2
5908 + u16 auto_neg_able:1; // bit 3
5909 + u16 remote_fault:1; // bit 4
5910 + u16 auto_neg_complete:1; // bit 5
5911 + u16 preamble_supress:1; // bit 6
5912 + u16 res1:1; // bit 7
5913 + u16 extend_status:1; // bit 8
5914 + u16 link_100T2hdx:1; // bit 9
5915 + u16 link_100T2fdx:1; // bit 10
5916 + u16 link_10hdx:1; // bit 11
5917 + u16 link_10fdx:1; // bit 12
5918 + u16 link_100hdx:1; // bit 13
5919 + u16 link_100fdx:1; // bit 14
5920 + u16 link_100T4:1; // bit 15
5921 +#endif
5922 + } bits;
5923 +} MI_BMSR_t, *PMI_BMSR_t;
5924 +
5925 +/* MI Register 2: Physical Identifier 1 */
5926 +typedef union _MI_IDR1_t {
5927 + u16 value;
5928 + struct {
5929 + u16 ieee_address:16; // 0x0282 default(bits 0-15)
5930 + } bits;
5931 +} MI_IDR1_t, *PMI_IDR1_t;
5932 +
5933 +/* MI Register 3: Physical Identifier 2 */
5934 +typedef union _MI_IDR2_t {
5935 + u16 value;
5936 + struct {
5937 +#ifdef _BIT_FIELDS_HTOL
5938 + u16 ieee_address:6; // 111100 default(bits 10-15)
5939 + u16 model_no:6; // 000001 default(bits 4-9)
5940 + u16 rev_no:4; // 0010 default(bits 0-3)
5941 +#else
5942 + u16 rev_no:4; // 0010 default(bits 0-3)
5943 + u16 model_no:6; // 000001 default(bits 4-9)
5944 + u16 ieee_address:6; // 111100 default(bits 10-15)
5945 +#endif
5946 + } bits;
5947 +} MI_IDR2_t, *PMI_IDR2_t;
5948 +
5949 +/* MI Register 4: Auto-negotiation advertisement register */
5950 +typedef union _MI_ANAR_t {
5951 + u16 value;
5952 + struct {
5953 +#ifdef _BIT_FIELDS_HTOL
5954 + u16 np_indication:1; // bit 15
5955 + u16 res2:1; // bit 14
5956 + u16 remote_fault:1; // bit 13
5957 + u16 res1:1; // bit 12
5958 + u16 cap_asmpause:1; // bit 11
5959 + u16 cap_pause:1; // bit 10
5960 + u16 cap_100T4:1; // bit 9
5961 + u16 cap_100fdx:1; // bit 8
5962 + u16 cap_100hdx:1; // bit 7
5963 + u16 cap_10fdx:1; // bit 6
5964 + u16 cap_10hdx:1; // bit 5
5965 + u16 selector:5; // bits 0-4
5966 +#else
5967 + u16 selector:5; // bits 0-4
5968 + u16 cap_10hdx:1; // bit 5
5969 + u16 cap_10fdx:1; // bit 6
5970 + u16 cap_100hdx:1; // bit 7
5971 + u16 cap_100fdx:1; // bit 8
5972 + u16 cap_100T4:1; // bit 9
5973 + u16 cap_pause:1; // bit 10
5974 + u16 cap_asmpause:1; // bit 11
5975 + u16 res1:1; // bit 12
5976 + u16 remote_fault:1; // bit 13
5977 + u16 res2:1; // bit 14
5978 + u16 np_indication:1; // bit 15
5979 +#endif
5980 + } bits;
5981 +} MI_ANAR_t, *PMI_ANAR_t;
5982 +
5983 +/* MI Register 5: Auto-negotiation link partner advertisement register */
5984 +typedef struct _MI_ANLPAR_t {
5985 + u16 value;
5986 + struct {
5987 +#ifdef _BIT_FIELDS_HTOL
5988 + u16 np_indication:1; // bit 15
5989 + u16 acknowledge:1; // bit 14
5990 + u16 remote_fault:1; // bit 13
5991 + u16 res1:1; // bit 12
5992 + u16 cap_asmpause:1; // bit 11
5993 + u16 cap_pause:1; // bit 10
5994 + u16 cap_100T4:1; // bit 9
5995 + u16 cap_100fdx:1; // bit 8
5996 + u16 cap_100hdx:1; // bit 7
5997 + u16 cap_10fdx:1; // bit 6
5998 + u16 cap_10hdx:1; // bit 5
5999 + u16 selector:5; // bits 0-4
6000 +#else
6001 + u16 selector:5; // bits 0-4
6002 + u16 cap_10hdx:1; // bit 5
6003 + u16 cap_10fdx:1; // bit 6
6004 + u16 cap_100hdx:1; // bit 7
6005 + u16 cap_100fdx:1; // bit 8
6006 + u16 cap_100T4:1; // bit 9
6007 + u16 cap_pause:1; // bit 10
6008 + u16 cap_asmpause:1; // bit 11
6009 + u16 res1:1; // bit 12
6010 + u16 remote_fault:1; // bit 13
6011 + u16 acknowledge:1; // bit 14
6012 + u16 np_indication:1; // bit 15
6013 +#endif
6014 + } bits;
6015 +} MI_ANLPAR_t, *PMI_ANLPAR_t;
6016 +
6017 +/* MI Register 6: Auto-negotiation expansion register */
6018 +typedef union _MI_ANER_t {
6019 + u16 value;
6020 + struct {
6021 +#ifdef _BIT_FIELDS_HTOL
6022 + u16 res:11; // bits 5-15
6023 + u16 pdf:1; // bit 4
6024 + u16 lp_np_able:1; // bit 3
6025 + u16 np_able:1; // bit 2
6026 + u16 page_rx:1; // bit 1
6027 + u16 lp_an_able:1; // bit 0
6028 +#else
6029 + u16 lp_an_able:1; // bit 0
6030 + u16 page_rx:1; // bit 1
6031 + u16 np_able:1; // bit 2
6032 + u16 lp_np_able:1; // bit 3
6033 + u16 pdf:1; // bit 4
6034 + u16 res:11; // bits 5-15
6035 +#endif
6036 + } bits;
6037 +} MI_ANER_t, *PMI_ANER_t;
6038 +
6039 +/* MI Register 7: Auto-negotiation next page transmit reg(0x07) */
6040 +typedef union _MI_ANNPTR_t {
6041 + u16 value;
6042 + struct {
6043 +#ifdef _BIT_FIELDS_HTOL
6044 + u16 np:1; // bit 15
6045 + u16 res1:1; // bit 14
6046 + u16 msg_page:1; // bit 13
6047 + u16 ack2:1; // bit 12
6048 + u16 toggle:1; // bit 11
6049 + u16 msg:11; // bits 0-10
6050 +#else
6051 + u16 msg:11; // bits 0-10
6052 + u16 toggle:1; // bit 11
6053 + u16 ack2:1; // bit 12
6054 + u16 msg_page:1; // bit 13
6055 + u16 res1:1; // bit 14
6056 + u16 np:1; // bit 15
6057 +#endif
6058 + } bits;
6059 +} MI_ANNPTR_t, *PMI_ANNPTR_t;
6060 +
6061 +/* MI Register 8: Link Partner Next Page Reg(0x08) */
6062 +typedef union _MI_LPNPR_t {
6063 + u16 value;
6064 + struct {
6065 +#ifdef _BIT_FIELDS_HTOL
6066 + u16 np:1; // bit 15
6067 + u16 ack:1; // bit 14
6068 + u16 msg_page:1; // bit 13
6069 + u16 ack2:1; // bit 12
6070 + u16 toggle:1; // bit 11
6071 + u16 msg:11; // bits 0-10
6072 +#else
6073 + u16 msg:11; // bits 0-10
6074 + u16 toggle:1; // bit 11
6075 + u16 ack2:1; // bit 12
6076 + u16 msg_page:1; // bit 13
6077 + u16 ack:1; // bit 14
6078 + u16 np:1; // bit 15
6079 +#endif
6080 + } bits;
6081 +} MI_LPNPR_t, *PMI_LPNPR_t;
6082 +
6083 +/* MI Register 9: 1000BaseT Control Reg(0x09) */
6084 +typedef union _MI_GCR_t {
6085 + u16 value;
6086 + struct {
6087 +#ifdef _BIT_FIELDS_HTOL
6088 + u16 test_mode:3; // bits 13-15
6089 + u16 ms_config_en:1; // bit 12
6090 + u16 ms_value:1; // bit 11
6091 + u16 port_type:1; // bit 10
6092 + u16 link_1000fdx:1; // bit 9
6093 + u16 link_1000hdx:1; // bit 8
6094 + u16 res:8; // bit 0-7
6095 +#else
6096 + u16 res:8; // bit 0-7
6097 + u16 link_1000hdx:1; // bit 8
6098 + u16 link_1000fdx:1; // bit 9
6099 + u16 port_type:1; // bit 10
6100 + u16 ms_value:1; // bit 11
6101 + u16 ms_config_en:1; // bit 12
6102 + u16 test_mode:3; // bits 13-15
6103 +#endif
6104 + } bits;
6105 +} MI_GCR_t, *PMI_GCR_t;
6106 +
6107 +/* MI Register 10: 1000BaseT Status Reg(0x0A) */
6108 +typedef union _MI_GSR_t {
6109 + u16 value;
6110 + struct {
6111 +#ifdef _BIT_FIELDS_HTOL
6112 + u16 ms_config_fault:1; // bit 15
6113 + u16 ms_resolve:1; // bit 14
6114 + u16 local_rx_status:1; // bit 13
6115 + u16 remote_rx_status:1; // bit 12
6116 + u16 link_1000fdx:1; // bit 11
6117 + u16 link_1000hdx:1; // bit 10
6118 + u16 res:2; // bits 8-9
6119 + u16 idle_err_cnt:8; // bits 0-7
6120 +#else
6121 + u16 idle_err_cnt:8; // bits 0-7
6122 + u16 res:2; // bits 8-9
6123 + u16 link_1000hdx:1; // bit 10
6124 + u16 link_1000fdx:1; // bit 11
6125 + u16 remote_rx_status:1; // bit 12
6126 + u16 local_rx_status:1; // bit 13
6127 + u16 ms_resolve:1; // bit 14
6128 + u16 ms_config_fault:1; // bit 15
6129 +#endif
6130 + } bits;
6131 +} MI_GSR_t, *PMI_GSR_t;
6132 +
6133 +/* MI Register 11 - 14: Reserved Regs(0x0B - 0x0E) */
6134 +typedef union _MI_RES_t {
6135 + u16 value;
6136 + struct {
6137 +#ifdef _BIT_FIELDS_HTOL
6138 + u16 res15:1; // bit 15
6139 + u16 res14:1; // bit 14
6140 + u16 res13:1; // bit 13
6141 + u16 res12:1; // bit 12
6142 + u16 res11:1; // bit 11
6143 + u16 res10:1; // bit 10
6144 + u16 res9:1; // bit 9
6145 + u16 res8:1; // bit 8
6146 + u16 res7:1; // bit 7
6147 + u16 res6:1; // bit 6
6148 + u16 res5:1; // bit 5
6149 + u16 res4:1; // bit 4
6150 + u16 res3:1; // bit 3
6151 + u16 res2:1; // bit 2
6152 + u16 res1:1; // bit 1
6153 + u16 res0:1; // bit 0
6154 +#else
6155 + u16 res0:1; // bit 0
6156 + u16 res1:1; // bit 1
6157 + u16 res2:1; // bit 2
6158 + u16 res3:1; // bit 3
6159 + u16 res4:1; // bit 4
6160 + u16 res5:1; // bit 5
6161 + u16 res6:1; // bit 6
6162 + u16 res7:1; // bit 7
6163 + u16 res8:1; // bit 8
6164 + u16 res9:1; // bit 9
6165 + u16 res10:1; // bit 10
6166 + u16 res11:1; // bit 11
6167 + u16 res12:1; // bit 12
6168 + u16 res13:1; // bit 13
6169 + u16 res14:1; // bit 14
6170 + u16 res15:1; // bit 15
6171 +#endif
6172 + } bits;
6173 +} MI_RES_t, *PMI_RES_t;
6174 +
6175 +/* MI Register 15: Extended status Reg(0x0F) */
6176 +typedef union _MI_ESR_t {
6177 + u16 value;
6178 + struct {
6179 +#ifdef _BIT_FIELDS_HTOL
6180 + u16 link_1000Xfdx:1; // bit 15
6181 + u16 link_1000Xhdx:1; // bit 14
6182 + u16 link_1000fdx:1; // bit 13
6183 + u16 link_1000hdx:1; // bit 12
6184 + u16 res:12; // bit 0-11
6185 +#else
6186 + u16 res:12; // bit 0-11
6187 + u16 link_1000hdx:1; // bit 12
6188 + u16 link_1000fdx:1; // bit 13
6189 + u16 link_1000Xhdx:1; // bit 14
6190 + u16 link_1000Xfdx:1; // bit 15
6191 +#endif
6192 + } bits;
6193 +} MI_ESR_t, *PMI_ESR_t;
6194 +
6195 +/* MI Register 16 - 18: Reserved Reg(0x10-0x12) */
6196 +
6197 +/* MI Register 19: Loopback Control Reg(0x13) */
6198 +typedef union _MI_LCR_t {
6199 + u16 value;
6200 + struct {
6201 +#ifdef _BIT_FIELDS_HTOL
6202 + u16 mii_en:1; // bit 15
6203 + u16 pcs_en:1; // bit 14
6204 + u16 pmd_en:1; // bit 13
6205 + u16 all_digital_en:1; // bit 12
6206 + u16 replica_en:1; // bit 11
6207 + u16 line_driver_en:1; // bit 10
6208 + u16 res:10; // bit 0-9
6209 +#else
6210 + u16 res:10; // bit 0-9
6211 + u16 line_driver_en:1; // bit 10
6212 + u16 replica_en:1; // bit 11
6213 + u16 all_digital_en:1; // bit 12
6214 + u16 pmd_en:1; // bit 13
6215 + u16 pcs_en:1; // bit 14
6216 + u16 mii_en:1; // bit 15
6217 +#endif
6218 + } bits;
6219 +} MI_LCR_t, *PMI_LCR_t;
6220 +
6221 +/* MI Register 20: Reserved Reg(0x14) */
6222 +
6223 +/* MI Register 21: Management Interface Control Reg(0x15) */
6224 +typedef union _MI_MICR_t {
6225 + u16 value;
6226 + struct {
6227 +#ifdef _BIT_FIELDS_HTOL
6228 + u16 res1:5; // bits 11-15
6229 + u16 mi_error_count:7; // bits 4-10
6230 + u16 res2:1; // bit 3
6231 + u16 ignore_10g_fr:1; // bit 2
6232 + u16 res3:1; // bit 1
6233 + u16 preamble_supress_en:1; // bit 0
6234 +#else
6235 + u16 preamble_supress_en:1; // bit 0
6236 + u16 res3:1; // bit 1
6237 + u16 ignore_10g_fr:1; // bit 2
6238 + u16 res2:1; // bit 3
6239 + u16 mi_error_count:7; // bits 4-10
6240 + u16 res1:5; // bits 11-15
6241 +#endif
6242 + } bits;
6243 +} MI_MICR_t, *PMI_MICR_t;
6244 +
6245 +/* MI Register 22: PHY Configuration Reg(0x16) */
6246 +typedef union _MI_PHY_CONFIG_t {
6247 + u16 value;
6248 + struct {
6249 +#ifdef _BIT_FIELDS_HTOL
6250 + u16 crs_tx_en:1; // bit 15
6251 + u16 res1:1; // bit 14
6252 + u16 tx_fifo_depth:2; // bits 12-13
6253 + u16 speed_downshift:2; // bits 10-11
6254 + u16 pbi_detect:1; // bit 9
6255 + u16 tbi_rate:1; // bit 8
6256 + u16 alternate_np:1; // bit 7
6257 + u16 group_mdio_en:1; // bit 6
6258 + u16 tx_clock_en:1; // bit 5
6259 + u16 sys_clock_en:1; // bit 4
6260 + u16 res2:1; // bit 3
6261 + u16 mac_if_mode:3; // bits 0-2
6262 +#else
6263 + u16 mac_if_mode:3; // bits 0-2
6264 + u16 res2:1; // bit 3
6265 + u16 sys_clock_en:1; // bit 4
6266 + u16 tx_clock_en:1; // bit 5
6267 + u16 group_mdio_en:1; // bit 6
6268 + u16 alternate_np:1; // bit 7
6269 + u16 tbi_rate:1; // bit 8
6270 + u16 pbi_detect:1; // bit 9
6271 + u16 speed_downshift:2; // bits 10-11
6272 + u16 tx_fifo_depth:2; // bits 12-13
6273 + u16 res1:1; // bit 14
6274 + u16 crs_tx_en:1; // bit 15
6275 +#endif
6276 + } bits;
6277 +} MI_PHY_CONFIG_t, *PMI_PHY_CONFIG_t;
6278 +
6279 +/* MI Register 23: PHY CONTROL Reg(0x17) */
6280 +typedef union _MI_PHY_CONTROL_t {
6281 + u16 value;
6282 + struct {
6283 +#ifdef _BIT_FIELDS_HTOL
6284 + u16 res1:1; // bit 15
6285 + u16 tdr_en:1; // bit 14
6286 + u16 res2:1; // bit 13
6287 + u16 downshift_attempts:2; // bits 11-12
6288 + u16 res3:5; // bit 6-10
6289 + u16 jabber_10baseT:1; // bit 5
6290 + u16 sqe_10baseT:1; // bit 4
6291 + u16 tp_loopback_10baseT:1; // bit 3
6292 + u16 preamble_gen_en:1; // bit 2
6293 + u16 res4:1; // bit 1
6294 + u16 force_int:1; // bit 0
6295 +#else
6296 + u16 force_int:1; // bit 0
6297 + u16 res4:1; // bit 1
6298 + u16 preamble_gen_en:1; // bit 2
6299 + u16 tp_loopback_10baseT:1; // bit 3
6300 + u16 sqe_10baseT:1; // bit 4
6301 + u16 jabber_10baseT:1; // bit 5
6302 + u16 res3:5; // bit 6-10
6303 + u16 downshift_attempts:2; // bits 11-12
6304 + u16 res2:1; // bit 13
6305 + u16 tdr_en:1; // bit 14
6306 + u16 res1:1; // bit 15
6307 +#endif
6308 + } bits;
6309 +} MI_PHY_CONTROL_t, *PMI_PHY_CONTROL_t;
6310 +
6311 +/* MI Register 24: Interrupt Mask Reg(0x18) */
6312 +typedef union _MI_IMR_t {
6313 + u16 value;
6314 + struct {
6315 +#ifdef _BIT_FIELDS_HTOL
6316 + u16 res1:6; // bits 10-15
6317 + u16 mdio_sync_lost:1; // bit 9
6318 + u16 autoneg_status:1; // bit 8
6319 + u16 hi_bit_err:1; // bit 7
6320 + u16 np_rx:1; // bit 6
6321 + u16 err_counter_full:1; // bit 5
6322 + u16 fifo_over_underflow:1; // bit 4
6323 + u16 rx_status:1; // bit 3
6324 + u16 link_status:1; // bit 2
6325 + u16 automatic_speed:1; // bit 1
6326 + u16 int_en:1; // bit 0
6327 +#else
6328 + u16 int_en:1; // bit 0
6329 + u16 automatic_speed:1; // bit 1
6330 + u16 link_status:1; // bit 2
6331 + u16 rx_status:1; // bit 3
6332 + u16 fifo_over_underflow:1; // bit 4
6333 + u16 err_counter_full:1; // bit 5
6334 + u16 np_rx:1; // bit 6
6335 + u16 hi_bit_err:1; // bit 7
6336 + u16 autoneg_status:1; // bit 8
6337 + u16 mdio_sync_lost:1; // bit 9
6338 + u16 res1:6; // bits 10-15
6339 +#endif
6340 + } bits;
6341 +} MI_IMR_t, *PMI_IMR_t;
6342 +
6343 +/* MI Register 25: Interrupt Status Reg(0x19) */
6344 +typedef union _MI_ISR_t {
6345 + u16 value;
6346 + struct {
6347 +#ifdef _BIT_FIELDS_HTOL
6348 + u16 res1:6; // bits 10-15
6349 + u16 mdio_sync_lost:1; // bit 9
6350 + u16 autoneg_status:1; // bit 8
6351 + u16 hi_bit_err:1; // bit 7
6352 + u16 np_rx:1; // bit 6
6353 + u16 err_counter_full:1; // bit 5
6354 + u16 fifo_over_underflow:1; // bit 4
6355 + u16 rx_status:1; // bit 3
6356 + u16 link_status:1; // bit 2
6357 + u16 automatic_speed:1; // bit 1
6358 + u16 int_en:1; // bit 0
6359 +#else
6360 + u16 int_en:1; // bit 0
6361 + u16 automatic_speed:1; // bit 1
6362 + u16 link_status:1; // bit 2
6363 + u16 rx_status:1; // bit 3
6364 + u16 fifo_over_underflow:1; // bit 4
6365 + u16 err_counter_full:1; // bit 5
6366 + u16 np_rx:1; // bit 6
6367 + u16 hi_bit_err:1; // bit 7
6368 + u16 autoneg_status:1; // bit 8
6369 + u16 mdio_sync_lost:1; // bit 9
6370 + u16 res1:6; // bits 10-15
6371 +#endif
6372 + } bits;
6373 +} MI_ISR_t, *PMI_ISR_t;
6374 +
6375 +/* MI Register 26: PHY Status Reg(0x1A) */
6376 +typedef union _MI_PSR_t {
6377 + u16 value;
6378 + struct {
6379 +#ifdef _BIT_FIELDS_HTOL
6380 + u16 res1:1; // bit 15
6381 + u16 autoneg_fault:2; // bit 13-14
6382 + u16 autoneg_status:1; // bit 12
6383 + u16 mdi_x_status:1; // bit 11
6384 + u16 polarity_status:1; // bit 10
6385 + u16 speed_status:2; // bits 8-9
6386 + u16 duplex_status:1; // bit 7
6387 + u16 link_status:1; // bit 6
6388 + u16 tx_status:1; // bit 5
6389 + u16 rx_status:1; // bit 4
6390 + u16 collision_status:1; // bit 3
6391 + u16 autoneg_en:1; // bit 2
6392 + u16 pause_en:1; // bit 1
6393 + u16 asymmetric_dir:1; // bit 0
6394 +#else
6395 + u16 asymmetric_dir:1; // bit 0
6396 + u16 pause_en:1; // bit 1
6397 + u16 autoneg_en:1; // bit 2
6398 + u16 collision_status:1; // bit 3
6399 + u16 rx_status:1; // bit 4
6400 + u16 tx_status:1; // bit 5
6401 + u16 link_status:1; // bit 6
6402 + u16 duplex_status:1; // bit 7
6403 + u16 speed_status:2; // bits 8-9
6404 + u16 polarity_status:1; // bit 10
6405 + u16 mdi_x_status:1; // bit 11
6406 + u16 autoneg_status:1; // bit 12
6407 + u16 autoneg_fault:2; // bit 13-14
6408 + u16 res1:1; // bit 15
6409 +#endif
6410 + } bits;
6411 +} MI_PSR_t, *PMI_PSR_t;
6412 +
6413 +/* MI Register 27: LED Control Reg 1(0x1B) */
6414 +typedef union _MI_LCR1_t {
6415 + u16 value;
6416 + struct {
6417 +#ifdef _BIT_FIELDS_HTOL
6418 + u16 res1:2; // bits 14-15
6419 + u16 led_dup_indicate:2; // bits 12-13
6420 + u16 led_10baseT:2; // bits 10-11
6421 + u16 led_collision:2; // bits 8-9
6422 + u16 res2:2; // bits 6-7
6423 + u16 res3:2; // bits 4-5
6424 + u16 pulse_dur:2; // bits 2-3
6425 + u16 pulse_stretch1:1; // bit 1
6426 + u16 pulse_stretch0:1; // bit 0
6427 +#else
6428 + u16 pulse_stretch0:1; // bit 0
6429 + u16 pulse_stretch1:1; // bit 1
6430 + u16 pulse_dur:2; // bits 2-3
6431 + u16 res3:2; // bits 4-5
6432 + u16 res2:2; // bits 6-7
6433 + u16 led_collision:2; // bits 8-9
6434 + u16 led_10baseT:2; // bits 10-11
6435 + u16 led_dup_indicate:2; // bits 12-13
6436 + u16 res1:2; // bits 14-15
6437 +#endif
6438 + } bits;
6439 +} MI_LCR1_t, *PMI_LCR1_t;
6440 +
6441 +/* MI Register 28: LED Control Reg 2(0x1C) */
6442 +typedef union _MI_LCR2_t {
6443 + u16 value;
6444 + struct {
6445 +#ifdef _BIT_FIELDS_HTOL
6446 + u16 led_link:4; // bits 12-15
6447 + u16 led_tx_rx:4; // bits 8-11
6448 + u16 led_100BaseTX:4; // bits 4-7
6449 + u16 led_1000BaseT:4; // bits 0-3
6450 +#else
6451 + u16 led_1000BaseT:4; // bits 0-3
6452 + u16 led_100BaseTX:4; // bits 4-7
6453 + u16 led_tx_rx:4; // bits 8-11
6454 + u16 led_link:4; // bits 12-15
6455 +#endif
6456 + } bits;
6457 +} MI_LCR2_t, *PMI_LCR2_t;
6458 +
6459 +/* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */
6460 +
6461 +/* TruePHY headers */
6462 +typedef struct _TRUEPHY_ACCESS_MI_REGS_ {
6463 + TRUEPHY_HANDLE hTruePhy;
6464 + int32_t nPhyId;
6465 + u8 bReadWrite;
6466 + u8 *pbyRegs;
6467 + u8 *pwData;
6468 + int32_t nRegCount;
6469 +} TRUEPHY_ACCESS_MI_REGS, *PTRUEPHY_ACCESS_MI_REGS;
6470 +
6471 +/* TruePHY headers */
6472 +typedef struct _TAG_TPAL_ACCESS_MI_REGS_ {
6473 + u32 nPhyId;
6474 + u8 bReadWrite;
6475 + u32 nRegCount;
6476 + u16 Data[4096];
6477 + u8 Regs[4096];
6478 +} TPAL_ACCESS_MI_REGS, *PTPAL_ACCESS_MI_REGS;
6479 +
6480 +
6481 +typedef TRUEPHY_HANDLE TPAL_HANDLE;
6482 +
6483 +/* Forward declaration of the private adapter structure */
6484 +struct et131x_adapter;
6485 +
6486 +/* OS Specific Functions*/
6487 +void TPAL_SetPhy10HalfDuplex(struct et131x_adapter *adapter);
6488 +void TPAL_SetPhy10FullDuplex(struct et131x_adapter *adapter);
6489 +void TPAL_SetPhy10Force(struct et131x_adapter *pAdapter);
6490 +void TPAL_SetPhy100HalfDuplex(struct et131x_adapter *adapter);
6491 +void TPAL_SetPhy100FullDuplex(struct et131x_adapter *adapter);
6492 +void TPAL_SetPhy100Force(struct et131x_adapter *pAdapter);
6493 +void TPAL_SetPhy1000FullDuplex(struct et131x_adapter *adapter);
6494 +void TPAL_SetPhyAutoNeg(struct et131x_adapter *adapter);
6495 +
6496 +/* Prototypes for ET1310_phy.c */
6497 +int et131x_xcvr_find(struct et131x_adapter *adapter);
6498 +int et131x_setphy_normal(struct et131x_adapter *adapter);
6499 +int32_t PhyMiRead(struct et131x_adapter *adapter,
6500 + u8 xcvrAddr, u8 xcvrReg, u16 *value);
6501 +
6502 +/* static inline function does not work because et131x_adapter is not always
6503 + * defined
6504 + */
6505 +#define MiRead(adapter, xcvrReg, value) \
6506 + PhyMiRead((adapter), (adapter)->Stats.xcvr_addr, (xcvrReg), (value))
6507 +
6508 +int32_t MiWrite(struct et131x_adapter *adapter,
6509 + u8 xcvReg, u16 value);
6510 +void et131x_Mii_check(struct et131x_adapter *pAdapter,
6511 + MI_BMSR_t bmsr, MI_BMSR_t bmsr_ints);
6512 +
6513 +/* This last is not strictly required (the driver could call the TPAL
6514 + * version instead), but this sets the adapter up correctly, and calls the
6515 + * access routine indirectly. This protects the driver from changes in TPAL.
6516 + */
6517 +void SetPhy_10BaseTHalfDuplex(struct et131x_adapter *adapter);
6518 +
6519 +/* Defines for PHY access routines */
6520 +
6521 +// Define bit operation flags
6522 +#define TRUEPHY_BIT_CLEAR 0
6523 +#define TRUEPHY_BIT_SET 1
6524 +#define TRUEPHY_BIT_READ 2
6525 +
6526 +// Define read/write operation flags
6527 +#ifndef TRUEPHY_READ
6528 +#define TRUEPHY_READ 0
6529 +#define TRUEPHY_WRITE 1
6530 +#define TRUEPHY_MASK 2
6531 +#endif
6532 +
6533 +// Define speeds
6534 +#define TRUEPHY_SPEED_10MBPS 0
6535 +#define TRUEPHY_SPEED_100MBPS 1
6536 +#define TRUEPHY_SPEED_1000MBPS 2
6537 +
6538 +// Define duplex modes
6539 +#define TRUEPHY_DUPLEX_HALF 0
6540 +#define TRUEPHY_DUPLEX_FULL 1
6541 +
6542 +// Define master/slave configuration values
6543 +#define TRUEPHY_CFG_SLAVE 0
6544 +#define TRUEPHY_CFG_MASTER 1
6545 +
6546 +// Define MDI/MDI-X settings
6547 +#define TRUEPHY_MDI 0
6548 +#define TRUEPHY_MDIX 1
6549 +#define TRUEPHY_AUTO_MDI_MDIX 2
6550 +
6551 +// Define 10Base-T link polarities
6552 +#define TRUEPHY_POLARITY_NORMAL 0
6553 +#define TRUEPHY_POLARITY_INVERTED 1
6554 +
6555 +// Define auto-negotiation results
6556 +#define TRUEPHY_ANEG_NOT_COMPLETE 0
6557 +#define TRUEPHY_ANEG_COMPLETE 1
6558 +#define TRUEPHY_ANEG_DISABLED 2
6559 +
6560 +/* Define duplex advertisment flags */
6561 +#define TRUEPHY_ADV_DUPLEX_NONE 0x00
6562 +#define TRUEPHY_ADV_DUPLEX_FULL 0x01
6563 +#define TRUEPHY_ADV_DUPLEX_HALF 0x02
6564 +#define TRUEPHY_ADV_DUPLEX_BOTH \
6565 + (TRUEPHY_ADV_DUPLEX_FULL | TRUEPHY_ADV_DUPLEX_HALF)
6566 +
6567 +#define PHY_CONTROL 0x00 //#define TRU_MI_CONTROL_REGISTER 0
6568 +#define PHY_STATUS 0x01 //#define TRU_MI_STATUS_REGISTER 1
6569 +#define PHY_ID_1 0x02 //#define TRU_MI_PHY_IDENTIFIER_1_REGISTER 2
6570 +#define PHY_ID_2 0x03 //#define TRU_MI_PHY_IDENTIFIER_2_REGISTER 3
6571 +#define PHY_AUTO_ADVERTISEMENT 0x04 //#define TRU_MI_ADVERTISEMENT_REGISTER 4
6572 +#define PHY_AUTO_LINK_PARTNER 0x05 //#define TRU_MI_LINK_PARTNER_ABILITY_REGISTER 5
6573 +#define PHY_AUTO_EXPANSION 0x06 //#define TRU_MI_EXPANSION_REGISTER 6
6574 +#define PHY_AUTO_NEXT_PAGE_TX 0x07 //#define TRU_MI_NEXT_PAGE_TRANSMIT_REGISTER 7
6575 +#define PHY_LINK_PARTNER_NEXT_PAGE 0x08 //#define TRU_MI_LINK_PARTNER_NEXT_PAGE_REGISTER 8
6576 +#define PHY_1000_CONTROL 0x09 //#define TRU_MI_1000BASET_CONTROL_REGISTER 9
6577 +#define PHY_1000_STATUS 0x0A //#define TRU_MI_1000BASET_STATUS_REGISTER 10
6578 +
6579 +#define PHY_EXTENDED_STATUS 0x0F //#define TRU_MI_EXTENDED_STATUS_REGISTER 15
6580 +
6581 +// some defines for modem registers that seem to be 'reserved'
6582 +#define PHY_INDEX_REG 0x10
6583 +#define PHY_DATA_REG 0x11
6584 +
6585 +#define PHY_MPHY_CONTROL_REG 0x12 //#define TRU_VMI_MPHY_CONTROL_REGISTER 18
6586 +
6587 +#define PHY_LOOPBACK_CONTROL 0x13 //#define TRU_VMI_LOOPBACK_CONTROL_1_REGISTER 19
6588 + //#define TRU_VMI_LOOPBACK_CONTROL_2_REGISTER 20
6589 +#define PHY_REGISTER_MGMT_CONTROL 0x15 //#define TRU_VMI_MI_SEQ_CONTROL_REGISTER 21
6590 +#define PHY_CONFIG 0x16 //#define TRU_VMI_CONFIGURATION_REGISTER 22
6591 +#define PHY_PHY_CONTROL 0x17 //#define TRU_VMI_PHY_CONTROL_REGISTER 23
6592 +#define PHY_INTERRUPT_MASK 0x18 //#define TRU_VMI_INTERRUPT_MASK_REGISTER 24
6593 +#define PHY_INTERRUPT_STATUS 0x19 //#define TRU_VMI_INTERRUPT_STATUS_REGISTER 25
6594 +#define PHY_PHY_STATUS 0x1A //#define TRU_VMI_PHY_STATUS_REGISTER 26
6595 +#define PHY_LED_1 0x1B //#define TRU_VMI_LED_CONTROL_1_REGISTER 27
6596 +#define PHY_LED_2 0x1C //#define TRU_VMI_LED_CONTROL_2_REGISTER 28
6597 + //#define TRU_VMI_LINK_CONTROL_REGISTER 29
6598 + //#define TRU_VMI_TIMING_CONTROL_REGISTER
6599 +
6600 +/* Prototypes for PHY access routines */
6601 +void ET1310_PhyInit(struct et131x_adapter *adapter);
6602 +void ET1310_PhyReset(struct et131x_adapter *adapter);
6603 +void ET1310_PhyPowerDown(struct et131x_adapter *adapter, bool down);
6604 +void ET1310_PhyAutoNeg(struct et131x_adapter *adapter, bool enable);
6605 +void ET1310_PhyDuplexMode(struct et131x_adapter *adapter, u16 duplex);
6606 +void ET1310_PhySpeedSelect(struct et131x_adapter *adapter, u16 speed);
6607 +void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *adapter,
6608 + u16 duplex);
6609 +void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *adapter,
6610 + u16 duplex);
6611 +void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *adapter,
6612 + u16 duplex);
6613 +void ET1310_PhyLinkStatus(struct et131x_adapter *adapter,
6614 + u8 *ucLinkStatus,
6615 + u32 *uiAutoNeg,
6616 + u32 *uiLinkSpeed,
6617 + u32 *uiDuplexMode,
6618 + u32 *uiMdiMdix,
6619 + u32 *uiMasterSlave, u32 *uiPolarity);
6620 +void ET1310_PhyAndOrReg(struct et131x_adapter *adapter,
6621 + u16 regnum, u16 andMask, u16 orMask);
6622 +void ET1310_PhyAccessMiBit(struct et131x_adapter *adapter,
6623 + u16 action,
6624 + u16 regnum, u16 bitnum, u8 *value);
6625 +
6626 +#endif /* _ET1310_PHY_H_ */
6627 diff --git a/drivers/staging/et131x/et1310_pm.c b/drivers/staging/et131x/et1310_pm.c
6628 new file mode 100644
6629 index 0000000..9539bc6
6630 --- /dev/null
6631 +++ b/drivers/staging/et131x/et1310_pm.c
6632 @@ -0,0 +1,207 @@
6633 +/*
6634 + * Agere Systems Inc.
6635 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
6636 + *
6637 + * Copyright © 2005 Agere Systems Inc.
6638 + * All rights reserved.
6639 + * http://www.agere.com
6640 + *
6641 + *------------------------------------------------------------------------------
6642 + *
6643 + * et1310_pm.c - All power management related code (not completely implemented)
6644 + *
6645 + *------------------------------------------------------------------------------
6646 + *
6647 + * SOFTWARE LICENSE
6648 + *
6649 + * This software is provided subject to the following terms and conditions,
6650 + * which you should read carefully before using the software. Using this
6651 + * software indicates your acceptance of these terms and conditions. If you do
6652 + * not agree with these terms and conditions, do not use the software.
6653 + *
6654 + * Copyright © 2005 Agere Systems Inc.
6655 + * All rights reserved.
6656 + *
6657 + * Redistribution and use in source or binary forms, with or without
6658 + * modifications, are permitted provided that the following conditions are met:
6659 + *
6660 + * . Redistributions of source code must retain the above copyright notice, this
6661 + * list of conditions and the following Disclaimer as comments in the code as
6662 + * well as in the documentation and/or other materials provided with the
6663 + * distribution.
6664 + *
6665 + * . Redistributions in binary form must reproduce the above copyright notice,
6666 + * this list of conditions and the following Disclaimer in the documentation
6667 + * and/or other materials provided with the distribution.
6668 + *
6669 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
6670 + * may be used to endorse or promote products derived from this software
6671 + * without specific prior written permission.
6672 + *
6673 + * Disclaimer
6674 + *
6675 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
6676 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
6677 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
6678 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
6679 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
6680 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
6681 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
6682 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
6683 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
6684 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
6685 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
6686 + * DAMAGE.
6687 + *
6688 + */
6689 +
6690 +#include "et131x_version.h"
6691 +#include "et131x_debug.h"
6692 +#include "et131x_defs.h"
6693 +
6694 +#include <linux/init.h>
6695 +#include <linux/module.h>
6696 +#include <linux/types.h>
6697 +#include <linux/kernel.h>
6698 +
6699 +#include <linux/sched.h>
6700 +#include <linux/ptrace.h>
6701 +#include <linux/slab.h>
6702 +#include <linux/ctype.h>
6703 +#include <linux/string.h>
6704 +#include <linux/timer.h>
6705 +#include <linux/interrupt.h>
6706 +#include <linux/in.h>
6707 +#include <linux/delay.h>
6708 +#include <asm/io.h>
6709 +#include <asm/system.h>
6710 +#include <asm/bitops.h>
6711 +
6712 +#include <linux/netdevice.h>
6713 +#include <linux/etherdevice.h>
6714 +#include <linux/skbuff.h>
6715 +#include <linux/if_arp.h>
6716 +#include <linux/ioport.h>
6717 +
6718 +#include "et1310_phy.h"
6719 +#include "et1310_pm.h"
6720 +#include "et1310_jagcore.h"
6721 +#include "et1310_mac.h"
6722 +#include "et1310_rx.h"
6723 +
6724 +#include "et131x_adapter.h"
6725 +#include "et131x_initpci.h"
6726 +
6727 +/* Data for debugging facilities */
6728 +#ifdef CONFIG_ET131X_DEBUG
6729 +extern dbg_info_t *et131x_dbginfo;
6730 +#endif /* CONFIG_ET131X_DEBUG */
6731 +
6732 +/**
6733 + * EnablePhyComa - called when network cable is unplugged
6734 + * @pAdapter: pointer to our adapter structure
6735 + *
6736 + * driver receive an phy status change interrupt while in D0 and check that
6737 + * phy_status is down.
6738 + *
6739 + * -- gate off JAGCore;
6740 + * -- set gigE PHY in Coma mode
6741 + * -- wake on phy_interrupt; Perform software reset JAGCore,
6742 + * re-initialize jagcore and gigE PHY
6743 + *
6744 + * Add D0-ASPM-PhyLinkDown Support:
6745 + * -- while in D0, when there is a phy_interrupt indicating phy link
6746 + * down status, call the MPSetPhyComa routine to enter this active
6747 + * state power saving mode
6748 + * -- while in D0-ASPM-PhyLinkDown mode, when there is a phy_interrupt
6749 + * indicating linkup status, call the MPDisablePhyComa routine to
6750 + * restore JAGCore and gigE PHY
6751 + */
6752 +void EnablePhyComa(struct et131x_adapter *pAdapter)
6753 +{
6754 + unsigned long lockflags;
6755 + PM_CSR_t GlobalPmCSR;
6756 + int32_t LoopCounter = 10;
6757 +
6758 + DBG_ENTER(et131x_dbginfo);
6759 +
6760 + GlobalPmCSR.value = readl(&pAdapter->CSRAddress->global.pm_csr.value);
6761 +
6762 + /* Save the GbE PHY speed and duplex modes. Need to restore this
6763 + * when cable is plugged back in
6764 + */
6765 + pAdapter->PoMgmt.PowerDownSpeed = pAdapter->AiForceSpeed;
6766 + pAdapter->PoMgmt.PowerDownDuplex = pAdapter->AiForceDpx;
6767 +
6768 + /* Stop sending packets. */
6769 + spin_lock_irqsave(&pAdapter->SendHWLock, lockflags);
6770 + MP_SET_FLAG(pAdapter, fMP_ADAPTER_LOWER_POWER);
6771 + spin_unlock_irqrestore(&pAdapter->SendHWLock, lockflags);
6772 +
6773 + /* Wait for outstanding Receive packets */
6774 + while ((MP_GET_RCV_REF(pAdapter) != 0) && (LoopCounter-- > 0)) {
6775 + mdelay(2);
6776 + }
6777 +
6778 + /* Gate off JAGCore 3 clock domains */
6779 + GlobalPmCSR.bits.pm_sysclk_gate = 0;
6780 + GlobalPmCSR.bits.pm_txclk_gate = 0;
6781 + GlobalPmCSR.bits.pm_rxclk_gate = 0;
6782 + writel(GlobalPmCSR.value, &pAdapter->CSRAddress->global.pm_csr.value);
6783 +
6784 + /* Program gigE PHY in to Coma mode */
6785 + GlobalPmCSR.bits.pm_phy_sw_coma = 1;
6786 + writel(GlobalPmCSR.value, &pAdapter->CSRAddress->global.pm_csr.value);
6787 +
6788 + DBG_LEAVE(et131x_dbginfo);
6789 +}
6790 +
6791 +/**
6792 + * DisablePhyComa - Disable the Phy Coma Mode
6793 + * @pAdapter: pointer to our adapter structure
6794 + */
6795 +void DisablePhyComa(struct et131x_adapter *pAdapter)
6796 +{
6797 + PM_CSR_t GlobalPmCSR;
6798 +
6799 + DBG_ENTER(et131x_dbginfo);
6800 +
6801 + GlobalPmCSR.value = readl(&pAdapter->CSRAddress->global.pm_csr.value);
6802 +
6803 + /* Disable phy_sw_coma register and re-enable JAGCore clocks */
6804 + GlobalPmCSR.bits.pm_sysclk_gate = 1;
6805 + GlobalPmCSR.bits.pm_txclk_gate = 1;
6806 + GlobalPmCSR.bits.pm_rxclk_gate = 1;
6807 + GlobalPmCSR.bits.pm_phy_sw_coma = 0;
6808 + writel(GlobalPmCSR.value, &pAdapter->CSRAddress->global.pm_csr.value);
6809 +
6810 + /* Restore the GbE PHY speed and duplex modes;
6811 + * Reset JAGCore; re-configure and initialize JAGCore and gigE PHY
6812 + */
6813 + pAdapter->AiForceSpeed = pAdapter->PoMgmt.PowerDownSpeed;
6814 + pAdapter->AiForceDpx = pAdapter->PoMgmt.PowerDownDuplex;
6815 +
6816 + /* Re-initialize the send structures */
6817 + et131x_init_send(pAdapter);
6818 +
6819 + /* Reset the RFD list and re-start RU */
6820 + et131x_reset_recv(pAdapter);
6821 +
6822 + /* Bring the device back to the state it was during init prior to
6823 + * autonegotiation being complete. This way, when we get the auto-neg
6824 + * complete interrupt, we can complete init by calling ConfigMacREGS2.
6825 + */
6826 + et131x_soft_reset(pAdapter);
6827 +
6828 + /* setup et1310 as per the documentation ?? */
6829 + et131x_adapter_setup(pAdapter);
6830 +
6831 + /* Allow Tx to restart */
6832 + MP_CLEAR_FLAG(pAdapter, fMP_ADAPTER_LOWER_POWER);
6833 +
6834 + /* Need to re-enable Rx. */
6835 + et131x_rx_dma_enable(pAdapter);
6836 +
6837 + DBG_LEAVE(et131x_dbginfo);
6838 +}
6839 +
6840 diff --git a/drivers/staging/et131x/et1310_pm.h b/drivers/staging/et131x/et1310_pm.h
6841 new file mode 100644
6842 index 0000000..6802338
6843 --- /dev/null
6844 +++ b/drivers/staging/et131x/et1310_pm.h
6845 @@ -0,0 +1,125 @@
6846 +/*
6847 + * Agere Systems Inc.
6848 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
6849 + *
6850 + * Copyright © 2005 Agere Systems Inc.
6851 + * All rights reserved.
6852 + * http://www.agere.com
6853 + *
6854 + *------------------------------------------------------------------------------
6855 + *
6856 + * et1310_pm.h - Defines, structs, enums, prototypes, etc. pertaining to power
6857 + * management.
6858 + *
6859 + *------------------------------------------------------------------------------
6860 + *
6861 + * SOFTWARE LICENSE
6862 + *
6863 + * This software is provided subject to the following terms and conditions,
6864 + * which you should read carefully before using the software. Using this
6865 + * software indicates your acceptance of these terms and conditions. If you do
6866 + * not agree with these terms and conditions, do not use the software.
6867 + *
6868 + * Copyright © 2005 Agere Systems Inc.
6869 + * All rights reserved.
6870 + *
6871 + * Redistribution and use in source or binary forms, with or without
6872 + * modifications, are permitted provided that the following conditions are met:
6873 + *
6874 + * . Redistributions of source code must retain the above copyright notice, this
6875 + * list of conditions and the following Disclaimer as comments in the code as
6876 + * well as in the documentation and/or other materials provided with the
6877 + * distribution.
6878 + *
6879 + * . Redistributions in binary form must reproduce the above copyright notice,
6880 + * this list of conditions and the following Disclaimer in the documentation
6881 + * and/or other materials provided with the distribution.
6882 + *
6883 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
6884 + * may be used to endorse or promote products derived from this software
6885 + * without specific prior written permission.
6886 + *
6887 + * Disclaimer
6888 + *
6889 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
6890 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
6891 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
6892 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
6893 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
6894 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
6895 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
6896 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
6897 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
6898 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
6899 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
6900 + * DAMAGE.
6901 + *
6902 + */
6903 +
6904 +#ifndef _ET1310_PM_H_
6905 +#define _ET1310_PM_H_
6906 +
6907 +#include "et1310_address_map.h"
6908 +
6909 +#define MAX_WOL_PACKET_SIZE 0x80
6910 +#define MAX_WOL_MASK_SIZE ( MAX_WOL_PACKET_SIZE / 8 )
6911 +#define NUM_WOL_PATTERNS 0x5
6912 +#define CRC16_POLY 0x1021
6913 +
6914 +/* Definition of NDIS_DEVICE_POWER_STATE */
6915 +typedef enum {
6916 + NdisDeviceStateUnspecified = 0,
6917 + NdisDeviceStateD0,
6918 + NdisDeviceStateD1,
6919 + NdisDeviceStateD2,
6920 + NdisDeviceStateD3
6921 +} NDIS_DEVICE_POWER_STATE;
6922 +
6923 +typedef struct _MP_POWER_MGMT {
6924 + /* variable putting the phy into coma mode when boot up with no cable
6925 + * plugged in after 5 seconds
6926 + */
6927 + u8 TransPhyComaModeOnBoot;
6928 +
6929 + /* Array holding the five CRC values that the device is currently
6930 + * using for WOL. This will be queried when a pattern is to be
6931 + * removed.
6932 + */
6933 + u32 localWolAndCrc0;
6934 + u16 WOLPatternList[NUM_WOL_PATTERNS];
6935 + u8 WOLMaskList[NUM_WOL_PATTERNS][MAX_WOL_MASK_SIZE];
6936 + u32 WOLMaskSize[NUM_WOL_PATTERNS];
6937 +
6938 + /* IP address */
6939 + union {
6940 + u32 u32;
6941 + u8 u8[4];
6942 + } IPAddress;
6943 +
6944 + /* Current Power state of the adapter. */
6945 + NDIS_DEVICE_POWER_STATE PowerState;
6946 + bool WOLState;
6947 + bool WOLEnabled;
6948 + bool Failed10Half;
6949 + bool bFailedStateTransition;
6950 +
6951 + /* Next two used to save power information at power down. This
6952 + * information will be used during power up to set up parts of Power
6953 + * Management in JAGCore
6954 + */
6955 + u32 tx_en;
6956 + u32 rx_en;
6957 + u16 PowerDownSpeed;
6958 + u8 PowerDownDuplex;
6959 +} MP_POWER_MGMT, *PMP_POWER_MGMT;
6960 +
6961 +/* Forward declaration of the private adapter structure
6962 + * ( IS THERE A WAY TO DO THIS WITH A TYPEDEF??? )
6963 + */
6964 +struct et131x_adapter;
6965 +
6966 +u16 CalculateCCITCRC16(u8 *Pattern, u8 *Mask, u32 MaskSize);
6967 +void EnablePhyComa(struct et131x_adapter *adapter);
6968 +void DisablePhyComa(struct et131x_adapter *adapter);
6969 +
6970 +#endif /* _ET1310_PM_H_ */
6971 diff --git a/drivers/staging/et131x/et1310_rx.c b/drivers/staging/et131x/et1310_rx.c
6972 new file mode 100644
6973 index 0000000..ec98da5
6974 --- /dev/null
6975 +++ b/drivers/staging/et131x/et1310_rx.c
6976 @@ -0,0 +1,1391 @@
6977 +/*
6978 + * Agere Systems Inc.
6979 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
6980 + *
6981 + * Copyright © 2005 Agere Systems Inc.
6982 + * All rights reserved.
6983 + * http://www.agere.com
6984 + *
6985 + *------------------------------------------------------------------------------
6986 + *
6987 + * et1310_rx.c - Routines used to perform data reception
6988 + *
6989 + *------------------------------------------------------------------------------
6990 + *
6991 + * SOFTWARE LICENSE
6992 + *
6993 + * This software is provided subject to the following terms and conditions,
6994 + * which you should read carefully before using the software. Using this
6995 + * software indicates your acceptance of these terms and conditions. If you do
6996 + * not agree with these terms and conditions, do not use the software.
6997 + *
6998 + * Copyright © 2005 Agere Systems Inc.
6999 + * All rights reserved.
7000 + *
7001 + * Redistribution and use in source or binary forms, with or without
7002 + * modifications, are permitted provided that the following conditions are met:
7003 + *
7004 + * . Redistributions of source code must retain the above copyright notice, this
7005 + * list of conditions and the following Disclaimer as comments in the code as
7006 + * well as in the documentation and/or other materials provided with the
7007 + * distribution.
7008 + *
7009 + * . Redistributions in binary form must reproduce the above copyright notice,
7010 + * this list of conditions and the following Disclaimer in the documentation
7011 + * and/or other materials provided with the distribution.
7012 + *
7013 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
7014 + * may be used to endorse or promote products derived from this software
7015 + * without specific prior written permission.
7016 + *
7017 + * Disclaimer
7018 + *
7019 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
7020 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
7021 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
7022 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
7023 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
7024 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
7025 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
7026 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
7027 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
7028 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
7029 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
7030 + * DAMAGE.
7031 + *
7032 + */
7033 +
7034 +#include "et131x_version.h"
7035 +#include "et131x_debug.h"
7036 +#include "et131x_defs.h"
7037 +
7038 +#include <linux/pci.h>
7039 +#include <linux/init.h>
7040 +#include <linux/module.h>
7041 +#include <linux/types.h>
7042 +#include <linux/kernel.h>
7043 +
7044 +#include <linux/sched.h>
7045 +#include <linux/ptrace.h>
7046 +#include <linux/slab.h>
7047 +#include <linux/ctype.h>
7048 +#include <linux/string.h>
7049 +#include <linux/timer.h>
7050 +#include <linux/interrupt.h>
7051 +#include <linux/in.h>
7052 +#include <linux/delay.h>
7053 +#include <asm/io.h>
7054 +#include <asm/system.h>
7055 +#include <asm/bitops.h>
7056 +
7057 +#include <linux/netdevice.h>
7058 +#include <linux/etherdevice.h>
7059 +#include <linux/skbuff.h>
7060 +#include <linux/if_arp.h>
7061 +#include <linux/ioport.h>
7062 +
7063 +#include "et1310_phy.h"
7064 +#include "et1310_pm.h"
7065 +#include "et1310_jagcore.h"
7066 +
7067 +#include "et131x_adapter.h"
7068 +#include "et131x_initpci.h"
7069 +
7070 +#include "et1310_rx.h"
7071 +
7072 +/* Data for debugging facilities */
7073 +#ifdef CONFIG_ET131X_DEBUG
7074 +extern dbg_info_t *et131x_dbginfo;
7075 +#endif /* CONFIG_ET131X_DEBUG */
7076 +
7077 +
7078 +void nic_return_rfd(struct et131x_adapter *pAdapter, PMP_RFD pMpRfd);
7079 +
7080 +/**
7081 + * et131x_rx_dma_memory_alloc
7082 + * @adapter: pointer to our private adapter structure
7083 + *
7084 + * Returns 0 on success and errno on failure (as defined in errno.h)
7085 + *
7086 + * Allocates Free buffer ring 1 for sure, free buffer ring 0 if required,
7087 + * and the Packet Status Ring.
7088 + */
7089 +int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
7090 +{
7091 + uint32_t OuterLoop, InnerLoop;
7092 + uint32_t bufsize;
7093 + uint32_t pktStatRingSize, FBRChunkSize;
7094 + RX_RING_t *rx_ring;
7095 +
7096 + DBG_ENTER(et131x_dbginfo);
7097 +
7098 + /* Setup some convenience pointers */
7099 + rx_ring = (RX_RING_t *) & adapter->RxRing;
7100 +
7101 + /* Alloc memory for the lookup table */
7102 +#ifdef USE_FBR0
7103 + rx_ring->Fbr[0] = kmalloc(sizeof(FBRLOOKUPTABLE), GFP_KERNEL);
7104 +#endif
7105 +
7106 + rx_ring->Fbr[1] = kmalloc(sizeof(FBRLOOKUPTABLE), GFP_KERNEL);
7107 +
7108 + /* The first thing we will do is configure the sizes of the buffer
7109 + * rings. These will change based on jumbo packet support. Larger
7110 + * jumbo packets increases the size of each entry in FBR0, and the
7111 + * number of entries in FBR0, while at the same time decreasing the
7112 + * number of entries in FBR1.
7113 + *
7114 + * FBR1 holds "large" frames, FBR0 holds "small" frames. If FBR1
7115 + * entries are huge in order to accomodate a "jumbo" frame, then it
7116 + * will have less entries. Conversely, FBR1 will now be relied upon
7117 + * to carry more "normal" frames, thus it's entry size also increases
7118 + * and the number of entries goes up too (since it now carries
7119 + * "small" + "regular" packets.
7120 + *
7121 + * In this scheme, we try to maintain 512 entries between the two
7122 + * rings. Also, FBR1 remains a constant size - when it's size doubles
7123 + * the number of entries halves. FBR0 increases in size, however.
7124 + */
7125 +
7126 + if (adapter->RegistryJumboPacket < 2048) {
7127 +#ifdef USE_FBR0
7128 + rx_ring->Fbr0BufferSize = 256;
7129 + rx_ring->Fbr0NumEntries = 512;
7130 +#endif
7131 + rx_ring->Fbr1BufferSize = 2048;
7132 + rx_ring->Fbr1NumEntries = 512;
7133 + } else if (adapter->RegistryJumboPacket < 4096) {
7134 +#ifdef USE_FBR0
7135 + rx_ring->Fbr0BufferSize = 512;
7136 + rx_ring->Fbr0NumEntries = 1024;
7137 +#endif
7138 + rx_ring->Fbr1BufferSize = 4096;
7139 + rx_ring->Fbr1NumEntries = 512;
7140 + } else {
7141 +#ifdef USE_FBR0
7142 + rx_ring->Fbr0BufferSize = 1024;
7143 + rx_ring->Fbr0NumEntries = 768;
7144 +#endif
7145 + rx_ring->Fbr1BufferSize = 16384;
7146 + rx_ring->Fbr1NumEntries = 128;
7147 + }
7148 +
7149 +#ifdef USE_FBR0
7150 + adapter->RxRing.PsrNumEntries = adapter->RxRing.Fbr0NumEntries +
7151 + adapter->RxRing.Fbr1NumEntries;
7152 +#else
7153 + adapter->RxRing.PsrNumEntries = adapter->RxRing.Fbr1NumEntries;
7154 +#endif
7155 +
7156 + /* Allocate an area of memory for Free Buffer Ring 1 */
7157 + bufsize = (sizeof(FBR_DESC_t) * rx_ring->Fbr1NumEntries) + 0xfff;
7158 + rx_ring->pFbr1RingVa = pci_alloc_consistent(adapter->pdev,
7159 + bufsize,
7160 + &rx_ring->pFbr1RingPa);
7161 + if (!rx_ring->pFbr1RingVa) {
7162 + DBG_ERROR(et131x_dbginfo,
7163 + "Cannot alloc memory for Free Buffer Ring 1\n");
7164 + DBG_LEAVE(et131x_dbginfo);
7165 + return -ENOMEM;
7166 + }
7167 +
7168 + /* Save physical address
7169 + *
7170 + * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
7171 + * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
7172 + * are ever returned, make sure the high part is retrieved here
7173 + * before storing the adjusted address.
7174 + */
7175 + rx_ring->Fbr1Realpa = rx_ring->pFbr1RingPa;
7176 +
7177 + /* Align Free Buffer Ring 1 on a 4K boundary */
7178 + et131x_align_allocated_memory(adapter,
7179 + &rx_ring->Fbr1Realpa,
7180 + &rx_ring->Fbr1offset, 0x0FFF);
7181 +
7182 + rx_ring->pFbr1RingVa = (void *)((uint8_t *) rx_ring->pFbr1RingVa +
7183 + rx_ring->Fbr1offset);
7184 +
7185 +#ifdef USE_FBR0
7186 + /* Allocate an area of memory for Free Buffer Ring 0 */
7187 + bufsize = (sizeof(FBR_DESC_t) * rx_ring->Fbr0NumEntries) + 0xfff;
7188 + rx_ring->pFbr0RingVa = pci_alloc_consistent(adapter->pdev,
7189 + bufsize,
7190 + &rx_ring->pFbr0RingPa);
7191 + if (!rx_ring->pFbr0RingVa) {
7192 + DBG_ERROR(et131x_dbginfo,
7193 + "Cannot alloc memory for Free Buffer Ring 0\n");
7194 + DBG_LEAVE(et131x_dbginfo);
7195 + return -ENOMEM;
7196 + }
7197 +
7198 + /* Save physical address
7199 + *
7200 + * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
7201 + * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
7202 + * are ever returned, make sure the high part is retrieved here before
7203 + * storing the adjusted address.
7204 + */
7205 + rx_ring->Fbr0Realpa = rx_ring->pFbr0RingPa;
7206 +
7207 + /* Align Free Buffer Ring 0 on a 4K boundary */
7208 + et131x_align_allocated_memory(adapter,
7209 + &rx_ring->Fbr0Realpa,
7210 + &rx_ring->Fbr0offset, 0x0FFF);
7211 +
7212 + rx_ring->pFbr0RingVa = (void *)((uint8_t *) rx_ring->pFbr0RingVa +
7213 + rx_ring->Fbr0offset);
7214 +#endif
7215 +
7216 + for (OuterLoop = 0; OuterLoop < (rx_ring->Fbr1NumEntries / FBR_CHUNKS);
7217 + OuterLoop++) {
7218 + uint64_t Fbr1Offset;
7219 + uint64_t Fbr1TempPa;
7220 + uint32_t Fbr1Align;
7221 +
7222 + /* This code allocates an area of memory big enough for N
7223 + * free buffers + (buffer_size - 1) so that the buffers can
7224 + * be aligned on 4k boundaries. If each buffer were aligned
7225 + * to a buffer_size boundary, the effect would be to double
7226 + * the size of FBR0. By allocating N buffers at once, we
7227 + * reduce this overhead.
7228 + */
7229 + if (rx_ring->Fbr1BufferSize > 4096) {
7230 + Fbr1Align = 4096;
7231 + } else {
7232 + Fbr1Align = rx_ring->Fbr1BufferSize;
7233 + }
7234 +
7235 + FBRChunkSize =
7236 + (FBR_CHUNKS * rx_ring->Fbr1BufferSize) + Fbr1Align - 1;
7237 + rx_ring->Fbr1MemVa[OuterLoop] =
7238 + pci_alloc_consistent(adapter->pdev, FBRChunkSize,
7239 + &rx_ring->Fbr1MemPa[OuterLoop]);
7240 +
7241 + if (!rx_ring->Fbr1MemVa[OuterLoop]) {
7242 + DBG_ERROR(et131x_dbginfo, "Could not alloc memory\n");
7243 + DBG_LEAVE(et131x_dbginfo);
7244 + return -ENOMEM;
7245 + }
7246 +
7247 + /* See NOTE in "Save Physical Address" comment above */
7248 + Fbr1TempPa = rx_ring->Fbr1MemPa[OuterLoop];
7249 +
7250 + et131x_align_allocated_memory(adapter,
7251 + &Fbr1TempPa,
7252 + &Fbr1Offset, (Fbr1Align - 1));
7253 +
7254 + for (InnerLoop = 0; InnerLoop < FBR_CHUNKS; InnerLoop++) {
7255 + uint32_t index = (OuterLoop * FBR_CHUNKS) + InnerLoop;
7256 +
7257 + /* Save the Virtual address of this index for quick
7258 + * access later
7259 + */
7260 + rx_ring->Fbr[1]->Va[index] =
7261 + (uint8_t *) rx_ring->Fbr1MemVa[OuterLoop] +
7262 + (InnerLoop * rx_ring->Fbr1BufferSize) + Fbr1Offset;
7263 +
7264 + /* now store the physical address in the descriptor
7265 + * so the device can access it
7266 + */
7267 + rx_ring->Fbr[1]->PAHigh[index] =
7268 + (uint32_t) (Fbr1TempPa >> 32);
7269 + rx_ring->Fbr[1]->PALow[index] = (uint32_t) Fbr1TempPa;
7270 +
7271 + Fbr1TempPa += rx_ring->Fbr1BufferSize;
7272 +
7273 + rx_ring->Fbr[1]->Buffer1[index] =
7274 + rx_ring->Fbr[1]->Va[index];
7275 + rx_ring->Fbr[1]->Buffer2[index] =
7276 + rx_ring->Fbr[1]->Va[index] - 4;
7277 + }
7278 + }
7279 +
7280 +#ifdef USE_FBR0
7281 + /* Same for FBR0 (if in use) */
7282 + for (OuterLoop = 0; OuterLoop < (rx_ring->Fbr0NumEntries / FBR_CHUNKS);
7283 + OuterLoop++) {
7284 + uint64_t Fbr0Offset;
7285 + uint64_t Fbr0TempPa;
7286 +
7287 + FBRChunkSize = ((FBR_CHUNKS + 1) * rx_ring->Fbr0BufferSize) - 1;
7288 + rx_ring->Fbr0MemVa[OuterLoop] =
7289 + pci_alloc_consistent(adapter->pdev, FBRChunkSize,
7290 + &rx_ring->Fbr0MemPa[OuterLoop]);
7291 +
7292 + if (!rx_ring->Fbr0MemVa[OuterLoop]) {
7293 + DBG_ERROR(et131x_dbginfo, "Could not alloc memory\n");
7294 + DBG_LEAVE(et131x_dbginfo);
7295 + return -ENOMEM;
7296 + }
7297 +
7298 + /* See NOTE in "Save Physical Address" comment above */
7299 + Fbr0TempPa = rx_ring->Fbr0MemPa[OuterLoop];
7300 +
7301 + et131x_align_allocated_memory(adapter,
7302 + &Fbr0TempPa,
7303 + &Fbr0Offset,
7304 + rx_ring->Fbr0BufferSize - 1);
7305 +
7306 + for (InnerLoop = 0; InnerLoop < FBR_CHUNKS; InnerLoop++) {
7307 + uint32_t index = (OuterLoop * FBR_CHUNKS) + InnerLoop;
7308 +
7309 + rx_ring->Fbr[0]->Va[index] =
7310 + (uint8_t *) rx_ring->Fbr0MemVa[OuterLoop] +
7311 + (InnerLoop * rx_ring->Fbr0BufferSize) + Fbr0Offset;
7312 +
7313 + rx_ring->Fbr[0]->PAHigh[index] =
7314 + (uint32_t) (Fbr0TempPa >> 32);
7315 + rx_ring->Fbr[0]->PALow[index] = (uint32_t) Fbr0TempPa;
7316 +
7317 + Fbr0TempPa += rx_ring->Fbr0BufferSize;
7318 +
7319 + rx_ring->Fbr[0]->Buffer1[index] =
7320 + rx_ring->Fbr[0]->Va[index];
7321 + rx_ring->Fbr[0]->Buffer2[index] =
7322 + rx_ring->Fbr[0]->Va[index] - 4;
7323 + }
7324 + }
7325 +#endif
7326 +
7327 + /* Allocate an area of memory for FIFO of Packet Status ring entries */
7328 + pktStatRingSize =
7329 + sizeof(PKT_STAT_DESC_t) * adapter->RxRing.PsrNumEntries;
7330 +
7331 + rx_ring->pPSRingVa = pci_alloc_consistent(adapter->pdev,
7332 + pktStatRingSize + 0x0fff,
7333 + &rx_ring->pPSRingPa);
7334 +
7335 + if (!rx_ring->pPSRingVa) {
7336 + DBG_ERROR(et131x_dbginfo,
7337 + "Cannot alloc memory for Packet Status Ring\n");
7338 + DBG_LEAVE(et131x_dbginfo);
7339 + return -ENOMEM;
7340 + }
7341 +
7342 + /* Save physical address
7343 + *
7344 + * NOTE : pci_alloc_consistent(), used above to alloc DMA regions,
7345 + * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
7346 + * are ever returned, make sure the high part is retrieved here before
7347 + * storing the adjusted address.
7348 + */
7349 + rx_ring->pPSRingRealPa = rx_ring->pPSRingPa;
7350 +
7351 + /* Align Packet Status Ring on a 4K boundary */
7352 + et131x_align_allocated_memory(adapter,
7353 + &rx_ring->pPSRingRealPa,
7354 + &rx_ring->pPSRingOffset, 0x0FFF);
7355 +
7356 + rx_ring->pPSRingVa = (void *)((uint8_t *) rx_ring->pPSRingVa +
7357 + rx_ring->pPSRingOffset);
7358 +
7359 + /* Allocate an area of memory for writeback of status information */
7360 + rx_ring->pRxStatusVa = pci_alloc_consistent(adapter->pdev,
7361 + sizeof(RX_STATUS_BLOCK_t) +
7362 + 0x7, &rx_ring->pRxStatusPa);
7363 + if (!rx_ring->pRxStatusVa) {
7364 + DBG_ERROR(et131x_dbginfo,
7365 + "Cannot alloc memory for Status Block\n");
7366 + DBG_LEAVE(et131x_dbginfo);
7367 + return -ENOMEM;
7368 + }
7369 +
7370 + /* Save physical address */
7371 + rx_ring->RxStatusRealPA = rx_ring->pRxStatusPa;
7372 +
7373 + /* Align write back on an 8 byte boundary */
7374 + et131x_align_allocated_memory(adapter,
7375 + &rx_ring->RxStatusRealPA,
7376 + &rx_ring->RxStatusOffset, 0x07);
7377 +
7378 + rx_ring->pRxStatusVa = (void *)((uint8_t *) rx_ring->pRxStatusVa +
7379 + rx_ring->RxStatusOffset);
7380 + rx_ring->NumRfd = NIC_DEFAULT_NUM_RFD;
7381 +
7382 + /* Recv
7383 + * pci_pool_create initializes a lookaside list. After successful
7384 + * creation, nonpaged fixed-size blocks can be allocated from and
7385 + * freed to the lookaside list.
7386 + * RFDs will be allocated from this pool.
7387 + */
7388 + rx_ring->RecvLookaside = kmem_cache_create(adapter->netdev->name,
7389 + sizeof(MP_RFD),
7390 + 0,
7391 + SLAB_CACHE_DMA |
7392 + SLAB_HWCACHE_ALIGN,
7393 + NULL);
7394 +
7395 + MP_SET_FLAG(adapter, fMP_ADAPTER_RECV_LOOKASIDE);
7396 +
7397 + /* The RFDs are going to be put on lists later on, so initialize the
7398 + * lists now.
7399 + */
7400 + INIT_LIST_HEAD(&rx_ring->RecvList);
7401 + INIT_LIST_HEAD(&rx_ring->RecvPendingList);
7402 +
7403 + DBG_LEAVE(et131x_dbginfo);
7404 + return 0;
7405 +}
7406 +
7407 +/**
7408 + * et131x_rx_dma_memory_free - Free all memory allocated within this module.
7409 + * @adapter: pointer to our private adapter structure
7410 + */
7411 +void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
7412 +{
7413 + uint32_t index;
7414 + uint32_t bufsize;
7415 + uint32_t pktStatRingSize;
7416 + PMP_RFD pMpRfd;
7417 + RX_RING_t *rx_ring;
7418 +
7419 + DBG_ENTER(et131x_dbginfo);
7420 +
7421 + /* Setup some convenience pointers */
7422 + rx_ring = (RX_RING_t *) & adapter->RxRing;
7423 +
7424 + /* Free RFDs and associated packet descriptors */
7425 + DBG_ASSERT(rx_ring->nReadyRecv == rx_ring->NumRfd);
7426 +
7427 + while (!list_empty(&rx_ring->RecvList)) {
7428 + pMpRfd = (MP_RFD *) list_entry(rx_ring->RecvList.next,
7429 + MP_RFD, list_node);
7430 +
7431 + list_del(&pMpRfd->list_node);
7432 + et131x_rfd_resources_free(adapter, pMpRfd);
7433 + }
7434 +
7435 + while (!list_empty(&rx_ring->RecvPendingList)) {
7436 + pMpRfd = (MP_RFD *) list_entry(rx_ring->RecvPendingList.next,
7437 + MP_RFD, list_node);
7438 + list_del(&pMpRfd->list_node);
7439 + et131x_rfd_resources_free(adapter, pMpRfd);
7440 + }
7441 +
7442 + /* Free Free Buffer Ring 1 */
7443 + if (rx_ring->pFbr1RingVa) {
7444 + /* First the packet memory */
7445 + for (index = 0; index <
7446 + (rx_ring->Fbr1NumEntries / FBR_CHUNKS); index++) {
7447 + if (rx_ring->Fbr1MemVa[index]) {
7448 + uint32_t Fbr1Align;
7449 +
7450 + if (rx_ring->Fbr1BufferSize > 4096) {
7451 + Fbr1Align = 4096;
7452 + } else {
7453 + Fbr1Align = rx_ring->Fbr1BufferSize;
7454 + }
7455 +
7456 + bufsize =
7457 + (rx_ring->Fbr1BufferSize * FBR_CHUNKS) +
7458 + Fbr1Align - 1;
7459 +
7460 + pci_free_consistent(adapter->pdev,
7461 + bufsize,
7462 + rx_ring->Fbr1MemVa[index],
7463 + rx_ring->Fbr1MemPa[index]);
7464 +
7465 + rx_ring->Fbr1MemVa[index] = NULL;
7466 + }
7467 + }
7468 +
7469 + /* Now the FIFO itself */
7470 + rx_ring->pFbr1RingVa = (void *)((uint8_t *) rx_ring->pFbr1RingVa -
7471 + rx_ring->Fbr1offset);
7472 +
7473 + bufsize =
7474 + (sizeof(FBR_DESC_t) * rx_ring->Fbr1NumEntries) + 0xfff;
7475 +
7476 + pci_free_consistent(adapter->pdev,
7477 + bufsize,
7478 + rx_ring->pFbr1RingVa, rx_ring->pFbr1RingPa);
7479 +
7480 + rx_ring->pFbr1RingVa = NULL;
7481 + }
7482 +
7483 +#ifdef USE_FBR0
7484 + /* Now the same for Free Buffer Ring 0 */
7485 + if (rx_ring->pFbr0RingVa) {
7486 + /* First the packet memory */
7487 + for (index = 0; index <
7488 + (rx_ring->Fbr0NumEntries / FBR_CHUNKS); index++) {
7489 + if (rx_ring->Fbr0MemVa[index]) {
7490 + bufsize =
7491 + (rx_ring->Fbr0BufferSize *
7492 + (FBR_CHUNKS + 1)) - 1;
7493 +
7494 + pci_free_consistent(adapter->pdev,
7495 + bufsize,
7496 + rx_ring->Fbr0MemVa[index],
7497 + rx_ring->Fbr0MemPa[index]);
7498 +
7499 + rx_ring->Fbr0MemVa[index] = NULL;
7500 + }
7501 + }
7502 +
7503 + /* Now the FIFO itself */
7504 + rx_ring->pFbr0RingVa = (void *)((uint8_t *) rx_ring->pFbr0RingVa -
7505 + rx_ring->Fbr0offset);
7506 +
7507 + bufsize =
7508 + (sizeof(FBR_DESC_t) * rx_ring->Fbr0NumEntries) + 0xfff;
7509 +
7510 + pci_free_consistent(adapter->pdev,
7511 + bufsize,
7512 + rx_ring->pFbr0RingVa, rx_ring->pFbr0RingPa);
7513 +
7514 + rx_ring->pFbr0RingVa = NULL;
7515 + }
7516 +#endif
7517 +
7518 + /* Free Packet Status Ring */
7519 + if (rx_ring->pPSRingVa) {
7520 + rx_ring->pPSRingVa = (void *)((uint8_t *) rx_ring->pPSRingVa -
7521 + rx_ring->pPSRingOffset);
7522 +
7523 + pktStatRingSize =
7524 + sizeof(PKT_STAT_DESC_t) * adapter->RxRing.PsrNumEntries;
7525 +
7526 + pci_free_consistent(adapter->pdev,
7527 + pktStatRingSize + 0x0fff,
7528 + rx_ring->pPSRingVa, rx_ring->pPSRingPa);
7529 +
7530 + rx_ring->pPSRingVa = NULL;
7531 + }
7532 +
7533 + /* Free area of memory for the writeback of status information */
7534 + if (rx_ring->pRxStatusVa) {
7535 + rx_ring->pRxStatusVa = (void *)((uint8_t *) rx_ring->pRxStatusVa -
7536 + rx_ring->RxStatusOffset);
7537 +
7538 + pci_free_consistent(adapter->pdev,
7539 + sizeof(RX_STATUS_BLOCK_t) + 0x7,
7540 + rx_ring->pRxStatusVa, rx_ring->pRxStatusPa);
7541 +
7542 + rx_ring->pRxStatusVa = NULL;
7543 + }
7544 +
7545 + /* Free receive buffer pool */
7546 +
7547 + /* Free receive packet pool */
7548 +
7549 + /* Destroy the lookaside (RFD) pool */
7550 + if (MP_TEST_FLAG(adapter, fMP_ADAPTER_RECV_LOOKASIDE)) {
7551 + kmem_cache_destroy(rx_ring->RecvLookaside);
7552 + MP_CLEAR_FLAG(adapter, fMP_ADAPTER_RECV_LOOKASIDE);
7553 + }
7554 +
7555 + /* Free the FBR Lookup Table */
7556 +#ifdef USE_FBR0
7557 + kfree(rx_ring->Fbr[0]);
7558 +#endif
7559 +
7560 + kfree(rx_ring->Fbr[1]);
7561 +
7562 + /* Reset Counters */
7563 + rx_ring->nReadyRecv = 0;
7564 +
7565 + DBG_LEAVE(et131x_dbginfo);
7566 +}
7567 +
7568 +/**
7569 + * et131x_init_recv - Initialize receive data structures.
7570 + * @adapter: pointer to our private adapter structure
7571 + *
7572 + * Returns 0 on success and errno on failure (as defined in errno.h)
7573 + */
7574 +int et131x_init_recv(struct et131x_adapter *adapter)
7575 +{
7576 + int status = -ENOMEM;
7577 + PMP_RFD pMpRfd = NULL;
7578 + uint32_t RfdCount;
7579 + uint32_t TotalNumRfd = 0;
7580 + RX_RING_t *rx_ring = NULL;
7581 +
7582 + DBG_ENTER(et131x_dbginfo);
7583 +
7584 + /* Setup some convenience pointers */
7585 + rx_ring = (RX_RING_t *) & adapter->RxRing;
7586 +
7587 + /* Setup each RFD */
7588 + for (RfdCount = 0; RfdCount < rx_ring->NumRfd; RfdCount++) {
7589 + pMpRfd = (MP_RFD *) kmem_cache_alloc(rx_ring->RecvLookaside,
7590 + GFP_ATOMIC | GFP_DMA);
7591 +
7592 + if (!pMpRfd) {
7593 + DBG_ERROR(et131x_dbginfo,
7594 + "Couldn't alloc RFD out of kmem_cache\n");
7595 + status = -ENOMEM;
7596 + continue;
7597 + }
7598 +
7599 + status = et131x_rfd_resources_alloc(adapter, pMpRfd);
7600 + if (status != 0) {
7601 + DBG_ERROR(et131x_dbginfo,
7602 + "Couldn't alloc packet for RFD\n");
7603 + kmem_cache_free(rx_ring->RecvLookaside, pMpRfd);
7604 + continue;
7605 + }
7606 +
7607 + /* Add this RFD to the RecvList */
7608 + list_add_tail(&pMpRfd->list_node, &rx_ring->RecvList);
7609 +
7610 + /* Increment both the available RFD's, and the total RFD's. */
7611 + rx_ring->nReadyRecv++;
7612 + TotalNumRfd++;
7613 + }
7614 +
7615 + if (TotalNumRfd > NIC_MIN_NUM_RFD) {
7616 + status = 0;
7617 + }
7618 +
7619 + rx_ring->NumRfd = TotalNumRfd;
7620 +
7621 + if (status != 0) {
7622 + kmem_cache_free(rx_ring->RecvLookaside, pMpRfd);
7623 + DBG_ERROR(et131x_dbginfo,
7624 + "Allocation problems in et131x_init_recv\n");
7625 + }
7626 +
7627 + DBG_LEAVE(et131x_dbginfo);
7628 + return status;
7629 +}
7630 +
7631 +/**
7632 + * et131x_rfd_resources_alloc
7633 + * @adapter: pointer to our private adapter structure
7634 + * @pMpRfd: pointer to a RFD
7635 + *
7636 + * Returns 0 on success and errno on failure (as defined in errno.h)
7637 + */
7638 +int et131x_rfd_resources_alloc(struct et131x_adapter *adapter, MP_RFD *pMpRfd)
7639 +{
7640 + pMpRfd->Packet = NULL;
7641 +
7642 + return 0;
7643 +}
7644 +
7645 +/**
7646 + * et131x_rfd_resources_free - Free the packet allocated for the given RFD
7647 + * @adapter: pointer to our private adapter structure
7648 + * @pMpRfd: pointer to a RFD
7649 + */
7650 +void et131x_rfd_resources_free(struct et131x_adapter *adapter, MP_RFD *pMpRfd)
7651 +{
7652 + pMpRfd->Packet = NULL;
7653 + kmem_cache_free(adapter->RxRing.RecvLookaside, pMpRfd);
7654 +}
7655 +
7656 +/**
7657 + * ConfigRxDmaRegs - Start of Rx_DMA init sequence
7658 + * @pAdapter: pointer to our adapter structure
7659 + */
7660 +void ConfigRxDmaRegs(struct et131x_adapter *pAdapter)
7661 +{
7662 + struct _RXDMA_t __iomem *pRxDma = &pAdapter->CSRAddress->rxdma;
7663 + struct _rx_ring_t *pRxLocal = &pAdapter->RxRing;
7664 + PFBR_DESC_t pFbrEntry;
7665 + uint32_t iEntry;
7666 + RXDMA_PSR_NUM_DES_t psr_num_des;
7667 + unsigned long lockflags;
7668 +
7669 + DBG_ENTER(et131x_dbginfo);
7670 +
7671 + /* Halt RXDMA to perform the reconfigure. */
7672 + et131x_rx_dma_disable(pAdapter);
7673 +
7674 + /* Load the completion writeback physical address
7675 + *
7676 + * NOTE : pci_alloc_consistent(), used above to alloc DMA regions,
7677 + * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
7678 + * are ever returned, make sure the high part is retrieved here
7679 + * before storing the adjusted address.
7680 + */
7681 + writel((uint32_t) (pRxLocal->RxStatusRealPA >> 32),
7682 + &pRxDma->dma_wb_base_hi);
7683 + writel((uint32_t) pRxLocal->RxStatusRealPA, &pRxDma->dma_wb_base_lo);
7684 +
7685 + memset(pRxLocal->pRxStatusVa, 0, sizeof(RX_STATUS_BLOCK_t));
7686 +
7687 + /* Set the address and parameters of the packet status ring into the
7688 + * 1310's registers
7689 + */
7690 + writel((uint32_t) (pRxLocal->pPSRingRealPa >> 32),
7691 + &pRxDma->psr_base_hi);
7692 + writel((uint32_t) pRxLocal->pPSRingRealPa, &pRxDma->psr_base_lo);
7693 + writel(pRxLocal->PsrNumEntries - 1, &pRxDma->psr_num_des.value);
7694 + writel(0, &pRxDma->psr_full_offset.value);
7695 +
7696 + psr_num_des.value = readl(&pRxDma->psr_num_des.value);
7697 + writel((psr_num_des.bits.psr_ndes * LO_MARK_PERCENT_FOR_PSR) / 100,
7698 + &pRxDma->psr_min_des.value);
7699 +
7700 + spin_lock_irqsave(&pAdapter->RcvLock, lockflags);
7701 +
7702 + /* These local variables track the PSR in the adapter structure */
7703 + pRxLocal->local_psr_full.bits.psr_full = 0;
7704 + pRxLocal->local_psr_full.bits.psr_full_wrap = 0;
7705 +
7706 + /* Now's the best time to initialize FBR1 contents */
7707 + pFbrEntry = (PFBR_DESC_t) pRxLocal->pFbr1RingVa;
7708 + for (iEntry = 0; iEntry < pRxLocal->Fbr1NumEntries; iEntry++) {
7709 + pFbrEntry->addr_hi = pRxLocal->Fbr[1]->PAHigh[iEntry];
7710 + pFbrEntry->addr_lo = pRxLocal->Fbr[1]->PALow[iEntry];
7711 + pFbrEntry->word2.bits.bi = iEntry;
7712 + pFbrEntry++;
7713 + }
7714 +
7715 + /* Set the address and parameters of Free buffer ring 1 (and 0 if
7716 + * required) into the 1310's registers
7717 + */
7718 + writel((uint32_t) (pRxLocal->Fbr1Realpa >> 32), &pRxDma->fbr1_base_hi);
7719 + writel((uint32_t) pRxLocal->Fbr1Realpa, &pRxDma->fbr1_base_lo);
7720 + writel(pRxLocal->Fbr1NumEntries - 1, &pRxDma->fbr1_num_des.value);
7721 +
7722 + {
7723 + DMA10W_t fbr1_full = { 0 };
7724 +
7725 + fbr1_full.bits.val = 0;
7726 + fbr1_full.bits.wrap = 1;
7727 + writel(fbr1_full.value, &pRxDma->fbr1_full_offset.value);
7728 + }
7729 +
7730 + /* This variable tracks the free buffer ring 1 full position, so it
7731 + * has to match the above.
7732 + */
7733 + pRxLocal->local_Fbr1_full.bits.val = 0;
7734 + pRxLocal->local_Fbr1_full.bits.wrap = 1;
7735 + writel(((pRxLocal->Fbr1NumEntries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
7736 + &pRxDma->fbr1_min_des.value);
7737 +
7738 +#ifdef USE_FBR0
7739 + /* Now's the best time to initialize FBR0 contents */
7740 + pFbrEntry = (PFBR_DESC_t) pRxLocal->pFbr0RingVa;
7741 + for (iEntry = 0; iEntry < pRxLocal->Fbr0NumEntries; iEntry++) {
7742 + pFbrEntry->addr_hi = pRxLocal->Fbr[0]->PAHigh[iEntry];
7743 + pFbrEntry->addr_lo = pRxLocal->Fbr[0]->PALow[iEntry];
7744 + pFbrEntry->word2.bits.bi = iEntry;
7745 + pFbrEntry++;
7746 + }
7747 +
7748 + writel((uint32_t) (pRxLocal->Fbr0Realpa >> 32), &pRxDma->fbr0_base_hi);
7749 + writel((uint32_t) pRxLocal->Fbr0Realpa, &pRxDma->fbr0_base_lo);
7750 + writel(pRxLocal->Fbr0NumEntries - 1, &pRxDma->fbr0_num_des.value);
7751 +
7752 + {
7753 + DMA10W_t fbr0_full = { 0 };
7754 +
7755 + fbr0_full.bits.val = 0;
7756 + fbr0_full.bits.wrap = 1;
7757 + writel(fbr0_full.value, &pRxDma->fbr0_full_offset.value);
7758 + }
7759 +
7760 + /* This variable tracks the free buffer ring 0 full position, so it
7761 + * has to match the above.
7762 + */
7763 + pRxLocal->local_Fbr0_full.bits.val = 0;
7764 + pRxLocal->local_Fbr0_full.bits.wrap = 1;
7765 + writel(((pRxLocal->Fbr0NumEntries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
7766 + &pRxDma->fbr0_min_des.value);
7767 +#endif
7768 +
7769 + /* Program the number of packets we will receive before generating an
7770 + * interrupt.
7771 + * For version B silicon, this value gets updated once autoneg is
7772 + *complete.
7773 + */
7774 + writel(pAdapter->RegistryRxNumBuffers, &pRxDma->num_pkt_done.value);
7775 +
7776 + /* The "time_done" is not working correctly to coalesce interrupts
7777 + * after a given time period, but rather is giving us an interrupt
7778 + * regardless of whether we have received packets.
7779 + * This value gets updated once autoneg is complete.
7780 + */
7781 + writel(pAdapter->RegistryRxTimeInterval, &pRxDma->max_pkt_time.value);
7782 +
7783 + spin_unlock_irqrestore(&pAdapter->RcvLock, lockflags);
7784 +
7785 + DBG_LEAVE(et131x_dbginfo);
7786 +}
7787 +
7788 +/**
7789 + * SetRxDmaTimer - Set the heartbeat timer according to line rate.
7790 + * @pAdapter: pointer to our adapter structure
7791 + */
7792 +void SetRxDmaTimer(struct et131x_adapter *pAdapter)
7793 +{
7794 + /* For version B silicon, we do not use the RxDMA timer for 10 and 100
7795 + * Mbits/s line rates. We do not enable and RxDMA interrupt coalescing.
7796 + */
7797 + if ((pAdapter->uiLinkSpeed == TRUEPHY_SPEED_100MBPS) ||
7798 + (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_10MBPS)) {
7799 + writel(0, &pAdapter->CSRAddress->rxdma.max_pkt_time.value);
7800 + writel(1, &pAdapter->CSRAddress->rxdma.num_pkt_done.value);
7801 + }
7802 +}
7803 +
7804 +/**
7805 + * et131x_rx_dma_disable - Stop of Rx_DMA on the ET1310
7806 + * @pAdapter: pointer to our adapter structure
7807 + */
7808 +void et131x_rx_dma_disable(struct et131x_adapter *pAdapter)
7809 +{
7810 + RXDMA_CSR_t csr;
7811 +
7812 + DBG_ENTER(et131x_dbginfo);
7813 +
7814 + /* Setup the receive dma configuration register */
7815 + writel(0x00002001, &pAdapter->CSRAddress->rxdma.csr.value);
7816 + csr.value = readl(&pAdapter->CSRAddress->rxdma.csr.value);
7817 + if (csr.bits.halt_status != 1) {
7818 + udelay(5);
7819 + csr.value = readl(&pAdapter->CSRAddress->rxdma.csr.value);
7820 + if (csr.bits.halt_status != 1) {
7821 + DBG_ERROR(et131x_dbginfo,
7822 + "RX Dma failed to enter halt state. CSR 0x%08x\n",
7823 + csr.value);
7824 + }
7825 + }
7826 +
7827 + DBG_LEAVE(et131x_dbginfo);
7828 +}
7829 +
7830 +/**
7831 + * et131x_rx_dma_enable - re-start of Rx_DMA on the ET1310.
7832 + * @pAdapter: pointer to our adapter structure
7833 + */
7834 +void et131x_rx_dma_enable(struct et131x_adapter *pAdapter)
7835 +{
7836 + DBG_RX_ENTER(et131x_dbginfo);
7837 +
7838 + if (pAdapter->RegistryPhyLoopbk) {
7839 + /* RxDMA is disabled for loopback operation. */
7840 + writel(0x1, &pAdapter->CSRAddress->rxdma.csr.value);
7841 + } else {
7842 + /* Setup the receive dma configuration register for normal operation */
7843 + RXDMA_CSR_t csr = { 0 };
7844 +
7845 + csr.bits.fbr1_enable = 1;
7846 + if (pAdapter->RxRing.Fbr1BufferSize == 4096) {
7847 + csr.bits.fbr1_size = 1;
7848 + } else if (pAdapter->RxRing.Fbr1BufferSize == 8192) {
7849 + csr.bits.fbr1_size = 2;
7850 + } else if (pAdapter->RxRing.Fbr1BufferSize == 16384) {
7851 + csr.bits.fbr1_size = 3;
7852 + }
7853 +#ifdef USE_FBR0
7854 + csr.bits.fbr0_enable = 1;
7855 + if (pAdapter->RxRing.Fbr0BufferSize == 256) {
7856 + csr.bits.fbr0_size = 1;
7857 + } else if (pAdapter->RxRing.Fbr0BufferSize == 512) {
7858 + csr.bits.fbr0_size = 2;
7859 + } else if (pAdapter->RxRing.Fbr0BufferSize == 1024) {
7860 + csr.bits.fbr0_size = 3;
7861 + }
7862 +#endif
7863 + writel(csr.value, &pAdapter->CSRAddress->rxdma.csr.value);
7864 +
7865 + csr.value = readl(&pAdapter->CSRAddress->rxdma.csr.value);
7866 + if (csr.bits.halt_status != 0) {
7867 + udelay(5);
7868 + csr.value = readl(&pAdapter->CSRAddress->rxdma.csr.value);
7869 + if (csr.bits.halt_status != 0) {
7870 + DBG_ERROR(et131x_dbginfo,
7871 + "RX Dma failed to exit halt state. CSR 0x%08x\n",
7872 + csr.value);
7873 + }
7874 + }
7875 + }
7876 +
7877 + DBG_RX_LEAVE(et131x_dbginfo);
7878 +}
7879 +
7880 +/**
7881 + * nic_rx_pkts - Checks the hardware for available packets
7882 + * @pAdapter: pointer to our adapter
7883 + *
7884 + * Returns pMpRfd, a pointer to our MPRFD.
7885 + *
7886 + * Checks the hardware for available packets, using completion ring
7887 + * If packets are available, it gets an RFD from the RecvList, attaches
7888 + * the packet to it, puts the RFD in the RecvPendList, and also returns
7889 + * the pointer to the RFD.
7890 + */
7891 +PMP_RFD nic_rx_pkts(struct et131x_adapter *pAdapter)
7892 +{
7893 + struct _rx_ring_t *pRxLocal = &pAdapter->RxRing;
7894 + PRX_STATUS_BLOCK_t pRxStatusBlock;
7895 + PPKT_STAT_DESC_t pPSREntry;
7896 + PMP_RFD pMpRfd;
7897 + uint32_t nIndex;
7898 + uint8_t *pBufVa;
7899 + unsigned long lockflags;
7900 + struct list_head *element;
7901 + uint8_t ringIndex;
7902 + uint16_t bufferIndex;
7903 + uint32_t localLen;
7904 + PKT_STAT_DESC_WORD0_t Word0;
7905 +
7906 +
7907 + DBG_RX_ENTER(et131x_dbginfo);
7908 +
7909 + /* RX Status block is written by the DMA engine prior to every
7910 + * interrupt. It contains the next to be used entry in the Packet
7911 + * Status Ring, and also the two Free Buffer rings.
7912 + */
7913 + pRxStatusBlock = (PRX_STATUS_BLOCK_t) pRxLocal->pRxStatusVa;
7914 +
7915 + if (pRxStatusBlock->Word1.bits.PSRoffset ==
7916 + pRxLocal->local_psr_full.bits.psr_full &&
7917 + pRxStatusBlock->Word1.bits.PSRwrap ==
7918 + pRxLocal->local_psr_full.bits.psr_full_wrap) {
7919 + /* Looks like this ring is not updated yet */
7920 + DBG_RX(et131x_dbginfo, "(0)\n");
7921 + DBG_RX_LEAVE(et131x_dbginfo);
7922 + return NULL;
7923 + }
7924 +
7925 + /* The packet status ring indicates that data is available. */
7926 + pPSREntry = (PPKT_STAT_DESC_t) (pRxLocal->pPSRingVa) +
7927 + pRxLocal->local_psr_full.bits.psr_full;
7928 +
7929 + /* Grab any information that is required once the PSR is
7930 + * advanced, since we can no longer rely on the memory being
7931 + * accurate
7932 + */
7933 + localLen = pPSREntry->word1.bits.length;
7934 + ringIndex = (uint8_t) pPSREntry->word1.bits.ri;
7935 + bufferIndex = (uint16_t) pPSREntry->word1.bits.bi;
7936 + Word0 = pPSREntry->word0;
7937 +
7938 + DBG_RX(et131x_dbginfo, "RX PACKET STATUS\n");
7939 + DBG_RX(et131x_dbginfo, "\tlength : %d\n", localLen);
7940 + DBG_RX(et131x_dbginfo, "\tringIndex : %d\n", ringIndex);
7941 + DBG_RX(et131x_dbginfo, "\tbufferIndex : %d\n", bufferIndex);
7942 + DBG_RX(et131x_dbginfo, "\tword0 : 0x%08x\n", Word0.value);
7943 +
7944 +#if 0
7945 + /* Check the Status Word that the MAC has appended to the PSR
7946 + * entry in case the MAC has detected errors.
7947 + */
7948 + if (Word0.value & ALCATEL_BAD_STATUS) {
7949 + DBG_ERROR(et131x_dbginfo,
7950 + "NICRxPkts >> Alcatel Status Word error."
7951 + "Value 0x%08x\n", pPSREntry->word0.value);
7952 + }
7953 +#endif
7954 +
7955 + /* Indicate that we have used this PSR entry. */
7956 + if (++pRxLocal->local_psr_full.bits.psr_full >
7957 + pRxLocal->PsrNumEntries - 1) {
7958 + pRxLocal->local_psr_full.bits.psr_full = 0;
7959 + pRxLocal->local_psr_full.bits.psr_full_wrap ^= 1;
7960 + }
7961 +
7962 + writel(pRxLocal->local_psr_full.value,
7963 + &pAdapter->CSRAddress->rxdma.psr_full_offset.value);
7964 +
7965 +#ifndef USE_FBR0
7966 + if (ringIndex != 1) {
7967 + DBG_ERROR(et131x_dbginfo,
7968 + "NICRxPkts PSR Entry %d indicates "
7969 + "Buffer Ring 0 in use\n",
7970 + pRxLocal->local_psr_full.bits.psr_full);
7971 + DBG_RX_LEAVE(et131x_dbginfo);
7972 + return NULL;
7973 + }
7974 +#endif
7975 +
7976 +#ifdef USE_FBR0
7977 + if (ringIndex > 1 ||
7978 + (ringIndex == 0 &&
7979 + bufferIndex > pRxLocal->Fbr0NumEntries - 1) ||
7980 + (ringIndex == 1 &&
7981 + bufferIndex > pRxLocal->Fbr1NumEntries - 1))
7982 +#else
7983 + if (ringIndex != 1 ||
7984 + bufferIndex > pRxLocal->Fbr1NumEntries - 1)
7985 +#endif
7986 + {
7987 + /* Illegal buffer or ring index cannot be used by S/W*/
7988 + DBG_ERROR(et131x_dbginfo,
7989 + "NICRxPkts PSR Entry %d indicates "
7990 + "length of %d and/or bad bi(%d)\n",
7991 + pRxLocal->local_psr_full.bits.psr_full,
7992 + localLen, bufferIndex);
7993 + DBG_RX_LEAVE(et131x_dbginfo);
7994 + return NULL;
7995 + }
7996 +
7997 + /* Get and fill the RFD. */
7998 + spin_lock_irqsave(&pAdapter->RcvLock, lockflags);
7999 +
8000 + pMpRfd = NULL;
8001 + element = pRxLocal->RecvList.next;
8002 + pMpRfd = (PMP_RFD) list_entry(element, MP_RFD, list_node);
8003 +
8004 + if (pMpRfd == NULL) {
8005 + DBG_RX(et131x_dbginfo,
8006 + "NULL RFD returned from RecvList via list_entry()\n");
8007 + DBG_RX_LEAVE(et131x_dbginfo);
8008 + spin_unlock_irqrestore(&pAdapter->RcvLock, lockflags);
8009 + return NULL;
8010 + }
8011 +
8012 + list_del(&pMpRfd->list_node);
8013 + pRxLocal->nReadyRecv--;
8014 +
8015 + spin_unlock_irqrestore(&pAdapter->RcvLock, lockflags);
8016 +
8017 + pMpRfd->iBufferIndex = bufferIndex;
8018 + pMpRfd->iRingIndex = ringIndex;
8019 +
8020 + /* In V1 silicon, there is a bug which screws up filtering of
8021 + * runt packets. Therefore runt packet filtering is disabled
8022 + * in the MAC and the packets are dropped here. They are
8023 + * also counted here.
8024 + */
8025 + if (localLen < (NIC_MIN_PACKET_SIZE + 4)) {
8026 + pAdapter->Stats.other_errors++;
8027 + localLen = 0;
8028 + }
8029 +
8030 + if (localLen) {
8031 + if (pAdapter->ReplicaPhyLoopbk == 1) {
8032 + pBufVa = pRxLocal->Fbr[ringIndex]->Va[bufferIndex];
8033 +
8034 + if (memcmp(&pBufVa[6], &pAdapter->CurrentAddress[0],
8035 + ETH_ALEN) == 0) {
8036 + if (memcmp(&pBufVa[42], "Replica packet",
8037 + ETH_HLEN)) {
8038 + pAdapter->ReplicaPhyLoopbkPF = 1;
8039 + }
8040 + }
8041 + DBG_WARNING(et131x_dbginfo,
8042 + "pBufVa:\t%02x:%02x:%02x:%02x:%02x:%02x\n",
8043 + pBufVa[6], pBufVa[7], pBufVa[8],
8044 + pBufVa[9], pBufVa[10], pBufVa[11]);
8045 +
8046 + DBG_WARNING(et131x_dbginfo,
8047 + "CurrentAddr:\t%02x:%02x:%02x:%02x:%02x:%02x\n",
8048 + pAdapter->CurrentAddress[0],
8049 + pAdapter->CurrentAddress[1],
8050 + pAdapter->CurrentAddress[2],
8051 + pAdapter->CurrentAddress[3],
8052 + pAdapter->CurrentAddress[4],
8053 + pAdapter->CurrentAddress[5]);
8054 + }
8055 +
8056 + /* Determine if this is a multicast packet coming in */
8057 + if ((Word0.value & ALCATEL_MULTICAST_PKT) &&
8058 + !(Word0.value & ALCATEL_BROADCAST_PKT)) {
8059 + /* Promiscuous mode and Multicast mode are
8060 + * not mutually exclusive as was first
8061 + * thought. I guess Promiscuous is just
8062 + * considered a super-set of the other
8063 + * filters. Generally filter is 0x2b when in
8064 + * promiscuous mode.
8065 + */
8066 + if ((pAdapter->PacketFilter & ET131X_PACKET_TYPE_MULTICAST)
8067 + && !(pAdapter->PacketFilter & ET131X_PACKET_TYPE_PROMISCUOUS)
8068 + && !(pAdapter->PacketFilter & ET131X_PACKET_TYPE_ALL_MULTICAST)) {
8069 + pBufVa = pRxLocal->Fbr[ringIndex]->
8070 + Va[bufferIndex];
8071 +
8072 + /* Loop through our list to see if the
8073 + * destination address of this packet
8074 + * matches one in our list.
8075 + */
8076 + for (nIndex = 0;
8077 + nIndex < pAdapter->MCAddressCount;
8078 + nIndex++) {
8079 + if (pBufVa[0] ==
8080 + pAdapter->MCList[nIndex][0]
8081 + && pBufVa[1] ==
8082 + pAdapter->MCList[nIndex][1]
8083 + && pBufVa[2] ==
8084 + pAdapter->MCList[nIndex][2]
8085 + && pBufVa[3] ==
8086 + pAdapter->MCList[nIndex][3]
8087 + && pBufVa[4] ==
8088 + pAdapter->MCList[nIndex][4]
8089 + && pBufVa[5] ==
8090 + pAdapter->MCList[nIndex][5]) {
8091 + break;
8092 + }
8093 + }
8094 +
8095 + /* If our index is equal to the number
8096 + * of Multicast address we have, then
8097 + * this means we did not find this
8098 + * packet's matching address in our
8099 + * list. Set the PacketSize to zero,
8100 + * so we free our RFD when we return
8101 + * from this function.
8102 + */
8103 + if (nIndex == pAdapter->MCAddressCount) {
8104 + localLen = 0;
8105 + }
8106 + }
8107 +
8108 + if (localLen > 0) {
8109 + pAdapter->Stats.multircv++;
8110 + }
8111 + } else if (Word0.value & ALCATEL_BROADCAST_PKT) {
8112 + pAdapter->Stats.brdcstrcv++;
8113 + } else {
8114 + /* Not sure what this counter measures in
8115 + * promiscuous mode. Perhaps we should check
8116 + * the MAC address to see if it is directed
8117 + * to us in promiscuous mode.
8118 + */
8119 + pAdapter->Stats.unircv++;
8120 + }
8121 + }
8122 +
8123 + if (localLen > 0) {
8124 + struct sk_buff *skb = NULL;
8125 +
8126 + //pMpRfd->PacketSize = localLen - 4;
8127 + pMpRfd->PacketSize = localLen;
8128 +
8129 + skb = dev_alloc_skb(pMpRfd->PacketSize + 2);
8130 + if (!skb) {
8131 + DBG_ERROR(et131x_dbginfo,
8132 + "Couldn't alloc an SKB for Rx\n");
8133 + DBG_RX_LEAVE(et131x_dbginfo);
8134 + return NULL;
8135 + }
8136 +
8137 + pAdapter->net_stats.rx_bytes += pMpRfd->PacketSize;
8138 +
8139 + memcpy(skb_put(skb, pMpRfd->PacketSize),
8140 + pRxLocal->Fbr[ringIndex]->Va[bufferIndex],
8141 + pMpRfd->PacketSize);
8142 +
8143 + skb->dev = pAdapter->netdev;
8144 + skb->protocol = eth_type_trans(skb, pAdapter->netdev);
8145 + skb->ip_summed = CHECKSUM_NONE;
8146 +
8147 + netif_rx(skb);
8148 + } else {
8149 + pMpRfd->PacketSize = 0;
8150 + }
8151 +
8152 + nic_return_rfd(pAdapter, pMpRfd);
8153 +
8154 + DBG_RX(et131x_dbginfo, "(1)\n");
8155 + DBG_RX_LEAVE(et131x_dbginfo);
8156 + return pMpRfd;
8157 +}
8158 +
8159 +/**
8160 + * et131x_reset_recv - Reset the receive list
8161 + * @pAdapter: pointer to our adapter
8162 + *
8163 + * Assumption, Rcv spinlock has been acquired.
8164 + */
8165 +void et131x_reset_recv(struct et131x_adapter *pAdapter)
8166 +{
8167 + PMP_RFD pMpRfd;
8168 + struct list_head *element;
8169 +
8170 + DBG_ENTER(et131x_dbginfo);
8171 +
8172 + DBG_ASSERT(!list_empty(&pAdapter->RxRing.RecvList));
8173 +
8174 + /* Take all the RFD's from the pending list, and stick them on the
8175 + * RecvList.
8176 + */
8177 + while (!list_empty(&pAdapter->RxRing.RecvPendingList)) {
8178 + element = pAdapter->RxRing.RecvPendingList.next;
8179 +
8180 + pMpRfd = (PMP_RFD) list_entry(element, MP_RFD, list_node);
8181 +
8182 + list_del(&pMpRfd->list_node);
8183 + list_add_tail(&pMpRfd->list_node, &pAdapter->RxRing.RecvList);
8184 + }
8185 +
8186 + DBG_LEAVE(et131x_dbginfo);
8187 +}
8188 +
8189 +/**
8190 + * et131x_handle_recv_interrupt - Interrupt handler for receive processing
8191 + * @pAdapter: pointer to our adapter
8192 + *
8193 + * Assumption, Rcv spinlock has been acquired.
8194 + */
8195 +void et131x_handle_recv_interrupt(struct et131x_adapter *pAdapter)
8196 +{
8197 + PMP_RFD pMpRfd = NULL;
8198 + struct sk_buff *PacketArray[NUM_PACKETS_HANDLED];
8199 + PMP_RFD RFDFreeArray[NUM_PACKETS_HANDLED];
8200 + uint32_t PacketArrayCount = 0;
8201 + uint32_t PacketsToHandle;
8202 + uint32_t PacketFreeCount = 0;
8203 + bool TempUnfinishedRec = false;
8204 +
8205 + DBG_RX_ENTER(et131x_dbginfo);
8206 +
8207 + PacketsToHandle = NUM_PACKETS_HANDLED;
8208 +
8209 + /* Process up to available RFD's */
8210 + while (PacketArrayCount < PacketsToHandle) {
8211 + if (list_empty(&pAdapter->RxRing.RecvList)) {
8212 + DBG_ASSERT(pAdapter->RxRing.nReadyRecv == 0);
8213 + DBG_ERROR(et131x_dbginfo, "NO RFD's !!!!!!!!!!!!!\n");
8214 + TempUnfinishedRec = true;
8215 + break;
8216 + }
8217 +
8218 + pMpRfd = nic_rx_pkts(pAdapter);
8219 +
8220 + if (pMpRfd == NULL) {
8221 + break;
8222 + }
8223 +
8224 + /* Do not receive any packets until a filter has been set.
8225 + * Do not receive any packets until we are at D0.
8226 + * Do not receive any packets until we have link.
8227 + * If length is zero, return the RFD in order to advance the
8228 + * Free buffer ring.
8229 + */
8230 + if ((!pAdapter->PacketFilter) ||
8231 + (pAdapter->PoMgmt.PowerState != NdisDeviceStateD0) ||
8232 + (!MP_LINK_DETECTED(pAdapter)) ||
8233 + (pMpRfd->PacketSize == 0)) {
8234 + continue;
8235 + }
8236 +
8237 + /* Increment the number of packets we received */
8238 + pAdapter->Stats.ipackets++;
8239 +
8240 + /* Set the status on the packet, either resources or success */
8241 + if (pAdapter->RxRing.nReadyRecv >= RFD_LOW_WATER_MARK) {
8242 + /* Put this RFD on the pending list
8243 + *
8244 + * NOTE: nic_rx_pkts() above is already returning the
8245 + * RFD to the RecvList, so don't additionally do that
8246 + * here.
8247 + * Besides, we don't really need (at this point) the
8248 + * pending list anyway.
8249 + */
8250 + //spin_lock_irqsave( &pAdapter->RcvPendLock, lockflags );
8251 + //list_add_tail( &pMpRfd->list_node, &pAdapter->RxRing.RecvPendingList );
8252 + //spin_unlock_irqrestore( &pAdapter->RcvPendLock, lockflags );
8253 +
8254 + /* Update the number of outstanding Recvs */
8255 + //MP_INC_RCV_REF( pAdapter );
8256 + } else {
8257 + RFDFreeArray[PacketFreeCount] = pMpRfd;
8258 + PacketFreeCount++;
8259 +
8260 + DBG_WARNING(et131x_dbginfo,
8261 + "RFD's are running out !!!!!!!!!!!!!\n");
8262 + }
8263 +
8264 + PacketArray[PacketArrayCount] = pMpRfd->Packet;
8265 + PacketArrayCount++;
8266 + }
8267 +
8268 + if ((PacketArrayCount == NUM_PACKETS_HANDLED) || TempUnfinishedRec) {
8269 + pAdapter->RxRing.UnfinishedReceives = true;
8270 + writel(pAdapter->RegistryTxTimeInterval * NANO_IN_A_MICRO,
8271 + &pAdapter->CSRAddress->global.watchdog_timer);
8272 + } else {
8273 + /* Watchdog timer will disable itself if appropriate. */
8274 + pAdapter->RxRing.UnfinishedReceives = false;
8275 + }
8276 +
8277 + DBG_RX_LEAVE(et131x_dbginfo);
8278 +}
8279 +
8280 +/**
8281 + * NICReturnRFD - Recycle a RFD and put it back onto the receive list
8282 + * @pAdapter: pointer to our adapter
8283 + * @pMpRfd: pointer to the RFD
8284 + */
8285 +void nic_return_rfd(struct et131x_adapter *pAdapter, PMP_RFD pMpRfd)
8286 +{
8287 + struct _rx_ring_t *pRxLocal = &pAdapter->RxRing;
8288 + struct _RXDMA_t __iomem *pRxDma = &pAdapter->CSRAddress->rxdma;
8289 + uint16_t bi = pMpRfd->iBufferIndex;
8290 + uint8_t ri = pMpRfd->iRingIndex;
8291 + unsigned long lockflags;
8292 +
8293 + DBG_RX_ENTER(et131x_dbginfo);
8294 +
8295 + /* We don't use any of the OOB data besides status. Otherwise, we
8296 + * need to clean up OOB data
8297 + */
8298 + if (
8299 +#ifdef USE_FBR0
8300 + (ri == 0 && bi < pRxLocal->Fbr0NumEntries) ||
8301 +#endif
8302 + (ri == 1 && bi < pRxLocal->Fbr1NumEntries)) {
8303 + spin_lock_irqsave(&pAdapter->FbrLock, lockflags);
8304 +
8305 + if (ri == 1) {
8306 + PFBR_DESC_t pNextDesc =
8307 + (PFBR_DESC_t) (pRxLocal->pFbr1RingVa) +
8308 + pRxLocal->local_Fbr1_full.bits.val;
8309 +
8310 + /* Handle the Free Buffer Ring advancement here. Write
8311 + * the PA / Buffer Index for the returned buffer into
8312 + * the oldest (next to be freed)FBR entry
8313 + */
8314 + pNextDesc->addr_hi = pRxLocal->Fbr[1]->PAHigh[bi];
8315 + pNextDesc->addr_lo = pRxLocal->Fbr[1]->PALow[bi];
8316 + pNextDesc->word2.value = bi;
8317 +
8318 + if (++pRxLocal->local_Fbr1_full.bits.val >
8319 + (pRxLocal->Fbr1NumEntries - 1)) {
8320 + pRxLocal->local_Fbr1_full.bits.val = 0;
8321 + pRxLocal->local_Fbr1_full.bits.wrap ^= 1;
8322 + }
8323 +
8324 + writel(pRxLocal->local_Fbr1_full.value,
8325 + &pRxDma->fbr1_full_offset.value);
8326 + }
8327 +#ifdef USE_FBR0
8328 + else {
8329 + PFBR_DESC_t pNextDesc =
8330 + (PFBR_DESC_t) pRxLocal->pFbr0RingVa +
8331 + pRxLocal->local_Fbr0_full.bits.val;
8332 +
8333 + /* Handle the Free Buffer Ring advancement here. Write
8334 + * the PA / Buffer Index for the returned buffer into
8335 + * the oldest (next to be freed) FBR entry
8336 + */
8337 + pNextDesc->addr_hi = pRxLocal->Fbr[0]->PAHigh[bi];
8338 + pNextDesc->addr_lo = pRxLocal->Fbr[0]->PALow[bi];
8339 + pNextDesc->word2.value = bi;
8340 +
8341 + if (++pRxLocal->local_Fbr0_full.bits.val >
8342 + (pRxLocal->Fbr0NumEntries - 1)) {
8343 + pRxLocal->local_Fbr0_full.bits.val = 0;
8344 + pRxLocal->local_Fbr0_full.bits.wrap ^= 1;
8345 + }
8346 +
8347 + writel(pRxLocal->local_Fbr0_full.value,
8348 + &pRxDma->fbr0_full_offset.value);
8349 + }
8350 +#endif
8351 + spin_unlock_irqrestore(&pAdapter->FbrLock, lockflags);
8352 + } else {
8353 + DBG_ERROR(et131x_dbginfo,
8354 + "NICReturnRFD illegal Buffer Index returned\n");
8355 + }
8356 +
8357 + /* The processing on this RFD is done, so put it back on the tail of
8358 + * our list
8359 + */
8360 + spin_lock_irqsave(&pAdapter->RcvLock, lockflags);
8361 + list_add_tail(&pMpRfd->list_node, &pRxLocal->RecvList);
8362 + pRxLocal->nReadyRecv++;
8363 + spin_unlock_irqrestore(&pAdapter->RcvLock, lockflags);
8364 +
8365 + DBG_ASSERT(pRxLocal->nReadyRecv <= pRxLocal->NumRfd);
8366 + DBG_RX_LEAVE(et131x_dbginfo);
8367 +}
8368 diff --git a/drivers/staging/et131x/et1310_rx.h b/drivers/staging/et131x/et1310_rx.h
8369 new file mode 100644
8370 index 0000000..ea66dbc
8371 --- /dev/null
8372 +++ b/drivers/staging/et131x/et1310_rx.h
8373 @@ -0,0 +1,373 @@
8374 +/*
8375 + * Agere Systems Inc.
8376 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
8377 + *
8378 + * Copyright © 2005 Agere Systems Inc.
8379 + * All rights reserved.
8380 + * http://www.agere.com
8381 + *
8382 + *------------------------------------------------------------------------------
8383 + *
8384 + * et1310_rx.h - Defines, structs, enums, prototypes, etc. pertaining to data
8385 + * reception.
8386 + *
8387 + *------------------------------------------------------------------------------
8388 + *
8389 + * SOFTWARE LICENSE
8390 + *
8391 + * This software is provided subject to the following terms and conditions,
8392 + * which you should read carefully before using the software. Using this
8393 + * software indicates your acceptance of these terms and conditions. If you do
8394 + * not agree with these terms and conditions, do not use the software.
8395 + *
8396 + * Copyright © 2005 Agere Systems Inc.
8397 + * All rights reserved.
8398 + *
8399 + * Redistribution and use in source or binary forms, with or without
8400 + * modifications, are permitted provided that the following conditions are met:
8401 + *
8402 + * . Redistributions of source code must retain the above copyright notice, this
8403 + * list of conditions and the following Disclaimer as comments in the code as
8404 + * well as in the documentation and/or other materials provided with the
8405 + * distribution.
8406 + *
8407 + * . Redistributions in binary form must reproduce the above copyright notice,
8408 + * this list of conditions and the following Disclaimer in the documentation
8409 + * and/or other materials provided with the distribution.
8410 + *
8411 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
8412 + * may be used to endorse or promote products derived from this software
8413 + * without specific prior written permission.
8414 + *
8415 + * Disclaimer
8416 + *
8417 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
8418 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
8419 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
8420 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
8421 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
8422 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
8423 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
8424 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
8425 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
8426 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
8427 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
8428 + * DAMAGE.
8429 + *
8430 + */
8431 +
8432 +#ifndef __ET1310_RX_H__
8433 +#define __ET1310_RX_H__
8434 +
8435 +#include "et1310_address_map.h"
8436 +
8437 +#define USE_FBR0 true
8438 +
8439 +#ifdef USE_FBR0
8440 +//#define FBR0_BUFFER_SIZE 256
8441 +#endif
8442 +
8443 +//#define FBR1_BUFFER_SIZE 2048
8444 +
8445 +#define FBR_CHUNKS 32
8446 +
8447 +#define MAX_DESC_PER_RING_RX 1024
8448 +
8449 +/* number of RFDs - default and min */
8450 +#ifdef USE_FBR0
8451 +#define RFD_LOW_WATER_MARK 40
8452 +#define NIC_MIN_NUM_RFD 64
8453 +#define NIC_DEFAULT_NUM_RFD 1024
8454 +#else
8455 +#define RFD_LOW_WATER_MARK 20
8456 +#define NIC_MIN_NUM_RFD 64
8457 +#define NIC_DEFAULT_NUM_RFD 256
8458 +#endif
8459 +
8460 +#define NUM_PACKETS_HANDLED 256
8461 +
8462 +#define ALCATEL_BAD_STATUS 0xe47f0000
8463 +#define ALCATEL_MULTICAST_PKT 0x01000000
8464 +#define ALCATEL_BROADCAST_PKT 0x02000000
8465 +
8466 +/* typedefs for Free Buffer Descriptors */
8467 +typedef union _FBR_WORD2_t {
8468 + u32 value;
8469 + struct {
8470 +#ifdef _BIT_FIELDS_HTOL
8471 + u32 reserved:22; // bits 10-31
8472 + u32 bi:10; // bits 0-9(Buffer Index)
8473 +#else
8474 + u32 bi:10; // bits 0-9(Buffer Index)
8475 + u32 reserved:22; // bit 10-31
8476 +#endif
8477 + } bits;
8478 +} FBR_WORD2_t, *PFBR_WORD2_t;
8479 +
8480 +typedef struct _FBR_DESC_t {
8481 + u32 addr_lo;
8482 + u32 addr_hi;
8483 + FBR_WORD2_t word2;
8484 +} FBR_DESC_t, *PFBR_DESC_t;
8485 +
8486 +/* Typedefs for Packet Status Ring Descriptors */
8487 +typedef union _PKT_STAT_DESC_WORD0_t {
8488 + u32 value;
8489 + struct {
8490 +#ifdef _BIT_FIELDS_HTOL
8491 + // top 16 bits are from the Alcatel Status Word as enumerated in
8492 + // PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2)
8493 +#if 0
8494 + u32 asw_trunc:1; // bit 31(Rx frame truncated)
8495 +#endif
8496 + u32 asw_long_evt:1; // bit 31(Rx long event)
8497 + u32 asw_VLAN_tag:1; // bit 30(VLAN tag detected)
8498 + u32 asw_unsupported_op:1; // bit 29(unsupported OP code)
8499 + u32 asw_pause_frame:1; // bit 28(is a pause frame)
8500 + u32 asw_control_frame:1; // bit 27(is a control frame)
8501 + u32 asw_dribble_nibble:1; // bit 26(spurious bits after EOP)
8502 + u32 asw_broadcast:1; // bit 25(has a broadcast address)
8503 + u32 asw_multicast:1; // bit 24(has a multicast address)
8504 + u32 asw_OK:1; // bit 23(valid CRC + no code error)
8505 + u32 asw_too_long:1; // bit 22(frame length > 1518 bytes)
8506 + u32 asw_len_chk_err:1; // bit 21(frame length field incorrect)
8507 + u32 asw_CRC_err:1; // bit 20(CRC error)
8508 + u32 asw_code_err:1; // bit 19(one or more nibbles signalled as errors)
8509 + u32 asw_false_carrier_event:1; // bit 18(bad carrier since last good packet)
8510 + u32 asw_RX_DV_event:1; // bit 17(short receive event detected)
8511 + u32 asw_prev_pkt_dropped:1;// bit 16(e.g. IFG too small on previous)
8512 + u32 unused:5; // bits 11-15
8513 + u32 vp:1; // bit 10(VLAN Packet)
8514 + u32 jp:1; // bit 9(Jumbo Packet)
8515 + u32 ft:1; // bit 8(Frame Truncated)
8516 + u32 drop:1; // bit 7(Drop packet)
8517 + u32 rxmac_error:1; // bit 6(RXMAC Error Indicator)
8518 + u32 wol:1; // bit 5(WOL Event)
8519 + u32 tcpp:1; // bit 4(TCP checksum pass)
8520 + u32 tcpa:1; // bit 3(TCP checksum assist)
8521 + u32 ipp:1; // bit 2(IP checksum pass)
8522 + u32 ipa:1; // bit 1(IP checksum assist)
8523 + u32 hp:1; // bit 0(hash pass)
8524 +#else
8525 + u32 hp:1; // bit 0(hash pass)
8526 + u32 ipa:1; // bit 1(IP checksum assist)
8527 + u32 ipp:1; // bit 2(IP checksum pass)
8528 + u32 tcpa:1; // bit 3(TCP checksum assist)
8529 + u32 tcpp:1; // bit 4(TCP checksum pass)
8530 + u32 wol:1; // bit 5(WOL Event)
8531 + u32 rxmac_error:1; // bit 6(RXMAC Error Indicator)
8532 + u32 drop:1; // bit 7(Drop packet)
8533 + u32 ft:1; // bit 8(Frame Truncated)
8534 + u32 jp:1; // bit 9(Jumbo Packet)
8535 + u32 vp:1; // bit 10(VLAN Packet)
8536 + u32 unused:5; // bits 11-15
8537 + u32 asw_prev_pkt_dropped:1;// bit 16(e.g. IFG too small on previous)
8538 + u32 asw_RX_DV_event:1; // bit 17(short receive event detected)
8539 + u32 asw_false_carrier_event:1; // bit 18(bad carrier since last good packet)
8540 + u32 asw_code_err:1; // bit 19(one or more nibbles signalled as errors)
8541 + u32 asw_CRC_err:1; // bit 20(CRC error)
8542 + u32 asw_len_chk_err:1; // bit 21(frame length field incorrect)
8543 + u32 asw_too_long:1; // bit 22(frame length > 1518 bytes)
8544 + u32 asw_OK:1; // bit 23(valid CRC + no code error)
8545 + u32 asw_multicast:1; // bit 24(has a multicast address)
8546 + u32 asw_broadcast:1; // bit 25(has a broadcast address)
8547 + u32 asw_dribble_nibble:1; // bit 26(spurious bits after EOP)
8548 + u32 asw_control_frame:1; // bit 27(is a control frame)
8549 + u32 asw_pause_frame:1; // bit 28(is a pause frame)
8550 + u32 asw_unsupported_op:1; // bit 29(unsupported OP code)
8551 + u32 asw_VLAN_tag:1; // bit 30(VLAN tag detected)
8552 + u32 asw_long_evt:1; // bit 31(Rx long event)
8553 +#if 0
8554 + u32 asw_trunc:1; // bit 31(Rx frame truncated)
8555 +#endif
8556 +#endif
8557 + } bits;
8558 +} PKT_STAT_DESC_WORD0_t, *PPKT_STAT_WORD0_t;
8559 +
8560 +typedef union _PKT_STAT_DESC_WORD1_t {
8561 + u32 value;
8562 + struct {
8563 +#ifdef _BIT_FIELDS_HTOL
8564 + u32 unused:4; // bits 28-31
8565 + u32 ri:2; // bits 26-27(Ring Index)
8566 + u32 bi:10; // bits 16-25(Buffer Index)
8567 + u32 length:16; // bit 0-15(length in bytes)
8568 +#else
8569 + u32 length:16; // bit 0-15(length in bytes)
8570 + u32 bi:10; // bits 16-25(Buffer Index)
8571 + u32 ri:2; // bits 26-27(Ring Index)
8572 + u32 unused:4; // bits 28-31
8573 +#endif
8574 + } bits;
8575 +} PKT_STAT_DESC_WORD1_t, *PPKT_STAT_WORD1_t;
8576 +
8577 +typedef struct _PKT_STAT_DESC_t {
8578 + PKT_STAT_DESC_WORD0_t word0;
8579 + PKT_STAT_DESC_WORD1_t word1;
8580 +} PKT_STAT_DESC_t, *PPKT_STAT_DESC_t;
8581 +
8582 +/* Typedefs for the RX DMA status word */
8583 +
8584 +/*
8585 + * RXSTAT_WORD0_t structure holds part of the status bits of the Rx DMA engine
8586 + * that get copied out to memory by the ET-1310. Word 0 is a 32 bit word
8587 + * whichcontains Free Buffer ring 0 and 1 available offset.
8588 + */
8589 +typedef union _rxstat_word0_t {
8590 + u32 value;
8591 + struct {
8592 +#ifdef _BIT_FIELDS_HTOL
8593 + u32 FBR1unused:5; // bits 27-31
8594 + u32 FBR1wrap:1; // bit 26
8595 + u32 FBR1offset:10; // bits 16-25
8596 + u32 FBR0unused:5; // bits 11-15
8597 + u32 FBR0wrap:1; // bit 10
8598 + u32 FBR0offset:10; // bits 0-9
8599 +#else
8600 + u32 FBR0offset:10; // bits 0-9
8601 + u32 FBR0wrap:1; // bit 10
8602 + u32 FBR0unused:5; // bits 11-15
8603 + u32 FBR1offset:10; // bits 16-25
8604 + u32 FBR1wrap:1; // bit 26
8605 + u32 FBR1unused:5; // bits 27-31
8606 +#endif
8607 + } bits;
8608 +} RXSTAT_WORD0_t, *PRXSTAT_WORD0_t;
8609 +
8610 +/*
8611 + * RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine
8612 + * that get copied out to memory by the ET-1310. Word 3 is a 32 bit word
8613 + * which contains the Packet Status Ring available offset.
8614 + */
8615 +typedef union _rxstat_word1_t {
8616 + u32 value;
8617 + struct {
8618 +#ifdef _BIT_FIELDS_HTOL
8619 + u32 PSRunused:3; // bits 29-31
8620 + u32 PSRwrap:1; // bit 28
8621 + u32 PSRoffset:12; // bits 16-27
8622 + u32 reserved:16; // bits 0-15
8623 +#else
8624 + u32 reserved:16; // bits 0-15
8625 + u32 PSRoffset:12; // bits 16-27
8626 + u32 PSRwrap:1; // bit 28
8627 + u32 PSRunused:3; // bits 29-31
8628 +#endif
8629 + } bits;
8630 +} RXSTAT_WORD1_t, *PRXSTAT_WORD1_t;
8631 +
8632 +/*
8633 + * RX_STATUS_BLOCK_t is sructure representing the status of the Rx DMA engine
8634 + * it sits in free memory, and is pointed to by 0x101c / 0x1020
8635 + */
8636 +typedef struct _rx_status_block_t {
8637 + RXSTAT_WORD0_t Word0;
8638 + RXSTAT_WORD1_t Word1;
8639 +} RX_STATUS_BLOCK_t, *PRX_STATUS_BLOCK_t;
8640 +
8641 +/*
8642 + * Structure for look-up table holding free buffer ring pointers
8643 + */
8644 +typedef struct _FbrLookupTable {
8645 + void *Va[MAX_DESC_PER_RING_RX];
8646 + void *Buffer1[MAX_DESC_PER_RING_RX];
8647 + void *Buffer2[MAX_DESC_PER_RING_RX];
8648 + u32 PAHigh[MAX_DESC_PER_RING_RX];
8649 + u32 PALow[MAX_DESC_PER_RING_RX];
8650 +} FBRLOOKUPTABLE, *PFBRLOOKUPTABLE;
8651 +
8652 +typedef enum {
8653 + ONE_PACKET_INTERRUPT,
8654 + FOUR_PACKET_INTERRUPT
8655 +} eRX_INTERRUPT_STATE_t, *PeRX_INTERRUPT_STATE_t;
8656 +
8657 +/*
8658 + * Structure to hold the skb's in a list
8659 + */
8660 +typedef struct rx_skb_list_elem {
8661 + struct list_head skb_list_elem;
8662 + dma_addr_t dma_addr;
8663 + struct sk_buff *skb;
8664 +} RX_SKB_LIST_ELEM, *PRX_SKB_LIST_ELEM;
8665 +
8666 +/*
8667 + * RX_RING_t is sructure representing the adaptor's local reference(s) to the
8668 + * rings
8669 + */
8670 +typedef struct _rx_ring_t {
8671 +#ifdef USE_FBR0
8672 + void *pFbr0RingVa;
8673 + dma_addr_t pFbr0RingPa;
8674 + void *Fbr0MemVa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
8675 + dma_addr_t Fbr0MemPa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
8676 + uint64_t Fbr0Realpa;
8677 + uint64_t Fbr0offset;
8678 + DMA10W_t local_Fbr0_full;
8679 + u32 Fbr0NumEntries;
8680 + u32 Fbr0BufferSize;
8681 +#endif
8682 + void *pFbr1RingVa;
8683 + dma_addr_t pFbr1RingPa;
8684 + void *Fbr1MemVa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
8685 + dma_addr_t Fbr1MemPa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
8686 + uint64_t Fbr1Realpa;
8687 + uint64_t Fbr1offset;
8688 + FBRLOOKUPTABLE *Fbr[2];
8689 + DMA10W_t local_Fbr1_full;
8690 + u32 Fbr1NumEntries;
8691 + u32 Fbr1BufferSize;
8692 +
8693 + void *pPSRingVa;
8694 + dma_addr_t pPSRingPa;
8695 + uint64_t pPSRingRealPa;
8696 + uint64_t pPSRingOffset;
8697 + RXDMA_PSR_FULL_OFFSET_t local_psr_full;
8698 + u32 PsrNumEntries;
8699 +
8700 + void *pRxStatusVa;
8701 + dma_addr_t pRxStatusPa;
8702 + uint64_t RxStatusRealPA;
8703 + uint64_t RxStatusOffset;
8704 +
8705 + struct list_head RecvBufferPool;
8706 +
8707 + /* RECV */
8708 + struct list_head RecvList;
8709 + struct list_head RecvPendingList;
8710 + u32 nReadyRecv;
8711 +
8712 + u32 NumRfd;
8713 +
8714 + bool UnfinishedReceives;
8715 +
8716 + struct list_head RecvPacketPool;
8717 +
8718 + /* lookaside lists */
8719 + struct kmem_cache *RecvLookaside;
8720 +} RX_RING_t, *PRX_RING_t;
8721 +
8722 +/* Forward reference of RFD */
8723 +struct _MP_RFD;
8724 +
8725 +/* Forward declaration of the private adapter structure */
8726 +struct et131x_adapter;
8727 +
8728 +/* PROTOTYPES for Initialization */
8729 +int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter);
8730 +void et131x_rx_dma_memory_free(struct et131x_adapter *adapter);
8731 +int et131x_rfd_resources_alloc(struct et131x_adapter *adapter,
8732 + struct _MP_RFD *pMpRfd);
8733 +void et131x_rfd_resources_free(struct et131x_adapter *adapter,
8734 + struct _MP_RFD *pMpRfd);
8735 +int et131x_init_recv(struct et131x_adapter *adapter);
8736 +
8737 +void ConfigRxDmaRegs(struct et131x_adapter *adapter);
8738 +void SetRxDmaTimer(struct et131x_adapter *adapter);
8739 +void et131x_rx_dma_disable(struct et131x_adapter *adapter);
8740 +void et131x_rx_dma_enable(struct et131x_adapter *adapter);
8741 +
8742 +void et131x_reset_recv(struct et131x_adapter *adapter);
8743 +
8744 +void et131x_handle_recv_interrupt(struct et131x_adapter *adapter);
8745 +
8746 +#endif /* __ET1310_RX_H__ */
8747 diff --git a/drivers/staging/et131x/et1310_tx.c b/drivers/staging/et131x/et1310_tx.c
8748 new file mode 100644
8749 index 0000000..a95c260
8750 --- /dev/null
8751 +++ b/drivers/staging/et131x/et1310_tx.c
8752 @@ -0,0 +1,1525 @@
8753 +/*
8754 + * Agere Systems Inc.
8755 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
8756 + *
8757 + * Copyright © 2005 Agere Systems Inc.
8758 + * All rights reserved.
8759 + * http://www.agere.com
8760 + *
8761 + *------------------------------------------------------------------------------
8762 + *
8763 + * et1310_tx.c - Routines used to perform data transmission.
8764 + *
8765 + *------------------------------------------------------------------------------
8766 + *
8767 + * SOFTWARE LICENSE
8768 + *
8769 + * This software is provided subject to the following terms and conditions,
8770 + * which you should read carefully before using the software. Using this
8771 + * software indicates your acceptance of these terms and conditions. If you do
8772 + * not agree with these terms and conditions, do not use the software.
8773 + *
8774 + * Copyright © 2005 Agere Systems Inc.
8775 + * All rights reserved.
8776 + *
8777 + * Redistribution and use in source or binary forms, with or without
8778 + * modifications, are permitted provided that the following conditions are met:
8779 + *
8780 + * . Redistributions of source code must retain the above copyright notice, this
8781 + * list of conditions and the following Disclaimer as comments in the code as
8782 + * well as in the documentation and/or other materials provided with the
8783 + * distribution.
8784 + *
8785 + * . Redistributions in binary form must reproduce the above copyright notice,
8786 + * this list of conditions and the following Disclaimer in the documentation
8787 + * and/or other materials provided with the distribution.
8788 + *
8789 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
8790 + * may be used to endorse or promote products derived from this software
8791 + * without specific prior written permission.
8792 + *
8793 + * Disclaimer
8794 + *
8795 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
8796 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
8797 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
8798 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
8799 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
8800 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
8801 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
8802 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
8803 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
8804 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
8805 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
8806 + * DAMAGE.
8807 + *
8808 + */
8809 +
8810 +#include "et131x_version.h"
8811 +#include "et131x_debug.h"
8812 +#include "et131x_defs.h"
8813 +
8814 +#include <linux/pci.h>
8815 +#include <linux/init.h>
8816 +#include <linux/module.h>
8817 +#include <linux/types.h>
8818 +#include <linux/kernel.h>
8819 +
8820 +#include <linux/sched.h>
8821 +#include <linux/ptrace.h>
8822 +#include <linux/slab.h>
8823 +#include <linux/ctype.h>
8824 +#include <linux/string.h>
8825 +#include <linux/timer.h>
8826 +#include <linux/interrupt.h>
8827 +#include <linux/in.h>
8828 +#include <linux/delay.h>
8829 +#include <asm/io.h>
8830 +#include <asm/system.h>
8831 +#include <asm/bitops.h>
8832 +
8833 +#include <linux/netdevice.h>
8834 +#include <linux/etherdevice.h>
8835 +#include <linux/skbuff.h>
8836 +#include <linux/if_arp.h>
8837 +#include <linux/ioport.h>
8838 +
8839 +#include "et1310_phy.h"
8840 +#include "et1310_pm.h"
8841 +#include "et1310_jagcore.h"
8842 +
8843 +#include "et131x_adapter.h"
8844 +#include "et131x_initpci.h"
8845 +#include "et131x_isr.h"
8846 +
8847 +#include "et1310_tx.h"
8848 +
8849 +/* Data for debugging facilities */
8850 +#ifdef CONFIG_ET131X_DEBUG
8851 +extern dbg_info_t *et131x_dbginfo;
8852 +#endif /* CONFIG_ET131X_DEBUG */
8853 +
8854 +static void et131x_update_tcb_list(struct et131x_adapter *pAdapter);
8855 +static void et131x_check_send_wait_list(struct et131x_adapter *pAdapter);
8856 +static inline void et131x_free_send_packet(struct et131x_adapter *pAdapter,
8857 + PMP_TCB pMpTcb);
8858 +static int et131x_send_packet(struct sk_buff *skb,
8859 + struct et131x_adapter *pAdapter);
8860 +static int nic_send_packet(struct et131x_adapter *pAdapter, PMP_TCB pMpTcb);
8861 +
8862 +/**
8863 + * et131x_tx_dma_memory_alloc
8864 + * @adapter: pointer to our private adapter structure
8865 + *
8866 + * Returns 0 on success and errno on failure (as defined in errno.h).
8867 + *
8868 + * Allocates memory that will be visible both to the device and to the CPU.
8869 + * The OS will pass us packets, pointers to which we will insert in the Tx
8870 + * Descriptor queue. The device will read this queue to find the packets in
8871 + * memory. The device will update the "status" in memory each time it xmits a
8872 + * packet.
8873 + */
8874 +int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter)
8875 +{
8876 + int desc_size = 0;
8877 + TX_RING_t *tx_ring = &adapter->TxRing;
8878 +
8879 + DBG_ENTER(et131x_dbginfo);
8880 +
8881 + /* Allocate memory for the TCB's (Transmit Control Block) */
8882 + adapter->TxRing.MpTcbMem = (MP_TCB *) kcalloc(NUM_TCB, sizeof(MP_TCB),
8883 + GFP_ATOMIC | GFP_DMA);
8884 + if (!adapter->TxRing.MpTcbMem) {
8885 + DBG_ERROR(et131x_dbginfo, "Cannot alloc memory for TCBs\n");
8886 + DBG_LEAVE(et131x_dbginfo);
8887 + return -ENOMEM;
8888 + }
8889 +
8890 + /* Allocate enough memory for the Tx descriptor ring, and allocate
8891 + * some extra so that the ring can be aligned on a 4k boundary.
8892 + */
8893 + desc_size = (sizeof(TX_DESC_ENTRY_t) * NUM_DESC_PER_RING_TX) + 4096 - 1;
8894 + tx_ring->pTxDescRingVa =
8895 + (PTX_DESC_ENTRY_t) pci_alloc_consistent(adapter->pdev, desc_size,
8896 + &tx_ring->pTxDescRingPa);
8897 + if (!adapter->TxRing.pTxDescRingVa) {
8898 + DBG_ERROR(et131x_dbginfo, "Cannot alloc memory for Tx Ring\n");
8899 + DBG_LEAVE(et131x_dbginfo);
8900 + return -ENOMEM;
8901 + }
8902 +
8903 + /* Save physical address
8904 + *
8905 + * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
8906 + * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
8907 + * are ever returned, make sure the high part is retrieved here before
8908 + * storing the adjusted address.
8909 + */
8910 + tx_ring->pTxDescRingAdjustedPa = tx_ring->pTxDescRingPa;
8911 +
8912 + /* Align Tx Descriptor Ring on a 4k (0x1000) byte boundary */
8913 + et131x_align_allocated_memory(adapter,
8914 + &tx_ring->pTxDescRingAdjustedPa,
8915 + &tx_ring->TxDescOffset, 0x0FFF);
8916 +
8917 + tx_ring->pTxDescRingVa += tx_ring->TxDescOffset;
8918 +
8919 + /* Allocate memory for the Tx status block */
8920 + tx_ring->pTxStatusVa = pci_alloc_consistent(adapter->pdev,
8921 + sizeof(TX_STATUS_BLOCK_t),
8922 + &tx_ring->pTxStatusPa);
8923 + if (!adapter->TxRing.pTxStatusPa) {
8924 + DBG_ERROR(et131x_dbginfo,
8925 + "Cannot alloc memory for Tx status block\n");
8926 + DBG_LEAVE(et131x_dbginfo);
8927 + return -ENOMEM;
8928 + }
8929 +
8930 + /* Allocate memory for a dummy buffer */
8931 + tx_ring->pTxDummyBlkVa = pci_alloc_consistent(adapter->pdev,
8932 + NIC_MIN_PACKET_SIZE,
8933 + &tx_ring->pTxDummyBlkPa);
8934 + if (!adapter->TxRing.pTxDummyBlkPa) {
8935 + DBG_ERROR(et131x_dbginfo,
8936 + "Cannot alloc memory for Tx dummy buffer\n");
8937 + DBG_LEAVE(et131x_dbginfo);
8938 + return -ENOMEM;
8939 + }
8940 +
8941 + DBG_LEAVE(et131x_dbginfo);
8942 + return 0;
8943 +}
8944 +
8945 +/**
8946 + * et131x_tx_dma_memory_free - Free all memory allocated within this module
8947 + * @adapter: pointer to our private adapter structure
8948 + *
8949 + * Returns 0 on success and errno on failure (as defined in errno.h).
8950 + */
8951 +void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
8952 +{
8953 + int desc_size = 0;
8954 +
8955 + DBG_ENTER(et131x_dbginfo);
8956 +
8957 + if (adapter->TxRing.pTxDescRingVa) {
8958 + /* Free memory relating to Tx rings here */
8959 + adapter->TxRing.pTxDescRingVa -= adapter->TxRing.TxDescOffset;
8960 +
8961 + desc_size =
8962 + (sizeof(TX_DESC_ENTRY_t) * NUM_DESC_PER_RING_TX) + 4096 - 1;
8963 +
8964 + pci_free_consistent(adapter->pdev,
8965 + desc_size,
8966 + adapter->TxRing.pTxDescRingVa,
8967 + adapter->TxRing.pTxDescRingPa);
8968 +
8969 + adapter->TxRing.pTxDescRingVa = NULL;
8970 + }
8971 +
8972 + /* Free memory for the Tx status block */
8973 + if (adapter->TxRing.pTxStatusVa) {
8974 + pci_free_consistent(adapter->pdev,
8975 + sizeof(TX_STATUS_BLOCK_t),
8976 + adapter->TxRing.pTxStatusVa,
8977 + adapter->TxRing.pTxStatusPa);
8978 +
8979 + adapter->TxRing.pTxStatusVa = NULL;
8980 + }
8981 +
8982 + /* Free memory for the dummy buffer */
8983 + if (adapter->TxRing.pTxDummyBlkVa) {
8984 + pci_free_consistent(adapter->pdev,
8985 + NIC_MIN_PACKET_SIZE,
8986 + adapter->TxRing.pTxDummyBlkVa,
8987 + adapter->TxRing.pTxDummyBlkPa);
8988 +
8989 + adapter->TxRing.pTxDummyBlkVa = NULL;
8990 + }
8991 +
8992 + /* Free the memory for MP_TCB structures */
8993 + if (adapter->TxRing.MpTcbMem) {
8994 + kfree(adapter->TxRing.MpTcbMem);
8995 + adapter->TxRing.MpTcbMem = NULL;
8996 + }
8997 +
8998 + DBG_LEAVE(et131x_dbginfo);
8999 +}
9000 +
9001 +/**
9002 + * ConfigTxDmaRegs - Set up the tx dma section of the JAGCore.
9003 + * @adapter: pointer to our private adapter structure
9004 + */
9005 +void ConfigTxDmaRegs(struct et131x_adapter *pAdapter)
9006 +{
9007 + struct _TXDMA_t __iomem *pTxDma = &pAdapter->CSRAddress->txdma;
9008 +
9009 + DBG_ENTER(et131x_dbginfo);
9010 +
9011 + /* Load the hardware with the start of the transmit descriptor ring. */
9012 + writel((uint32_t) (pAdapter->TxRing.pTxDescRingAdjustedPa >> 32),
9013 + &pTxDma->pr_base_hi);
9014 + writel((uint32_t) pAdapter->TxRing.pTxDescRingAdjustedPa,
9015 + &pTxDma->pr_base_lo);
9016 +
9017 + /* Initialise the transmit DMA engine */
9018 + writel(NUM_DESC_PER_RING_TX - 1, &pTxDma->pr_num_des.value);
9019 +
9020 + /* Load the completion writeback physical address
9021 + *
9022 + * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
9023 + * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
9024 + * are ever returned, make sure the high part is retrieved here before
9025 + * storing the adjusted address.
9026 + */
9027 + writel(0, &pTxDma->dma_wb_base_hi);
9028 + writel(pAdapter->TxRing.pTxStatusPa, &pTxDma->dma_wb_base_lo);
9029 +
9030 + memset(pAdapter->TxRing.pTxStatusVa, 0, sizeof(TX_STATUS_BLOCK_t));
9031 +
9032 + writel(0, &pTxDma->service_request.value);
9033 + pAdapter->TxRing.txDmaReadyToSend.value = 0;
9034 +
9035 + DBG_LEAVE(et131x_dbginfo);
9036 +}
9037 +
9038 +/**
9039 + * et131x_tx_dma_disable - Stop of Tx_DMA on the ET1310
9040 + * @pAdapter: pointer to our adapter structure
9041 + */
9042 +void et131x_tx_dma_disable(struct et131x_adapter *pAdapter)
9043 +{
9044 + DBG_ENTER(et131x_dbginfo);
9045 +
9046 + /* Setup the tramsmit dma configuration register */
9047 + writel(0x101, &pAdapter->CSRAddress->txdma.csr.value);
9048 +
9049 + DBG_LEAVE(et131x_dbginfo);
9050 +}
9051 +
9052 +/**
9053 + * et131x_tx_dma_enable - re-start of Tx_DMA on the ET1310.
9054 + * @pAdapter: pointer to our adapter structure
9055 + *
9056 + * Mainly used after a return to the D0 (full-power) state from a lower state.
9057 + */
9058 +void et131x_tx_dma_enable(struct et131x_adapter *pAdapter)
9059 +{
9060 + DBG_ENTER(et131x_dbginfo);
9061 +
9062 + if (pAdapter->RegistryPhyLoopbk) {
9063 + /* TxDMA is disabled for loopback operation. */
9064 + writel(0x101, &pAdapter->CSRAddress->txdma.csr.value);
9065 + } else {
9066 + TXDMA_CSR_t csr = { 0 };
9067 +
9068 + /* Setup the transmit dma configuration register for normal
9069 + * operation
9070 + */
9071 + csr.bits.sngl_epkt_mode = 1;
9072 + csr.bits.halt = 0;
9073 + csr.bits.cache_thrshld = pAdapter->RegistryDMACache;
9074 + writel(csr.value, &pAdapter->CSRAddress->txdma.csr.value);
9075 + }
9076 +
9077 + DBG_LEAVE(et131x_dbginfo);
9078 +}
9079 +
9080 +/**
9081 + * et131x_init_send - Initialize send data structures
9082 + * @adapter: pointer to our private adapter structure
9083 + */
9084 +void et131x_init_send(struct et131x_adapter *adapter)
9085 +{
9086 + PMP_TCB pMpTcb;
9087 + uint32_t TcbCount;
9088 + TX_RING_t *tx_ring;
9089 +
9090 + DBG_ENTER(et131x_dbginfo);
9091 +
9092 + /* Setup some convenience pointers */
9093 + tx_ring = &adapter->TxRing;
9094 + pMpTcb = adapter->TxRing.MpTcbMem;
9095 +
9096 + tx_ring->TCBReadyQueueHead = pMpTcb;
9097 +
9098 + /* Go through and set up each TCB */
9099 + for (TcbCount = 0; TcbCount < NUM_TCB; TcbCount++) {
9100 + memset(pMpTcb, 0, sizeof(MP_TCB));
9101 +
9102 + /* Set the link pointer in HW TCB to the next TCB in the
9103 + * chain. If this is the last TCB in the chain, also set the
9104 + * tail pointer.
9105 + */
9106 + if (TcbCount < NUM_TCB - 1) {
9107 + pMpTcb->Next = pMpTcb + 1;
9108 + } else {
9109 + tx_ring->TCBReadyQueueTail = pMpTcb;
9110 + pMpTcb->Next = (PMP_TCB) NULL;
9111 + }
9112 +
9113 + pMpTcb++;
9114 + }
9115 +
9116 + /* Curr send queue should now be empty */
9117 + tx_ring->CurrSendHead = (PMP_TCB) NULL;
9118 + tx_ring->CurrSendTail = (PMP_TCB) NULL;
9119 +
9120 + INIT_LIST_HEAD(&adapter->TxRing.SendWaitQueue);
9121 +
9122 + DBG_LEAVE(et131x_dbginfo);
9123 +}
9124 +
9125 +/**
9126 + * et131x_send_packets - This function is called by the OS to send packets
9127 + * @skb: the packet(s) to send
9128 + * @netdev:device on which to TX the above packet(s)
9129 + *
9130 + * Return 0 in almost all cases; non-zero value in extreme hard failure only
9131 + */
9132 +int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev)
9133 +{
9134 + int status = 0;
9135 + struct et131x_adapter *pAdapter = NULL;
9136 +
9137 + DBG_TX_ENTER(et131x_dbginfo);
9138 +
9139 + pAdapter = netdev_priv(netdev);
9140 +
9141 + /* Send these packets
9142 + *
9143 + * NOTE: The Linux Tx entry point is only given one packet at a time
9144 + * to Tx, so the PacketCount and it's array used makes no sense here
9145 + */
9146 +
9147 + /* Queue is not empty or TCB is not available */
9148 + if (!list_empty(&pAdapter->TxRing.SendWaitQueue) ||
9149 + MP_TCB_RESOURCES_NOT_AVAILABLE(pAdapter)) {
9150 + /* NOTE: If there's an error on send, no need to queue the
9151 + * packet under Linux; if we just send an error up to the
9152 + * netif layer, it will resend the skb to us.
9153 + */
9154 + DBG_VERBOSE(et131x_dbginfo, "TCB Resources Not Available\n");
9155 + status = -ENOMEM;
9156 + } else {
9157 + /* We need to see if the link is up; if it's not, make the
9158 + * netif layer think we're good and drop the packet
9159 + */
9160 + //if( MP_SHOULD_FAIL_SEND( pAdapter ) || pAdapter->DriverNoPhyAccess )
9161 + if (MP_SHOULD_FAIL_SEND(pAdapter) || pAdapter->DriverNoPhyAccess
9162 + || !netif_carrier_ok(netdev)) {
9163 + DBG_VERBOSE(et131x_dbginfo,
9164 + "Can't Tx, Link is DOWN; drop the packet\n");
9165 +
9166 + dev_kfree_skb_any(skb);
9167 + skb = NULL;
9168 +
9169 + pAdapter->net_stats.tx_dropped++;
9170 + } else {
9171 + status = et131x_send_packet(skb, pAdapter);
9172 +
9173 + if (status == -ENOMEM) {
9174 +
9175 + /* NOTE: If there's an error on send, no need
9176 + * to queue the packet under Linux; if we just
9177 + * send an error up to the netif layer, it
9178 + * will resend the skb to us.
9179 + */
9180 + DBG_WARNING(et131x_dbginfo,
9181 + "Resources problem, Queue tx packet\n");
9182 + } else if (status != 0) {
9183 + /* On any other error, make netif think we're
9184 + * OK and drop the packet
9185 + */
9186 + DBG_WARNING(et131x_dbginfo,
9187 + "General error, drop packet\n");
9188 +
9189 + dev_kfree_skb_any(skb);
9190 + skb = NULL;
9191 +
9192 + pAdapter->net_stats.tx_dropped++;
9193 + }
9194 + }
9195 + }
9196 +
9197 + DBG_TX_LEAVE(et131x_dbginfo);
9198 + return status;
9199 +}
9200 +
9201 +/**
9202 + * et131x_send_packet - Do the work to send a packet
9203 + * @skb: the packet(s) to send
9204 + * @pAdapter: a pointer to the device's private adapter structure
9205 + *
9206 + * Return 0 in almost all cases; non-zero value in extreme hard failure only.
9207 + *
9208 + * Assumption: Send spinlock has been acquired
9209 + */
9210 +static int et131x_send_packet(struct sk_buff *skb,
9211 + struct et131x_adapter *pAdapter)
9212 +{
9213 + int status = 0;
9214 + PMP_TCB pMpTcb = NULL;
9215 + uint16_t *pShBufVa;
9216 + unsigned long lockflags;
9217 +
9218 + DBG_TX_ENTER(et131x_dbginfo);
9219 +
9220 + /* Is our buffer scattered, or continuous? */
9221 + if (skb_shinfo(skb)->nr_frags == 0) {
9222 + DBG_TX(et131x_dbginfo, "Scattered buffer: NO\n");
9223 + } else {
9224 + DBG_TX(et131x_dbginfo, "Scattered buffer: YES, Num Frags: %d\n",
9225 + skb_shinfo(skb)->nr_frags);
9226 + }
9227 +
9228 + /* All packets must have at least a MAC address and a protocol type */
9229 + if (skb->len < ETH_HLEN) {
9230 + DBG_ERROR(et131x_dbginfo,
9231 + "Packet size < ETH_HLEN (14 bytes)\n");
9232 + DBG_LEAVE(et131x_dbginfo);
9233 + return -EIO;
9234 + }
9235 +
9236 + /* Get a TCB for this packet */
9237 + spin_lock_irqsave(&pAdapter->TCBReadyQLock, lockflags);
9238 +
9239 + pMpTcb = pAdapter->TxRing.TCBReadyQueueHead;
9240 +
9241 + if (pMpTcb == NULL) {
9242 + spin_unlock_irqrestore(&pAdapter->TCBReadyQLock, lockflags);
9243 +
9244 + DBG_WARNING(et131x_dbginfo, "Can't obtain a TCB\n");
9245 + DBG_TX_LEAVE(et131x_dbginfo);
9246 + return -ENOMEM;
9247 + }
9248 +
9249 + pAdapter->TxRing.TCBReadyQueueHead = pMpTcb->Next;
9250 +
9251 + if (pAdapter->TxRing.TCBReadyQueueHead == NULL) {
9252 + pAdapter->TxRing.TCBReadyQueueTail = NULL;
9253 + }
9254 +
9255 + spin_unlock_irqrestore(&pAdapter->TCBReadyQLock, lockflags);
9256 +
9257 + pMpTcb->PacketLength = skb->len;
9258 + pMpTcb->Packet = skb;
9259 +
9260 + if ((skb->data != NULL) && ((skb->len - skb->data_len) >= 6)) {
9261 + pShBufVa = (uint16_t *) skb->data;
9262 +
9263 + if ((pShBufVa[0] == 0xffff) &&
9264 + (pShBufVa[1] == 0xffff) && (pShBufVa[2] == 0xffff)) {
9265 + MP_SET_FLAG(pMpTcb, fMP_DEST_BROAD);
9266 + } else if ((pShBufVa[0] & 0x3) == 0x0001) {
9267 + MP_SET_FLAG(pMpTcb, fMP_DEST_MULTI);
9268 + }
9269 + }
9270 +
9271 + pMpTcb->Next = NULL;
9272 +
9273 + /* Call the NIC specific send handler. */
9274 + if (status == 0) {
9275 + status = nic_send_packet(pAdapter, pMpTcb);
9276 + }
9277 +
9278 + if (status != 0) {
9279 + spin_lock_irqsave(&pAdapter->TCBReadyQLock, lockflags);
9280 +
9281 + if (pAdapter->TxRing.TCBReadyQueueTail) {
9282 + pAdapter->TxRing.TCBReadyQueueTail->Next = pMpTcb;
9283 + } else {
9284 + /* Apparently ready Q is empty. */
9285 + pAdapter->TxRing.TCBReadyQueueHead = pMpTcb;
9286 + }
9287 +
9288 + pAdapter->TxRing.TCBReadyQueueTail = pMpTcb;
9289 +
9290 + spin_unlock_irqrestore(&pAdapter->TCBReadyQLock, lockflags);
9291 +
9292 + DBG_TX_LEAVE(et131x_dbginfo);
9293 + return status;
9294 + }
9295 +
9296 + DBG_ASSERT(pAdapter->TxRing.nBusySend <= NUM_TCB);
9297 +
9298 + DBG_TX_LEAVE(et131x_dbginfo);
9299 + return 0;
9300 +}
9301 +
9302 +/**
9303 + * nic_send_packet - NIC specific send handler for version B silicon.
9304 + * @pAdapter: pointer to our adapter
9305 + * @pMpTcb: pointer to MP_TCB
9306 + *
9307 + * Returns 0 or errno.
9308 + */
9309 +static int nic_send_packet(struct et131x_adapter *pAdapter, PMP_TCB pMpTcb)
9310 +{
9311 + uint32_t loopIndex;
9312 + TX_DESC_ENTRY_t CurDesc[24];
9313 + uint32_t FragmentNumber = 0;
9314 + uint32_t iThisCopy, iRemainder;
9315 + struct sk_buff *pPacket = pMpTcb->Packet;
9316 + uint32_t FragListCount = skb_shinfo(pPacket)->nr_frags + 1;
9317 + struct skb_frag_struct *pFragList = &skb_shinfo(pPacket)->frags[0];
9318 + unsigned long lockflags1, lockflags2;
9319 +
9320 + DBG_TX_ENTER(et131x_dbginfo);
9321 +
9322 + /* Part of the optimizations of this send routine restrict us to
9323 + * sending 24 fragments at a pass. In practice we should never see
9324 + * more than 5 fragments.
9325 + *
9326 + * NOTE: The older version of this function (below) can handle any
9327 + * number of fragments. If needed, we can call this function,
9328 + * although it is less efficient.
9329 + */
9330 + if (FragListCount > 23) {
9331 + DBG_TX_LEAVE(et131x_dbginfo);
9332 + return -EIO;
9333 + }
9334 +
9335 + memset(CurDesc, 0, sizeof(TX_DESC_ENTRY_t) * (FragListCount + 1));
9336 +
9337 + for (loopIndex = 0; loopIndex < FragListCount; loopIndex++) {
9338 + /* If there is something in this element, lets get a
9339 + * descriptor from the ring and get the necessary data
9340 + */
9341 + if (loopIndex == 0) {
9342 + /* If the fragments are smaller than a standard MTU,
9343 + * then map them to a single descriptor in the Tx
9344 + * Desc ring. However, if they're larger, as is
9345 + * possible with support for jumbo packets, then
9346 + * split them each across 2 descriptors.
9347 + *
9348 + * This will work until we determine why the hardware
9349 + * doesn't seem to like large fragments.
9350 + */
9351 + if ((pPacket->len - pPacket->data_len) <= 1514) {
9352 + DBG_TX(et131x_dbginfo,
9353 + "Got packet of length %d, "
9354 + "filling desc entry %d, "
9355 + "TCB: 0x%p\n",
9356 + (pPacket->len - pPacket->data_len),
9357 + pAdapter->TxRing.txDmaReadyToSend.bits.
9358 + val, pMpTcb);
9359 +
9360 + CurDesc[FragmentNumber].DataBufferPtrHigh = 0;
9361 +
9362 + CurDesc[FragmentNumber].word2.bits.
9363 + length_in_bytes =
9364 + pPacket->len - pPacket->data_len;
9365 +
9366 + /* NOTE: Here, the dma_addr_t returned from
9367 + * pci_map_single() is implicitly cast as a
9368 + * uint32_t. Although dma_addr_t can be
9369 + * 64-bit, the address returned by
9370 + * pci_map_single() is always 32-bit
9371 + * addressable (as defined by the pci/dma
9372 + * subsystem)
9373 + */
9374 + CurDesc[FragmentNumber++].DataBufferPtrLow =
9375 + pci_map_single(pAdapter->pdev,
9376 + pPacket->data,
9377 + pPacket->len -
9378 + pPacket->data_len,
9379 + PCI_DMA_TODEVICE);
9380 + } else {
9381 + DBG_TX(et131x_dbginfo,
9382 + "Got packet of length %d, "
9383 + "filling desc entry %d, "
9384 + "TCB: 0x%p\n",
9385 + (pPacket->len - pPacket->data_len),
9386 + pAdapter->TxRing.txDmaReadyToSend.bits.
9387 + val, pMpTcb);
9388 +
9389 + CurDesc[FragmentNumber].DataBufferPtrHigh = 0;
9390 +
9391 + CurDesc[FragmentNumber].word2.bits.
9392 + length_in_bytes =
9393 + ((pPacket->len - pPacket->data_len) / 2);
9394 +
9395 + /* NOTE: Here, the dma_addr_t returned from
9396 + * pci_map_single() is implicitly cast as a
9397 + * uint32_t. Although dma_addr_t can be
9398 + * 64-bit, the address returned by
9399 + * pci_map_single() is always 32-bit
9400 + * addressable (as defined by the pci/dma
9401 + * subsystem)
9402 + */
9403 + CurDesc[FragmentNumber++].DataBufferPtrLow =
9404 + pci_map_single(pAdapter->pdev,
9405 + pPacket->data,
9406 + ((pPacket->len -
9407 + pPacket->data_len) / 2),
9408 + PCI_DMA_TODEVICE);
9409 + CurDesc[FragmentNumber].DataBufferPtrHigh = 0;
9410 +
9411 + CurDesc[FragmentNumber].word2.bits.
9412 + length_in_bytes =
9413 + ((pPacket->len - pPacket->data_len) / 2);
9414 +
9415 + /* NOTE: Here, the dma_addr_t returned from
9416 + * pci_map_single() is implicitly cast as a
9417 + * uint32_t. Although dma_addr_t can be
9418 + * 64-bit, the address returned by
9419 + * pci_map_single() is always 32-bit
9420 + * addressable (as defined by the pci/dma
9421 + * subsystem)
9422 + */
9423 + CurDesc[FragmentNumber++].DataBufferPtrLow =
9424 + pci_map_single(pAdapter->pdev,
9425 + pPacket->data +
9426 + ((pPacket->len -
9427 + pPacket->data_len) / 2),
9428 + ((pPacket->len -
9429 + pPacket->data_len) / 2),
9430 + PCI_DMA_TODEVICE);
9431 + }
9432 + } else {
9433 + DBG_TX(et131x_dbginfo,
9434 + "Got packet of length %d,"
9435 + "filling desc entry %d\n"
9436 + "TCB: 0x%p\n",
9437 + pFragList[loopIndex].size,
9438 + pAdapter->TxRing.txDmaReadyToSend.bits.val,
9439 + pMpTcb);
9440 +
9441 + CurDesc[FragmentNumber].DataBufferPtrHigh = 0;
9442 +
9443 + CurDesc[FragmentNumber].word2.bits.length_in_bytes =
9444 + pFragList[loopIndex - 1].size;
9445 +
9446 + /* NOTE: Here, the dma_addr_t returned from
9447 + * pci_map_page() is implicitly cast as a uint32_t.
9448 + * Although dma_addr_t can be 64-bit, the address
9449 + * returned by pci_map_page() is always 32-bit
9450 + * addressable (as defined by the pci/dma subsystem)
9451 + */
9452 + CurDesc[FragmentNumber++].DataBufferPtrLow =
9453 + pci_map_page(pAdapter->pdev,
9454 + pFragList[loopIndex - 1].page,
9455 + pFragList[loopIndex - 1].page_offset,
9456 + pFragList[loopIndex - 1].size,
9457 + PCI_DMA_TODEVICE);
9458 + }
9459 + }
9460 +
9461 + if (FragmentNumber == 0) {
9462 + DBG_WARNING(et131x_dbginfo, "No. frags is 0\n");
9463 + return -EIO;
9464 + }
9465 +
9466 + if (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
9467 + if (++pAdapter->TxRing.TxPacketsSinceLastinterrupt ==
9468 + pAdapter->RegistryTxNumBuffers) {
9469 + CurDesc[FragmentNumber - 1].word3.value = 0x5;
9470 + pAdapter->TxRing.TxPacketsSinceLastinterrupt = 0;
9471 + } else {
9472 + CurDesc[FragmentNumber - 1].word3.value = 0x1;
9473 + }
9474 + } else {
9475 + CurDesc[FragmentNumber - 1].word3.value = 0x5;
9476 + }
9477 +
9478 + CurDesc[0].word3.bits.f = 1;
9479 +
9480 + pMpTcb->WrIndexStart = pAdapter->TxRing.txDmaReadyToSend;
9481 + pMpTcb->PacketStaleCount = 0;
9482 +
9483 + spin_lock_irqsave(&pAdapter->SendHWLock, lockflags1);
9484 +
9485 + iThisCopy =
9486 + NUM_DESC_PER_RING_TX - pAdapter->TxRing.txDmaReadyToSend.bits.val;
9487 +
9488 + if (iThisCopy >= FragmentNumber) {
9489 + iRemainder = 0;
9490 + iThisCopy = FragmentNumber;
9491 + } else {
9492 + iRemainder = FragmentNumber - iThisCopy;
9493 + }
9494 +
9495 + memcpy(pAdapter->TxRing.pTxDescRingVa +
9496 + pAdapter->TxRing.txDmaReadyToSend.bits.val, CurDesc,
9497 + sizeof(TX_DESC_ENTRY_t) * iThisCopy);
9498 +
9499 + pAdapter->TxRing.txDmaReadyToSend.bits.val += iThisCopy;
9500 +
9501 + if ((pAdapter->TxRing.txDmaReadyToSend.bits.val == 0) ||
9502 + (pAdapter->TxRing.txDmaReadyToSend.bits.val ==
9503 + NUM_DESC_PER_RING_TX)) {
9504 + if (pAdapter->TxRing.txDmaReadyToSend.bits.wrap) {
9505 + pAdapter->TxRing.txDmaReadyToSend.value = 0;
9506 + } else {
9507 + pAdapter->TxRing.txDmaReadyToSend.value = 0x400;
9508 + }
9509 + }
9510 +
9511 + if (iRemainder) {
9512 + memcpy(pAdapter->TxRing.pTxDescRingVa,
9513 + CurDesc + iThisCopy,
9514 + sizeof(TX_DESC_ENTRY_t) * iRemainder);
9515 +
9516 + pAdapter->TxRing.txDmaReadyToSend.bits.val += iRemainder;
9517 + }
9518 +
9519 + if (pAdapter->TxRing.txDmaReadyToSend.bits.val == 0) {
9520 + if (pAdapter->TxRing.txDmaReadyToSend.value) {
9521 + pMpTcb->WrIndex.value = NUM_DESC_PER_RING_TX - 1;
9522 + } else {
9523 + pMpTcb->WrIndex.value =
9524 + 0x400 | (NUM_DESC_PER_RING_TX - 1);
9525 + }
9526 + } else {
9527 + pMpTcb->WrIndex.value =
9528 + pAdapter->TxRing.txDmaReadyToSend.value - 1;
9529 + }
9530 +
9531 + spin_lock_irqsave(&pAdapter->TCBSendQLock, lockflags2);
9532 +
9533 + if (pAdapter->TxRing.CurrSendTail) {
9534 + pAdapter->TxRing.CurrSendTail->Next = pMpTcb;
9535 + } else {
9536 + pAdapter->TxRing.CurrSendHead = pMpTcb;
9537 + }
9538 +
9539 + pAdapter->TxRing.CurrSendTail = pMpTcb;
9540 +
9541 + DBG_ASSERT(pMpTcb->Next == NULL);
9542 +
9543 + pAdapter->TxRing.nBusySend++;
9544 +
9545 + spin_unlock_irqrestore(&pAdapter->TCBSendQLock, lockflags2);
9546 +
9547 + /* Write the new write pointer back to the device. */
9548 + writel(pAdapter->TxRing.txDmaReadyToSend.value,
9549 + &pAdapter->CSRAddress->txdma.service_request.value);
9550 +
9551 + /* For Gig only, we use Tx Interrupt coalescing. Enable the software
9552 + * timer to wake us up if this packet isn't followed by N more.
9553 + */
9554 + if (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
9555 + writel(pAdapter->RegistryTxTimeInterval * NANO_IN_A_MICRO,
9556 + &pAdapter->CSRAddress->global.watchdog_timer);
9557 + }
9558 +
9559 + spin_unlock_irqrestore(&pAdapter->SendHWLock, lockflags1);
9560 +
9561 + DBG_TX_LEAVE(et131x_dbginfo);
9562 + return 0;
9563 +}
9564 +
9565 +/*
9566 + * NOTE: For now, keep this older version of NICSendPacket around for
9567 + * reference, even though it's not used
9568 + */
9569 +#if 0
9570 +
9571 +/**
9572 + * NICSendPacket - NIC specific send handler.
9573 + * @pAdapter: pointer to our adapter
9574 + * @pMpTcb: pointer to MP_TCB
9575 + *
9576 + * Returns 0 on succes, errno on failure.
9577 + *
9578 + * This version of the send routine is designed for version A silicon.
9579 + * Assumption - Send spinlock has been acquired.
9580 + */
9581 +static int nic_send_packet(struct et131x_adapter *pAdapter, PMP_TCB pMpTcb)
9582 +{
9583 + uint32_t loopIndex, fragIndex, loopEnd;
9584 + uint32_t iSplitFirstElement = 0;
9585 + uint32_t SegmentSize = 0;
9586 + TX_DESC_ENTRY_t CurDesc;
9587 + TX_DESC_ENTRY_t *CurDescPostCopy = NULL;
9588 + uint32_t SlotsAvailable;
9589 + DMA10W_t ServiceComplete;
9590 + unsigned int lockflags1, lockflags2;
9591 + struct sk_buff *pPacket = pMpTcb->Packet;
9592 + uint32_t FragListCount = skb_shinfo(pPacket)->nr_frags + 1;
9593 + struct skb_frag_struct *pFragList = &skb_shinfo(pPacket)->frags[0];
9594 +
9595 + DBG_TX_ENTER(et131x_dbginfo);
9596 +
9597 + ServiceComplete.value =
9598 + readl(&pAdapter->CSRAddress->txdma.NewServiceComplete.value);
9599 +
9600 + /*
9601 + * Attempt to fix TWO hardware bugs:
9602 + * 1) NEVER write an odd number of descriptors.
9603 + * 2) If packet length is less than NIC_MIN_PACKET_SIZE, then pad the
9604 + * packet to NIC_MIN_PACKET_SIZE bytes by adding a new last
9605 + * descriptor IN HALF DUPLEX MODE ONLY
9606 + * NOTE that (2) interacts with (1). If the packet is less than
9607 + * NIC_MIN_PACKET_SIZE bytes then we will append a descriptor.
9608 + * Therefore if it is even now, it will eventually end up odd, and
9609 + * so will need adjusting.
9610 + *
9611 + * VLAN tags get involved since VLAN tags add another one or two
9612 + * segments.
9613 + */
9614 + DBG_TX(et131x_dbginfo,
9615 + "pMpTcb->PacketLength: %d\n", pMpTcb->PacketLength);
9616 +
9617 + if ((pAdapter->uiDuplexMode == 0)
9618 + && (pMpTcb->PacketLength < NIC_MIN_PACKET_SIZE)) {
9619 + DBG_TX(et131x_dbginfo,
9620 + "HALF DUPLEX mode AND len < MIN_PKT_SIZE\n");
9621 + if ((FragListCount & 0x1) == 0) {
9622 + DBG_TX(et131x_dbginfo,
9623 + "Even number of descs, split 1st elem\n");
9624 + iSplitFirstElement = 1;
9625 + //SegmentSize = pFragList[0].size / 2;
9626 + SegmentSize = (pPacket->len - pPacket->data_len) / 2;
9627 + }
9628 + } else if (FragListCount & 0x1) {
9629 + DBG_TX(et131x_dbginfo, "Odd number of descs, split 1st elem\n");
9630 +
9631 + iSplitFirstElement = 1;
9632 + //SegmentSize = pFragList[0].size / 2;
9633 + SegmentSize = (pPacket->len - pPacket->data_len) / 2;
9634 + }
9635 +
9636 + spin_lock_irqsave(&pAdapter->SendHWLock, lockflags1);
9637 +
9638 + if (pAdapter->TxRing.txDmaReadyToSend.bits.serv_req_wrap ==
9639 + ServiceComplete.bits.serv_cpl_wrap) {
9640 + /* The ring hasn't wrapped. Slots available should be
9641 + * (RING_SIZE) - the difference between the two pointers.
9642 + */
9643 + SlotsAvailable = NUM_DESC_PER_RING_TX -
9644 + (pAdapter->TxRing.txDmaReadyToSend.bits.serv_req -
9645 + ServiceComplete.bits.serv_cpl);
9646 + } else {
9647 + /* The ring has wrapped. Slots available should be the
9648 + * difference between the two pointers.
9649 + */
9650 + SlotsAvailable = ServiceComplete.bits.serv_cpl -
9651 + pAdapter->TxRing.txDmaReadyToSend.bits.serv_req;
9652 + }
9653 +
9654 + if ((FragListCount + iSplitFirstElement) > SlotsAvailable) {
9655 + DBG_WARNING(et131x_dbginfo,
9656 + "Not Enough Space in Tx Desc Ring\n");
9657 + spin_unlock_irqrestore(&pAdapter->SendHWLock, lockflags1);
9658 + return -ENOMEM;
9659 + }
9660 +
9661 + loopEnd = (FragListCount) + iSplitFirstElement;
9662 + fragIndex = 0;
9663 +
9664 + DBG_TX(et131x_dbginfo,
9665 + "TCB : 0x%p\n"
9666 + "Packet (SKB) : 0x%p\t Packet->len: %d\t Packet->data_len: %d\n"
9667 + "FragListCount : %d\t iSplitFirstElement: %d\t loopEnd:%d\n",
9668 + pMpTcb,
9669 + pPacket, pPacket->len, pPacket->data_len,
9670 + FragListCount, iSplitFirstElement, loopEnd);
9671 +
9672 + for (loopIndex = 0; loopIndex < loopEnd; loopIndex++) {
9673 + if (loopIndex > iSplitFirstElement) {
9674 + fragIndex++;
9675 + }
9676 +
9677 + DBG_TX(et131x_dbginfo,
9678 + "In loop, loopIndex: %d\t fragIndex: %d\n", loopIndex,
9679 + fragIndex);
9680 +
9681 + /* If there is something in this element, let's get a
9682 + * descriptor from the ring and get the necessary data
9683 + */
9684 + DBG_TX(et131x_dbginfo,
9685 + "Packet Length %d,"
9686 + "filling desc entry %d\n",
9687 + pPacket->len,
9688 + pAdapter->TxRing.txDmaReadyToSend.bits.serv_req);
9689 +
9690 + // NOTE - Should we do a paranoia check here to make sure the fragment
9691 + // actually has a length? It's HIGHLY unlikely the fragment would
9692 + // contain no data...
9693 + if (1) {
9694 + // NOTE - Currently always getting 32-bit addrs, and dma_addr_t is
9695 + // only 32-bit, so leave "high" ptr value out for now
9696 + CurDesc.DataBufferPtrHigh = 0;
9697 +
9698 + CurDesc.word2.value = 0;
9699 + CurDesc.word3.value = 0;
9700 +
9701 + if (fragIndex == 0) {
9702 + if (iSplitFirstElement) {
9703 + DBG_TX(et131x_dbginfo,
9704 + "Split first element: YES\n");
9705 +
9706 + if (loopIndex == 0) {
9707 + DBG_TX(et131x_dbginfo,
9708 + "Got fragment of length %d, fragIndex: %d\n",
9709 + pPacket->len -
9710 + pPacket->data_len,
9711 + fragIndex);
9712 + DBG_TX(et131x_dbginfo,
9713 + "SegmentSize: %d\n",
9714 + SegmentSize);
9715 +
9716 + CurDesc.word2.bits.
9717 + length_in_bytes =
9718 + SegmentSize;
9719 + CurDesc.DataBufferPtrLow =
9720 + pci_map_single(pAdapter->
9721 + pdev,
9722 + pPacket->
9723 + data,
9724 + SegmentSize,
9725 + PCI_DMA_TODEVICE);
9726 + DBG_TX(et131x_dbginfo,
9727 + "pci_map_single() returns: 0x%08x\n",
9728 + CurDesc.
9729 + DataBufferPtrLow);
9730 + } else {
9731 + DBG_TX(et131x_dbginfo,
9732 + "Got fragment of length %d, fragIndex: %d\n",
9733 + pPacket->len -
9734 + pPacket->data_len,
9735 + fragIndex);
9736 + DBG_TX(et131x_dbginfo,
9737 + "Leftover Size: %d\n",
9738 + (pPacket->len -
9739 + pPacket->data_len -
9740 + SegmentSize));
9741 +
9742 + CurDesc.word2.bits.
9743 + length_in_bytes =
9744 + ((pPacket->len -
9745 + pPacket->data_len) -
9746 + SegmentSize);
9747 + CurDesc.DataBufferPtrLow =
9748 + pci_map_single(pAdapter->
9749 + pdev,
9750 + (pPacket->
9751 + data +
9752 + SegmentSize),
9753 + (pPacket->
9754 + len -
9755 + pPacket->
9756 + data_len -
9757 + SegmentSize),
9758 + PCI_DMA_TODEVICE);
9759 + DBG_TX(et131x_dbginfo,
9760 + "pci_map_single() returns: 0x%08x\n",
9761 + CurDesc.
9762 + DataBufferPtrLow);
9763 + }
9764 + } else {
9765 + DBG_TX(et131x_dbginfo,
9766 + "Split first element: NO\n");
9767 +
9768 + CurDesc.word2.bits.length_in_bytes =
9769 + pPacket->len - pPacket->data_len;
9770 +
9771 + CurDesc.DataBufferPtrLow =
9772 + pci_map_single(pAdapter->pdev,
9773 + pPacket->data,
9774 + (pPacket->len -
9775 + pPacket->data_len),
9776 + PCI_DMA_TODEVICE);
9777 + DBG_TX(et131x_dbginfo,
9778 + "pci_map_single() returns: 0x%08x\n",
9779 + CurDesc.DataBufferPtrLow);
9780 + }
9781 + } else {
9782 +
9783 + CurDesc.word2.bits.length_in_bytes =
9784 + pFragList[fragIndex - 1].size;
9785 + CurDesc.DataBufferPtrLow =
9786 + pci_map_page(pAdapter->pdev,
9787 + pFragList[fragIndex - 1].page,
9788 + pFragList[fragIndex -
9789 + 1].page_offset,
9790 + pFragList[fragIndex - 1].size,
9791 + PCI_DMA_TODEVICE);
9792 + DBG_TX(et131x_dbginfo,
9793 + "pci_map_page() returns: 0x%08x\n",
9794 + CurDesc.DataBufferPtrLow);
9795 + }
9796 +
9797 + if (loopIndex == 0) {
9798 + /* This is the first descriptor of the packet
9799 + *
9800 + * Set the "f" bit to indicate this is the
9801 + * first descriptor in the packet.
9802 + */
9803 + DBG_TX(et131x_dbginfo,
9804 + "This is our FIRST descriptor\n");
9805 + CurDesc.word3.bits.f = 1;
9806 +
9807 + pMpTcb->WrIndexStart =
9808 + pAdapter->TxRing.txDmaReadyToSend;
9809 + }
9810 +
9811 + if ((loopIndex == (loopEnd - 1)) &&
9812 + (pAdapter->uiDuplexMode ||
9813 + (pMpTcb->PacketLength >= NIC_MIN_PACKET_SIZE))) {
9814 + /* This is the Last descriptor of the packet */
9815 + DBG_TX(et131x_dbginfo,
9816 + "THIS is our LAST descriptor\n");
9817 +
9818 + if (pAdapter->uiLinkSpeed ==
9819 + TRUEPHY_SPEED_1000MBPS) {
9820 + if (++pAdapter->TxRing.
9821 + TxPacketsSinceLastinterrupt >=
9822 + pAdapter->RegistryTxNumBuffers) {
9823 + CurDesc.word3.value = 0x5;
9824 + pAdapter->TxRing.
9825 + TxPacketsSinceLastinterrupt
9826 + = 0;
9827 + } else {
9828 + CurDesc.word3.value = 0x1;
9829 + }
9830 + } else {
9831 + CurDesc.word3.value = 0x5;
9832 + }
9833 +
9834 + /* Following index will be used during freeing
9835 + * of packet
9836 + */
9837 + pMpTcb->WrIndex =
9838 + pAdapter->TxRing.txDmaReadyToSend;
9839 + pMpTcb->PacketStaleCount = 0;
9840 + }
9841 +
9842 + /* Copy the descriptor (filled above) into the
9843 + * descriptor ring at the next free entry. Advance
9844 + * the "next free entry" variable
9845 + */
9846 + memcpy(pAdapter->TxRing.pTxDescRingVa +
9847 + pAdapter->TxRing.txDmaReadyToSend.bits.serv_req,
9848 + &CurDesc, sizeof(TX_DESC_ENTRY_t));
9849 +
9850 + CurDescPostCopy =
9851 + pAdapter->TxRing.pTxDescRingVa +
9852 + pAdapter->TxRing.txDmaReadyToSend.bits.serv_req;
9853 +
9854 + DBG_TX(et131x_dbginfo,
9855 + "CURRENT DESCRIPTOR\n"
9856 + "\tAddress : 0x%p\n"
9857 + "\tDataBufferPtrHigh : 0x%08x\n"
9858 + "\tDataBufferPtrLow : 0x%08x\n"
9859 + "\tword2 : 0x%08x\n"
9860 + "\tword3 : 0x%08x\n",
9861 + CurDescPostCopy,
9862 + CurDescPostCopy->DataBufferPtrHigh,
9863 + CurDescPostCopy->DataBufferPtrLow,
9864 + CurDescPostCopy->word2.value,
9865 + CurDescPostCopy->word3.value);
9866 +
9867 + if (++pAdapter->TxRing.txDmaReadyToSend.bits.serv_req >=
9868 + NUM_DESC_PER_RING_TX) {
9869 + if (pAdapter->TxRing.txDmaReadyToSend.bits.
9870 + serv_req_wrap) {
9871 + pAdapter->TxRing.txDmaReadyToSend.
9872 + value = 0;
9873 + } else {
9874 + pAdapter->TxRing.txDmaReadyToSend.
9875 + value = 0x400;
9876 + }
9877 + }
9878 + }
9879 + }
9880 +
9881 + if (pAdapter->uiDuplexMode == 0 &&
9882 + pMpTcb->PacketLength < NIC_MIN_PACKET_SIZE) {
9883 + // NOTE - Same 32/64-bit issue as above...
9884 + CurDesc.DataBufferPtrHigh = 0x0;
9885 + CurDesc.DataBufferPtrLow = pAdapter->TxRing.pTxDummyBlkPa;
9886 + CurDesc.word2.value = 0;
9887 +
9888 + if (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
9889 + if (++pAdapter->TxRing.TxPacketsSinceLastinterrupt >=
9890 + pAdapter->RegistryTxNumBuffers) {
9891 + CurDesc.word3.value = 0x5;
9892 + pAdapter->TxRing.TxPacketsSinceLastinterrupt =
9893 + 0;
9894 + } else {
9895 + CurDesc.word3.value = 0x1;
9896 + }
9897 + } else {
9898 + CurDesc.word3.value = 0x5;
9899 + }
9900 +
9901 + CurDesc.word2.bits.length_in_bytes =
9902 + NIC_MIN_PACKET_SIZE - pMpTcb->PacketLength;
9903 +
9904 + pMpTcb->WrIndex = pAdapter->TxRing.txDmaReadyToSend;
9905 +
9906 + memcpy(pAdapter->TxRing.pTxDescRingVa +
9907 + pAdapter->TxRing.txDmaReadyToSend.bits.serv_req,
9908 + &CurDesc, sizeof(TX_DESC_ENTRY_t));
9909 +
9910 + CurDescPostCopy =
9911 + pAdapter->TxRing.pTxDescRingVa +
9912 + pAdapter->TxRing.txDmaReadyToSend.bits.serv_req;
9913 +
9914 + DBG_TX(et131x_dbginfo,
9915 + "CURRENT DESCRIPTOR\n"
9916 + "\tAddress : 0x%p\n"
9917 + "\tDataBufferPtrHigh : 0x%08x\n"
9918 + "\tDataBufferPtrLow : 0x%08x\n"
9919 + "\tword2 : 0x%08x\n"
9920 + "\tword3 : 0x%08x\n",
9921 + CurDescPostCopy,
9922 + CurDescPostCopy->DataBufferPtrHigh,
9923 + CurDescPostCopy->DataBufferPtrLow,
9924 + CurDescPostCopy->word2.value,
9925 + CurDescPostCopy->word3.value);
9926 +
9927 + if (++pAdapter->TxRing.txDmaReadyToSend.bits.serv_req >=
9928 + NUM_DESC_PER_RING_TX) {
9929 + if (pAdapter->TxRing.txDmaReadyToSend.bits.
9930 + serv_req_wrap) {
9931 + pAdapter->TxRing.txDmaReadyToSend.value = 0;
9932 + } else {
9933 + pAdapter->TxRing.txDmaReadyToSend.value = 0x400;
9934 + }
9935 + }
9936 +
9937 + DBG_TX(et131x_dbginfo, "Padding descriptor %d by %d bytes\n",
9938 + //pAdapter->TxRing.txDmaReadyToSend.value,
9939 + pAdapter->TxRing.txDmaReadyToSend.bits.serv_req,
9940 + NIC_MIN_PACKET_SIZE - pMpTcb->PacketLength);
9941 + }
9942 +
9943 + spin_lock_irqsave(&pAdapter->TCBSendQLock, lockflags2);
9944 +
9945 + if (pAdapter->TxRing.CurrSendTail) {
9946 + pAdapter->TxRing.CurrSendTail->Next = pMpTcb;
9947 + } else {
9948 + pAdapter->TxRing.CurrSendHead = pMpTcb;
9949 + }
9950 +
9951 + pAdapter->TxRing.CurrSendTail = pMpTcb;
9952 +
9953 + DBG_ASSERT(pMpTcb->Next == NULL);
9954 +
9955 + pAdapter->TxRing.nBusySend++;
9956 +
9957 + spin_unlock_irqrestore(&pAdapter->TCBSendQLock, lockflags2);
9958 +
9959 + /* Write the new write pointer back to the device. */
9960 + writel(pAdapter->TxRing.txDmaReadyToSend.value,
9961 + &pAdapter->CSRAddress->txdma.service_request.value);
9962 +
9963 +#ifdef CONFIG_ET131X_DEBUG
9964 + DumpDeviceBlock(DBG_TX_ON, pAdapter, 1);
9965 +#endif
9966 +
9967 + /* For Gig only, we use Tx Interrupt coalescing. Enable the software
9968 + * timer to wake us up if this packet isn't followed by N more.
9969 + */
9970 + if (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
9971 + writel(pAdapter->RegistryTxTimeInterval * NANO_IN_A_MICRO,
9972 + &pAdapter->CSRAddress->global.watchdog_timer);
9973 + }
9974 +
9975 + spin_unlock_irqrestore(&pAdapter->SendHWLock, lockflags1);
9976 +
9977 + DBG_TX_LEAVE(et131x_dbginfo);
9978 + return 0;
9979 +}
9980 +
9981 +#endif
9982 +
9983 +/**
9984 + * et131x_free_send_packet - Recycle a MP_TCB, complete the packet if necessary
9985 + * @pAdapter: pointer to our adapter
9986 + * @pMpTcb: pointer to MP_TCB
9987 + *
9988 + * Assumption - Send spinlock has been acquired
9989 + */
9990 +__inline void et131x_free_send_packet(struct et131x_adapter *pAdapter, PMP_TCB pMpTcb)
9991 +{
9992 + unsigned long lockflags;
9993 + TX_DESC_ENTRY_t *desc = NULL;
9994 + struct net_device_stats *stats = &pAdapter->net_stats;
9995 +
9996 + if (MP_TEST_FLAG(pMpTcb, fMP_DEST_BROAD)) {
9997 + atomic_inc(&pAdapter->Stats.brdcstxmt);
9998 + } else if (MP_TEST_FLAG(pMpTcb, fMP_DEST_MULTI)) {
9999 + atomic_inc(&pAdapter->Stats.multixmt);
10000 + } else {
10001 + atomic_inc(&pAdapter->Stats.unixmt);
10002 + }
10003 +
10004 + if (pMpTcb->Packet) {
10005 + stats->tx_bytes += pMpTcb->Packet->len;
10006 +
10007 + /* Iterate through the TX descriptors on the ring
10008 + * corresponding to this packet and umap the fragments
10009 + * they point to
10010 + */
10011 + DBG_TX(et131x_dbginfo,
10012 + "Unmap descriptors Here\n"
10013 + "TCB : 0x%p\n"
10014 + "TCB Next : 0x%p\n"
10015 + "TCB PacketLength : %d\n"
10016 + "TCB WrIndex.value : 0x%08x\n"
10017 + "TCB WrIndex.bits.val : %d\n"
10018 + "TCB WrIndex.value : 0x%08x\n"
10019 + "TCB WrIndex.bits.val : %d\n",
10020 + pMpTcb,
10021 + pMpTcb->Next,
10022 + pMpTcb->PacketLength,
10023 + pMpTcb->WrIndexStart.value,
10024 + pMpTcb->WrIndexStart.bits.val,
10025 + pMpTcb->WrIndex.value,
10026 + pMpTcb->WrIndex.bits.val);
10027 +
10028 + do {
10029 + desc =
10030 + (TX_DESC_ENTRY_t *) (pAdapter->TxRing.
10031 + pTxDescRingVa +
10032 + pMpTcb->WrIndexStart.bits.val);
10033 +
10034 + DBG_TX(et131x_dbginfo,
10035 + "CURRENT DESCRIPTOR\n"
10036 + "\tAddress : 0x%p\n"
10037 + "\tDataBufferPtrHigh : 0x%08x\n"
10038 + "\tDataBufferPtrLow : 0x%08x\n"
10039 + "\tword2 : 0x%08x\n"
10040 + "\tword3 : 0x%08x\n",
10041 + desc,
10042 + desc->DataBufferPtrHigh,
10043 + desc->DataBufferPtrLow,
10044 + desc->word2.value,
10045 + desc->word3.value);
10046 +
10047 + pci_unmap_single(pAdapter->pdev,
10048 + desc->DataBufferPtrLow,
10049 + desc->word2.value, PCI_DMA_TODEVICE);
10050 +
10051 + if (++pMpTcb->WrIndexStart.bits.val >=
10052 + NUM_DESC_PER_RING_TX) {
10053 + if (pMpTcb->WrIndexStart.bits.wrap) {
10054 + pMpTcb->WrIndexStart.value = 0;
10055 + } else {
10056 + pMpTcb->WrIndexStart.value = 0x400;
10057 + }
10058 + }
10059 + }
10060 + while (desc != (pAdapter->TxRing.pTxDescRingVa +
10061 + pMpTcb->WrIndex.bits.val));
10062 +
10063 + DBG_TX(et131x_dbginfo,
10064 + "Free Packet (SKB) : 0x%p\n", pMpTcb->Packet);
10065 +
10066 + dev_kfree_skb_any(pMpTcb->Packet);
10067 + }
10068 +
10069 + memset(pMpTcb, 0, sizeof(MP_TCB));
10070 +
10071 + /* Add the TCB to the Ready Q */
10072 + spin_lock_irqsave(&pAdapter->TCBReadyQLock, lockflags);
10073 +
10074 + pAdapter->Stats.opackets++;
10075 +
10076 + if (pAdapter->TxRing.TCBReadyQueueTail) {
10077 + pAdapter->TxRing.TCBReadyQueueTail->Next = pMpTcb;
10078 + } else {
10079 + /* Apparently ready Q is empty. */
10080 + pAdapter->TxRing.TCBReadyQueueHead = pMpTcb;
10081 + }
10082 +
10083 + pAdapter->TxRing.TCBReadyQueueTail = pMpTcb;
10084 +
10085 + spin_unlock_irqrestore(&pAdapter->TCBReadyQLock, lockflags);
10086 +
10087 + DBG_ASSERT(pAdapter->TxRing.nBusySend >= 0);
10088 +}
10089 +
10090 +/**
10091 + * et131x_free_busy_send_packets - Free and complete the stopped active sends
10092 + * @pAdapter: pointer to our adapter
10093 + *
10094 + * Assumption - Send spinlock has been acquired
10095 + */
10096 +void et131x_free_busy_send_packets(struct et131x_adapter *pAdapter)
10097 +{
10098 + PMP_TCB pMpTcb;
10099 + struct list_head *pEntry;
10100 + struct sk_buff *pPacket = NULL;
10101 + unsigned long lockflags;
10102 + uint32_t FreeCounter = 0;
10103 +
10104 + DBG_ENTER(et131x_dbginfo);
10105 +
10106 + while (!list_empty(&pAdapter->TxRing.SendWaitQueue)) {
10107 + spin_lock_irqsave(&pAdapter->SendWaitLock, lockflags);
10108 +
10109 + pAdapter->TxRing.nWaitSend--;
10110 + spin_unlock_irqrestore(&pAdapter->SendWaitLock, lockflags);
10111 +
10112 + pEntry = pAdapter->TxRing.SendWaitQueue.next;
10113 +
10114 + pPacket = NULL;
10115 + }
10116 +
10117 + pAdapter->TxRing.nWaitSend = 0;
10118 +
10119 + /* Any packets being sent? Check the first TCB on the send list */
10120 + spin_lock_irqsave(&pAdapter->TCBSendQLock, lockflags);
10121 +
10122 + pMpTcb = pAdapter->TxRing.CurrSendHead;
10123 +
10124 + while ((pMpTcb != NULL) && (FreeCounter < NUM_TCB)) {
10125 + PMP_TCB pNext = pMpTcb->Next;
10126 +
10127 + pAdapter->TxRing.CurrSendHead = pNext;
10128 +
10129 + if (pNext == NULL) {
10130 + pAdapter->TxRing.CurrSendTail = NULL;
10131 + }
10132 +
10133 + pAdapter->TxRing.nBusySend--;
10134 +
10135 + spin_unlock_irqrestore(&pAdapter->TCBSendQLock, lockflags);
10136 +
10137 + DBG_VERBOSE(et131x_dbginfo, "pMpTcb = 0x%p\n", pMpTcb);
10138 +
10139 + FreeCounter++;
10140 + MP_FREE_SEND_PACKET_FUN(pAdapter, pMpTcb);
10141 +
10142 + spin_lock_irqsave(&pAdapter->TCBSendQLock, lockflags);
10143 +
10144 + pMpTcb = pAdapter->TxRing.CurrSendHead;
10145 + }
10146 +
10147 + if (FreeCounter == NUM_TCB) {
10148 + DBG_ERROR(et131x_dbginfo,
10149 + "MpFreeBusySendPackets exitted loop for a bad reason\n");
10150 + BUG();
10151 + }
10152 +
10153 + spin_unlock_irqrestore(&pAdapter->TCBSendQLock, lockflags);
10154 +
10155 + pAdapter->TxRing.nBusySend = 0;
10156 +
10157 + DBG_LEAVE(et131x_dbginfo);
10158 +}
10159 +
10160 +/**
10161 + * et131x_handle_send_interrupt - Interrupt handler for sending processing
10162 + * @pAdapter: pointer to our adapter
10163 + *
10164 + * Re-claim the send resources, complete sends and get more to send from
10165 + * the send wait queue.
10166 + *
10167 + * Assumption - Send spinlock has been acquired
10168 + */
10169 +void et131x_handle_send_interrupt(struct et131x_adapter *pAdapter)
10170 +{
10171 + DBG_TX_ENTER(et131x_dbginfo);
10172 +
10173 + /* Mark as completed any packets which have been sent by the device. */
10174 + et131x_update_tcb_list(pAdapter);
10175 +
10176 + /* If we queued any transmits because we didn't have any TCBs earlier,
10177 + * dequeue and send those packets now, as long as we have free TCBs.
10178 + */
10179 + et131x_check_send_wait_list(pAdapter);
10180 +
10181 + DBG_TX_LEAVE(et131x_dbginfo);
10182 +}
10183 +
10184 +/**
10185 + * et131x_update_tcb_list - Helper routine for Send Interrupt handler
10186 + * @pAdapter: pointer to our adapter
10187 + *
10188 + * Re-claims the send resources and completes sends. Can also be called as
10189 + * part of the NIC send routine when the "ServiceComplete" indication has
10190 + * wrapped.
10191 + */
10192 +static void et131x_update_tcb_list(struct et131x_adapter *pAdapter)
10193 +{
10194 + unsigned long lockflags;
10195 + DMA10W_t ServiceComplete;
10196 + PMP_TCB pMpTcb;
10197 +
10198 + ServiceComplete.value =
10199 + readl(&pAdapter->CSRAddress->txdma.NewServiceComplete.value);
10200 +
10201 + /* Has the ring wrapped? Process any descriptors that do not have
10202 + * the same "wrap" indicator as the current completion indicator
10203 + */
10204 + spin_lock_irqsave(&pAdapter->TCBSendQLock, lockflags);
10205 +
10206 + pMpTcb = pAdapter->TxRing.CurrSendHead;
10207 + while (pMpTcb &&
10208 + ServiceComplete.bits.wrap != pMpTcb->WrIndex.bits.wrap &&
10209 + ServiceComplete.bits.val < pMpTcb->WrIndex.bits.val) {
10210 + pAdapter->TxRing.nBusySend--;
10211 + pAdapter->TxRing.CurrSendHead = pMpTcb->Next;
10212 + if (pMpTcb->Next == NULL) {
10213 + pAdapter->TxRing.CurrSendTail = NULL;
10214 + }
10215 +
10216 + spin_unlock_irqrestore(&pAdapter->TCBSendQLock, lockflags);
10217 + MP_FREE_SEND_PACKET_FUN(pAdapter, pMpTcb);
10218 + spin_lock_irqsave(&pAdapter->TCBSendQLock, lockflags);
10219 +
10220 + /* Goto the next packet */
10221 + pMpTcb = pAdapter->TxRing.CurrSendHead;
10222 + }
10223 + while (pMpTcb &&
10224 + ServiceComplete.bits.wrap == pMpTcb->WrIndex.bits.wrap &&
10225 + ServiceComplete.bits.val > pMpTcb->WrIndex.bits.val) {
10226 + pAdapter->TxRing.nBusySend--;
10227 + pAdapter->TxRing.CurrSendHead = pMpTcb->Next;
10228 + if (pMpTcb->Next == NULL) {
10229 + pAdapter->TxRing.CurrSendTail = NULL;
10230 + }
10231 +
10232 + spin_unlock_irqrestore(&pAdapter->TCBSendQLock, lockflags);
10233 + MP_FREE_SEND_PACKET_FUN(pAdapter, pMpTcb);
10234 + spin_lock_irqsave(&pAdapter->TCBSendQLock, lockflags);
10235 +
10236 + /* Goto the next packet */
10237 + pMpTcb = pAdapter->TxRing.CurrSendHead;
10238 + }
10239 +
10240 + /* Wake up the queue when we hit a low-water mark */
10241 + if (pAdapter->TxRing.nBusySend <= (NUM_TCB / 3)) {
10242 + netif_wake_queue(pAdapter->netdev);
10243 + }
10244 +
10245 + spin_unlock_irqrestore(&pAdapter->TCBSendQLock, lockflags);
10246 +}
10247 +
10248 +/**
10249 + * et131x_check_send_wait_list - Helper routine for the interrupt handler
10250 + * @pAdapter: pointer to our adapter
10251 + *
10252 + * Takes packets from the send wait queue and posts them to the device (if
10253 + * room available).
10254 + */
10255 +static void et131x_check_send_wait_list(struct et131x_adapter *pAdapter)
10256 +{
10257 + unsigned long lockflags;
10258 +
10259 + spin_lock_irqsave(&pAdapter->SendWaitLock, lockflags);
10260 +
10261 + while (!list_empty(&pAdapter->TxRing.SendWaitQueue) &&
10262 + MP_TCB_RESOURCES_AVAILABLE(pAdapter)) {
10263 + struct list_head *pEntry;
10264 +
10265 + DBG_VERBOSE(et131x_dbginfo, "Tx packets on the wait queue\n");
10266 +
10267 + pEntry = pAdapter->TxRing.SendWaitQueue.next;
10268 +
10269 + pAdapter->TxRing.nWaitSend--;
10270 +
10271 + DBG_WARNING(et131x_dbginfo,
10272 + "MpHandleSendInterrupt - sent a queued pkt. Waiting %d\n",
10273 + pAdapter->TxRing.nWaitSend);
10274 + }
10275 +
10276 + spin_unlock_irqrestore(&pAdapter->SendWaitLock, lockflags);
10277 +}
10278 diff --git a/drivers/staging/et131x/et1310_tx.h b/drivers/staging/et131x/et1310_tx.h
10279 new file mode 100644
10280 index 0000000..2819c78
10281 --- /dev/null
10282 +++ b/drivers/staging/et131x/et1310_tx.h
10283 @@ -0,0 +1,242 @@
10284 +/*
10285 + * Agere Systems Inc.
10286 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
10287 + *
10288 + * Copyright © 2005 Agere Systems Inc.
10289 + * All rights reserved.
10290 + * http://www.agere.com
10291 + *
10292 + *------------------------------------------------------------------------------
10293 + *
10294 + * et1310_tx.h - Defines, structs, enums, prototypes, etc. pertaining to data
10295 + * transmission.
10296 + *
10297 + *------------------------------------------------------------------------------
10298 + *
10299 + * SOFTWARE LICENSE
10300 + *
10301 + * This software is provided subject to the following terms and conditions,
10302 + * which you should read carefully before using the software. Using this
10303 + * software indicates your acceptance of these terms and conditions. If you do
10304 + * not agree with these terms and conditions, do not use the software.
10305 + *
10306 + * Copyright © 2005 Agere Systems Inc.
10307 + * All rights reserved.
10308 + *
10309 + * Redistribution and use in source or binary forms, with or without
10310 + * modifications, are permitted provided that the following conditions are met:
10311 + *
10312 + * . Redistributions of source code must retain the above copyright notice, this
10313 + * list of conditions and the following Disclaimer as comments in the code as
10314 + * well as in the documentation and/or other materials provided with the
10315 + * distribution.
10316 + *
10317 + * . Redistributions in binary form must reproduce the above copyright notice,
10318 + * this list of conditions and the following Disclaimer in the documentation
10319 + * and/or other materials provided with the distribution.
10320 + *
10321 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
10322 + * may be used to endorse or promote products derived from this software
10323 + * without specific prior written permission.
10324 + *
10325 + * Disclaimer
10326 + *
10327 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
10328 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
10329 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
10330 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
10331 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
10332 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10333 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
10334 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
10335 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
10336 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
10337 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
10338 + * DAMAGE.
10339 + *
10340 + */
10341 +
10342 +#ifndef __ET1310_TX_H__
10343 +#define __ET1310_TX_H__
10344 +
10345 +
10346 +/* Typedefs for Tx Descriptor Ring */
10347 +
10348 +/*
10349 + * TXDESC_WORD2_t structure holds part of the control bits in the Tx Descriptor
10350 + * ring for the ET-1310
10351 + */
10352 +typedef union _txdesc_word2_t {
10353 + u32 value;
10354 + struct {
10355 +#ifdef _BIT_FIELDS_HTOL
10356 + u32 vlan_prio:3; // bits 29-31(VLAN priority)
10357 + u32 vlan_cfi:1; // bit 28(cfi)
10358 + u32 vlan_tag:12; // bits 16-27(VLAN tag)
10359 + u32 length_in_bytes:16; // bits 0-15(packet length)
10360 +#else
10361 + u32 length_in_bytes:16; // bits 0-15(packet length)
10362 + u32 vlan_tag:12; // bits 16-27(VLAN tag)
10363 + u32 vlan_cfi:1; // bit 28(cfi)
10364 + u32 vlan_prio:3; // bits 29-31(VLAN priority)
10365 +#endif /* _BIT_FIELDS_HTOL */
10366 + } bits;
10367 +} TXDESC_WORD2_t, *PTXDESC_WORD2_t;
10368 +
10369 +/*
10370 + * TXDESC_WORD3_t structure holds part of the control bits in the Tx Descriptor
10371 + * ring for the ET-1310
10372 + */
10373 +typedef union _txdesc_word3_t {
10374 + u32 value;
10375 + struct {
10376 +#ifdef _BIT_FIELDS_HTOL
10377 + u32 unused:17; // bits 15-31
10378 + u32 udpa:1; // bit 14(UDP checksum assist)
10379 + u32 tcpa:1; // bit 13(TCP checksum assist)
10380 + u32 ipa:1; // bit 12(IP checksum assist)
10381 + u32 vlan:1; // bit 11(append VLAN tag)
10382 + u32 hp:1; // bit 10(Packet is a Huge packet)
10383 + u32 pp:1; // bit 9(pad packet)
10384 + u32 mac:1; // bit 8(MAC override)
10385 + u32 crc:1; // bit 7(append CRC)
10386 + u32 e:1; // bit 6(Tx frame has error)
10387 + u32 pf:1; // bit 5(send pause frame)
10388 + u32 bp:1; // bit 4(Issue half-duplex backpressure (XON/XOFF)
10389 + u32 cw:1; // bit 3(Control word - no packet data)
10390 + u32 ir:1; // bit 2(interrupt the processor when this pkt sent)
10391 + u32 f:1; // bit 1(first packet in the sequence)
10392 + u32 l:1; // bit 0(last packet in the sequence)
10393 +#else
10394 + u32 l:1; // bit 0(last packet in the sequence)
10395 + u32 f:1; // bit 1(first packet in the sequence)
10396 + u32 ir:1; // bit 2(interrupt the processor when this pkt sent)
10397 + u32 cw:1; // bit 3(Control word - no packet data)
10398 + u32 bp:1; // bit 4(Issue half-duplex backpressure (XON/XOFF)
10399 + u32 pf:1; // bit 5(send pause frame)
10400 + u32 e:1; // bit 6(Tx frame has error)
10401 + u32 crc:1; // bit 7(append CRC)
10402 + u32 mac:1; // bit 8(MAC override)
10403 + u32 pp:1; // bit 9(pad packet)
10404 + u32 hp:1; // bit 10(Packet is a Huge packet)
10405 + u32 vlan:1; // bit 11(append VLAN tag)
10406 + u32 ipa:1; // bit 12(IP checksum assist)
10407 + u32 tcpa:1; // bit 13(TCP checksum assist)
10408 + u32 udpa:1; // bit 14(UDP checksum assist)
10409 + u32 unused:17; // bits 15-31
10410 +#endif /* _BIT_FIELDS_HTOL */
10411 + } bits;
10412 +} TXDESC_WORD3_t, *PTXDESC_WORD3_t;
10413 +
10414 +/* TX_DESC_ENTRY_t is sructure representing each descriptor on the ring */
10415 +typedef struct _tx_desc_entry_t {
10416 + u32 DataBufferPtrHigh;
10417 + u32 DataBufferPtrLow;
10418 + TXDESC_WORD2_t word2; // control words how to xmit the
10419 + TXDESC_WORD3_t word3; // data (detailed above)
10420 +} TX_DESC_ENTRY_t, *PTX_DESC_ENTRY_t;
10421 +
10422 +
10423 +/* Typedefs for Tx DMA engine status writeback */
10424 +
10425 +/*
10426 + * TX_STATUS_BLOCK_t is sructure representing the status of the Tx DMA engine
10427 + * it sits in free memory, and is pointed to by 0x101c / 0x1020
10428 + */
10429 +typedef union _tx_status_block_t {
10430 + u32 value;
10431 + struct {
10432 +#ifdef _BIT_FIELDS_HTOL
10433 + u32 unused:21; // bits 11-31
10434 + u32 serv_cpl_wrap:1; // bit 10
10435 + u32 serv_cpl:10; // bits 0-9
10436 +#else
10437 + u32 serv_cpl:10; // bits 0-9
10438 + u32 serv_cpl_wrap:1; // bit 10
10439 + u32 unused:21; // bits 11-31
10440 +#endif
10441 + } bits;
10442 +} TX_STATUS_BLOCK_t, *PTX_STATUS_BLOCK_t;
10443 +
10444 +/* TCB (Transmit Control Block) */
10445 +typedef struct _MP_TCB {
10446 + struct _MP_TCB *Next;
10447 + u32 Flags;
10448 + u32 Count;
10449 + u32 PacketStaleCount;
10450 + struct sk_buff *Packet;
10451 + u32 PacketLength;
10452 + DMA10W_t WrIndex;
10453 + DMA10W_t WrIndexStart;
10454 +} MP_TCB, *PMP_TCB;
10455 +
10456 +/* Structure to hold the skb's in a list */
10457 +typedef struct tx_skb_list_elem {
10458 + struct list_head skb_list_elem;
10459 + struct sk_buff *skb;
10460 +} TX_SKB_LIST_ELEM, *PTX_SKB_LIST_ELEM;
10461 +
10462 +/* TX_RING_t is sructure representing our local reference(s) to the ring */
10463 +typedef struct _tx_ring_t {
10464 + /* TCB (Transmit Control Block) memory and lists */
10465 + PMP_TCB MpTcbMem;
10466 +
10467 + /* List of TCBs that are ready to be used */
10468 + PMP_TCB TCBReadyQueueHead;
10469 + PMP_TCB TCBReadyQueueTail;
10470 +
10471 + /* list of TCBs that are currently being sent. NOTE that access to all
10472 + * three of these (including nBusySend) are controlled via the
10473 + * TCBSendQLock. This lock should be secured prior to incementing /
10474 + * decrementing nBusySend, or any queue manipulation on CurrSendHead /
10475 + * Tail
10476 + */
10477 + PMP_TCB CurrSendHead;
10478 + PMP_TCB CurrSendTail;
10479 + int32_t nBusySend;
10480 +
10481 + /* List of packets (not TCBs) that were queued for lack of resources */
10482 + struct list_head SendWaitQueue;
10483 + int32_t nWaitSend;
10484 +
10485 + /* The actual descriptor ring */
10486 + PTX_DESC_ENTRY_t pTxDescRingVa;
10487 + dma_addr_t pTxDescRingPa;
10488 + uint64_t pTxDescRingAdjustedPa;
10489 + uint64_t TxDescOffset;
10490 +
10491 + /* ReadyToSend indicates where we last wrote to in the descriptor ring. */
10492 + DMA10W_t txDmaReadyToSend;
10493 +
10494 + /* The location of the write-back status block */
10495 + PTX_STATUS_BLOCK_t pTxStatusVa;
10496 + dma_addr_t pTxStatusPa;
10497 +
10498 + /* A Block of zeroes used to pad packets that are less than 60 bytes */
10499 + void *pTxDummyBlkVa;
10500 + dma_addr_t pTxDummyBlkPa;
10501 +
10502 + TXMAC_ERR_t TxMacErr;
10503 +
10504 + /* Variables to track the Tx interrupt coalescing features */
10505 + int32_t TxPacketsSinceLastinterrupt;
10506 +} TX_RING_t, *PTX_RING_t;
10507 +
10508 +/* Forward declaration of the frag-list for the following prototypes */
10509 +typedef struct _MP_FRAG_LIST MP_FRAG_LIST, *PMP_FRAG_LIST;
10510 +
10511 +/* Forward declaration of the private adapter structure */
10512 +struct et131x_adapter;
10513 +
10514 +/* PROTOTYPES for et1310_tx.c */
10515 +int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter);
10516 +void et131x_tx_dma_memory_free(struct et131x_adapter *adapter);
10517 +void ConfigTxDmaRegs(struct et131x_adapter *pAdapter);
10518 +void et131x_init_send(struct et131x_adapter *adapter);
10519 +void et131x_tx_dma_disable(struct et131x_adapter *pAdapter);
10520 +void et131x_tx_dma_enable(struct et131x_adapter *pAdapter);
10521 +void et131x_handle_send_interrupt(struct et131x_adapter *pAdapter);
10522 +void et131x_free_busy_send_packets(struct et131x_adapter *pAdapter);
10523 +int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev);
10524 +
10525 +#endif /* __ET1310_TX_H__ */
10526 diff --git a/drivers/staging/et131x/et131x_adapter.h b/drivers/staging/et131x/et131x_adapter.h
10527 new file mode 100644
10528 index 0000000..36e61a4
10529 --- /dev/null
10530 +++ b/drivers/staging/et131x/et131x_adapter.h
10531 @@ -0,0 +1,347 @@
10532 +/*
10533 + * Agere Systems Inc.
10534 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
10535 + *
10536 + * Copyright © 2005 Agere Systems Inc.
10537 + * All rights reserved.
10538 + * http://www.agere.com
10539 + *
10540 + *------------------------------------------------------------------------------
10541 + *
10542 + * et131x_adapter.h - Header which includes the private adapter structure, along
10543 + * with related support structures, macros, definitions, etc.
10544 + *
10545 + *------------------------------------------------------------------------------
10546 + *
10547 + * SOFTWARE LICENSE
10548 + *
10549 + * This software is provided subject to the following terms and conditions,
10550 + * which you should read carefully before using the software. Using this
10551 + * software indicates your acceptance of these terms and conditions. If you do
10552 + * not agree with these terms and conditions, do not use the software.
10553 + *
10554 + * Copyright © 2005 Agere Systems Inc.
10555 + * All rights reserved.
10556 + *
10557 + * Redistribution and use in source or binary forms, with or without
10558 + * modifications, are permitted provided that the following conditions are met:
10559 + *
10560 + * . Redistributions of source code must retain the above copyright notice, this
10561 + * list of conditions and the following Disclaimer as comments in the code as
10562 + * well as in the documentation and/or other materials provided with the
10563 + * distribution.
10564 + *
10565 + * . Redistributions in binary form must reproduce the above copyright notice,
10566 + * this list of conditions and the following Disclaimer in the documentation
10567 + * and/or other materials provided with the distribution.
10568 + *
10569 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
10570 + * may be used to endorse or promote products derived from this software
10571 + * without specific prior written permission.
10572 + *
10573 + * Disclaimer
10574 + *
10575 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
10576 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
10577 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
10578 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
10579 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
10580 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10581 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
10582 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
10583 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
10584 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
10585 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
10586 + * DAMAGE.
10587 + *
10588 + */
10589 +
10590 +#ifndef __ET131X_ADAPTER_H__
10591 +#define __ET131X_ADAPTER_H__
10592 +
10593 +#include "et1310_address_map.h"
10594 +#include "et1310_tx.h"
10595 +#include "et1310_rx.h"
10596 +
10597 +/*
10598 + * Do not change these values: if changed, then change also in respective
10599 + * TXdma and Rxdma engines
10600 + */
10601 +#define NUM_DESC_PER_RING_TX 512 // TX Do not change these values
10602 +#define NUM_TCB 64
10603 +
10604 +/*
10605 + * These values are all superseded by registry entries to facilitate tuning.
10606 + * Once the desired performance has been achieved, the optimal registry values
10607 + * should be re-populated to these #defines:
10608 + */
10609 +#define NUM_TRAFFIC_CLASSES 1
10610 +
10611 +/*
10612 + * There are three ways of counting errors - if there are more than X errors
10613 + * in Y packets (represented by the "SAMPLE" macros), if there are more than
10614 + * N errors in a S mSec time period (the "PERIOD" macros), or if there are
10615 + * consecutive packets with errors (CONSEC_ERRORED_THRESH). This last covers
10616 + * for "Bursty" errors, and the errored packets may well not be contiguous,
10617 + * but several errors where the packet counter has changed by less than a
10618 + * small amount will cause this count to increment.
10619 + */
10620 +#define TX_PACKETS_IN_SAMPLE 10000
10621 +#define TX_MAX_ERRORS_IN_SAMPLE 50
10622 +
10623 +#define TX_ERROR_PERIOD 1000
10624 +#define TX_MAX_ERRORS_IN_PERIOD 10
10625 +
10626 +#define LINK_DETECTION_TIMER 5000
10627 +
10628 +#define TX_CONSEC_RANGE 5
10629 +#define TX_CONSEC_ERRORED_THRESH 10
10630 +
10631 +#define LO_MARK_PERCENT_FOR_PSR 15
10632 +#define LO_MARK_PERCENT_FOR_RX 15
10633 +
10634 +/* Macros for flag and ref count operations */
10635 +#define MP_SET_FLAG(_M, _F) ((_M)->Flags |= (_F))
10636 +#define MP_CLEAR_FLAG(_M, _F) ((_M)->Flags &= ~(_F))
10637 +#define MP_CLEAR_FLAGS(_M) ((_M)->Flags = 0)
10638 +#define MP_TEST_FLAG(_M, _F) (((_M)->Flags & (_F)) != 0)
10639 +#define MP_TEST_FLAGS(_M, _F) (((_M)->Flags & (_F)) == (_F))
10640 +#define MP_IS_FLAG_CLEAR(_M, _F) (((_M)->Flags & (_F)) == 0)
10641 +
10642 +#define MP_INC_RCV_REF(_A) atomic_inc(&(_A)->RcvRefCount)
10643 +#define MP_DEC_RCV_REF(_A) atomic_dec(&(_A)->RcvRefCount)
10644 +#define MP_GET_RCV_REF(_A) atomic_read(&(_A)->RcvRefCount)
10645 +
10646 +/* Macros specific to the private adapter structure */
10647 +#define MP_TCB_RESOURCES_AVAILABLE(_M) ((_M)->TxRing.nBusySend < NUM_TCB)
10648 +#define MP_TCB_RESOURCES_NOT_AVAILABLE(_M) ((_M)->TxRing.nBusySend >= NUM_TCB)
10649 +
10650 +#define MP_SHOULD_FAIL_SEND(_M) ((_M)->Flags & fMP_ADAPTER_FAIL_SEND_MASK)
10651 +#define MP_IS_NOT_READY(_M) ((_M)->Flags & fMP_ADAPTER_NOT_READY_MASK)
10652 +#define MP_IS_READY(_M) !((_M)->Flags & fMP_ADAPTER_NOT_READY_MASK)
10653 +
10654 +#define MP_HAS_CABLE(_M) !((_M)->Flags & fMP_ADAPTER_NO_CABLE)
10655 +#define MP_LINK_DETECTED(_M) !((_M)->Flags & fMP_ADAPTER_LINK_DETECTION)
10656 +
10657 +/* Counters for error rate monitoring */
10658 +typedef struct _MP_ERR_COUNTERS {
10659 + u32 PktCountTxPackets;
10660 + u32 PktCountTxErrors;
10661 + u32 TimerBasedTxErrors;
10662 + u32 PktCountLastError;
10663 + u32 ErredConsecPackets;
10664 +} MP_ERR_COUNTERS, *PMP_ERR_COUNTERS;
10665 +
10666 +/* RFD (Receive Frame Descriptor) */
10667 +typedef struct _MP_RFD {
10668 + struct list_head list_node;
10669 + struct sk_buff *Packet;
10670 + u32 PacketSize; // total size of receive frame
10671 + u16 iBufferIndex;
10672 + u8 iRingIndex;
10673 +} MP_RFD, *PMP_RFD;
10674 +
10675 +/* Enum for Flow Control */
10676 +typedef enum _eflow_control_t {
10677 + Both = 0,
10678 + TxOnly = 1,
10679 + RxOnly = 2,
10680 + None = 3
10681 +} eFLOW_CONTROL_t, *PeFLOW_CONTROL_t;
10682 +
10683 +/* Struct to define some device statistics */
10684 +typedef struct _ce_stats_t {
10685 + /* Link Input/Output stats */
10686 + uint64_t ipackets; // # of in packets
10687 + uint64_t opackets; // # of out packets
10688 +
10689 + /* MIB II variables
10690 + *
10691 + * NOTE: atomic_t types are only guaranteed to store 24-bits; if we
10692 + * MUST have 32, then we'll need another way to perform atomic
10693 + * operations
10694 + */
10695 + u32 unircv; // # multicast packets received
10696 + atomic_t unixmt; // # multicast packets for Tx
10697 + u32 multircv; // # multicast packets received
10698 + atomic_t multixmt; // # multicast packets for Tx
10699 + u32 brdcstrcv; // # broadcast packets received
10700 + atomic_t brdcstxmt; // # broadcast packets for Tx
10701 + u32 norcvbuf; // # Rx packets discarded
10702 + u32 noxmtbuf; // # Tx packets discarded
10703 +
10704 + /* Transciever state informations. */
10705 + u8 xcvr_addr;
10706 + u32 xcvr_id;
10707 +
10708 + /* Tx Statistics. */
10709 + u32 tx_uflo; // Tx Underruns
10710 +
10711 + u32 collisions;
10712 + u32 excessive_collisions;
10713 + u32 first_collision;
10714 + u32 late_collisions;
10715 + u32 max_pkt_error;
10716 + u32 tx_deferred;
10717 +
10718 + /* Rx Statistics. */
10719 + u32 rx_ov_flow; // Rx Over Flow
10720 +
10721 + u32 length_err;
10722 + u32 alignment_err;
10723 + u32 crc_err;
10724 + u32 code_violations;
10725 + u32 other_errors;
10726 +
10727 +#ifdef CONFIG_ET131X_DEBUG
10728 + u32 UnhandledInterruptsPerSec;
10729 + u32 RxDmaInterruptsPerSec;
10730 + u32 TxDmaInterruptsPerSec;
10731 + u32 WatchDogInterruptsPerSec;
10732 +#endif /* CONFIG_ET131X_DEBUG */
10733 +
10734 + u32 SynchrounousIterations;
10735 + INTERRUPT_t InterruptStatus;
10736 +} CE_STATS_t, *PCE_STATS_t;
10737 +
10738 +/* The private adapter structure */
10739 +struct et131x_adapter {
10740 + struct net_device *netdev;
10741 + struct pci_dev *pdev;
10742 +
10743 + struct work_struct task;
10744 +
10745 + /* Flags that indicate current state of the adapter */
10746 + u32 Flags;
10747 + u32 HwErrCount;
10748 +
10749 + /* Configuration */
10750 + u8 PermanentAddress[ETH_ALEN];
10751 + u8 CurrentAddress[ETH_ALEN];
10752 + bool bOverrideAddress;
10753 + bool bEepromPresent;
10754 + u8 eepromData[2];
10755 +
10756 + /* Spinlocks */
10757 + spinlock_t Lock;
10758 +
10759 + spinlock_t TCBSendQLock;
10760 + spinlock_t TCBReadyQLock;
10761 + spinlock_t SendHWLock;
10762 + spinlock_t SendWaitLock;
10763 +
10764 + spinlock_t RcvLock;
10765 + spinlock_t RcvPendLock;
10766 + spinlock_t FbrLock;
10767 +
10768 + spinlock_t PHYLock;
10769 +
10770 + /* Packet Filter and look ahead size */
10771 + u32 PacketFilter;
10772 + u32 ulLookAhead;
10773 + u32 uiLinkSpeed;
10774 + u32 uiDuplexMode;
10775 + u32 uiAutoNegStatus;
10776 + u8 ucLinkStatus;
10777 +
10778 + /* multicast list */
10779 + u32 MCAddressCount;
10780 + u8 MCList[NIC_MAX_MCAST_LIST][ETH_ALEN];
10781 +
10782 + /* MAC test */
10783 + TXMAC_TXTEST_t TxMacTest;
10784 +
10785 + /* Pointer to the device's PCI register space */
10786 + ADDRESS_MAP_t __iomem *CSRAddress;
10787 +
10788 + /* PCI config space info, for debug purposes only. */
10789 + u8 RevisionID;
10790 + u16 VendorID;
10791 + u16 DeviceID;
10792 + u16 SubVendorID;
10793 + u16 SubSystemID;
10794 + u32 CacheFillSize;
10795 + u16 PciXDevCtl;
10796 + u8 pci_lat_timer;
10797 + u8 pci_hdr_type;
10798 + u8 pci_bist;
10799 + u32 pci_cfg_state[64 / sizeof(u32)];
10800 +
10801 + /* Registry parameters */
10802 + u8 SpeedDuplex; // speed/duplex
10803 + eFLOW_CONTROL_t RegistryFlowControl; // for 802.3x flow control
10804 + u8 RegistryWOLMatch; // Enable WOL pattern-matching
10805 + u8 RegistryWOLLink; // Link state change is independant
10806 + u8 RegistryPhyComa; // Phy Coma mode enable/disable
10807 +
10808 + u32 RegistryRxMemEnd; // Size of internal rx memory
10809 + u8 RegistryMACStat; // If set, read MACSTAT, else don't
10810 + u32 RegistryVlanTag; // 802.1q Vlan TAG
10811 + u32 RegistryJumboPacket; // Max supported ethernet packet size
10812 +
10813 + u32 RegistryTxNumBuffers;
10814 + u32 RegistryTxTimeInterval;
10815 +
10816 + u32 RegistryRxNumBuffers;
10817 + u32 RegistryRxTimeInterval;
10818 +
10819 + /* Validation helpers */
10820 + u8 RegistryPMWOL;
10821 + u8 RegistryNMIDisable;
10822 + u32 RegistryDMACache;
10823 + u32 RegistrySCGain;
10824 + u8 RegistryPhyLoopbk; // Enable Phy loopback
10825 +
10826 + /* Derived from the registry: */
10827 + u8 AiForceDpx; // duplex setting
10828 + u16 AiForceSpeed; // 'Speed', user over-ride of line speed
10829 + eFLOW_CONTROL_t FlowControl; // flow control validated by the far-end
10830 + enum {
10831 + NETIF_STATUS_INVALID = 0,
10832 + NETIF_STATUS_MEDIA_CONNECT,
10833 + NETIF_STATUS_MEDIA_DISCONNECT,
10834 + NETIF_STATUS_MAX
10835 + } MediaState;
10836 + u8 DriverNoPhyAccess;
10837 +
10838 + /* Minimize init-time */
10839 + bool bQueryPending;
10840 + bool bSetPending;
10841 + bool bResetPending;
10842 + struct timer_list ErrorTimer;
10843 + bool bLinkTimerActive;
10844 + MP_POWER_MGMT PoMgmt;
10845 + INTERRUPT_t CachedMaskValue;
10846 +
10847 + atomic_t RcvRefCount; // Num packets not yet returned
10848 +
10849 + /* Xcvr status at last poll */
10850 + MI_BMSR_t Bmsr;
10851 +
10852 + /* Tx Memory Variables */
10853 + TX_RING_t TxRing;
10854 +
10855 + /* Rx Memory Variables */
10856 + RX_RING_t RxRing;
10857 +
10858 + /* ET1310 register Access */
10859 + JAGCORE_ACCESS_REGS JagCoreRegs;
10860 + PCI_CFG_SPACE_REGS PciCfgRegs;
10861 +
10862 + /* Loopback specifics */
10863 + u8 ReplicaPhyLoopbk; // Replica Enable
10864 + u8 ReplicaPhyLoopbkPF; // Replica Enable Pass/Fail
10865 +
10866 + /* Stats */
10867 + CE_STATS_t Stats;
10868 +
10869 + struct net_device_stats net_stats;
10870 + struct net_device_stats net_stats_prev;
10871 +};
10872 +
10873 +#define MPSendPacketsHandler MPSendPackets
10874 +#define MP_FREE_SEND_PACKET_FUN(Adapter, pMpTcb) \
10875 + et131x_free_send_packet(Adapter, pMpTcb)
10876 +#define MpSendPacketFun(Adapter, Packet) MpSendPacket(Adapter, Packet)
10877 +
10878 +#endif /* __ET131X_ADAPTER_H__ */
10879 diff --git a/drivers/staging/et131x/et131x_config.c b/drivers/staging/et131x/et131x_config.c
10880 new file mode 100644
10881 index 0000000..0adbaa6
10882 --- /dev/null
10883 +++ b/drivers/staging/et131x/et131x_config.c
10884 @@ -0,0 +1,325 @@
10885 +/*
10886 + * Agere Systems Inc.
10887 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
10888 + *
10889 + * Copyright © 2005 Agere Systems Inc.
10890 + * All rights reserved.
10891 + * http://www.agere.com
10892 + *
10893 + *------------------------------------------------------------------------------
10894 + *
10895 + * et131x_config.c - Handles parsing of configuration data during
10896 + * initialization.
10897 + *
10898 + *------------------------------------------------------------------------------
10899 + *
10900 + * SOFTWARE LICENSE
10901 + *
10902 + * This software is provided subject to the following terms and conditions,
10903 + * which you should read carefully before using the software. Using this
10904 + * software indicates your acceptance of these terms and conditions. If you do
10905 + * not agree with these terms and conditions, do not use the software.
10906 + *
10907 + * Copyright © 2005 Agere Systems Inc.
10908 + * All rights reserved.
10909 + *
10910 + * Redistribution and use in source or binary forms, with or without
10911 + * modifications, are permitted provided that the following conditions are met:
10912 + *
10913 + * . Redistributions of source code must retain the above copyright notice, this
10914 + * list of conditions and the following Disclaimer as comments in the code as
10915 + * well as in the documentation and/or other materials provided with the
10916 + * distribution.
10917 + *
10918 + * . Redistributions in binary form must reproduce the above copyright notice,
10919 + * this list of conditions and the following Disclaimer in the documentation
10920 + * and/or other materials provided with the distribution.
10921 + *
10922 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
10923 + * may be used to endorse or promote products derived from this software
10924 + * without specific prior written permission.
10925 + *
10926 + * Disclaimer
10927 + *
10928 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
10929 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
10930 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
10931 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
10932 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
10933 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10934 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
10935 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
10936 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
10937 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
10938 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
10939 + * DAMAGE.
10940 + *
10941 + */
10942 +
10943 +#include "et131x_version.h"
10944 +#include "et131x_debug.h"
10945 +#include "et131x_defs.h"
10946 +
10947 +#include <linux/init.h>
10948 +#include <linux/module.h>
10949 +#include <linux/types.h>
10950 +#include <linux/kernel.h>
10951 +
10952 +#include <linux/sched.h>
10953 +#include <linux/ptrace.h>
10954 +#include <linux/slab.h>
10955 +#include <linux/ctype.h>
10956 +#include <linux/string.h>
10957 +#include <linux/timer.h>
10958 +#include <linux/interrupt.h>
10959 +#include <linux/in.h>
10960 +#include <linux/delay.h>
10961 +#include <asm/io.h>
10962 +#include <asm/system.h>
10963 +#include <asm/bitops.h>
10964 +
10965 +#include <linux/netdevice.h>
10966 +#include <linux/etherdevice.h>
10967 +#include <linux/skbuff.h>
10968 +#include <linux/if_arp.h>
10969 +#include <linux/ioport.h>
10970 +
10971 +#include "et1310_phy.h"
10972 +#include "et1310_pm.h"
10973 +#include "et1310_jagcore.h"
10974 +
10975 +#include "et131x_adapter.h"
10976 +#include "et131x_initpci.h"
10977 +#include "et131x_config.h"
10978 +
10979 +#include "et1310_tx.h"
10980 +
10981 +/* Data for debugging facilities */
10982 +#ifdef CONFIG_ET131X_DEBUG
10983 +extern dbg_info_t *et131x_dbginfo;
10984 +#endif /* CONFIG_ET131X_DEBUG */
10985 +
10986 +/* Defines for Parameter Default/Min/Max vaules */
10987 +#define PARM_SPEED_DUPLEX_DEF 0
10988 +#define PARM_SPEED_DUPLEX_MIN 0
10989 +#define PARM_SPEED_DUPLEX_MAX 5
10990 +
10991 +#define PARM_VLAN_TAG_DEF 0
10992 +#define PARM_VLAN_TAG_MIN 0
10993 +#define PARM_VLAN_TAG_MAX 4095
10994 +
10995 +#define PARM_FLOW_CTL_DEF 0
10996 +#define PARM_FLOW_CTL_MIN 0
10997 +#define PARM_FLOW_CTL_MAX 3
10998 +
10999 +#define PARM_WOL_LINK_DEF 3
11000 +#define PARM_WOL_LINK_MIN 0
11001 +#define PARM_WOL_LINK_MAX 3
11002 +
11003 +#define PARM_WOL_MATCH_DEF 7
11004 +#define PARM_WOL_MATCH_MIN 0
11005 +#define PARM_WOL_MATCH_MAX 7
11006 +
11007 +#define PARM_JUMBO_PKT_DEF 1514
11008 +#define PARM_JUMBO_PKT_MIN 1514
11009 +#define PARM_JUMBO_PKT_MAX 9216
11010 +
11011 +#define PARM_PHY_COMA_DEF 0
11012 +#define PARM_PHY_COMA_MIN 0
11013 +#define PARM_PHY_COMA_MAX 1
11014 +
11015 +#define PARM_RX_NUM_BUFS_DEF 4
11016 +#define PARM_RX_NUM_BUFS_MIN 1
11017 +#define PARM_RX_NUM_BUFS_MAX 64
11018 +
11019 +#define PARM_RX_TIME_INT_DEF 10
11020 +#define PARM_RX_TIME_INT_MIN 2
11021 +#define PARM_RX_TIME_INT_MAX 320
11022 +
11023 +#define PARM_TX_NUM_BUFS_DEF 4
11024 +#define PARM_TX_NUM_BUFS_MIN 1
11025 +#define PARM_TX_NUM_BUFS_MAX 40
11026 +
11027 +#define PARM_TX_TIME_INT_DEF 40
11028 +#define PARM_TX_TIME_INT_MIN 1
11029 +#define PARM_TX_TIME_INT_MAX 140
11030 +
11031 +#define PARM_RX_MEM_END_DEF 0x2bc
11032 +#define PARM_RX_MEM_END_MIN 0
11033 +#define PARM_RX_MEM_END_MAX 0x3ff
11034 +
11035 +#define PARM_MAC_STAT_DEF 1
11036 +#define PARM_MAC_STAT_MIN 0
11037 +#define PARM_MAC_STAT_MAX 1
11038 +
11039 +#define PARM_SC_GAIN_DEF 7
11040 +#define PARM_SC_GAIN_MIN 0
11041 +#define PARM_SC_GAIN_MAX 7
11042 +
11043 +#define PARM_PM_WOL_DEF 0
11044 +#define PARM_PM_WOL_MIN 0
11045 +#define PARM_PM_WOL_MAX 1
11046 +
11047 +#define PARM_NMI_DISABLE_DEF 0
11048 +#define PARM_NMI_DISABLE_MIN 0
11049 +#define PARM_NMI_DISABLE_MAX 2
11050 +
11051 +#define PARM_DMA_CACHE_DEF 0
11052 +#define PARM_DMA_CACHE_MIN 0
11053 +#define PARM_DMA_CACHE_MAX 15
11054 +
11055 +#define PARM_PHY_LOOPBK_DEF 0
11056 +#define PARM_PHY_LOOPBK_MIN 0
11057 +#define PARM_PHY_LOOPBK_MAX 1
11058 +
11059 +#define PARM_MAC_ADDRESS_DEF { 0x00, 0x05, 0x3d, 0x00, 0x02, 0x00 }
11060 +
11061 +/* Module parameter for disabling NMI
11062 + * et131x_speed_set :
11063 + * Set Link speed and dublex manually (0-5) [0]
11064 + * 1 : 10Mb Half-Duplex
11065 + * 2 : 10Mb Full-Duplex
11066 + * 3 : 100Mb Half-Duplex
11067 + * 4 : 100Mb Full-Duplex
11068 + * 5 : 1000Mb Full-Duplex
11069 + * 0 : Auto Speed Auto Dublex // default
11070 + */
11071 +static u32 et131x_nmi_disable = PARM_NMI_DISABLE_DEF;
11072 +module_param(et131x_nmi_disable, uint, 0);
11073 +MODULE_PARM_DESC(et131x_nmi_disable, "Disable NMI (0-2) [0]");
11074 +
11075 +/* Module parameter for manual speed setting
11076 + * et131x_nmi_disable :
11077 + * Disable NMI (0-2) [0]
11078 + * 0 :
11079 + * 1 :
11080 + * 2 :
11081 + */
11082 +static u32 et131x_speed_set = PARM_SPEED_DUPLEX_DEF;
11083 +module_param(et131x_speed_set, uint, 0);
11084 +MODULE_PARM_DESC(et131x_speed_set,
11085 + "Set Link speed and dublex manually (0-5) [0] \n 1 : 10Mb Half-Duplex \n 2 : 10Mb Full-Duplex \n 3 : 100Mb Half-Duplex \n 4 : 100Mb Full-Duplex \n 5 : 1000Mb Full-Duplex \n 0 : Auto Speed Auto Dublex");
11086 +
11087 +/**
11088 + * et131x_config_parse
11089 + * @pAdapter: pointer to the private adapter struct
11090 + *
11091 + * Parses a configuration from some location (module parameters, for example)
11092 + * into the private adapter struct
11093 + */
11094 +void et131x_config_parse(struct et131x_adapter *pAdapter)
11095 +{
11096 + uint8_t macAddrDef[] = PARM_MAC_ADDRESS_DEF;
11097 +
11098 + DBG_ENTER(et131x_dbginfo);
11099 +
11100 + /*
11101 + * The NDIS driver uses the registry to store persistent per-device
11102 + * configuration, and reads this configuration into the appropriate
11103 + * elements of the private adapter structure on initialization.
11104 + * Because Linux has no analog to the registry, use this function to
11105 + * initialize the private adapter structure with a default
11106 + * configuration.
11107 + *
11108 + * One other possibility is to use a series of module parameters which
11109 + * can be passed in by the caller when the module is initialized.
11110 + * However, this implementation does not allow for seperate
11111 + * configurations in the event multiple devices are present, and hence
11112 + * will not suffice.
11113 + *
11114 + * If another method is derived which addresses this problem, this is
11115 + * where it should be implemented.
11116 + */
11117 +
11118 + /* Set the private adapter struct with default values for the
11119 + * corresponding parameters
11120 + */
11121 + if (et131x_speed_set != PARM_SPEED_DUPLEX_DEF) {
11122 + DBG_VERBOSE(et131x_dbginfo, "Speed set manually to : %d \n",
11123 + et131x_speed_set);
11124 + pAdapter->SpeedDuplex = et131x_speed_set;
11125 + } else {
11126 + pAdapter->SpeedDuplex = PARM_SPEED_DUPLEX_DEF;
11127 + }
11128 +
11129 + // pAdapter->SpeedDuplex = PARM_SPEED_DUPLEX_DEF;
11130 +
11131 + pAdapter->RegistryVlanTag = PARM_VLAN_TAG_DEF;
11132 + pAdapter->RegistryFlowControl = PARM_FLOW_CTL_DEF;
11133 + pAdapter->RegistryWOLLink = PARM_WOL_LINK_DEF;
11134 + pAdapter->RegistryWOLMatch = PARM_WOL_MATCH_DEF;
11135 + pAdapter->RegistryJumboPacket = PARM_JUMBO_PKT_DEF;
11136 + pAdapter->RegistryPhyComa = PARM_PHY_COMA_DEF;
11137 + pAdapter->RegistryRxNumBuffers = PARM_RX_NUM_BUFS_DEF;
11138 + pAdapter->RegistryRxTimeInterval = PARM_RX_TIME_INT_DEF;
11139 + pAdapter->RegistryTxNumBuffers = PARM_TX_NUM_BUFS_DEF;
11140 + pAdapter->RegistryTxTimeInterval = PARM_TX_TIME_INT_DEF;
11141 + pAdapter->RegistryRxMemEnd = PARM_RX_MEM_END_DEF;
11142 + pAdapter->RegistryMACStat = PARM_MAC_STAT_DEF;
11143 + pAdapter->RegistrySCGain = PARM_SC_GAIN_DEF;
11144 + pAdapter->RegistryPMWOL = PARM_PM_WOL_DEF;
11145 +
11146 + if (et131x_nmi_disable != PARM_NMI_DISABLE_DEF) {
11147 + pAdapter->RegistryNMIDisable = et131x_nmi_disable;
11148 + } else {
11149 + pAdapter->RegistryNMIDisable = PARM_NMI_DISABLE_DEF;
11150 + }
11151 +
11152 + pAdapter->RegistryDMACache = PARM_DMA_CACHE_DEF;
11153 + pAdapter->RegistryPhyLoopbk = PARM_PHY_LOOPBK_DEF;
11154 +
11155 + /* Set the MAC address to a default */
11156 + memcpy(pAdapter->CurrentAddress, macAddrDef, ETH_ALEN);
11157 + pAdapter->bOverrideAddress = false;
11158 +
11159 + DBG_TRACE(et131x_dbginfo,
11160 + "Default MAC Address : %02x:%02x:%02x:%02x:%02x:%02x\n",
11161 + pAdapter->CurrentAddress[0], pAdapter->CurrentAddress[1],
11162 + pAdapter->CurrentAddress[2], pAdapter->CurrentAddress[3],
11163 + pAdapter->CurrentAddress[4], pAdapter->CurrentAddress[5]);
11164 +
11165 + /* Decode SpeedDuplex
11166 + *
11167 + * Set up as if we are auto negotiating always and then change if we
11168 + * go into force mode
11169 + */
11170 + pAdapter->AiForceSpeed = 0; // Auto speed
11171 + pAdapter->AiForceDpx = 0; // Auto FDX
11172 +
11173 + /* If we are the 10/100 device, and gigabit is somehow requested then
11174 + * knock it down to 100 full.
11175 + */
11176 + if ((pAdapter->DeviceID == ET131X_PCI_DEVICE_ID_FAST) &&
11177 + (pAdapter->SpeedDuplex == 5)) {
11178 + pAdapter->SpeedDuplex = 4;
11179 + }
11180 +
11181 + switch (pAdapter->SpeedDuplex) {
11182 + case 1: // 10Mb Half-Duplex
11183 + pAdapter->AiForceSpeed = 10;
11184 + pAdapter->AiForceDpx = 1;
11185 + break;
11186 +
11187 + case 2: // 10Mb Full-Duplex
11188 + pAdapter->AiForceSpeed = 10;
11189 + pAdapter->AiForceDpx = 2;
11190 + break;
11191 +
11192 + case 3: // 100Mb Half-Duplex
11193 + pAdapter->AiForceSpeed = 100;
11194 + pAdapter->AiForceDpx = 1;
11195 + break;
11196 +
11197 + case 4: // 100Mb Full-Duplex
11198 + pAdapter->AiForceSpeed = 100;
11199 + pAdapter->AiForceDpx = 2;
11200 + break;
11201 +
11202 + case 5: // 1000Mb Full-Duplex
11203 + pAdapter->AiForceSpeed = 1000;
11204 + pAdapter->AiForceDpx = 2;
11205 + break;
11206 + }
11207 +
11208 + DBG_LEAVE(et131x_dbginfo);
11209 +}
11210 diff --git a/drivers/staging/et131x/et131x_config.h b/drivers/staging/et131x/et131x_config.h
11211 new file mode 100644
11212 index 0000000..642c0f6
11213 --- /dev/null
11214 +++ b/drivers/staging/et131x/et131x_config.h
11215 @@ -0,0 +1,67 @@
11216 +/*
11217 + * Agere Systems Inc.
11218 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
11219 + *
11220 + * Copyright © 2005 Agere Systems Inc.
11221 + * All rights reserved.
11222 + * http://www.agere.com
11223 + *
11224 + *------------------------------------------------------------------------------
11225 + *
11226 + * et131x_config.h - Defines, structs, enums, prototypes, etc. to support
11227 + * et131x_config.c
11228 + *
11229 + *------------------------------------------------------------------------------
11230 + *
11231 + * SOFTWARE LICENSE
11232 + *
11233 + * This software is provided subject to the following terms and conditions,
11234 + * which you should read carefully before using the software. Using this
11235 + * software indicates your acceptance of these terms and conditions. If you do
11236 + * not agree with these terms and conditions, do not use the software.
11237 + *
11238 + * Copyright © 2005 Agere Systems Inc.
11239 + * All rights reserved.
11240 + *
11241 + * Redistribution and use in source or binary forms, with or without
11242 + * modifications, are permitted provided that the following conditions are met:
11243 + *
11244 + * . Redistributions of source code must retain the above copyright notice, this
11245 + * list of conditions and the following Disclaimer as comments in the code as
11246 + * well as in the documentation and/or other materials provided with the
11247 + * distribution.
11248 + *
11249 + * . Redistributions in binary form must reproduce the above copyright notice,
11250 + * this list of conditions and the following Disclaimer in the documentation
11251 + * and/or other materials provided with the distribution.
11252 + *
11253 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
11254 + * may be used to endorse or promote products derived from this software
11255 + * without specific prior written permission.
11256 + *
11257 + * Disclaimer
11258 + *
11259 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
11260 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
11261 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
11262 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
11263 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
11264 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11265 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
11266 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
11267 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
11268 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
11269 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
11270 + * DAMAGE.
11271 + *
11272 + */
11273 +
11274 +#ifndef __ET131X_CONFIG_H__
11275 +#define __ET131X_CONFIG_H__
11276 +
11277 +/* Forward declaration of the private adapter structure */
11278 +struct et131x_adapter;
11279 +
11280 +void et131x_config_parse(struct et131x_adapter *adapter);
11281 +
11282 +#endif /* __ET131X_CONFIG_H__ */
11283 diff --git a/drivers/staging/et131x/et131x_debug.c b/drivers/staging/et131x/et131x_debug.c
11284 new file mode 100644
11285 index 0000000..9ee5bce
11286 --- /dev/null
11287 +++ b/drivers/staging/et131x/et131x_debug.c
11288 @@ -0,0 +1,218 @@
11289 +/*
11290 + * Agere Systems Inc.
11291 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
11292 + *
11293 + * Copyright © 2005 Agere Systems Inc.
11294 + * All rights reserved.
11295 + * http://www.agere.com
11296 + *
11297 + *------------------------------------------------------------------------------
11298 + *
11299 + * et131x_debug.c - Routines used for debugging.
11300 + *
11301 + *------------------------------------------------------------------------------
11302 + *
11303 + * SOFTWARE LICENSE
11304 + *
11305 + * This software is provided subject to the following terms and conditions,
11306 + * which you should read carefully before using the software. Using this
11307 + * software indicates your acceptance of these terms and conditions. If you do
11308 + * not agree with these terms and conditions, do not use the software.
11309 + *
11310 + * Copyright © 2005 Agere Systems Inc.
11311 + * All rights reserved.
11312 + *
11313 + * Redistribution and use in source or binary forms, with or without
11314 + * modifications, are permitted provided that the following conditions are met:
11315 + *
11316 + * . Redistributions of source code must retain the above copyright notice, this
11317 + * list of conditions and the following Disclaimer as comments in the code as
11318 + * well as in the documentation and/or other materials provided with the
11319 + * distribution.
11320 + *
11321 + * . Redistributions in binary form must reproduce the above copyright notice,
11322 + * this list of conditions and the following Disclaimer in the documentation
11323 + * and/or other materials provided with the distribution.
11324 + *
11325 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
11326 + * may be used to endorse or promote products derived from this software
11327 + * without specific prior written permission.
11328 + *
11329 + * Disclaimer
11330 + *
11331 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
11332 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
11333 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
11334 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
11335 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
11336 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11337 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
11338 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
11339 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
11340 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
11341 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
11342 + * DAMAGE.
11343 + *
11344 + */
11345 +
11346 +#ifdef CONFIG_ET131X_DEBUG
11347 +
11348 +#include "et131x_version.h"
11349 +#include "et131x_debug.h"
11350 +#include "et131x_defs.h"
11351 +
11352 +#include <linux/pci.h>
11353 +#include <linux/init.h>
11354 +#include <linux/module.h>
11355 +#include <linux/types.h>
11356 +#include <linux/kernel.h>
11357 +
11358 +#include <linux/sched.h>
11359 +#include <linux/ptrace.h>
11360 +#include <linux/slab.h>
11361 +#include <linux/ctype.h>
11362 +#include <linux/string.h>
11363 +#include <linux/timer.h>
11364 +#include <linux/interrupt.h>
11365 +#include <linux/in.h>
11366 +#include <linux/delay.h>
11367 +#include <asm/io.h>
11368 +#include <asm/system.h>
11369 +#include <asm/bitops.h>
11370 +
11371 +#include <linux/netdevice.h>
11372 +#include <linux/etherdevice.h>
11373 +#include <linux/skbuff.h>
11374 +#include <linux/if_arp.h>
11375 +#include <linux/ioport.h>
11376 +#include <linux/random.h>
11377 +
11378 +#include "et1310_phy.h"
11379 +#include "et1310_pm.h"
11380 +#include "et1310_jagcore.h"
11381 +
11382 +#include "et131x_adapter.h"
11383 +#include "et131x_netdev.h"
11384 +#include "et131x_config.h"
11385 +#include "et131x_isr.h"
11386 +
11387 +#include "et1310_address_map.h"
11388 +#include "et1310_jagcore.h"
11389 +#include "et1310_tx.h"
11390 +#include "et1310_rx.h"
11391 +#include "et1310_mac.h"
11392 +
11393 +/* Data for debugging facilities */
11394 +extern dbg_info_t *et131x_dbginfo;
11395 +
11396 +/**
11397 + * DumpTxQueueContents - Dump out the tx queue and the shadow pointers
11398 + * @pAdapter: pointer to our adapter structure
11399 + */
11400 +void DumpTxQueueContents(int dbgLvl, struct et131x_adapter *pAdapter)
11401 +{
11402 + MMC_t __iomem *mmc = &pAdapter->CSRAddress->mmc;
11403 + uint32_t TxQueueAddr;
11404 +
11405 + if (DBG_FLAGS(et131x_dbginfo) & dbgLvl) {
11406 + for (TxQueueAddr = 0x200; TxQueueAddr < 0x3ff; TxQueueAddr++) {
11407 + MMC_SRAM_ACCESS_t sram_access;
11408 +
11409 + sram_access.value = readl(&mmc->sram_access.value);
11410 + sram_access.bits.req_addr = TxQueueAddr;
11411 + sram_access.bits.req_access = 1;
11412 + writel(sram_access.value, &mmc->sram_access.value);
11413 +
11414 + DBG_PRINT("Addr 0x%x, Access 0x%08x\t"
11415 + "Value 1 0x%08x, Value 2 0x%08x, "
11416 + "Value 3 0x%08x, Value 4 0x%08x, \n",
11417 + TxQueueAddr,
11418 + readl(&mmc->sram_access.value),
11419 + readl(&mmc->sram_word1),
11420 + readl(&mmc->sram_word2),
11421 + readl(&mmc->sram_word3),
11422 + readl(&mmc->sram_word4));
11423 + }
11424 +
11425 + DBG_PRINT("Shadow Pointers 0x%08x\n",
11426 + readl(&pAdapter->CSRAddress->txmac.shadow_ptr.value));
11427 + }
11428 +}
11429 +
11430 +/**
11431 + * DumpDeviceBlock
11432 + * @pAdapter: pointer to our adapter
11433 + *
11434 + * Dumps the first 64 regs of each block of the et-1310 (each block is
11435 + * mapped to a new page, each page is 4096 bytes).
11436 + */
11437 +#define NUM_BLOCKS 8
11438 +void DumpDeviceBlock(int dbgLvl, struct et131x_adapter *pAdapter,
11439 + uint32_t Block)
11440 +{
11441 + uint32_t Address1, Address2;
11442 + uint32_t __iomem *BigDevicePointer =
11443 + (uint32_t __iomem *) pAdapter->CSRAddress;
11444 + const char *BlockNames[NUM_BLOCKS] = {
11445 + "Global", "Tx DMA", "Rx DMA", "Tx MAC",
11446 + "Rx MAC", "MAC", "MAC Stat", "MMC"
11447 + };
11448 +
11449 + /* Output the debug counters to the debug terminal */
11450 + if (DBG_FLAGS(et131x_dbginfo) & dbgLvl) {
11451 + DBG_PRINT("%s block\n", BlockNames[Block]);
11452 + BigDevicePointer += Block * 1024;
11453 + for (Address1 = 0; Address1 < 8; Address1++) {
11454 + for (Address2 = 0; Address2 < 8; Address2++) {
11455 + if (Block == 0 &&
11456 + (Address1 * 8 + Address2) == 6) {
11457 + DBG_PRINT(" ISR , ");
11458 + } else {
11459 + DBG_PRINT("0x%08x, ",
11460 + readl(BigDevicePointer++));
11461 + }
11462 + }
11463 + DBG_PRINT("\n");
11464 + }
11465 + DBG_PRINT("\n");
11466 + }
11467 +}
11468 +
11469 +/**
11470 + * DumpDeviceReg
11471 + * @pAdapter: pointer to our adapter
11472 + *
11473 + * Dumps the first 64 regs of each block of the et-1310 (each block is
11474 + * mapped to a new page, each page is 4096 bytes).
11475 + */
11476 +void DumpDeviceReg(int dbgLvl, struct et131x_adapter *pAdapter)
11477 +{
11478 + uint32_t Address1, Address2;
11479 + uint32_t Block;
11480 + uint32_t __iomem *BigDevicePointer =
11481 + (uint32_t __iomem *) pAdapter->CSRAddress;
11482 + uint32_t __iomem *Pointer;
11483 + const char *BlockNames[NUM_BLOCKS] = {
11484 + "Global", "Tx DMA", "Rx DMA", "Tx MAC",
11485 + "Rx MAC", "MAC", "MAC Stat", "MMC"
11486 + };
11487 +
11488 + /* Output the debug counters to the debug terminal */
11489 + if (DBG_FLAGS(et131x_dbginfo) & dbgLvl) {
11490 + for (Block = 0; Block < NUM_BLOCKS; Block++) {
11491 + DBG_PRINT("%s block\n", BlockNames[Block]);
11492 + Pointer = BigDevicePointer + (Block * 1024);
11493 +
11494 + for (Address1 = 0; Address1 < 8; Address1++) {
11495 + for (Address2 = 0; Address2 < 8; Address2++) {
11496 + DBG_PRINT("0x%08x, ",
11497 + readl(Pointer++));
11498 + }
11499 + DBG_PRINT("\n");
11500 + }
11501 + DBG_PRINT("\n");
11502 + }
11503 + }
11504 +}
11505 +
11506 +#endif // CONFIG_ET131X_DEBUG
11507 diff --git a/drivers/staging/et131x/et131x_debug.h b/drivers/staging/et131x/et131x_debug.h
11508 new file mode 100644
11509 index 0000000..dab6080
11510 --- /dev/null
11511 +++ b/drivers/staging/et131x/et131x_debug.h
11512 @@ -0,0 +1,201 @@
11513 +/*
11514 + * Agere Systems Inc.
11515 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
11516 + *
11517 + * Copyright © 2005 Agere Systems Inc.
11518 + * All rights reserved.
11519 + * http://www.agere.com
11520 + *
11521 + *------------------------------------------------------------------------------
11522 + *
11523 + * et131x_debug.h - Defines, structs, enums, prototypes, etc. used for
11524 + * outputting debug messages to the system logging facility
11525 + * (ksyslogd)
11526 + *
11527 + *------------------------------------------------------------------------------
11528 + *
11529 + * SOFTWARE LICENSE
11530 + *
11531 + * This software is provided subject to the following terms and conditions,
11532 + * which you should read carefully before using the software. Using this
11533 + * software indicates your acceptance of these terms and conditions. If you do
11534 + * not agree with these terms and conditions, do not use the software.
11535 + *
11536 + * Copyright © 2005 Agere Systems Inc.
11537 + * All rights reserved.
11538 + *
11539 + * Redistribution and use in source or binary forms, with or without
11540 + * modifications, are permitted provided that the following conditions are met:
11541 + *
11542 + * . Redistributions of source code must retain the above copyright notice, this
11543 + * list of conditions and the following Disclaimer as comments in the code as
11544 + * well as in the documentation and/or other materials provided with the
11545 + * distribution.
11546 + *
11547 + * . Redistributions in binary form must reproduce the above copyright notice,
11548 + * this list of conditions and the following Disclaimer in the documentation
11549 + * and/or other materials provided with the distribution.
11550 + *
11551 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
11552 + * may be used to endorse or promote products derived from this software
11553 + * without specific prior written permission.
11554 + *
11555 + * Disclaimer
11556 + *
11557 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
11558 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
11559 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
11560 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
11561 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
11562 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11563 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
11564 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
11565 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
11566 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
11567 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
11568 + * DAMAGE.
11569 + *
11570 + */
11571 +
11572 +#ifndef __ET131X_DBG_H__
11573 +#define __ET131X_DBG_H__
11574 +
11575 +/* Define Masks for debugging types/levels */
11576 +#define DBG_ERROR_ON 0x00000001L
11577 +#define DBG_WARNING_ON 0x00000002L
11578 +#define DBG_NOTICE_ON 0x00000004L
11579 +#define DBG_TRACE_ON 0x00000008L
11580 +#define DBG_VERBOSE_ON 0x00000010L
11581 +#define DBG_PARAM_ON 0x00000020L
11582 +#define DBG_BREAK_ON 0x00000040L
11583 +#define DBG_RX_ON 0x00000100L
11584 +#define DBG_TX_ON 0x00000200L
11585 +
11586 +#ifdef CONFIG_ET131X_DEBUG
11587 +
11588 +/*
11589 + * Set the level of debugging if not done with a preprocessor define. See
11590 + * et131x_main.c, function et131x_init_module() for how the debug level
11591 + * translates into the types of messages displayed.
11592 + */
11593 +#ifndef DBG_LVL
11594 +#define DBG_LVL 3
11595 +#endif /* DBG_LVL */
11596 +
11597 +#define DBG_DEFAULTS (DBG_ERROR_ON | DBG_WARNING_ON | DBG_BREAK_ON )
11598 +
11599 +#define DBG_FLAGS(A) (A)->dbgFlags
11600 +#define DBG_NAME(A) (A)->dbgName
11601 +#define DBG_LEVEL(A) (A)->dbgLevel
11602 +
11603 +#ifndef DBG_PRINT
11604 +#define DBG_PRINT(S...) printk(KERN_DEBUG S)
11605 +#endif /* DBG_PRINT */
11606 +
11607 +#ifndef DBG_PRINTC
11608 +#define DBG_PRINTC(S...) printk(S)
11609 +#endif /* DBG_PRINTC */
11610 +
11611 +#ifndef DBG_TRAP
11612 +#define DBG_TRAP {} /* BUG() */
11613 +#endif /* DBG_TRAP */
11614 +
11615 +#define _ENTER_STR ">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>"
11616 +#define _LEAVE_STR "<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<"
11617 +
11618 +#define _DBG_ENTER(A) printk(KERN_DEBUG "%s:%.*s:%s\n", DBG_NAME(A), \
11619 + ++DBG_LEVEL(A), _ENTER_STR, __func__)
11620 +#define _DBG_LEAVE(A) printk(KERN_DEBUG "%s:%.*s:%s\n", DBG_NAME(A), \
11621 + DBG_LEVEL(A)--, _LEAVE_STR, __func__)
11622 +
11623 +#define DBG_ENTER(A) {if (DBG_FLAGS(A) & DBG_TRACE_ON) \
11624 + _DBG_ENTER(A);}
11625 +
11626 +#define DBG_LEAVE(A) {if (DBG_FLAGS(A) & DBG_TRACE_ON) \
11627 + _DBG_LEAVE(A);}
11628 +
11629 +#define DBG_PARAM(A,N,F,S...) {if (DBG_FLAGS(A) & DBG_PARAM_ON) \
11630 + DBG_PRINT(" %s -- "F"\n",N,S);}
11631 +
11632 +#define DBG_ERROR(A,S...) \
11633 + if (DBG_FLAGS(A) & DBG_ERROR_ON) { \
11634 + DBG_PRINT("%s:ERROR:%s ",DBG_NAME(A), __func__); \
11635 + DBG_PRINTC(S); \
11636 + DBG_TRAP; \
11637 + }
11638 +
11639 +#define DBG_WARNING(A,S...) {if (DBG_FLAGS(A) & DBG_WARNING_ON) \
11640 + {DBG_PRINT("%s:WARNING:%s ",DBG_NAME(A),__func__);DBG_PRINTC(S);}}
11641 +
11642 +#define DBG_NOTICE(A,S...) {if (DBG_FLAGS(A) & DBG_NOTICE_ON) \
11643 + {DBG_PRINT("%s:NOTICE:%s ",DBG_NAME(A),__func__);DBG_PRINTC(S);}}
11644 +
11645 +#define DBG_TRACE(A,S...) {if (DBG_FLAGS(A) & DBG_TRACE_ON) \
11646 + {DBG_PRINT("%s:TRACE:%s ",DBG_NAME(A), __func__);DBG_PRINTC(S);}}
11647 +
11648 +#define DBG_VERBOSE(A,S...) {if (DBG_FLAGS(A) & DBG_VERBOSE_ON) \
11649 + {DBG_PRINT("%s:VERBOSE:%s ",DBG_NAME(A), __func__);DBG_PRINTC(S);}}
11650 +
11651 +#define DBG_RX(A,S...) {if (DBG_FLAGS(A) & DBG_RX_ON) \
11652 + {DBG_PRINT(S);}}
11653 +
11654 +#define DBG_RX_ENTER(A) {if (DBG_FLAGS(A) & DBG_RX_ON) \
11655 + _DBG_ENTER(A);}
11656 +
11657 +#define DBG_RX_LEAVE(A) {if (DBG_FLAGS(A) & DBG_RX_ON) \
11658 + _DBG_LEAVE(A);}
11659 +
11660 +#define DBG_TX(A,S...) {if (DBG_FLAGS(A) & DBG_TX_ON) \
11661 + {DBG_PRINT(S);}}
11662 +
11663 +#define DBG_TX_ENTER(A) {if (DBG_FLAGS(A) & DBG_TX_ON) \
11664 + _DBG_ENTER(A);}
11665 +
11666 +#define DBG_TX_LEAVE(A) {if (DBG_FLAGS(A) & DBG_TX_ON) \
11667 + _DBG_LEAVE(A);}
11668 +
11669 +#define DBG_ASSERT(C) {if (!(C)) \
11670 + {DBG_PRINT("ASSERT(%s) -- %s#%d (%s)\n", \
11671 + #C,__FILE__,__LINE__,__func__); \
11672 + DBG_TRAP;}}
11673 +#define STATIC
11674 +
11675 +typedef struct {
11676 + char *dbgName;
11677 + int dbgLevel;
11678 + unsigned long dbgFlags;
11679 +} dbg_info_t;
11680 +
11681 +#else /* CONFIG_ET131X_DEBUG */
11682 +
11683 +#define DBG_DEFN
11684 +#define DBG_TRAP
11685 +#define DBG_PRINT(S...)
11686 +#define DBG_ENTER(A)
11687 +#define DBG_LEAVE(A)
11688 +#define DBG_PARAM(A,N,F,S...)
11689 +#define DBG_ERROR(A,S...)
11690 +#define DBG_WARNING(A,S...)
11691 +#define DBG_NOTICE(A,S...)
11692 +#define DBG_TRACE(A,S...)
11693 +#define DBG_VERBOSE(A,S...)
11694 +#define DBG_RX(A,S...)
11695 +#define DBG_RX_ENTER(A)
11696 +#define DBG_RX_LEAVE(A)
11697 +#define DBG_TX(A,S...)
11698 +#define DBG_TX_ENTER(A)
11699 +#define DBG_TX_LEAVE(A)
11700 +#define DBG_ASSERT(C)
11701 +#define STATIC static
11702 +
11703 +#endif /* CONFIG_ET131X_DEBUG */
11704 +
11705 +/* Forward declaration of the private adapter structure */
11706 +struct et131x_adapter;
11707 +
11708 +void DumpTxQueueContents(int dbgLvl, struct et131x_adapter *adapter);
11709 +void DumpDeviceBlock(int dbgLvl, struct et131x_adapter *adapter,
11710 + unsigned int Block);
11711 +void DumpDeviceReg(int dbgLvl, struct et131x_adapter *adapter);
11712 +
11713 +#endif /* __ET131X_DBG_H__ */
11714 diff --git a/drivers/staging/et131x/et131x_defs.h b/drivers/staging/et131x/et131x_defs.h
11715 new file mode 100644
11716 index 0000000..886cb78
11717 --- /dev/null
11718 +++ b/drivers/staging/et131x/et131x_defs.h
11719 @@ -0,0 +1,128 @@
11720 +/*
11721 + * Agere Systems Inc.
11722 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
11723 + *
11724 + * Copyright © 2005 Agere Systems Inc.
11725 + * All rights reserved.
11726 + * http://www.agere.com
11727 + *
11728 + *------------------------------------------------------------------------------
11729 + *
11730 + * et131x_defs.h - Defines, structs, enums, prototypes, etc. to assist with OS
11731 + * compatibility
11732 + *
11733 + *------------------------------------------------------------------------------
11734 + *
11735 + * SOFTWARE LICENSE
11736 + *
11737 + * This software is provided subject to the following terms and conditions,
11738 + * which you should read carefully before using the software. Using this
11739 + * software indicates your acceptance of these terms and conditions. If you do
11740 + * not agree with these terms and conditions, do not use the software.
11741 + *
11742 + * Copyright © 2005 Agere Systems Inc.
11743 + * All rights reserved.
11744 + *
11745 + * Redistribution and use in source or binary forms, with or without
11746 + * modifications, are permitted provided that the following conditions are met:
11747 + *
11748 + * . Redistributions of source code must retain the above copyright notice, this
11749 + * list of conditions and the following Disclaimer as comments in the code as
11750 + * well as in the documentation and/or other materials provided with the
11751 + * distribution.
11752 + *
11753 + * . Redistributions in binary form must reproduce the above copyright notice,
11754 + * this list of conditions and the following Disclaimer in the documentation
11755 + * and/or other materials provided with the distribution.
11756 + *
11757 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
11758 + * may be used to endorse or promote products derived from this software
11759 + * without specific prior written permission.
11760 + *
11761 + * Disclaimer
11762 + *
11763 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
11764 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
11765 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
11766 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
11767 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
11768 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11769 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
11770 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
11771 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
11772 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
11773 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
11774 + * DAMAGE.
11775 + *
11776 + */
11777 +
11778 +#ifndef __ET131X_DEFS_H__
11779 +#define __ET131X_DEFS_H__
11780 +
11781 +/* Packet and header sizes */
11782 +#define NIC_MIN_PACKET_SIZE 60
11783 +#define NIC_HEADER_SIZE ETH_HLEN /* 14 */
11784 +
11785 +/* Multicast list size */
11786 +#define NIC_MAX_MCAST_LIST 128
11787 +
11788 +/* Supported Filters */
11789 +#define ET131X_PACKET_TYPE_DIRECTED 0x0001
11790 +#define ET131X_PACKET_TYPE_MULTICAST 0x0002
11791 +#define ET131X_PACKET_TYPE_BROADCAST 0x0004
11792 +#define ET131X_PACKET_TYPE_PROMISCUOUS 0x0008
11793 +#define ET131X_PACKET_TYPE_ALL_MULTICAST 0x0010
11794 +
11795 +/* Tx Timeout */
11796 +#define ET131X_TX_TIMEOUT (1 * HZ)
11797 +#define NIC_SEND_HANG_THRESHOLD 0
11798 +
11799 +/* MP_TCB flags */
11800 +#define fMP_DEST_MULTI 0x00000001
11801 +#define fMP_DEST_BROAD 0x00000002
11802 +
11803 +/* MP_ADAPTER flags */
11804 +#define fMP_ADAPTER_RECV_LOOKASIDE 0x00000004
11805 +#define fMP_ADAPTER_INTERRUPT_IN_USE 0x00000008
11806 +#define fMP_ADAPTER_SECONDARY 0x00000010
11807 +
11808 +/* MP_SHARED flags */
11809 +#define fMP_ADAPTER_SHUTDOWN 0x00100000
11810 +#define fMP_ADAPTER_LOWER_POWER 0x00200000
11811 +
11812 +#define fMP_ADAPTER_NON_RECOVER_ERROR 0x00800000
11813 +#define fMP_ADAPTER_RESET_IN_PROGRESS 0x01000000
11814 +#define fMP_ADAPTER_NO_CABLE 0x02000000
11815 +#define fMP_ADAPTER_HARDWARE_ERROR 0x04000000
11816 +#define fMP_ADAPTER_REMOVE_IN_PROGRESS 0x08000000
11817 +#define fMP_ADAPTER_HALT_IN_PROGRESS 0x10000000
11818 +#define fMP_ADAPTER_LINK_DETECTION 0x20000000
11819 +
11820 +#define fMP_ADAPTER_FAIL_SEND_MASK 0x3ff00000
11821 +#define fMP_ADAPTER_NOT_READY_MASK 0x3ff00000
11822 +
11823 +/* Some offsets in PCI config space that are actually used. */
11824 +#define ET1310_PCI_PM_CAPABILITY 0x40
11825 +#define ET1310_PCI_PM_CSR 0x44
11826 +#define ET1310_PCI_MAX_PYLD 0x4C
11827 +#define ET1310_PCI_DEV_CTRL 0x50
11828 +#define ET1310_PCI_DEV_STAT 0x52
11829 +#define ET1310_NMI_DISABLE 0x61
11830 +#define ET1310_PCI_MAC_ADDRESS 0xA4
11831 +#define ET1310_PCI_EEPROM_STATUS 0xB2
11832 +#define ET1310_PCI_PHY_INDEX_REG 0xB4
11833 +#define ET1310_PCI_ACK_NACK 0xC0
11834 +#define ET1310_PCI_REPLAY 0xC2
11835 +#define ET1310_PCI_L0L1LATENCY 0xCF
11836 +#define ET1310_PCI_SEL_PHY_CTRL 0xE4
11837 +#define ET1310_PCI_ADVANCED_ERR 0x100
11838 +
11839 +/* PCI Vendor/Product IDs */
11840 +#define ET131X_PCI_VENDOR_ID 0x11C1 // Agere Systems
11841 +#define ET131X_PCI_DEVICE_ID_GIG 0xED00 // ET1310 1000 Base-T
11842 +#define ET131X_PCI_DEVICE_ID_FAST 0xED01 // ET1310 100 Base-T
11843 +
11844 +/* Define order of magnitude converter */
11845 +#define NANO_IN_A_MICRO 1000
11846 +
11847 +#endif /* __ET131X_DEFS_H__ */
11848 diff --git a/drivers/staging/et131x/et131x_initpci.c b/drivers/staging/et131x/et131x_initpci.c
11849 new file mode 100644
11850 index 0000000..4c6f171
11851 --- /dev/null
11852 +++ b/drivers/staging/et131x/et131x_initpci.c
11853 @@ -0,0 +1,1046 @@
11854 +/*
11855 + * Agere Systems Inc.
11856 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
11857 + *
11858 + * Copyright © 2005 Agere Systems Inc.
11859 + * All rights reserved.
11860 + * http://www.agere.com
11861 + *
11862 + *------------------------------------------------------------------------------
11863 + *
11864 + * et131x_initpci.c - Routines and data used to register the driver with the
11865 + * PCI (and PCI Express) subsystem, as well as basic driver
11866 + * init and startup.
11867 + *
11868 + *------------------------------------------------------------------------------
11869 + *
11870 + * SOFTWARE LICENSE
11871 + *
11872 + * This software is provided subject to the following terms and conditions,
11873 + * which you should read carefully before using the software. Using this
11874 + * software indicates your acceptance of these terms and conditions. If you do
11875 + * not agree with these terms and conditions, do not use the software.
11876 + *
11877 + * Copyright © 2005 Agere Systems Inc.
11878 + * All rights reserved.
11879 + *
11880 + * Redistribution and use in source or binary forms, with or without
11881 + * modifications, are permitted provided that the following conditions are met:
11882 + *
11883 + * . Redistributions of source code must retain the above copyright notice, this
11884 + * list of conditions and the following Disclaimer as comments in the code as
11885 + * well as in the documentation and/or other materials provided with the
11886 + * distribution.
11887 + *
11888 + * . Redistributions in binary form must reproduce the above copyright notice,
11889 + * this list of conditions and the following Disclaimer in the documentation
11890 + * and/or other materials provided with the distribution.
11891 + *
11892 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
11893 + * may be used to endorse or promote products derived from this software
11894 + * without specific prior written permission.
11895 + *
11896 + * Disclaimer
11897 + *
11898 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
11899 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
11900 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
11901 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
11902 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
11903 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11904 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
11905 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
11906 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
11907 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
11908 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
11909 + * DAMAGE.
11910 + *
11911 + */
11912 +
11913 +#include "et131x_version.h"
11914 +#include "et131x_debug.h"
11915 +#include "et131x_defs.h"
11916 +
11917 +#include <linux/pci.h>
11918 +#include <linux/init.h>
11919 +#include <linux/module.h>
11920 +#include <linux/types.h>
11921 +#include <linux/kernel.h>
11922 +
11923 +#include <linux/sched.h>
11924 +#include <linux/ptrace.h>
11925 +#include <linux/slab.h>
11926 +#include <linux/ctype.h>
11927 +#include <linux/string.h>
11928 +#include <linux/timer.h>
11929 +#include <linux/interrupt.h>
11930 +#include <linux/in.h>
11931 +#include <linux/delay.h>
11932 +#include <asm/io.h>
11933 +#include <asm/system.h>
11934 +#include <asm/bitops.h>
11935 +
11936 +#include <linux/netdevice.h>
11937 +#include <linux/etherdevice.h>
11938 +#include <linux/skbuff.h>
11939 +#include <linux/if_arp.h>
11940 +#include <linux/ioport.h>
11941 +#include <linux/random.h>
11942 +
11943 +#include "et1310_phy.h"
11944 +#include "et1310_pm.h"
11945 +#include "et1310_jagcore.h"
11946 +
11947 +#include "et131x_adapter.h"
11948 +#include "et131x_netdev.h"
11949 +#include "et131x_config.h"
11950 +#include "et131x_isr.h"
11951 +
11952 +#include "et1310_address_map.h"
11953 +#include "et1310_jagcore.h"
11954 +#include "et1310_tx.h"
11955 +#include "et1310_rx.h"
11956 +#include "et1310_mac.h"
11957 +#include "et1310_eeprom.h"
11958 +
11959 +
11960 +int __devinit et131x_pci_setup(struct pci_dev *pdev,
11961 + const struct pci_device_id *ent);
11962 +void __devexit et131x_pci_remove(struct pci_dev *pdev);
11963 +
11964 +
11965 +/* Modinfo parameters (filled out using defines from et131x_version.h) */
11966 +MODULE_AUTHOR(DRIVER_AUTHOR);
11967 +MODULE_DESCRIPTION(DRIVER_INFO);
11968 +MODULE_LICENSE(DRIVER_LICENSE);
11969 +
11970 +/* Module Parameters and related data for debugging facilities */
11971 +#ifdef CONFIG_ET131X_DEBUG
11972 +static u32 et131x_debug_level = DBG_LVL;
11973 +static u32 et131x_debug_flags = DBG_DEFAULTS;
11974 +
11975 +/*
11976 +et131x_debug_level :
11977 + Level of debugging desired (0-7)
11978 + 7 : DBG_RX_ON | DBG_TX_ON
11979 + 6 : DBG_PARAM_ON
11980 + 5 : DBG_VERBOSE_ON
11981 + 4 : DBG_TRACE_ON
11982 + 3 : DBG_NOTICE_ON
11983 + 2 : no debug info
11984 + 1 : no debug info
11985 + 0 : no debug info
11986 +*/
11987 +
11988 +module_param(et131x_debug_level, uint, 0);
11989 +module_param(et131x_debug_flags, uint, 0);
11990 +
11991 +MODULE_PARM_DESC(et131x_debug_level, "Level of debugging desired (0-7)");
11992 +
11993 +static dbg_info_t et131x_info = { DRIVER_NAME_EXT, 0, 0 };
11994 +dbg_info_t *et131x_dbginfo = &et131x_info;
11995 +#endif /* CONFIG_ET131X_DEBUG */
11996 +
11997 +static struct pci_device_id et131x_pci_table[] __devinitdata = {
11998 + {ET131X_PCI_VENDOR_ID, ET131X_PCI_DEVICE_ID_GIG, PCI_ANY_ID,
11999 + PCI_ANY_ID, 0, 0, 0UL},
12000 + {ET131X_PCI_VENDOR_ID, ET131X_PCI_DEVICE_ID_FAST, PCI_ANY_ID,
12001 + PCI_ANY_ID, 0, 0, 0UL},
12002 + {0,}
12003 +};
12004 +
12005 +MODULE_DEVICE_TABLE(pci, et131x_pci_table);
12006 +
12007 +static struct pci_driver et131x_driver = {
12008 + .name = DRIVER_NAME,
12009 + .id_table = et131x_pci_table,
12010 + .probe = et131x_pci_setup,
12011 + .remove = __devexit_p(et131x_pci_remove),
12012 + .suspend = NULL, //et131x_pci_suspend,
12013 + .resume = NULL, //et131x_pci_resume,
12014 +};
12015 +
12016 +
12017 +/**
12018 + * et131x_init_module - The "main" entry point called on driver initialization
12019 + *
12020 + * Returns 0 on success, errno on failure (as defined in errno.h)
12021 + */
12022 +int et131x_init_module(void)
12023 +{
12024 + int result;
12025 +
12026 +#ifdef CONFIG_ET131X_DEBUG
12027 + /* Set the level of debug messages displayed using the module
12028 + * parameter
12029 + */
12030 + et131x_dbginfo->dbgFlags = et131x_debug_flags;
12031 +
12032 + switch (et131x_debug_level) {
12033 + case 7:
12034 + et131x_dbginfo->dbgFlags |= (DBG_RX_ON | DBG_TX_ON);
12035 +
12036 + case 6:
12037 + et131x_dbginfo->dbgFlags |= DBG_PARAM_ON;
12038 +
12039 + case 5:
12040 + et131x_dbginfo->dbgFlags |= DBG_VERBOSE_ON;
12041 +
12042 + case 4:
12043 + et131x_dbginfo->dbgFlags |= DBG_TRACE_ON;
12044 +
12045 + case 3:
12046 + et131x_dbginfo->dbgFlags |= DBG_NOTICE_ON;
12047 +
12048 + case 2:
12049 + case 1:
12050 + case 0:
12051 + default:
12052 + break;
12053 + }
12054 +#endif /* CONFIG_ET131X_DEBUG */
12055 +
12056 + DBG_ENTER(et131x_dbginfo);
12057 + DBG_PRINT("%s\n", DRIVER_INFO);
12058 +
12059 + result = pci_register_driver(&et131x_driver);
12060 +
12061 + DBG_LEAVE(et131x_dbginfo);
12062 + return result;
12063 +}
12064 +
12065 +/**
12066 + * et131x_cleanup_module - The entry point called on driver cleanup
12067 + */
12068 +void et131x_cleanup_module(void)
12069 +{
12070 + DBG_ENTER(et131x_dbginfo);
12071 +
12072 + pci_unregister_driver(&et131x_driver);
12073 +
12074 + DBG_LEAVE(et131x_dbginfo);
12075 +}
12076 +
12077 +/*
12078 + * These macros map the driver-specific init_module() and cleanup_module()
12079 + * routines so they can be called by the kernel.
12080 + */
12081 +module_init(et131x_init_module);
12082 +module_exit(et131x_cleanup_module);
12083 +
12084 +
12085 +/**
12086 + * et131x_find_adapter - Find the adapter and get all the assigned resources
12087 + * @adapter: pointer to our private adapter structure
12088 + *
12089 + * Returns 0 on success, errno on failure (as defined in errno.h)
12090 + */
12091 +int et131x_find_adapter(struct et131x_adapter *adapter, struct pci_dev *pdev)
12092 +{
12093 + int result;
12094 + uint8_t eepromStat;
12095 + uint8_t maxPayload = 0;
12096 + uint8_t read_size_reg;
12097 +
12098 + DBG_ENTER(et131x_dbginfo);
12099 +
12100 + /* Allow disabling of Non-Maskable Interrupts in I/O space, to
12101 + * support validation.
12102 + */
12103 + if (adapter->RegistryNMIDisable) {
12104 + uint8_t RegisterVal;
12105 +
12106 + RegisterVal = inb(ET1310_NMI_DISABLE);
12107 + RegisterVal &= 0xf3;
12108 +
12109 + if (adapter->RegistryNMIDisable == 2) {
12110 + RegisterVal |= 0xc;
12111 + }
12112 +
12113 + outb(ET1310_NMI_DISABLE, RegisterVal);
12114 + }
12115 +
12116 + /* We first need to check the EEPROM Status code located at offset
12117 + * 0xB2 of config space
12118 + */
12119 + result = pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS,
12120 + &eepromStat);
12121 +
12122 + /* THIS IS A WORKAROUND:
12123 + * I need to call this function twice to get my card in a
12124 + * LG M1 Express Dual running. I tried also a msleep before this
12125 + * function, because I thougth there could be some time condidions
12126 + * but it didn't work. Call the whole function twice also work.
12127 + */
12128 + result = pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS,
12129 + &eepromStat);
12130 + if (result != PCIBIOS_SUCCESSFUL) {
12131 + DBG_ERROR(et131x_dbginfo, "Could not read PCI config space for "
12132 + "EEPROM Status\n");
12133 + DBG_LEAVE(et131x_dbginfo);
12134 + return -EIO;
12135 + }
12136 +
12137 + /* Determine if the error(s) we care about are present. If they are
12138 + * present, we need to fail.
12139 + */
12140 + if (eepromStat & 0x4C) {
12141 + result = pci_read_config_byte(pdev, PCI_REVISION_ID,
12142 + &adapter->RevisionID);
12143 + if (result != PCIBIOS_SUCCESSFUL) {
12144 + DBG_ERROR(et131x_dbginfo,
12145 + "Could not read PCI config space for "
12146 + "Revision ID\n");
12147 + DBG_LEAVE(et131x_dbginfo);
12148 + return -EIO;
12149 + } else if (adapter->RevisionID == 0x01) {
12150 + int32_t nLoop;
12151 + uint8_t ucTemp[4] = { 0xFE, 0x13, 0x10, 0xFF };
12152 +
12153 + /* Re-write the first 4 bytes if we have an eeprom
12154 + * present and the revision id is 1, this fixes the
12155 + * corruption seen with 1310 B Silicon
12156 + */
12157 + for (nLoop = 0; nLoop < 3; nLoop++) {
12158 + EepromWriteByte(adapter, nLoop, ucTemp[nLoop],
12159 + 0, SINGLE_BYTE);
12160 + }
12161 + }
12162 +
12163 + DBG_ERROR(et131x_dbginfo,
12164 + "Fatal EEPROM Status Error - 0x%04x\n", eepromStat);
12165 +
12166 + /* This error could mean that there was an error reading the
12167 + * eeprom or that the eeprom doesn't exist. We will treat
12168 + * each case the same and not try to gather additional
12169 + * information that normally would come from the eeprom, like
12170 + * MAC Address
12171 + */
12172 + adapter->bEepromPresent = false;
12173 +
12174 + DBG_LEAVE(et131x_dbginfo);
12175 + return -EIO;
12176 + } else {
12177 + DBG_TRACE(et131x_dbginfo, "EEPROM Status Code - 0x%04x\n",
12178 + eepromStat);
12179 + adapter->bEepromPresent = true;
12180 + }
12181 +
12182 + /* Read the EEPROM for information regarding LED behavior. Refer to
12183 + * ET1310_phy.c, et131x_xcvr_init(), for its use.
12184 + */
12185 + EepromReadByte(adapter, 0x70, &adapter->eepromData[0], 0, SINGLE_BYTE);
12186 + EepromReadByte(adapter, 0x71, &adapter->eepromData[1], 0, SINGLE_BYTE);
12187 +
12188 + if (adapter->eepromData[0] != 0xcd) {
12189 + adapter->eepromData[1] = 0x00; // Disable all optional features
12190 + }
12191 +
12192 + /* Let's set up the PORT LOGIC Register. First we need to know what
12193 + * the max_payload_size is
12194 + */
12195 + result = pci_read_config_byte(pdev, ET1310_PCI_MAX_PYLD, &maxPayload);
12196 + if (result != PCIBIOS_SUCCESSFUL) {
12197 + DBG_ERROR(et131x_dbginfo, "Could not read PCI config space for "
12198 + "Max Payload Size\n");
12199 + DBG_LEAVE(et131x_dbginfo);
12200 + return -EIO;
12201 + }
12202 +
12203 + /* Program the Ack/Nak latency and replay timers */
12204 + maxPayload &= 0x07; // Only the lower 3 bits are valid
12205 +
12206 + if (maxPayload < 2) {
12207 + const uint16_t AckNak[2] = { 0x76, 0xD0 };
12208 + const uint16_t Replay[2] = { 0x1E0, 0x2ED };
12209 +
12210 + result = pci_write_config_word(pdev, ET1310_PCI_ACK_NACK,
12211 + AckNak[maxPayload]);
12212 + if (result != PCIBIOS_SUCCESSFUL) {
12213 + DBG_ERROR(et131x_dbginfo,
12214 + "Could not write PCI config space "
12215 + "for ACK/NAK\n");
12216 + DBG_LEAVE(et131x_dbginfo);
12217 + return -EIO;
12218 + }
12219 +
12220 + result = pci_write_config_word(pdev, ET1310_PCI_REPLAY,
12221 + Replay[maxPayload]);
12222 + if (result != PCIBIOS_SUCCESSFUL) {
12223 + DBG_ERROR(et131x_dbginfo,
12224 + "Could not write PCI config space "
12225 + "for Replay Timer\n");
12226 + DBG_LEAVE(et131x_dbginfo);
12227 + return -EIO;
12228 + }
12229 + }
12230 +
12231 + /* l0s and l1 latency timers. We are using default values.
12232 + * Representing 001 for L0s and 010 for L1
12233 + */
12234 + result = pci_write_config_byte(pdev, ET1310_PCI_L0L1LATENCY, 0x11);
12235 + if (result != PCIBIOS_SUCCESSFUL) {
12236 + DBG_ERROR(et131x_dbginfo,
12237 + "Could not write PCI config space for "
12238 + "Latency Timers\n");
12239 + DBG_LEAVE(et131x_dbginfo);
12240 + return -EIO;
12241 + }
12242 +
12243 + /* Change the max read size to 2k */
12244 + result = pci_read_config_byte(pdev, 0x51, &read_size_reg);
12245 + if (result != PCIBIOS_SUCCESSFUL) {
12246 + DBG_ERROR(et131x_dbginfo,
12247 + "Could not read PCI config space for Max read size\n");
12248 + DBG_LEAVE(et131x_dbginfo);
12249 + return -EIO;
12250 + }
12251 +
12252 + read_size_reg &= 0x8f;
12253 + read_size_reg |= 0x40;
12254 +
12255 + result = pci_write_config_byte(pdev, 0x51, read_size_reg);
12256 + if (result != PCIBIOS_SUCCESSFUL) {
12257 + DBG_ERROR(et131x_dbginfo,
12258 + "Could not write PCI config space for Max read size\n");
12259 + DBG_LEAVE(et131x_dbginfo);
12260 + return -EIO;
12261 + }
12262 +
12263 + /* PCI Express Configuration registers 0x48-0x5B (Device Control) */
12264 + result = pci_read_config_word(pdev, ET1310_PCI_DEV_CTRL,
12265 + &adapter->PciXDevCtl);
12266 + if (result != PCIBIOS_SUCCESSFUL) {
12267 + DBG_ERROR(et131x_dbginfo,
12268 + "Could not read PCI config space for PCI Express Dev Ctl\n");
12269 + DBG_LEAVE(et131x_dbginfo);
12270 + return -EIO;
12271 + }
12272 +
12273 + /* Get MAC address from config space if an eeprom exists, otherwise
12274 + * the MAC address there will not be valid
12275 + */
12276 + if (adapter->bEepromPresent) {
12277 + int i;
12278 +
12279 + for (i = 0; i < ETH_ALEN; i++) {
12280 + result = pci_read_config_byte(
12281 + pdev, ET1310_PCI_MAC_ADDRESS + i,
12282 + adapter->PermanentAddress + i);
12283 + if (result != PCIBIOS_SUCCESSFUL) {
12284 + DBG_ERROR(et131x_dbginfo,
12285 + "Could not read PCI config space for MAC address\n");
12286 + DBG_LEAVE(et131x_dbginfo);
12287 + return -EIO;
12288 + }
12289 + }
12290 + }
12291 +
12292 + DBG_LEAVE(et131x_dbginfo);
12293 + return 0;
12294 +}
12295 +
12296 +/**
12297 + * et131x_error_timer_handler
12298 + * @data: timer-specific variable; here a pointer to our adapter structure
12299 + *
12300 + * The routine called when the error timer expires, to track the number of
12301 + * recurring errors.
12302 + */
12303 +void et131x_error_timer_handler(unsigned long data)
12304 +{
12305 + struct et131x_adapter *pAdapter = (struct et131x_adapter *) data;
12306 + PM_CSR_t pm_csr;
12307 +
12308 + pm_csr.value = readl(&pAdapter->CSRAddress->global.pm_csr.value);
12309 +
12310 + if (pm_csr.bits.pm_phy_sw_coma == 0) {
12311 + if (pAdapter->RegistryMACStat) {
12312 + UpdateMacStatHostCounters(pAdapter);
12313 + }
12314 + } else {
12315 + DBG_VERBOSE(et131x_dbginfo,
12316 + "No interrupts, in PHY coma, pm_csr = 0x%x\n",
12317 + pm_csr.value);
12318 + }
12319 +
12320 + if (!pAdapter->Bmsr.bits.link_status &&
12321 + pAdapter->RegistryPhyComa &&
12322 + pAdapter->PoMgmt.TransPhyComaModeOnBoot < 11) {
12323 + pAdapter->PoMgmt.TransPhyComaModeOnBoot++;
12324 + }
12325 +
12326 + if (pAdapter->PoMgmt.TransPhyComaModeOnBoot == 10) {
12327 + if (!pAdapter->Bmsr.bits.link_status
12328 + && pAdapter->RegistryPhyComa) {
12329 + if (pm_csr.bits.pm_phy_sw_coma == 0) {
12330 + // NOTE - This was originally a 'sync with interrupt'. How
12331 + // to do that under Linux?
12332 + et131x_enable_interrupts(pAdapter);
12333 + EnablePhyComa(pAdapter);
12334 + }
12335 + }
12336 + }
12337 +
12338 + /* This is a periodic timer, so reschedule */
12339 + mod_timer(&pAdapter->ErrorTimer, jiffies +
12340 + TX_ERROR_PERIOD * HZ / 1000);
12341 +}
12342 +
12343 +/**
12344 + * et131x_link_detection_handler
12345 + *
12346 + * Timer function for link up at driver load time
12347 + */
12348 +void et131x_link_detection_handler(unsigned long data)
12349 +{
12350 + struct et131x_adapter *pAdapter = (struct et131x_adapter *) data;
12351 + unsigned long lockflags;
12352 +
12353 + /* Let everyone know that we have run */
12354 + pAdapter->bLinkTimerActive = false;
12355 +
12356 + if (pAdapter->MediaState == 0) {
12357 + spin_lock_irqsave(&pAdapter->Lock, lockflags);
12358 +
12359 + pAdapter->MediaState = NETIF_STATUS_MEDIA_DISCONNECT;
12360 + MP_CLEAR_FLAG(pAdapter, fMP_ADAPTER_LINK_DETECTION);
12361 +
12362 + spin_unlock_irqrestore(&pAdapter->Lock, lockflags);
12363 +
12364 + netif_carrier_off(pAdapter->netdev);
12365 +
12366 + pAdapter->bSetPending = false;
12367 + }
12368 +}
12369 +
12370 +/**
12371 + * et131x_adapter_setup - Set the adapter up as per cassini+ documentation
12372 + * @adapter: pointer to our private adapter structure
12373 + *
12374 + * Returns 0 on success, errno on failure (as defined in errno.h)
12375 + */
12376 +int et131x_adapter_setup(struct et131x_adapter *pAdapter)
12377 +{
12378 + int status = 0;
12379 +
12380 + DBG_ENTER(et131x_dbginfo);
12381 +
12382 + /* Configure the JAGCore */
12383 + ConfigGlobalRegs(pAdapter);
12384 +
12385 + ConfigMACRegs1(pAdapter);
12386 + ConfigMMCRegs(pAdapter);
12387 +
12388 + ConfigRxMacRegs(pAdapter);
12389 + ConfigTxMacRegs(pAdapter);
12390 +
12391 + ConfigRxDmaRegs(pAdapter);
12392 + ConfigTxDmaRegs(pAdapter);
12393 +
12394 + ConfigMacStatRegs(pAdapter);
12395 +
12396 + /* Move the following code to Timer function?? */
12397 + status = et131x_xcvr_find(pAdapter);
12398 +
12399 + if (status != 0) {
12400 + DBG_WARNING(et131x_dbginfo, "Could not find the xcvr\n");
12401 + }
12402 +
12403 + /* Prepare the TRUEPHY library. */
12404 + ET1310_PhyInit(pAdapter);
12405 +
12406 + /* Reset the phy now so changes take place */
12407 + ET1310_PhyReset(pAdapter);
12408 +
12409 + /* Power down PHY */
12410 + ET1310_PhyPowerDown(pAdapter, 1);
12411 +
12412 + /*
12413 + * We need to turn off 1000 base half dulplex, the mac does not
12414 + * support it. For the 10/100 part, turn off all gig advertisement
12415 + */
12416 + if (pAdapter->DeviceID != ET131X_PCI_DEVICE_ID_FAST) {
12417 + ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_FULL);
12418 + } else {
12419 + ET1310_PhyAdvertise1000BaseT(pAdapter, TRUEPHY_ADV_DUPLEX_NONE);
12420 + }
12421 +
12422 + /* Power up PHY */
12423 + ET1310_PhyPowerDown(pAdapter, 0);
12424 +
12425 + et131x_setphy_normal(pAdapter);
12426 +
12427 + DBG_LEAVE(et131x_dbginfo);
12428 + return status;
12429 +}
12430 +
12431 +/**
12432 + * et131x_setup_hardware_properties - set up the MAC Address on the ET1310
12433 + * @adapter: pointer to our private adapter structure
12434 + */
12435 +void et131x_setup_hardware_properties(struct et131x_adapter *adapter)
12436 +{
12437 + DBG_ENTER(et131x_dbginfo);
12438 +
12439 + /* If have our default mac from registry and no mac address from
12440 + * EEPROM then we need to generate the last octet and set it on the
12441 + * device
12442 + */
12443 + if (!adapter->bOverrideAddress) {
12444 + if (adapter->PermanentAddress[0] == 0x00 &&
12445 + adapter->PermanentAddress[1] == 0x00 &&
12446 + adapter->PermanentAddress[2] == 0x00 &&
12447 + adapter->PermanentAddress[3] == 0x00 &&
12448 + adapter->PermanentAddress[4] == 0x00 &&
12449 + adapter->PermanentAddress[5] == 0x00) {
12450 + /*
12451 + * We need to randomly generate the last octet so we
12452 + * decrease our chances of setting the mac address to
12453 + * same as another one of our cards in the system
12454 + */
12455 + get_random_bytes(&adapter->CurrentAddress[5], 1);
12456 +
12457 + /*
12458 + * We have the default value in the register we are
12459 + * working with so we need to copy the current
12460 + * address into the permanent address
12461 + */
12462 + memcpy(adapter->PermanentAddress,
12463 + adapter->CurrentAddress, ETH_ALEN);
12464 + } else {
12465 + /* We do not have an override address, so set the
12466 + * current address to the permanent address and add
12467 + * it to the device
12468 + */
12469 + memcpy(adapter->CurrentAddress,
12470 + adapter->PermanentAddress, ETH_ALEN);
12471 + }
12472 + }
12473 +
12474 + DBG_LEAVE(et131x_dbginfo);
12475 +}
12476 +
12477 +/**
12478 + * et131x_soft_reset - Issue a soft reset to the hardware, complete for ET1310
12479 + * @adapter: pointer to our private adapter structure
12480 + */
12481 +void et131x_soft_reset(struct et131x_adapter *adapter)
12482 +{
12483 + DBG_ENTER(et131x_dbginfo);
12484 +
12485 + /* Disable MAC Core */
12486 + writel(0xc00f0000, &adapter->CSRAddress->mac.cfg1.value);
12487 +
12488 + /* Set everything to a reset value */
12489 + writel(0x7F, &adapter->CSRAddress->global.sw_reset.value);
12490 + writel(0x000f0000, &adapter->CSRAddress->mac.cfg1.value);
12491 + writel(0x00000000, &adapter->CSRAddress->mac.cfg1.value);
12492 +
12493 + DBG_LEAVE(et131x_dbginfo);
12494 +}
12495 +
12496 +/**
12497 + * et131x_align_allocated_memory - Align allocated memory on a given boundary
12498 + * @adapter: pointer to our adapter structure
12499 + * @phys_addr: pointer to Physical address
12500 + * @offset: pointer to the offset variable
12501 + * @mask: correct mask
12502 + */
12503 +void et131x_align_allocated_memory(struct et131x_adapter *adapter,
12504 + uint64_t *phys_addr,
12505 + uint64_t *offset, uint64_t mask)
12506 +{
12507 + uint64_t new_addr;
12508 +
12509 + DBG_ENTER(et131x_dbginfo);
12510 +
12511 + *offset = 0;
12512 +
12513 + new_addr = *phys_addr & ~mask;
12514 +
12515 + if (new_addr != *phys_addr) {
12516 + /* Move to next aligned block */
12517 + new_addr += mask + 1;
12518 + /* Return offset for adjusting virt addr */
12519 + *offset = new_addr - *phys_addr;
12520 + /* Return new physical address */
12521 + *phys_addr = new_addr;
12522 + }
12523 +
12524 + DBG_LEAVE(et131x_dbginfo);
12525 +}
12526 +
12527 +/**
12528 + * et131x_adapter_memory_alloc
12529 + * @adapter: pointer to our private adapter structure
12530 + *
12531 + * Returns 0 on success, errno on failure (as defined in errno.h).
12532 + *
12533 + * Allocate all the memory blocks for send, receive and others.
12534 + */
12535 +int et131x_adapter_memory_alloc(struct et131x_adapter *adapter)
12536 +{
12537 + int status = 0;
12538 +
12539 + DBG_ENTER(et131x_dbginfo);
12540 +
12541 + do {
12542 + /* Allocate memory for the Tx Ring */
12543 + status = et131x_tx_dma_memory_alloc(adapter);
12544 + if (status != 0) {
12545 + DBG_ERROR(et131x_dbginfo,
12546 + "et131x_tx_dma_memory_alloc FAILED\n");
12547 + break;
12548 + }
12549 +
12550 + /* Receive buffer memory allocation */
12551 + status = et131x_rx_dma_memory_alloc(adapter);
12552 + if (status != 0) {
12553 + DBG_ERROR(et131x_dbginfo,
12554 + "et131x_rx_dma_memory_alloc FAILED\n");
12555 + et131x_tx_dma_memory_free(adapter);
12556 + break;
12557 + }
12558 +
12559 + /* Init receive data structures */
12560 + status = et131x_init_recv(adapter);
12561 + if (status != 0) {
12562 + DBG_ERROR(et131x_dbginfo, "et131x_init_recv FAILED\n");
12563 + et131x_tx_dma_memory_free(adapter);
12564 + et131x_rx_dma_memory_free(adapter);
12565 + break;
12566 + }
12567 + } while (0);
12568 +
12569 + DBG_LEAVE(et131x_dbginfo);
12570 + return status;
12571 +}
12572 +
12573 +/**
12574 + * et131x_adapter_memory_free - Free all memory allocated for use by Tx & Rx
12575 + * @adapter: pointer to our private adapter structure
12576 + */
12577 +void et131x_adapter_memory_free(struct et131x_adapter *adapter)
12578 +{
12579 + DBG_ENTER(et131x_dbginfo);
12580 +
12581 + /* Free DMA memory */
12582 + et131x_tx_dma_memory_free(adapter);
12583 + et131x_rx_dma_memory_free(adapter);
12584 +
12585 + DBG_LEAVE(et131x_dbginfo);
12586 +}
12587 +
12588 +/**
12589 + * et131x_pci_remove
12590 + * @pdev: a pointer to the device's pci_dev structure
12591 + *
12592 + * Registered in the pci_driver structure, this function is called when the
12593 + * PCI subsystem detects that a PCI device which matches the information
12594 + * contained in the pci_device_id table has been removed.
12595 + */
12596 +void __devexit et131x_pci_remove(struct pci_dev *pdev)
12597 +{
12598 + struct net_device *netdev;
12599 + struct et131x_adapter *adapter;
12600 +
12601 + DBG_ENTER(et131x_dbginfo);
12602 +
12603 + /* Retrieve the net_device pointer from the pci_dev struct, as well
12604 + * as the private adapter struct
12605 + */
12606 + netdev = (struct net_device *) pci_get_drvdata(pdev);
12607 + adapter = netdev_priv(netdev);
12608 +
12609 + /* Perform device cleanup */
12610 + unregister_netdev(netdev);
12611 + et131x_adapter_memory_free(adapter);
12612 + iounmap(adapter->CSRAddress);
12613 + free_netdev(netdev);
12614 + pci_release_regions(pdev);
12615 + pci_disable_device(pdev);
12616 +
12617 + DBG_LEAVE(et131x_dbginfo);
12618 +}
12619 +
12620 +/**
12621 + * et131x_pci_setup - Perform device initialization
12622 + * @pdev: a pointer to the device's pci_dev structure
12623 + * @ent: this device's entry in the pci_device_id table
12624 + *
12625 + * Returns 0 on success, errno on failure (as defined in errno.h)
12626 + *
12627 + * Registered in the pci_driver structure, this function is called when the
12628 + * PCI subsystem finds a new PCI device which matches the information
12629 + * contained in the pci_device_id table. This routine is the equivalent to
12630 + * a device insertion routine.
12631 + */
12632 +int __devinit et131x_pci_setup(struct pci_dev *pdev,
12633 + const struct pci_device_id *ent)
12634 +{
12635 + int result = 0;
12636 + int pm_cap;
12637 + bool pci_using_dac;
12638 + struct net_device *netdev = NULL;
12639 + struct et131x_adapter *adapter = NULL;
12640 +
12641 + DBG_ENTER(et131x_dbginfo);
12642 +
12643 + /* Enable the device via the PCI subsystem */
12644 + result = pci_enable_device(pdev);
12645 + if (result != 0) {
12646 + DBG_ERROR(et131x_dbginfo, "pci_enable_device() failed\n");
12647 + goto out;
12648 + }
12649 +
12650 + /* Perform some basic PCI checks */
12651 + if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12652 + DBG_ERROR(et131x_dbginfo,
12653 + "Can't find PCI device's base address\n");
12654 + result = -ENODEV;
12655 + goto out;
12656 + }
12657 +
12658 + result = pci_request_regions(pdev, DRIVER_NAME);
12659 + if (result != 0) {
12660 + DBG_ERROR(et131x_dbginfo, "Can't get PCI resources\n");
12661 + goto err_disable;
12662 + }
12663 +
12664 + /* Enable PCI bus mastering */
12665 + DBG_TRACE(et131x_dbginfo, "Setting PCI Bus Mastering...\n");
12666 + pci_set_master(pdev);
12667 +
12668 + /* Query PCI for Power Mgmt Capabilities
12669 + *
12670 + * NOTE: Now reading PowerMgmt in another location; is this still
12671 + * needed?
12672 + */
12673 + pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
12674 + if (pm_cap == 0) {
12675 + DBG_ERROR(et131x_dbginfo,
12676 + "Cannot find Power Management capabilities\n");
12677 + result = -EIO;
12678 + goto err_release_res;
12679 + }
12680 +
12681 + /* Check the DMA addressing support of this device */
12682 + if (!pci_set_dma_mask(pdev, 0xffffffffffffffffULL)) {
12683 + DBG_TRACE(et131x_dbginfo, "64-bit DMA addressing supported\n");
12684 + pci_using_dac = true;
12685 +
12686 + result =
12687 + pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL);
12688 + if (result != 0) {
12689 + DBG_ERROR(et131x_dbginfo,
12690 + "Unable to obtain 64 bit DMA for consistent allocations\n");
12691 + goto err_release_res;
12692 + }
12693 + } else if (!pci_set_dma_mask(pdev, 0xffffffffULL)) {
12694 + DBG_TRACE(et131x_dbginfo,
12695 + "64-bit DMA addressing NOT supported\n");
12696 + DBG_TRACE(et131x_dbginfo,
12697 + "32-bit DMA addressing will be used\n");
12698 + pci_using_dac = false;
12699 + } else {
12700 + DBG_ERROR(et131x_dbginfo, "No usable DMA addressing method\n");
12701 + result = -EIO;
12702 + goto err_release_res;
12703 + }
12704 +
12705 + /* Allocate netdev and private adapter structs */
12706 + DBG_TRACE(et131x_dbginfo,
12707 + "Allocate netdev and private adapter structs...\n");
12708 + netdev = et131x_device_alloc();
12709 + if (netdev == NULL) {
12710 + DBG_ERROR(et131x_dbginfo, "Couldn't alloc netdev struct\n");
12711 + result = -ENOMEM;
12712 + goto err_release_res;
12713 + }
12714 +
12715 + /* Setup the fundamental net_device and private adapter structure elements */
12716 + DBG_TRACE(et131x_dbginfo, "Setting fundamental net_device info...\n");
12717 + SET_NETDEV_DEV(netdev, &pdev->dev);
12718 + if (pci_using_dac) {
12719 + //netdev->features |= NETIF_F_HIGHDMA;
12720 + }
12721 +
12722 + /*
12723 + * NOTE - Turn this on when we're ready to deal with SG-DMA
12724 + *
12725 + * NOTE: According to "Linux Device Drivers", 3rd ed, Rubini et al,
12726 + * if checksumming is not performed in HW, then the kernel will not
12727 + * use SG.
12728 + * From pp 510-511:
12729 + *
12730 + * "Note that the kernel does not perform scatter/gather I/O to your
12731 + * device if it does not also provide some form of checksumming as
12732 + * well. The reason is that, if the kernel has to make a pass over a
12733 + * fragmented ("nonlinear") packet to calculate the checksum, it
12734 + * might as well copy the data and coalesce the packet at the same
12735 + * time."
12736 + *
12737 + * This has been verified by setting the flags below and still not
12738 + * receiving a scattered buffer from the network stack, so leave it
12739 + * off until checksums are calculated in HW.
12740 + */
12741 + //netdev->features |= NETIF_F_SG;
12742 + //netdev->features |= NETIF_F_NO_CSUM;
12743 + //netdev->features |= NETIF_F_LLTX;
12744 +
12745 + /* Allocate private adapter struct and copy in relevant information */
12746 + adapter = netdev_priv(netdev);
12747 + adapter->pdev = pdev;
12748 + adapter->netdev = netdev;
12749 + adapter->VendorID = pdev->vendor;
12750 + adapter->DeviceID = pdev->device;
12751 +
12752 + /* Do the same for the netdev struct */
12753 + netdev->irq = pdev->irq;
12754 + netdev->base_addr = pdev->resource[0].start;
12755 +
12756 + /* Initialize spinlocks here */
12757 + DBG_TRACE(et131x_dbginfo, "Initialize spinlocks...\n");
12758 +
12759 + spin_lock_init(&adapter->Lock);
12760 + spin_lock_init(&adapter->TCBSendQLock);
12761 + spin_lock_init(&adapter->TCBReadyQLock);
12762 + spin_lock_init(&adapter->SendHWLock);
12763 + spin_lock_init(&adapter->SendWaitLock);
12764 + spin_lock_init(&adapter->RcvLock);
12765 + spin_lock_init(&adapter->RcvPendLock);
12766 + spin_lock_init(&adapter->FbrLock);
12767 + spin_lock_init(&adapter->PHYLock);
12768 +
12769 + /* Parse configuration parameters into the private adapter struct */
12770 + et131x_config_parse(adapter);
12771 +
12772 + /* Find the physical adapter
12773 + *
12774 + * NOTE: This is the equivalent of the MpFindAdapter() routine; can we
12775 + * lump it's init with the device specific init below into a
12776 + * single init function?
12777 + */
12778 + //while (et131x_find_adapter(adapter, pdev) != 0);
12779 + et131x_find_adapter(adapter, pdev);
12780 +
12781 + /* Map the bus-relative registers to system virtual memory */
12782 + DBG_TRACE(et131x_dbginfo,
12783 + "Mapping bus-relative registers to virtual memory...\n");
12784 +
12785 + adapter->CSRAddress = ioremap_nocache(pci_resource_start(pdev, 0),
12786 + pci_resource_len(pdev, 0));
12787 + if (adapter->CSRAddress == NULL) {
12788 + DBG_ERROR(et131x_dbginfo, "Cannot map device registers\n");
12789 + result = -ENOMEM;
12790 + goto err_free_dev;
12791 + }
12792 +
12793 + /* Perform device-specific initialization here (See code below) */
12794 +
12795 + /* If Phy COMA mode was enabled when we went down, disable it here. */
12796 + {
12797 + PM_CSR_t GlobalPmCSR = { 0 };
12798 +
12799 + GlobalPmCSR.bits.pm_sysclk_gate = 1;
12800 + GlobalPmCSR.bits.pm_txclk_gate = 1;
12801 + GlobalPmCSR.bits.pm_rxclk_gate = 1;
12802 + writel(GlobalPmCSR.value,
12803 + &adapter->CSRAddress->global.pm_csr.value);
12804 + }
12805 +
12806 + /* Issue a global reset to the et1310 */
12807 + DBG_TRACE(et131x_dbginfo, "Issuing soft reset...\n");
12808 + et131x_soft_reset(adapter);
12809 +
12810 + /* Disable all interrupts (paranoid) */
12811 + DBG_TRACE(et131x_dbginfo, "Disable device interrupts...\n");
12812 + et131x_disable_interrupts(adapter);
12813 +
12814 + /* Allocate DMA memory */
12815 + result = et131x_adapter_memory_alloc(adapter);
12816 + if (result != 0) {
12817 + DBG_ERROR(et131x_dbginfo,
12818 + "Could not alloc adapater memory (DMA)\n");
12819 + goto err_iounmap;
12820 + }
12821 +
12822 + /* Init send data structures */
12823 + DBG_TRACE(et131x_dbginfo, "Init send data structures...\n");
12824 + et131x_init_send(adapter);
12825 +
12826 + adapter->PoMgmt.PowerState = NdisDeviceStateD0;
12827 +
12828 + /* Register the interrupt
12829 + *
12830 + * NOTE - This is being done in the open routine, where most other
12831 + * Linux drivers setup IRQ handlers. Make sure device
12832 + * interrupts are not turned on before the IRQ is registered!!
12833 + *
12834 + * What we will do here is setup the task structure for the
12835 + * ISR's deferred handler
12836 + */
12837 + INIT_WORK(&adapter->task, et131x_isr_handler);
12838 +
12839 + /* Determine MAC Address, and copy into the net_device struct */
12840 + DBG_TRACE(et131x_dbginfo, "Retrieve MAC address...\n");
12841 + et131x_setup_hardware_properties(adapter);
12842 +
12843 + memcpy(netdev->dev_addr, adapter->CurrentAddress, ETH_ALEN);
12844 +
12845 + /* Setup et1310 as per the documentation */
12846 + DBG_TRACE(et131x_dbginfo, "Setup the adapter...\n");
12847 + et131x_adapter_setup(adapter);
12848 +
12849 + /* Create a timer to count errors received by the NIC */
12850 + init_timer(&adapter->ErrorTimer);
12851 +
12852 + adapter->ErrorTimer.expires = jiffies + TX_ERROR_PERIOD * HZ / 1000;
12853 + adapter->ErrorTimer.function = et131x_error_timer_handler;
12854 + adapter->ErrorTimer.data = (unsigned long)adapter;
12855 +
12856 + /* Initialize link state */
12857 + et131x_link_detection_handler((unsigned long)adapter);
12858 +
12859 + /* Intialize variable for counting how long we do not have link status */
12860 + adapter->PoMgmt.TransPhyComaModeOnBoot = 0;
12861 +
12862 + /* We can enable interrupts now
12863 + *
12864 + * NOTE - Because registration of interrupt handler is done in the
12865 + * device's open(), defer enabling device interrupts to that
12866 + * point
12867 + */
12868 +
12869 + /* Register the net_device struct with the Linux network layer */
12870 + DBG_TRACE(et131x_dbginfo, "Registering net_device...\n");
12871 + if ((result = register_netdev(netdev)) != 0) {
12872 + DBG_ERROR(et131x_dbginfo, "register_netdev() failed\n");
12873 + goto err_mem_free;
12874 + }
12875 +
12876 + /* Register the net_device struct with the PCI subsystem. Save a copy
12877 + * of the PCI config space for this device now that the device has
12878 + * been initialized, just in case it needs to be quickly restored.
12879 + */
12880 + pci_set_drvdata(pdev, netdev);
12881 +
12882 + pci_save_state(adapter->pdev);
12883 +
12884 +out:
12885 + DBG_LEAVE(et131x_dbginfo);
12886 + return result;
12887 +
12888 +err_mem_free:
12889 + et131x_adapter_memory_free(adapter);
12890 +err_iounmap:
12891 + iounmap(adapter->CSRAddress);
12892 +err_free_dev:
12893 + free_netdev(netdev);
12894 +err_release_res:
12895 + pci_release_regions(pdev);
12896 +err_disable:
12897 + pci_disable_device(pdev);
12898 + goto out;
12899 +}
12900 diff --git a/drivers/staging/et131x/et131x_initpci.h b/drivers/staging/et131x/et131x_initpci.h
12901 new file mode 100644
12902 index 0000000..bbacb62
12903 --- /dev/null
12904 +++ b/drivers/staging/et131x/et131x_initpci.h
12905 @@ -0,0 +1,73 @@
12906 +/*
12907 + * Agere Systems Inc.
12908 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
12909 + *
12910 + * Copyright © 2005 Agere Systems Inc.
12911 + * All rights reserved.
12912 + * http://www.agere.com
12913 + *
12914 + *------------------------------------------------------------------------------
12915 + *
12916 + * et131x_initpci.h - Header which includes common data and function prototypes
12917 + * related to the driver's PCI (and PCI Express) information.
12918 + *
12919 + *------------------------------------------------------------------------------
12920 + *
12921 + * SOFTWARE LICENSE
12922 + *
12923 + * This software is provided subject to the following terms and conditions,
12924 + * which you should read carefully before using the software. Using this
12925 + * software indicates your acceptance of these terms and conditions. If you do
12926 + * not agree with these terms and conditions, do not use the software.
12927 + *
12928 + * Copyright © 2005 Agere Systems Inc.
12929 + * All rights reserved.
12930 + *
12931 + * Redistribution and use in source or binary forms, with or without
12932 + * modifications, are permitted provided that the following conditions are met:
12933 + *
12934 + * . Redistributions of source code must retain the above copyright notice, this
12935 + * list of conditions and the following Disclaimer as comments in the code as
12936 + * well as in the documentation and/or other materials provided with the
12937 + * distribution.
12938 + *
12939 + * . Redistributions in binary form must reproduce the above copyright notice,
12940 + * this list of conditions and the following Disclaimer in the documentation
12941 + * and/or other materials provided with the distribution.
12942 + *
12943 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
12944 + * may be used to endorse or promote products derived from this software
12945 + * without specific prior written permission.
12946 + *
12947 + * Disclaimer
12948 + *
12949 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
12950 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
12951 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
12952 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
12953 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
12954 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
12955 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
12956 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
12957 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
12958 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
12959 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
12960 + * DAMAGE.
12961 + *
12962 + */
12963 +
12964 +#ifndef __ET131X_INITPCI_H__
12965 +#define __ET131X_INITPCI_H__
12966 +
12967 +/* Function Prototypes */
12968 +void et131x_align_allocated_memory(struct et131x_adapter *adapter,
12969 + u64 *phys_addr,
12970 + u64 *offset, u64 mask);
12971 +
12972 +int et131x_adapter_setup(struct et131x_adapter *adapter);
12973 +int et131x_adapter_memory_alloc(struct et131x_adapter *adapter);
12974 +void et131x_adapter_memory_free(struct et131x_adapter *adapter);
12975 +void et131x_setup_hardware_properties(struct et131x_adapter *adapter);
12976 +void et131x_soft_reset(struct et131x_adapter *adapter);
12977 +
12978 +#endif /* __ET131X_INITPCI_H__ */
12979 diff --git a/drivers/staging/et131x/et131x_isr.c b/drivers/staging/et131x/et131x_isr.c
12980 new file mode 100644
12981 index 0000000..00afad1
12982 --- /dev/null
12983 +++ b/drivers/staging/et131x/et131x_isr.c
12984 @@ -0,0 +1,488 @@
12985 +/*
12986 + * Agere Systems Inc.
12987 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
12988 + *
12989 + * Copyright © 2005 Agere Systems Inc.
12990 + * All rights reserved.
12991 + * http://www.agere.com
12992 + *
12993 + *------------------------------------------------------------------------------
12994 + *
12995 + * et131x_isr.c - File which contains the ISR, ISR handler, and related routines
12996 + * for processing interrupts from the device.
12997 + *
12998 + *------------------------------------------------------------------------------
12999 + *
13000 + * SOFTWARE LICENSE
13001 + *
13002 + * This software is provided subject to the following terms and conditions,
13003 + * which you should read carefully before using the software. Using this
13004 + * software indicates your acceptance of these terms and conditions. If you do
13005 + * not agree with these terms and conditions, do not use the software.
13006 + *
13007 + * Copyright © 2005 Agere Systems Inc.
13008 + * All rights reserved.
13009 + *
13010 + * Redistribution and use in source or binary forms, with or without
13011 + * modifications, are permitted provided that the following conditions are met:
13012 + *
13013 + * . Redistributions of source code must retain the above copyright notice, this
13014 + * list of conditions and the following Disclaimer as comments in the code as
13015 + * well as in the documentation and/or other materials provided with the
13016 + * distribution.
13017 + *
13018 + * . Redistributions in binary form must reproduce the above copyright notice,
13019 + * this list of conditions and the following Disclaimer in the documentation
13020 + * and/or other materials provided with the distribution.
13021 + *
13022 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
13023 + * may be used to endorse or promote products derived from this software
13024 + * without specific prior written permission.
13025 + *
13026 + * Disclaimer
13027 + *
13028 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
13029 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
13030 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
13031 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
13032 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
13033 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
13034 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
13035 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
13036 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
13037 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
13038 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
13039 + * DAMAGE.
13040 + *
13041 + */
13042 +
13043 +#include "et131x_version.h"
13044 +#include "et131x_debug.h"
13045 +#include "et131x_defs.h"
13046 +
13047 +#include <linux/init.h>
13048 +#include <linux/module.h>
13049 +#include <linux/types.h>
13050 +#include <linux/kernel.h>
13051 +
13052 +#include <linux/sched.h>
13053 +#include <linux/ptrace.h>
13054 +#include <linux/slab.h>
13055 +#include <linux/ctype.h>
13056 +#include <linux/string.h>
13057 +#include <linux/timer.h>
13058 +#include <linux/interrupt.h>
13059 +#include <linux/in.h>
13060 +#include <linux/delay.h>
13061 +#include <asm/io.h>
13062 +#include <asm/system.h>
13063 +#include <asm/bitops.h>
13064 +
13065 +#include <linux/netdevice.h>
13066 +#include <linux/etherdevice.h>
13067 +#include <linux/skbuff.h>
13068 +#include <linux/if_arp.h>
13069 +#include <linux/ioport.h>
13070 +
13071 +#include "et1310_phy.h"
13072 +#include "et1310_pm.h"
13073 +#include "et1310_jagcore.h"
13074 +#include "et1310_mac.h"
13075 +
13076 +#include "et131x_adapter.h"
13077 +
13078 +/* Data for debugging facilities */
13079 +#ifdef CONFIG_ET131X_DEBUG
13080 +extern dbg_info_t *et131x_dbginfo;
13081 +#endif /* CONFIG_ET131X_DEBUG */
13082 +
13083 +/**
13084 + * et131x_isr - The Interrupt Service Routine for the driver.
13085 + * @irq: the IRQ on which the interrupt was received.
13086 + * @dev_id: device-specific info (here a pointer to a net_device struct)
13087 + *
13088 + * Returns a value indicating if the interrupt was handled.
13089 + */
13090 +irqreturn_t et131x_isr(int irq, void *dev_id)
13091 +{
13092 + bool handled = true;
13093 + struct net_device *netdev = (struct net_device *)dev_id;
13094 + struct et131x_adapter *adapter = NULL;
13095 + INTERRUPT_t status;
13096 +
13097 + if (netdev == NULL || !netif_device_present(netdev)) {
13098 + DBG_WARNING(et131x_dbginfo,
13099 + "No net_device struct or device not present\n");
13100 + handled = false;
13101 + goto out;
13102 + }
13103 +
13104 + adapter = netdev_priv(netdev);
13105 +
13106 + /* If the adapter is in low power state, then it should not
13107 + * recognize any interrupt
13108 + */
13109 +
13110 + /* Disable Device Interrupts */
13111 + et131x_disable_interrupts(adapter);
13112 +
13113 + /* Get a copy of the value in the interrupt status register
13114 + * so we can process the interrupting section
13115 + */
13116 + status.value = readl(&adapter->CSRAddress->global.int_status.value);
13117 +
13118 + if (adapter->FlowControl == TxOnly ||
13119 + adapter->FlowControl == Both) {
13120 + status.value &= ~INT_MASK_ENABLE;
13121 + } else {
13122 + status.value &= ~INT_MASK_ENABLE_NO_FLOW;
13123 + }
13124 +
13125 + /* Make sure this is our interrupt */
13126 + if (!status.value) {
13127 +#ifdef CONFIG_ET131X_DEBUG
13128 + adapter->Stats.UnhandledInterruptsPerSec++;
13129 +#endif
13130 + handled = false;
13131 + DBG_VERBOSE(et131x_dbginfo, "NOT OUR INTERRUPT\n");
13132 + et131x_enable_interrupts(adapter);
13133 + goto out;
13134 + }
13135 +
13136 + /* This is our interrupt, so process accordingly */
13137 +#ifdef CONFIG_ET131X_DEBUG
13138 + if (status.bits.rxdma_xfr_done) {
13139 + adapter->Stats.RxDmaInterruptsPerSec++;
13140 + }
13141 +
13142 + if (status.bits.txdma_isr) {
13143 + adapter->Stats.TxDmaInterruptsPerSec++;
13144 + }
13145 +#endif
13146 +
13147 + if (status.bits.watchdog_interrupt) {
13148 + PMP_TCB pMpTcb = adapter->TxRing.CurrSendHead;
13149 +
13150 + if (pMpTcb) {
13151 + if (++pMpTcb->PacketStaleCount > 1) {
13152 + status.bits.txdma_isr = 1;
13153 + }
13154 + }
13155 +
13156 + if (adapter->RxRing.UnfinishedReceives) {
13157 + status.bits.rxdma_xfr_done = 1;
13158 + } else if (pMpTcb == NULL) {
13159 + writel(0, &adapter->CSRAddress->global.watchdog_timer);
13160 + }
13161 +
13162 + status.bits.watchdog_interrupt = 0;
13163 +#ifdef CONFIG_ET131X_DEBUG
13164 + adapter->Stats.WatchDogInterruptsPerSec++;
13165 +#endif
13166 + }
13167 +
13168 + if (status.value == 0) {
13169 + /* This interrupt has in some way been "handled" by
13170 + * the ISR. Either it was a spurious Rx interrupt, or
13171 + * it was a Tx interrupt that has been filtered by
13172 + * the ISR.
13173 + */
13174 + et131x_enable_interrupts(adapter);
13175 + goto out;
13176 + }
13177 +
13178 + /* We need to save the interrupt status value for use in our
13179 + * DPC. We will clear the software copy of that in that
13180 + * routine.
13181 + */
13182 + adapter->Stats.InterruptStatus = status;
13183 +
13184 + /* Schedule the ISR handler as a bottom-half task in the
13185 + * kernel's tq_immediate queue, and mark the queue for
13186 + * execution
13187 + */
13188 + schedule_work(&adapter->task);
13189 +
13190 +out:
13191 + return IRQ_RETVAL(handled);
13192 +}
13193 +
13194 +/**
13195 + * et131x_isr_handler - The ISR handler
13196 + * @p_adapter, a pointer to the device's private adapter structure
13197 + *
13198 + * scheduled to run in a deferred context by the ISR. This is where the ISR's
13199 + * work actually gets done.
13200 + */
13201 +void et131x_isr_handler(struct work_struct *work)
13202 +{
13203 + struct et131x_adapter *pAdapter =
13204 + container_of(work, struct et131x_adapter, task);
13205 + INTERRUPT_t GlobStatus = pAdapter->Stats.InterruptStatus;
13206 + ADDRESS_MAP_t __iomem *iomem = pAdapter->CSRAddress;
13207 +
13208 + /*
13209 + * These first two are by far the most common. Once handled, we clear
13210 + * their two bits in the status word. If the word is now zero, we
13211 + * exit.
13212 + */
13213 + /* Handle all the completed Transmit interrupts */
13214 + if (GlobStatus.bits.txdma_isr) {
13215 + DBG_TX(et131x_dbginfo, "TXDMA_ISR interrupt\n");
13216 + et131x_handle_send_interrupt(pAdapter);
13217 + }
13218 +
13219 + /* Handle all the completed Receives interrupts */
13220 + if (GlobStatus.bits.rxdma_xfr_done) {
13221 + DBG_RX(et131x_dbginfo, "RXDMA_XFR_DONE interrupt\n");
13222 + et131x_handle_recv_interrupt(pAdapter);
13223 + }
13224 +
13225 + GlobStatus.value &= 0xffffffd7;
13226 +
13227 + if (GlobStatus.value) {
13228 + /* Handle the TXDMA Error interrupt */
13229 + if (GlobStatus.bits.txdma_err) {
13230 + TXDMA_ERROR_t TxDmaErr;
13231 +
13232 + /* Following read also clears the register (COR) */
13233 + TxDmaErr.value = readl(&iomem->txdma.TxDmaError.value);
13234 +
13235 + DBG_WARNING(et131x_dbginfo,
13236 + "TXDMA_ERR interrupt, error = %d\n",
13237 + TxDmaErr.value);
13238 + }
13239 +
13240 + /* Handle Free Buffer Ring 0 and 1 Low interrupt */
13241 + if (GlobStatus.bits.rxdma_fb_ring0_low ||
13242 + GlobStatus.bits.rxdma_fb_ring1_low) {
13243 + /*
13244 + * This indicates the number of unused buffers in
13245 + * RXDMA free buffer ring 0 is <= the limit you
13246 + * programmed. Free buffer resources need to be
13247 + * returned. Free buffers are consumed as packets
13248 + * are passed from the network to the host. The host
13249 + * becomes aware of the packets from the contents of
13250 + * the packet status ring. This ring is queried when
13251 + * the packet done interrupt occurs. Packets are then
13252 + * passed to the OS. When the OS is done with the
13253 + * packets the resources can be returned to the
13254 + * ET1310 for re-use. This interrupt is one method of
13255 + * returning resources.
13256 + */
13257 + DBG_WARNING(et131x_dbginfo,
13258 + "RXDMA_FB_RING0_LOW or "
13259 + "RXDMA_FB_RING1_LOW interrupt\n");
13260 +
13261 + /* If the user has flow control on, then we will
13262 + * send a pause packet, otherwise just exit
13263 + */
13264 + if (pAdapter->FlowControl == TxOnly ||
13265 + pAdapter->FlowControl == Both) {
13266 + PM_CSR_t pm_csr;
13267 +
13268 + /* Tell the device to send a pause packet via
13269 + * the back pressure register
13270 + */
13271 + pm_csr.value = readl(&iomem->global.pm_csr.value);
13272 + if (pm_csr.bits.pm_phy_sw_coma == 0) {
13273 + TXMAC_BP_CTRL_t bp_ctrl = { 0 };
13274 +
13275 + bp_ctrl.bits.bp_req = 1;
13276 + bp_ctrl.bits.bp_xonxoff = 1;
13277 + writel(bp_ctrl.value,
13278 + &iomem->txmac.bp_ctrl.value);
13279 + }
13280 + }
13281 + }
13282 +
13283 + /* Handle Packet Status Ring Low Interrupt */
13284 + if (GlobStatus.bits.rxdma_pkt_stat_ring_low) {
13285 + DBG_WARNING(et131x_dbginfo,
13286 + "RXDMA_PKT_STAT_RING_LOW interrupt\n");
13287 +
13288 + /*
13289 + * Same idea as with the two Free Buffer Rings.
13290 + * Packets going from the network to the host each
13291 + * consume a free buffer resource and a packet status
13292 + * resource. These resoures are passed to the OS.
13293 + * When the OS is done with the resources, they need
13294 + * to be returned to the ET1310. This is one method
13295 + * of returning the resources.
13296 + */
13297 + }
13298 +
13299 + /* Handle RXDMA Error Interrupt */
13300 + if (GlobStatus.bits.rxdma_err) {
13301 + /*
13302 + * The rxdma_error interrupt is sent when a time-out
13303 + * on a request issued by the JAGCore has occurred or
13304 + * a completion is returned with an un-successful
13305 + * status. In both cases the request is considered
13306 + * complete. The JAGCore will automatically re-try the
13307 + * request in question. Normally information on events
13308 + * like these are sent to the host using the "Advanced
13309 + * Error Reporting" capability. This interrupt is
13310 + * another way of getting similar information. The
13311 + * only thing required is to clear the interrupt by
13312 + * reading the ISR in the global resources. The
13313 + * JAGCore will do a re-try on the request. Normally
13314 + * you should never see this interrupt. If you start
13315 + * to see this interrupt occurring frequently then
13316 + * something bad has occurred. A reset might be the
13317 + * thing to do.
13318 + */
13319 + // TRAP();
13320 +
13321 + pAdapter->TxMacTest.value =
13322 + readl(&iomem->txmac.tx_test.value);
13323 + DBG_WARNING(et131x_dbginfo,
13324 + "RxDMA_ERR interrupt, error %x\n",
13325 + pAdapter->TxMacTest.value);
13326 + }
13327 +
13328 + /* Handle the Wake on LAN Event */
13329 + if (GlobStatus.bits.wake_on_lan) {
13330 + /*
13331 + * This is a secondary interrupt for wake on LAN.
13332 + * The driver should never see this, if it does,
13333 + * something serious is wrong. We will TRAP the
13334 + * message when we are in DBG mode, otherwise we
13335 + * will ignore it.
13336 + */
13337 + DBG_ERROR(et131x_dbginfo, "WAKE_ON_LAN interrupt\n");
13338 + }
13339 +
13340 + /* Handle the PHY interrupt */
13341 + if (GlobStatus.bits.phy_interrupt) {
13342 + PM_CSR_t pm_csr;
13343 + MI_BMSR_t BmsrInts, BmsrData;
13344 + MI_ISR_t myIsr;
13345 +
13346 + DBG_VERBOSE(et131x_dbginfo, "PHY interrupt\n");
13347 +
13348 + /* If we are in coma mode when we get this interrupt,
13349 + * we need to disable it.
13350 + */
13351 + pm_csr.value = readl(&iomem->global.pm_csr.value);
13352 + if (pm_csr.bits.pm_phy_sw_coma == 1) {
13353 + /*
13354 + * Check to see if we are in coma mode and if
13355 + * so, disable it because we will not be able
13356 + * to read PHY values until we are out.
13357 + */
13358 + DBG_VERBOSE(et131x_dbginfo,
13359 + "Device is in COMA mode, "
13360 + "need to wake up\n");
13361 + DisablePhyComa(pAdapter);
13362 + }
13363 +
13364 + /* Read the PHY ISR to clear the reason for the
13365 + * interrupt.
13366 + */
13367 + MiRead(pAdapter, (uint8_t) offsetof(MI_REGS_t, isr),
13368 + &myIsr.value);
13369 +
13370 + if (!pAdapter->ReplicaPhyLoopbk) {
13371 + MiRead(pAdapter,
13372 + (uint8_t) offsetof(MI_REGS_t, bmsr),
13373 + &BmsrData.value);
13374 +
13375 + BmsrInts.value =
13376 + pAdapter->Bmsr.value ^ BmsrData.value;
13377 + pAdapter->Bmsr.value = BmsrData.value;
13378 +
13379 + DBG_VERBOSE(et131x_dbginfo,
13380 + "Bmsr.value = 0x%04x,"
13381 + "Bmsr_ints.value = 0x%04x\n",
13382 + BmsrData.value, BmsrInts.value);
13383 +
13384 + /* Do all the cable in / cable out stuff */
13385 + et131x_Mii_check(pAdapter, BmsrData, BmsrInts);
13386 + }
13387 + }
13388 +
13389 + /* Let's move on to the TxMac */
13390 + if (GlobStatus.bits.txmac_interrupt) {
13391 + pAdapter->TxRing.TxMacErr.value =
13392 + readl(&iomem->txmac.err.value);
13393 +
13394 + /*
13395 + * When any of the errors occur and TXMAC generates
13396 + * an interrupt to report these errors, it usually
13397 + * means that TXMAC has detected an error in the data
13398 + * stream retrieved from the on-chip Tx Q. All of
13399 + * these errors are catastrophic and TXMAC won't be
13400 + * able to recover data when these errors occur. In
13401 + * a nutshell, the whole Tx path will have to be reset
13402 + * and re-configured afterwards.
13403 + */
13404 + DBG_WARNING(et131x_dbginfo,
13405 + "TXMAC interrupt, error 0x%08x\n",
13406 + pAdapter->TxRing.TxMacErr.value);
13407 +
13408 + /* If we are debugging, we want to see this error,
13409 + * otherwise we just want the device to be reset and
13410 + * continue
13411 + */
13412 + //DBG_TRAP();
13413 + }
13414 +
13415 + /* Handle RXMAC Interrupt */
13416 + if (GlobStatus.bits.rxmac_interrupt) {
13417 + /*
13418 + * These interrupts are catastrophic to the device,
13419 + * what we need to do is disable the interrupts and
13420 + * set the flag to cause us to reset so we can solve
13421 + * this issue.
13422 + */
13423 + // MP_SET_FLAG( pAdapter, fMP_ADAPTER_HARDWARE_ERROR );
13424 +
13425 + DBG_WARNING(et131x_dbginfo,
13426 + "RXMAC interrupt, error 0x%08x. Requesting reset\n",
13427 + readl(&iomem->rxmac.err_reg.value));
13428 +
13429 + DBG_WARNING(et131x_dbginfo,
13430 + "Enable 0x%08x, Diag 0x%08x\n",
13431 + readl(&iomem->rxmac.ctrl.value),
13432 + readl(&iomem->rxmac.rxq_diag.value));
13433 +
13434 + /*
13435 + * If we are debugging, we want to see this error,
13436 + * otherwise we just want the device to be reset and
13437 + * continue
13438 + */
13439 + // TRAP();
13440 + }
13441 +
13442 + /* Handle MAC_STAT Interrupt */
13443 + if (GlobStatus.bits.mac_stat_interrupt) {
13444 + /*
13445 + * This means at least one of the un-masked counters
13446 + * in the MAC_STAT block has rolled over. Use this
13447 + * to maintain the top, software managed bits of the
13448 + * counter(s).
13449 + */
13450 + DBG_VERBOSE(et131x_dbginfo, "MAC_STAT interrupt\n");
13451 + HandleMacStatInterrupt(pAdapter);
13452 + }
13453 +
13454 + /* Handle SLV Timeout Interrupt */
13455 + if (GlobStatus.bits.slv_timeout) {
13456 + /*
13457 + * This means a timeout has occured on a read or
13458 + * write request to one of the JAGCore registers. The
13459 + * Global Resources block has terminated the request
13460 + * and on a read request, returned a "fake" value.
13461 + * The most likely reasons are: Bad Address or the
13462 + * addressed module is in a power-down state and
13463 + * can't respond.
13464 + */
13465 + DBG_VERBOSE(et131x_dbginfo, "SLV_TIMEOUT interrupt\n");
13466 + }
13467 + }
13468 +
13469 + if (pAdapter->PoMgmt.PowerState == NdisDeviceStateD0) {
13470 + et131x_enable_interrupts(pAdapter);
13471 + }
13472 +}
13473 diff --git a/drivers/staging/et131x/et131x_isr.h b/drivers/staging/et131x/et131x_isr.h
13474 new file mode 100644
13475 index 0000000..76a51d5
13476 --- /dev/null
13477 +++ b/drivers/staging/et131x/et131x_isr.h
13478 @@ -0,0 +1,65 @@
13479 +/*
13480 + * Agere Systems Inc.
13481 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
13482 + *
13483 + * Copyright © 2005 Agere Systems Inc.
13484 + * All rights reserved.
13485 + * http://www.agere.com
13486 + *
13487 + *------------------------------------------------------------------------------
13488 + *
13489 + * et131x_isr.h - Defines, structs, enums, prototypes, etc. pertaining to the
13490 + * ISR processing code.
13491 + *
13492 + *------------------------------------------------------------------------------
13493 + *
13494 + * SOFTWARE LICENSE
13495 + *
13496 + * This software is provided subject to the following terms and conditions,
13497 + * which you should read carefully before using the software. Using this
13498 + * software indicates your acceptance of these terms and conditions. If you do
13499 + * not agree with these terms and conditions, do not use the software.
13500 + *
13501 + * Copyright © 2005 Agere Systems Inc.
13502 + * All rights reserved.
13503 + *
13504 + * Redistribution and use in source or binary forms, with or without
13505 + * modifications, are permitted provided that the following conditions are met:
13506 + *
13507 + * . Redistributions of source code must retain the above copyright notice, this
13508 + * list of conditions and the following Disclaimer as comments in the code as
13509 + * well as in the documentation and/or other materials provided with the
13510 + * distribution.
13511 + *
13512 + * . Redistributions in binary form must reproduce the above copyright notice,
13513 + * this list of conditions and the following Disclaimer in the documentation
13514 + * and/or other materials provided with the distribution.
13515 + *
13516 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
13517 + * may be used to endorse or promote products derived from this software
13518 + * without specific prior written permission.
13519 + *
13520 + * Disclaimer
13521 + *
13522 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
13523 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
13524 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
13525 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
13526 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
13527 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
13528 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
13529 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
13530 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
13531 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
13532 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
13533 + * DAMAGE.
13534 + *
13535 + */
13536 +
13537 +#ifndef __ET131X_ISR_H__
13538 +#define __ET131X_ISR_H__
13539 +
13540 +irqreturn_t et131x_isr(int irq, void *dev_id);
13541 +void et131x_isr_handler(struct work_struct *work);
13542 +
13543 +#endif /* __ET131X_ISR_H__ */
13544 diff --git a/drivers/staging/et131x/et131x_netdev.c b/drivers/staging/et131x/et131x_netdev.c
13545 new file mode 100644
13546 index 0000000..de65972
13547 --- /dev/null
13548 +++ b/drivers/staging/et131x/et131x_netdev.c
13549 @@ -0,0 +1,856 @@
13550 +/*
13551 + * Agere Systems Inc.
13552 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
13553 + *
13554 + * Copyright © 2005 Agere Systems Inc.
13555 + * All rights reserved.
13556 + * http://www.agere.com
13557 + *
13558 + *------------------------------------------------------------------------------
13559 + *
13560 + * et131x_netdev.c - Routines and data required by all Linux network devices.
13561 + *
13562 + *------------------------------------------------------------------------------
13563 + *
13564 + * SOFTWARE LICENSE
13565 + *
13566 + * This software is provided subject to the following terms and conditions,
13567 + * which you should read carefully before using the software. Using this
13568 + * software indicates your acceptance of these terms and conditions. If you do
13569 + * not agree with these terms and conditions, do not use the software.
13570 + *
13571 + * Copyright © 2005 Agere Systems Inc.
13572 + * All rights reserved.
13573 + *
13574 + * Redistribution and use in source or binary forms, with or without
13575 + * modifications, are permitted provided that the following conditions are met:
13576 + *
13577 + * . Redistributions of source code must retain the above copyright notice, this
13578 + * list of conditions and the following Disclaimer as comments in the code as
13579 + * well as in the documentation and/or other materials provided with the
13580 + * distribution.
13581 + *
13582 + * . Redistributions in binary form must reproduce the above copyright notice,
13583 + * this list of conditions and the following Disclaimer in the documentation
13584 + * and/or other materials provided with the distribution.
13585 + *
13586 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
13587 + * may be used to endorse or promote products derived from this software
13588 + * without specific prior written permission.
13589 + *
13590 + * Disclaimer
13591 + *
13592 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
13593 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
13594 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
13595 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
13596 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
13597 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
13598 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
13599 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
13600 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
13601 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
13602 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
13603 + * DAMAGE.
13604 + *
13605 + */
13606 +
13607 +#include "et131x_version.h"
13608 +#include "et131x_debug.h"
13609 +#include "et131x_defs.h"
13610 +
13611 +#include <linux/init.h>
13612 +#include <linux/module.h>
13613 +#include <linux/types.h>
13614 +#include <linux/kernel.h>
13615 +
13616 +#include <linux/sched.h>
13617 +#include <linux/ptrace.h>
13618 +#include <linux/slab.h>
13619 +#include <linux/ctype.h>
13620 +#include <linux/string.h>
13621 +#include <linux/timer.h>
13622 +#include <linux/interrupt.h>
13623 +#include <linux/in.h>
13624 +#include <linux/delay.h>
13625 +#include <asm/io.h>
13626 +#include <asm/system.h>
13627 +#include <asm/bitops.h>
13628 +
13629 +#include <linux/mii.h>
13630 +#include <linux/netdevice.h>
13631 +#include <linux/etherdevice.h>
13632 +#include <linux/skbuff.h>
13633 +#include <linux/if_arp.h>
13634 +#include <linux/ioport.h>
13635 +
13636 +#include "et1310_phy.h"
13637 +#include "et1310_pm.h"
13638 +#include "et1310_jagcore.h"
13639 +#include "et1310_mac.h"
13640 +#include "et1310_tx.h"
13641 +
13642 +#include "et131x_adapter.h"
13643 +#include "et131x_isr.h"
13644 +#include "et131x_initpci.h"
13645 +
13646 +/* Data for debugging facilities */
13647 +#ifdef CONFIG_ET131X_DEBUG
13648 +extern dbg_info_t *et131x_dbginfo;
13649 +#endif /* CONFIG_ET131X_DEBUG */
13650 +
13651 +struct net_device_stats *et131x_stats(struct net_device *netdev);
13652 +int et131x_open(struct net_device *netdev);
13653 +int et131x_close(struct net_device *netdev);
13654 +int et131x_ioctl(struct net_device *netdev, struct ifreq *reqbuf, int cmd);
13655 +void et131x_multicast(struct net_device *netdev);
13656 +int et131x_tx(struct sk_buff *skb, struct net_device *netdev);
13657 +void et131x_tx_timeout(struct net_device *netdev);
13658 +int et131x_change_mtu(struct net_device *netdev, int new_mtu);
13659 +int et131x_set_mac_addr(struct net_device *netdev, void *new_mac);
13660 +void et131x_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
13661 +void et131x_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
13662 +void et131x_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
13663 +
13664 +/**
13665 + * et131x_device_alloc
13666 + *
13667 + * Returns pointer to the allocated and initialized net_device struct for
13668 + * this device.
13669 + *
13670 + * Create instances of net_device and wl_private for the new adapter and
13671 + * register the device's entry points in the net_device structure.
13672 + */
13673 +struct net_device *et131x_device_alloc(void)
13674 +{
13675 + struct net_device *netdev;
13676 +
13677 + DBG_ENTER(et131x_dbginfo);
13678 +
13679 + /* Alloc net_device and adapter structs */
13680 + netdev = alloc_etherdev(sizeof(struct et131x_adapter));
13681 +
13682 + if (netdev == NULL) {
13683 + DBG_ERROR(et131x_dbginfo,
13684 + "Alloc of net_device struct failed\n");
13685 + DBG_LEAVE(et131x_dbginfo);
13686 + return NULL;
13687 + }
13688 +
13689 + /* Setup the function registration table (and other data) for a
13690 + * net_device
13691 + */
13692 + //netdev->init = &et131x_init;
13693 + //netdev->set_config = &et131x_config;
13694 + netdev->get_stats = &et131x_stats;
13695 + netdev->open = &et131x_open;
13696 + netdev->stop = &et131x_close;
13697 + netdev->do_ioctl = &et131x_ioctl;
13698 + netdev->set_multicast_list = &et131x_multicast;
13699 + netdev->hard_start_xmit = &et131x_tx;
13700 + netdev->tx_timeout = &et131x_tx_timeout;
13701 + netdev->watchdog_timeo = ET131X_TX_TIMEOUT;
13702 + netdev->change_mtu = &et131x_change_mtu;
13703 + netdev->set_mac_address = &et131x_set_mac_addr;
13704 +
13705 + //netdev->ethtool_ops = &et131x_ethtool_ops;
13706 +
13707 + // Poll?
13708 + //netdev->poll = &et131x_poll;
13709 + //netdev->poll_controller = &et131x_poll_controller;
13710 +
13711 + DBG_LEAVE(et131x_dbginfo);
13712 + return netdev;
13713 +}
13714 +
13715 +/**
13716 + * et131x_stats - Return the current device statistics.
13717 + * @netdev: device whose stats are being queried
13718 + *
13719 + * Returns 0 on success, errno on failure (as defined in errno.h)
13720 + */
13721 +struct net_device_stats *et131x_stats(struct net_device *netdev)
13722 +{
13723 + struct et131x_adapter *adapter = netdev_priv(netdev);
13724 + struct net_device_stats *stats = &adapter->net_stats;
13725 + CE_STATS_t *devstat = &adapter->Stats;
13726 +
13727 + DBG_ENTER(et131x_dbginfo);
13728 +
13729 + stats->rx_packets = devstat->ipackets;
13730 + stats->tx_packets = devstat->opackets;
13731 + stats->rx_errors = devstat->length_err + devstat->alignment_err +
13732 + devstat->crc_err + devstat->code_violations + devstat->other_errors;
13733 + stats->tx_errors = devstat->max_pkt_error;
13734 + stats->multicast = devstat->multircv;
13735 + stats->collisions = devstat->collisions;
13736 +
13737 + stats->rx_length_errors = devstat->length_err;
13738 + stats->rx_over_errors = devstat->rx_ov_flow;
13739 + stats->rx_crc_errors = devstat->crc_err;
13740 +
13741 + // NOTE: These stats don't have corresponding values in CE_STATS, so we're
13742 + // going to have to update these directly from within the TX/RX code
13743 + //stats->rx_bytes = 20; //devstat->;
13744 + //stats->tx_bytes = 20; //devstat->;
13745 + //stats->rx_dropped = devstat->;
13746 + //stats->tx_dropped = devstat->;
13747 +
13748 + // NOTE: Not used, can't find analogous statistics
13749 + //stats->rx_frame_errors = devstat->;
13750 + //stats->rx_fifo_errors = devstat->;
13751 + //stats->rx_missed_errors = devstat->;
13752 +
13753 + //stats->tx_aborted_errors = devstat->;
13754 + //stats->tx_carrier_errors = devstat->;
13755 + //stats->tx_fifo_errors = devstat->;
13756 + //stats->tx_heartbeat_errors = devstat->;
13757 + //stats->tx_window_errors = devstat->;
13758 +
13759 + DBG_LEAVE(et131x_dbginfo);
13760 + return stats;
13761 +}
13762 +
13763 +/**
13764 + * et131x_open - Open the device for use.
13765 + * @netdev: device to be opened
13766 + *
13767 + * Returns 0 on success, errno on failure (as defined in errno.h)
13768 + */
13769 +int et131x_open(struct net_device *netdev)
13770 +{
13771 + int result = 0;
13772 + struct et131x_adapter *adapter = netdev_priv(netdev);
13773 +
13774 + DBG_ENTER(et131x_dbginfo);
13775 +
13776 + /* Start the timer to track NIC errors */
13777 + add_timer(&adapter->ErrorTimer);
13778 +
13779 + /* Register our ISR */
13780 + DBG_TRACE(et131x_dbginfo, "Registering ISR...\n");
13781 +
13782 + result =
13783 + request_irq(netdev->irq, et131x_isr, IRQF_SHARED, netdev->name,
13784 + netdev);
13785 + if (result) {
13786 + DBG_ERROR(et131x_dbginfo, "Could not register ISR\n");
13787 + DBG_LEAVE(et131x_dbginfo);
13788 + return result;
13789 + }
13790 +
13791 + /* Enable the Tx and Rx DMA engines (if not already enabled) */
13792 + et131x_rx_dma_enable(adapter);
13793 + et131x_tx_dma_enable(adapter);
13794 +
13795 + /* Enable device interrupts */
13796 + et131x_enable_interrupts(adapter);
13797 +
13798 + MP_SET_FLAG(adapter, fMP_ADAPTER_INTERRUPT_IN_USE);
13799 +
13800 + /* We're ready to move some data, so start the queue */
13801 + netif_start_queue(netdev);
13802 +
13803 + DBG_LEAVE(et131x_dbginfo);
13804 + return result;
13805 +}
13806 +
13807 +/**
13808 + * et131x_close - Close the device
13809 + * @netdev: device to be closed
13810 + *
13811 + * Returns 0 on success, errno on failure (as defined in errno.h)
13812 + */
13813 +int et131x_close(struct net_device *netdev)
13814 +{
13815 + struct et131x_adapter *adapter = netdev_priv(netdev);
13816 +
13817 + DBG_ENTER(et131x_dbginfo);
13818 +
13819 + /* First thing is to stop the queue */
13820 + netif_stop_queue(netdev);
13821 +
13822 + /* Stop the Tx and Rx DMA engines */
13823 + et131x_rx_dma_disable(adapter);
13824 + et131x_tx_dma_disable(adapter);
13825 +
13826 + /* Disable device interrupts */
13827 + et131x_disable_interrupts(adapter);
13828 +
13829 + /* Deregistering ISR */
13830 + MP_CLEAR_FLAG(adapter, fMP_ADAPTER_INTERRUPT_IN_USE);
13831 +
13832 + DBG_TRACE(et131x_dbginfo, "Deregistering ISR...\n");
13833 + free_irq(netdev->irq, netdev);
13834 +
13835 + /* Stop the error timer */
13836 + del_timer_sync(&adapter->ErrorTimer);
13837 +
13838 + DBG_LEAVE(et131x_dbginfo);
13839 + return 0;
13840 +}
13841 +
13842 +/**
13843 + * et131x_ioctl_mii - The function which handles MII IOCTLs
13844 + * @netdev: device on which the query is being made
13845 + * @reqbuf: the request-specific data buffer
13846 + * @cmd: the command request code
13847 + *
13848 + * Returns 0 on success, errno on failure (as defined in errno.h)
13849 + */
13850 +int et131x_ioctl_mii(struct net_device *netdev, struct ifreq *reqbuf, int cmd)
13851 +{
13852 + int status = 0;
13853 + struct et131x_adapter *pAdapter = netdev_priv(netdev);
13854 + struct mii_ioctl_data *data = if_mii(reqbuf);
13855 +
13856 + DBG_ENTER(et131x_dbginfo);
13857 +
13858 + switch (cmd) {
13859 + case SIOCGMIIPHY:
13860 + DBG_VERBOSE(et131x_dbginfo, "SIOCGMIIPHY\n");
13861 + data->phy_id = pAdapter->Stats.xcvr_addr;
13862 + break;
13863 +
13864 + case SIOCGMIIREG:
13865 + DBG_VERBOSE(et131x_dbginfo, "SIOCGMIIREG\n");
13866 + if (!capable(CAP_NET_ADMIN)) {
13867 + status = -EPERM;
13868 + } else {
13869 + status = MiRead(pAdapter,
13870 + data->reg_num, &data->val_out);
13871 + }
13872 + break;
13873 +
13874 + case SIOCSMIIREG:
13875 + DBG_VERBOSE(et131x_dbginfo, "SIOCSMIIREG\n");
13876 + if (!capable(CAP_NET_ADMIN)) {
13877 + status = -EPERM;
13878 + } else {
13879 + status = MiWrite(pAdapter, data->reg_num,
13880 + data->val_in);
13881 + }
13882 + break;
13883 +
13884 + default:
13885 + status = -EOPNOTSUPP;
13886 + }
13887 +
13888 + DBG_LEAVE(et131x_dbginfo);
13889 + return status;
13890 +}
13891 +
13892 +/**
13893 + * et131x_ioctl - The I/O Control handler for the driver
13894 + * @netdev: device on which the control request is being made
13895 + * @reqbuf: a pointer to the IOCTL request buffer
13896 + * @cmd: the IOCTL command code
13897 + *
13898 + * Returns 0 on success, errno on failure (as defined in errno.h)
13899 + */
13900 +int et131x_ioctl(struct net_device *netdev, struct ifreq *reqbuf, int cmd)
13901 +{
13902 + int status = 0;
13903 +
13904 + DBG_ENTER(et131x_dbginfo);
13905 +
13906 + switch (cmd) {
13907 + case SIOCGMIIPHY:
13908 + case SIOCGMIIREG:
13909 + case SIOCSMIIREG:
13910 + status = et131x_ioctl_mii(netdev, reqbuf, cmd);
13911 + break;
13912 +
13913 + default:
13914 + DBG_WARNING(et131x_dbginfo, "Unhandled IOCTL Code: 0x%04x\n",
13915 + cmd);
13916 + status = -EOPNOTSUPP;
13917 + }
13918 +
13919 + DBG_LEAVE(et131x_dbginfo);
13920 + return status;
13921 +}
13922 +
13923 +/**
13924 + * et131x_set_packet_filter - Configures the Rx Packet filtering on the device
13925 + * @adapter: pointer to our private adapter structure
13926 + *
13927 + * Returns 0 on success, errno on failure
13928 + */
13929 +int et131x_set_packet_filter(struct et131x_adapter *adapter)
13930 +{
13931 + int status = 0;
13932 + uint32_t filter = adapter->PacketFilter;
13933 + RXMAC_CTRL_t ctrl;
13934 + RXMAC_PF_CTRL_t pf_ctrl;
13935 +
13936 + DBG_ENTER(et131x_dbginfo);
13937 +
13938 + ctrl.value = readl(&adapter->CSRAddress->rxmac.ctrl.value);
13939 + pf_ctrl.value = readl(&adapter->CSRAddress->rxmac.pf_ctrl.value);
13940 +
13941 + /* Default to disabled packet filtering. Enable it in the individual
13942 + * case statements that require the device to filter something
13943 + */
13944 + ctrl.bits.pkt_filter_disable = 1;
13945 +
13946 + /* Set us to be in promiscuous mode so we receive everything, this
13947 + * is also true when we get a packet filter of 0
13948 + */
13949 + if ((filter & ET131X_PACKET_TYPE_PROMISCUOUS) || filter == 0) {
13950 + pf_ctrl.bits.filter_broad_en = 0;
13951 + pf_ctrl.bits.filter_multi_en = 0;
13952 + pf_ctrl.bits.filter_uni_en = 0;
13953 + } else {
13954 + /*
13955 + * Set us up with Multicast packet filtering. Three cases are
13956 + * possible - (1) we have a multi-cast list, (2) we receive ALL
13957 + * multicast entries or (3) we receive none.
13958 + */
13959 + if (filter & ET131X_PACKET_TYPE_ALL_MULTICAST) {
13960 + DBG_VERBOSE(et131x_dbginfo,
13961 + "Multicast filtering OFF (Rx ALL MULTICAST)\n");
13962 + pf_ctrl.bits.filter_multi_en = 0;
13963 + } else {
13964 + DBG_VERBOSE(et131x_dbginfo, "Multicast filtering ON\n");
13965 + SetupDeviceForMulticast(adapter);
13966 + pf_ctrl.bits.filter_multi_en = 1;
13967 + ctrl.bits.pkt_filter_disable = 0;
13968 + }
13969 +
13970 + /* Set us up with Unicast packet filtering */
13971 + if (filter & ET131X_PACKET_TYPE_DIRECTED) {
13972 + DBG_VERBOSE(et131x_dbginfo, "Unicast Filtering ON\n");
13973 + SetupDeviceForUnicast(adapter);
13974 + pf_ctrl.bits.filter_uni_en = 1;
13975 + ctrl.bits.pkt_filter_disable = 0;
13976 + }
13977 +
13978 + /* Set us up with Broadcast packet filtering */
13979 + if (filter & ET131X_PACKET_TYPE_BROADCAST) {
13980 + DBG_VERBOSE(et131x_dbginfo, "Broadcast Filtering ON\n");
13981 + pf_ctrl.bits.filter_broad_en = 1;
13982 + ctrl.bits.pkt_filter_disable = 0;
13983 + } else {
13984 + DBG_VERBOSE(et131x_dbginfo,
13985 + "Broadcast Filtering OFF\n");
13986 + pf_ctrl.bits.filter_broad_en = 0;
13987 + }
13988 +
13989 + /* Setup the receive mac configuration registers - Packet
13990 + * Filter control + the enable / disable for packet filter
13991 + * in the control reg.
13992 + */
13993 + writel(pf_ctrl.value,
13994 + &adapter->CSRAddress->rxmac.pf_ctrl.value);
13995 + writel(ctrl.value, &adapter->CSRAddress->rxmac.ctrl.value);
13996 + }
13997 +
13998 + DBG_LEAVE(et131x_dbginfo);
13999 + return status;
14000 +}
14001 +
14002 +/**
14003 + * et131x_multicast - The handler to configure multicasting on the interface
14004 + * @netdev: a pointer to a net_device struct representing the device
14005 + */
14006 +void et131x_multicast(struct net_device *netdev)
14007 +{
14008 + struct et131x_adapter *adapter = netdev_priv(netdev);
14009 + uint32_t PacketFilter = 0;
14010 + uint32_t count;
14011 + unsigned long lockflags;
14012 + struct dev_mc_list *mclist = netdev->mc_list;
14013 +
14014 + DBG_ENTER(et131x_dbginfo);
14015 +
14016 + spin_lock_irqsave(&adapter->Lock, lockflags);
14017 +
14018 + /* Before we modify the platform-independent filter flags, store them
14019 + * locally. This allows us to determine if anything's changed and if
14020 + * we even need to bother the hardware
14021 + */
14022 + PacketFilter = adapter->PacketFilter;
14023 +
14024 + /* Clear the 'multicast' flag locally; becuase we only have a single
14025 + * flag to check multicast, and multiple multicast addresses can be
14026 + * set, this is the easiest way to determine if more than one
14027 + * multicast address is being set.
14028 + */
14029 + PacketFilter &= ~ET131X_PACKET_TYPE_MULTICAST;
14030 +
14031 + /* Check the net_device flags and set the device independent flags
14032 + * accordingly
14033 + */
14034 + DBG_VERBOSE(et131x_dbginfo,
14035 + "MULTICAST ADDR COUNT: %d\n", netdev->mc_count);
14036 +
14037 + if (netdev->flags & IFF_PROMISC) {
14038 + DBG_VERBOSE(et131x_dbginfo, "Request: PROMISCUOUS MODE ON\n");
14039 + adapter->PacketFilter |= ET131X_PACKET_TYPE_PROMISCUOUS;
14040 + } else {
14041 + DBG_VERBOSE(et131x_dbginfo, "Request: PROMISCUOUS MODE OFF\n");
14042 + adapter->PacketFilter &= ~ET131X_PACKET_TYPE_PROMISCUOUS;
14043 + }
14044 +
14045 + if (netdev->flags & IFF_ALLMULTI) {
14046 + DBG_VERBOSE(et131x_dbginfo, "Request: ACCEPT ALL MULTICAST\n");
14047 + adapter->PacketFilter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
14048 + }
14049 +
14050 + if (netdev->mc_count > NIC_MAX_MCAST_LIST) {
14051 + DBG_WARNING(et131x_dbginfo,
14052 + "ACCEPT ALL MULTICAST for now, as there's more Multicast "
14053 + "addresses than the HW supports\n");
14054 +
14055 + adapter->PacketFilter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
14056 + }
14057 +
14058 + if (netdev->mc_count < 1) {
14059 + DBG_VERBOSE(et131x_dbginfo, "Request: REJECT ALL MULTICAST\n");
14060 + adapter->PacketFilter &= ~ET131X_PACKET_TYPE_ALL_MULTICAST;
14061 + adapter->PacketFilter &= ~ET131X_PACKET_TYPE_MULTICAST;
14062 + } else {
14063 + DBG_VERBOSE(et131x_dbginfo,
14064 + "Request: SET MULTICAST FILTER(S)\n");
14065 + adapter->PacketFilter |= ET131X_PACKET_TYPE_MULTICAST;
14066 + }
14067 +
14068 + /* Set values in the private adapter struct */
14069 + adapter->MCAddressCount = netdev->mc_count;
14070 +
14071 + if (netdev->mc_count) {
14072 + if (mclist->dmi_addrlen != ETH_ALEN) {
14073 + DBG_WARNING(et131x_dbginfo,
14074 + "Multicast addrs are not ETH_ALEN in size\n");
14075 + } else {
14076 + count = netdev->mc_count - 1;
14077 + memcpy(adapter->MCList[count], mclist->dmi_addr,
14078 + ETH_ALEN);
14079 + }
14080 + }
14081 +
14082 + /* Are the new flags different from the previous ones? If not, then no
14083 + * action is required
14084 + *
14085 + * NOTE - This block will always update the MCList with the hardware,
14086 + * even if the addresses aren't the same.
14087 + */
14088 + if (PacketFilter != adapter->PacketFilter) {
14089 + /* Call the device's filter function */
14090 + DBG_VERBOSE(et131x_dbginfo, "UPDATE REQUIRED, FLAGS changed\n");
14091 +
14092 + et131x_set_packet_filter(adapter);
14093 + } else {
14094 + DBG_VERBOSE(et131x_dbginfo,
14095 + "NO UPDATE REQUIRED, FLAGS didn't change\n");
14096 + }
14097 +
14098 + spin_unlock_irqrestore(&adapter->Lock, lockflags);
14099 +
14100 + DBG_LEAVE(et131x_dbginfo);
14101 +}
14102 +
14103 +/**
14104 + * et131x_tx - The handler to tx a packet on the device
14105 + * @skb: data to be Tx'd
14106 + * @netdev: device on which data is to be Tx'd
14107 + *
14108 + * Returns 0 on success, errno on failure (as defined in errno.h)
14109 + */
14110 +int et131x_tx(struct sk_buff *skb, struct net_device *netdev)
14111 +{
14112 + int status = 0;
14113 +
14114 + DBG_TX_ENTER(et131x_dbginfo);
14115 +
14116 + /* Save the timestamp for the TX timeout watchdog */
14117 + netdev->trans_start = jiffies;
14118 +
14119 + /* Call the device-specific data Tx routine */
14120 + status = et131x_send_packets(skb, netdev);
14121 +
14122 + /* Check status and manage the netif queue if necessary */
14123 + if (status != 0) {
14124 + if (status == -ENOMEM) {
14125 + DBG_VERBOSE(et131x_dbginfo,
14126 + "OUT OF TCBs; STOP NETIF QUEUE\n");
14127 +
14128 + /* Put the queue to sleep until resources are
14129 + * available
14130 + */
14131 + netif_stop_queue(netdev);
14132 + status = 1;
14133 + } else {
14134 + DBG_WARNING(et131x_dbginfo,
14135 + "Misc error; drop packet\n");
14136 + status = 0;
14137 + }
14138 + }
14139 +
14140 + DBG_TX_LEAVE(et131x_dbginfo);
14141 + return status;
14142 +}
14143 +
14144 +/**
14145 + * et131x_tx_timeout - Timeout handler
14146 + * @netdev: a pointer to a net_device struct representing the device
14147 + *
14148 + * The handler called when a Tx request times out. The timeout period is
14149 + * specified by the 'tx_timeo" element in the net_device structure (see
14150 + * et131x_alloc_device() to see how this value is set).
14151 + */
14152 +void et131x_tx_timeout(struct net_device *netdev)
14153 +{
14154 + struct et131x_adapter *pAdapter = netdev_priv(netdev);
14155 + PMP_TCB pMpTcb;
14156 + unsigned long lockflags;
14157 +
14158 + DBG_WARNING(et131x_dbginfo, "TX TIMEOUT\n");
14159 +
14160 + /* Just skip this part if the adapter is doing link detection */
14161 + if (MP_TEST_FLAG(pAdapter, fMP_ADAPTER_LINK_DETECTION)) {
14162 + DBG_ERROR(et131x_dbginfo, "Still doing link detection\n");
14163 + return;
14164 + }
14165 +
14166 + /* Any nonrecoverable hardware error?
14167 + * Checks adapter->flags for any failure in phy reading
14168 + */
14169 + if (MP_TEST_FLAG(pAdapter, fMP_ADAPTER_NON_RECOVER_ERROR)) {
14170 + DBG_WARNING(et131x_dbginfo, "Non recoverable error - remove\n");
14171 + return;
14172 + }
14173 +
14174 + /* Hardware failure? */
14175 + if (MP_TEST_FLAG(pAdapter, fMP_ADAPTER_HARDWARE_ERROR)) {
14176 + DBG_WARNING(et131x_dbginfo, "hardware error - reset\n");
14177 + return;
14178 + }
14179 +
14180 + /* Is send stuck? */
14181 + spin_lock_irqsave(&pAdapter->TCBSendQLock, lockflags);
14182 +
14183 + pMpTcb = pAdapter->TxRing.CurrSendHead;
14184 +
14185 + if (pMpTcb != NULL) {
14186 + pMpTcb->Count++;
14187 +
14188 + if (pMpTcb->Count > NIC_SEND_HANG_THRESHOLD) {
14189 +#ifdef CONFIG_ET131X_DEBUG
14190 + TX_STATUS_BLOCK_t txDmaComplete =
14191 + *(pAdapter->TxRing.pTxStatusVa);
14192 + PTX_DESC_ENTRY_t pDesc =
14193 + pAdapter->TxRing.pTxDescRingVa +
14194 + pMpTcb->WrIndex.bits.val;
14195 +#endif
14196 + TX_DESC_ENTRY_t StuckDescriptors[10];
14197 +
14198 + if (pMpTcb->WrIndex.bits.val > 7) {
14199 + memcpy(StuckDescriptors,
14200 + pAdapter->TxRing.pTxDescRingVa +
14201 + pMpTcb->WrIndex.bits.val - 6,
14202 + sizeof(TX_DESC_ENTRY_t) * 10);
14203 + }
14204 +
14205 + spin_unlock_irqrestore(&pAdapter->TCBSendQLock,
14206 + lockflags);
14207 +
14208 + DBG_WARNING(et131x_dbginfo,
14209 + "Send stuck - reset. pMpTcb->WrIndex %x, Flags 0x%08x\n",
14210 + pMpTcb->WrIndex.bits.val,
14211 + pMpTcb->Flags);
14212 +
14213 + DBG_WARNING(et131x_dbginfo,
14214 + "pDesc 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
14215 + pDesc->DataBufferPtrHigh,
14216 + pDesc->DataBufferPtrLow, pDesc->word2.value,
14217 + pDesc->word3.value);
14218 +
14219 + DBG_WARNING(et131x_dbginfo,
14220 + "WbStatus 0x%08x\n", txDmaComplete.value);
14221 +
14222 +#ifdef CONFIG_ET131X_DEBUG
14223 + DumpDeviceBlock(DBG_WARNING_ON, pAdapter, 0);
14224 + DumpDeviceBlock(DBG_WARNING_ON, pAdapter, 1);
14225 + DumpDeviceBlock(DBG_WARNING_ON, pAdapter, 3);
14226 + DumpDeviceBlock(DBG_WARNING_ON, pAdapter, 5);
14227 +#endif
14228 + et131x_close(netdev);
14229 + et131x_open(netdev);
14230 +
14231 + return;
14232 + }
14233 + }
14234 +
14235 + spin_unlock_irqrestore(&pAdapter->TCBSendQLock, lockflags);
14236 +}
14237 +
14238 +/**
14239 + * et131x_change_mtu - The handler called to change the MTU for the device
14240 + * @netdev: device whose MTU is to be changed
14241 + * @new_mtu: the desired MTU
14242 + *
14243 + * Returns 0 on success, errno on failure (as defined in errno.h)
14244 + */
14245 +int et131x_change_mtu(struct net_device *netdev, int new_mtu)
14246 +{
14247 + int result = 0;
14248 + struct et131x_adapter *adapter = netdev_priv(netdev);
14249 +
14250 + DBG_ENTER(et131x_dbginfo);
14251 +
14252 + /* Make sure the requested MTU is valid */
14253 + if (new_mtu == 0 || new_mtu > 9216) {
14254 + DBG_LEAVE(et131x_dbginfo);
14255 + return -EINVAL;
14256 + }
14257 +
14258 + /* Stop the netif queue */
14259 + netif_stop_queue(netdev);
14260 +
14261 + /* Stop the Tx and Rx DMA engines */
14262 + et131x_rx_dma_disable(adapter);
14263 + et131x_tx_dma_disable(adapter);
14264 +
14265 + /* Disable device interrupts */
14266 + et131x_disable_interrupts(adapter);
14267 + et131x_handle_send_interrupt(adapter);
14268 + et131x_handle_recv_interrupt(adapter);
14269 +
14270 + /* Set the new MTU */
14271 + netdev->mtu = new_mtu;
14272 +
14273 + /* Free Rx DMA memory */
14274 + et131x_adapter_memory_free(adapter);
14275 +
14276 + /* Set the config parameter for Jumbo Packet support */
14277 + adapter->RegistryJumboPacket = new_mtu + 14;
14278 + et131x_soft_reset(adapter);
14279 +
14280 + /* Alloc and init Rx DMA memory */
14281 + result = et131x_adapter_memory_alloc(adapter);
14282 + if (result != 0) {
14283 + DBG_WARNING(et131x_dbginfo,
14284 + "Change MTU failed; couldn't re-alloc DMA memory\n");
14285 + return result;
14286 + }
14287 +
14288 + et131x_init_send(adapter);
14289 +
14290 + et131x_setup_hardware_properties(adapter);
14291 + memcpy(netdev->dev_addr, adapter->CurrentAddress, ETH_ALEN);
14292 +
14293 + /* Init the device with the new settings */
14294 + et131x_adapter_setup(adapter);
14295 +
14296 + /* Enable interrupts */
14297 + if (MP_TEST_FLAG(adapter, fMP_ADAPTER_INTERRUPT_IN_USE)) {
14298 + et131x_enable_interrupts(adapter);
14299 + }
14300 +
14301 + /* Restart the Tx and Rx DMA engines */
14302 + et131x_rx_dma_enable(adapter);
14303 + et131x_tx_dma_enable(adapter);
14304 +
14305 + /* Restart the netif queue */
14306 + netif_wake_queue(netdev);
14307 +
14308 + DBG_LEAVE(et131x_dbginfo);
14309 + return result;
14310 +}
14311 +
14312 +/**
14313 + * et131x_set_mac_addr - handler to change the MAC address for the device
14314 + * @netdev: device whose MAC is to be changed
14315 + * @new_mac: the desired MAC address
14316 + *
14317 + * Returns 0 on success, errno on failure (as defined in errno.h)
14318 + *
14319 + * IMPLEMENTED BY : blux http://berndlux.de 22.01.2007 21:14
14320 + */
14321 +int et131x_set_mac_addr(struct net_device *netdev, void *new_mac)
14322 +{
14323 + int result = 0;
14324 + struct et131x_adapter *adapter = netdev_priv(netdev);
14325 + struct sockaddr *address = new_mac;
14326 +
14327 + DBG_ENTER(et131x_dbginfo);
14328 + // begin blux
14329 + // DBG_VERBOSE( et131x_dbginfo, "Function not implemented!!\n" );
14330 +
14331 + if (adapter == NULL) {
14332 + DBG_LEAVE(et131x_dbginfo);
14333 + return -ENODEV;
14334 + }
14335 +
14336 + /* Make sure the requested MAC is valid */
14337 + if (!is_valid_ether_addr(address->sa_data)) {
14338 + DBG_LEAVE(et131x_dbginfo);
14339 + return -EINVAL;
14340 + }
14341 +
14342 + /* Stop the netif queue */
14343 + netif_stop_queue(netdev);
14344 +
14345 + /* Stop the Tx and Rx DMA engines */
14346 + et131x_rx_dma_disable(adapter);
14347 + et131x_tx_dma_disable(adapter);
14348 +
14349 + /* Disable device interrupts */
14350 + et131x_disable_interrupts(adapter);
14351 + et131x_handle_send_interrupt(adapter);
14352 + et131x_handle_recv_interrupt(adapter);
14353 +
14354 + /* Set the new MAC */
14355 + // netdev->set_mac_address = &new_mac;
14356 + // netdev->mtu = new_mtu;
14357 +
14358 + memcpy(netdev->dev_addr, address->sa_data, netdev->addr_len);
14359 +
14360 + printk("%s: Setting MAC address to %02x:%02x:%02x:%02x:%02x:%02x\n",
14361 + netdev->name, netdev->dev_addr[0], netdev->dev_addr[1],
14362 + netdev->dev_addr[2], netdev->dev_addr[3], netdev->dev_addr[4],
14363 + netdev->dev_addr[5]);
14364 +
14365 + /* Free Rx DMA memory */
14366 + et131x_adapter_memory_free(adapter);
14367 +
14368 + /* Set the config parameter for Jumbo Packet support */
14369 + // adapter->RegistryJumboPacket = new_mtu + 14;
14370 + // blux: not needet here, w'll change the MAC
14371 +
14372 + et131x_soft_reset(adapter);
14373 +
14374 + /* Alloc and init Rx DMA memory */
14375 + result = et131x_adapter_memory_alloc(adapter);
14376 + if (result != 0) {
14377 + DBG_WARNING(et131x_dbginfo,
14378 + "Change MAC failed; couldn't re-alloc DMA memory\n");
14379 + return result;
14380 + }
14381 +
14382 + et131x_init_send(adapter);
14383 +
14384 + et131x_setup_hardware_properties(adapter);
14385 + // memcpy( netdev->dev_addr, adapter->CurrentAddress, ETH_ALEN );
14386 + // blux: no, do not override our nice address
14387 +
14388 + /* Init the device with the new settings */
14389 + et131x_adapter_setup(adapter);
14390 +
14391 + /* Enable interrupts */
14392 + if (MP_TEST_FLAG(adapter, fMP_ADAPTER_INTERRUPT_IN_USE)) {
14393 + et131x_enable_interrupts(adapter);
14394 + }
14395 +
14396 + /* Restart the Tx and Rx DMA engines */
14397 + et131x_rx_dma_enable(adapter);
14398 + et131x_tx_dma_enable(adapter);
14399 +
14400 + /* Restart the netif queue */
14401 + netif_wake_queue(netdev);
14402 +
14403 + DBG_LEAVE(et131x_dbginfo);
14404 + return result;
14405 +}
14406 diff --git a/drivers/staging/et131x/et131x_netdev.h b/drivers/staging/et131x/et131x_netdev.h
14407 new file mode 100644
14408 index 0000000..b8acd14
14409 --- /dev/null
14410 +++ b/drivers/staging/et131x/et131x_netdev.h
14411 @@ -0,0 +1,64 @@
14412 +/*
14413 + * Agere Systems Inc.
14414 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
14415 + *
14416 + * Copyright © 2005 Agere Systems Inc.
14417 + * All rights reserved.
14418 + * http://www.agere.com
14419 + *
14420 + *------------------------------------------------------------------------------
14421 + *
14422 + * et131x_netdev.h - Defines, structs, enums, prototypes, etc. related to the
14423 + * driver's net_device support.
14424 + *
14425 + *------------------------------------------------------------------------------
14426 + *
14427 + * SOFTWARE LICENSE
14428 + *
14429 + * This software is provided subject to the following terms and conditions,
14430 + * which you should read carefully before using the software. Using this
14431 + * software indicates your acceptance of these terms and conditions. If you do
14432 + * not agree with these terms and conditions, do not use the software.
14433 + *
14434 + * Copyright © 2005 Agere Systems Inc.
14435 + * All rights reserved.
14436 + *
14437 + * Redistribution and use in source or binary forms, with or without
14438 + * modifications, are permitted provided that the following conditions are met:
14439 + *
14440 + * . Redistributions of source code must retain the above copyright notice, this
14441 + * list of conditions and the following Disclaimer as comments in the code as
14442 + * well as in the documentation and/or other materials provided with the
14443 + * distribution.
14444 + *
14445 + * . Redistributions in binary form must reproduce the above copyright notice,
14446 + * this list of conditions and the following Disclaimer in the documentation
14447 + * and/or other materials provided with the distribution.
14448 + *
14449 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
14450 + * may be used to endorse or promote products derived from this software
14451 + * without specific prior written permission.
14452 + *
14453 + * Disclaimer
14454 + *
14455 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
14456 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
14457 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
14458 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
14459 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
14460 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
14461 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
14462 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
14463 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
14464 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
14465 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
14466 + * DAMAGE.
14467 + *
14468 + */
14469 +
14470 +#ifndef __ET131X_NETDEV_H__
14471 +#define __ET131X_NETDEV_H__
14472 +
14473 +struct net_device *et131x_device_alloc(void);
14474 +
14475 +#endif /* __ET131X_NETDEV_H__ */
14476 diff --git a/drivers/staging/et131x/et131x_version.h b/drivers/staging/et131x/et131x_version.h
14477 new file mode 100644
14478 index 0000000..2ea645e
14479 --- /dev/null
14480 +++ b/drivers/staging/et131x/et131x_version.h
14481 @@ -0,0 +1,81 @@
14482 +/*
14483 + * Agere Systems Inc.
14484 + * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
14485 + *
14486 + * Copyright © 2005 Agere Systems Inc.
14487 + * All rights reserved.
14488 + * http://www.agere.com
14489 + *
14490 + *------------------------------------------------------------------------------
14491 + *
14492 + * et131x_version.h - This file provides system and device version information.
14493 + *
14494 + *------------------------------------------------------------------------------
14495 + *
14496 + * SOFTWARE LICENSE
14497 + *
14498 + * This software is provided subject to the following terms and conditions,
14499 + * which you should read carefully before using the software. Using this
14500 + * software indicates your acceptance of these terms and conditions. If you do
14501 + * not agree with these terms and conditions, do not use the software.
14502 + *
14503 + * Copyright © 2005 Agere Systems Inc.
14504 + * All rights reserved.
14505 + *
14506 + * Redistribution and use in source or binary forms, with or without
14507 + * modifications, are permitted provided that the following conditions are met:
14508 + *
14509 + * . Redistributions of source code must retain the above copyright notice, this
14510 + * list of conditions and the following Disclaimer as comments in the code as
14511 + * well as in the documentation and/or other materials provided with the
14512 + * distribution.
14513 + *
14514 + * . Redistributions in binary form must reproduce the above copyright notice,
14515 + * this list of conditions and the following Disclaimer in the documentation
14516 + * and/or other materials provided with the distribution.
14517 + *
14518 + * . Neither the name of Agere Systems Inc. nor the names of the contributors
14519 + * may be used to endorse or promote products derived from this software
14520 + * without specific prior written permission.
14521 + *
14522 + * Disclaimer
14523 + *
14524 + * THIS SOFTWARE IS PROVIDED \93AS IS\94 AND ANY EXPRESS OR IMPLIED WARRANTIES,
14525 + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
14526 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
14527 + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
14528 + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
14529 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
14530 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
14531 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
14532 + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
14533 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
14534 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
14535 + * DAMAGE.
14536 + *
14537 + */
14538 +
14539 +#ifndef __ET131X_VERSION_H__
14540 +#define __ET131X_VERSION_H__
14541 +
14542 +#define DRIVER_AUTHOR "Victor Soriano (vjsoriano@agere.com)"
14543 +#define DRIVER_LICENSE "Dual BSD/GPL"
14544 +#define DRIVER_DEVICE_STRING "ET1310"
14545 +#define DRIVER_NAME "et131x"
14546 +#define DRIVER_MAJOR_VERSION 1
14547 +#define DRIVER_MINOR_VERSION 2
14548 +#define DRIVER_PATCH_VERSION 3
14549 +#define DRIVER_VERSION_STRING "1.2.3"
14550 +#define DRIVER_VENDOR "Agere Systems, http://www.agere.com"
14551 +#define DRIVER_DESC "10/100/1000 Base-T Ethernet Driver"
14552 +
14553 +#define STRUCT_MODULE "net" /* blux: missed by the kernel */
14554 +
14555 +#define DRIVER_INFO DRIVER_DESC " for the "\
14556 + DRIVER_DEVICE_STRING ", v" \
14557 + DRIVER_VERSION_STRING " by " \
14558 + DRIVER_VENDOR
14559 +
14560 +#define DRIVER_NAME_EXT "et131x.ko"
14561 +
14562 +#endif /* __ET131X_VERSION_H__ */
14563 --
14564 1.6.0.2
14565
Peter's tree of IPFire 2.x