1 From: Seth Heasley <seth.heasley@intel.com>
2 Date: Thu, 28 Aug 2008 22:40:59 +0000 (-0700)
3 Subject: x86/PCI: irq and pci_ids patch for Intel Ibex Peak DeviceIDs
4 X-Git-Tag: v2.6.28-rc1~77^2~28
5 X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Ftorvalds%2Flinux-2.6.git;a=commitdiff_plain;h=37a84ec668ba251ae02cf2c2c664baf6b247ae1f
8 x86/PCI: irq and pci_ids patch for Intel Ibex Peak DeviceIDs
10 This patch updates the Intel Ibex Peak (PCH) LPC and SMBus Controller
13 The LPC Controller ID is set by Firmware within the range of
14 0x3b00-3b1f. This range is included in pci_ids.h using min and max
15 values, and irq.c now has code to handle the range (in lieu of 32
16 additions to a SWITCH statement).
18 The SMBus Controller ID is a fixed-value and will not change.
20 Signed-off-by: Seth Heasley <seth.heasley@intel.com>
21 Acked-by: Jean Delvare <khali@linux-fr.org>
22 Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
23 Acked-by: John Jolly <jjolly@suse.de>
27 arch/x86/pci/irq.c | 11 +++++++++--
28 include/linux/pci_ids.h | 6 +++---
29 2 files changed, 12 insertions(+), 5 deletions(-)
31 --- a/arch/x86/pci/irq.c
32 +++ b/arch/x86/pci/irq.c
33 @@ -591,13 +591,20 @@ static __init int intel_router_probe(str
34 case PCI_DEVICE_ID_INTEL_ICH10_1:
35 case PCI_DEVICE_ID_INTEL_ICH10_2:
36 case PCI_DEVICE_ID_INTEL_ICH10_3:
37 - case PCI_DEVICE_ID_INTEL_PCH_0:
38 - case PCI_DEVICE_ID_INTEL_PCH_1:
40 r->get = pirq_piix_get;
41 r->set = pirq_piix_set;
45 + if ((device >= PCI_DEVICE_ID_INTEL_PCH_LPC_MIN) &&
46 + (device <= PCI_DEVICE_ID_INTEL_PCH_LPC_MAX)) {
47 + r->name = "PIIX/ICH";
48 + r->get = pirq_piix_get;
49 + r->set = pirq_piix_set;
56 --- a/include/linux/pci_ids.h
57 +++ b/include/linux/pci_ids.h
59 #define PCI_DEVICE_ID_INTEL_ICH10_3 0x3a1a
60 #define PCI_DEVICE_ID_INTEL_ICH10_4 0x3a30
61 #define PCI_DEVICE_ID_INTEL_ICH10_5 0x3a60
62 -#define PCI_DEVICE_ID_INTEL_PCH_0 0x3b10
63 -#define PCI_DEVICE_ID_INTEL_PCH_1 0x3b11
64 -#define PCI_DEVICE_ID_INTEL_PCH_2 0x3b30
65 +#define PCI_DEVICE_ID_INTEL_PCH_LPC_MIN 0x3b00
66 +#define PCI_DEVICE_ID_INTEL_PCH_LPC_MAX 0x3b1f
67 +#define PCI_DEVICE_ID_INTEL_PCH_SMBUS 0x3b30
68 #define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f
69 #define PCI_DEVICE_ID_INTEL_5100_16 0x65f0
70 #define PCI_DEVICE_ID_INTEL_5100_21 0x65f5