Add patches to detect Realtek 8102/8103 to r8101 driver.
[people/pmueller/ipfire-2.x.git] / src / r8101 / r8101.c
1 /*
2 * r8101.c: RealTek 8101 ethernet driver.
3 *
4 * This driver based on r8169 from Kernel 2.6.27.39 with SuSE patches
5 * All pciids except for 8101 are removed becaue we want use
6 * original realtek drivers except for 8101 because the
7 * vendors r8101 produce a kernel panic.
8 *
9 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
10 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
11 * Copyright (c) 2009 Arne Fitzenreiter <arne_f@ipfire.org>
12 * Copyright (c) a lot of people too. Please respect their work.
13 *
14 * See MAINTAINERS file for support contact information.
15 */
16
17 #include <linux/module.h>
18 #include <linux/moduleparam.h>
19 #include <linux/pci.h>
20 #include <linux/netdevice.h>
21 #include <linux/etherdevice.h>
22 #include <linux/delay.h>
23 #include <linux/ethtool.h>
24 #include <linux/mii.h>
25 #include <linux/if_vlan.h>
26 #include <linux/crc32.h>
27 #include <linux/in.h>
28 #include <linux/ip.h>
29 #include <linux/tcp.h>
30 #include <linux/init.h>
31 #include <linux/dma-mapping.h>
32
33 #include <asm/system.h>
34 #include <asm/io.h>
35 #include <asm/irq.h>
36
37 #define RTL8101_VERSION "2.3LK-NAPI"
38 #define MODULENAME "r8101"
39 #define PFX MODULENAME ": "
40
41 #ifdef RTL8101_DEBUG
42 #define assert(expr) \
43 if (!(expr)) { \
44 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
45 #expr,__FILE__,__FUNCTION__,__LINE__); \
46 }
47 #define dprintk(fmt, args...) \
48 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
49 #else
50 #define assert(expr) do {} while (0)
51 #define dprintk(fmt, args...) do {} while (0)
52 #endif /* RTL8101_DEBUG */
53
54 #define R8101_MSG_DEFAULT \
55 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
56
57 #define TX_BUFFS_AVAIL(tp) \
58 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
59
60 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
61 static const int max_interrupt_work = 20;
62
63 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
64 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
65 static const int multicast_filter_limit = 32;
66
67 /* MAC address length */
68 #define MAC_ADDR_LEN 6
69
70 #define MAX_READ_REQUEST_SHIFT 12
71 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
72 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
73 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
74 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
75 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
76 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
77
78 #define R8101_REGS_SIZE 256
79 #define R8101_NAPI_WEIGHT 64
80 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
81 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
82 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
83 #define R8101_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
84 #define R8101_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
85
86 #define RTL8101_TX_TIMEOUT (6*HZ)
87 #define RTL8101_PHY_TIMEOUT (10*HZ)
88
89 /* write/read MMIO register */
90 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
91 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
92 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
93 #define RTL_R8(reg) readb (ioaddr + (reg))
94 #define RTL_R16(reg) readw (ioaddr + (reg))
95 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
96
97 enum mac_version {
98 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
99 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
100 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
101 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
102 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
103 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
104 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
105 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
106 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
107 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
108 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
109 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
110 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
111 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
112 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
113 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
114 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
115 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
116 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
117 RTL_GIGA_MAC_VER_20 = 0x14 // 8168C
118 };
119
120 #define _R(NAME,MAC,MASK) \
121 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
122
123 static const struct {
124 const char *name;
125 u8 mac_version;
126 u32 RxConfigMask; /* Clears the bits supported by this chip */
127 } rtl_chip_info[] = {
128 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
129 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
130 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
131 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
132 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
133 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
134 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
135 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
136 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
137 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
138 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
139 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
140 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
141 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
142 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
144 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
145 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
146 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
147 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880) // PCI-E
148 };
149 #undef _R
150
151 enum cfg_version {
152 RTL_CFG_0 = 0x00,
153 RTL_CFG_1,
154 RTL_CFG_2
155 };
156
157 static void rtl_hw_start_8169(struct net_device *);
158 static void rtl_hw_start_8168(struct net_device *);
159 static void rtl_hw_start_8101(struct net_device *);
160
161 static struct pci_device_id rtl8101_pci_tbl[] = {
162 // { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
163 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
164 // { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
165 // { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
166 // { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
167 // { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
168 // { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
169 // { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
170 // { PCI_VENDOR_ID_LINKSYS, 0x1032,
171 // PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
172 { 0x0001, 0x8168,
173 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
174 {0,},
175 };
176
177 MODULE_DEVICE_TABLE(pci, rtl8101_pci_tbl);
178
179 static int rx_copybreak = 200;
180 static int use_dac;
181 static struct {
182 u32 msg_enable;
183 } debug = { -1 };
184
185 enum rtl_registers {
186 MAC0 = 0, /* Ethernet hardware address. */
187 MAC4 = 4,
188 MAR0 = 8, /* Multicast filter. */
189 CounterAddrLow = 0x10,
190 CounterAddrHigh = 0x14,
191 TxDescStartAddrLow = 0x20,
192 TxDescStartAddrHigh = 0x24,
193 TxHDescStartAddrLow = 0x28,
194 TxHDescStartAddrHigh = 0x2c,
195 FLASH = 0x30,
196 ERSR = 0x36,
197 ChipCmd = 0x37,
198 TxPoll = 0x38,
199 IntrMask = 0x3c,
200 IntrStatus = 0x3e,
201 TxConfig = 0x40,
202 RxConfig = 0x44,
203 RxMissed = 0x4c,
204 Cfg9346 = 0x50,
205 Config0 = 0x51,
206 Config1 = 0x52,
207 Config2 = 0x53,
208 Config3 = 0x54,
209 Config4 = 0x55,
210 Config5 = 0x56,
211 MultiIntr = 0x5c,
212 PHYAR = 0x60,
213 PHYstatus = 0x6c,
214 RxMaxSize = 0xda,
215 CPlusCmd = 0xe0,
216 IntrMitigate = 0xe2,
217 RxDescAddrLow = 0xe4,
218 RxDescAddrHigh = 0xe8,
219 EarlyTxThres = 0xec,
220 FuncEvent = 0xf0,
221 FuncEventMask = 0xf4,
222 FuncPresetState = 0xf8,
223 FuncForceEvent = 0xfc,
224 };
225
226 enum rtl8110_registers {
227 TBICSR = 0x64,
228 TBI_ANAR = 0x68,
229 TBI_LPAR = 0x6a,
230 };
231
232 enum rtl8168_8101_registers {
233 CSIDR = 0x64,
234 CSIAR = 0x68,
235 #define CSIAR_FLAG 0x80000000
236 #define CSIAR_WRITE_CMD 0x80000000
237 #define CSIAR_BYTE_ENABLE 0x0f
238 #define CSIAR_BYTE_ENABLE_SHIFT 12
239 #define CSIAR_ADDR_MASK 0x0fff
240
241 EPHYAR = 0x80,
242 #define EPHYAR_FLAG 0x80000000
243 #define EPHYAR_WRITE_CMD 0x80000000
244 #define EPHYAR_REG_MASK 0x1f
245 #define EPHYAR_REG_SHIFT 16
246 #define EPHYAR_DATA_MASK 0xffff
247 DBG_REG = 0xd1,
248 #define FIX_NAK_1 (1 << 4)
249 #define FIX_NAK_2 (1 << 3)
250 };
251
252 enum rtl_register_content {
253 /* InterruptStatusBits */
254 SYSErr = 0x8000,
255 PCSTimeout = 0x4000,
256 SWInt = 0x0100,
257 TxDescUnavail = 0x0080,
258 RxFIFOOver = 0x0040,
259 LinkChg = 0x0020,
260 RxOverflow = 0x0010,
261 TxErr = 0x0008,
262 TxOK = 0x0004,
263 RxErr = 0x0002,
264 RxOK = 0x0001,
265
266 /* RxStatusDesc */
267 RxFOVF = (1 << 23),
268 RxRWT = (1 << 22),
269 RxRES = (1 << 21),
270 RxRUNT = (1 << 20),
271 RxCRC = (1 << 19),
272
273 /* ChipCmdBits */
274 CmdReset = 0x10,
275 CmdRxEnb = 0x08,
276 CmdTxEnb = 0x04,
277 RxBufEmpty = 0x01,
278
279 /* TXPoll register p.5 */
280 HPQ = 0x80, /* Poll cmd on the high prio queue */
281 NPQ = 0x40, /* Poll cmd on the low prio queue */
282 FSWInt = 0x01, /* Forced software interrupt */
283
284 /* Cfg9346Bits */
285 Cfg9346_Lock = 0x00,
286 Cfg9346_Unlock = 0xc0,
287
288 /* rx_mode_bits */
289 AcceptErr = 0x20,
290 AcceptRunt = 0x10,
291 AcceptBroadcast = 0x08,
292 AcceptMulticast = 0x04,
293 AcceptMyPhys = 0x02,
294 AcceptAllPhys = 0x01,
295
296 /* RxConfigBits */
297 RxCfgFIFOShift = 13,
298 RxCfgDMAShift = 8,
299
300 /* TxConfigBits */
301 TxInterFrameGapShift = 24,
302 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
303
304 /* Config1 register p.24 */
305 LEDS1 = (1 << 7),
306 LEDS0 = (1 << 6),
307 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
308 Speed_down = (1 << 4),
309 MEMMAP = (1 << 3),
310 IOMAP = (1 << 2),
311 VPD = (1 << 1),
312 PMEnable = (1 << 0), /* Power Management Enable */
313
314 /* Config2 register p. 25 */
315 PCI_Clock_66MHz = 0x01,
316 PCI_Clock_33MHz = 0x00,
317
318 /* Config3 register p.25 */
319 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
320 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
321 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
322
323 /* Config5 register p.27 */
324 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
325 MWF = (1 << 5), /* Accept Multicast wakeup frame */
326 UWF = (1 << 4), /* Accept Unicast wakeup frame */
327 LanWake = (1 << 1), /* LanWake enable/disable */
328 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
329
330 /* TBICSR p.28 */
331 TBIReset = 0x80000000,
332 TBILoopback = 0x40000000,
333 TBINwEnable = 0x20000000,
334 TBINwRestart = 0x10000000,
335 TBILinkOk = 0x02000000,
336 TBINwComplete = 0x01000000,
337
338 /* CPlusCmd p.31 */
339 EnableBist = (1 << 15), // 8168 8101
340 Mac_dbgo_oe = (1 << 14), // 8168 8101
341 Normal_mode = (1 << 13), // unused
342 Force_half_dup = (1 << 12), // 8168 8101
343 Force_rxflow_en = (1 << 11), // 8168 8101
344 Force_txflow_en = (1 << 10), // 8168 8101
345 Cxpl_dbg_sel = (1 << 9), // 8168 8101
346 ASF = (1 << 8), // 8168 8101
347 PktCntrDisable = (1 << 7), // 8168 8101
348 Mac_dbgo_sel = 0x001c, // 8168
349 RxVlan = (1 << 6),
350 RxChkSum = (1 << 5),
351 PCIDAC = (1 << 4),
352 PCIMulRW = (1 << 3),
353 INTT_0 = 0x0000, // 8168
354 INTT_1 = 0x0001, // 8168
355 INTT_2 = 0x0002, // 8168
356 INTT_3 = 0x0003, // 8168
357
358 /* rtl8101_PHYstatus */
359 TBI_Enable = 0x80,
360 TxFlowCtrl = 0x40,
361 RxFlowCtrl = 0x20,
362 _1000bpsF = 0x10,
363 _100bps = 0x08,
364 _10bps = 0x04,
365 LinkStatus = 0x02,
366 FullDup = 0x01,
367
368 /* _TBICSRBit */
369 TBILinkOK = 0x02000000,
370
371 /* DumpCounterCommand */
372 CounterDump = 0x8,
373 };
374
375 enum desc_status_bit {
376 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
377 RingEnd = (1 << 30), /* End of descriptor ring */
378 FirstFrag = (1 << 29), /* First segment of a packet */
379 LastFrag = (1 << 28), /* Final segment of a packet */
380
381 /* Tx private */
382 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
383 MSSShift = 16, /* MSS value position */
384 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
385 IPCS = (1 << 18), /* Calculate IP checksum */
386 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
387 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
388 TxVlanTag = (1 << 17), /* Add VLAN tag */
389
390 /* Rx private */
391 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
392 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
393
394 #define RxProtoUDP (PID1)
395 #define RxProtoTCP (PID0)
396 #define RxProtoIP (PID1 | PID0)
397 #define RxProtoMask RxProtoIP
398
399 IPFail = (1 << 16), /* IP checksum failed */
400 UDPFail = (1 << 15), /* UDP/IP checksum failed */
401 TCPFail = (1 << 14), /* TCP/IP checksum failed */
402 RxVlanTag = (1 << 16), /* VLAN tag available */
403 };
404
405 #define RsvdMask 0x3fffc000
406
407 struct TxDesc {
408 __le32 opts1;
409 __le32 opts2;
410 __le64 addr;
411 };
412
413 struct RxDesc {
414 __le32 opts1;
415 __le32 opts2;
416 __le64 addr;
417 };
418
419 struct ring_info {
420 struct sk_buff *skb;
421 u32 len;
422 u8 __pad[sizeof(void *) - sizeof(u32)];
423 };
424
425 enum features {
426 RTL_FEATURE_WOL = (1 << 0),
427 RTL_FEATURE_MSI = (1 << 1),
428 RTL_FEATURE_GMII = (1 << 2),
429 };
430
431 struct rtl8101_counters {
432 __le64 tx_packets;
433 __le64 rx_packets;
434 __le64 tx_errors;
435 __le32 rx_errors;
436 __le16 rx_missed;
437 __le16 align_errors;
438 __le32 tx_one_collision;
439 __le32 tx_multi_collision;
440 __le64 rx_unicast;
441 __le64 rx_broadcast;
442 __le32 rx_multicast;
443 __le16 tx_aborted;
444 __le16 tx_underun;
445 };
446
447 struct rtl8101_private {
448 void __iomem *mmio_addr; /* memory map physical address */
449 struct pci_dev *pci_dev; /* Index of PCI device */
450 struct net_device *dev;
451 struct napi_struct napi;
452 spinlock_t lock; /* spin lock flag */
453 u32 msg_enable;
454 int chipset;
455 int mac_version;
456 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
457 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
458 u32 dirty_rx;
459 u32 dirty_tx;
460 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
461 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
462 dma_addr_t TxPhyAddr;
463 dma_addr_t RxPhyAddr;
464 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
465 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
466 unsigned align;
467 unsigned rx_buf_sz;
468 struct timer_list timer;
469 u16 cp_cmd;
470 u16 intr_event;
471 u16 napi_event;
472 u16 intr_mask;
473 int phy_auto_nego_reg;
474 int phy_1000_ctrl_reg;
475 #ifdef CONFIG_R8101_VLAN
476 struct vlan_group *vlgrp;
477 #endif
478 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
479 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
480 void (*phy_reset_enable)(void __iomem *);
481 void (*hw_start)(struct net_device *);
482 unsigned int (*phy_reset_pending)(void __iomem *);
483 unsigned int (*link_ok)(void __iomem *);
484 int pcie_cap;
485 struct delayed_work task;
486 unsigned features;
487
488 struct mii_if_info mii;
489 struct rtl8101_counters counters;
490 };
491
492 MODULE_AUTHOR("Realtek,the Linux r8169 crew & Arne Fitzenreiter <arne_f@ipfire.org>");
493 MODULE_DESCRIPTION("RealTek RTL-8101 Fast Ethernet driver");
494 module_param(rx_copybreak, int, 0);
495 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
496 module_param(use_dac, int, 0);
497 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
498 module_param_named(debug, debug.msg_enable, int, 0);
499 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
500 MODULE_LICENSE("GPL");
501 MODULE_VERSION(RTL8101_VERSION);
502
503 static int rtl8101_open(struct net_device *dev);
504 static int rtl8101_start_xmit(struct sk_buff *skb, struct net_device *dev);
505 static irqreturn_t rtl8101_interrupt(int irq, void *dev_instance);
506 static int rtl8101_init_ring(struct net_device *dev);
507 static void rtl_hw_start(struct net_device *dev);
508 static int rtl8101_close(struct net_device *dev);
509 static void rtl_set_rx_mode(struct net_device *dev);
510 static void rtl8101_tx_timeout(struct net_device *dev);
511 static struct net_device_stats *rtl8101_get_stats(struct net_device *dev);
512 static int rtl8101_rx_interrupt(struct net_device *, struct rtl8101_private *,
513 void __iomem *, u32 budget);
514 static int rtl8101_change_mtu(struct net_device *dev, int new_mtu);
515 static void rtl8101_down(struct net_device *dev);
516 static void rtl8101_rx_clear(struct rtl8101_private *tp);
517 static int rtl8101_poll(struct napi_struct *napi, int budget);
518
519 static const unsigned int rtl8101_rx_config =
520 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
521
522 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
523 {
524 int i;
525
526 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
527
528 for (i = 20; i > 0; i--) {
529 /*
530 * Check if the RTL8101 has completed writing to the specified
531 * MII register.
532 */
533 if (!(RTL_R32(PHYAR) & 0x80000000))
534 break;
535 udelay(25);
536 }
537 }
538
539 static int mdio_read(void __iomem *ioaddr, int reg_addr)
540 {
541 int i, value = -1;
542
543 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
544
545 for (i = 20; i > 0; i--) {
546 /*
547 * Check if the RTL8101 has completed retrieving data from
548 * the specified MII register.
549 */
550 if (RTL_R32(PHYAR) & 0x80000000) {
551 value = RTL_R32(PHYAR) & 0xffff;
552 break;
553 }
554 udelay(25);
555 }
556 return value;
557 }
558
559 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
560 {
561 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
562 }
563
564 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
565 int val)
566 {
567 struct rtl8101_private *tp = netdev_priv(dev);
568 void __iomem *ioaddr = tp->mmio_addr;
569
570 mdio_write(ioaddr, location, val);
571 }
572
573 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
574 {
575 struct rtl8101_private *tp = netdev_priv(dev);
576 void __iomem *ioaddr = tp->mmio_addr;
577
578 return mdio_read(ioaddr, location);
579 }
580
581 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
582 {
583 unsigned int i;
584
585 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
586 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
587
588 for (i = 0; i < 100; i++) {
589 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
590 break;
591 udelay(10);
592 }
593 }
594
595 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
596 {
597 u16 value = 0xffff;
598 unsigned int i;
599
600 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
601
602 for (i = 0; i < 100; i++) {
603 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
604 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
605 break;
606 }
607 udelay(10);
608 }
609
610 return value;
611 }
612
613 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
614 {
615 unsigned int i;
616
617 RTL_W32(CSIDR, value);
618 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
619 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
620
621 for (i = 0; i < 100; i++) {
622 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
623 break;
624 udelay(10);
625 }
626 }
627
628 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
629 {
630 u32 value = ~0x00;
631 unsigned int i;
632
633 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
634 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
635
636 for (i = 0; i < 100; i++) {
637 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
638 value = RTL_R32(CSIDR);
639 break;
640 }
641 udelay(10);
642 }
643
644 return value;
645 }
646
647 static void rtl8101_irq_mask_and_ack(void __iomem *ioaddr)
648 {
649 RTL_W16(IntrMask, 0x0000);
650
651 RTL_W16(IntrStatus, 0xffff);
652 }
653
654 static void rtl8101_asic_down(void __iomem *ioaddr)
655 {
656 RTL_W8(ChipCmd, 0x00);
657 rtl8101_irq_mask_and_ack(ioaddr);
658 RTL_R16(CPlusCmd);
659 }
660
661 static unsigned int rtl8101_tbi_reset_pending(void __iomem *ioaddr)
662 {
663 return RTL_R32(TBICSR) & TBIReset;
664 }
665
666 static unsigned int rtl8101_xmii_reset_pending(void __iomem *ioaddr)
667 {
668 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
669 }
670
671 static unsigned int rtl8101_tbi_link_ok(void __iomem *ioaddr)
672 {
673 return RTL_R32(TBICSR) & TBILinkOk;
674 }
675
676 static unsigned int rtl8101_xmii_link_ok(void __iomem *ioaddr)
677 {
678 return RTL_R8(PHYstatus) & LinkStatus;
679 }
680
681 static void rtl8101_tbi_reset_enable(void __iomem *ioaddr)
682 {
683 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
684 }
685
686 static void rtl8101_xmii_reset_enable(void __iomem *ioaddr)
687 {
688 unsigned int val;
689
690 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
691 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
692 }
693
694 static void rtl8101_check_link_status(struct net_device *dev,
695 struct rtl8101_private *tp,
696 void __iomem *ioaddr)
697 {
698 unsigned long flags;
699
700 spin_lock_irqsave(&tp->lock, flags);
701 if (tp->link_ok(ioaddr)) {
702 netif_carrier_on(dev);
703 if (netif_msg_ifup(tp))
704 printk(KERN_INFO PFX "%s: link up\n", dev->name);
705 } else {
706 if (netif_msg_ifdown(tp))
707 printk(KERN_INFO PFX "%s: link down\n", dev->name);
708 netif_carrier_off(dev);
709 }
710 spin_unlock_irqrestore(&tp->lock, flags);
711 }
712
713 static void rtl8101_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
714 {
715 struct rtl8101_private *tp = netdev_priv(dev);
716 void __iomem *ioaddr = tp->mmio_addr;
717 u8 options;
718
719 wol->wolopts = 0;
720
721 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
722 wol->supported = WAKE_ANY;
723
724 spin_lock_irq(&tp->lock);
725
726 options = RTL_R8(Config1);
727 if (!(options & PMEnable))
728 goto out_unlock;
729
730 options = RTL_R8(Config3);
731 if (options & LinkUp)
732 wol->wolopts |= WAKE_PHY;
733 if (options & MagicPacket)
734 wol->wolopts |= WAKE_MAGIC;
735
736 options = RTL_R8(Config5);
737 if (options & UWF)
738 wol->wolopts |= WAKE_UCAST;
739 if (options & BWF)
740 wol->wolopts |= WAKE_BCAST;
741 if (options & MWF)
742 wol->wolopts |= WAKE_MCAST;
743
744 out_unlock:
745 spin_unlock_irq(&tp->lock);
746 }
747
748 static int rtl8101_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
749 {
750 struct rtl8101_private *tp = netdev_priv(dev);
751 void __iomem *ioaddr = tp->mmio_addr;
752 unsigned int i;
753 static struct {
754 u32 opt;
755 u16 reg;
756 u8 mask;
757 } cfg[] = {
758 { WAKE_ANY, Config1, PMEnable },
759 { WAKE_PHY, Config3, LinkUp },
760 { WAKE_MAGIC, Config3, MagicPacket },
761 { WAKE_UCAST, Config5, UWF },
762 { WAKE_BCAST, Config5, BWF },
763 { WAKE_MCAST, Config5, MWF },
764 { WAKE_ANY, Config5, LanWake }
765 };
766
767 spin_lock_irq(&tp->lock);
768
769 RTL_W8(Cfg9346, Cfg9346_Unlock);
770
771 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
772 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
773 if (wol->wolopts & cfg[i].opt)
774 options |= cfg[i].mask;
775 RTL_W8(cfg[i].reg, options);
776 }
777
778 RTL_W8(Cfg9346, Cfg9346_Lock);
779
780 if (wol->wolopts)
781 tp->features |= RTL_FEATURE_WOL;
782 else
783 tp->features &= ~RTL_FEATURE_WOL;
784
785 spin_unlock_irq(&tp->lock);
786
787 return 0;
788 }
789
790 static void rtl8101_get_drvinfo(struct net_device *dev,
791 struct ethtool_drvinfo *info)
792 {
793 struct rtl8101_private *tp = netdev_priv(dev);
794
795 strcpy(info->driver, MODULENAME);
796 strcpy(info->version, RTL8101_VERSION);
797 strcpy(info->bus_info, pci_name(tp->pci_dev));
798 }
799
800 static int rtl8101_get_regs_len(struct net_device *dev)
801 {
802 return R8101_REGS_SIZE;
803 }
804
805 static int rtl8101_set_speed_tbi(struct net_device *dev,
806 u8 autoneg, u16 speed, u8 duplex)
807 {
808 struct rtl8101_private *tp = netdev_priv(dev);
809 void __iomem *ioaddr = tp->mmio_addr;
810 int ret = 0;
811 u32 reg;
812
813 reg = RTL_R32(TBICSR);
814 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
815 (duplex == DUPLEX_FULL)) {
816 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
817 } else if (autoneg == AUTONEG_ENABLE)
818 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
819 else {
820 if (netif_msg_link(tp)) {
821 printk(KERN_WARNING "%s: "
822 "incorrect speed setting refused in TBI mode\n",
823 dev->name);
824 }
825 ret = -EOPNOTSUPP;
826 }
827
828 return ret;
829 }
830
831 static int rtl8101_set_speed_xmii(struct net_device *dev,
832 u8 autoneg, u16 speed, u8 duplex)
833 {
834 struct rtl8101_private *tp = netdev_priv(dev);
835 void __iomem *ioaddr = tp->mmio_addr;
836 int giga_ctrl, bmcr;
837
838 if (autoneg == AUTONEG_ENABLE) {
839 int auto_nego;
840
841 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
842 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
843 ADVERTISE_100HALF | ADVERTISE_100FULL);
844 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
845
846 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
847 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
848
849 /* The 8100e/8101e/8102e do Fast Ethernet only. */
850 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
851 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
852 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
853 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
854 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
855 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
856 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
857 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
858 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
859 } else if (netif_msg_link(tp)) {
860 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
861 dev->name);
862 }
863
864 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
865
866 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
867 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
868 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
869 /*
870 * Wake up the PHY.
871 * Vendor specific (0x1f) and reserved (0x0e) MII
872 * registers.
873 */
874 mdio_write(ioaddr, 0x1f, 0x0000);
875 mdio_write(ioaddr, 0x0e, 0x0000);
876 }
877
878 tp->phy_auto_nego_reg = auto_nego;
879
880 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
881 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
882 } else {
883 giga_ctrl = 0;
884
885 if (speed == SPEED_10)
886 bmcr = 0;
887 else if (speed == SPEED_100)
888 bmcr = BMCR_SPEED100;
889 else
890 return -EINVAL;
891
892 if (duplex == DUPLEX_FULL)
893 bmcr |= BMCR_FULLDPLX;
894
895 mdio_write(ioaddr, 0x1f, 0x0000);
896 }
897
898 tp->phy_1000_ctrl_reg = giga_ctrl;
899
900 mdio_write(ioaddr, MII_BMCR, bmcr);
901
902 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
903 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
904 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
905 mdio_write(ioaddr, 0x17, 0x2138);
906 mdio_write(ioaddr, 0x0e, 0x0260);
907 } else {
908 mdio_write(ioaddr, 0x17, 0x2108);
909 mdio_write(ioaddr, 0x0e, 0x0000);
910 }
911 }
912
913 return 0;
914 }
915
916 static int rtl8101_set_speed(struct net_device *dev,
917 u8 autoneg, u16 speed, u8 duplex)
918 {
919 struct rtl8101_private *tp = netdev_priv(dev);
920 int ret;
921
922 ret = tp->set_speed(dev, autoneg, speed, duplex);
923
924 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
925 mod_timer(&tp->timer, jiffies + RTL8101_PHY_TIMEOUT);
926
927 return ret;
928 }
929
930 static int rtl8101_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
931 {
932 struct rtl8101_private *tp = netdev_priv(dev);
933 unsigned long flags;
934 int ret;
935
936 spin_lock_irqsave(&tp->lock, flags);
937 ret = rtl8101_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
938 spin_unlock_irqrestore(&tp->lock, flags);
939
940 return ret;
941 }
942
943 static u32 rtl8101_get_rx_csum(struct net_device *dev)
944 {
945 struct rtl8101_private *tp = netdev_priv(dev);
946
947 return tp->cp_cmd & RxChkSum;
948 }
949
950 static int rtl8101_set_rx_csum(struct net_device *dev, u32 data)
951 {
952 struct rtl8101_private *tp = netdev_priv(dev);
953 void __iomem *ioaddr = tp->mmio_addr;
954 unsigned long flags;
955
956 spin_lock_irqsave(&tp->lock, flags);
957
958 if (data)
959 tp->cp_cmd |= RxChkSum;
960 else
961 tp->cp_cmd &= ~RxChkSum;
962
963 RTL_W16(CPlusCmd, tp->cp_cmd);
964 RTL_R16(CPlusCmd);
965
966 spin_unlock_irqrestore(&tp->lock, flags);
967
968 return 0;
969 }
970
971 #ifdef CONFIG_R8101_VLAN
972
973 static inline u32 rtl8101_tx_vlan_tag(struct rtl8101_private *tp,
974 struct sk_buff *skb)
975 {
976 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
977 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
978 }
979
980 static void rtl8101_vlan_rx_register(struct net_device *dev,
981 struct vlan_group *grp)
982 {
983 struct rtl8101_private *tp = netdev_priv(dev);
984 void __iomem *ioaddr = tp->mmio_addr;
985 unsigned long flags;
986
987 spin_lock_irqsave(&tp->lock, flags);
988 tp->vlgrp = grp;
989 if (tp->vlgrp)
990 tp->cp_cmd |= RxVlan;
991 else
992 tp->cp_cmd &= ~RxVlan;
993 RTL_W16(CPlusCmd, tp->cp_cmd);
994 RTL_R16(CPlusCmd);
995 spin_unlock_irqrestore(&tp->lock, flags);
996 }
997
998 static int rtl8101_rx_vlan_skb(struct rtl8101_private *tp, struct RxDesc *desc,
999 struct sk_buff *skb)
1000 {
1001 u32 opts2 = le32_to_cpu(desc->opts2);
1002 struct vlan_group *vlgrp = tp->vlgrp;
1003 int ret;
1004
1005 if (vlgrp && (opts2 & RxVlanTag)) {
1006 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1007 ret = 0;
1008 } else
1009 ret = -1;
1010 desc->opts2 = 0;
1011 return ret;
1012 }
1013
1014 #else /* !CONFIG_R8101_VLAN */
1015
1016 static inline u32 rtl8101_tx_vlan_tag(struct rtl8101_private *tp,
1017 struct sk_buff *skb)
1018 {
1019 return 0;
1020 }
1021
1022 static int rtl8101_rx_vlan_skb(struct rtl8101_private *tp, struct RxDesc *desc,
1023 struct sk_buff *skb)
1024 {
1025 return -1;
1026 }
1027
1028 #endif
1029
1030 static int rtl8101_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1031 {
1032 struct rtl8101_private *tp = netdev_priv(dev);
1033 void __iomem *ioaddr = tp->mmio_addr;
1034 u32 status;
1035
1036 cmd->supported =
1037 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1038 cmd->port = PORT_FIBRE;
1039 cmd->transceiver = XCVR_INTERNAL;
1040
1041 status = RTL_R32(TBICSR);
1042 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1043 cmd->autoneg = !!(status & TBINwEnable);
1044
1045 cmd->speed = SPEED_1000;
1046 cmd->duplex = DUPLEX_FULL; /* Always set */
1047
1048 return 0;
1049 }
1050
1051 static int rtl8101_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1052 {
1053 struct rtl8101_private *tp = netdev_priv(dev);
1054
1055 return mii_ethtool_gset(&tp->mii, cmd);
1056 }
1057
1058 static int rtl8101_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1059 {
1060 struct rtl8101_private *tp = netdev_priv(dev);
1061 unsigned long flags;
1062 int rc;
1063
1064 spin_lock_irqsave(&tp->lock, flags);
1065
1066 rc = tp->get_settings(dev, cmd);
1067
1068 spin_unlock_irqrestore(&tp->lock, flags);
1069 return rc;
1070 }
1071
1072 static void rtl8101_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1073 void *p)
1074 {
1075 struct rtl8101_private *tp = netdev_priv(dev);
1076 unsigned long flags;
1077
1078 if (regs->len > R8101_REGS_SIZE)
1079 regs->len = R8101_REGS_SIZE;
1080
1081 spin_lock_irqsave(&tp->lock, flags);
1082 memcpy_fromio(p, tp->mmio_addr, regs->len);
1083 spin_unlock_irqrestore(&tp->lock, flags);
1084 }
1085
1086 static u32 rtl8101_get_msglevel(struct net_device *dev)
1087 {
1088 struct rtl8101_private *tp = netdev_priv(dev);
1089
1090 return tp->msg_enable;
1091 }
1092
1093 static void rtl8101_set_msglevel(struct net_device *dev, u32 value)
1094 {
1095 struct rtl8101_private *tp = netdev_priv(dev);
1096
1097 tp->msg_enable = value;
1098 }
1099
1100 static const char rtl8101_gstrings[][ETH_GSTRING_LEN] = {
1101 "tx_packets",
1102 "rx_packets",
1103 "tx_errors",
1104 "rx_errors",
1105 "rx_missed",
1106 "align_errors",
1107 "tx_single_collisions",
1108 "tx_multi_collisions",
1109 "unicast",
1110 "broadcast",
1111 "multicast",
1112 "tx_aborted",
1113 "tx_underrun",
1114 };
1115
1116 static int rtl8101_get_sset_count(struct net_device *dev, int sset)
1117 {
1118 switch (sset) {
1119 case ETH_SS_STATS:
1120 return ARRAY_SIZE(rtl8101_gstrings);
1121 default:
1122 return -EOPNOTSUPP;
1123 }
1124 }
1125
1126 static void rtl8101_update_counters(struct net_device *dev)
1127 {
1128 struct rtl8101_private *tp = netdev_priv(dev);
1129 void __iomem *ioaddr = tp->mmio_addr;
1130 struct rtl8101_counters *counters;
1131 dma_addr_t paddr;
1132 u32 cmd;
1133 int wait = 1000;
1134
1135 /*
1136 * Some chips are unable to dump tally counters when the receiver
1137 * is disabled.
1138 */
1139 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1140 return;
1141
1142 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1143 if (!counters)
1144 return;
1145
1146 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1147 cmd = (u64)paddr & DMA_32BIT_MASK;
1148 RTL_W32(CounterAddrLow, cmd);
1149 RTL_W32(CounterAddrLow, cmd | CounterDump);
1150
1151 while (wait--) {
1152 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1153 /* copy updated counters */
1154 memcpy(&tp->counters, counters, sizeof(*counters));
1155 break;
1156 }
1157 udelay(10);
1158 }
1159
1160 RTL_W32(CounterAddrLow, 0);
1161 RTL_W32(CounterAddrHigh, 0);
1162
1163 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1164 }
1165
1166 static void rtl8101_get_ethtool_stats(struct net_device *dev,
1167 struct ethtool_stats *stats, u64 *data)
1168 {
1169 struct rtl8101_private *tp = netdev_priv(dev);
1170
1171 ASSERT_RTNL();
1172
1173 rtl8101_update_counters(dev);
1174
1175 data[0] = le64_to_cpu(tp->counters.tx_packets);
1176 data[1] = le64_to_cpu(tp->counters.rx_packets);
1177 data[2] = le64_to_cpu(tp->counters.tx_errors);
1178 data[3] = le32_to_cpu(tp->counters.rx_errors);
1179 data[4] = le16_to_cpu(tp->counters.rx_missed);
1180 data[5] = le16_to_cpu(tp->counters.align_errors);
1181 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1182 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1183 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1184 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1185 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1186 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1187 data[12] = le16_to_cpu(tp->counters.tx_underun);
1188 }
1189
1190 static void rtl8101_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1191 {
1192 switch(stringset) {
1193 case ETH_SS_STATS:
1194 memcpy(data, *rtl8101_gstrings, sizeof(rtl8101_gstrings));
1195 break;
1196 }
1197 }
1198
1199 static const struct ethtool_ops rtl8101_ethtool_ops = {
1200 .get_drvinfo = rtl8101_get_drvinfo,
1201 .get_regs_len = rtl8101_get_regs_len,
1202 .get_link = ethtool_op_get_link,
1203 .get_settings = rtl8101_get_settings,
1204 .set_settings = rtl8101_set_settings,
1205 .get_msglevel = rtl8101_get_msglevel,
1206 .set_msglevel = rtl8101_set_msglevel,
1207 .get_rx_csum = rtl8101_get_rx_csum,
1208 .set_rx_csum = rtl8101_set_rx_csum,
1209 .set_tx_csum = ethtool_op_set_tx_csum,
1210 .set_sg = ethtool_op_set_sg,
1211 .set_tso = ethtool_op_set_tso,
1212 .get_regs = rtl8101_get_regs,
1213 .get_wol = rtl8101_get_wol,
1214 .set_wol = rtl8101_set_wol,
1215 .get_strings = rtl8101_get_strings,
1216 .get_sset_count = rtl8101_get_sset_count,
1217 .get_ethtool_stats = rtl8101_get_ethtool_stats,
1218 };
1219
1220 static void rtl8101_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1221 int bitnum, int bitval)
1222 {
1223 int val;
1224
1225 val = mdio_read(ioaddr, reg);
1226 val = (bitval == 1) ?
1227 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1228 mdio_write(ioaddr, reg, val & 0xffff);
1229 }
1230
1231 static void rtl8101_get_mac_version(struct rtl8101_private *tp,
1232 void __iomem *ioaddr)
1233 {
1234 /*
1235 * The driver currently handles the 8168Bf and the 8168Be identically
1236 * but they can be identified more specifically through the test below
1237 * if needed:
1238 *
1239 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1240 *
1241 * Same thing for the 8101Eb and the 8101Ec:
1242 *
1243 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1244 */
1245 const struct {
1246 u32 mask;
1247 u32 val;
1248 int mac_version;
1249 } mac_info[] = {
1250 /* 8168B family. */
1251 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1252 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1253 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1254 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 },
1255
1256 /* 8168B family. */
1257 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1258 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1259 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1260 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1261
1262 /* 8101 family. */
1263 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1264 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1265 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1266 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1267 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1268 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1269 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1270 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1271 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1272 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1273 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1274 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1275 /* FIXME: where did these entries come from ? -- FR */
1276 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1277 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1278
1279 /* 8110 family. */
1280 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1281 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1282 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1283 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1284 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1285 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1286
1287 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1288 }, *p = mac_info;
1289 u32 reg;
1290
1291 reg = RTL_R32(TxConfig);
1292 while ((reg & p->mask) != p->val)
1293 p++;
1294 tp->mac_version = p->mac_version;
1295
1296 if (p->mask == 0x00000000) {
1297 struct pci_dev *pdev = tp->pci_dev;
1298
1299 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1300 }
1301 }
1302
1303 static void rtl8101_print_mac_version(struct rtl8101_private *tp)
1304 {
1305 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1306 }
1307
1308 struct phy_reg {
1309 u16 reg;
1310 u16 val;
1311 };
1312
1313 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1314 {
1315 while (len-- > 0) {
1316 mdio_write(ioaddr, regs->reg, regs->val);
1317 regs++;
1318 }
1319 }
1320
1321 static void rtl8101s_hw_phy_config(void __iomem *ioaddr)
1322 {
1323 struct {
1324 u16 regs[5]; /* Beware of bit-sign propagation */
1325 } phy_magic[5] = { {
1326 { 0x0000, //w 4 15 12 0
1327 0x00a1, //w 3 15 0 00a1
1328 0x0008, //w 2 15 0 0008
1329 0x1020, //w 1 15 0 1020
1330 0x1000 } },{ //w 0 15 0 1000
1331 { 0x7000, //w 4 15 12 7
1332 0xff41, //w 3 15 0 ff41
1333 0xde60, //w 2 15 0 de60
1334 0x0140, //w 1 15 0 0140
1335 0x0077 } },{ //w 0 15 0 0077
1336 { 0xa000, //w 4 15 12 a
1337 0xdf01, //w 3 15 0 df01
1338 0xdf20, //w 2 15 0 df20
1339 0xff95, //w 1 15 0 ff95
1340 0xfa00 } },{ //w 0 15 0 fa00
1341 { 0xb000, //w 4 15 12 b
1342 0xff41, //w 3 15 0 ff41
1343 0xde20, //w 2 15 0 de20
1344 0x0140, //w 1 15 0 0140
1345 0x00bb } },{ //w 0 15 0 00bb
1346 { 0xf000, //w 4 15 12 f
1347 0xdf01, //w 3 15 0 df01
1348 0xdf20, //w 2 15 0 df20
1349 0xff95, //w 1 15 0 ff95
1350 0xbf00 } //w 0 15 0 bf00
1351 }
1352 }, *p = phy_magic;
1353 unsigned int i;
1354
1355 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1356 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1357 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1358 rtl8101_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1359
1360 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1361 int val, pos = 4;
1362
1363 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1364 mdio_write(ioaddr, pos, val);
1365 while (--pos >= 0)
1366 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1367 rtl8101_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1368 rtl8101_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1369 }
1370 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1371 }
1372
1373 static void rtl8101sb_hw_phy_config(void __iomem *ioaddr)
1374 {
1375 struct phy_reg phy_reg_init[] = {
1376 { 0x1f, 0x0002 },
1377 { 0x01, 0x90d0 },
1378 { 0x1f, 0x0000 }
1379 };
1380
1381 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1382 }
1383
1384 static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
1385 {
1386 struct phy_reg phy_reg_init[] = {
1387 { 0x1f, 0x0000 },
1388 { 0x1d, 0x0f00 },
1389 { 0x1f, 0x0002 },
1390 { 0x0c, 0x1ec8 },
1391 { 0x1f, 0x0000 }
1392 };
1393
1394 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1395 }
1396
1397 static void rtl8168c_hw_phy_config(void __iomem *ioaddr)
1398 {
1399 struct phy_reg phy_reg_init[] = {
1400 { 0x1f, 0x0001 },
1401 { 0x12, 0x2300 },
1402 { 0x1f, 0x0002 },
1403 { 0x00, 0x88d4 },
1404 { 0x01, 0x82b1 },
1405 { 0x03, 0x7002 },
1406 { 0x08, 0x9e30 },
1407 { 0x09, 0x01f0 },
1408 { 0x0a, 0x5500 },
1409 { 0x0c, 0x00c8 },
1410 { 0x1f, 0x0003 },
1411 { 0x12, 0xc096 },
1412 { 0x16, 0x000a },
1413 { 0x1f, 0x0000 }
1414 };
1415
1416 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1417 }
1418
1419 static void rtl8168cx_hw_phy_config(void __iomem *ioaddr)
1420 {
1421 struct phy_reg phy_reg_init[] = {
1422 { 0x1f, 0x0000 },
1423 { 0x12, 0x2300 },
1424 { 0x1f, 0x0003 },
1425 { 0x16, 0x0f0a },
1426 { 0x1f, 0x0000 },
1427 { 0x1f, 0x0002 },
1428 { 0x0c, 0x7eb8 },
1429 { 0x1f, 0x0000 }
1430 };
1431
1432 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1433 }
1434
1435 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1436 {
1437 struct phy_reg phy_reg_init[] = {
1438 { 0x1f, 0x0003 },
1439 { 0x08, 0x441d },
1440 { 0x01, 0x9100 },
1441 { 0x1f, 0x0000 }
1442 };
1443
1444 mdio_write(ioaddr, 0x1f, 0x0000);
1445 mdio_patch(ioaddr, 0x11, 1 << 12);
1446 mdio_patch(ioaddr, 0x19, 1 << 13);
1447
1448 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1449 }
1450
1451 static void rtl_hw_phy_config(struct net_device *dev)
1452 {
1453 struct rtl8101_private *tp = netdev_priv(dev);
1454 void __iomem *ioaddr = tp->mmio_addr;
1455
1456 rtl8101_print_mac_version(tp);
1457
1458 switch (tp->mac_version) {
1459 case RTL_GIGA_MAC_VER_01:
1460 break;
1461 case RTL_GIGA_MAC_VER_02:
1462 case RTL_GIGA_MAC_VER_03:
1463 rtl8101s_hw_phy_config(ioaddr);
1464 break;
1465 case RTL_GIGA_MAC_VER_04:
1466 rtl8101sb_hw_phy_config(ioaddr);
1467 break;
1468 case RTL_GIGA_MAC_VER_07:
1469 case RTL_GIGA_MAC_VER_08:
1470 case RTL_GIGA_MAC_VER_09:
1471 rtl8102e_hw_phy_config(ioaddr);
1472 break;
1473 case RTL_GIGA_MAC_VER_18:
1474 rtl8168cp_hw_phy_config(ioaddr);
1475 break;
1476 case RTL_GIGA_MAC_VER_19:
1477 rtl8168c_hw_phy_config(ioaddr);
1478 break;
1479 case RTL_GIGA_MAC_VER_20:
1480 rtl8168cx_hw_phy_config(ioaddr);
1481 break;
1482 default:
1483 break;
1484 }
1485 }
1486
1487 static void rtl8101_phy_timer(unsigned long __opaque)
1488 {
1489 struct net_device *dev = (struct net_device *)__opaque;
1490 struct rtl8101_private *tp = netdev_priv(dev);
1491 struct timer_list *timer = &tp->timer;
1492 void __iomem *ioaddr = tp->mmio_addr;
1493 unsigned long timeout = RTL8101_PHY_TIMEOUT;
1494
1495 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1496
1497 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1498 return;
1499
1500 spin_lock_irq(&tp->lock);
1501
1502 if (tp->phy_reset_pending(ioaddr)) {
1503 /*
1504 * A busy loop could burn quite a few cycles on nowadays CPU.
1505 * Let's delay the execution of the timer for a few ticks.
1506 */
1507 timeout = HZ/10;
1508 goto out_mod_timer;
1509 }
1510
1511 if (tp->link_ok(ioaddr))
1512 goto out_unlock;
1513
1514 if (netif_msg_link(tp))
1515 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1516
1517 tp->phy_reset_enable(ioaddr);
1518
1519 out_mod_timer:
1520 mod_timer(timer, jiffies + timeout);
1521 out_unlock:
1522 spin_unlock_irq(&tp->lock);
1523 }
1524
1525 static inline void rtl8101_delete_timer(struct net_device *dev)
1526 {
1527 struct rtl8101_private *tp = netdev_priv(dev);
1528 struct timer_list *timer = &tp->timer;
1529
1530 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1531 return;
1532
1533 del_timer_sync(timer);
1534 }
1535
1536 static inline void rtl8101_request_timer(struct net_device *dev)
1537 {
1538 struct rtl8101_private *tp = netdev_priv(dev);
1539 struct timer_list *timer = &tp->timer;
1540
1541 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1542 return;
1543
1544 mod_timer(timer, jiffies + RTL8101_PHY_TIMEOUT);
1545 }
1546
1547 #ifdef CONFIG_NET_POLL_CONTROLLER
1548 /*
1549 * Polling 'interrupt' - used by things like netconsole to send skbs
1550 * without having to re-enable interrupts. It's not called while
1551 * the interrupt routine is executing.
1552 */
1553 static void rtl8101_netpoll(struct net_device *dev)
1554 {
1555 struct rtl8101_private *tp = netdev_priv(dev);
1556 struct pci_dev *pdev = tp->pci_dev;
1557
1558 disable_irq(pdev->irq);
1559 rtl8101_interrupt(pdev->irq, dev);
1560 enable_irq(pdev->irq);
1561 }
1562 #endif
1563
1564 static void rtl8101_release_board(struct pci_dev *pdev, struct net_device *dev,
1565 void __iomem *ioaddr)
1566 {
1567 iounmap(ioaddr);
1568 pci_release_regions(pdev);
1569 pci_disable_device(pdev);
1570 free_netdev(dev);
1571 }
1572
1573 static void rtl8101_phy_reset(struct net_device *dev,
1574 struct rtl8101_private *tp)
1575 {
1576 void __iomem *ioaddr = tp->mmio_addr;
1577 unsigned int i;
1578
1579 tp->phy_reset_enable(ioaddr);
1580 for (i = 0; i < 100; i++) {
1581 if (!tp->phy_reset_pending(ioaddr))
1582 return;
1583 msleep(1);
1584 }
1585 if (netif_msg_link(tp))
1586 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1587 }
1588
1589 static void rtl8101_init_phy(struct net_device *dev, struct rtl8101_private *tp)
1590 {
1591 void __iomem *ioaddr = tp->mmio_addr;
1592
1593 rtl_hw_phy_config(dev);
1594
1595 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1596 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1597 RTL_W8(0x82, 0x01);
1598 }
1599
1600 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1601
1602 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1603 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1604
1605 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1606 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1607 RTL_W8(0x82, 0x01);
1608 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1609 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1610 }
1611
1612 rtl8101_phy_reset(dev, tp);
1613
1614 /*
1615 * rtl8101_set_speed_xmii takes good care of the Fast Ethernet
1616 * only 8101. Don't panic.
1617 */
1618 rtl8101_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1619
1620 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1621 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1622 }
1623
1624 static void rtl_rar_set(struct rtl8101_private *tp, u8 *addr)
1625 {
1626 void __iomem *ioaddr = tp->mmio_addr;
1627 u32 high;
1628 u32 low;
1629
1630 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1631 high = addr[4] | (addr[5] << 8);
1632
1633 spin_lock_irq(&tp->lock);
1634
1635 RTL_W8(Cfg9346, Cfg9346_Unlock);
1636 RTL_W32(MAC0, low);
1637 RTL_W32(MAC4, high);
1638 RTL_W8(Cfg9346, Cfg9346_Lock);
1639
1640 spin_unlock_irq(&tp->lock);
1641 }
1642
1643 static int rtl_set_mac_address(struct net_device *dev, void *p)
1644 {
1645 struct rtl8101_private *tp = netdev_priv(dev);
1646 struct sockaddr *addr = p;
1647
1648 if (!is_valid_ether_addr(addr->sa_data))
1649 return -EADDRNOTAVAIL;
1650
1651 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1652
1653 rtl_rar_set(tp, dev->dev_addr);
1654
1655 return 0;
1656 }
1657
1658 static int rtl8101_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1659 {
1660 struct rtl8101_private *tp = netdev_priv(dev);
1661 struct mii_ioctl_data *data = if_mii(ifr);
1662
1663 if (!netif_running(dev))
1664 return -ENODEV;
1665
1666 switch (cmd) {
1667 case SIOCGMIIPHY:
1668 data->phy_id = 32; /* Internal PHY */
1669 return 0;
1670
1671 case SIOCGMIIREG:
1672 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1673 return 0;
1674
1675 case SIOCSMIIREG:
1676 if (!capable(CAP_NET_ADMIN))
1677 return -EPERM;
1678 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1679 return 0;
1680 }
1681 return -EOPNOTSUPP;
1682 }
1683
1684 static const struct rtl_cfg_info {
1685 void (*hw_start)(struct net_device *);
1686 unsigned int region;
1687 unsigned int align;
1688 u16 intr_event;
1689 u16 napi_event;
1690 unsigned features;
1691 } rtl_cfg_infos [] = {
1692 [RTL_CFG_0] = {
1693 .hw_start = rtl_hw_start_8169,
1694 .region = 1,
1695 .align = 0,
1696 .intr_event = SYSErr | LinkChg | RxOverflow |
1697 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1698 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1699 .features = RTL_FEATURE_GMII
1700 },
1701 [RTL_CFG_1] = {
1702 .hw_start = rtl_hw_start_8168,
1703 .region = 2,
1704 .align = 8,
1705 .intr_event = SYSErr | LinkChg | RxOverflow |
1706 TxErr | TxOK | RxOK | RxErr,
1707 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
1708 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI
1709 },
1710 [RTL_CFG_2] = {
1711 .hw_start = rtl_hw_start_8101,
1712 .region = 2,
1713 .align = 8,
1714 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1715 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1716 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1717 .features = RTL_FEATURE_MSI
1718 }
1719 };
1720
1721 /* Cfg9346_Unlock assumed. */
1722 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1723 const struct rtl_cfg_info *cfg)
1724 {
1725 unsigned msi = 0;
1726 u8 cfg2;
1727
1728 cfg2 = RTL_R8(Config2) & ~MSIEnable;
1729 if (cfg->features & RTL_FEATURE_MSI) {
1730 if (pci_enable_msi(pdev)) {
1731 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1732 } else {
1733 cfg2 |= MSIEnable;
1734 msi = RTL_FEATURE_MSI;
1735 }
1736 }
1737 RTL_W8(Config2, cfg2);
1738 return msi;
1739 }
1740
1741 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8101_private *tp)
1742 {
1743 if (tp->features & RTL_FEATURE_MSI) {
1744 pci_disable_msi(pdev);
1745 tp->features &= ~RTL_FEATURE_MSI;
1746 }
1747 }
1748
1749 static int __devinit
1750 rtl8101_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1751 {
1752 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1753 const unsigned int region = cfg->region;
1754 struct rtl8101_private *tp;
1755 struct mii_if_info *mii;
1756 struct net_device *dev;
1757 void __iomem *ioaddr;
1758 unsigned int i;
1759 int rc;
1760
1761 if (netif_msg_drv(&debug)) {
1762 printk(KERN_INFO "%s Fast Ethernet driver %s loaded\n",
1763 MODULENAME, RTL8101_VERSION);
1764 }
1765
1766 dev = alloc_etherdev(sizeof (*tp));
1767 if (!dev) {
1768 if (netif_msg_drv(&debug))
1769 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1770 rc = -ENOMEM;
1771 goto out;
1772 }
1773
1774 SET_NETDEV_DEV(dev, &pdev->dev);
1775 tp = netdev_priv(dev);
1776 tp->dev = dev;
1777 tp->pci_dev = pdev;
1778 tp->msg_enable = netif_msg_init(debug.msg_enable, R8101_MSG_DEFAULT);
1779
1780 mii = &tp->mii;
1781 mii->dev = dev;
1782 mii->mdio_read = rtl_mdio_read;
1783 mii->mdio_write = rtl_mdio_write;
1784 mii->phy_id_mask = 0x1f;
1785 mii->reg_num_mask = 0x1f;
1786 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
1787
1788 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1789 rc = pci_enable_device(pdev);
1790 if (rc < 0) {
1791 if (netif_msg_probe(tp))
1792 dev_err(&pdev->dev, "enable failure\n");
1793 goto err_out_free_dev_1;
1794 }
1795
1796 rc = pci_set_mwi(pdev);
1797 if (rc < 0)
1798 goto err_out_disable_2;
1799
1800 /* make sure PCI base addr 1 is MMIO */
1801 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1802 if (netif_msg_probe(tp)) {
1803 dev_err(&pdev->dev,
1804 "region #%d not an MMIO resource, aborting\n",
1805 region);
1806 }
1807 rc = -ENODEV;
1808 goto err_out_mwi_3;
1809 }
1810
1811 /* check for weird/broken PCI region reporting */
1812 if (pci_resource_len(pdev, region) < R8101_REGS_SIZE) {
1813 if (netif_msg_probe(tp)) {
1814 dev_err(&pdev->dev,
1815 "Invalid PCI region size(s), aborting\n");
1816 }
1817 rc = -ENODEV;
1818 goto err_out_mwi_3;
1819 }
1820
1821 rc = pci_request_regions(pdev, MODULENAME);
1822 if (rc < 0) {
1823 if (netif_msg_probe(tp))
1824 dev_err(&pdev->dev, "could not request regions.\n");
1825 goto err_out_mwi_3;
1826 }
1827
1828 tp->cp_cmd = PCIMulRW | RxChkSum;
1829
1830 if ((sizeof(dma_addr_t) > 4) &&
1831 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1832 tp->cp_cmd |= PCIDAC;
1833 dev->features |= NETIF_F_HIGHDMA;
1834 } else {
1835 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1836 if (rc < 0) {
1837 if (netif_msg_probe(tp)) {
1838 dev_err(&pdev->dev,
1839 "DMA configuration failed.\n");
1840 }
1841 goto err_out_free_res_4;
1842 }
1843 }
1844
1845 pci_set_master(pdev);
1846
1847 /* ioremap MMIO region */
1848 ioaddr = ioremap(pci_resource_start(pdev, region), R8101_REGS_SIZE);
1849 if (!ioaddr) {
1850 if (netif_msg_probe(tp))
1851 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1852 rc = -EIO;
1853 goto err_out_free_res_4;
1854 }
1855
1856 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1857 if (!tp->pcie_cap && netif_msg_probe(tp))
1858 dev_info(&pdev->dev, "no PCI Express capability\n");
1859
1860 RTL_W16(IntrMask, 0x0000);
1861
1862 /* Soft reset the chip. */
1863 RTL_W8(ChipCmd, CmdReset);
1864
1865 /* Check that the chip has finished the reset. */
1866 for (i = 0; i < 100; i++) {
1867 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1868 break;
1869 msleep_interruptible(1);
1870 }
1871
1872 RTL_W16(IntrStatus, 0xffff);
1873
1874 /* Identify chip attached to board */
1875 rtl8101_get_mac_version(tp, ioaddr);
1876
1877 rtl8101_print_mac_version(tp);
1878
1879 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1880 if (tp->mac_version == rtl_chip_info[i].mac_version)
1881 break;
1882 }
1883 if (i == ARRAY_SIZE(rtl_chip_info)) {
1884 /* Unknown chip: assume array element #0, original RTL-8101 */
1885 if (netif_msg_probe(tp)) {
1886 dev_printk(KERN_DEBUG, &pdev->dev,
1887 "unknown chip version, assuming %s\n",
1888 rtl_chip_info[0].name);
1889 }
1890 i = 0;
1891 }
1892 tp->chipset = i;
1893
1894 RTL_W8(Cfg9346, Cfg9346_Unlock);
1895 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1896 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1897 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
1898 RTL_W8(Cfg9346, Cfg9346_Lock);
1899
1900 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
1901 (RTL_R8(PHYstatus) & TBI_Enable)) {
1902 tp->set_speed = rtl8101_set_speed_tbi;
1903 tp->get_settings = rtl8101_gset_tbi;
1904 tp->phy_reset_enable = rtl8101_tbi_reset_enable;
1905 tp->phy_reset_pending = rtl8101_tbi_reset_pending;
1906 tp->link_ok = rtl8101_tbi_link_ok;
1907
1908 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1909 } else {
1910 tp->set_speed = rtl8101_set_speed_xmii;
1911 tp->get_settings = rtl8101_gset_xmii;
1912 tp->phy_reset_enable = rtl8101_xmii_reset_enable;
1913 tp->phy_reset_pending = rtl8101_xmii_reset_pending;
1914 tp->link_ok = rtl8101_xmii_link_ok;
1915
1916 dev->do_ioctl = rtl8101_ioctl;
1917 }
1918
1919 /* Get MAC address. FIXME: read EEPROM */
1920 for (i = 0; i < MAC_ADDR_LEN; i++)
1921 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1922 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1923
1924 dev->open = rtl8101_open;
1925 dev->hard_start_xmit = rtl8101_start_xmit;
1926 dev->get_stats = rtl8101_get_stats;
1927 SET_ETHTOOL_OPS(dev, &rtl8101_ethtool_ops);
1928 dev->stop = rtl8101_close;
1929 dev->tx_timeout = rtl8101_tx_timeout;
1930 dev->set_multicast_list = rtl_set_rx_mode;
1931 dev->watchdog_timeo = RTL8101_TX_TIMEOUT;
1932 dev->irq = pdev->irq;
1933 dev->base_addr = (unsigned long) ioaddr;
1934 dev->change_mtu = rtl8101_change_mtu;
1935 dev->set_mac_address = rtl_set_mac_address;
1936
1937 netif_napi_add(dev, &tp->napi, rtl8101_poll, R8101_NAPI_WEIGHT);
1938
1939 #ifdef CONFIG_R8101_VLAN
1940 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1941 dev->vlan_rx_register = rtl8101_vlan_rx_register;
1942 #endif
1943
1944 #ifdef CONFIG_NET_POLL_CONTROLLER
1945 dev->poll_controller = rtl8101_netpoll;
1946 #endif
1947
1948 tp->intr_mask = 0xffff;
1949 tp->mmio_addr = ioaddr;
1950 tp->align = cfg->align;
1951 tp->hw_start = cfg->hw_start;
1952 tp->intr_event = cfg->intr_event;
1953 tp->napi_event = cfg->napi_event;
1954
1955 init_timer(&tp->timer);
1956 tp->timer.data = (unsigned long) dev;
1957 tp->timer.function = rtl8101_phy_timer;
1958
1959 spin_lock_init(&tp->lock);
1960
1961 rc = register_netdev(dev);
1962 if (rc < 0)
1963 goto err_out_msi_5;
1964
1965 pci_set_drvdata(pdev, dev);
1966
1967 if (netif_msg_probe(tp)) {
1968 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1969
1970 printk(KERN_INFO "%s: %s at 0x%lx, "
1971 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1972 "XID %08x IRQ %d\n",
1973 dev->name,
1974 rtl_chip_info[tp->chipset].name,
1975 dev->base_addr,
1976 dev->dev_addr[0], dev->dev_addr[1],
1977 dev->dev_addr[2], dev->dev_addr[3],
1978 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
1979 }
1980
1981 rtl8101_init_phy(dev, tp);
1982
1983 out:
1984 return rc;
1985
1986 err_out_msi_5:
1987 rtl_disable_msi(pdev, tp);
1988 iounmap(ioaddr);
1989 err_out_free_res_4:
1990 pci_release_regions(pdev);
1991 err_out_mwi_3:
1992 pci_clear_mwi(pdev);
1993 err_out_disable_2:
1994 pci_disable_device(pdev);
1995 err_out_free_dev_1:
1996 free_netdev(dev);
1997 goto out;
1998 }
1999
2000 static void __devexit rtl8101_remove_one(struct pci_dev *pdev)
2001 {
2002 struct net_device *dev = pci_get_drvdata(pdev);
2003 struct rtl8101_private *tp = netdev_priv(dev);
2004
2005 flush_scheduled_work();
2006
2007 unregister_netdev(dev);
2008 rtl_disable_msi(pdev, tp);
2009 rtl8101_release_board(pdev, dev, tp->mmio_addr);
2010 pci_set_drvdata(pdev, NULL);
2011 }
2012
2013 static void rtl8101_set_rxbufsize(struct rtl8101_private *tp,
2014 struct net_device *dev)
2015 {
2016 unsigned int mtu = dev->mtu;
2017
2018 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2019 }
2020
2021 static int rtl8101_open(struct net_device *dev)
2022 {
2023 struct rtl8101_private *tp = netdev_priv(dev);
2024 struct pci_dev *pdev = tp->pci_dev;
2025 int retval = -ENOMEM;
2026
2027
2028 rtl8101_set_rxbufsize(tp, dev);
2029
2030 /*
2031 * Rx and Tx desscriptors needs 256 bytes alignment.
2032 * pci_alloc_consistent provides more.
2033 */
2034 tp->TxDescArray = pci_alloc_consistent(pdev, R8101_TX_RING_BYTES,
2035 &tp->TxPhyAddr);
2036 if (!tp->TxDescArray)
2037 goto out;
2038
2039 tp->RxDescArray = pci_alloc_consistent(pdev, R8101_RX_RING_BYTES,
2040 &tp->RxPhyAddr);
2041 if (!tp->RxDescArray)
2042 goto err_free_tx_0;
2043
2044 retval = rtl8101_init_ring(dev);
2045 if (retval < 0)
2046 goto err_free_rx_1;
2047
2048 INIT_DELAYED_WORK(&tp->task, NULL);
2049
2050 smp_mb();
2051
2052 retval = request_irq(dev->irq, rtl8101_interrupt,
2053 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
2054 dev->name, dev);
2055 if (retval < 0)
2056 goto err_release_ring_2;
2057
2058 napi_enable(&tp->napi);
2059
2060 rtl_hw_start(dev);
2061
2062 rtl8101_request_timer(dev);
2063
2064 rtl8101_check_link_status(dev, tp, tp->mmio_addr);
2065 out:
2066 return retval;
2067
2068 err_release_ring_2:
2069 rtl8101_rx_clear(tp);
2070 err_free_rx_1:
2071 pci_free_consistent(pdev, R8101_RX_RING_BYTES, tp->RxDescArray,
2072 tp->RxPhyAddr);
2073 err_free_tx_0:
2074 pci_free_consistent(pdev, R8101_TX_RING_BYTES, tp->TxDescArray,
2075 tp->TxPhyAddr);
2076 goto out;
2077 }
2078
2079 static void rtl8101_hw_reset(void __iomem *ioaddr)
2080 {
2081 /* Disable interrupts */
2082 rtl8101_irq_mask_and_ack(ioaddr);
2083
2084 /* Reset the chipset */
2085 RTL_W8(ChipCmd, CmdReset);
2086
2087 /* PCI commit */
2088 RTL_R8(ChipCmd);
2089 }
2090
2091 static void rtl_set_rx_tx_config_registers(struct rtl8101_private *tp)
2092 {
2093 void __iomem *ioaddr = tp->mmio_addr;
2094 u32 cfg = rtl8101_rx_config;
2095
2096 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2097 RTL_W32(RxConfig, cfg);
2098
2099 /* Set DMA burst size and Interframe Gap Time */
2100 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2101 (InterFrameGap << TxInterFrameGapShift));
2102 }
2103
2104 static void rtl_hw_start(struct net_device *dev)
2105 {
2106 struct rtl8101_private *tp = netdev_priv(dev);
2107 void __iomem *ioaddr = tp->mmio_addr;
2108 unsigned int i;
2109
2110 /* Soft reset the chip. */
2111 RTL_W8(ChipCmd, CmdReset);
2112
2113 /* Check that the chip has finished the reset. */
2114 for (i = 0; i < 100; i++) {
2115 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2116 break;
2117 msleep_interruptible(1);
2118 }
2119
2120 tp->hw_start(dev);
2121
2122 netif_start_queue(dev);
2123 }
2124
2125
2126 static void rtl_set_rx_tx_desc_registers(struct rtl8101_private *tp,
2127 void __iomem *ioaddr)
2128 {
2129 /*
2130 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2131 * register to be written before TxDescAddrLow to work.
2132 * Switching from MMIO to I/O access fixes the issue as well.
2133 */
2134 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2135 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
2136 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2137 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
2138 }
2139
2140 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2141 {
2142 u16 cmd;
2143
2144 cmd = RTL_R16(CPlusCmd);
2145 RTL_W16(CPlusCmd, cmd);
2146 return cmd;
2147 }
2148
2149 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
2150 {
2151 /* Low hurts. Let's disable the filtering. */
2152 RTL_W16(RxMaxSize, rx_buf_sz);
2153 }
2154
2155 static void rtl8101_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2156 {
2157 struct {
2158 u32 mac_version;
2159 u32 clk;
2160 u32 val;
2161 } cfg2_info [] = {
2162 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2163 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2164 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2165 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2166 }, *p = cfg2_info;
2167 unsigned int i;
2168 u32 clk;
2169
2170 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2171 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
2172 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2173 RTL_W32(0x7c, p->val);
2174 break;
2175 }
2176 }
2177 }
2178
2179 static void rtl_hw_start_8169(struct net_device *dev)
2180 {
2181 struct rtl8101_private *tp = netdev_priv(dev);
2182 void __iomem *ioaddr = tp->mmio_addr;
2183 struct pci_dev *pdev = tp->pci_dev;
2184
2185 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2186 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2187 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2188 }
2189
2190 RTL_W8(Cfg9346, Cfg9346_Unlock);
2191 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2192 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2193 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2194 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2195 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2196
2197 RTL_W8(EarlyTxThres, EarlyTxThld);
2198
2199 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
2200
2201 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2202 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2203 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2204 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2205 rtl_set_rx_tx_config_registers(tp);
2206
2207 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2208
2209 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2210 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2211 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2212 "Bit-3 and bit-14 MUST be 1\n");
2213 tp->cp_cmd |= (1 << 14);
2214 }
2215
2216 RTL_W16(CPlusCmd, tp->cp_cmd);
2217
2218 rtl8101_set_magic_reg(ioaddr, tp->mac_version);
2219
2220 /*
2221 * Undocumented corner. Supposedly:
2222 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2223 */
2224 RTL_W16(IntrMitigate, 0x0000);
2225
2226 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2227
2228 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2229 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2230 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2231 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2232 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2233 rtl_set_rx_tx_config_registers(tp);
2234 }
2235
2236 RTL_W8(Cfg9346, Cfg9346_Lock);
2237
2238 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2239 RTL_R8(IntrMask);
2240
2241 RTL_W32(RxMissed, 0);
2242
2243 rtl_set_rx_mode(dev);
2244
2245 /* no early-rx interrupts */
2246 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2247
2248 /* Enable all known interrupts by setting the interrupt mask. */
2249 RTL_W16(IntrMask, tp->intr_event);
2250 }
2251
2252 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
2253 {
2254 struct net_device *dev = pci_get_drvdata(pdev);
2255 struct rtl8101_private *tp = netdev_priv(dev);
2256 int cap = tp->pcie_cap;
2257
2258 if (cap) {
2259 u16 ctl;
2260
2261 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2262 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2263 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2264 }
2265 }
2266
2267 static void rtl_csi_access_enable(void __iomem *ioaddr)
2268 {
2269 u32 csi;
2270
2271 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2272 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2273 }
2274
2275 struct ephy_info {
2276 unsigned int offset;
2277 u16 mask;
2278 u16 bits;
2279 };
2280
2281 static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2282 {
2283 u16 w;
2284
2285 while (len-- > 0) {
2286 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2287 rtl_ephy_write(ioaddr, e->offset, w);
2288 e++;
2289 }
2290 }
2291
2292 static void rtl_hw_start_8168(struct net_device *dev)
2293 {
2294 struct rtl8101_private *tp = netdev_priv(dev);
2295 void __iomem *ioaddr = tp->mmio_addr;
2296 struct pci_dev *pdev = tp->pci_dev;
2297
2298 RTL_W8(Cfg9346, Cfg9346_Unlock);
2299
2300 RTL_W8(EarlyTxThres, EarlyTxThld);
2301
2302 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
2303
2304 rtl_set_rx_tx_config_registers(tp);
2305
2306 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2307
2308 RTL_W16(CPlusCmd, tp->cp_cmd);
2309
2310 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2311
2312 RTL_W16(IntrMitigate, 0x5151);
2313
2314 /* Work around for RxFIFO overflow. */
2315 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2316 tp->intr_event |= RxFIFOOver | PCSTimeout;
2317 tp->intr_event &= ~RxOverflow;
2318 }
2319
2320 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2321
2322 RTL_W8(Cfg9346, Cfg9346_Lock);
2323
2324 RTL_R8(IntrMask);
2325
2326 rtl_set_rx_mode(dev);
2327
2328 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2329
2330 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2331
2332 RTL_W16(IntrMask, tp->intr_event);
2333 }
2334
2335 #define R810X_CPCMD_QUIRK_MASK (\
2336 EnableBist | \
2337 Mac_dbgo_oe | \
2338 Force_half_dup | \
2339 Force_half_dup | \
2340 Force_txflow_en | \
2341 Cxpl_dbg_sel | \
2342 ASF | \
2343 PktCntrDisable | \
2344 PCIDAC | \
2345 PCIMulRW)
2346
2347 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2348 {
2349 static struct ephy_info e_info_8102e_1[] = {
2350 { 0x01, 0, 0x6e65 },
2351 { 0x02, 0, 0x091f },
2352 { 0x03, 0, 0xc2f9 },
2353 { 0x06, 0, 0xafb5 },
2354 { 0x07, 0, 0x0e00 },
2355 { 0x19, 0, 0xec80 },
2356 { 0x01, 0, 0x2e65 },
2357 { 0x01, 0, 0x6e65 }
2358 };
2359 u8 cfg1;
2360
2361 rtl_csi_access_enable(ioaddr);
2362
2363 RTL_W8(DBG_REG, FIX_NAK_1);
2364
2365 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2366
2367 RTL_W8(Config1,
2368 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2369 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2370
2371 cfg1 = RTL_R8(Config1);
2372 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2373 RTL_W8(Config1, cfg1 & ~LEDS0);
2374
2375 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2376
2377 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2378 }
2379
2380 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2381 {
2382 rtl_csi_access_enable(ioaddr);
2383
2384 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2385
2386 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2387 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2388
2389 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2390 }
2391
2392 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2393 {
2394 rtl_hw_start_8102e_2(ioaddr, pdev);
2395
2396 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2397 }
2398
2399 static void rtl_hw_start_8101(struct net_device *dev)
2400 {
2401 struct rtl8101_private *tp = netdev_priv(dev);
2402 void __iomem *ioaddr = tp->mmio_addr;
2403 struct pci_dev *pdev = tp->pci_dev;
2404
2405 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2406 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2407 int cap = tp->pcie_cap;
2408
2409 if (cap) {
2410 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2411 PCI_EXP_DEVCTL_NOSNOOP_EN);
2412 }
2413 }
2414
2415 switch (tp->mac_version) {
2416 case RTL_GIGA_MAC_VER_07:
2417 rtl_hw_start_8102e_1(ioaddr, pdev);
2418 break;
2419
2420 case RTL_GIGA_MAC_VER_08:
2421 rtl_hw_start_8102e_3(ioaddr, pdev);
2422 break;
2423
2424 case RTL_GIGA_MAC_VER_09:
2425 rtl_hw_start_8102e_2(ioaddr, pdev);
2426 break;
2427 }
2428
2429 RTL_W8(Cfg9346, Cfg9346_Unlock);
2430
2431 RTL_W8(EarlyTxThres, EarlyTxThld);
2432
2433 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
2434
2435 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2436
2437 RTL_W16(CPlusCmd, tp->cp_cmd);
2438
2439 RTL_W16(IntrMitigate, 0x0000);
2440
2441 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2442
2443 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2444 rtl_set_rx_tx_config_registers(tp);
2445
2446 RTL_W8(Cfg9346, Cfg9346_Lock);
2447
2448 RTL_R8(IntrMask);
2449
2450 rtl_set_rx_mode(dev);
2451
2452 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2453
2454 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2455
2456 RTL_W16(IntrMask, tp->intr_event);
2457 }
2458
2459 static int rtl8101_change_mtu(struct net_device *dev, int new_mtu)
2460 {
2461 struct rtl8101_private *tp = netdev_priv(dev);
2462 int ret = 0;
2463
2464 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2465 return -EINVAL;
2466
2467 dev->mtu = new_mtu;
2468
2469 if (!netif_running(dev))
2470 goto out;
2471
2472 rtl8101_down(dev);
2473
2474 rtl8101_set_rxbufsize(tp, dev);
2475
2476 ret = rtl8101_init_ring(dev);
2477 if (ret < 0)
2478 goto out;
2479
2480 napi_enable(&tp->napi);
2481
2482 rtl_hw_start(dev);
2483
2484 rtl8101_request_timer(dev);
2485
2486 out:
2487 return ret;
2488 }
2489
2490 static inline void rtl8101_make_unusable_by_asic(struct RxDesc *desc)
2491 {
2492 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
2493 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2494 }
2495
2496 static void rtl8101_free_rx_skb(struct rtl8101_private *tp,
2497 struct sk_buff **sk_buff, struct RxDesc *desc)
2498 {
2499 struct pci_dev *pdev = tp->pci_dev;
2500
2501 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2502 PCI_DMA_FROMDEVICE);
2503 dev_kfree_skb(*sk_buff);
2504 *sk_buff = NULL;
2505 rtl8101_make_unusable_by_asic(desc);
2506 }
2507
2508 static inline void rtl8101_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2509 {
2510 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2511
2512 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2513 }
2514
2515 static inline void rtl8101_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2516 u32 rx_buf_sz)
2517 {
2518 desc->addr = cpu_to_le64(mapping);
2519 wmb();
2520 rtl8101_mark_to_asic(desc, rx_buf_sz);
2521 }
2522
2523 static struct sk_buff *rtl8101_alloc_rx_skb(struct pci_dev *pdev,
2524 struct net_device *dev,
2525 struct RxDesc *desc, int rx_buf_sz,
2526 unsigned int align)
2527 {
2528 struct sk_buff *skb;
2529 dma_addr_t mapping;
2530 unsigned int pad;
2531
2532 pad = align ? align : NET_IP_ALIGN;
2533
2534 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2535 if (!skb)
2536 goto err_out;
2537
2538 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2539
2540 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2541 PCI_DMA_FROMDEVICE);
2542
2543 rtl8101_map_to_asic(desc, mapping, rx_buf_sz);
2544 out:
2545 return skb;
2546
2547 err_out:
2548 rtl8101_make_unusable_by_asic(desc);
2549 goto out;
2550 }
2551
2552 static void rtl8101_rx_clear(struct rtl8101_private *tp)
2553 {
2554 unsigned int i;
2555
2556 for (i = 0; i < NUM_RX_DESC; i++) {
2557 if (tp->Rx_skbuff[i]) {
2558 rtl8101_free_rx_skb(tp, tp->Rx_skbuff + i,
2559 tp->RxDescArray + i);
2560 }
2561 }
2562 }
2563
2564 static u32 rtl8101_rx_fill(struct rtl8101_private *tp, struct net_device *dev,
2565 u32 start, u32 end)
2566 {
2567 u32 cur;
2568
2569 for (cur = start; end - cur != 0; cur++) {
2570 struct sk_buff *skb;
2571 unsigned int i = cur % NUM_RX_DESC;
2572
2573 WARN_ON((s32)(end - cur) < 0);
2574
2575 if (tp->Rx_skbuff[i])
2576 continue;
2577
2578 skb = rtl8101_alloc_rx_skb(tp->pci_dev, dev,
2579 tp->RxDescArray + i,
2580 tp->rx_buf_sz, tp->align);
2581 if (!skb)
2582 break;
2583
2584 tp->Rx_skbuff[i] = skb;
2585 }
2586 return cur - start;
2587 }
2588
2589 static inline void rtl8101_mark_as_last_descriptor(struct RxDesc *desc)
2590 {
2591 desc->opts1 |= cpu_to_le32(RingEnd);
2592 }
2593
2594 static void rtl8101_init_ring_indexes(struct rtl8101_private *tp)
2595 {
2596 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2597 }
2598
2599 static int rtl8101_init_ring(struct net_device *dev)
2600 {
2601 struct rtl8101_private *tp = netdev_priv(dev);
2602
2603 rtl8101_init_ring_indexes(tp);
2604
2605 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2606 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2607
2608 if (rtl8101_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2609 goto err_out;
2610
2611 rtl8101_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2612
2613 return 0;
2614
2615 err_out:
2616 rtl8101_rx_clear(tp);
2617 return -ENOMEM;
2618 }
2619
2620 static void rtl8101_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2621 struct TxDesc *desc)
2622 {
2623 unsigned int len = tx_skb->len;
2624
2625 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2626 desc->opts1 = 0x00;
2627 desc->opts2 = 0x00;
2628 desc->addr = 0x00;
2629 tx_skb->len = 0;
2630 }
2631
2632 static void rtl8101_tx_clear(struct rtl8101_private *tp)
2633 {
2634 unsigned int i;
2635
2636 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2637 unsigned int entry = i % NUM_TX_DESC;
2638 struct ring_info *tx_skb = tp->tx_skb + entry;
2639 unsigned int len = tx_skb->len;
2640
2641 if (len) {
2642 struct sk_buff *skb = tx_skb->skb;
2643
2644 rtl8101_unmap_tx_skb(tp->pci_dev, tx_skb,
2645 tp->TxDescArray + entry);
2646 if (skb) {
2647 dev_kfree_skb(skb);
2648 tx_skb->skb = NULL;
2649 }
2650 tp->dev->stats.tx_dropped++;
2651 }
2652 }
2653 tp->cur_tx = tp->dirty_tx = 0;
2654 }
2655
2656 static void rtl8101_schedule_work(struct net_device *dev, work_func_t task)
2657 {
2658 struct rtl8101_private *tp = netdev_priv(dev);
2659
2660 PREPARE_DELAYED_WORK(&tp->task, task);
2661 schedule_delayed_work(&tp->task, 4);
2662 }
2663
2664 static void rtl8101_wait_for_quiescence(struct net_device *dev)
2665 {
2666 struct rtl8101_private *tp = netdev_priv(dev);
2667 void __iomem *ioaddr = tp->mmio_addr;
2668
2669 synchronize_irq(dev->irq);
2670
2671 /* Wait for any pending NAPI task to complete */
2672 napi_disable(&tp->napi);
2673
2674 rtl8101_irq_mask_and_ack(ioaddr);
2675
2676 tp->intr_mask = 0xffff;
2677 RTL_W16(IntrMask, tp->intr_event);
2678 napi_enable(&tp->napi);
2679 }
2680
2681 static void rtl8101_reinit_task(struct work_struct *work)
2682 {
2683 struct rtl8101_private *tp =
2684 container_of(work, struct rtl8101_private, task.work);
2685 struct net_device *dev = tp->dev;
2686 int ret;
2687
2688 rtnl_lock();
2689
2690 if (!netif_running(dev))
2691 goto out_unlock;
2692
2693 rtl8101_wait_for_quiescence(dev);
2694 rtl8101_close(dev);
2695
2696 ret = rtl8101_open(dev);
2697 if (unlikely(ret < 0)) {
2698 if (net_ratelimit() && netif_msg_drv(tp)) {
2699 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
2700 " Rescheduling.\n", dev->name, ret);
2701 }
2702 rtl8101_schedule_work(dev, rtl8101_reinit_task);
2703 }
2704
2705 out_unlock:
2706 rtnl_unlock();
2707 }
2708
2709 static void rtl8101_reset_task(struct work_struct *work)
2710 {
2711 struct rtl8101_private *tp =
2712 container_of(work, struct rtl8101_private, task.work);
2713 struct net_device *dev = tp->dev;
2714
2715 rtnl_lock();
2716
2717 if (!netif_running(dev))
2718 goto out_unlock;
2719
2720 rtl8101_wait_for_quiescence(dev);
2721
2722 rtl8101_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
2723 rtl8101_tx_clear(tp);
2724
2725 if (tp->dirty_rx == tp->cur_rx) {
2726 rtl8101_init_ring_indexes(tp);
2727 rtl_hw_start(dev);
2728 netif_wake_queue(dev);
2729 rtl8101_check_link_status(dev, tp, tp->mmio_addr);
2730 } else {
2731 if (net_ratelimit() && netif_msg_intr(tp)) {
2732 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
2733 dev->name);
2734 }
2735 rtl8101_schedule_work(dev, rtl8101_reset_task);
2736 }
2737
2738 out_unlock:
2739 rtnl_unlock();
2740 }
2741
2742 static void rtl8101_tx_timeout(struct net_device *dev)
2743 {
2744 struct rtl8101_private *tp = netdev_priv(dev);
2745
2746 rtl8101_hw_reset(tp->mmio_addr);
2747
2748 /* Let's wait a bit while any (async) irq lands on */
2749 rtl8101_schedule_work(dev, rtl8101_reset_task);
2750 }
2751
2752 static int rtl8101_xmit_frags(struct rtl8101_private *tp, struct sk_buff *skb,
2753 u32 opts1)
2754 {
2755 struct skb_shared_info *info = skb_shinfo(skb);
2756 unsigned int cur_frag, entry;
2757 struct TxDesc * uninitialized_var(txd);
2758
2759 entry = tp->cur_tx;
2760 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2761 skb_frag_t *frag = info->frags + cur_frag;
2762 dma_addr_t mapping;
2763 u32 status, len;
2764 void *addr;
2765
2766 entry = (entry + 1) % NUM_TX_DESC;
2767
2768 txd = tp->TxDescArray + entry;
2769 len = frag->size;
2770 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2771 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2772
2773 /* anti gcc 2.95.3 bugware (sic) */
2774 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2775
2776 txd->opts1 = cpu_to_le32(status);
2777 txd->addr = cpu_to_le64(mapping);
2778
2779 tp->tx_skb[entry].len = len;
2780 }
2781
2782 if (cur_frag) {
2783 tp->tx_skb[entry].skb = skb;
2784 txd->opts1 |= cpu_to_le32(LastFrag);
2785 }
2786
2787 return cur_frag;
2788 }
2789
2790 static inline u32 rtl8101_tso_csum(struct sk_buff *skb, struct net_device *dev)
2791 {
2792 if (dev->features & NETIF_F_TSO) {
2793 u32 mss = skb_shinfo(skb)->gso_size;
2794
2795 if (mss)
2796 return LargeSend | ((mss & MSSMask) << MSSShift);
2797 }
2798 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2799 const struct iphdr *ip = ip_hdr(skb);
2800
2801 if (ip->protocol == IPPROTO_TCP)
2802 return IPCS | TCPCS;
2803 else if (ip->protocol == IPPROTO_UDP)
2804 return IPCS | UDPCS;
2805 WARN_ON(1); /* we need a WARN() */
2806 }
2807 return 0;
2808 }
2809
2810 static int rtl8101_start_xmit(struct sk_buff *skb, struct net_device *dev)
2811 {
2812 struct rtl8101_private *tp = netdev_priv(dev);
2813 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2814 struct TxDesc *txd = tp->TxDescArray + entry;
2815 void __iomem *ioaddr = tp->mmio_addr;
2816 dma_addr_t mapping;
2817 u32 status, len;
2818 u32 opts1;
2819 int ret = NETDEV_TX_OK;
2820
2821 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2822 if (netif_msg_drv(tp)) {
2823 printk(KERN_ERR
2824 "%s: BUG! Tx Ring full when queue awake!\n",
2825 dev->name);
2826 }
2827 goto err_stop;
2828 }
2829
2830 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2831 goto err_stop;
2832
2833 opts1 = DescOwn | rtl8101_tso_csum(skb, dev);
2834
2835 frags = rtl8101_xmit_frags(tp, skb, opts1);
2836 if (frags) {
2837 len = skb_headlen(skb);
2838 opts1 |= FirstFrag;
2839 } else {
2840 len = skb->len;
2841 opts1 |= FirstFrag | LastFrag;
2842 tp->tx_skb[entry].skb = skb;
2843 }
2844
2845 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2846
2847 tp->tx_skb[entry].len = len;
2848 txd->addr = cpu_to_le64(mapping);
2849 txd->opts2 = cpu_to_le32(rtl8101_tx_vlan_tag(tp, skb));
2850
2851 wmb();
2852
2853 /* anti gcc 2.95.3 bugware (sic) */
2854 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2855 txd->opts1 = cpu_to_le32(status);
2856
2857 dev->trans_start = jiffies;
2858
2859 tp->cur_tx += frags + 1;
2860
2861 smp_wmb();
2862
2863 RTL_W8(TxPoll, NPQ); /* set polling bit */
2864
2865 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2866 netif_stop_queue(dev);
2867 smp_rmb();
2868 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2869 netif_wake_queue(dev);
2870 }
2871
2872 out:
2873 return ret;
2874
2875 err_stop:
2876 netif_stop_queue(dev);
2877 ret = NETDEV_TX_BUSY;
2878 dev->stats.tx_dropped++;
2879 goto out;
2880 }
2881
2882 static void rtl8101_pcierr_interrupt(struct net_device *dev)
2883 {
2884 struct rtl8101_private *tp = netdev_priv(dev);
2885 struct pci_dev *pdev = tp->pci_dev;
2886 void __iomem *ioaddr = tp->mmio_addr;
2887 u16 pci_status, pci_cmd;
2888
2889 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2890 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2891
2892 if (netif_msg_intr(tp)) {
2893 printk(KERN_ERR
2894 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2895 dev->name, pci_cmd, pci_status);
2896 }
2897
2898 /*
2899 * The recovery sequence below admits a very elaborated explanation:
2900 * - it seems to work;
2901 * - I did not see what else could be done;
2902 * - it makes iop3xx happy.
2903 *
2904 * Feel free to adjust to your needs.
2905 */
2906 if (pdev->broken_parity_status)
2907 pci_cmd &= ~PCI_COMMAND_PARITY;
2908 else
2909 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2910
2911 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2912
2913 pci_write_config_word(pdev, PCI_STATUS,
2914 pci_status & (PCI_STATUS_DETECTED_PARITY |
2915 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2916 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2917
2918 /* The infamous DAC f*ckup only happens at boot time */
2919 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2920 if (netif_msg_intr(tp))
2921 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2922 tp->cp_cmd &= ~PCIDAC;
2923 RTL_W16(CPlusCmd, tp->cp_cmd);
2924 dev->features &= ~NETIF_F_HIGHDMA;
2925 }
2926
2927 rtl8101_hw_reset(ioaddr);
2928
2929 rtl8101_schedule_work(dev, rtl8101_reinit_task);
2930 }
2931
2932 static void rtl8101_tx_interrupt(struct net_device *dev,
2933 struct rtl8101_private *tp,
2934 void __iomem *ioaddr)
2935 {
2936 unsigned int dirty_tx, tx_left;
2937
2938 dirty_tx = tp->dirty_tx;
2939 smp_rmb();
2940 tx_left = tp->cur_tx - dirty_tx;
2941
2942 while (tx_left > 0) {
2943 unsigned int entry = dirty_tx % NUM_TX_DESC;
2944 struct ring_info *tx_skb = tp->tx_skb + entry;
2945 u32 len = tx_skb->len;
2946 u32 status;
2947
2948 rmb();
2949 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2950 if (status & DescOwn)
2951 break;
2952
2953 dev->stats.tx_bytes += len;
2954 dev->stats.tx_packets++;
2955
2956 rtl8101_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2957
2958 if (status & LastFrag) {
2959 dev_kfree_skb_irq(tx_skb->skb);
2960 tx_skb->skb = NULL;
2961 }
2962 dirty_tx++;
2963 tx_left--;
2964 }
2965
2966 if (tp->dirty_tx != dirty_tx) {
2967 tp->dirty_tx = dirty_tx;
2968 smp_wmb();
2969 if (netif_queue_stopped(dev) &&
2970 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2971 netif_wake_queue(dev);
2972 }
2973 /*
2974 * 8168 hack: TxPoll requests are lost when the Tx packets are
2975 * too close. Let's kick an extra TxPoll request when a burst
2976 * of start_xmit activity is detected (if it is not detected,
2977 * it is slow enough). -- FR
2978 */
2979 smp_rmb();
2980 if (tp->cur_tx != dirty_tx)
2981 RTL_W8(TxPoll, NPQ);
2982 }
2983 }
2984
2985 static inline int rtl8101_fragmented_frame(u32 status)
2986 {
2987 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2988 }
2989
2990 static inline void rtl8101_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2991 {
2992 u32 opts1 = le32_to_cpu(desc->opts1);
2993 u32 status = opts1 & RxProtoMask;
2994
2995 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2996 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2997 ((status == RxProtoIP) && !(opts1 & IPFail)))
2998 skb->ip_summed = CHECKSUM_UNNECESSARY;
2999 else
3000 skb->ip_summed = CHECKSUM_NONE;
3001 }
3002
3003 static inline bool rtl8101_try_rx_copy(struct sk_buff **sk_buff,
3004 struct rtl8101_private *tp, int pkt_size,
3005 dma_addr_t addr)
3006 {
3007 struct sk_buff *skb;
3008 bool done = false;
3009
3010 if (pkt_size >= rx_copybreak)
3011 goto out;
3012
3013 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
3014 if (!skb)
3015 goto out;
3016
3017 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3018 PCI_DMA_FROMDEVICE);
3019 skb_reserve(skb, NET_IP_ALIGN);
3020 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3021 *sk_buff = skb;
3022 done = true;
3023 out:
3024 return done;
3025 }
3026
3027 static int rtl8101_rx_interrupt(struct net_device *dev,
3028 struct rtl8101_private *tp,
3029 void __iomem *ioaddr, u32 budget)
3030 {
3031 unsigned int cur_rx, rx_left;
3032 unsigned int delta, count;
3033
3034 cur_rx = tp->cur_rx;
3035 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
3036 rx_left = min(rx_left, budget);
3037
3038 for (; rx_left > 0; rx_left--, cur_rx++) {
3039 unsigned int entry = cur_rx % NUM_RX_DESC;
3040 struct RxDesc *desc = tp->RxDescArray + entry;
3041 u32 status;
3042
3043 rmb();
3044 status = le32_to_cpu(desc->opts1);
3045
3046 if (status & DescOwn)
3047 break;
3048 if (unlikely(status & RxRES)) {
3049 if (netif_msg_rx_err(tp)) {
3050 printk(KERN_INFO
3051 "%s: Rx ERROR. status = %08x\n",
3052 dev->name, status);
3053 }
3054 dev->stats.rx_errors++;
3055 if (status & (RxRWT | RxRUNT))
3056 dev->stats.rx_length_errors++;
3057 if (status & RxCRC)
3058 dev->stats.rx_crc_errors++;
3059 if (status & RxFOVF) {
3060 rtl8101_schedule_work(dev, rtl8101_reset_task);
3061 dev->stats.rx_fifo_errors++;
3062 }
3063 rtl8101_mark_to_asic(desc, tp->rx_buf_sz);
3064 } else {
3065 struct sk_buff *skb = tp->Rx_skbuff[entry];
3066 dma_addr_t addr = le64_to_cpu(desc->addr);
3067 int pkt_size = (status & 0x00001FFF) - 4;
3068 struct pci_dev *pdev = tp->pci_dev;
3069
3070 /*
3071 * The driver does not support incoming fragmented
3072 * frames. They are seen as a symptom of over-mtu
3073 * sized frames.
3074 */
3075 if (unlikely(rtl8101_fragmented_frame(status))) {
3076 dev->stats.rx_dropped++;
3077 dev->stats.rx_length_errors++;
3078 rtl8101_mark_to_asic(desc, tp->rx_buf_sz);
3079 continue;
3080 }