2 * r8101.c: RealTek 8101 ethernet driver.
4 * This driver based on r8169 from Kernel 2.6.27.39 with SuSE patches
5 * All pciids except for 8101 are removed becaue we want use
6 * original realtek drivers except for 8101 because the
7 * vendors r8101 produce a kernel panic.
9 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
10 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
11 * Copyright (c) 2009 Arne Fitzenreiter <arne_f@ipfire.org>
12 * Copyright (c) a lot of people too. Please respect their work.
14 * See MAINTAINERS file for support contact information.
17 #include <linux/module.h>
18 #include <linux/moduleparam.h>
19 #include <linux/pci.h>
20 #include <linux/netdevice.h>
21 #include <linux/etherdevice.h>
22 #include <linux/delay.h>
23 #include <linux/ethtool.h>
24 #include <linux/mii.h>
25 #include <linux/if_vlan.h>
26 #include <linux/crc32.h>
29 #include <linux/tcp.h>
30 #include <linux/init.h>
31 #include <linux/dma-mapping.h>
33 #include <asm/system.h>
37 #define RTL8101_VERSION "2.3LK-NAPI"
38 #define MODULENAME "r8101"
39 #define PFX MODULENAME ": "
42 #define assert(expr) \
44 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
45 #expr,__FILE__,__FUNCTION__,__LINE__); \
47 #define dprintk(fmt, args...) \
48 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
50 #define assert(expr) do {} while (0)
51 #define dprintk(fmt, args...) do {} while (0)
52 #endif /* RTL8101_DEBUG */
54 #define R8101_MSG_DEFAULT \
55 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
57 #define TX_BUFFS_AVAIL(tp) \
58 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
60 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
61 static const int max_interrupt_work
= 20;
63 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
64 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
65 static const int multicast_filter_limit
= 32;
67 /* MAC address length */
68 #define MAC_ADDR_LEN 6
70 #define MAX_READ_REQUEST_SHIFT 12
71 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
72 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
73 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
74 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
75 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
76 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
78 #define R8101_REGS_SIZE 256
79 #define R8101_NAPI_WEIGHT 64
80 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
81 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
82 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
83 #define R8101_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
84 #define R8101_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
86 #define RTL8101_TX_TIMEOUT (6*HZ)
87 #define RTL8101_PHY_TIMEOUT (10*HZ)
89 /* write/read MMIO register */
90 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
91 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
92 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
93 #define RTL_R8(reg) readb (ioaddr + (reg))
94 #define RTL_R16(reg) readw (ioaddr + (reg))
95 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
98 RTL_GIGA_MAC_VER_01
= 0x01, // 8169
99 RTL_GIGA_MAC_VER_02
= 0x02, // 8169S
100 RTL_GIGA_MAC_VER_03
= 0x03, // 8110S
101 RTL_GIGA_MAC_VER_04
= 0x04, // 8169SB
102 RTL_GIGA_MAC_VER_05
= 0x05, // 8110SCd
103 RTL_GIGA_MAC_VER_06
= 0x06, // 8110SCe
104 RTL_GIGA_MAC_VER_07
= 0x07, // 8102e
105 RTL_GIGA_MAC_VER_08
= 0x08, // 8102e
106 RTL_GIGA_MAC_VER_09
= 0x09, // 8102e
107 RTL_GIGA_MAC_VER_10
= 0x0a, // 8101e
108 RTL_GIGA_MAC_VER_11
= 0x0b, // 8168Bb
109 RTL_GIGA_MAC_VER_12
= 0x0c, // 8168Be
110 RTL_GIGA_MAC_VER_13
= 0x0d, // 8101Eb
111 RTL_GIGA_MAC_VER_14
= 0x0e, // 8101 ?
112 RTL_GIGA_MAC_VER_15
= 0x0f, // 8101 ?
113 RTL_GIGA_MAC_VER_16
= 0x11, // 8101Ec
114 RTL_GIGA_MAC_VER_17
= 0x10, // 8168Bf
115 RTL_GIGA_MAC_VER_18
= 0x12, // 8168CP
116 RTL_GIGA_MAC_VER_19
= 0x13, // 8168C
117 RTL_GIGA_MAC_VER_20
= 0x14 // 8168C
120 #define _R(NAME,MAC,MASK) \
121 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
123 static const struct {
126 u32 RxConfigMask
; /* Clears the bits supported by this chip */
127 } rtl_chip_info
[] = {
128 _R("RTL8169", RTL_GIGA_MAC_VER_01
, 0xff7e1880), // 8169
129 _R("RTL8169s", RTL_GIGA_MAC_VER_02
, 0xff7e1880), // 8169S
130 _R("RTL8110s", RTL_GIGA_MAC_VER_03
, 0xff7e1880), // 8110S
131 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04
, 0xff7e1880), // 8169SB
132 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05
, 0xff7e1880), // 8110SCd
133 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06
, 0xff7e1880), // 8110SCe
134 _R("RTL8102e", RTL_GIGA_MAC_VER_07
, 0xff7e1880), // PCI-E
135 _R("RTL8102e", RTL_GIGA_MAC_VER_08
, 0xff7e1880), // PCI-E
136 _R("RTL8102e", RTL_GIGA_MAC_VER_09
, 0xff7e1880), // PCI-E
137 _R("RTL8101e", RTL_GIGA_MAC_VER_10
, 0xff7e1880), // PCI-E
138 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11
, 0xff7e1880), // PCI-E
139 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12
, 0xff7e1880), // PCI-E
140 _R("RTL8101e", RTL_GIGA_MAC_VER_13
, 0xff7e1880), // PCI-E 8139
141 _R("RTL8100e", RTL_GIGA_MAC_VER_14
, 0xff7e1880), // PCI-E 8139
142 _R("RTL8100e", RTL_GIGA_MAC_VER_15
, 0xff7e1880), // PCI-E 8139
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17
, 0xff7e1880), // PCI-E
144 _R("RTL8101e", RTL_GIGA_MAC_VER_16
, 0xff7e1880), // PCI-E
145 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18
, 0xff7e1880), // PCI-E
146 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19
, 0xff7e1880), // PCI-E
147 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20
, 0xff7e1880) // PCI-E
157 static void rtl_hw_start_8169(struct net_device
*);
158 static void rtl_hw_start_8168(struct net_device
*);
159 static void rtl_hw_start_8101(struct net_device
*);
161 static struct pci_device_id rtl8101_pci_tbl
[] = {
162 // { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
163 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
164 // { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
165 // { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
166 // { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
167 // { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
168 // { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
169 // { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
170 // { PCI_VENDOR_ID_LINKSYS, 0x1032,
171 // PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
173 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
177 MODULE_DEVICE_TABLE(pci
, rtl8101_pci_tbl
);
179 static int rx_copybreak
= 200;
186 MAC0
= 0, /* Ethernet hardware address. */
188 MAR0
= 8, /* Multicast filter. */
189 CounterAddrLow
= 0x10,
190 CounterAddrHigh
= 0x14,
191 TxDescStartAddrLow
= 0x20,
192 TxDescStartAddrHigh
= 0x24,
193 TxHDescStartAddrLow
= 0x28,
194 TxHDescStartAddrHigh
= 0x2c,
217 RxDescAddrLow
= 0xe4,
218 RxDescAddrHigh
= 0xe8,
221 FuncEventMask
= 0xf4,
222 FuncPresetState
= 0xf8,
223 FuncForceEvent
= 0xfc,
226 enum rtl8110_registers
{
232 enum rtl8168_8101_registers
{
235 #define CSIAR_FLAG 0x80000000
236 #define CSIAR_WRITE_CMD 0x80000000
237 #define CSIAR_BYTE_ENABLE 0x0f
238 #define CSIAR_BYTE_ENABLE_SHIFT 12
239 #define CSIAR_ADDR_MASK 0x0fff
242 #define EPHYAR_FLAG 0x80000000
243 #define EPHYAR_WRITE_CMD 0x80000000
244 #define EPHYAR_REG_MASK 0x1f
245 #define EPHYAR_REG_SHIFT 16
246 #define EPHYAR_DATA_MASK 0xffff
248 #define FIX_NAK_1 (1 << 4)
249 #define FIX_NAK_2 (1 << 3)
252 enum rtl_register_content
{
253 /* InterruptStatusBits */
257 TxDescUnavail
= 0x0080,
279 /* TXPoll register p.5 */
280 HPQ
= 0x80, /* Poll cmd on the high prio queue */
281 NPQ
= 0x40, /* Poll cmd on the low prio queue */
282 FSWInt
= 0x01, /* Forced software interrupt */
286 Cfg9346_Unlock
= 0xc0,
291 AcceptBroadcast
= 0x08,
292 AcceptMulticast
= 0x04,
294 AcceptAllPhys
= 0x01,
301 TxInterFrameGapShift
= 24,
302 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
304 /* Config1 register p.24 */
307 MSIEnable
= (1 << 5), /* Enable Message Signaled Interrupt */
308 Speed_down
= (1 << 4),
312 PMEnable
= (1 << 0), /* Power Management Enable */
314 /* Config2 register p. 25 */
315 PCI_Clock_66MHz
= 0x01,
316 PCI_Clock_33MHz
= 0x00,
318 /* Config3 register p.25 */
319 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
320 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
321 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
323 /* Config5 register p.27 */
324 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
325 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
326 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
327 LanWake
= (1 << 1), /* LanWake enable/disable */
328 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
331 TBIReset
= 0x80000000,
332 TBILoopback
= 0x40000000,
333 TBINwEnable
= 0x20000000,
334 TBINwRestart
= 0x10000000,
335 TBILinkOk
= 0x02000000,
336 TBINwComplete
= 0x01000000,
339 EnableBist
= (1 << 15), // 8168 8101
340 Mac_dbgo_oe
= (1 << 14), // 8168 8101
341 Normal_mode
= (1 << 13), // unused
342 Force_half_dup
= (1 << 12), // 8168 8101
343 Force_rxflow_en
= (1 << 11), // 8168 8101
344 Force_txflow_en
= (1 << 10), // 8168 8101
345 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
346 ASF
= (1 << 8), // 8168 8101
347 PktCntrDisable
= (1 << 7), // 8168 8101
348 Mac_dbgo_sel
= 0x001c, // 8168
353 INTT_0
= 0x0000, // 8168
354 INTT_1
= 0x0001, // 8168
355 INTT_2
= 0x0002, // 8168
356 INTT_3
= 0x0003, // 8168
358 /* rtl8101_PHYstatus */
369 TBILinkOK
= 0x02000000,
371 /* DumpCounterCommand */
375 enum desc_status_bit
{
376 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
377 RingEnd
= (1 << 30), /* End of descriptor ring */
378 FirstFrag
= (1 << 29), /* First segment of a packet */
379 LastFrag
= (1 << 28), /* Final segment of a packet */
382 LargeSend
= (1 << 27), /* TCP Large Send Offload (TSO) */
383 MSSShift
= 16, /* MSS value position */
384 MSSMask
= 0xfff, /* MSS value + LargeSend bit: 12 bits */
385 IPCS
= (1 << 18), /* Calculate IP checksum */
386 UDPCS
= (1 << 17), /* Calculate UDP/IP checksum */
387 TCPCS
= (1 << 16), /* Calculate TCP/IP checksum */
388 TxVlanTag
= (1 << 17), /* Add VLAN tag */
391 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
392 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
394 #define RxProtoUDP (PID1)
395 #define RxProtoTCP (PID0)
396 #define RxProtoIP (PID1 | PID0)
397 #define RxProtoMask RxProtoIP
399 IPFail
= (1 << 16), /* IP checksum failed */
400 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
401 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
402 RxVlanTag
= (1 << 16), /* VLAN tag available */
405 #define RsvdMask 0x3fffc000
422 u8 __pad
[sizeof(void *) - sizeof(u32
)];
426 RTL_FEATURE_WOL
= (1 << 0),
427 RTL_FEATURE_MSI
= (1 << 1),
428 RTL_FEATURE_GMII
= (1 << 2),
431 struct rtl8101_counters
{
438 __le32 tx_one_collision
;
439 __le32 tx_multi_collision
;
447 struct rtl8101_private
{
448 void __iomem
*mmio_addr
; /* memory map physical address */
449 struct pci_dev
*pci_dev
; /* Index of PCI device */
450 struct net_device
*dev
;
451 struct napi_struct napi
;
452 spinlock_t lock
; /* spin lock flag */
456 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
457 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
460 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
461 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
462 dma_addr_t TxPhyAddr
;
463 dma_addr_t RxPhyAddr
;
464 struct sk_buff
*Rx_skbuff
[NUM_RX_DESC
]; /* Rx data buffers */
465 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
468 struct timer_list timer
;
473 int phy_auto_nego_reg
;
474 int phy_1000_ctrl_reg
;
475 #ifdef CONFIG_R8101_VLAN
476 struct vlan_group
*vlgrp
;
478 int (*set_speed
)(struct net_device
*, u8 autoneg
, u16 speed
, u8 duplex
);
479 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
480 void (*phy_reset_enable
)(void __iomem
*);
481 void (*hw_start
)(struct net_device
*);
482 unsigned int (*phy_reset_pending
)(void __iomem
*);
483 unsigned int (*link_ok
)(void __iomem
*);
485 struct delayed_work task
;
488 struct mii_if_info mii
;
489 struct rtl8101_counters counters
;
492 MODULE_AUTHOR("Realtek,the Linux r8169 crew & Arne Fitzenreiter <arne_f@ipfire.org>");
493 MODULE_DESCRIPTION("RealTek RTL-8101 Fast Ethernet driver");
494 module_param(rx_copybreak
, int, 0);
495 MODULE_PARM_DESC(rx_copybreak
, "Copy breakpoint for copy-only-tiny-frames");
496 module_param(use_dac
, int, 0);
497 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
498 module_param_named(debug
, debug
.msg_enable
, int, 0);
499 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
500 MODULE_LICENSE("GPL");
501 MODULE_VERSION(RTL8101_VERSION
);
503 static int rtl8101_open(struct net_device
*dev
);
504 static int rtl8101_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
505 static irqreturn_t
rtl8101_interrupt(int irq
, void *dev_instance
);
506 static int rtl8101_init_ring(struct net_device
*dev
);
507 static void rtl_hw_start(struct net_device
*dev
);
508 static int rtl8101_close(struct net_device
*dev
);
509 static void rtl_set_rx_mode(struct net_device
*dev
);
510 static void rtl8101_tx_timeout(struct net_device
*dev
);
511 static struct net_device_stats
*rtl8101_get_stats(struct net_device
*dev
);
512 static int rtl8101_rx_interrupt(struct net_device
*, struct rtl8101_private
*,
513 void __iomem
*, u32 budget
);
514 static int rtl8101_change_mtu(struct net_device
*dev
, int new_mtu
);
515 static void rtl8101_down(struct net_device
*dev
);
516 static void rtl8101_rx_clear(struct rtl8101_private
*tp
);
517 static int rtl8101_poll(struct napi_struct
*napi
, int budget
);
519 static const unsigned int rtl8101_rx_config
=
520 (RX_FIFO_THRESH
<< RxCfgFIFOShift
) | (RX_DMA_BURST
<< RxCfgDMAShift
);
522 static void mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
526 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
528 for (i
= 20; i
> 0; i
--) {
530 * Check if the RTL8101 has completed writing to the specified
533 if (!(RTL_R32(PHYAR
) & 0x80000000))
539 static int mdio_read(void __iomem
*ioaddr
, int reg_addr
)
543 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
545 for (i
= 20; i
> 0; i
--) {
547 * Check if the RTL8101 has completed retrieving data from
548 * the specified MII register.
550 if (RTL_R32(PHYAR
) & 0x80000000) {
551 value
= RTL_R32(PHYAR
) & 0xffff;
559 static void mdio_patch(void __iomem
*ioaddr
, int reg_addr
, int value
)
561 mdio_write(ioaddr
, reg_addr
, mdio_read(ioaddr
, reg_addr
) | value
);
564 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
567 struct rtl8101_private
*tp
= netdev_priv(dev
);
568 void __iomem
*ioaddr
= tp
->mmio_addr
;
570 mdio_write(ioaddr
, location
, val
);
573 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
575 struct rtl8101_private
*tp
= netdev_priv(dev
);
576 void __iomem
*ioaddr
= tp
->mmio_addr
;
578 return mdio_read(ioaddr
, location
);
581 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
585 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
586 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
588 for (i
= 0; i
< 100; i
++) {
589 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
595 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
600 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
602 for (i
= 0; i
< 100; i
++) {
603 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
604 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
613 static void rtl_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
617 RTL_W32(CSIDR
, value
);
618 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
619 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
621 for (i
= 0; i
< 100; i
++) {
622 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
628 static u32
rtl_csi_read(void __iomem
*ioaddr
, int addr
)
633 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
634 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
636 for (i
= 0; i
< 100; i
++) {
637 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
638 value
= RTL_R32(CSIDR
);
647 static void rtl8101_irq_mask_and_ack(void __iomem
*ioaddr
)
649 RTL_W16(IntrMask
, 0x0000);
651 RTL_W16(IntrStatus
, 0xffff);
654 static void rtl8101_asic_down(void __iomem
*ioaddr
)
656 RTL_W8(ChipCmd
, 0x00);
657 rtl8101_irq_mask_and_ack(ioaddr
);
661 static unsigned int rtl8101_tbi_reset_pending(void __iomem
*ioaddr
)
663 return RTL_R32(TBICSR
) & TBIReset
;
666 static unsigned int rtl8101_xmii_reset_pending(void __iomem
*ioaddr
)
668 return mdio_read(ioaddr
, MII_BMCR
) & BMCR_RESET
;
671 static unsigned int rtl8101_tbi_link_ok(void __iomem
*ioaddr
)
673 return RTL_R32(TBICSR
) & TBILinkOk
;
676 static unsigned int rtl8101_xmii_link_ok(void __iomem
*ioaddr
)
678 return RTL_R8(PHYstatus
) & LinkStatus
;
681 static void rtl8101_tbi_reset_enable(void __iomem
*ioaddr
)
683 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
686 static void rtl8101_xmii_reset_enable(void __iomem
*ioaddr
)
690 val
= mdio_read(ioaddr
, MII_BMCR
) | BMCR_RESET
;
691 mdio_write(ioaddr
, MII_BMCR
, val
& 0xffff);
694 static void rtl8101_check_link_status(struct net_device
*dev
,
695 struct rtl8101_private
*tp
,
696 void __iomem
*ioaddr
)
700 spin_lock_irqsave(&tp
->lock
, flags
);
701 if (tp
->link_ok(ioaddr
)) {
702 netif_carrier_on(dev
);
703 if (netif_msg_ifup(tp
))
704 printk(KERN_INFO PFX
"%s: link up\n", dev
->name
);
706 if (netif_msg_ifdown(tp
))
707 printk(KERN_INFO PFX
"%s: link down\n", dev
->name
);
708 netif_carrier_off(dev
);
710 spin_unlock_irqrestore(&tp
->lock
, flags
);
713 static void rtl8101_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
715 struct rtl8101_private
*tp
= netdev_priv(dev
);
716 void __iomem
*ioaddr
= tp
->mmio_addr
;
721 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
722 wol
->supported
= WAKE_ANY
;
724 spin_lock_irq(&tp
->lock
);
726 options
= RTL_R8(Config1
);
727 if (!(options
& PMEnable
))
730 options
= RTL_R8(Config3
);
731 if (options
& LinkUp
)
732 wol
->wolopts
|= WAKE_PHY
;
733 if (options
& MagicPacket
)
734 wol
->wolopts
|= WAKE_MAGIC
;
736 options
= RTL_R8(Config5
);
738 wol
->wolopts
|= WAKE_UCAST
;
740 wol
->wolopts
|= WAKE_BCAST
;
742 wol
->wolopts
|= WAKE_MCAST
;
745 spin_unlock_irq(&tp
->lock
);
748 static int rtl8101_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
750 struct rtl8101_private
*tp
= netdev_priv(dev
);
751 void __iomem
*ioaddr
= tp
->mmio_addr
;
758 { WAKE_ANY
, Config1
, PMEnable
},
759 { WAKE_PHY
, Config3
, LinkUp
},
760 { WAKE_MAGIC
, Config3
, MagicPacket
},
761 { WAKE_UCAST
, Config5
, UWF
},
762 { WAKE_BCAST
, Config5
, BWF
},
763 { WAKE_MCAST
, Config5
, MWF
},
764 { WAKE_ANY
, Config5
, LanWake
}
767 spin_lock_irq(&tp
->lock
);
769 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
771 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
772 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
773 if (wol
->wolopts
& cfg
[i
].opt
)
774 options
|= cfg
[i
].mask
;
775 RTL_W8(cfg
[i
].reg
, options
);
778 RTL_W8(Cfg9346
, Cfg9346_Lock
);
781 tp
->features
|= RTL_FEATURE_WOL
;
783 tp
->features
&= ~RTL_FEATURE_WOL
;
785 spin_unlock_irq(&tp
->lock
);
790 static void rtl8101_get_drvinfo(struct net_device
*dev
,
791 struct ethtool_drvinfo
*info
)
793 struct rtl8101_private
*tp
= netdev_priv(dev
);
795 strcpy(info
->driver
, MODULENAME
);
796 strcpy(info
->version
, RTL8101_VERSION
);
797 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
800 static int rtl8101_get_regs_len(struct net_device
*dev
)
802 return R8101_REGS_SIZE
;
805 static int rtl8101_set_speed_tbi(struct net_device
*dev
,
806 u8 autoneg
, u16 speed
, u8 duplex
)
808 struct rtl8101_private
*tp
= netdev_priv(dev
);
809 void __iomem
*ioaddr
= tp
->mmio_addr
;
813 reg
= RTL_R32(TBICSR
);
814 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
815 (duplex
== DUPLEX_FULL
)) {
816 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
817 } else if (autoneg
== AUTONEG_ENABLE
)
818 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
820 if (netif_msg_link(tp
)) {
821 printk(KERN_WARNING
"%s: "
822 "incorrect speed setting refused in TBI mode\n",
831 static int rtl8101_set_speed_xmii(struct net_device
*dev
,
832 u8 autoneg
, u16 speed
, u8 duplex
)
834 struct rtl8101_private
*tp
= netdev_priv(dev
);
835 void __iomem
*ioaddr
= tp
->mmio_addr
;
838 if (autoneg
== AUTONEG_ENABLE
) {
841 auto_nego
= mdio_read(ioaddr
, MII_ADVERTISE
);
842 auto_nego
|= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
843 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
844 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
846 giga_ctrl
= mdio_read(ioaddr
, MII_CTRL1000
);
847 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
849 /* The 8100e/8101e/8102e do Fast Ethernet only. */
850 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_07
) &&
851 (tp
->mac_version
!= RTL_GIGA_MAC_VER_08
) &&
852 (tp
->mac_version
!= RTL_GIGA_MAC_VER_09
) &&
853 (tp
->mac_version
!= RTL_GIGA_MAC_VER_10
) &&
854 (tp
->mac_version
!= RTL_GIGA_MAC_VER_13
) &&
855 (tp
->mac_version
!= RTL_GIGA_MAC_VER_14
) &&
856 (tp
->mac_version
!= RTL_GIGA_MAC_VER_15
) &&
857 (tp
->mac_version
!= RTL_GIGA_MAC_VER_16
)) {
858 giga_ctrl
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
859 } else if (netif_msg_link(tp
)) {
860 printk(KERN_INFO
"%s: PHY does not support 1000Mbps.\n",
864 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
866 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_11
) ||
867 (tp
->mac_version
== RTL_GIGA_MAC_VER_12
) ||
868 (tp
->mac_version
>= RTL_GIGA_MAC_VER_17
)) {
871 * Vendor specific (0x1f) and reserved (0x0e) MII
874 mdio_write(ioaddr
, 0x1f, 0x0000);
875 mdio_write(ioaddr
, 0x0e, 0x0000);
878 tp
->phy_auto_nego_reg
= auto_nego
;
880 mdio_write(ioaddr
, MII_ADVERTISE
, auto_nego
);
881 mdio_write(ioaddr
, MII_CTRL1000
, giga_ctrl
);
885 if (speed
== SPEED_10
)
887 else if (speed
== SPEED_100
)
888 bmcr
= BMCR_SPEED100
;
892 if (duplex
== DUPLEX_FULL
)
893 bmcr
|= BMCR_FULLDPLX
;
895 mdio_write(ioaddr
, 0x1f, 0x0000);
898 tp
->phy_1000_ctrl_reg
= giga_ctrl
;
900 mdio_write(ioaddr
, MII_BMCR
, bmcr
);
902 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
903 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
904 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
905 mdio_write(ioaddr
, 0x17, 0x2138);
906 mdio_write(ioaddr
, 0x0e, 0x0260);
908 mdio_write(ioaddr
, 0x17, 0x2108);
909 mdio_write(ioaddr
, 0x0e, 0x0000);
916 static int rtl8101_set_speed(struct net_device
*dev
,
917 u8 autoneg
, u16 speed
, u8 duplex
)
919 struct rtl8101_private
*tp
= netdev_priv(dev
);
922 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
);
924 if (netif_running(dev
) && (tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
925 mod_timer(&tp
->timer
, jiffies
+ RTL8101_PHY_TIMEOUT
);
930 static int rtl8101_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
932 struct rtl8101_private
*tp
= netdev_priv(dev
);
936 spin_lock_irqsave(&tp
->lock
, flags
);
937 ret
= rtl8101_set_speed(dev
, cmd
->autoneg
, cmd
->speed
, cmd
->duplex
);
938 spin_unlock_irqrestore(&tp
->lock
, flags
);
943 static u32
rtl8101_get_rx_csum(struct net_device
*dev
)
945 struct rtl8101_private
*tp
= netdev_priv(dev
);
947 return tp
->cp_cmd
& RxChkSum
;
950 static int rtl8101_set_rx_csum(struct net_device
*dev
, u32 data
)
952 struct rtl8101_private
*tp
= netdev_priv(dev
);
953 void __iomem
*ioaddr
= tp
->mmio_addr
;
956 spin_lock_irqsave(&tp
->lock
, flags
);
959 tp
->cp_cmd
|= RxChkSum
;
961 tp
->cp_cmd
&= ~RxChkSum
;
963 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
966 spin_unlock_irqrestore(&tp
->lock
, flags
);
971 #ifdef CONFIG_R8101_VLAN
973 static inline u32
rtl8101_tx_vlan_tag(struct rtl8101_private
*tp
,
976 return (tp
->vlgrp
&& vlan_tx_tag_present(skb
)) ?
977 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
980 static void rtl8101_vlan_rx_register(struct net_device
*dev
,
981 struct vlan_group
*grp
)
983 struct rtl8101_private
*tp
= netdev_priv(dev
);
984 void __iomem
*ioaddr
= tp
->mmio_addr
;
987 spin_lock_irqsave(&tp
->lock
, flags
);
990 tp
->cp_cmd
|= RxVlan
;
992 tp
->cp_cmd
&= ~RxVlan
;
993 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
995 spin_unlock_irqrestore(&tp
->lock
, flags
);
998 static int rtl8101_rx_vlan_skb(struct rtl8101_private
*tp
, struct RxDesc
*desc
,
1001 u32 opts2
= le32_to_cpu(desc
->opts2
);
1002 struct vlan_group
*vlgrp
= tp
->vlgrp
;
1005 if (vlgrp
&& (opts2
& RxVlanTag
)) {
1006 vlan_hwaccel_receive_skb(skb
, vlgrp
, swab16(opts2
& 0xffff));
1014 #else /* !CONFIG_R8101_VLAN */
1016 static inline u32
rtl8101_tx_vlan_tag(struct rtl8101_private
*tp
,
1017 struct sk_buff
*skb
)
1022 static int rtl8101_rx_vlan_skb(struct rtl8101_private
*tp
, struct RxDesc
*desc
,
1023 struct sk_buff
*skb
)
1030 static int rtl8101_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1032 struct rtl8101_private
*tp
= netdev_priv(dev
);
1033 void __iomem
*ioaddr
= tp
->mmio_addr
;
1037 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1038 cmd
->port
= PORT_FIBRE
;
1039 cmd
->transceiver
= XCVR_INTERNAL
;
1041 status
= RTL_R32(TBICSR
);
1042 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1043 cmd
->autoneg
= !!(status
& TBINwEnable
);
1045 cmd
->speed
= SPEED_1000
;
1046 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1051 static int rtl8101_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1053 struct rtl8101_private
*tp
= netdev_priv(dev
);
1055 return mii_ethtool_gset(&tp
->mii
, cmd
);
1058 static int rtl8101_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1060 struct rtl8101_private
*tp
= netdev_priv(dev
);
1061 unsigned long flags
;
1064 spin_lock_irqsave(&tp
->lock
, flags
);
1066 rc
= tp
->get_settings(dev
, cmd
);
1068 spin_unlock_irqrestore(&tp
->lock
, flags
);
1072 static void rtl8101_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1075 struct rtl8101_private
*tp
= netdev_priv(dev
);
1076 unsigned long flags
;
1078 if (regs
->len
> R8101_REGS_SIZE
)
1079 regs
->len
= R8101_REGS_SIZE
;
1081 spin_lock_irqsave(&tp
->lock
, flags
);
1082 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1083 spin_unlock_irqrestore(&tp
->lock
, flags
);
1086 static u32
rtl8101_get_msglevel(struct net_device
*dev
)
1088 struct rtl8101_private
*tp
= netdev_priv(dev
);
1090 return tp
->msg_enable
;
1093 static void rtl8101_set_msglevel(struct net_device
*dev
, u32 value
)
1095 struct rtl8101_private
*tp
= netdev_priv(dev
);
1097 tp
->msg_enable
= value
;
1100 static const char rtl8101_gstrings
[][ETH_GSTRING_LEN
] = {
1107 "tx_single_collisions",
1108 "tx_multi_collisions",
1116 static int rtl8101_get_sset_count(struct net_device
*dev
, int sset
)
1120 return ARRAY_SIZE(rtl8101_gstrings
);
1126 static void rtl8101_update_counters(struct net_device
*dev
)
1128 struct rtl8101_private
*tp
= netdev_priv(dev
);
1129 void __iomem
*ioaddr
= tp
->mmio_addr
;
1130 struct rtl8101_counters
*counters
;
1136 * Some chips are unable to dump tally counters when the receiver
1139 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
1142 counters
= pci_alloc_consistent(tp
->pci_dev
, sizeof(*counters
), &paddr
);
1146 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1147 cmd
= (u64
)paddr
& DMA_32BIT_MASK
;
1148 RTL_W32(CounterAddrLow
, cmd
);
1149 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1152 if ((RTL_R32(CounterAddrLow
) & CounterDump
) == 0) {
1153 /* copy updated counters */
1154 memcpy(&tp
->counters
, counters
, sizeof(*counters
));
1160 RTL_W32(CounterAddrLow
, 0);
1161 RTL_W32(CounterAddrHigh
, 0);
1163 pci_free_consistent(tp
->pci_dev
, sizeof(*counters
), counters
, paddr
);
1166 static void rtl8101_get_ethtool_stats(struct net_device
*dev
,
1167 struct ethtool_stats
*stats
, u64
*data
)
1169 struct rtl8101_private
*tp
= netdev_priv(dev
);
1173 rtl8101_update_counters(dev
);
1175 data
[0] = le64_to_cpu(tp
->counters
.tx_packets
);
1176 data
[1] = le64_to_cpu(tp
->counters
.rx_packets
);
1177 data
[2] = le64_to_cpu(tp
->counters
.tx_errors
);
1178 data
[3] = le32_to_cpu(tp
->counters
.rx_errors
);
1179 data
[4] = le16_to_cpu(tp
->counters
.rx_missed
);
1180 data
[5] = le16_to_cpu(tp
->counters
.align_errors
);
1181 data
[6] = le32_to_cpu(tp
->counters
.tx_one_collision
);
1182 data
[7] = le32_to_cpu(tp
->counters
.tx_multi_collision
);
1183 data
[8] = le64_to_cpu(tp
->counters
.rx_unicast
);
1184 data
[9] = le64_to_cpu(tp
->counters
.rx_broadcast
);
1185 data
[10] = le32_to_cpu(tp
->counters
.rx_multicast
);
1186 data
[11] = le16_to_cpu(tp
->counters
.tx_aborted
);
1187 data
[12] = le16_to_cpu(tp
->counters
.tx_underun
);
1190 static void rtl8101_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1194 memcpy(data
, *rtl8101_gstrings
, sizeof(rtl8101_gstrings
));
1199 static const struct ethtool_ops rtl8101_ethtool_ops
= {
1200 .get_drvinfo
= rtl8101_get_drvinfo
,
1201 .get_regs_len
= rtl8101_get_regs_len
,
1202 .get_link
= ethtool_op_get_link
,
1203 .get_settings
= rtl8101_get_settings
,
1204 .set_settings
= rtl8101_set_settings
,
1205 .get_msglevel
= rtl8101_get_msglevel
,
1206 .set_msglevel
= rtl8101_set_msglevel
,
1207 .get_rx_csum
= rtl8101_get_rx_csum
,
1208 .set_rx_csum
= rtl8101_set_rx_csum
,
1209 .set_tx_csum
= ethtool_op_set_tx_csum
,
1210 .set_sg
= ethtool_op_set_sg
,
1211 .set_tso
= ethtool_op_set_tso
,
1212 .get_regs
= rtl8101_get_regs
,
1213 .get_wol
= rtl8101_get_wol
,
1214 .set_wol
= rtl8101_set_wol
,
1215 .get_strings
= rtl8101_get_strings
,
1216 .get_sset_count
= rtl8101_get_sset_count
,
1217 .get_ethtool_stats
= rtl8101_get_ethtool_stats
,
1220 static void rtl8101_write_gmii_reg_bit(void __iomem
*ioaddr
, int reg
,
1221 int bitnum
, int bitval
)
1225 val
= mdio_read(ioaddr
, reg
);
1226 val
= (bitval
== 1) ?
1227 val
| (bitval
<< bitnum
) : val
& ~(0x0001 << bitnum
);
1228 mdio_write(ioaddr
, reg
, val
& 0xffff);
1231 static void rtl8101_get_mac_version(struct rtl8101_private
*tp
,
1232 void __iomem
*ioaddr
)
1235 * The driver currently handles the 8168Bf and the 8168Be identically
1236 * but they can be identified more specifically through the test below
1239 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1241 * Same thing for the 8101Eb and the 8101Ec:
1243 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1251 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1252 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1253 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1254 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20
},
1257 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1258 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1259 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1260 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1263 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1264 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1265 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1266 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1267 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1268 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1269 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1270 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1271 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1272 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1273 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1274 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1275 /* FIXME: where did these entries come from ? -- FR */
1276 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1277 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1280 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1281 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1282 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1283 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1284 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1285 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1287 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01
} /* Catch-all */
1291 reg
= RTL_R32(TxConfig
);
1292 while ((reg
& p
->mask
) != p
->val
)
1294 tp
->mac_version
= p
->mac_version
;
1296 if (p
->mask
== 0x00000000) {
1297 struct pci_dev
*pdev
= tp
->pci_dev
;
1299 dev_info(&pdev
->dev
, "unknown MAC (%08x)\n", reg
);
1303 static void rtl8101_print_mac_version(struct rtl8101_private
*tp
)
1305 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1313 static void rtl_phy_write(void __iomem
*ioaddr
, struct phy_reg
*regs
, int len
)
1316 mdio_write(ioaddr
, regs
->reg
, regs
->val
);
1321 static void rtl8101s_hw_phy_config(void __iomem
*ioaddr
)
1324 u16 regs
[5]; /* Beware of bit-sign propagation */
1325 } phy_magic
[5] = { {
1326 { 0x0000, //w 4 15 12 0
1327 0x00a1, //w 3 15 0 00a1
1328 0x0008, //w 2 15 0 0008
1329 0x1020, //w 1 15 0 1020
1330 0x1000 } },{ //w 0 15 0 1000
1331 { 0x7000, //w 4 15 12 7
1332 0xff41, //w 3 15 0 ff41
1333 0xde60, //w 2 15 0 de60
1334 0x0140, //w 1 15 0 0140
1335 0x0077 } },{ //w 0 15 0 0077
1336 { 0xa000, //w 4 15 12 a
1337 0xdf01, //w 3 15 0 df01
1338 0xdf20, //w 2 15 0 df20
1339 0xff95, //w 1 15 0 ff95
1340 0xfa00 } },{ //w 0 15 0 fa00
1341 { 0xb000, //w 4 15 12 b
1342 0xff41, //w 3 15 0 ff41
1343 0xde20, //w 2 15 0 de20
1344 0x0140, //w 1 15 0 0140
1345 0x00bb } },{ //w 0 15 0 00bb
1346 { 0xf000, //w 4 15 12 f
1347 0xdf01, //w 3 15 0 df01
1348 0xdf20, //w 2 15 0 df20
1349 0xff95, //w 1 15 0 ff95
1350 0xbf00 } //w 0 15 0 bf00
1355 mdio_write(ioaddr
, 0x1f, 0x0001); //w 31 2 0 1
1356 mdio_write(ioaddr
, 0x15, 0x1000); //w 21 15 0 1000
1357 mdio_write(ioaddr
, 0x18, 0x65c7); //w 24 15 0 65c7
1358 rtl8101_write_gmii_reg_bit(ioaddr
, 4, 11, 0); //w 4 11 11 0
1360 for (i
= 0; i
< ARRAY_SIZE(phy_magic
); i
++, p
++) {
1363 val
= (mdio_read(ioaddr
, pos
) & 0x0fff) | (p
->regs
[0] & 0xffff);
1364 mdio_write(ioaddr
, pos
, val
);
1366 mdio_write(ioaddr
, pos
, p
->regs
[4 - pos
] & 0xffff);
1367 rtl8101_write_gmii_reg_bit(ioaddr
, 4, 11, 1); //w 4 11 11 1
1368 rtl8101_write_gmii_reg_bit(ioaddr
, 4, 11, 0); //w 4 11 11 0
1370 mdio_write(ioaddr
, 0x1f, 0x0000); //w 31 2 0 0
1373 static void rtl8101sb_hw_phy_config(void __iomem
*ioaddr
)
1375 struct phy_reg phy_reg_init
[] = {
1381 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1384 static void rtl8168cp_hw_phy_config(void __iomem
*ioaddr
)
1386 struct phy_reg phy_reg_init
[] = {
1394 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1397 static void rtl8168c_hw_phy_config(void __iomem
*ioaddr
)
1399 struct phy_reg phy_reg_init
[] = {
1416 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1419 static void rtl8168cx_hw_phy_config(void __iomem
*ioaddr
)
1421 struct phy_reg phy_reg_init
[] = {
1432 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1435 static void rtl8102e_hw_phy_config(void __iomem
*ioaddr
)
1437 struct phy_reg phy_reg_init
[] = {
1444 mdio_write(ioaddr
, 0x1f, 0x0000);
1445 mdio_patch(ioaddr
, 0x11, 1 << 12);
1446 mdio_patch(ioaddr
, 0x19, 1 << 13);
1448 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1451 static void rtl_hw_phy_config(struct net_device
*dev
)
1453 struct rtl8101_private
*tp
= netdev_priv(dev
);
1454 void __iomem
*ioaddr
= tp
->mmio_addr
;
1456 rtl8101_print_mac_version(tp
);
1458 switch (tp
->mac_version
) {
1459 case RTL_GIGA_MAC_VER_01
:
1461 case RTL_GIGA_MAC_VER_02
:
1462 case RTL_GIGA_MAC_VER_03
:
1463 rtl8101s_hw_phy_config(ioaddr
);
1465 case RTL_GIGA_MAC_VER_04
:
1466 rtl8101sb_hw_phy_config(ioaddr
);
1468 case RTL_GIGA_MAC_VER_07
:
1469 case RTL_GIGA_MAC_VER_08
:
1470 case RTL_GIGA_MAC_VER_09
:
1471 rtl8102e_hw_phy_config(ioaddr
);
1473 case RTL_GIGA_MAC_VER_18
:
1474 rtl8168cp_hw_phy_config(ioaddr
);
1476 case RTL_GIGA_MAC_VER_19
:
1477 rtl8168c_hw_phy_config(ioaddr
);
1479 case RTL_GIGA_MAC_VER_20
:
1480 rtl8168cx_hw_phy_config(ioaddr
);
1487 static void rtl8101_phy_timer(unsigned long __opaque
)
1489 struct net_device
*dev
= (struct net_device
*)__opaque
;
1490 struct rtl8101_private
*tp
= netdev_priv(dev
);
1491 struct timer_list
*timer
= &tp
->timer
;
1492 void __iomem
*ioaddr
= tp
->mmio_addr
;
1493 unsigned long timeout
= RTL8101_PHY_TIMEOUT
;
1495 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
1497 if (!(tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
1500 spin_lock_irq(&tp
->lock
);
1502 if (tp
->phy_reset_pending(ioaddr
)) {
1504 * A busy loop could burn quite a few cycles on nowadays CPU.
1505 * Let's delay the execution of the timer for a few ticks.
1511 if (tp
->link_ok(ioaddr
))
1514 if (netif_msg_link(tp
))
1515 printk(KERN_WARNING
"%s: PHY reset until link up\n", dev
->name
);
1517 tp
->phy_reset_enable(ioaddr
);
1520 mod_timer(timer
, jiffies
+ timeout
);
1522 spin_unlock_irq(&tp
->lock
);
1525 static inline void rtl8101_delete_timer(struct net_device
*dev
)
1527 struct rtl8101_private
*tp
= netdev_priv(dev
);
1528 struct timer_list
*timer
= &tp
->timer
;
1530 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
1533 del_timer_sync(timer
);
1536 static inline void rtl8101_request_timer(struct net_device
*dev
)
1538 struct rtl8101_private
*tp
= netdev_priv(dev
);
1539 struct timer_list
*timer
= &tp
->timer
;
1541 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
1544 mod_timer(timer
, jiffies
+ RTL8101_PHY_TIMEOUT
);
1547 #ifdef CONFIG_NET_POLL_CONTROLLER
1549 * Polling 'interrupt' - used by things like netconsole to send skbs
1550 * without having to re-enable interrupts. It's not called while
1551 * the interrupt routine is executing.
1553 static void rtl8101_netpoll(struct net_device
*dev
)
1555 struct rtl8101_private
*tp
= netdev_priv(dev
);
1556 struct pci_dev
*pdev
= tp
->pci_dev
;
1558 disable_irq(pdev
->irq
);
1559 rtl8101_interrupt(pdev
->irq
, dev
);
1560 enable_irq(pdev
->irq
);
1564 static void rtl8101_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
1565 void __iomem
*ioaddr
)
1568 pci_release_regions(pdev
);
1569 pci_disable_device(pdev
);
1573 static void rtl8101_phy_reset(struct net_device
*dev
,
1574 struct rtl8101_private
*tp
)
1576 void __iomem
*ioaddr
= tp
->mmio_addr
;
1579 tp
->phy_reset_enable(ioaddr
);
1580 for (i
= 0; i
< 100; i
++) {
1581 if (!tp
->phy_reset_pending(ioaddr
))
1585 if (netif_msg_link(tp
))
1586 printk(KERN_ERR
"%s: PHY reset failed.\n", dev
->name
);
1589 static void rtl8101_init_phy(struct net_device
*dev
, struct rtl8101_private
*tp
)
1591 void __iomem
*ioaddr
= tp
->mmio_addr
;
1593 rtl_hw_phy_config(dev
);
1595 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
1596 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1600 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
1602 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
1603 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
1605 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
1606 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1608 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1609 mdio_write(ioaddr
, 0x0b, 0x0000); //w 0x0b 15 0 0
1612 rtl8101_phy_reset(dev
, tp
);
1615 * rtl8101_set_speed_xmii takes good care of the Fast Ethernet
1616 * only 8101. Don't panic.
1618 rtl8101_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
);
1620 if ((RTL_R8(PHYstatus
) & TBI_Enable
) && netif_msg_link(tp
))
1621 printk(KERN_INFO PFX
"%s: TBI auto-negotiating\n", dev
->name
);
1624 static void rtl_rar_set(struct rtl8101_private
*tp
, u8
*addr
)
1626 void __iomem
*ioaddr
= tp
->mmio_addr
;
1630 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
1631 high
= addr
[4] | (addr
[5] << 8);
1633 spin_lock_irq(&tp
->lock
);
1635 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1637 RTL_W32(MAC4
, high
);
1638 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1640 spin_unlock_irq(&tp
->lock
);
1643 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
1645 struct rtl8101_private
*tp
= netdev_priv(dev
);
1646 struct sockaddr
*addr
= p
;
1648 if (!is_valid_ether_addr(addr
->sa_data
))
1649 return -EADDRNOTAVAIL
;
1651 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
1653 rtl_rar_set(tp
, dev
->dev_addr
);
1658 static int rtl8101_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1660 struct rtl8101_private
*tp
= netdev_priv(dev
);
1661 struct mii_ioctl_data
*data
= if_mii(ifr
);
1663 if (!netif_running(dev
))
1668 data
->phy_id
= 32; /* Internal PHY */
1672 data
->val_out
= mdio_read(tp
->mmio_addr
, data
->reg_num
& 0x1f);
1676 if (!capable(CAP_NET_ADMIN
))
1678 mdio_write(tp
->mmio_addr
, data
->reg_num
& 0x1f, data
->val_in
);
1684 static const struct rtl_cfg_info
{
1685 void (*hw_start
)(struct net_device
*);
1686 unsigned int region
;
1691 } rtl_cfg_infos
[] = {
1693 .hw_start
= rtl_hw_start_8169
,
1696 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
1697 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
1698 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
1699 .features
= RTL_FEATURE_GMII
1702 .hw_start
= rtl_hw_start_8168
,
1705 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
1706 TxErr
| TxOK
| RxOK
| RxErr
,
1707 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
1708 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
1711 .hw_start
= rtl_hw_start_8101
,
1714 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
1715 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
1716 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
1717 .features
= RTL_FEATURE_MSI
1721 /* Cfg9346_Unlock assumed. */
1722 static unsigned rtl_try_msi(struct pci_dev
*pdev
, void __iomem
*ioaddr
,
1723 const struct rtl_cfg_info
*cfg
)
1728 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
1729 if (cfg
->features
& RTL_FEATURE_MSI
) {
1730 if (pci_enable_msi(pdev
)) {
1731 dev_info(&pdev
->dev
, "no MSI. Back to INTx.\n");
1734 msi
= RTL_FEATURE_MSI
;
1737 RTL_W8(Config2
, cfg2
);
1741 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8101_private
*tp
)
1743 if (tp
->features
& RTL_FEATURE_MSI
) {
1744 pci_disable_msi(pdev
);
1745 tp
->features
&= ~RTL_FEATURE_MSI
;
1749 static int __devinit
1750 rtl8101_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1752 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
1753 const unsigned int region
= cfg
->region
;
1754 struct rtl8101_private
*tp
;
1755 struct mii_if_info
*mii
;
1756 struct net_device
*dev
;
1757 void __iomem
*ioaddr
;
1761 if (netif_msg_drv(&debug
)) {
1762 printk(KERN_INFO
"%s Fast Ethernet driver %s loaded\n",
1763 MODULENAME
, RTL8101_VERSION
);
1766 dev
= alloc_etherdev(sizeof (*tp
));
1768 if (netif_msg_drv(&debug
))
1769 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
1774 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1775 tp
= netdev_priv(dev
);
1778 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8101_MSG_DEFAULT
);
1782 mii
->mdio_read
= rtl_mdio_read
;
1783 mii
->mdio_write
= rtl_mdio_write
;
1784 mii
->phy_id_mask
= 0x1f;
1785 mii
->reg_num_mask
= 0x1f;
1786 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
1788 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1789 rc
= pci_enable_device(pdev
);
1791 if (netif_msg_probe(tp
))
1792 dev_err(&pdev
->dev
, "enable failure\n");
1793 goto err_out_free_dev_1
;
1796 rc
= pci_set_mwi(pdev
);
1798 goto err_out_disable_2
;
1800 /* make sure PCI base addr 1 is MMIO */
1801 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
1802 if (netif_msg_probe(tp
)) {
1804 "region #%d not an MMIO resource, aborting\n",
1811 /* check for weird/broken PCI region reporting */
1812 if (pci_resource_len(pdev
, region
) < R8101_REGS_SIZE
) {
1813 if (netif_msg_probe(tp
)) {
1815 "Invalid PCI region size(s), aborting\n");
1821 rc
= pci_request_regions(pdev
, MODULENAME
);
1823 if (netif_msg_probe(tp
))
1824 dev_err(&pdev
->dev
, "could not request regions.\n");
1828 tp
->cp_cmd
= PCIMulRW
| RxChkSum
;
1830 if ((sizeof(dma_addr_t
) > 4) &&
1831 !pci_set_dma_mask(pdev
, DMA_64BIT_MASK
) && use_dac
) {
1832 tp
->cp_cmd
|= PCIDAC
;
1833 dev
->features
|= NETIF_F_HIGHDMA
;
1835 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
1837 if (netif_msg_probe(tp
)) {
1839 "DMA configuration failed.\n");
1841 goto err_out_free_res_4
;
1845 pci_set_master(pdev
);
1847 /* ioremap MMIO region */
1848 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8101_REGS_SIZE
);
1850 if (netif_msg_probe(tp
))
1851 dev_err(&pdev
->dev
, "cannot remap MMIO, aborting\n");
1853 goto err_out_free_res_4
;
1856 tp
->pcie_cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
1857 if (!tp
->pcie_cap
&& netif_msg_probe(tp
))
1858 dev_info(&pdev
->dev
, "no PCI Express capability\n");
1860 RTL_W16(IntrMask
, 0x0000);
1862 /* Soft reset the chip. */
1863 RTL_W8(ChipCmd
, CmdReset
);
1865 /* Check that the chip has finished the reset. */
1866 for (i
= 0; i
< 100; i
++) {
1867 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
1869 msleep_interruptible(1);
1872 RTL_W16(IntrStatus
, 0xffff);
1874 /* Identify chip attached to board */
1875 rtl8101_get_mac_version(tp
, ioaddr
);
1877 rtl8101_print_mac_version(tp
);
1879 for (i
= 0; i
< ARRAY_SIZE(rtl_chip_info
); i
++) {
1880 if (tp
->mac_version
== rtl_chip_info
[i
].mac_version
)
1883 if (i
== ARRAY_SIZE(rtl_chip_info
)) {
1884 /* Unknown chip: assume array element #0, original RTL-8101 */
1885 if (netif_msg_probe(tp
)) {
1886 dev_printk(KERN_DEBUG
, &pdev
->dev
,
1887 "unknown chip version, assuming %s\n",
1888 rtl_chip_info
[0].name
);
1894 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1895 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
1896 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
1897 tp
->features
|= rtl_try_msi(pdev
, ioaddr
, cfg
);
1898 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1900 if ((tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) &&
1901 (RTL_R8(PHYstatus
) & TBI_Enable
)) {
1902 tp
->set_speed
= rtl8101_set_speed_tbi
;
1903 tp
->get_settings
= rtl8101_gset_tbi
;
1904 tp
->phy_reset_enable
= rtl8101_tbi_reset_enable
;
1905 tp
->phy_reset_pending
= rtl8101_tbi_reset_pending
;
1906 tp
->link_ok
= rtl8101_tbi_link_ok
;
1908 tp
->phy_1000_ctrl_reg
= ADVERTISE_1000FULL
; /* Implied by TBI */
1910 tp
->set_speed
= rtl8101_set_speed_xmii
;
1911 tp
->get_settings
= rtl8101_gset_xmii
;
1912 tp
->phy_reset_enable
= rtl8101_xmii_reset_enable
;
1913 tp
->phy_reset_pending
= rtl8101_xmii_reset_pending
;
1914 tp
->link_ok
= rtl8101_xmii_link_ok
;
1916 dev
->do_ioctl
= rtl8101_ioctl
;
1919 /* Get MAC address. FIXME: read EEPROM */
1920 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
1921 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
1922 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
1924 dev
->open
= rtl8101_open
;
1925 dev
->hard_start_xmit
= rtl8101_start_xmit
;
1926 dev
->get_stats
= rtl8101_get_stats
;
1927 SET_ETHTOOL_OPS(dev
, &rtl8101_ethtool_ops
);
1928 dev
->stop
= rtl8101_close
;
1929 dev
->tx_timeout
= rtl8101_tx_timeout
;
1930 dev
->set_multicast_list
= rtl_set_rx_mode
;
1931 dev
->watchdog_timeo
= RTL8101_TX_TIMEOUT
;
1932 dev
->irq
= pdev
->irq
;
1933 dev
->base_addr
= (unsigned long) ioaddr
;
1934 dev
->change_mtu
= rtl8101_change_mtu
;
1935 dev
->set_mac_address
= rtl_set_mac_address
;
1937 netif_napi_add(dev
, &tp
->napi
, rtl8101_poll
, R8101_NAPI_WEIGHT
);
1939 #ifdef CONFIG_R8101_VLAN
1940 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
1941 dev
->vlan_rx_register
= rtl8101_vlan_rx_register
;
1944 #ifdef CONFIG_NET_POLL_CONTROLLER
1945 dev
->poll_controller
= rtl8101_netpoll
;
1948 tp
->intr_mask
= 0xffff;
1949 tp
->mmio_addr
= ioaddr
;
1950 tp
->align
= cfg
->align
;
1951 tp
->hw_start
= cfg
->hw_start
;
1952 tp
->intr_event
= cfg
->intr_event
;
1953 tp
->napi_event
= cfg
->napi_event
;
1955 init_timer(&tp
->timer
);
1956 tp
->timer
.data
= (unsigned long) dev
;
1957 tp
->timer
.function
= rtl8101_phy_timer
;
1959 spin_lock_init(&tp
->lock
);
1961 rc
= register_netdev(dev
);
1965 pci_set_drvdata(pdev
, dev
);
1967 if (netif_msg_probe(tp
)) {
1968 u32 xid
= RTL_R32(TxConfig
) & 0x7cf0f8ff;
1970 printk(KERN_INFO
"%s: %s at 0x%lx, "
1971 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1972 "XID %08x IRQ %d\n",
1974 rtl_chip_info
[tp
->chipset
].name
,
1976 dev
->dev_addr
[0], dev
->dev_addr
[1],
1977 dev
->dev_addr
[2], dev
->dev_addr
[3],
1978 dev
->dev_addr
[4], dev
->dev_addr
[5], xid
, dev
->irq
);
1981 rtl8101_init_phy(dev
, tp
);
1987 rtl_disable_msi(pdev
, tp
);
1990 pci_release_regions(pdev
);
1992 pci_clear_mwi(pdev
);
1994 pci_disable_device(pdev
);
2000 static void __devexit
rtl8101_remove_one(struct pci_dev
*pdev
)
2002 struct net_device
*dev
= pci_get_drvdata(pdev
);
2003 struct rtl8101_private
*tp
= netdev_priv(dev
);
2005 flush_scheduled_work();
2007 unregister_netdev(dev
);
2008 rtl_disable_msi(pdev
, tp
);
2009 rtl8101_release_board(pdev
, dev
, tp
->mmio_addr
);
2010 pci_set_drvdata(pdev
, NULL
);
2013 static void rtl8101_set_rxbufsize(struct rtl8101_private
*tp
,
2014 struct net_device
*dev
)
2016 unsigned int mtu
= dev
->mtu
;
2018 tp
->rx_buf_sz
= (mtu
> RX_BUF_SIZE
) ? mtu
+ ETH_HLEN
+ 8 : RX_BUF_SIZE
;
2021 static int rtl8101_open(struct net_device
*dev
)
2023 struct rtl8101_private
*tp
= netdev_priv(dev
);
2024 struct pci_dev
*pdev
= tp
->pci_dev
;
2025 int retval
= -ENOMEM
;
2028 rtl8101_set_rxbufsize(tp
, dev
);
2031 * Rx and Tx desscriptors needs 256 bytes alignment.
2032 * pci_alloc_consistent provides more.
2034 tp
->TxDescArray
= pci_alloc_consistent(pdev
, R8101_TX_RING_BYTES
,
2036 if (!tp
->TxDescArray
)
2039 tp
->RxDescArray
= pci_alloc_consistent(pdev
, R8101_RX_RING_BYTES
,
2041 if (!tp
->RxDescArray
)
2044 retval
= rtl8101_init_ring(dev
);
2048 INIT_DELAYED_WORK(&tp
->task
, NULL
);
2052 retval
= request_irq(dev
->irq
, rtl8101_interrupt
,
2053 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
2056 goto err_release_ring_2
;
2058 napi_enable(&tp
->napi
);
2062 rtl8101_request_timer(dev
);
2064 rtl8101_check_link_status(dev
, tp
, tp
->mmio_addr
);
2069 rtl8101_rx_clear(tp
);
2071 pci_free_consistent(pdev
, R8101_RX_RING_BYTES
, tp
->RxDescArray
,
2074 pci_free_consistent(pdev
, R8101_TX_RING_BYTES
, tp
->TxDescArray
,
2079 static void rtl8101_hw_reset(void __iomem
*ioaddr
)
2081 /* Disable interrupts */
2082 rtl8101_irq_mask_and_ack(ioaddr
);
2084 /* Reset the chipset */
2085 RTL_W8(ChipCmd
, CmdReset
);
2091 static void rtl_set_rx_tx_config_registers(struct rtl8101_private
*tp
)
2093 void __iomem
*ioaddr
= tp
->mmio_addr
;
2094 u32 cfg
= rtl8101_rx_config
;
2096 cfg
|= (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
2097 RTL_W32(RxConfig
, cfg
);
2099 /* Set DMA burst size and Interframe Gap Time */
2100 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
2101 (InterFrameGap
<< TxInterFrameGapShift
));
2104 static void rtl_hw_start(struct net_device
*dev
)
2106 struct rtl8101_private
*tp
= netdev_priv(dev
);
2107 void __iomem
*ioaddr
= tp
->mmio_addr
;
2110 /* Soft reset the chip. */
2111 RTL_W8(ChipCmd
, CmdReset
);
2113 /* Check that the chip has finished the reset. */
2114 for (i
= 0; i
< 100; i
++) {
2115 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
2117 msleep_interruptible(1);
2122 netif_start_queue(dev
);
2126 static void rtl_set_rx_tx_desc_registers(struct rtl8101_private
*tp
,
2127 void __iomem
*ioaddr
)
2130 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2131 * register to be written before TxDescAddrLow to work.
2132 * Switching from MMIO to I/O access fixes the issue as well.
2134 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
2135 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_32BIT_MASK
);
2136 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
2137 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_32BIT_MASK
);
2140 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
2144 cmd
= RTL_R16(CPlusCmd
);
2145 RTL_W16(CPlusCmd
, cmd
);
2149 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
2151 /* Low hurts. Let's disable the filtering. */
2152 RTL_W16(RxMaxSize
, rx_buf_sz
);
2155 static void rtl8101_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
2162 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
2163 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
2164 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
2165 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
2170 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
2171 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
2172 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
2173 RTL_W32(0x7c, p
->val
);
2179 static void rtl_hw_start_8169(struct net_device
*dev
)
2181 struct rtl8101_private
*tp
= netdev_priv(dev
);
2182 void __iomem
*ioaddr
= tp
->mmio_addr
;
2183 struct pci_dev
*pdev
= tp
->pci_dev
;
2185 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
2186 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
2187 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
2190 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2191 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
2192 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2193 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
2194 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
2195 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2197 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2199 rtl_set_rx_max_size(ioaddr
, tp
->rx_buf_sz
);
2201 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
2202 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2203 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
2204 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
2205 rtl_set_rx_tx_config_registers(tp
);
2207 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
2209 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2210 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
2211 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2212 "Bit-3 and bit-14 MUST be 1\n");
2213 tp
->cp_cmd
|= (1 << 14);
2216 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2218 rtl8101_set_magic_reg(ioaddr
, tp
->mac_version
);
2221 * Undocumented corner. Supposedly:
2222 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2224 RTL_W16(IntrMitigate
, 0x0000);
2226 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2228 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) &&
2229 (tp
->mac_version
!= RTL_GIGA_MAC_VER_02
) &&
2230 (tp
->mac_version
!= RTL_GIGA_MAC_VER_03
) &&
2231 (tp
->mac_version
!= RTL_GIGA_MAC_VER_04
)) {
2232 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2233 rtl_set_rx_tx_config_registers(tp
);
2236 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2238 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2241 RTL_W32(RxMissed
, 0);
2243 rtl_set_rx_mode(dev
);
2245 /* no early-rx interrupts */
2246 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
2248 /* Enable all known interrupts by setting the interrupt mask. */
2249 RTL_W16(IntrMask
, tp
->intr_event
);
2252 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
2254 struct net_device
*dev
= pci_get_drvdata(pdev
);
2255 struct rtl8101_private
*tp
= netdev_priv(dev
);
2256 int cap
= tp
->pcie_cap
;
2261 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2262 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
2263 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
2267 static void rtl_csi_access_enable(void __iomem
*ioaddr
)
2271 csi
= rtl_csi_read(ioaddr
, 0x070c) & 0x00ffffff;
2272 rtl_csi_write(ioaddr
, 0x070c, csi
| 0x27000000);
2276 unsigned int offset
;
2281 static void rtl_ephy_init(void __iomem
*ioaddr
, struct ephy_info
*e
, int len
)
2286 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
2287 rtl_ephy_write(ioaddr
, e
->offset
, w
);
2292 static void rtl_hw_start_8168(struct net_device
*dev
)
2294 struct rtl8101_private
*tp
= netdev_priv(dev
);
2295 void __iomem
*ioaddr
= tp
->mmio_addr
;
2296 struct pci_dev
*pdev
= tp
->pci_dev
;
2298 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2300 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2302 rtl_set_rx_max_size(ioaddr
, tp
->rx_buf_sz
);
2304 rtl_set_rx_tx_config_registers(tp
);
2306 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
2308 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2310 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2312 RTL_W16(IntrMitigate
, 0x5151);
2314 /* Work around for RxFIFO overflow. */
2315 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
2316 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
2317 tp
->intr_event
&= ~RxOverflow
;
2320 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2322 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2326 rtl_set_rx_mode(dev
);
2328 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2330 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
2332 RTL_W16(IntrMask
, tp
->intr_event
);
2335 #define R810X_CPCMD_QUIRK_MASK (\
2347 static void rtl_hw_start_8102e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2349 static struct ephy_info e_info_8102e_1
[] = {
2350 { 0x01, 0, 0x6e65 },
2351 { 0x02, 0, 0x091f },
2352 { 0x03, 0, 0xc2f9 },
2353 { 0x06, 0, 0xafb5 },
2354 { 0x07, 0, 0x0e00 },
2355 { 0x19, 0, 0xec80 },
2356 { 0x01, 0, 0x2e65 },
2361 rtl_csi_access_enable(ioaddr
);
2363 RTL_W8(DBG_REG
, FIX_NAK_1
);
2365 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2368 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
2369 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2371 cfg1
= RTL_R8(Config1
);
2372 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
2373 RTL_W8(Config1
, cfg1
& ~LEDS0
);
2375 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
2377 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
2380 static void rtl_hw_start_8102e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2382 rtl_csi_access_enable(ioaddr
);
2384 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2386 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
2387 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2389 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
2392 static void rtl_hw_start_8102e_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2394 rtl_hw_start_8102e_2(ioaddr
, pdev
);
2396 rtl_ephy_write(ioaddr
, 0x03, 0xc2f9);
2399 static void rtl_hw_start_8101(struct net_device
*dev
)
2401 struct rtl8101_private
*tp
= netdev_priv(dev
);
2402 void __iomem
*ioaddr
= tp
->mmio_addr
;
2403 struct pci_dev
*pdev
= tp
->pci_dev
;
2405 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
2406 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
)) {
2407 int cap
= tp
->pcie_cap
;
2410 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
2411 PCI_EXP_DEVCTL_NOSNOOP_EN
);
2415 switch (tp
->mac_version
) {
2416 case RTL_GIGA_MAC_VER_07
:
2417 rtl_hw_start_8102e_1(ioaddr
, pdev
);
2420 case RTL_GIGA_MAC_VER_08
:
2421 rtl_hw_start_8102e_3(ioaddr
, pdev
);
2424 case RTL_GIGA_MAC_VER_09
:
2425 rtl_hw_start_8102e_2(ioaddr
, pdev
);
2429 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2431 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2433 rtl_set_rx_max_size(ioaddr
, tp
->rx_buf_sz
);
2435 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
2437 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2439 RTL_W16(IntrMitigate
, 0x0000);
2441 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2443 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2444 rtl_set_rx_tx_config_registers(tp
);
2446 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2450 rtl_set_rx_mode(dev
);
2452 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2454 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
2456 RTL_W16(IntrMask
, tp
->intr_event
);
2459 static int rtl8101_change_mtu(struct net_device
*dev
, int new_mtu
)
2461 struct rtl8101_private
*tp
= netdev_priv(dev
);
2464 if (new_mtu
< ETH_ZLEN
|| new_mtu
> SafeMtu
)
2469 if (!netif_running(dev
))
2474 rtl8101_set_rxbufsize(tp
, dev
);
2476 ret
= rtl8101_init_ring(dev
);
2480 napi_enable(&tp
->napi
);
2484 rtl8101_request_timer(dev
);
2490 static inline void rtl8101_make_unusable_by_asic(struct RxDesc
*desc
)
2492 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
2493 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
2496 static void rtl8101_free_rx_skb(struct rtl8101_private
*tp
,
2497 struct sk_buff
**sk_buff
, struct RxDesc
*desc
)
2499 struct pci_dev
*pdev
= tp
->pci_dev
;
2501 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), tp
->rx_buf_sz
,
2502 PCI_DMA_FROMDEVICE
);
2503 dev_kfree_skb(*sk_buff
);
2505 rtl8101_make_unusable_by_asic(desc
);
2508 static inline void rtl8101_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
2510 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
2512 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
2515 static inline void rtl8101_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
2518 desc
->addr
= cpu_to_le64(mapping
);
2520 rtl8101_mark_to_asic(desc
, rx_buf_sz
);
2523 static struct sk_buff
*rtl8101_alloc_rx_skb(struct pci_dev
*pdev
,
2524 struct net_device
*dev
,
2525 struct RxDesc
*desc
, int rx_buf_sz
,
2528 struct sk_buff
*skb
;
2532 pad
= align
? align
: NET_IP_ALIGN
;
2534 skb
= netdev_alloc_skb(dev
, rx_buf_sz
+ pad
);
2538 skb_reserve(skb
, align
? ((pad
- 1) & (unsigned long)skb
->data
) : pad
);
2540 mapping
= pci_map_single(pdev
, skb
->data
, rx_buf_sz
,
2541 PCI_DMA_FROMDEVICE
);
2543 rtl8101_map_to_asic(desc
, mapping
, rx_buf_sz
);
2548 rtl8101_make_unusable_by_asic(desc
);
2552 static void rtl8101_rx_clear(struct rtl8101_private
*tp
)
2556 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
2557 if (tp
->Rx_skbuff
[i
]) {
2558 rtl8101_free_rx_skb(tp
, tp
->Rx_skbuff
+ i
,
2559 tp
->RxDescArray
+ i
);
2564 static u32
rtl8101_rx_fill(struct rtl8101_private
*tp
, struct net_device
*dev
,
2569 for (cur
= start
; end
- cur
!= 0; cur
++) {
2570 struct sk_buff
*skb
;
2571 unsigned int i
= cur
% NUM_RX_DESC
;
2573 WARN_ON((s32
)(end
- cur
) < 0);
2575 if (tp
->Rx_skbuff
[i
])
2578 skb
= rtl8101_alloc_rx_skb(tp
->pci_dev
, dev
,
2579 tp
->RxDescArray
+ i
,
2580 tp
->rx_buf_sz
, tp
->align
);
2584 tp
->Rx_skbuff
[i
] = skb
;
2589 static inline void rtl8101_mark_as_last_descriptor(struct RxDesc
*desc
)
2591 desc
->opts1
|= cpu_to_le32(RingEnd
);
2594 static void rtl8101_init_ring_indexes(struct rtl8101_private
*tp
)
2596 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
2599 static int rtl8101_init_ring(struct net_device
*dev
)
2601 struct rtl8101_private
*tp
= netdev_priv(dev
);
2603 rtl8101_init_ring_indexes(tp
);
2605 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
2606 memset(tp
->Rx_skbuff
, 0x0, NUM_RX_DESC
* sizeof(struct sk_buff
*));
2608 if (rtl8101_rx_fill(tp
, dev
, 0, NUM_RX_DESC
) != NUM_RX_DESC
)
2611 rtl8101_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
2616 rtl8101_rx_clear(tp
);
2620 static void rtl8101_unmap_tx_skb(struct pci_dev
*pdev
, struct ring_info
*tx_skb
,
2621 struct TxDesc
*desc
)
2623 unsigned int len
= tx_skb
->len
;
2625 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), len
, PCI_DMA_TODEVICE
);
2632 static void rtl8101_tx_clear(struct rtl8101_private
*tp
)
2636 for (i
= tp
->dirty_tx
; i
< tp
->dirty_tx
+ NUM_TX_DESC
; i
++) {
2637 unsigned int entry
= i
% NUM_TX_DESC
;
2638 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
2639 unsigned int len
= tx_skb
->len
;
2642 struct sk_buff
*skb
= tx_skb
->skb
;
2644 rtl8101_unmap_tx_skb(tp
->pci_dev
, tx_skb
,
2645 tp
->TxDescArray
+ entry
);
2650 tp
->dev
->stats
.tx_dropped
++;
2653 tp
->cur_tx
= tp
->dirty_tx
= 0;
2656 static void rtl8101_schedule_work(struct net_device
*dev
, work_func_t task
)
2658 struct rtl8101_private
*tp
= netdev_priv(dev
);
2660 PREPARE_DELAYED_WORK(&tp
->task
, task
);
2661 schedule_delayed_work(&tp
->task
, 4);
2664 static void rtl8101_wait_for_quiescence(struct net_device
*dev
)
2666 struct rtl8101_private
*tp
= netdev_priv(dev
);
2667 void __iomem
*ioaddr
= tp
->mmio_addr
;
2669 synchronize_irq(dev
->irq
);
2671 /* Wait for any pending NAPI task to complete */
2672 napi_disable(&tp
->napi
);
2674 rtl8101_irq_mask_and_ack(ioaddr
);
2676 tp
->intr_mask
= 0xffff;
2677 RTL_W16(IntrMask
, tp
->intr_event
);
2678 napi_enable(&tp
->napi
);
2681 static void rtl8101_reinit_task(struct work_struct
*work
)
2683 struct rtl8101_private
*tp
=
2684 container_of(work
, struct rtl8101_private
, task
.work
);
2685 struct net_device
*dev
= tp
->dev
;
2690 if (!netif_running(dev
))
2693 rtl8101_wait_for_quiescence(dev
);
2696 ret
= rtl8101_open(dev
);
2697 if (unlikely(ret
< 0)) {
2698 if (net_ratelimit() && netif_msg_drv(tp
)) {
2699 printk(KERN_ERR PFX
"%s: reinit failure (status = %d)."
2700 " Rescheduling.\n", dev
->name
, ret
);
2702 rtl8101_schedule_work(dev
, rtl8101_reinit_task
);
2709 static void rtl8101_reset_task(struct work_struct
*work
)
2711 struct rtl8101_private
*tp
=
2712 container_of(work
, struct rtl8101_private
, task
.work
);
2713 struct net_device
*dev
= tp
->dev
;
2717 if (!netif_running(dev
))
2720 rtl8101_wait_for_quiescence(dev
);
2722 rtl8101_rx_interrupt(dev
, tp
, tp
->mmio_addr
, ~(u32
)0);
2723 rtl8101_tx_clear(tp
);
2725 if (tp
->dirty_rx
== tp
->cur_rx
) {
2726 rtl8101_init_ring_indexes(tp
);
2728 netif_wake_queue(dev
);
2729 rtl8101_check_link_status(dev
, tp
, tp
->mmio_addr
);
2731 if (net_ratelimit() && netif_msg_intr(tp
)) {
2732 printk(KERN_EMERG PFX
"%s: Rx buffers shortage\n",
2735 rtl8101_schedule_work(dev
, rtl8101_reset_task
);
2742 static void rtl8101_tx_timeout(struct net_device
*dev
)
2744 struct rtl8101_private
*tp
= netdev_priv(dev
);
2746 rtl8101_hw_reset(tp
->mmio_addr
);
2748 /* Let's wait a bit while any (async) irq lands on */
2749 rtl8101_schedule_work(dev
, rtl8101_reset_task
);
2752 static int rtl8101_xmit_frags(struct rtl8101_private
*tp
, struct sk_buff
*skb
,
2755 struct skb_shared_info
*info
= skb_shinfo(skb
);
2756 unsigned int cur_frag
, entry
;
2757 struct TxDesc
* uninitialized_var(txd
);
2760 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
2761 skb_frag_t
*frag
= info
->frags
+ cur_frag
;
2766 entry
= (entry
+ 1) % NUM_TX_DESC
;
2768 txd
= tp
->TxDescArray
+ entry
;
2770 addr
= ((void *) page_address(frag
->page
)) + frag
->page_offset
;
2771 mapping
= pci_map_single(tp
->pci_dev
, addr
, len
, PCI_DMA_TODEVICE
);
2773 /* anti gcc 2.95.3 bugware (sic) */
2774 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
2776 txd
->opts1
= cpu_to_le32(status
);
2777 txd
->addr
= cpu_to_le64(mapping
);
2779 tp
->tx_skb
[entry
].len
= len
;
2783 tp
->tx_skb
[entry
].skb
= skb
;
2784 txd
->opts1
|= cpu_to_le32(LastFrag
);
2790 static inline u32
rtl8101_tso_csum(struct sk_buff
*skb
, struct net_device
*dev
)
2792 if (dev
->features
& NETIF_F_TSO
) {
2793 u32 mss
= skb_shinfo(skb
)->gso_size
;
2796 return LargeSend
| ((mss
& MSSMask
) << MSSShift
);
2798 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
2799 const struct iphdr
*ip
= ip_hdr(skb
);
2801 if (ip
->protocol
== IPPROTO_TCP
)
2802 return IPCS
| TCPCS
;
2803 else if (ip
->protocol
== IPPROTO_UDP
)
2804 return IPCS
| UDPCS
;
2805 WARN_ON(1); /* we need a WARN() */
2810 static int rtl8101_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2812 struct rtl8101_private
*tp
= netdev_priv(dev
);
2813 unsigned int frags
, entry
= tp
->cur_tx
% NUM_TX_DESC
;
2814 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
2815 void __iomem
*ioaddr
= tp
->mmio_addr
;
2819 int ret
= NETDEV_TX_OK
;
2821 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
2822 if (netif_msg_drv(tp
)) {
2824 "%s: BUG! Tx Ring full when queue awake!\n",
2830 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
2833 opts1
= DescOwn
| rtl8101_tso_csum(skb
, dev
);
2835 frags
= rtl8101_xmit_frags(tp
, skb
, opts1
);
2837 len
= skb_headlen(skb
);
2841 opts1
|= FirstFrag
| LastFrag
;
2842 tp
->tx_skb
[entry
].skb
= skb
;
2845 mapping
= pci_map_single(tp
->pci_dev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
2847 tp
->tx_skb
[entry
].len
= len
;
2848 txd
->addr
= cpu_to_le64(mapping
);
2849 txd
->opts2
= cpu_to_le32(rtl8101_tx_vlan_tag(tp
, skb
));
2853 /* anti gcc 2.95.3 bugware (sic) */
2854 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
2855 txd
->opts1
= cpu_to_le32(status
);
2857 dev
->trans_start
= jiffies
;
2859 tp
->cur_tx
+= frags
+ 1;
2863 RTL_W8(TxPoll
, NPQ
); /* set polling bit */
2865 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
2866 netif_stop_queue(dev
);
2868 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
2869 netif_wake_queue(dev
);
2876 netif_stop_queue(dev
);
2877 ret
= NETDEV_TX_BUSY
;
2878 dev
->stats
.tx_dropped
++;
2882 static void rtl8101_pcierr_interrupt(struct net_device
*dev
)
2884 struct rtl8101_private
*tp
= netdev_priv(dev
);
2885 struct pci_dev
*pdev
= tp
->pci_dev
;
2886 void __iomem
*ioaddr
= tp
->mmio_addr
;
2887 u16 pci_status
, pci_cmd
;
2889 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
2890 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
2892 if (netif_msg_intr(tp
)) {
2894 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2895 dev
->name
, pci_cmd
, pci_status
);
2899 * The recovery sequence below admits a very elaborated explanation:
2900 * - it seems to work;
2901 * - I did not see what else could be done;
2902 * - it makes iop3xx happy.
2904 * Feel free to adjust to your needs.
2906 if (pdev
->broken_parity_status
)
2907 pci_cmd
&= ~PCI_COMMAND_PARITY
;
2909 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
2911 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
2913 pci_write_config_word(pdev
, PCI_STATUS
,
2914 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
2915 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
2916 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
2918 /* The infamous DAC f*ckup only happens at boot time */
2919 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
2920 if (netif_msg_intr(tp
))
2921 printk(KERN_INFO
"%s: disabling PCI DAC.\n", dev
->name
);
2922 tp
->cp_cmd
&= ~PCIDAC
;
2923 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2924 dev
->features
&= ~NETIF_F_HIGHDMA
;
2927 rtl8101_hw_reset(ioaddr
);
2929 rtl8101_schedule_work(dev
, rtl8101_reinit_task
);
2932 static void rtl8101_tx_interrupt(struct net_device
*dev
,
2933 struct rtl8101_private
*tp
,
2934 void __iomem
*ioaddr
)
2936 unsigned int dirty_tx
, tx_left
;
2938 dirty_tx
= tp
->dirty_tx
;
2940 tx_left
= tp
->cur_tx
- dirty_tx
;
2942 while (tx_left
> 0) {
2943 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
2944 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
2945 u32 len
= tx_skb
->len
;
2949 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
2950 if (status
& DescOwn
)
2953 dev
->stats
.tx_bytes
+= len
;
2954 dev
->stats
.tx_packets
++;
2956 rtl8101_unmap_tx_skb(tp
->pci_dev
, tx_skb
, tp
->TxDescArray
+ entry
);
2958 if (status
& LastFrag
) {
2959 dev_kfree_skb_irq(tx_skb
->skb
);
2966 if (tp
->dirty_tx
!= dirty_tx
) {
2967 tp
->dirty_tx
= dirty_tx
;
2969 if (netif_queue_stopped(dev
) &&
2970 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
2971 netif_wake_queue(dev
);
2974 * 8168 hack: TxPoll requests are lost when the Tx packets are
2975 * too close. Let's kick an extra TxPoll request when a burst
2976 * of start_xmit activity is detected (if it is not detected,
2977 * it is slow enough). -- FR
2980 if (tp
->cur_tx
!= dirty_tx
)
2981 RTL_W8(TxPoll
, NPQ
);
2985 static inline int rtl8101_fragmented_frame(u32 status
)
2987 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
2990 static inline void rtl8101_rx_csum(struct sk_buff
*skb
, struct RxDesc
*desc
)
2992 u32 opts1
= le32_to_cpu(desc
->opts1
);
2993 u32 status
= opts1
& RxProtoMask
;
2995 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
2996 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)) ||
2997 ((status
== RxProtoIP
) && !(opts1
& IPFail
)))
2998 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
3000 skb
->ip_summed
= CHECKSUM_NONE
;
3003 static inline bool rtl8101_try_rx_copy(struct sk_buff
**sk_buff
,
3004 struct rtl8101_private
*tp
, int pkt_size
,
3007 struct sk_buff
*skb
;
3010 if (pkt_size
>= rx_copybreak
)
3013 skb
= netdev_alloc_skb(tp
->dev
, pkt_size
+ NET_IP_ALIGN
);
3017 pci_dma_sync_single_for_cpu(tp
->pci_dev
, addr
, pkt_size
,
3018 PCI_DMA_FROMDEVICE
);
3019 skb_reserve(skb
, NET_IP_ALIGN
);
3020 skb_copy_from_linear_data(*sk_buff
, skb
->data
, pkt_size
);
3027 static int rtl8101_rx_interrupt(struct net_device
*dev
,
3028 struct rtl8101_private
*tp
,
3029 void __iomem
*ioaddr
, u32 budget
)
3031 unsigned int cur_rx
, rx_left
;
3032 unsigned int delta
, count
;
3034 cur_rx
= tp
->cur_rx
;
3035 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
3036 rx_left
= min(rx_left
, budget
);
3038 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
3039 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
3040 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
3044 status
= le32_to_cpu(desc
->opts1
);
3046 if (status
& DescOwn
)
3048 if (unlikely(status
& RxRES
)) {
3049 if (netif_msg_rx_err(tp
)) {
3051 "%s: Rx ERROR. status = %08x\n",
3054 dev
->stats
.rx_errors
++;
3055 if (status
& (RxRWT
| RxRUNT
))
3056 dev
->stats
.rx_length_errors
++;
3058 dev
->stats
.rx_crc_errors
++;
3059 if (status
& RxFOVF
) {
3060 rtl8101_schedule_work(dev
, rtl8101_reset_task
);
3061 dev
->stats
.rx_fifo_errors
++;
3063 rtl8101_mark_to_asic(desc
, tp
->rx_buf_sz
);
3065 struct sk_buff
*skb
= tp
->Rx_skbuff
[entry
];
3066 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
3067 int pkt_size
= (status
& 0x00001FFF) - 4;
3068 struct pci_dev
*pdev
= tp
->pci_dev
;
3071 * The driver does not support incoming fragmented
3072 * frames. They are seen as a symptom of over-mtu
3075 if (unlikely(rtl8101_fragmented_frame(status
))) {
3076 dev
->stats
.rx_dropped
++;
3077 dev
->stats
.rx_length_errors
++;
3078 rtl8101_mark_to_asic(desc
, tp
->rx_buf_sz
);
3082 rtl8101_rx_csum(skb
, desc
);
3084 if (rtl8101_try_rx_copy(&skb
, tp
, pkt_size
, addr
)) {
3085 pci_dma_sync_single_for_device(pdev
, addr
,
3086 pkt_size
, PCI_DMA_FROMDEVICE
);
3087 rtl8101_mark_to_asic(desc
, tp
->rx_buf_sz
);
3089 pci_unmap_single(pdev
, addr
, tp
->rx_buf_sz
,
3090 PCI_DMA_FROMDEVICE
);
3091 tp
->Rx_skbuff
[entry
] = NULL
;
3094 skb_put(skb
, pkt_size
);
3095 skb
->protocol
= eth_type_trans(skb
, dev
);
3097 if (rtl8101_rx_vlan_skb(tp
, desc
, skb
) < 0)
3098 netif_receive_skb(skb
);
3100 dev
->last_rx
= jiffies
;
3101 dev
->stats
.rx_bytes
+= pkt_size
;
3102 dev
->stats
.rx_packets
++;
3105 /* Work around for AMD plateform. */
3106 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
3107 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
3113 count
= cur_rx
- tp
->cur_rx
;
3114 tp
->cur_rx
= cur_rx
;
3116 delta
= rtl8101_rx_fill(tp
, dev
, tp
->dirty_rx
, tp
->cur_rx
);
3117 if (!delta
&& count
&& netif_msg_intr(tp
))
3118 printk(KERN_INFO
"%s: no Rx buffer allocated\n", dev
->name
);
3119 tp
->dirty_rx
+= delta
;
3122 * FIXME: until there is periodic timer to try and refill the ring,
3123 * a temporary shortage may definitely kill the Rx process.
3124 * - disable the asic to try and avoid an overflow and kick it again
3126 * - how do others driver handle this condition (Uh oh...).
3128 if ((tp
->dirty_rx
+ NUM_RX_DESC
== tp
->cur_rx
) && netif_msg_intr(tp
))
3129 printk(KERN_EMERG
"%s: Rx buffers exhausted\n", dev
->name
);
3134 static irqreturn_t
rtl8101_interrupt(int irq
, void *dev_instance
)
3136 struct net_device
*dev
= dev_instance
;
3137 struct rtl8101_private
*tp
= netdev_priv(dev
);
3138 void __iomem
*ioaddr
= tp
->mmio_addr
;
3142 /* loop handling interrupts until we have no new ones or
3143 * we hit a invalid/hotplug case.
3145 status
= RTL_R16(IntrStatus
);
3146 while (status
&& status
!= 0xffff) {
3149 /* Handle all of the error cases first. These will reset
3150 * the chip, so just exit the loop.
3152 if (unlikely(!netif_running(dev
))) {
3153 rtl8101_asic_down(ioaddr
);
3157 /* Work around for rx fifo overflow */
3158 if (unlikely(status
& RxFIFOOver
) &&
3159 (tp
->mac_version
== RTL_GIGA_MAC_VER_11
)) {
3160 netif_stop_queue(dev
);
3161 rtl8101_tx_timeout(dev
);
3165 if (unlikely(status
& SYSErr
)) {
3166 rtl8101_pcierr_interrupt(dev
);
3170 if (status
& LinkChg
)
3171 rtl8101_check_link_status(dev
, tp
, ioaddr
);
3173 /* We need to see the lastest version of tp->intr_mask to
3174 * avoid ignoring an MSI interrupt and having to wait for
3175 * another event which may never come.
3178 if (status
& tp
->intr_mask
& tp
->napi_event
) {
3179 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
3180 tp
->intr_mask
= ~tp
->napi_event
;
3182 if (likely(napi_schedule_prep(&tp
->napi
)))
3183 __napi_schedule(&tp
->napi
);
3184 else if (netif_msg_intr(tp
)) {
3185 printk(KERN_INFO
"%s: interrupt %04x in poll\n",
3190 /* We only get a new MSI interrupt when all active irq
3191 * sources on the chip have been acknowledged. So, ack
3192 * everything we've seen and check if new sources have become
3193 * active to avoid blocking all interrupts from the chip.
3196 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
3197 status
= RTL_R16(IntrStatus
);
3200 return IRQ_RETVAL(handled
);
3203 static int rtl8101_poll(struct napi_struct
*napi
, int budget
)
3205 struct rtl8101_private
*tp
= container_of(napi
, struct rtl8101_private
, napi
);
3206 struct net_device
*dev
= tp
->dev
;
3207 void __iomem
*ioaddr
= tp
->mmio_addr
;
3210 work_done
= rtl8101_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
3211 rtl8101_tx_interrupt(dev
, tp
, ioaddr
);
3213 if (work_done
< budget
) {
3214 netif_rx_complete(dev
, napi
);
3216 /* We need for force the visibility of tp->intr_mask
3217 * for other CPUs, as we can loose an MSI interrupt
3218 * and potentially wait for a retransmit timeout if we don't.
3219 * The posted write to IntrMask is safe, as it will
3220 * eventually make it to the chip and we won't loose anything
3223 tp
->intr_mask
= 0xffff;
3225 RTL_W16(IntrMask
, tp
->intr_event
);
3231 static void rtl8101_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
3233 struct rtl8101_private
*tp
= netdev_priv(dev
);
3235 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
3238 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
3239 RTL_W32(RxMissed
, 0);
3242 static void rtl8101_down(struct net_device
*dev
)
3244 struct rtl8101_private
*tp
= netdev_priv(dev
);
3245 void __iomem
*ioaddr
= tp
->mmio_addr
;
3246 unsigned int intrmask
;
3248 rtl8101_delete_timer(dev
);
3250 netif_stop_queue(dev
);
3252 napi_disable(&tp
->napi
);
3255 spin_lock_irq(&tp
->lock
);
3257 rtl8101_asic_down(ioaddr
);
3259 rtl8101_rx_missed(dev
, ioaddr
);
3261 spin_unlock_irq(&tp
->lock
);
3263 synchronize_irq(dev
->irq
);
3265 /* Give a racing hard_start_xmit a few cycles to complete. */
3266 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
3269 * And now for the 50k$ question: are IRQ disabled or not ?
3271 * Two paths lead here:
3273 * -> netif_running() is available to sync the current code and the
3274 * IRQ handler. See rtl8101_interrupt for details.
3275 * 2) dev->change_mtu
3276 * -> rtl8101_poll can not be issued again and re-enable the
3277 * interruptions. Let's simply issue the IRQ down sequence again.
3279 * No loop if hotpluged or major error (0xffff).
3281 intrmask
= RTL_R16(IntrMask
);
3282 if (intrmask
&& (intrmask
!= 0xffff))
3285 rtl8101_tx_clear(tp
);
3287 rtl8101_rx_clear(tp
);
3290 static int rtl8101_close(struct net_device
*dev
)
3292 struct rtl8101_private
*tp
= netdev_priv(dev
);
3293 struct pci_dev
*pdev
= tp
->pci_dev
;
3295 /* update counters before going down */
3296 rtl8101_update_counters(dev
);
3300 free_irq(dev
->irq
, dev
);
3302 pci_free_consistent(pdev
, R8101_RX_RING_BYTES
, tp
->RxDescArray
,
3304 pci_free_consistent(pdev
, R8101_TX_RING_BYTES
, tp
->TxDescArray
,
3306 tp
->TxDescArray
= NULL
;
3307 tp
->RxDescArray
= NULL
;
3312 static void rtl_set_rx_mode(struct net_device
*dev
)
3314 struct rtl8101_private
*tp
= netdev_priv(dev
);
3315 void __iomem
*ioaddr
= tp
->mmio_addr
;
3316 unsigned long flags
;
3317 u32 mc_filter
[2]; /* Multicast hash filter */
3321 if (dev
->flags
& IFF_PROMISC
) {
3322 /* Unconditionally log net taps. */
3323 if (netif_msg_link(tp
)) {
3324 printk(KERN_NOTICE
"%s: Promiscuous mode enabled.\n",
3328 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
3330 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
3331 } else if ((dev
->mc_count
> multicast_filter_limit
)
3332 || (dev
->flags
& IFF_ALLMULTI
)) {
3333 /* Too many to filter perfectly -- accept all multicasts. */
3334 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
3335 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
3337 struct dev_mc_list
*mclist
;
3340 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
3341 mc_filter
[1] = mc_filter
[0] = 0;
3342 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
3343 i
++, mclist
= mclist
->next
) {
3344 int bit_nr
= ether_crc(ETH_ALEN
, mclist
->dmi_addr
) >> 26;
3345 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
3346 rx_mode
|= AcceptMulticast
;
3350 spin_lock_irqsave(&tp
->lock
, flags
);
3352 tmp
= rtl8101_rx_config
| rx_mode
|
3353 (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
3355 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
3356 u32 data
= mc_filter
[0];
3358 mc_filter
[0] = swab32(mc_filter
[1]);
3359 mc_filter
[1] = swab32(data
);
3362 RTL_W32(MAR0
+ 0, mc_filter
[0]);
3363 RTL_W32(MAR0
+ 4, mc_filter
[1]);
3365 RTL_W32(RxConfig
, tmp
);
3367 spin_unlock_irqrestore(&tp
->lock
, flags
);
3371 * rtl8101_get_stats - Get rtl8101 read/write statistics
3372 * @dev: The Ethernet Device to get statistics for
3374 * Get TX/RX statistics for rtl8101
3376 static struct net_device_stats
*rtl8101_get_stats(struct net_device
*dev
)
3378 struct rtl8101_private
*tp
= netdev_priv(dev
);
3379 void __iomem
*ioaddr
= tp
->mmio_addr
;
3380 unsigned long flags
;
3382 if (netif_running(dev
)) {
3383 spin_lock_irqsave(&tp
->lock
, flags
);
3384 rtl8101_rx_missed(dev
, ioaddr
);
3385 spin_unlock_irqrestore(&tp
->lock
, flags
);
3393 static int rtl8101_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3395 struct net_device
*dev
= pci_get_drvdata(pdev
);
3396 struct rtl8101_private
*tp
= netdev_priv(dev
);
3397 void __iomem
*ioaddr
= tp
->mmio_addr
;
3399 if (!netif_running(dev
))
3400 goto out_pci_suspend
;
3402 netif_device_detach(dev
);
3403 netif_stop_queue(dev
);
3405 spin_lock_irq(&tp
->lock
);
3407 rtl8101_asic_down(ioaddr
);
3409 rtl8101_rx_missed(dev
, ioaddr
);
3411 spin_unlock_irq(&tp
->lock
);
3414 pci_save_state(pdev
);
3415 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
),
3416 (tp
->features
& RTL_FEATURE_WOL
) ? 1 : 0);
3417 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
3422 static int rtl8101_resume(struct pci_dev
*pdev
)
3424 struct net_device
*dev
= pci_get_drvdata(pdev
);
3426 pci_set_power_state(pdev
, PCI_D0
);
3427 pci_restore_state(pdev
);
3428 pci_enable_wake(pdev
, PCI_D0
, 0);
3430 if (!netif_running(dev
))
3433 netif_device_attach(dev
);
3435 rtl8101_schedule_work(dev
, rtl8101_reset_task
);
3440 #endif /* CONFIG_PM */
3442 static struct pci_driver rtl8101_pci_driver
= {
3444 .id_table
= rtl8101_pci_tbl
,
3445 .probe
= rtl8101_init_one
,
3446 .remove
= __devexit_p(rtl8101_remove_one
),
3448 .suspend
= rtl8101_suspend
,
3449 .resume
= rtl8101_resume
,
3453 static int __init
rtl8101_init_module(void)
3455 return pci_register_driver(&rtl8101_pci_driver
);
3458 static void __exit
rtl8101_cleanup_module(void)
3460 pci_unregister_driver(&rtl8101_pci_driver
);
3463 module_init(rtl8101_init_module
);
3464 module_exit(rtl8101_cleanup_module
);