From: Alok Kataria Subject: x86: add a synthetic TSC_RELIABLE feature bit Patch-mainline: References: bnc#441338 Impact: None, bit reservation only Add a synthetic TSC_RELIABLE feature bit which will be used to mark TSC as reliable so that we could skip all the runtime checks for TSC stablity, which have false positives in virtual environment. Signed-off-by: Alok N Kataria Signed-off-by: Dan Hecht Signed-off-by: H. Peter Anvin Signed-off-by: Takashi Iwai --- include/asm-x86/cpufeature.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) Index: linux-2.6.27.4-2-beta4/include/asm-x86/cpufeature.h =================================================================== --- linux-2.6.27.4-2-beta4.orig/include/asm-x86/cpufeature.h 2008-10-28 16:32:43.000000000 -0700 +++ linux-2.6.27.4-2-beta4/include/asm-x86/cpufeature.h 2008-11-10 12:41:49.000000000 -0800 @@ -83,7 +83,7 @@ #define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */ #define X86_FEATURE_AMDC1E (3*32+21) /* AMD C1E detected */ #define X86_FEATURE_XTOPOLOGY (3*32+22) /* cpu topology enum extensions */ - +#define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */ /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */