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Merge branch 'ppp-update' into beyond-next
[people/teissler/ipfire-2.x.git] / src / patches / binutils-2.22-pt-pax-flags-20111121.patch
CommitLineData
2fce30e6
AF		 1--- binutils-2.22/bfd/elf-bfd.h
2+++ binutils-2.22/bfd/elf-bfd.h
3@@ -1577,6 +1577,9 @@ struct elf_obj_tdata
4 /* Segment flags for the PT_GNU_STACK segment. */
5 unsigned int stack_flags;
6
7+ /* Segment flags for the PT_PAX_FLAGS segment. */
8+ unsigned int pax_flags;
9+
10 /* Symbol version definitions in external objects. */
11 Elf_Internal_Verdef *verdef;
12
13--- binutils-2.22/bfd/elf.c
14+++ binutils-2.22/bfd/elf.c
15@@ -1158,6 +1158,7 @@ get_segment_type (unsigned int p_type)
16 case PT_GNU_EH_FRAME: pt = "EH_FRAME"; break;
17 case PT_GNU_STACK: pt = "STACK"; break;
18 case PT_GNU_RELRO: pt = "RELRO"; break;
19+ case PT_PAX_FLAGS: pt = "PAX_FLAGS"; break;
20 default: pt = NULL; break;
21 }
22 return pt;
23@@ -2477,6 +2478,9 @@ bfd_section_from_phdr (bfd *abfd, Elf_Internal_Phdr *hdr, int hdr_index)
24 case PT_GNU_RELRO:
25 return _bfd_elf_make_section_from_phdr (abfd, hdr, hdr_index, "relro");
26
27+ case PT_PAX_FLAGS:
28+ return _bfd_elf_make_section_from_phdr (abfd, hdr, hdr_index, "pax_flags");
29+
30 default:
31 /* Check for any processor-specific program segment types. */
32 bed = get_elf_backend_data (abfd);
33@@ -3551,6 +3555,11 @@ get_program_header_size (bfd *abfd, struct bfd_link_info *info)
34 ++segs;
35 }
36
37+ {
38+ /* We need a PT_PAX_FLAGS segment. */
39+ ++segs;
40+ }
41+
42 for (s = abfd->sections; s != NULL; s = s->next)
43 {
44 if ((s->flags & SEC_LOAD) != 0
45@@ -4153,6 +4162,20 @@ _bfd_elf_map_sections_to_segments (bfd *abfd, struct bfd_link_info *info)
46 }
47 }
48
49+ {
50+ amt = sizeof (struct elf_segment_map);
51+ m = bfd_zalloc (abfd, amt);
52+ if (m == NULL)
53+ goto error_return;
54+ m->next = NULL;
55+ m->p_type = PT_PAX_FLAGS;
56+ m->p_flags = elf_tdata (abfd)->pax_flags;
57+ m->p_flags_valid = 1;
58+
59+ *pm = m;
60+ pm = &m->next;
61+ }
62+
63 free (sections);
64 elf_tdata (abfd)->segment_map = mfirst;
65 }
66@@ -5417,7 +5440,8 @@ rewrite_elf_program_header (bfd *ibfd, bfd *obfd)
67 6. PT_TLS segment includes only SHF_TLS sections.
68 7. SHF_TLS sections are only in PT_TLS or PT_LOAD segments.
69 8. PT_DYNAMIC should not contain empty sections at the beginning
70- (with the possible exception of .dynamic). */
71+ (with the possible exception of .dynamic).
72+ 9. PT_PAX_FLAGS segments do not include any sections. */
73 #define IS_SECTION_IN_INPUT_SEGMENT(section, segment, bed) \
74 ((((segment->p_paddr \
75 ? IS_CONTAINED_BY_LMA (section, segment, segment->p_paddr) \
76@@ -5425,6 +5449,7 @@ rewrite_elf_program_header (bfd *ibfd, bfd *obfd)
77 && (section->flags & SEC_ALLOC) != 0) \
78 || IS_NOTE (segment, section)) \
79 && segment->p_type != PT_GNU_STACK \
80+ && segment->p_type != PT_PAX_FLAGS \
81 && (segment->p_type != PT_TLS \
82 || (section->flags & SEC_THREAD_LOCAL)) \
83 && (segment->p_type == PT_LOAD \
84--- binutils-2.22/bfd/elflink.c
85+++ binutils-2.22/bfd/elflink.c
86@@ -5545,16 +5545,30 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
87 return TRUE;
88
89 bed = get_elf_backend_data (output_bfd);
90+
91+ elf_tdata (output_bfd)->pax_flags = PF_NORANDEXEC;
92+ if (info->execheap)
93+ elf_tdata (output_bfd)->pax_flags |= PF_NOMPROTECT;
94+ else if (info->noexecheap)
95+ elf_tdata (output_bfd)->pax_flags |= PF_MPROTECT;
96+
97 if (info->execstack)
98- elf_tdata (output_bfd)->stack_flags = PF_R | PF_W | PF_X;
99+ {
100+ elf_tdata (output_bfd)->stack_flags = PF_R | PF_W | PF_X;
101+ elf_tdata (output_bfd)->pax_flags |= PF_EMUTRAMP;
102+ }
103 else if (info->noexecstack)
104- elf_tdata (output_bfd)->stack_flags = PF_R | PF_W;
105+ {
106+ elf_tdata (output_bfd)->stack_flags = PF_R | PF_W;
107+ elf_tdata (output_bfd)->pax_flags |= PF_NOEMUTRAMP;
108+ }
109 else
110 {
111 bfd *inputobj;
112 asection *notesec = NULL;
113 int exec = 0;
114
115+ elf_tdata (output_bfd)->pax_flags |= PF_NOEMUTRAMP;
116 for (inputobj = info->input_bfds;
117 inputobj;
118 inputobj = inputobj->link_next)
119@@ -5567,7 +5581,11 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
120 if (s)
121 {
122 if (s->flags & SEC_CODE)
123- exec = PF_X;
124+ {
125+ elf_tdata (output_bfd)->pax_flags &= ~PF_NOEMUTRAMP;
126+ elf_tdata (output_bfd)->pax_flags |= PF_EMUTRAMP;
127+ exec = PF_X;
128+ }
129 notesec = s;
130 }
131 else if (bed->default_execstack)
132--- binutils-2.22/binutils/readelf.c
133+++ binutils-2.22/binutils/readelf.c
134@@ -2740,6 +2740,7 @@ get_segment_type (unsigned long p_type)
135 return "GNU_EH_FRAME";
136 case PT_GNU_STACK: return "GNU_STACK";
137 case PT_GNU_RELRO: return "GNU_RELRO";
138+ case PT_PAX_FLAGS: return "PAX_FLAGS";
139
140 default:
141 if ((p_type >= PT_LOPROC) && (p_type <= PT_HIPROC))
142--- binutils-2.22/include/bfdlink.h
143+++ binutils-2.22/include/bfdlink.h
144@@ -322,6 +322,14 @@ struct bfd_link_info
145 /* TRUE if PT_GNU_RELRO segment should be created. */
146 unsigned int relro: 1;
147
148+ /* TRUE if PT_PAX_FLAGS segment should be created with PF_NOMPROTECT
149+ flags. */
150+ unsigned int execheap: 1;
151+
152+ /* TRUE if PT_PAX_FLAGS segment should be created with PF_MPROTECT
153+ flags. */
154+ unsigned int noexecheap: 1;
155+
156 /* TRUE if .eh_frame_hdr section and PT_GNU_EH_FRAME ELF segment
157 should be created. */
158 unsigned int eh_frame_hdr: 1;
159--- binutils-2.22/include/elf/common.h
160+++ binutils-2.22/include/elf/common.h
161@@ -429,6 +429,7 @@
162 #define PT_SUNW_EH_FRAME PT_GNU_EH_FRAME /* Solaris uses the same value */
163 #define PT_GNU_STACK (PT_LOOS + 0x474e551) /* Stack flags */
164 #define PT_GNU_RELRO (PT_LOOS + 0x474e552) /* Read-only after relocation */
165+#define PT_PAX_FLAGS (PT_LOOS + 0x5041580) /* PaX flags */
166
167 /* Program segment permissions, in program header p_flags field. */
168
169@@ -439,6 +440,21 @@
170 #define PF_MASKOS 0x0FF00000 /* New value, Oct 4, 1999 Draft */
171 #define PF_MASKPROC 0xF0000000 /* Processor-specific reserved bits */
172
173+/* Flags to control PaX behavior. */
174+
175+#define PF_PAGEEXEC (1 << 4) /* Enable PAGEEXEC */
176+#define PF_NOPAGEEXEC (1 << 5) /* Disable PAGEEXEC */
177+#define PF_SEGMEXEC (1 << 6) /* Enable SEGMEXEC */
178+#define PF_NOSEGMEXEC (1 << 7) /* Disable SEGMEXEC */
179+#define PF_MPROTECT (1 << 8) /* Enable MPROTECT */
180+#define PF_NOMPROTECT (1 << 9) /* Disable MPROTECT */
181+#define PF_RANDEXEC (1 << 10) /* Enable RANDEXEC */
182+#define PF_NORANDEXEC (1 << 11) /* Disable RANDEXEC */
183+#define PF_EMUTRAMP (1 << 12) /* Enable EMUTRAMP */
184+#define PF_NOEMUTRAMP (1 << 13) /* Disable EMUTRAMP */
185+#define PF_RANDMMAP (1 << 14) /* Enable RANDMMAP */
186+#define PF_NORANDMMAP (1 << 15) /* Disable RANDMMAP */
187+
188 /* Values for section header, sh_type field. */
189
190 #define SHT_NULL 0 /* Section header table entry unused */
191--- binutils-2.22/ld/emultempl/elf32.em
192+++ binutils-2.22/ld/emultempl/elf32.em
193@@ -2285,6 +2285,16 @@ fragment <<EOF
194 link_info.noexecstack = TRUE;
195 link_info.execstack = FALSE;
196 }
197+ else if (strcmp (optarg, "execheap") == 0)
198+ {
199+ link_info.execheap = TRUE;
200+ link_info.noexecheap = FALSE;
201+ }
202+ else if (strcmp (optarg, "noexecheap") == 0)
203+ {
204+ link_info.noexecheap = TRUE;
205+ link_info.execheap = FALSE;
206+ }
207 EOF
208 if test x"$GENERATE_SHLIB_SCRIPT" = xyes; then
209 fragment <<EOF
210@@ -2368,6 +2378,8 @@ fragment <<EOF
211 -z defs Report unresolved symbols in object files.\n"));
212 fprintf (file, _("\
213 -z execstack Mark executable as requiring executable stack\n"));
214+ fprintf (file, _("\
215+ -z execheap Mark executable as requiring executable heap\n"));
216 EOF
217
218 if test x"$GENERATE_SHLIB_SCRIPT" = xyes; then
219@@ -2391,6 +2403,8 @@ fragment <<EOF
220 fragment <<EOF
221 fprintf (file, _("\
222 -z noexecstack Mark executable as not requiring executable stack\n"));
223+ fprintf (file, _("\
224+ -z noexecheap Mark executable as not requiring executable heap\n"));
225 EOF
226 if test x"$GENERATE_SHLIB_SCRIPT" = xyes; then
227 fragment <<EOF
228--- binutils-2.22/ld/ldgram.y
229+++ binutils-2.22/ld/ldgram.y
230@@ -1119,6 +1119,8 @@ phdr_type:
231 $$ = exp_intop (0x6474e550);
232 else if (strcmp (s, "PT_GNU_STACK") == 0)
233 $$ = exp_intop (0x6474e551);
234+ else if (strcmp (s, "PT_PAX_FLAGS") == 0)
235+ $$ = exp_intop (0x65041580);
236 else
237 {
238 einfo (_("\
239--- binutils-2.22/ld/testsuite/ld-alpha/tlsbin.rd
240+++ binutils-2.22/ld/testsuite/ld-alpha/tlsbin.rd
241@@ -35,13 +35,14 @@ There are [0-9]+ program headers, starting at offset [0-9]+
242
243 Program Headers:
244 Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
245- PHDR +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x0+150 R E 0x8
246+ PHDR +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x0+188 R E 0x8
247 INTERP +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ R +0x1
248 .*Requesting program interpreter.*
249 LOAD +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ R E 0x10000
250 LOAD +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RWE 0x10000
251 DYNAMIC +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RW +0x8
252 TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ R +0x4
253+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
254 #...
255
256 Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 3 entries:
257--- binutils-2.22/ld/testsuite/ld-alpha/tlsbinr.rd
258+++ binutils-2.22/ld/testsuite/ld-alpha/tlsbinr.rd
259@@ -42,6 +42,7 @@ Program Headers:
260 +LOAD +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RWE 0x10000
261 +DYNAMIC +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RW +0x8
262 +TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ R +0x4
263+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
264 #...
265
266 Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 2 entries:
267--- binutils-2.22/ld/testsuite/ld-alpha/tlspic.rd
268+++ binutils-2.22/ld/testsuite/ld-alpha/tlspic.rd
269@@ -38,6 +38,7 @@ Program Headers:
270 +LOAD +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RWE 0x10000
271 +DYNAMIC +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RW +0x8
272 +TLS +0x0+10e0 0x0+110e0 0x0+110e0 0x0+60 0x0+80 R +0x4
273+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
274 #...
275
276 Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 7 entries:
277--- binutils-2.22/ld/testsuite/ld-elf/eh1.d
278+++ binutils-2.22/ld/testsuite/ld-elf/eh1.d
279@@ -22,11 +22,11 @@ Contents of the .eh_frame section:
280 DW_CFA_nop
281 DW_CFA_nop
282
283-00000018 0000001c 0000001c FDE cie=00000000 pc=00400078..00400078
284- DW_CFA_advance_loc: 0 to 00400078
285+00000018 0000001c 0000001c FDE cie=00000000 pc=([0-9a-f]+)..\1
286+ DW_CFA_advance_loc: 0 to [0-9a-f]+
287 DW_CFA_def_cfa_offset: 16
288 DW_CFA_offset: r6 \(rbp\) at cfa-16
289- DW_CFA_advance_loc: 0 to 00400078
290+ DW_CFA_advance_loc: 0 to [0-9a-f]+
291 DW_CFA_def_cfa_register: r6 \(rbp\)
292
293 00000038 ZERO terminator
294--- binutils-2.22/ld/testsuite/ld-elf/eh2.d
295+++ binutils-2.22/ld/testsuite/ld-elf/eh2.d
296@@ -22,11 +22,11 @@ Contents of the .eh_frame section:
297 DW_CFA_nop
298 DW_CFA_nop
299
300-00000018 0000001c 0000001c FDE cie=00000000 pc=00400078..00400078
301- DW_CFA_advance_loc: 0 to 00400078
302+00000018 0000001c 0000001c FDE cie=00000000 pc=([0-9a-f]+)..\1
303+ DW_CFA_advance_loc: 0 to [0-9a-f]+
304 DW_CFA_def_cfa_offset: 16
305 DW_CFA_offset: r6 \(rbp\) at cfa-16
306- DW_CFA_advance_loc: 0 to 00400078
307+ DW_CFA_advance_loc: 0 to [0-9a-f]+
308 DW_CFA_def_cfa_register: r6 \(rbp\)
309
310 00000038 ZERO terminator
311--- binutils-2.22/ld/testsuite/ld-elf/eh3.d
312+++ binutils-2.22/ld/testsuite/ld-elf/eh3.d
313@@ -22,11 +22,11 @@ Contents of the .eh_frame section:
314 DW_CFA_nop
315 DW_CFA_nop
316
317-00000018 0000001c 0000001c FDE cie=00000000 pc=00400078..00400078
318- DW_CFA_advance_loc: 0 to 00400078
319+00000018 0000001c 0000001c FDE cie=00000000 pc=([0-9a-f]+)..\1
320+ DW_CFA_advance_loc: 0 to [0-9a-f]+
321 DW_CFA_def_cfa_offset: 16
322 DW_CFA_offset: r6 \(rbp\) at cfa-16
323- DW_CFA_advance_loc: 0 to 00400078
324+ DW_CFA_advance_loc: 0 to [0-9a-f]+
325 DW_CFA_def_cfa_register: r6 \(rbp\)
326
327 00000038 ZERO terminator
328--- binutils-2.22/ld/testsuite/ld-elf/orphan-region.d
329+++ binutils-2.22/ld/testsuite/ld-elf/orphan-region.d
330@@ -15,7 +15,9 @@
331 Program Headers:
332 Type.*
333 LOAD[ \t]+0x[0-9a-f]+ 0x0*40000000 0x0*40000000 0x[0-9a-f]+ 0x[0-9a-f]+ RWE 0x[0-9a-f]+
334+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
335
336 Section to Segment mapping:
337 Segment Sections...
338 00 .text .rodata .moredata *
339+ 01 +
340--- binutils-2.22/ld/testsuite/ld-i386/tlsbin.rd
341+++ binutils-2.22/ld/testsuite/ld-i386/tlsbin.rd
342@@ -44,6 +44,7 @@ Program Headers:
343 +LOAD.*
344 +DYNAMIC.*
345 +TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x0+60 0x0+a0 R +0x1000
346+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
347
348 Section to Segment mapping:
349 +Segment Sections...
350@@ -53,6 +54,7 @@ Program Headers:
351 +03 +.tdata .dynamic .got .got.plt *
352 +04 +.dynamic *
353 +05 +.tdata .tbss *
354+ +06 +
355
356 Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 9 entries:
357 Offset +Info +Type +Sym.Value +Sym. Name
358--- binutils-2.22/ld/testsuite/ld-i386/tlsbindesc.rd
359+++ binutils-2.22/ld/testsuite/ld-i386/tlsbindesc.rd
360@@ -42,6 +42,7 @@ Program Headers:
361 +LOAD.*
362 +DYNAMIC.*
363 +TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x0+60 0x0+a0 R +0x1000
364+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
365
366 Section to Segment mapping:
367 +Segment Sections...
368@@ -51,6 +52,7 @@ Program Headers:
369 +03 +.tdata .dynamic .got .got.plt *
370 +04 +.dynamic *
371 +05 +.tdata .tbss *
372+ +06 +
373
374 Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 9 entries:
375 Offset +Info +Type +Sym.Value +Sym. Name
376--- binutils-2.22/ld/testsuite/ld-i386/tlsdesc.rd
377+++ binutils-2.22/ld/testsuite/ld-i386/tlsdesc.rd
378@@ -39,6 +39,7 @@ Program Headers:
379 +LOAD.*
380 +DYNAMIC.*
381 +TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x0+60 0x0+80 R +0x1
382+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
383
384 Section to Segment mapping:
385 +Segment Sections...
386@@ -46,6 +47,7 @@ Program Headers:
387 +01 +.tdata .dynamic .got .got.plt *
388 +02 +.dynamic *
389 +03 +.tdata .tbss *
390+ +04 +
391
392 Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 20 entries:
393 Offset +Info +Type +Sym.Value +Sym. Name
394--- binutils-2.22/ld/testsuite/ld-i386/tlsdesc.sd
395+++ binutils-2.22/ld/testsuite/ld-i386/tlsdesc.sd
396@@ -14,7 +14,7 @@ Contents of section \.got:
397 [0-9a-f]+ 6c000000 b4ffffff 4c000000 68000000 .*
398 [0-9a-f]+ 50000000 70000000 00000000 bcffffff .*
399 Contents of section \.got\.plt:
400- [0-9a-f]+ b0150000 00000000 00000000 00000000 .*
401+ [0-9a-f]+ [a-f]0150000 00000000 00000000 00000000 .*
402 [0-9a-f]+ 20000000 00000000 60000000 00000000 .*
403 [0-9a-f]+ 00000000 00000000 00000000 00000000 .*
404 [0-9a-f]+ 40000000 +.*
405--- binutils-2.22/ld/testsuite/ld-i386/tlsgdesc.rd
406+++ binutils-2.22/ld/testsuite/ld-i386/tlsgdesc.rd
407@@ -36,12 +36,14 @@ Program Headers:
408 +LOAD.*
409 +LOAD.*
410 +DYNAMIC.*
411+ +PAX_FLAGS.*
412
413 Section to Segment mapping:
414 +Segment Sections...
415 +00 +.hash .dynsym .dynstr .rel.dyn .rel.plt .plt .text *
416 +01 +.dynamic .got .got.plt *
417 +02 +.dynamic *
418+ +03 +
419
420 Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 8 entries:
421 Offset +Info +Type +Sym.Value +Sym. Name
422--- binutils-2.22/ld/testsuite/ld-i386/tlsnopic.rd
423+++ binutils-2.22/ld/testsuite/ld-i386/tlsnopic.rd
424@@ -37,6 +37,7 @@ Program Headers:
425 +LOAD.*
426 +DYNAMIC.*
427 +TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x0+ 0x0+24 R +0x1
428+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
429
430 Section to Segment mapping:
431 +Segment Sections...
432@@ -44,6 +45,7 @@ Program Headers:
433 +01 +.dynamic .got .got.plt *
434 +02 +.dynamic *
435 +03 +.tbss *
436+ +04 +
437
438 Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 20 entries:
439 Offset +Info +Type +Sym.Value +Sym. Name
440--- binutils-2.22/ld/testsuite/ld-i386/tlspic.rd
441+++ binutils-2.22/ld/testsuite/ld-i386/tlspic.rd
442@@ -40,6 +40,7 @@ Program Headers:
443 +LOAD.*
444 +DYNAMIC.*
445 +TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x0+60 0x0+80 R +0x1
446+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
447
448 Section to Segment mapping:
449 +Segment Sections...
450@@ -47,6 +48,7 @@ Program Headers:
451 +01 +.tdata .dynamic .got .got.plt *
452 +02 +.dynamic *
453 +03 +.tdata .tbss *
454+ +04 +
455
456 Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 26 entries:
457 Offset +Info +Type +Sym.Value +Sym. Name
458--- binutils-2.22/ld/testsuite/ld-ia64/merge1.d
459+++ binutils-2.22/ld/testsuite/ld-ia64/merge1.d
460@@ -4,7 +4,7 @@
461 #objdump: -d
462
463 #...
464-0+1e0 <.text>:
465+[a-f0-9]+ <.text>:
466 [ ]*[a-f0-9]+: 0b 60 80 02 00 24 \[MMI\] addl r12=32,r1;;
467 [ ]*[a-f0-9]+: c0 c0 04 00 48 00 addl r12=24,r1
468 [ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;;
469--- binutils-2.22/ld/testsuite/ld-ia64/merge2.d
470+++ binutils-2.22/ld/testsuite/ld-ia64/merge2.d
471@@ -4,7 +4,7 @@
472 #objdump: -d
473
474 #...
475-0+1e0 <.text>:
476+[a-f0-9]+ <.text>:
477 [ ]*[a-f0-9]+: 0b 60 80 02 00 24 \[MMI\] addl r12=32,r1;;
478 [ ]*[a-f0-9]+: c0 c0 04 00 48 00 addl r12=24,r1
479 [ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;;
480--- binutils-2.22/ld/testsuite/ld-ia64/merge3.d
481+++ binutils-2.22/ld/testsuite/ld-ia64/merge3.d
482@@ -4,7 +4,7 @@
483 #objdump: -d
484
485 #...
486-0+210 <.text>:
487+[a-f0-9]+ <.text>:
488 [ ]*[a-f0-9]+: 0b 60 80 02 00 24 \[MMI\] addl r12=32,r1;;
489 [ ]*[a-f0-9]+: c0 40 05 00 48 00 addl r12=40,r1
490 [ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;;
491--- binutils-2.22/ld/testsuite/ld-ia64/merge4.d
492+++ binutils-2.22/ld/testsuite/ld-ia64/merge4.d
493@@ -4,7 +4,7 @@
494 #objdump: -d
495
496 #...
497-0+240 <.text>:
498+[a-f0-9]+ <.text>:
499 [ ]*[a-f0-9]+: 0b 60 80 02 00 24 \[MMI\] addl r12=32,r1;;
500 [ ]*[a-f0-9]+: c0 40 05 00 48 00 addl r12=40,r1
501 [ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;;
502--- binutils-2.22/ld/testsuite/ld-ia64/merge5.d
503+++ binutils-2.22/ld/testsuite/ld-ia64/merge5.d
504@@ -4,7 +4,7 @@
505 #objdump: -d
506
507 #...
508-0+270 <.text>:
509+[a-f0-9]+ <.text>:
510 [ ]*[a-f0-9]+: 0b 60 80 02 00 24 \[MMI\] addl r12=32,r1;;
511 [ ]*[a-f0-9]+: c0 40 05 00 48 00 addl r12=40,r1
512 [ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;;
513--- binutils-2.22/ld/testsuite/ld-ia64/tlsbin.rd
514+++ binutils-2.22/ld/testsuite/ld-ia64/tlsbin.rd
515@@ -36,13 +36,14 @@ There are [0-9]+ program headers, starting at offset [0-9]+
516
517 Program Headers:
518 +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
519- +PHDR +0x0+40 0x40+40 0x40+40 0x0+188 0x0+188 R E 0x8
520- +INTERP +0x0+1c8 0x40+1c8 0x40+1c8 0x[0-9a-f]+ 0x[0-9a-f]+ R +0x1
521+ +PHDR +0x0+40 0x40+40 0x40+40 (0x[0-9a-f]+) \1 R E 0x8
522+ +INTERP +0x0+([0-9a-f]+) (0x40+\1) \2 0x[0-9a-f]+ 0x[0-9a-f]+ R +0x1
523 .*Requesting program interpreter.*
524 +LOAD +0x0+ 0x40+ 0x40+ 0x0+1[0-9a-f]+ 0x0+1[0-9a-f]+ R E 0x10000
525 +LOAD +0x0+1[0-9a-f]+ 0x60+1[0-9a-f]+ 0x60+1[0-9a-f]+ 0x0+0[0-9a-f]+ 0x0+0[0-9a-f]+ RW +0x10000
526 +DYNAMIC +0x0+1[0-9a-f]+ 0x60+1[0-9a-f]+ 0x60+1[0-9a-f]+ 0x0+150 0x0+150 RW +0x8
527 +TLS +0x0+1[0-9a-f]+ 0x60+1[0-9a-f]+ 0x60+1[0-9a-f]+ 0x0+60 0x0+a0 R +0x4
528+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
529 +IA_64_UNWIND .* R +0x8
530 #...
531
532--- binutils-2.22/ld/testsuite/ld-ia64/tlspic.rd
533+++ binutils-2.22/ld/testsuite/ld-ia64/tlspic.rd
534@@ -40,6 +40,7 @@ Program Headers:
535 +LOAD +0x0+1[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+0[0-9a-f]+ 0x0+0[0-9a-f]+ RW +0x10000
536 +DYNAMIC +0x0+1[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+140 0x0+140 RW +0x8
537 +TLS +0x0+1[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+60 0x0+80 R +0x4
538+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
539 +IA_64_UNWIND +0x0+1[0-9a-f]+ 0x0+1[0-9a-f]+ 0x0+1[0-9a-f]+ 0x0+18 0x0+18 R +0x8
540 #...
541
542--- binutils-2.22/ld/testsuite/ld-mips-elf/multi-got-no-shared.d
543+++ binutils-2.22/ld/testsuite/ld-mips-elf/multi-got-no-shared.d
544@@ -8,9 +8,9 @@
545 .*: +file format.*
546
547 Disassembly of section \.text:
548-004000b0 <[^>]*> 3c1c0043 lui gp,0x43
549-004000b4 <[^>]*> 279c9ff0 addiu gp,gp,-24592
550-004000b8 <[^>]*> afbc0008 sw gp,8\(sp\)
551+004000d0 <[^>]*> 3c1c0043 lui gp,0x43
552+004000d4 <[^>]*> 279c9ff0 addiu gp,gp,-24592
553+004000d8 <[^>]*> afbc0008 sw gp,8\(sp\)
554 #...
555 00408d60 <[^>]*> 3c1c0043 lui gp,0x43
556 00408d64 <[^>]*> 279c2c98 addiu gp,gp,11416
557--- binutils-2.22/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.sd
558+++ binutils-2.22/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.sd
559@@ -1,7 +1,7 @@
560
561 Elf file type is DYN \(Shared object file\)
562 Entry point .*
563-There are 5 program headers, starting at offset .*
564+There are [0-9] program headers, starting at offset .*
565
566 Program Headers:
567 * Type * Offset * VirtAddr * PhysAddr * FileSiz * MemSiz * Flg * Align
568@@ -9,6 +9,7 @@ Program Headers:
569 * LOAD * [^ ]+ * 0x0+00000 * 0x0+00000 [^ ]+ * [^ ]+ * R E * 0x.*
570 * LOAD * [^ ]+ * 0x0+10000 * 0x0+10000 [^ ]+ * [^ ]+ * RW * 0x.*
571 * DYNAMIC * [^ ]+ * 0x0+00400 * 0x0+00400 .*
572+ * PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
573 * NULL * .*
574
575 *Section to Segment mapping:
576@@ -18,3 +19,4 @@ Program Headers:
577 *0*2 * \.data \.got *
578 *0*3 * \.dynamic *
579 *0*4 *
580+ *0*5 *
581--- binutils-2.22/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.sd
582+++ binutils-2.22/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.sd
583@@ -1,7 +1,7 @@
584
585 Elf file type is EXEC \(Executable file\)
586 Entry point 0x44000
587-There are 8 program headers, starting at offset .*
588+There are [0-9] program headers, starting at offset .*
589
590 Program Headers:
591 * Type * Offset * VirtAddr * PhysAddr * FileSiz * MemSiz * Flg * Align
592@@ -13,6 +13,7 @@ Program Headers:
593 * LOAD * [^ ]+ * 0x0+80000 * 0x0+80000 [^ ]+ * [^ ]+ * RW * 0x.*
594 * LOAD * [^ ]+ * 0x0+a0000 * 0x0+a0000 [^ ]+ * [^ ]+ * RW * 0x.*
595 * DYNAMIC * [^ ]+ * 0x0+42000 * 0x0+42000 .*
596+ * PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
597 * NULL * .*
598
599 *Section to Segment mapping:
600@@ -25,3 +26,4 @@ Program Headers:
601 *0*5 *\.got \.data *
602 *0*6 *\.dynamic *
603 *0*7 *
604+ *0*8 *
605--- binutils-2.22/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.sd
606+++ binutils-2.22/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.sd
607@@ -1,7 +1,7 @@
608
609 Elf file type is EXEC \(Executable file\)
610 Entry point 0x44000
611-There are 8 program headers, starting at offset .*
612+There are [0-9] program headers, starting at offset .*
613
614 Program Headers:
615 * Type * Offset * VirtAddr * PhysAddr * FileSiz * MemSiz * Flg * Align
616@@ -13,6 +13,7 @@ Program Headers:
617 * LOAD * [^ ]+ * 0x0+80000 * 0x0+80000 [^ ]+ * [^ ]+ * RW * 0x.*
618 * LOAD * [^ ]+ * 0x0+a0000 * 0x0+a0000 [^ ]+ * [^ ]+ * RW * 0x.*
619 * DYNAMIC * [^ ]+ * 0x0+42000 * 0x0+42000 .*
620+ * PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
621 * NULL * .*
622
623 *Section to Segment mapping:
624@@ -25,3 +26,4 @@ Program Headers:
625 *0*5 * \.got \.data \.bss *
626 *0*6 * \.dynamic *
627 *0*7 *
628+ *0*8 *
629--- binutils-2.22/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.sd
630+++ binutils-2.22/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.sd
631@@ -1,7 +1,7 @@
632
633 Elf file type is EXEC \(Executable file\)
634 Entry point 0x44000
635-There are 8 program headers, starting at offset .*
636+There are [0-9] program headers, starting at offset .*
637
638 Program Headers:
639 * Type * Offset * VirtAddr * PhysAddr * FileSiz * MemSiz * Flg * Align
640@@ -13,6 +13,7 @@ Program Headers:
641 * LOAD * [^ ]+ * 0x0+80000 * 0x0+80000 [^ ]+ * [^ ]+ * RW * 0x.*
642 * LOAD * [^ ]+ * 0x0+a0000 * 0x0+a0000 [^ ]+ * [^ ]+ * RW * 0x.*
643 * DYNAMIC * [^ ]+ * 0x0+42000 * 0x0+42000 .*
644+ * PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
645 * NULL * .*
646
647 *Section to Segment mapping:
648@@ -25,3 +26,4 @@ Program Headers:
649 *0*5 * \.got \.data \.bss *
650 *0*6 * \.dynamic *
651 *0*7 *
652+ *0*8 *
653--- binutils-2.22/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.sd
654+++ binutils-2.22/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.sd
655@@ -1,7 +1,7 @@
656
657 Elf file type is EXEC \(Executable file\)
658 Entry point 0x44000
659-There are 8 program headers, starting at offset .*
660+There are [0-9] program headers, starting at offset .*
661
662 Program Headers:
663 * Type * Offset * VirtAddr * PhysAddr * FileSiz * MemSiz * Flg * Align
664@@ -13,6 +13,7 @@ Program Headers:
665 * LOAD * [^ ]+ * 0x0+80000 * 0x0+80000 [^ ]+ * [^ ]+ * RW * 0x.*
666 * LOAD * [^ ]+ * 0x0+a0000 * 0x0+a0000 [^ ]+ * [^ ]+ * RW * 0x.*
667 * DYNAMIC * [^ ]+ * 0x0+42000 * 0x0+42000 .*
668+ * PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
669 * NULL * .*
670
671 *Section to Segment mapping:
672@@ -25,3 +26,4 @@ Program Headers:
673 *0*5 * \.got \.data \.bss *
674 *0*6 * \.dynamic *
675 *0*7 *
676+ *0*8 *
677--- binutils-2.22/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.sd
678+++ binutils-2.22/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.sd
679@@ -1,7 +1,7 @@
680
681 Elf file type is EXEC \(Executable file\)
682 Entry point 0x44000
683-There are 7 program headers, starting at offset .*
684+There are [0-9] program headers, starting at offset .*
685
686 Program Headers:
687 * Type * Offset * VirtAddr * PhysAddr * FileSiz * MemSiz * Flg * Align
688@@ -12,6 +12,7 @@ Program Headers:
689 * LOAD * [^ ]+ * 0x0+80000 * 0x0+80000 [^ ]+ * [^ ]+ * RW * 0x.*
690 * LOAD * [^ ]+ * 0x0+a0000 * 0x0+a0000 [^ ]+ * [^ ]+ * RW * 0x.*
691 * DYNAMIC * [^ ]+ * 0x0+42000 * 0x0+42000 .*
692+ * PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
693 * NULL * .*
694
695 *Section to Segment mapping:
696@@ -23,3 +24,4 @@ Program Headers:
697 *0*4 * \.got \.data \.bss *
698 *0*5 * \.dynamic *
699 *0*6 *
700+ *0*7 *
701--- binutils-2.22/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.sd
702+++ binutils-2.22/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.sd
703@@ -1,7 +1,7 @@
704
705 Elf file type is EXEC \(Executable file\)
706 Entry point 0x44000
707-There are 8 program headers, starting at offset .*
708+There are [0-9] program headers, starting at offset .*
709
710 Program Headers:
711 * Type * Offset * VirtAddr * PhysAddr * FileSiz * MemSiz * Flg * Align
712@@ -13,6 +13,7 @@ Program Headers:
713 * LOAD * [^ ]+ * 0x0+80000 * 0x0+80000 [^ ]+ * [^ ]+ * RW * 0x.*
714 * LOAD * [^ ]+ * 0x0+a0000 * 0x0+a0000 [^ ]+ * [^ ]+ * RW * 0x.*
715 * DYNAMIC * [^ ]+ * 0x0+42000 * 0x0+42000 .*
716+ * PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
717 * NULL * .*
718
719 *Section to Segment mapping:
720@@ -25,3 +26,4 @@ Program Headers:
721 *0*5 * \.got \.data \.bss *
722 *0*6 * \.dynamic *
723 *0*7 *
724+ *0*8 *
725--- binutils-2.22/ld/testsuite/ld-mips-elf/rel32-n32.d
726+++ binutils-2.22/ld/testsuite/ld-mips-elf/rel32-n32.d
727@@ -10,6 +10,6 @@ Relocation section '.rel.dyn' at offset .* contains 2 entries:
728 [0-9a-f ]+R_MIPS_REL32
729
730 Hex dump of section '.text':
731- 0x000002e0 00000000 00000000 00000000 00000000 ................
732- 0x000002f0 000002f0 00000000 00000000 00000000 ................
733 0x00000300 00000000 00000000 00000000 00000000 ................
734+ 0x00000310 00000310 00000000 00000000 00000000 ................
735+ 0x00000320 00000000 00000000 00000000 00000000 ................
736--- binutils-2.22/ld/testsuite/ld-mips-elf/rel32-o32.d
737+++ binutils-2.22/ld/testsuite/ld-mips-elf/rel32-o32.d
738@@ -10,6 +10,6 @@ Relocation section '.rel.dyn' at offset .* contains 2 entries:
739 [0-9a-f ]+R_MIPS_REL32
740
741 Hex dump of section '.text':
742- 0x000002e0 00000000 00000000 00000000 00000000 ................
743- 0x000002f0 000002f0 00000000 00000000 00000000 ................
744 0x00000300 00000000 00000000 00000000 00000000 ................
745+ 0x00000310 00000310 00000000 00000000 00000000 ................
746+ 0x00000320 00000000 00000000 00000000 00000000 ................
747--- binutils-2.22/ld/testsuite/ld-mips-elf/rel64.d
748+++ binutils-2.22/ld/testsuite/ld-mips-elf/rel64.d
749@@ -14,6 +14,6 @@ Relocation section '.rel.dyn' at offset .* contains 2 entries:
750 +Type3: R_MIPS_NONE
751
752 Hex dump of section '.text':
753- 0x00000450 00000000 00000000 00000000 00000000 ................
754- 0x00000460 00000000 00000460 00000000 00000000 ................
755- 0x00000470 00000000 00000000 00000000 00000000 ................
756+ 0x00000490 00000000 00000000 00000000 00000000 ................
757+ 0x000004a0 00000000 000004a0 00000000 00000000 ................
758+ 0x000004b0 00000000 00000000 00000000 00000000 ................
759--- binutils-2.22/ld/testsuite/ld-mips-elf/tlsbin-o32.d
760+++ binutils-2.22/ld/testsuite/ld-mips-elf/tlsbin-o32.d
761@@ -2,42 +2,42 @@
762
763 Disassembly of section .text:
764
765-004000d0 <__start>:
766- 4000d0: 3c1c0fc0 lui gp,0xfc0
767- 4000d4: 279c7f30 addiu gp,gp,32560
768- 4000d8: 0399e021 addu gp,gp,t9
769- 4000dc: 27bdfff0 addiu sp,sp,-16
770- 4000e0: afbe0008 sw s8,8\(sp\)
771- 4000e4: 03a0f021 move s8,sp
772- 4000e8: afbc0000 sw gp,0\(sp\)
773- 4000ec: 8f998018 lw t9,-32744\(gp\)
774- 4000f0: 27848028 addiu a0,gp,-32728
775- 4000f4: 0320f809 jalr t9
776- 4000f8: 00000000 nop
777- 4000fc: 8fdc0000 lw gp,0\(s8\)
778- 400100: 00000000 nop
779- 400104: 8f998018 lw t9,-32744\(gp\)
780- 400108: 27848020 addiu a0,gp,-32736
781- 40010c: 0320f809 jalr t9
782- 400110: 00000000 nop
783- 400114: 8fdc0000 lw gp,0\(s8\)
784- 400118: 00401021 move v0,v0
785- 40011c: 3c030000 lui v1,0x0
786- 400120: 24638000 addiu v1,v1,-32768
787- 400124: 00621821 addu v1,v1,v0
788- 400128: 7c02283b rdhwr v0,\$5
789- 40012c: 8f83801c lw v1,-32740\(gp\)
790- 400130: 00000000 nop
791- 400134: 00621821 addu v1,v1,v0
792- 400138: 7c02283b rdhwr v0,\$5
793- 40013c: 3c030000 lui v1,0x0
794- 400140: 24639004 addiu v1,v1,-28668
795- 400144: 00621821 addu v1,v1,v0
796- 400148: 03c0e821 move sp,s8
797- 40014c: 8fbe0008 lw s8,8\(sp\)
798- 400150: 03e00008 jr ra
799- 400154: 27bd0010 addiu sp,sp,16
800+00400[0-9a-f]{3} <__start>:
801+ 400[0-9a-f]{3}: 3c1c0fc0 lui gp,0xfc0
802+ 400[0-9a-f]{3}: 279c7f30 addiu gp,gp,32560
803+ 400[0-9a-f]{3}: 0399e021 addu gp,gp,t9
804+ 400[0-9a-f]{3}: 27bdfff0 addiu sp,sp,-16
805+ 400[0-9a-f]{3}: afbe0008 sw s8,8\(sp\)
806+ 400[0-9a-f]{3}: 03a0f021 move s8,sp
807+ 400[0-9a-f]{3}: afbc0000 sw gp,0\(sp\)
808+ 400[0-9a-f]{3}: 8f998018 lw t9,-32744\(gp\)
809+ 400[0-9a-f]{3}: 27848028 addiu a0,gp,-32728
810+ 400[0-9a-f]{3}: 0320f809 jalr t9
811+ 400[0-9a-f]{3}: 00000000 nop
812+ 400[0-9a-f]{3}: 8fdc0000 lw gp,0\(s8\)
813+ 400[0-9a-f]{3}: 00000000 nop
814+ 400[0-9a-f]{3}: 8f998018 lw t9,-32744\(gp\)
815+ 400[0-9a-f]{3}: 27848020 addiu a0,gp,-32736
816+ 400[0-9a-f]{3}: 0320f809 jalr t9
817+ 400[0-9a-f]{3}: 00000000 nop
818+ 400[0-9a-f]{3}: 8fdc0000 lw gp,0\(s8\)
819+ 400[0-9a-f]{3}: 00401021 move v0,v0
820+ 400[0-9a-f]{3}: 3c030000 lui v1,0x0
821+ 400[0-9a-f]{3}: 24638000 addiu v1,v1,-32768
822+ 400[0-9a-f]{3}: 00621821 addu v1,v1,v0
823+ 400[0-9a-f]{3}: 7c02283b rdhwr v0,\$5
824+ 400[0-9a-f]{3}: 8f83801c lw v1,-32740\(gp\)
825+ 400[0-9a-f]{3}: 00000000 nop
826+ 400[0-9a-f]{3}: 00621821 addu v1,v1,v0
827+ 400[0-9a-f]{3}: 7c02283b rdhwr v0,\$5
828+ 400[0-9a-f]{3}: 3c030000 lui v1,0x0
829+ 400[0-9a-f]{3}: 24639004 addiu v1,v1,-28668
830+ 400[0-9a-f]{3}: 00621821 addu v1,v1,v0
831+ 400[0-9a-f]{3}: 03c0e821 move sp,s8
832+ 400[0-9a-f]{3}: 8fbe0008 lw s8,8\(sp\)
833+ 400[0-9a-f]{3}: 03e00008 jr ra
834+ 400[0-9a-f]{3}: 27bd0010 addiu sp,sp,16
835
836-00400158 <__tls_get_addr>:
837- 400158: 03e00008 jr ra
838- 40015c: 00000000 nop
839+00400[0-9a-f]{3} <__tls_get_addr>:
840+ 400[0-9a-f]{3}: 03e00008 jr ra
841+ 400[0-9a-f]{3}: 00000000 nop
842--- binutils-2.22/ld/testsuite/ld-powerpc/tls.d
843+++ binutils-2.22/ld/testsuite/ld-powerpc/tls.d
844@@ -9,45 +9,45 @@
845
846 Disassembly of section \.text:
847
848-0+100000e8 <_start>:
849- 100000e8: 3c 6d 00 00 addis r3,r13,0
850- 100000ec: 60 00 00 00 nop
851- 100000f0: 38 63 90 78 addi r3,r3,-28552
852- 100000f4: 3c 6d 00 00 addis r3,r13,0
853- 100000f8: 60 00 00 00 nop
854- 100000fc: 38 63 10 00 addi r3,r3,4096
855- 10000100: 3c 6d 00 00 addis r3,r13,0
856- 10000104: 60 00 00 00 nop
857- 10000108: 38 63 90 40 addi r3,r3,-28608
858- 1000010c: 3c 6d 00 00 addis r3,r13,0
859- 10000110: 60 00 00 00 nop
860- 10000114: 38 63 10 00 addi r3,r3,4096
861- 10000118: 39 23 80 48 addi r9,r3,-32696
862- 1000011c: 3d 23 00 00 addis r9,r3,0
863- 10000120: 81 49 80 50 lwz r10,-32688\(r9\)
864- 10000124: e9 22 80 10 ld r9,-32752\(r2\)
865- 10000128: 7d 49 18 2a ldx r10,r9,r3
866- 1000012c: 3d 2d 00 00 addis r9,r13,0
867- 10000130: a1 49 90 60 lhz r10,-28576\(r9\)
868- 10000134: 89 4d 90 68 lbz r10,-28568\(r13\)
869- 10000138: 3d 2d 00 00 addis r9,r13,0
870- 1000013c: 99 49 90 70 stb r10,-28560\(r9\)
871- 10000140: 3c 6d 00 00 addis r3,r13,0
872- 10000144: 60 00 00 00 nop
873- 10000148: 38 63 90 00 addi r3,r3,-28672
874- 1000014c: 3c 6d 00 00 addis r3,r13,0
875- 10000150: 60 00 00 00 nop
876- 10000154: 38 63 10 00 addi r3,r3,4096
877- 10000158: f9 43 80 08 std r10,-32760\(r3\)
878- 1000015c: 3d 23 00 00 addis r9,r3,0
879- 10000160: 91 49 80 10 stw r10,-32752\(r9\)
880- 10000164: e9 22 80 08 ld r9,-32760\(r2\)
881- 10000168: 7d 49 19 2a stdx r10,r9,r3
882- 1000016c: 3d 2d 00 00 addis r9,r13,0
883- 10000170: b1 49 90 60 sth r10,-28576\(r9\)
884- 10000174: e9 4d 90 2a lwa r10,-28632\(r13\)
885- 10000178: 3d 2d 00 00 addis r9,r13,0
886- 1000017c: a9 49 90 30 lha r10,-28624\(r9\)
887+0+10000[0-9a-f]{3} <_start>:
888+ 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0
889+ 10000[0-9a-f]{3}: 60 00 00 00 nop
890+ 10000[0-9a-f]{3}: 38 63 90 78 addi r3,r3,-28552
891+ 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0
892+ 10000[0-9a-f]{3}: 60 00 00 00 nop
893+ 10000[0-9a-f]{3}: 38 63 10 00 addi r3,r3,4096
894+ 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0
895+ 10000[0-9a-f]{3}: 60 00 00 00 nop
896+ 10000[0-9a-f]{3}: 38 63 90 40 addi r3,r3,-28608
897+ 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0
898+ 10000[0-9a-f]{3}: 60 00 00 00 nop
899+ 10000[0-9a-f]{3}: 38 63 10 00 addi r3,r3,4096
900+ 10000[0-9a-f]{3}: 39 23 80 48 addi r9,r3,-32696
901+ 10000[0-9a-f]{3}: 3d 23 00 00 addis r9,r3,0
902+ 10000[0-9a-f]{3}: 81 49 80 50 lwz r10,-32688\(r9\)
903+ 10000[0-9a-f]{3}: e9 22 80 10 ld r9,-32752\(r2\)
904+ 10000[0-9a-f]{3}: 7d 49 18 2a ldx r10,r9,r3
905+ 10000[0-9a-f]{3}: 3d 2d 00 00 addis r9,r13,0
906+ 10000[0-9a-f]{3}: a1 49 90 60 lhz r10,-28576\(r9\)
907+ 10000[0-9a-f]{3}: 89 4d 90 68 lbz r10,-28568\(r13\)
908+ 10000[0-9a-f]{3}: 3d 2d 00 00 addis r9,r13,0
909+ 10000[0-9a-f]{3}: 99 49 90 70 stb r10,-28560\(r9\)
910+ 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0
911+ 10000[0-9a-f]{3}: 60 00 00 00 nop
912+ 10000[0-9a-f]{3}: 38 63 90 00 addi r3,r3,-28672
913+ 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0
914+ 10000[0-9a-f]{3}: 60 00 00 00 nop
915+ 10000[0-9a-f]{3}: 38 63 10 00 addi r3,r3,4096
916+ 10000[0-9a-f]{3}: f9 43 80 08 std r10,-32760\(r3\)
917+ 10000[0-9a-f]{3}: 3d 23 00 00 addis r9,r3,0
918+ 10000[0-9a-f]{3}: 91 49 80 10 stw r10,-32752\(r9\)
919+ 10000[0-9a-f]{3}: e9 22 80 08 ld r9,-32760\(r2\)
920+ 10000[0-9a-f]{3}: 7d 49 19 2a stdx r10,r9,r3
921+ 10000[0-9a-f]{3}: 3d 2d 00 00 addis r9,r13,0
922+ 10000[0-9a-f]{3}: b1 49 90 60 sth r10,-28576\(r9\)
923+ 10000[0-9a-f]{3}: e9 4d 90 2a lwa r10,-28632\(r13\)
924+ 10000[0-9a-f]{3}: 3d 2d 00 00 addis r9,r13,0
925+ 10000[0-9a-f]{3}: a9 49 90 30 lha r10,-28624\(r9\)
926
927-0+10000180 <\.__tls_get_addr>:
928- 10000180: 4e 80 00 20 blr
929+0+10000[0-9a-f]{3} <\.__tls_get_addr>:
930+ 10000[0-9a-f]{3}: 4e 80 00 20 blr
931--- binutils-2.22/ld/testsuite/ld-powerpc/tls.g
932+++ binutils-2.22/ld/testsuite/ld-powerpc/tls.g
933@@ -8,5 +8,5 @@
934 .*: +file format elf64-powerpc
935
936 Contents of section \.got:
937- 100101e0 00000000 100181e0 ffffffff ffff8018 .*
938- 100101f0 ffffffff ffff8058 .*
939+ 10010([0-9a-f]{3}) 00000000 10018\1 ffffffff ffff8018 .*
940+ 10010[0-9a-f]{3} ffffffff ffff8058 .*
941--- binutils-2.22/ld/testsuite/ld-powerpc/tls32.d
942+++ binutils-2.22/ld/testsuite/ld-powerpc/tls32.d
943@@ -9,42 +9,42 @@
944
945 Disassembly of section \.text:
946
947-0+1800094 <_start>:
948- 1800094: 3c 62 00 00 addis r3,r2,0
949- 1800098: 38 63 90 3c addi r3,r3,-28612
950- 180009c: 3c 62 00 00 addis r3,r2,0
951- 18000a0: 38 63 10 00 addi r3,r3,4096
952- 18000a4: 3c 62 00 00 addis r3,r2,0
953- 18000a8: 38 63 90 20 addi r3,r3,-28640
954- 18000ac: 3c 62 00 00 addis r3,r2,0
955- 18000b0: 38 63 10 00 addi r3,r3,4096
956- 18000b4: 39 23 80 24 addi r9,r3,-32732
957- 18000b8: 3d 23 00 00 addis r9,r3,0
958- 18000bc: 81 49 80 28 lwz r10,-32728\(r9\)
959- 18000c0: 3d 22 00 00 addis r9,r2,0
960- 18000c4: a1 49 90 30 lhz r10,-28624\(r9\)
961- 18000c8: 89 42 90 34 lbz r10,-28620\(r2\)
962- 18000cc: 3d 22 00 00 addis r9,r2,0
963- 18000d0: 99 49 90 38 stb r10,-28616\(r9\)
964- 18000d4: 3c 62 00 00 addis r3,r2,0
965- 18000d8: 38 63 90 00 addi r3,r3,-28672
966- 18000dc: 3c 62 00 00 addis r3,r2,0
967- 18000e0: 38 63 10 00 addi r3,r3,4096
968- 18000e4: 91 43 80 04 stw r10,-32764\(r3\)
969- 18000e8: 3d 23 00 00 addis r9,r3,0
970- 18000ec: 91 49 80 08 stw r10,-32760\(r9\)
971- 18000f0: 3d 22 00 00 addis r9,r2,0
972- 18000f4: b1 49 90 30 sth r10,-28624\(r9\)
973- 18000f8: a1 42 90 14 lhz r10,-28652\(r2\)
974- 18000fc: 3d 22 00 00 addis r9,r2,0
975- 1800100: a9 49 90 18 lha r10,-28648\(r9\)
976+0+1800[0-9a-f]{3} <_start>:
977+ 1800[0-9a-f]{3}: 3c 62 00 00 addis r3,r2,0
978+ 1800[0-9a-f]{3}: 38 63 90 3c addi r3,r3,-28612
979+ 1800[0-9a-f]{3}: 3c 62 00 00 addis r3,r2,0
980+ 1800[0-9a-f]{3}: 38 63 10 00 addi r3,r3,4096
981+ 1800[0-9a-f]{3}: 3c 62 00 00 addis r3,r2,0
982+ 1800[0-9a-f]{3}: 38 63 90 20 addi r3,r3,-28640
983+ 1800[0-9a-f]{3}: 3c 62 00 00 addis r3,r2,0
984+ 1800[0-9a-f]{3}: 38 63 10 00 addi r3,r3,4096
985+ 1800[0-9a-f]{3}: 39 23 80 24 addi r9,r3,-32732
986+ 1800[0-9a-f]{3}: 3d 23 00 00 addis r9,r3,0
987+ 1800[0-9a-f]{3}: 81 49 80 28 lwz r10,-32728\(r9\)
988+ 1800[0-9a-f]{3}: 3d 22 00 00 addis r9,r2,0
989+ 1800[0-9a-f]{3}: a1 49 90 30 lhz r10,-28624\(r9\)
990+ 1800[0-9a-f]{3}: 89 42 90 34 lbz r10,-28620\(r2\)
991+ 1800[0-9a-f]{3}: 3d 22 00 00 addis r9,r2,0
992+ 1800[0-9a-f]{3}: 99 49 90 38 stb r10,-28616\(r9\)
993+ 1800[0-9a-f]{3}: 3c 62 00 00 addis r3,r2,0
994+ 1800[0-9a-f]{3}: 38 63 90 00 addi r3,r3,-28672
995+ 1800[0-9a-f]{3}: 3c 62 00 00 addis r3,r2,0
996+ 1800[0-9a-f]{3}: 38 63 10 00 addi r3,r3,4096
997+ 1800[0-9a-f]{3}: 91 43 80 04 stw r10,-32764\(r3\)
998+ 1800[0-9a-f]{3}: 3d 23 00 00 addis r9,r3,0
999+ 1800[0-9a-f]{3}: 91 49 80 08 stw r10,-32760\(r9\)
1000+ 1800[0-9a-f]{3}: 3d 22 00 00 addis r9,r2,0
1001+ 1800[0-9a-f]{3}: b1 49 90 30 sth r10,-28624\(r9\)
1002+ 1800[0-9a-f]{3}: a1 42 90 14 lhz r10,-28652\(r2\)
1003+ 1800[0-9a-f]{3}: 3d 22 00 00 addis r9,r2,0
1004+ 1800[0-9a-f]{3}: a9 49 90 18 lha r10,-28648\(r9\)
1005
1006-0+1800104 <__tls_get_addr>:
1007- 1800104: 4e 80 00 20 blr
1008+0+1800[0-9a-f]{3} <__tls_get_addr>:
1009+ 1800[0-9a-f]{3}: 4e 80 00 20 blr
1010 Disassembly of section \.got:
1011
1012-0+1810128 <_GLOBAL_OFFSET_TABLE_-0x4>:
1013- 1810128: 4e 80 00 21 blrl
1014+0+1810[0-9a-f]{3} <_GLOBAL_OFFSET_TABLE_-0x4>:
1015+ 1810[0-9a-f]{3}: 4e 80 00 21 blrl
1016
1017-0+181012c <_GLOBAL_OFFSET_TABLE_>:
1018+0+1810[0-9a-f]{3} <_GLOBAL_OFFSET_TABLE_>:
1019 \.\.\.
1020--- binutils-2.22/ld/testsuite/ld-powerpc/tls32.g
1021+++ binutils-2.22/ld/testsuite/ld-powerpc/tls32.g
1022@@ -8,4 +8,4 @@
1023 .*: +file format elf32-powerpc
1024
1025 Contents of section \.got:
1026- 1810128 4e800021 00000000 00000000 00000000 .*
1027+ 18101[0-9a-f]{2} 4e800021 00000000 00000000 00000000 .*
1028--- binutils-2.22/ld/testsuite/ld-powerpc/tls32.t
1029+++ binutils-2.22/ld/testsuite/ld-powerpc/tls32.t
1030@@ -8,5 +8,5 @@
1031 .*: +file format elf32-powerpc
1032
1033 Contents of section \.tdata:
1034- 1810108 12345678 23456789 3456789a 456789ab .*
1035- 1810118 56789abc 6789abcd 789abcde 00c0ffee .*
1036+ 18101[0-9a-f]{2} 12345678 23456789 3456789a 456789ab .*
1037+ 18101[0-9a-f]{2} 56789abc 6789abcd 789abcde 00c0ffee .*
1038--- binutils-2.22/ld/testsuite/ld-powerpc/tlsexe32.d
1039+++ binutils-2.22/ld/testsuite/ld-powerpc/tlsexe32.d
1040@@ -44,4 +44,4 @@ Disassembly of section \.got:
1041 .*: 4e 80 00 21 blrl
1042
1043 .* <_GLOBAL_OFFSET_TABLE_>:
1044-.*: 01 81 02 b8 00 00 00 00 00 00 00 00 .*
1045+.*: 01 81 02 [bd]8 00 00 00 00 00 00 00 00 .*
1046--- binutils-2.22/ld/testsuite/ld-powerpc/tlsexe32.g
1047+++ binutils-2.22/ld/testsuite/ld-powerpc/tlsexe32.g
1048@@ -8,4 +8,4 @@
1049
1050 Contents of section \.got:
1051 .* 00000000 00000000 00000000 4e800021 .*
1052-.* 018102b8 00000000 00000000 .*
1053+.* 018102[bd]8 00000000 00000000 .*
1054--- binutils-2.22/ld/testsuite/ld-powerpc/tlsexe32.r
1055+++ binutils-2.22/ld/testsuite/ld-powerpc/tlsexe32.r
1056@@ -33,13 +33,14 @@ There are [0-9]+ program headers, starting at offset [0-9]+
1057
1058 Program Headers:
1059 +Type +Offset +VirtAddr +PhysAddr +FileSiz MemSiz +Flg Align
1060- +PHDR +0x000034 0x01800034 0x01800034 0x000c0 0x000c0 R E 0x4
1061- +INTERP +0x0000f4 0x018000f4 0x018000f4 0x00011 0x00011 R +0x1
1062+ +PHDR +0x000034 0x01800034 0x01800034 (0x000[0-9a-f]{2}) \1 R E 0x4
1063+ +INTERP +0x000([0-9a-f]{3}) 0x01800\1 0x01800\1 0x00011 0x00011 R +0x1
1064 +\[Requesting program interpreter: .*\]
1065 +LOAD .* R E 0x10000
1066 +LOAD .* RWE 0x10000
1067 +DYNAMIC .* RW +0x4
1068 +TLS .* 0x0001c 0x00038 R +0x4
1069+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
1070
1071 Section to Segment mapping:
1072 +Segment Sections\.\.\.
1073@@ -49,6 +50,7 @@ Program Headers:
1074 +03 +\.tdata \.dynamic \.got \.plt
1075 +04 +\.dynamic
1076 +05 +\.tdata \.tbss
1077+ +06 +
1078
1079 Relocation section '\.rela\.dyn' at offset .* contains 2 entries:
1080 Offset +Info +Type +Sym\. Value +Symbol's Name \+ Addend
1081--- binutils-2.22/ld/testsuite/ld-powerpc/tlsmark.d
1082+++ binutils-2.22/ld/testsuite/ld-powerpc/tlsmark.d
1083@@ -9,29 +9,29 @@
1084
1085 Disassembly of section \.text:
1086
1087-0+100000e8 <_start>:
1088- 100000e8: 48 00 00 18 b 10000100 <_start\+0x18>
1089- 100000ec: 60 00 00 00 nop
1090- 100000f0: 38 63 90 00 addi r3,r3,-28672
1091- 100000f4: e8 83 00 00 ld r4,0\(r3\)
1092- 100000f8: 3c 6d 00 00 addis r3,r13,0
1093- 100000fc: 48 00 00 0c b 10000108 <_start\+0x20>
1094- 10000100: 3c 6d 00 00 addis r3,r13,0
1095- 10000104: 4b ff ff e8 b 100000ec <_start\+0x4>
1096- 10000108: 60 00 00 00 nop
1097- 1000010c: 38 63 10 00 addi r3,r3,4096
1098- 10000110: e8 83 80 00 ld r4,-32768\(r3\)
1099- 10000114: 3c 6d 00 00 addis r3,r13,0
1100- 10000118: 48 00 00 0c b 10000124 <_start\+0x3c>
1101- 1000011c: 3c 6d 00 00 addis r3,r13,0
1102- 10000120: 48 00 00 14 b 10000134 <_start\+0x4c>
1103- 10000124: 60 00 00 00 nop
1104- 10000128: 38 63 90 04 addi r3,r3,-28668
1105- 1000012c: e8 a3 00 00 ld r5,0\(r3\)
1106- 10000130: 4b ff ff ec b 1000011c <_start\+0x34>
1107- 10000134: 60 00 00 00 nop
1108- 10000138: 38 63 10 00 addi r3,r3,4096
1109- 1000013c: e8 a3 80 04 ld r5,-32764\(r3\)
1110+0+10000[0-9a-f]{3} <_start>:
1111+ 10000[0-9a-f]{3}: 48 00 00 18 b 10000[0-9a-f]{3} <_start\+0x18>
1112+ 10000[0-9a-f]{3}: 60 00 00 00 nop
1113+ 10000[0-9a-f]{3}: 38 63 90 00 addi r3,r3,-28672
1114+ 10000[0-9a-f]{3}: e8 83 00 00 ld r4,0\(r3\)
1115+ 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0
1116+ 10000[0-9a-f]{3}: 48 00 00 0c b 10000[0-9a-f]{3} <_start\+0x20>
1117+ 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0
1118+ 10000[0-9a-f]{3}: 4b ff ff e8 b 10000[0-9a-f]{3} <_start\+0x4>
1119+ 10000[0-9a-f]{3}: 60 00 00 00 nop
1120+ 10000[0-9a-f]{3}: 38 63 10 00 addi r3,r3,4096
1121+ 10000[0-9a-f]{3}: e8 83 80 00 ld r4,-32768\(r3\)
1122+ 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0
1123+ 10000[0-9a-f]{3}: 48 00 00 0c b 10000[0-9a-f]{3} <_start\+0x3c>
1124+ 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0
1125+ 10000[0-9a-f]{3}: 48 00 00 14 b 10000[0-9a-f]{3} <_start\+0x4c>
1126+ 10000[0-9a-f]{3}: 60 00 00 00 nop
1127+ 10000[0-9a-f]{3}: 38 63 90 04 addi r3,r3,-28668
1128+ 10000[0-9a-f]{3}: e8 a3 00 00 ld r5,0\(r3\)
1129+ 10000[0-9a-f]{3}: 4b ff ff ec b 10000[0-9a-f]{3} <_start\+0x34>
1130+ 10000[0-9a-f]{3}: 60 00 00 00 nop
1131+ 10000[0-9a-f]{3}: 38 63 10 00 addi r3,r3,4096
1132+ 10000[0-9a-f]{3}: e8 a3 80 04 ld r5,-32764\(r3\)
1133
1134-0+10000140 <\.__tls_get_addr>:
1135- 10000140: 4e 80 00 20 blr
1136+0+10000[0-9a-f]{3} <\.__tls_get_addr>:
1137+ 10000[0-9a-f]{3}: 4e 80 00 20 blr
1138--- binutils-2.22/ld/testsuite/ld-powerpc/tlsmark32.d
1139+++ binutils-2.22/ld/testsuite/ld-powerpc/tlsmark32.d
1140@@ -9,17 +9,17 @@
1141
1142 Disassembly of section \.text:
1143
1144-0+1800094 <_start>:
1145- 1800094: 48 00 00 14 b 18000a8 <_start\+0x14>
1146- 1800098: 38 63 90 00 addi r3,r3,-28672
1147- 180009c: 80 83 00 00 lwz r4,0\(r3\)
1148- 18000a0: 3c 62 00 00 addis r3,r2,0
1149- 18000a4: 48 00 00 0c b 18000b0 <_start\+0x1c>
1150- 18000a8: 3c 62 00 00 addis r3,r2,0
1151- 18000ac: 4b ff ff ec b 1800098 <_start\+0x4>
1152- 18000b0: 38 63 10 00 addi r3,r3,4096
1153- 18000b4: 80 83 80 00 lwz r4,-32768\(r3\)
1154+0+18000[0-9a-f]{2} <_start>:
1155+ 18000[0-9a-f]{2}: 48 00 00 14 b 18000[0-9a-f]{2} <_start\+0x14>
1156+ 18000[0-9a-f]{2}: 38 63 90 00 addi r3,r3,-28672
1157+ 18000[0-9a-f]{2}: 80 83 00 00 lwz r4,0\(r3\)
1158+ 18000[0-9a-f]{2}: 3c 62 00 00 addis r3,r2,0
1159+ 18000[0-9a-f]{2}: 48 00 00 0c b 18000[0-9a-f]{2} <_start\+0x1c>
1160+ 18000[0-9a-f]{2}: 3c 62 00 00 addis r3,r2,0
1161+ 18000[0-9a-f]{2}: 4b ff ff ec b 18000[0-9a-f]{2} <_start\+0x4>
1162+ 18000[0-9a-f]{2}: 38 63 10 00 addi r3,r3,4096
1163+ 18000[0-9a-f]{2}: 80 83 80 00 lwz r4,-32768\(r3\)
1164
1165-0+18000b8 <__tls_get_addr>:
1166- 18000b8: 4e 80 00 20 blr
1167-#pass
1168\ No newline at end of file
1169+0+18000[0-9a-f]{2} <__tls_get_addr>:
1170+ 18000[0-9a-f]{2}: 4e 80 00 20 blr
1171+#pass
1172--- binutils-2.22/ld/testsuite/ld-powerpc/tlsopt1.d
1173+++ binutils-2.22/ld/testsuite/ld-powerpc/tlsopt1.d
1174@@ -9,17 +9,17 @@
1175
1176 Disassembly of section \.text:
1177
1178-0+100000e8 <\.__tls_get_addr>:
1179- 100000e8: 4e 80 00 20 blr
1180+0+10000[0-9a-f]{3} <\.__tls_get_addr>:
1181+ 10000[0-9a-f]{3}: 4e 80 00 20 blr
1182
1183 Disassembly of section \.no_opt1:
1184
1185-0+100000ec <\.no_opt1>:
1186- 100000ec: 38 62 80 08 addi r3,r2,-32760
1187- 100000f0: 2c 24 00 00 cmpdi r4,0
1188- 100000f4: 41 82 00 10 beq- .*
1189- 100000f8: 4b ff ff f1 bl 100000e8 <\.__tls_get_addr>
1190- 100000fc: 60 00 00 00 nop
1191- 10000100: 48 00 00 0c b .*
1192- 10000104: 4b ff ff e5 bl 100000e8 <\.__tls_get_addr>
1193- 10000108: 60 00 00 00 nop
1194+0+10000[0-9a-f]{3} <\.no_opt1>:
1195+ 10000[0-9a-f]{3}: 38 62 80 08 addi r3,r2,-32760
1196+ 10000[0-9a-f]{3}: 2c 24 00 00 cmpdi r4,0
1197+ 10000[0-9a-f]{3}: 41 82 00 10 beq- .*
1198+ 10000[0-9a-f]{3}: 4b ff ff f1 bl 10000[0-9a-f]{3} <\.__tls_get_addr>
1199+ 10000[0-9a-f]{3}: 60 00 00 00 nop
1200+ 10000[0-9a-f]{3}: 48 00 00 0c b .*
1201+ 10000[0-9a-f]{3}: 4b ff ff e5 bl 10000[0-9a-f]{3} <\.__tls_get_addr>
1202+ 10000[0-9a-f]{3}: 60 00 00 00 nop
1203--- binutils-2.22/ld/testsuite/ld-powerpc/tlsopt1_32.d
1204+++ binutils-2.22/ld/testsuite/ld-powerpc/tlsopt1_32.d
1205@@ -9,16 +9,16 @@
1206
1207 Disassembly of section \.text:
1208
1209-0+1800094 <__tls_get_addr>:
1210- 1800094: 4e 80 00 20 blr
1211+0+18000[0-9a-f]{2} <__tls_get_addr>:
1212+ 18000[0-9a-f]{2}: 4e 80 00 20 blr
1213
1214 Disassembly of section \.no_opt1:
1215
1216-0+1800098 <\.no_opt1>:
1217- 1800098: 38 6d ff f4 addi r3,r13,-12
1218- 180009c: 2c 04 00 00 cmpwi r4,0
1219- 18000a0: 41 82 00 0c beq- .*
1220- 18000a4: 4b ff ff f1 bl 1800094 <__tls_get_addr>
1221- 18000a8: 48 00 00 08 b .*
1222- 18000ac: 4b ff ff e9 bl 1800094 <__tls_get_addr>
1223+0+18000[0-9a-f]{2} <\.no_opt1>:
1224+ 18000[0-9a-f]{2}: 38 6d ff f4 addi r3,r13,-12
1225+ 18000[0-9a-f]{2}: 2c 04 00 00 cmpwi r4,0
1226+ 18000[0-9a-f]{2}: 41 82 00 0c beq- .*
1227+ 18000[0-9a-f]{2}: 4b ff ff f1 bl 18000[0-9a-f]{2} <__tls_get_addr>
1228+ 18000[0-9a-f]{2}: 48 00 00 08 b .*
1229+ 18000[0-9a-f]{2}: 4b ff ff e9 bl 18000[0-9a-f]{2} <__tls_get_addr>
1230 #pass
1231--- binutils-2.22/ld/testsuite/ld-powerpc/tlsopt2.d
1232+++ binutils-2.22/ld/testsuite/ld-powerpc/tlsopt2.d
1233@@ -9,15 +9,15 @@
1234
1235 Disassembly of section \.text:
1236
1237-0+100000e8 <\.__tls_get_addr>:
1238- 100000e8: 4e 80 00 20 blr
1239+0+10000[0-9a-f]{3} <\.__tls_get_addr>:
1240+ 10000[0-9a-f]{3}: 4e 80 00 20 blr
1241
1242 Disassembly of section \.no_opt2:
1243
1244-0+100000ec <\.no_opt2>:
1245- 100000ec: 38 62 80 08 addi r3,r2,-32760
1246- 100000f0: 2c 24 00 00 cmpdi r4,0
1247- 100000f4: 41 82 00 08 beq- .*
1248- 100000f8: 38 62 80 08 addi r3,r2,-32760
1249- 100000fc: 4b ff ff ed bl 100000e8 <\.__tls_get_addr>
1250- 10000100: 60 00 00 00 nop
1251+0+10000[0-9a-f]{3} <\.no_opt2>:
1252+ 10000[0-9a-f]{3}: 38 62 80 08 addi r3,r2,-32760
1253+ 10000[0-9a-f]{3}: 2c 24 00 00 cmpdi r4,0
1254+ 10000[0-9a-f]{3}: 41 82 00 08 beq- .*
1255+ 10000[0-9a-f]{3}: 38 62 80 08 addi r3,r2,-32760
1256+ 10000[0-9a-f]{3}: 4b ff ff ed bl 10000[0-9a-f]{3} <\.__tls_get_addr>
1257+ 10000[0-9a-f]{3}: 60 00 00 00 nop
1258--- binutils-2.22/ld/testsuite/ld-powerpc/tlsopt2_32.d
1259+++ binutils-2.22/ld/testsuite/ld-powerpc/tlsopt2_32.d
1260@@ -9,15 +9,15 @@
1261
1262 Disassembly of section \.text:
1263
1264-0+1800094 <__tls_get_addr>:
1265- 1800094: 4e 80 00 20 blr
1266+0+18000[0-9a-f]{2} <__tls_get_addr>:
1267+ 18000[0-9a-f]{2}: 4e 80 00 20 blr
1268
1269 Disassembly of section \.no_opt2:
1270
1271-0+1800098 <\.no_opt2>:
1272- 1800098: 38 6d ff f4 addi r3,r13,-12
1273- 180009c: 2c 04 00 00 cmpwi r4,0
1274- 18000a0: 41 82 00 08 beq- .*
1275- 18000a4: 38 6d ff f4 addi r3,r13,-12
1276- 18000a8: 4b ff ff ed bl 1800094 <__tls_get_addr>
1277+0+18000[0-9a-f]{2} <\.no_opt2>:
1278+ 18000[0-9a-f]{2}: 38 6d ff f4 addi r3,r13,-12
1279+ 18000[0-9a-f]{2}: 2c 04 00 00 cmpwi r4,0
1280+ 18000[0-9a-f]{2}: 41 82 00 08 beq- .*
1281+ 18000[0-9a-f]{2}: 38 6d ff f4 addi r3,r13,-12
1282+ 18000[0-9a-f]{2}: 4b ff ff ed bl 18000[0-9a-f]{2} <__tls_get_addr>
1283 #pass
1284--- binutils-2.22/ld/testsuite/ld-powerpc/tlsopt3.d
1285+++ binutils-2.22/ld/testsuite/ld-powerpc/tlsopt3.d
1286@@ -9,18 +9,18 @@
1287
1288 Disassembly of section \.text:
1289
1290-00000000100000e8 <\.__tls_get_addr>:
1291- 100000e8: 4e 80 00 20 blr
1292+0000000010000[0-9a-f]{3} <\.__tls_get_addr>:
1293+ 10000[0-9a-f]{3}: 4e 80 00 20 blr
1294
1295 Disassembly of section \.no_opt3:
1296
1297-00000000100000ec <\.no_opt3>:
1298- 100000ec: 38 62 80 08 addi r3,r2,-32760
1299- 100000f0: 48 00 00 0c b .*
1300- 100000f4: 38 62 80 18 addi r3,r2,-32744
1301- 100000f8: 48 00 00 10 b .*
1302- 100000fc: 4b ff ff ed bl 100000e8 <\.__tls_get_addr>
1303- 10000100: 60 00 00 00 nop
1304- 10000104: 48 00 00 0c b .*
1305- 10000108: 4b ff ff e1 bl 100000e8 <\.__tls_get_addr>
1306- 1000010c: 60 00 00 00 nop
1307+0000000010000[0-9a-f]{3} <\.no_opt3>:
1308+ 10000[0-9a-f]{3}: 38 62 80 08 addi r3,r2,-32760
1309+ 10000[0-9a-f]{3}: 48 00 00 0c b .*
1310+ 10000[0-9a-f]{3}: 38 62 80 18 addi r3,r2,-32744
1311+ 10000[0-9a-f]{3}: 48 00 00 10 b .*
1312+ 10000[0-9a-f]{3}: 4b ff ff ed bl 10000[0-9a-f]{3} <\.__tls_get_addr>
1313+ 10000[0-9a-f]{3}: 60 00 00 00 nop
1314+ 10000[0-9a-f]{3}: 48 00 00 0c b .*
1315+ 10000[0-9a-f]{3}: 4b ff ff e1 bl 10000[0-9a-f]{3} <\.__tls_get_addr>
1316+ 10000[0-9a-f]{3}: 60 00 00 00 nop
1317--- binutils-2.22/ld/testsuite/ld-powerpc/tlsopt3_32.d
1318+++ binutils-2.22/ld/testsuite/ld-powerpc/tlsopt3_32.d
1319@@ -9,17 +9,17 @@
1320
1321 Disassembly of section \.text:
1322
1323-0+1800094 <__tls_get_addr>:
1324- 1800094: 4e 80 00 20 blr
1325+0+18000[0-9a-f]{2} <__tls_get_addr>:
1326+ 18000[0-9a-f]{2}: 4e 80 00 20 blr
1327
1328 Disassembly of section \.no_opt3:
1329
1330-0+1800098 <\.no_opt3>:
1331- 1800098: 38 6d ff ec addi r3,r13,-20
1332- 180009c: 48 00 00 0c b .*
1333- 18000a0: 38 6d ff f4 addi r3,r13,-12
1334- 18000a4: 48 00 00 0c b .*
1335- 18000a8: 4b ff ff ed bl 1800094 <__tls_get_addr>
1336- 18000ac: 48 00 00 08 b .*
1337- 18000b0: 4b ff ff e5 bl 1800094 <__tls_get_addr>
1338+0+18000[0-9a-f]{2} <\.no_opt3>:
1339+ 18000[0-9a-f]{2}: 38 6d ff ec addi r3,r13,-20
1340+ 18000[0-9a-f]{2}: 48 00 00 0c b .*
1341+ 18000[0-9a-f]{2}: 38 6d ff f4 addi r3,r13,-12
1342+ 18000[0-9a-f]{2}: 48 00 00 0c b .*
1343+ 18000[0-9a-f]{2}: 4b ff ff ed bl 18000[0-9a-f]{2} <__tls_get_addr>
1344+ 18000[0-9a-f]{2}: 48 00 00 08 b .*
1345+ 18000[0-9a-f]{2}: 4b ff ff e5 bl 18000[0-9a-f]{2} <__tls_get_addr>
1346 #pass
1347--- binutils-2.22/ld/testsuite/ld-powerpc/tlsopt4.d
1348+++ binutils-2.22/ld/testsuite/ld-powerpc/tlsopt4.d
1349@@ -9,40 +9,40 @@
1350
1351 Disassembly of section \.text:
1352
1353-0+100000e8 <\.__tls_get_addr>:
1354- 100000e8: 4e 80 00 20 blr
1355+0+10000[0-9a-f]{3} <\.__tls_get_addr>:
1356+ 10000[0-9a-f]{3}: 4e 80 00 20 blr
1357
1358 Disassembly of section \.opt1:
1359
1360-0+100000ec <\.opt1>:
1361- 100000ec: 3c 6d 00 00 addis r3,r13,0
1362- 100000f0: 2c 24 00 00 cmpdi r4,0
1363- 100000f4: 41 82 00 10 beq- .*
1364- 100000f8: 60 00 00 00 nop
1365- 100000fc: 38 63 90 10 addi r3,r3,-28656
1366- 10000100: 48 00 00 0c b .*
1367- 10000104: 60 00 00 00 nop
1368- 10000108: 38 63 90 10 addi r3,r3,-28656
1369+0+10000[0-9a-f]{3} <\.opt1>:
1370+ 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0
1371+ 10000[0-9a-f]{3}: 2c 24 00 00 cmpdi r4,0
1372+ 10000[0-9a-f]{3}: 41 82 00 10 beq- .*
1373+ 10000[0-9a-f]{3}: 60 00 00 00 nop
1374+ 10000[0-9a-f]{3}: 38 63 90 10 addi r3,r3,-28656
1375+ 10000[0-9a-f]{3}: 48 00 00 0c b .*
1376+ 10000[0-9a-f]{3}: 60 00 00 00 nop
1377+ 10000[0-9a-f]{3}: 38 63 90 10 addi r3,r3,-28656
1378
1379 Disassembly of section \.opt2:
1380
1381-0+1000010c <\.opt2>:
1382- 1000010c: 3c 6d 00 00 addis r3,r13,0
1383- 10000110: 2c 24 00 00 cmpdi r4,0
1384- 10000114: 41 82 00 08 beq- .*
1385- 10000118: 3c 6d 00 00 addis r3,r13,0
1386- 1000011c: 60 00 00 00 nop
1387- 10000120: 38 63 90 10 addi r3,r3,-28656
1388+0+10000[0-9a-f]{3} <\.opt2>:
1389+ 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0
1390+ 10000[0-9a-f]{3}: 2c 24 00 00 cmpdi r4,0
1391+ 10000[0-9a-f]{3}: 41 82 00 08 beq- .*
1392+ 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0
1393+ 10000[0-9a-f]{3}: 60 00 00 00 nop
1394+ 10000[0-9a-f]{3}: 38 63 90 10 addi r3,r3,-28656
1395
1396 Disassembly of section \.opt3:
1397
1398-0+10000124 <\.opt3>:
1399- 10000124: 3c 6d 00 00 addis r3,r13,0
1400- 10000128: 48 00 00 0c b .*
1401- 1000012c: 3c 6d 00 00 addis r3,r13,0
1402- 10000130: 48 00 00 10 b .*
1403- 10000134: 60 00 00 00 nop
1404- 10000138: 38 63 90 10 addi r3,r3,-28656
1405- 1000013c: 48 00 00 0c b .*
1406- 10000140: 60 00 00 00 nop
1407- 10000144: 38 63 90 08 addi r3,r3,-28664
1408+0+10000[0-9a-f]{3} <\.opt3>:
1409+ 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0
1410+ 10000[0-9a-f]{3}: 48 00 00 0c b .*
1411+ 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0
1412+ 10000[0-9a-f]{3}: 48 00 00 10 b .*
1413+ 10000[0-9a-f]{3}: 60 00 00 00 nop
1414+ 10000[0-9a-f]{3}: 38 63 90 10 addi r3,r3,-28656
1415+ 10000[0-9a-f]{3}: 48 00 00 0c b .*
1416+ 10000[0-9a-f]{3}: 60 00 00 00 nop
1417+ 10000[0-9a-f]{3}: 38 63 90 08 addi r3,r3,-28664
1418--- binutils-2.22/ld/testsuite/ld-powerpc/tlsopt4_32.d
1419+++ binutils-2.22/ld/testsuite/ld-powerpc/tlsopt4_32.d
1420@@ -9,36 +9,36 @@
1421
1422 Disassembly of section \.text:
1423
1424-0+1800094 <__tls_get_addr>:
1425- 1800094: 4e 80 00 20 blr
1426+0+18000[0-9a-f]{2} <__tls_get_addr>:
1427+ 18000[0-9a-f]{2}: 4e 80 00 20 blr
1428
1429 Disassembly of section \.opt1:
1430
1431-0+1800098 <\.opt1>:
1432- 1800098: 3c 62 00 00 addis r3,r2,0
1433- 180009c: 2c 04 00 00 cmpwi r4,0
1434- 18000a0: 41 82 00 0c beq- .*
1435- 18000a4: 38 63 90 10 addi r3,r3,-28656
1436- 18000a8: 48 00 00 08 b .*
1437- 18000ac: 38 63 90 10 addi r3,r3,-28656
1438+0+18000[0-9a-f]{2} <\.opt1>:
1439+ 18000[0-9a-f]{2}: 3c 62 00 00 addis r3,r2,0
1440+ 18000[0-9a-f]{2}: 2c 04 00 00 cmpwi r4,0
1441+ 18000[0-9a-f]{2}: 41 82 00 0c beq- .*
1442+ 18000[0-9a-f]{2}: 38 63 90 10 addi r3,r3,-28656
1443+ 18000[0-9a-f]{2}: 48 00 00 08 b .*
1444+ 18000[0-9a-f]{2}: 38 63 90 10 addi r3,r3,-28656
1445
1446 Disassembly of section \.opt2:
1447
1448-0+18000b0 <\.opt2>:
1449- 18000b0: 3c 62 00 00 addis r3,r2,0
1450- 18000b4: 2c 04 00 00 cmpwi r4,0
1451- 18000b8: 41 82 00 08 beq- .*
1452- 18000bc: 3c 62 00 00 addis r3,r2,0
1453- 18000c0: 38 63 90 10 addi r3,r3,-28656
1454+0+18000[0-9a-f]{2} <\.opt2>:
1455+ 18000[0-9a-f]{2}: 3c 62 00 00 addis r3,r2,0
1456+ 18000[0-9a-f]{2}: 2c 04 00 00 cmpwi r4,0
1457+ 18000[0-9a-f]{2}: 41 82 00 08 beq- .*
1458+ 18000[0-9a-f]{2}: 3c 62 00 00 addis r3,r2,0
1459+ 18000[0-9a-f]{2}: 38 63 90 10 addi r3,r3,-28656
1460
1461 Disassembly of section \.opt3:
1462
1463-0+18000c4 <\.opt3>:
1464- 18000c4: 3c 62 00 00 addis r3,r2,0
1465- 18000c8: 48 00 00 0c b .*
1466- 18000cc: 3c 62 00 00 addis r3,r2,0
1467- 18000d0: 48 00 00 0c b .*
1468- 18000d4: 38 63 90 10 addi r3,r3,-28656
1469- 18000d8: 48 00 00 08 b .*
1470- 18000dc: 38 63 90 08 addi r3,r3,-28664
1471+0+18000[0-9a-f]{2} <\.opt3>:
1472+ 18000[0-9a-f]{2}: 3c 62 00 00 addis r3,r2,0
1473+ 18000[0-9a-f]{2}: 48 00 00 0c b .*
1474+ 18000[0-9a-f]{2}: 3c 62 00 00 addis r3,r2,0
1475+ 18000[0-9a-f]{2}: 48 00 00 0c b .*
1476+ 18000[0-9a-f]{2}: 38 63 90 10 addi r3,r3,-28656
1477+ 18000[0-9a-f]{2}: 48 00 00 08 b .*
1478+ 18000[0-9a-f]{2}: 38 63 90 08 addi r3,r3,-28664
1479 #pass
1480--- binutils-2.22/ld/testsuite/ld-powerpc/tlsso32.d
1481+++ binutils-2.22/ld/testsuite/ld-powerpc/tlsso32.d
1482@@ -42,5 +42,5 @@ Disassembly of section \.got:
1483 .* <\.got>:
1484 \.\.\.
1485 .*: 4e 80 00 21 blrl
1486-.*: 00 01 03 ec .*
1487+.*: 00 01 [0-9a-f]{2} [0-9a-f]{2} .*
1488 \.\.\.
1489--- binutils-2.22/ld/testsuite/ld-powerpc/tlsso32.g
1490+++ binutils-2.22/ld/testsuite/ld-powerpc/tlsso32.g
1491@@ -9,5 +9,5 @@
1492 Contents of section \.got:
1493 .* 00000000 00000000 00000000 00000000 .*
1494 .* 00000000 00000000 00000000 00000000 .*
1495-.* 00000000 4e800021 000103ec 00000000 .*
1496+.* 00000000 4e800021 00010[0-9a-f]{3} 00000000 .*
1497 .* 00000000 .*
1498--- binutils-2.22/ld/testsuite/ld-powerpc/tlsso32.r
1499+++ binutils-2.22/ld/testsuite/ld-powerpc/tlsso32.r
1500@@ -35,6 +35,7 @@ Program Headers:
1501 +LOAD .* RWE 0x10000
1502 +DYNAMIC .* RW +0x4
1503 +TLS .* 0x0+1c 0x0+38 R +0x4
1504+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
1505
1506 Section to Segment mapping:
1507 +Segment Sections\.\.\.
1508@@ -42,6 +43,7 @@ Program Headers:
1509 +01 +\.tdata \.dynamic \.got \.plt
1510 +02 +\.dynamic
1511 +03 +\.tdata \.tbss
1512+ +04 +
1513
1514 Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 18 entries:
1515 Offset +Info +Type +Sym\. Value +Symbol's Name \+ Addend
1516@@ -52,9 +54,9 @@ Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 18 entries:
1517 [0-9a-f ]+R_PPC_TPREL16 +0+30 +le0 \+ 0
1518 [0-9a-f ]+R_PPC_TPREL16_HA +0+34 +le1 \+ 0
1519 [0-9a-f ]+R_PPC_TPREL16_LO +0+34 +le1 \+ 0
1520-[0-9a-f ]+R_PPC_TPREL16 +0+103d0 +\.tdata \+ 103e4
1521-[0-9a-f ]+R_PPC_TPREL16_HA +0+103d0 +\.tdata \+ 103e8
1522-[0-9a-f ]+R_PPC_TPREL16_LO +0+103d0 +\.tdata \+ 103e8
1523+[0-9a-f ]+R_PPC_TPREL16 +0+103[df]0 +\.tdata \+ 10[0-9a-f]{3}
1524+[0-9a-f ]+R_PPC_TPREL16_HA +0+103[df]0 +\.tdata \+ 10[0-9a-f]{3}
1525+[0-9a-f ]+R_PPC_TPREL16_LO +0+103[df]0 +\.tdata \+ 10[0-9a-f]{3}
1526 [0-9a-f ]+R_PPC_DTPMOD32 +0+
1527 [0-9a-f ]+R_PPC_DTPREL32 +0+
1528 [0-9a-f ]+R_PPC_DTPMOD32 +0+
1529--- binutils-2.22/ld/testsuite/ld-powerpc/tlstoc.g
1530+++ binutils-2.22/ld/testsuite/ld-powerpc/tlstoc.g
1531@@ -8,8 +8,8 @@
1532 .*: +file format elf64-powerpc
1533
1534 Contents of section \.got:
1535- 100101a0 00000000 00000001 00000000 00000000 .*
1536- 100101b0 00000000 00000001 00000000 00000000 .*
1537- 100101c0 00000000 00000001 00000000 00000000 .*
1538- 100101d0 00000000 00000001 00000000 00000000 .*
1539- 100101e0 ffffffff ffff8060 00000000 00000000 .*
1540+ 10010[0-9a-f]{3} 00000000 00000001 00000000 00000000 .*
1541+ 10010[0-9a-f]{3} 00000000 00000001 00000000 00000000 .*
1542+ 10010[0-9a-f]{3} 00000000 00000001 00000000 00000000 .*
1543+ 10010[0-9a-f]{3} 00000000 00000001 00000000 00000000 .*
1544+ 10010[0-9a-f]{3} ffffffff ffff8060 00000000 00000000 .*
1545--- binutils-2.22/ld/testsuite/ld-powerpc/tlstoc.t
1546+++ binutils-2.22/ld/testsuite/ld-powerpc/tlstoc.t
1547@@ -8,7 +8,7 @@
1548 .*: +file format elf64-powerpc
1549
1550 Contents of section \.tdata:
1551- 10010148 00c0ffee 00000000 12345678 9abcdef0 .*
1552- 10010158 23456789 abcdef01 3456789a bcdef012 .*
1553- 10010168 456789ab cdef0123 56789abc def01234 .*
1554- 10010178 6789abcd ef012345 789abcde f0123456 .*
1555+ 10010180 00c0ffee 00000000 12345678 9abcdef0 .*
1556+ 10010190 23456789 abcdef01 3456789a bcdef012 .*
1557+ 100101a0 456789ab cdef0123 56789abc def01234 .*
1558+ 100101b0 6789abcd ef012345 789abcde f0123456 .*
1559--- binutils-2.22/ld/testsuite/ld-powerpc/tlstocso.g
1560+++ binutils-2.22/ld/testsuite/ld-powerpc/tlstocso.g
1561@@ -7,7 +7,7 @@
1562 .*: +file format elf64-powerpc
1563
1564 Contents of section \.got:
1565-.* 00000000 000186c0 00000000 00000000 .*
1566+.* 00000000 000186f8 00000000 00000000 .*
1567 .* 00000000 00000000 00000000 00000000 .*
1568 .* 00000000 00000000 00000000 00000000 .*
1569 .* 00000000 00000000 00000000 00000000 .*
1570--- binutils-2.22/ld/testsuite/ld-s390/tlsbin.rd
1571+++ binutils-2.22/ld/testsuite/ld-s390/tlsbin.rd
1572@@ -36,13 +36,14 @@ There are [0-9]+ program headers, starting at offset [0-9]+
1573
1574 Program Headers:
1575 +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
1576- +PHDR +0x0+34 0x0+400034 0x0+400034 0x0+c0 0x0+c0 R E 0x4
1577- +INTERP +0x0+f4 0x0+4000f4 0x0+4000f4 0x0+11 0x0+11 R +0x1
1578+ +PHDR +0x0+34 0x0+400034 0x0+400034 0x0+e0 0x0+e0 R E 0x4
1579+ +INTERP +0x0+114 0x0+400114 0x0+400114 0x0+11 0x0+11 R +0x1
1580 .*Requesting program interpreter.*
1581 +LOAD .* R E 0x1000
1582 +LOAD .* RW +0x1000
1583 +DYNAMIC .* RW +0x4
1584 +TLS .* 0x0+60 0x0+a0 R +0x20
1585+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
1586
1587 Section to Segment mapping:
1588 +Segment Sections...
1589@@ -52,6 +53,7 @@ Program Headers:
1590 +03 +.tdata .dynamic .got *
1591 +04 +.dynamic *
1592 +05 +.tdata .tbss *
1593+ +06 +
1594
1595 Relocation section '.rela.dyn' at offset .* contains 4 entries:
1596 Offset +Info +Type +Sym.Value +Sym. Name \+ Addend
1597--- binutils-2.22/ld/testsuite/ld-s390/tlsbin_64.rd
1598+++ binutils-2.22/ld/testsuite/ld-s390/tlsbin_64.rd
1599@@ -36,13 +36,14 @@ There are [0-9]+ program headers, starting at offset [0-9]+
1600
1601 Program Headers:
1602 +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
1603- +PHDR +0x0+40 0x0+80000040 0x0+80000040 0x0+150 0x0+150 R E 0x8
1604- +INTERP +0x0+190 0x0+80000190 0x0+80000190 0x0+11 0x0+11 R +0x1
1605+ +PHDR +0x0+40 0x0+80000040 0x0+80000040 0x0+188 0x0+188 R E 0x8
1606+ +INTERP +0x0+1c8 0x0+800001c8 0x0+800001c8 0x0+11 0x0+11 R +0x1
1607 .*Requesting program interpreter.*
1608 +LOAD .* R E 0x1000
1609 +LOAD .* RW +0x1000
1610 +DYNAMIC .* RW +0x8
1611 +TLS .* 0x0+60 0x0+a0 R +0x20
1612+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
1613
1614 Section to Segment mapping:
1615 +Segment Sections...
1616@@ -52,6 +53,7 @@ Program Headers:
1617 +03 +.tdata .dynamic .got *
1618 +04 +.dynamic *
1619 +05 +.tdata .tbss *
1620+ +06 +
1621
1622 Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 4 entries:
1623 +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
1624--- binutils-2.22/ld/testsuite/ld-s390/tlspic.rd
1625+++ binutils-2.22/ld/testsuite/ld-s390/tlspic.rd
1626@@ -39,6 +39,7 @@ Program Headers:
1627 +LOAD .* RW +0x1000
1628 +DYNAMIC .* RW +0x4
1629 +TLS .* 0x0+60 0x0+80 R +0x20
1630+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
1631
1632 Section to Segment mapping:
1633 +Segment Sections...
1634@@ -46,6 +47,7 @@ Program Headers:
1635 +01 +.tdata .dynamic .got
1636 +02 +.dynamic
1637 +03 +.tdata .tbss
1638+ +04 +
1639
1640 Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 14 entries:
1641 Offset +Info +Type +Sym.Value +Sym. Name \+ Addend
1642--- binutils-2.22/ld/testsuite/ld-s390/tlspic_64.rd
1643+++ binutils-2.22/ld/testsuite/ld-s390/tlspic_64.rd
1644@@ -39,6 +39,7 @@ Program Headers:
1645 +LOAD .* RW +0x1000
1646 +DYNAMIC .* RW +0x8
1647 +TLS .* 0x0+60 0x0+80 R +0x20
1648+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
1649
1650 Section to Segment mapping:
1651 +Segment Sections...
1652@@ -46,6 +47,7 @@ Program Headers:
1653 +01 +.tdata .dynamic .got *
1654 +02 +.dynamic *
1655 +03 +.tdata .tbss *
1656+ +04 +
1657
1658 Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 14 entries:
1659 +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
1660--- binutils-2.22/ld/testsuite/ld-scripts/empty-aligned.d
1661+++ binutils-2.22/ld/testsuite/ld-scripts/empty-aligned.d
1662@@ -8,7 +8,9 @@
1663 Program Headers:
1664 +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg +Align
1665 +LOAD +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ [RWE ]+ +0x[0-9a-f]+
1666+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
1667
1668 Section to Segment mapping:
1669 +Segment Sections\.\.\.
1670 +00 +.text
1671+ +01 +
1672--- binutils-2.22/ld/testsuite/ld-sh/tlsbin-2.d
1673+++ binutils-2.22/ld/testsuite/ld-sh/tlsbin-2.d
1674@@ -44,6 +44,7 @@ Program Headers:
1675 +LOAD.*
1676 +DYNAMIC.*
1677 +TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x0+18 0x0+28 R +0x4
1678+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
1679
1680 Section to Segment mapping:
1681 +Segment Sections\.\.\.
1682@@ -53,6 +54,7 @@ Program Headers:
1683 +03 +\.tdata \.dynamic \.got *
1684 +04 +\.dynamic *
1685 +05 +\.tdata \.tbss *
1686+ +06 +
1687
1688 Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 4 entries:
1689 Offset +Info +Type +Sym\.Value +Sym\. Name \+ Addend
1690--- binutils-2.22/ld/testsuite/ld-sh/tlspic-2.d
1691+++ binutils-2.22/ld/testsuite/ld-sh/tlspic-2.d
1692@@ -32,7 +32,7 @@ Key to Flags:
1693
1694 Elf file type is DYN \(Shared object file\)
1695 Entry point 0x[0-9a-f]+
1696-There are 4 program headers, starting at offset [0-9]+
1697+There are [0-9] program headers, starting at offset [0-9]+
1698
1699 Program Headers:
1700 +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
1701@@ -40,6 +40,7 @@ Program Headers:
1702 +LOAD.*
1703 +DYNAMIC.*
1704 +TLS .* 0x0+18 0x0+20 R +0x4
1705+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
1706
1707 Section to Segment mapping:
1708 +Segment Sections\.\.\.
1709@@ -47,6 +48,7 @@ Program Headers:
1710 +01 +\.tdata \.dynamic \.got *
1711 +02 +\.dynamic *
1712 +03 +\.tdata \.tbss *
1713+ +04 +
1714
1715 Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 10 entries:
1716 Offset +Info +Type +Sym\.Value +Sym\. Name \+ Addend
1717--- binutils-2.22/ld/testsuite/ld-sparc/gotop32.rd
1718+++ binutils-2.22/ld/testsuite/ld-sparc/gotop32.rd
1719@@ -31,6 +31,7 @@ Program Headers:
1720 +LOAD +0x0+ 0x0+ 0x0+ 0x0+2000 0x0+2000 R E 0x10000
1721 +LOAD +0x0+2000 0x0+12000 0x0+12000 0x0+2000 0x0+2000 RW +0x10000
1722 +DYNAMIC +0x0+2000 0x0+12000 0x0+12000 0x0+70 0x0+70 RW +0x4
1723+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
1724 #...
1725
1726 Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 1 entries:
1727--- binutils-2.22/ld/testsuite/ld-sparc/gotop64.rd
1728+++ binutils-2.22/ld/testsuite/ld-sparc/gotop64.rd
1729@@ -31,6 +31,7 @@ Program Headers:
1730 +LOAD +0x0+ 0x0+ 0x0+ 0x0+2000 0x0+2000 R E 0x100000
1731 +LOAD +0x0+2000 0x0+102000 0x0+102000 0x0+2000 0x0+2000 RW +0x100000
1732 +DYNAMIC +0x0+2000 0x0+102000 0x0+102000 0x0+e0 0x0+e0 RW +0x8
1733+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
1734 #...
1735
1736 Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 1 entries:
1737--- binutils-2.22/ld/testsuite/ld-sparc/tlssunbin32.rd
1738+++ binutils-2.22/ld/testsuite/ld-sparc/tlssunbin32.rd
1739@@ -30,13 +30,14 @@ There are [0-9]+ program headers, starting at offset [0-9]+
1740
1741 Program Headers:
1742 +Type +Offset +VirtAddr +PhysAddr +FileSiz MemSiz +Flg Align
1743- +PHDR +0x0+34 0x0+10034 0x0+10034 0x0+c0 0x0+c0 R E 0x4
1744- +INTERP +0x0+f4 0x0+100f4 0x0+100f4 0x0+11 0x0+11 R +0x1
1745+ +PHDR +0x0+34 0x0+10034 0x0+10034 (0x[0-9a-f]+) \1 R E 0x4
1746+ +INTERP +(0x[0-9a-f]+ ){3}0x0+11 0x0+11 R +0x1
1747 .*Requesting program interpreter.*
1748 +LOAD .* R E 0x10000
1749 +LOAD .* RW +0x10000
1750 +DYNAMIC .* RW +0x4
1751 +TLS .* 0x0+1060 0x0+10a0 R +0x4
1752+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
1753 #...
1754
1755 Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 4 entries:
1756--- binutils-2.22/ld/testsuite/ld-sparc/tlssunbin64.rd
1757+++ binutils-2.22/ld/testsuite/ld-sparc/tlssunbin64.rd
1758@@ -30,13 +30,14 @@ There are [0-9]+ program headers, starting at offset [0-9]+
1759
1760 Program Headers:
1761 +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
1762- +PHDR +0x0+40 0x0+100040 0x0+100040 0x0+150 0x0+150 R E 0x8
1763- +INTERP +0x0+190 0x0+100190 0x0+100190 0x0+19 0x0+19 R +0x1
1764+ +PHDR +0x0+40 0x0+100040 0x0+100040 (0x[0-9a-f]+) \1 R E 0x8
1765+ +INTERP +0x0+([0-9a-f]+) (0x0+10+\1) \2 0x0+19 0x0+19 R +0x1
1766 .*Requesting program interpreter.*
1767 +LOAD .* R E 0x100000
1768 +LOAD .* RW +0x100000
1769 +DYNAMIC .* RW +0x8
1770 +TLS .* 0x0+60 0x0+a0 R +0x4
1771+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
1772 #...
1773
1774 Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 4 entries:
1775--- binutils-2.22/ld/testsuite/ld-sparc/tlssunnopic32.rd
1776+++ binutils-2.22/ld/testsuite/ld-sparc/tlssunnopic32.rd
1777@@ -32,6 +32,7 @@ Program Headers:
1778 +LOAD .* RW +0x10000
1779 +DYNAMIC .* RW +0x4
1780 +TLS .* 0x0+ 0x0+24 R +0x4
1781+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
1782 #...
1783
1784 Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 12 entries:
1785--- binutils-2.22/ld/testsuite/ld-sparc/tlssunnopic64.rd
1786+++ binutils-2.22/ld/testsuite/ld-sparc/tlssunnopic64.rd
1787@@ -32,6 +32,7 @@ Program Headers:
1788 +LOAD .* RW +0x100000
1789 +DYNAMIC .* RW +0x8
1790 +TLS .* 0x0+ 0x0+24 R +0x4
1791+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
1792 #...
1793
1794 Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 14 entries:
1795--- binutils-2.22/ld/testsuite/ld-sparc/tlssunpic32.rd
1796+++ binutils-2.22/ld/testsuite/ld-sparc/tlssunpic32.rd
1797@@ -36,6 +36,7 @@ Program Headers:
1798 +LOAD +0x0+2000 0x0+12000 0x0+12000 0x0+184 0x0+184 RWE 0x10000
1799 +DYNAMIC +0x0+2060 0x0+12060 0x0+12060 0x0+98 0x0+98 RW +0x4
1800 +TLS +0x0+2000 0x0+12000 0x0+12000 0x0+60 0x0+80 R +0x4
1801+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
1802 #...
1803
1804 Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 14 entries:
1805--- binutils-2.22/ld/testsuite/ld-sparc/tlssunpic64.rd
1806+++ binutils-2.22/ld/testsuite/ld-sparc/tlssunpic64.rd
1807@@ -36,6 +36,7 @@ Program Headers:
1808 +LOAD +0x0+2000 0x0+102000 0x0+102000 0x0+3a0 0x0+3a0 RWE 0x100000
1809 +DYNAMIC +0x0+2060 0x0+102060 0x0+102060 0x0+130 0x0+130 RW +0x8
1810 +TLS +0x0+2000 0x0+102000 0x0+102000 0x0+60 0x0+80 R +0x4
1811+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
1812 #...
1813
1814 Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 14 entries:
1815--- binutils-2.22/ld/testsuite/ld-x86-64/protected3.d
1816+++ binutils-2.22/ld/testsuite/ld-x86-64/protected3.d
1817@@ -8,6 +8,6 @@
1818 Disassembly of section .text:
1819
1820 0+[a-f0-9]+ <bar>:
1821-[ ]*[a-f0-9]+: 8b 05 [a-f0-9][a-f0-9] 00 [a-f0-9][a-f0-9] 00 mov 0x[a-f0-9]+\(%rip\),%eax # [a-f0-9]+ <foo>
1822+[ ]*[a-f0-9]+: 8b 05 [a-f0-9][a-f0-9] [a-f0-9][a-f0-9] [a-f0-9][a-f0-9] 00 mov 0x[a-f0-9]+\(%rip\),%eax # [a-f0-9]+ <foo>
1823 [ ]*[a-f0-9]+: c3 retq
1824 #pass
1825--- binutils-2.22/ld/testsuite/ld-x86-64/tlsgdesc.rd
1826+++ binutils-2.22/ld/testsuite/ld-x86-64/tlsgdesc.rd
1827@@ -36,12 +36,14 @@ Program Headers:
1828 +LOAD.*
1829 +LOAD.*
1830 +DYNAMIC.*
1831+ +PAX_FLAGS.*
1832
1833 Section to Segment mapping:
1834 +Segment Sections...
1835 +00 +.hash .dynsym .dynstr .rela.dyn .rela.plt .plt .text *
1836 +01 +.dynamic .got .got.plt *
1837 +02 +.dynamic *
1838+ +03 +
1839
1840 Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 8 entries:
1841 +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
1842--- binutils-2.22/ld/testsuite/ld-x86-64/tlspic.rd
1843+++ binutils-2.22/ld/testsuite/ld-x86-64/tlspic.rd
1844@@ -40,6 +40,7 @@ Program Headers:
1845 +LOAD +0x0+11ac 0x0+2011ac 0x0+2011ac 0x0+244 0x0+244 RW +0x200000
1846 +DYNAMIC +0x0+1210 0x0+201210 0x0+201210 0x0+130 0x0+130 RW +0x8
1847 +TLS +0x0+11ac 0x0+2011ac 0x0+2011ac 0x0+60 0x0+80 R +0x1
1848+ +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48]
1849
1850 Section to Segment mapping:
1851 +Segment Sections...
1852@@ -47,6 +48,7 @@ Program Headers:
1853 +01 +.tdata .dynamic .got .got.plt *
1854 +02 +.dynamic *
1855 +03 +.tdata .tbss *
1856+ +04 +
1857
1858 Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 14 entries:
1859 +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
Timo's tree of IPFire 2.x