[people/teissler/ipfire-2.x.git] / src / patches / grsecurity-haswell-32bit-fix.patch

diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h
index 7430027..2124e35 100644
--- a/arch/x86/include/asm/mmu_context.h
+++ b/arch/x86/include/asm/mmu_context.h
@@ -80,7 +80,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
 #if defined(CONFIG_X86_64) && defined(CONFIG_PAX_MEMORY_UDEREF)
 		if (static_cpu_has(X86_FEATURE_PCID)) {
 			if (static_cpu_has(X86_FEATURE_INVPCID)) {
-				unsigned long descriptor[2];
+				u64 descriptor[2];
 				descriptor[0] = PCID_USER;
 				asm volatile(__ASM_INVPCID : : "d"(&descriptor), "a"(INVPCID_SINGLE_CONTEXT) : "memory");
 			} else {
@@ -144,7 +144,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
 #if defined(CONFIG_X86_64) && defined(CONFIG_PAX_MEMORY_UDEREF)
 		if (static_cpu_has(X86_FEATURE_PCID)) {
 			if (static_cpu_has(X86_FEATURE_INVPCID)) {
-				unsigned long descriptor[2];
+				u64 descriptor[2];
 				descriptor[0] = PCID_USER;
 				asm volatile(__ASM_INVPCID : : "d"(&descriptor), "a"(INVPCID_SINGLE_CONTEXT) : "memory");
 			} else {
diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
index 45844c0..ada2172 100644
--- a/arch/x86/include/asm/tlbflush.h
+++ b/arch/x86/include/asm/tlbflush.h
@@ -18,7 +18,7 @@
 static inline void __native_flush_tlb(void)
 {
 	if (static_cpu_has(X86_FEATURE_INVPCID)) {
-		unsigned long descriptor[2];
+		u64 descriptor[2];
 
 		descriptor[0] = PCID_KERNEL;
 		asm volatile(__ASM_INVPCID : : "d"(&descriptor), "a"(INVPCID_ALL_MONGLOBAL) : "memory");
@@ -42,7 +42,7 @@ static inline void __native_flush_tlb(void)
 static inline void __native_flush_tlb_global_irq_disabled(void)
 {
 	if (static_cpu_has(X86_FEATURE_INVPCID)) {
-		unsigned long descriptor[2];
+		u64 descriptor[2];
 
 		descriptor[0] = PCID_KERNEL;
 		asm volatile(__ASM_INVPCID : : "d"(&descriptor), "a"(INVPCID_ALL_GLOBAL) : "memory");
@@ -77,7 +77,7 @@ static inline void __native_flush_tlb_single(unsigned long addr)
 {
 
 	if (static_cpu_has(X86_FEATURE_INVPCID)) {
-		unsigned long descriptor[2];
+		u64 descriptor[2];
 
 		descriptor[0] = PCID_KERNEL;
 		descriptor[1] = addr;
Commit	Line	Data
62667a70 MT	1	diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h
	2	index 7430027..2124e35 100644
	3	--- a/arch/x86/include/asm/mmu_context.h
	4	+++ b/arch/x86/include/asm/mmu_context.h
	5	@@ -80,7 +80,7 @@ static inline void switch_mm(struct mm_struct prev, struct mm_struct next,
	6	#if defined(CONFIG_X86_64) && defined(CONFIG_PAX_MEMORY_UDEREF)
	7	if (static_cpu_has(X86_FEATURE_PCID)) {
	8	if (static_cpu_has(X86_FEATURE_INVPCID)) {
	9	- unsigned long descriptor[2];
	10	+ u64 descriptor[2];
	11	descriptor[0] = PCID_USER;
	12	asm volatile(__ASM_INVPCID : : "d"(&descriptor), "a"(INVPCID_SINGLE_CONTEXT) : "memory");
	13	} else {
	14	@@ -144,7 +144,7 @@ static inline void switch_mm(struct mm_struct prev, struct mm_struct next,
	15	#if defined(CONFIG_X86_64) && defined(CONFIG_PAX_MEMORY_UDEREF)
	16	if (static_cpu_has(X86_FEATURE_PCID)) {
	17	if (static_cpu_has(X86_FEATURE_INVPCID)) {
	18	- unsigned long descriptor[2];
	19	+ u64 descriptor[2];
	20	descriptor[0] = PCID_USER;
	21	asm volatile(__ASM_INVPCID : : "d"(&descriptor), "a"(INVPCID_SINGLE_CONTEXT) : "memory");
	22	} else {
	23	diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
	24	index 45844c0..ada2172 100644
	25	--- a/arch/x86/include/asm/tlbflush.h
	26	+++ b/arch/x86/include/asm/tlbflush.h
	27	@@ -18,7 +18,7 @@
	28	static inline void __native_flush_tlb(void)
	29	{
	30	if (static_cpu_has(X86_FEATURE_INVPCID)) {
	31	- unsigned long descriptor[2];
	32	+ u64 descriptor[2];
	33
	34	descriptor[0] = PCID_KERNEL;
	35	asm volatile(__ASM_INVPCID : : "d"(&descriptor), "a"(INVPCID_ALL_MONGLOBAL) : "memory");
	36	@@ -42,7 +42,7 @@ static inline void __native_flush_tlb(void)
	37	static inline void __native_flush_tlb_global_irq_disabled(void)
	38	{
	39	if (static_cpu_has(X86_FEATURE_INVPCID)) {
	40	- unsigned long descriptor[2];
	41	+ u64 descriptor[2];
	42
	43	descriptor[0] = PCID_KERNEL;
	44	asm volatile(__ASM_INVPCID : : "d"(&descriptor), "a"(INVPCID_ALL_GLOBAL) : "memory");
	45	@@ -77,7 +77,7 @@ static inline void __native_flush_tlb_single(unsigned long addr)
	46	{
	47
	48	if (static_cpu_has(X86_FEATURE_INVPCID)) {
	49	- unsigned long descriptor[2];
	50	+ u64 descriptor[2];
	51
	52	descriptor[0] = PCID_KERNEL;
	53	descriptor[1] = addr;