src/patches/glibc/glibc-rh696472.patch

   1 commit 3d29045b5e8329d97693eda8d98f1d1e60b99c8f
   2 Author: H.J. Lu <hongjiu.lu@intel.com>
   3 Date:   Fri Jun 3 07:01:25 2011 -0400
   4
   5     Assume Intel Core i3/i5/i7 processor if AVX is available
   6
   7 2011-06-02  H.J. Lu  <hongjiu.lu@intel.com>
   8
   9         * sysdeps/x86_64/multiarch/init-arch.c (__init_cpu_features):
  10         Assume Intel Core i3/i5/i7 processor if AVX is available.
  11
  12 diff --git a/sysdeps/x86_64/multiarch/init-arch.c b/sysdeps/x86_64/multiarch/init-arch.c
  13 index 34ec2df..809d105 100644
  14 --- a/sysdeps/x86_64/multiarch/init-arch.c
  15 +++ b/sysdeps/x86_64/multiarch/init-arch.c
  16 @@ -74,6 +74,7 @@ __init_cpu_features (void)
  17         }
  18        else if (family == 0x06)
  19         {
  20 +         ecx = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ecx;
  21           model += extended_model;
  22           switch (model)
  23             {
  24 @@ -83,6 +84,12 @@ __init_cpu_features (void)
  25               __cpu_features.feature[index_Slow_BSF] |= bit_Slow_BSF;
  26               break;
  27
  28 +           default:
  29 +             /* Unknown family 0x06 processors.  Assuming this is one
  30 +                of Core i3/i5/i7 processors if AVX is available.  */
  31 +             if ((ecx & bit_AVX) == 0)
  32 +               break;
  33 +
  34             case 0x1a:
  35             case 0x1e:
  36             case 0x1f: