src/patches/kernel/wandboard/imx/0015-PCI-imx6-Add-support-for-i.MX6-PCIe-controller.patch

   1 Subject: [PATCH 2/2] PCI: imx6: Add support for i.MX6 PCIe controller
   2 From: Sean Cross <xobs@kosagi.com>
   3
   4 Add support for the PCIe port present on the i.MX6 family of controllers.
   5 These use the Synopsis Designware core tied to their own PHY.
   6
   7 Signed-off-by: Sean Cross <xobs@kosagi.com>
   8 Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
   9 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  10 Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
  11 ---
  12  drivers/pci/host/Kconfig                           |   6 +
  13  drivers/pci/host/Makefile                          |   1 +
  14  drivers/pci/host/pci-imx6.c                        | 575 +++++++++++++++++++++
  15  4 files changed, 588 insertions(+), 1 deletion(-)
  16  create mode 100644 drivers/pci/host/pci-imx6.c
  17
  18 --- /dev/null
  19 +++ b/drivers/pci/host/Kconfig
  20 @@ -0,0 +1,13 @@
  21 +menu "PCI host controller drivers"
  22 +      depends on PCI
  23 +
  24 +config PCIE_DW
  25 +      bool
  26 +
  27 +config PCI_IMX6
  28 +       bool "Freescale i.MX6 PCIe controller"
  29 +       depends on SOC_IMX6Q
  30 +       select PCIEPORTBUS
  31 +       select PCIE_DW
  32 +
  33 +endmenu
  34 --- /dev/null
  35 +++ b/drivers/pci/host/Makefile
  36 @@ -0,0 +1,2 @@
  37 +obj-$(CONFIG_PCIE_DW) += pcie-designware.o
  38 +obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
  39 --- /dev/null
  40 +++ b/drivers/pci/host/pci-imx6.c
  41 @@ -0,0 +1,575 @@
  42 +/*
  43 + * PCIe host controller driver for Freescale i.MX6 SoCs
  44 + *
  45 + * Copyright (C) 2013 Kosagi
  46 + *             http://www.kosagi.com
  47 + *
  48 + * Author: Sean Cross <xobs@kosagi.com>
  49 + *
  50 + * This program is free software; you can redistribute it and/or modify
  51 + * it under the terms of the GNU General Public License version 2 as
  52 + * published by the Free Software Foundation.
  53 + */
  54 +
  55 +#include <linux/clk.h>
  56 +#include <linux/delay.h>
  57 +#include <linux/gpio.h>
  58 +#include <linux/kernel.h>
  59 +#include <linux/mfd/syscon.h>
  60 +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  61 +#include <linux/module.h>
  62 +#include <linux/of_gpio.h>
  63 +#include <linux/pci.h>
  64 +#include <linux/platform_device.h>
  65 +#include <linux/regmap.h>
  66 +#include <linux/resource.h>
  67 +#include <linux/signal.h>
  68 +#include <linux/types.h>
  69 +
  70 +#include "pcie-designware.h"
  71 +
  72 +#define to_imx6_pcie(x)        container_of(x, struct imx6_pcie, pp)
  73 +
  74 +struct imx6_pcie {
  75 +       int                     reset_gpio;
  76 +       int                     power_on_gpio;
  77 +       int                     wake_up_gpio;
  78 +       int                     disable_gpio;
  79 +       struct clk              *lvds_gate;
  80 +       struct clk              *sata_ref_100m;
  81 +       struct clk              *pcie_ref_125m;
  82 +       struct clk              *pcie_axi;
  83 +       struct pcie_port        pp;
  84 +       struct regmap           *iomuxc_gpr;
  85 +       void __iomem            *mem_base;
  86 +};
  87 +
  88 +/* PCIe Port Logic registers (memory-mapped) */
  89 +#define PL_OFFSET 0x700
  90 +#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
  91 +#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
  92 +
  93 +#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
  94 +#define PCIE_PHY_CTRL_DATA_LOC 0
  95 +#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
  96 +#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
  97 +#define PCIE_PHY_CTRL_WR_LOC 18
  98 +#define PCIE_PHY_CTRL_RD_LOC 19
  99 +
 100 +#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
 101 +#define PCIE_PHY_STAT_ACK_LOC 16
 102 +
 103 +/* PHY registers (not memory-mapped) */
 104 +#define PCIE_PHY_RX_ASIC_OUT 0x100D
 105 +
 106 +#define PHY_RX_OVRD_IN_LO 0x1005
 107 +#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
 108 +#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
 109 +
 110 +static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
 111 +{
 112 +       u32 val;
 113 +       u32 max_iterations = 10;
 114 +       u32 wait_counter = 0;
 115 +
 116 +       do {
 117 +               val = readl(dbi_base + PCIE_PHY_STAT);
 118 +               val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
 119 +               wait_counter++;
 120 +
 121 +               if (val == exp_val)
 122 +                       return 0;
 123 +
 124 +               udelay(1);
 125 +       } while (wait_counter < max_iterations);
 126 +
 127 +       return -ETIMEDOUT;
 128 +}
 129 +
 130 +static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
 131 +{
 132 +       u32 val;
 133 +       int ret;
 134 +
 135 +       val = addr << PCIE_PHY_CTRL_DATA_LOC;
 136 +       writel(val, dbi_base + PCIE_PHY_CTRL);
 137 +
 138 +       val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
 139 +       writel(val, dbi_base + PCIE_PHY_CTRL);
 140 +
 141 +       ret = pcie_phy_poll_ack(dbi_base, 1);
 142 +       if (ret)
 143 +               return ret;
 144 +
 145 +       val = addr << PCIE_PHY_CTRL_DATA_LOC;
 146 +       writel(val, dbi_base + PCIE_PHY_CTRL);
 147 +
 148 +       ret = pcie_phy_poll_ack(dbi_base, 0);
 149 +       if (ret)
 150 +               return ret;
 151 +
 152 +       return 0;
 153 +}
 154 +
 155 +/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
 156 +static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
 157 +{
 158 +       u32 val, phy_ctl;
 159 +       int ret;
 160 +
 161 +       ret = pcie_phy_wait_ack(dbi_base, addr);
 162 +       if (ret)
 163 +               return ret;
 164 +
 165 +       /* assert Read signal */
 166 +       phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
 167 +       writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
 168 +
 169 +       ret = pcie_phy_poll_ack(dbi_base, 1);
 170 +       if (ret)
 171 +               return ret;
 172 +
 173 +       val = readl(dbi_base + PCIE_PHY_STAT);
 174 +       *data = val & 0xffff;
 175 +
 176 +       /* deassert Read signal */
 177 +       writel(0x00, dbi_base + PCIE_PHY_CTRL);
 178 +
 179 +       ret = pcie_phy_poll_ack(dbi_base, 0);
 180 +       if (ret)
 181 +               return ret;
 182 +
 183 +       return 0;
 184 +}
 185 +
 186 +static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
 187 +{
 188 +       u32 var;
 189 +       int ret;
 190 +
 191 +       /* write addr */
 192 +       /* cap addr */
 193 +       ret = pcie_phy_wait_ack(dbi_base, addr);
 194 +       if (ret)
 195 +               return ret;
 196 +
 197 +       var = data << PCIE_PHY_CTRL_DATA_LOC;
 198 +       writel(var, dbi_base + PCIE_PHY_CTRL);
 199 +
 200 +       /* capture data */
 201 +       var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
 202 +       writel(var, dbi_base + PCIE_PHY_CTRL);
 203 +
 204 +       ret = pcie_phy_poll_ack(dbi_base, 1);
 205 +       if (ret)
 206 +               return ret;
 207 +
 208 +       /* deassert cap data */
 209 +       var = data << PCIE_PHY_CTRL_DATA_LOC;
 210 +       writel(var, dbi_base + PCIE_PHY_CTRL);
 211 +
 212 +       /* wait for ack de-assertion */
 213 +       ret = pcie_phy_poll_ack(dbi_base, 0);
 214 +       if (ret)
 215 +               return ret;
 216 +
 217 +       /* assert wr signal */
 218 +       var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
 219 +       writel(var, dbi_base + PCIE_PHY_CTRL);
 220 +
 221 +       /* wait for ack */
 222 +       ret = pcie_phy_poll_ack(dbi_base, 1);
 223 +       if (ret)
 224 +               return ret;
 225 +
 226 +       /* deassert wr signal */
 227 +       var = data << PCIE_PHY_CTRL_DATA_LOC;
 228 +       writel(var, dbi_base + PCIE_PHY_CTRL);
 229 +
 230 +       /* wait for ack de-assertion */
 231 +       ret = pcie_phy_poll_ack(dbi_base, 0);
 232 +       if (ret)
 233 +               return ret;
 234 +
 235 +       writel(0x0, dbi_base + PCIE_PHY_CTRL);
 236 +
 237 +       return 0;
 238 +}
 239 +
 240 +/*  Added for PCI abort handling */
 241 +static int imx6q_pcie_abort_handler(unsigned long addr,
 242 +               unsigned int fsr, struct pt_regs *regs)
 243 +{
 244 +       /*
 245 +        * If it was an imprecise abort, then we need to correct the
 246 +        * return address to be _after_ the instruction.
 247 +        */
 248 +       if (fsr & (1 << 10))
 249 +               regs->ARM_pc += 4;
 250 +       return 0;
 251 +}
 252 +
 253 +static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
 254 +{
 255 +       struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
 256 +
 257 +       regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 258 +                       IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
 259 +       regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 260 +                       IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
 261 +       regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 262 +                       IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
 263 +
 264 +       gpio_set_value(imx6_pcie->reset_gpio, 0);
 265 +       msleep(100);
 266 +       gpio_set_value(imx6_pcie->reset_gpio, 1);
 267 +
 268 +       return 0;
 269 +}
 270 +
 271 +static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 272 +{
 273 +       struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
 274 +       int ret;
 275 +
 276 +       if (gpio_is_valid(imx6_pcie->power_on_gpio))
 277 +               gpio_set_value(imx6_pcie->power_on_gpio, 1);
 278 +
 279 +       regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 280 +                       IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
 281 +       regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 282 +                       IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
 283 +
 284 +       ret = clk_prepare_enable(imx6_pcie->sata_ref_100m);
 285 +       if (ret) {
 286 +               dev_err(pp->dev, "unable to enable sata_ref_100m\n");
 287 +               goto err_sata_ref;
 288 +       }
 289 +
 290 +       ret = clk_prepare_enable(imx6_pcie->pcie_ref_125m);
 291 +       if (ret) {
 292 +               dev_err(pp->dev, "unable to enable pcie_ref_125m\n");
 293 +               goto err_pcie_ref;
 294 +       }
 295 +
 296 +       ret = clk_prepare_enable(imx6_pcie->lvds_gate);
 297 +       if (ret) {
 298 +               dev_err(pp->dev, "unable to enable lvds_gate\n");
 299 +               goto err_lvds_gate;
 300 +       }
 301 +
 302 +       ret = clk_prepare_enable(imx6_pcie->pcie_axi);
 303 +       if (ret) {
 304 +               dev_err(pp->dev, "unable to enable pcie_axi\n");
 305 +               goto err_pcie_axi;
 306 +       }
 307 +
 308 +       /* allow the clocks to stabilize */
 309 +       usleep_range(200, 500);
 310 +
 311 +       return 0;
 312 +
 313 +err_pcie_axi:
 314 +       clk_disable_unprepare(imx6_pcie->lvds_gate);
 315 +err_lvds_gate:
 316 +       clk_disable_unprepare(imx6_pcie->pcie_ref_125m);
 317 +err_pcie_ref:
 318 +       clk_disable_unprepare(imx6_pcie->sata_ref_100m);
 319 +err_sata_ref:
 320 +       return ret;
 321 +
 322 +}
 323 +
 324 +static void imx6_pcie_init_phy(struct pcie_port *pp)
 325 +{
 326 +       struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
 327 +
 328 +       regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 329 +                       IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
 330 +
 331 +       /* configure constant input signal to the pcie ctrl and phy */
 332 +       regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 333 +                       IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
 334 +       regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 335 +                       IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
 336 +
 337 +       regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 338 +                       IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0);
 339 +       regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 340 +                       IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6);
 341 +       regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 342 +                       IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12);
 343 +       regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 344 +                       IMX6Q_GPR8_TX_SWING_FULL, 127 << 18);
 345 +       regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 346 +                       IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
 347 +}
 348 +
 349 +static void imx6_pcie_host_init(struct pcie_port *pp)
 350 +{
 351 +       int count = 0;
 352 +       struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
 353 +
 354 +       imx6_pcie_assert_core_reset(pp);
 355 +
 356 +       imx6_pcie_init_phy(pp);
 357 +
 358 +       imx6_pcie_deassert_core_reset(pp);
 359 +
 360 +       dw_pcie_setup_rc(pp);
 361 +
 362 +       regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 363 +                       IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
 364 +
 365 +       while (!dw_pcie_link_up(pp)) {
 366 +               usleep_range(100, 1000);
 367 +               count++;
 368 +               if (count >= 10) {
 369 +                       dev_err(pp->dev, "phy link never came up\n");
 370 +                       dev_dbg(pp->dev,
 371 +                               "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
 372 +                               readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
 373 +                               readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
 374 +                       break;
 375 +               }
 376 +       }
 377 +
 378 +       return;
 379 +}
 380 +
 381 +static int imx6_pcie_link_up(struct pcie_port *pp)
 382 +{
 383 +       u32 rc, ltssm, rx_valid, temp;
 384 +
 385 +       /* link is debug bit 36, debug register 1 starts at bit 32 */
 386 +       rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & (0x1 << (36 - 32));
 387 +       if (rc)
 388 +               return -EAGAIN;
 389 +
 390 +       /*
 391 +        * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
 392 +        * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
 393 +        * If (MAC/LTSSM.state == Recovery.RcvrLock)
 394 +        * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
 395 +        * to gen2 is stuck
 396 +        */
 397 +       pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
 398 +       ltssm = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;
 399 +
 400 +       if (rx_valid & 0x01)
 401 +               return 0;
 402 +
 403 +       if (ltssm != 0x0d)
 404 +               return 0;
 405 +
 406 +       dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
 407 +
 408 +       pcie_phy_read(pp->dbi_base,
 409 +               PHY_RX_OVRD_IN_LO, &temp);
 410 +       temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN
 411 +               | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
 412 +       pcie_phy_write(pp->dbi_base,
 413 +               PHY_RX_OVRD_IN_LO, temp);
 414 +
 415 +       usleep_range(2000, 3000);
 416 +
 417 +       pcie_phy_read(pp->dbi_base,
 418 +               PHY_RX_OVRD_IN_LO, &temp);
 419 +       temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN
 420 +               | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
 421 +       pcie_phy_write(pp->dbi_base,
 422 +               PHY_RX_OVRD_IN_LO, temp);
 423 +
 424 +       return 0;
 425 +}
 426 +
 427 +static struct pcie_host_ops imx6_pcie_host_ops = {
 428 +       .link_up = imx6_pcie_link_up,
 429 +       .host_init = imx6_pcie_host_init,
 430 +};
 431 +
 432 +static int imx6_add_pcie_port(struct pcie_port *pp,
 433 +                       struct platform_device *pdev)
 434 +{
 435 +       int ret;
 436 +
 437 +       pp->irq = platform_get_irq(pdev, 0);
 438 +       if (!pp->irq) {
 439 +               dev_err(&pdev->dev, "failed to get irq\n");
 440 +               return -ENODEV;
 441 +       }
 442 +
 443 +       pp->root_bus_nr = -1;
 444 +       pp->ops = &imx6_pcie_host_ops;
 445 +
 446 +       spin_lock_init(&pp->conf_lock);
 447 +       ret = dw_pcie_host_init(pp);
 448 +       if (ret) {
 449 +               dev_err(&pdev->dev, "failed to initialize host\n");
 450 +               return ret;
 451 +       }
 452 +
 453 +       return 0;
 454 +}
 455 +
 456 +static int __init imx6_pcie_probe(struct platform_device *pdev)
 457 +{
 458 +       struct imx6_pcie *imx6_pcie;
 459 +       struct pcie_port *pp;
 460 +       struct device_node *np = pdev->dev.of_node;
 461 +       struct resource *dbi_base;
 462 +       int ret;
 463 +
 464 +       imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL);
 465 +       if (!imx6_pcie)
 466 +               return -ENOMEM;
 467 +
 468 +       pp = &imx6_pcie->pp;
 469 +       pp->dev = &pdev->dev;
 470 +
 471 +       /* Added for PCI abort handling */
 472 +       hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
 473 +               "imprecise external abort");
 474 +
 475 +       dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 476 +       if (!dbi_base) {
 477 +               dev_err(&pdev->dev, "dbi_base memory resource not found\n");
 478 +               return -ENODEV;
 479 +       }
 480 +
 481 +       pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
 482 +       if (IS_ERR(pp->dbi_base)) {
 483 +               dev_err(&pdev->dev, "unable to remap dbi_base\n");
 484 +               ret = PTR_ERR(pp->dbi_base);
 485 +               goto err;
 486 +       }
 487 +
 488 +       /* Fetch GPIOs */
 489 +       imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
 490 +       if (!gpio_is_valid(imx6_pcie->reset_gpio)) {
 491 +               dev_err(&pdev->dev, "no reset-gpio defined\n");
 492 +               ret = -ENODEV;
 493 +       }
 494 +       ret = devm_gpio_request_one(&pdev->dev,
 495 +                               imx6_pcie->reset_gpio,
 496 +                               GPIOF_OUT_INIT_LOW,
 497 +                               "PCIe reset");
 498 +       if (ret) {
 499 +               dev_err(&pdev->dev, "unable to get reset gpio\n");
 500 +               goto err;
 501 +       }
 502 +
 503 +       imx6_pcie->power_on_gpio = of_get_named_gpio(np, "power-on-gpio", 0);
 504 +       if (gpio_is_valid(imx6_pcie->power_on_gpio)) {
 505 +               ret = devm_gpio_request_one(&pdev->dev,
 506 +                                       imx6_pcie->power_on_gpio,
 507 +                                       GPIOF_OUT_INIT_LOW,
 508 +                                       "PCIe power enable");
 509 +               if (ret) {
 510 +                       dev_err(&pdev->dev, "unable to get power-on gpio\n");
 511 +                       goto err;
 512 +               }
 513 +       }
 514 +
 515 +       imx6_pcie->wake_up_gpio = of_get_named_gpio(np, "wake-up-gpio", 0);
 516 +       if (gpio_is_valid(imx6_pcie->wake_up_gpio)) {
 517 +               ret = devm_gpio_request_one(&pdev->dev,
 518 +                                       imx6_pcie->wake_up_gpio,
 519 +                                       GPIOF_IN,
 520 +                                       "PCIe wake up");
 521 +               if (ret) {
 522 +                       dev_err(&pdev->dev, "unable to get wake-up gpio\n");
 523 +                       goto err;
 524 +               }
 525 +       }
 526 +
 527 +       imx6_pcie->disable_gpio = of_get_named_gpio(np, "disable-gpio", 0);
 528 +       if (gpio_is_valid(imx6_pcie->disable_gpio)) {
 529 +               ret = devm_gpio_request_one(&pdev->dev,
 530 +                                       imx6_pcie->disable_gpio,
 531 +                                       GPIOF_OUT_INIT_HIGH,
 532 +                                       "PCIe disable endpoint");
 533 +               if (ret) {
 534 +                       dev_err(&pdev->dev, "unable to get disable-ep gpio\n");
 535 +                       goto err;
 536 +               }
 537 +       }
 538 +
 539 +       /* Fetch clocks */
 540 +       imx6_pcie->lvds_gate = devm_clk_get(&pdev->dev, "lvds_gate");
 541 +       if (IS_ERR(imx6_pcie->lvds_gate)) {
 542 +               dev_err(&pdev->dev,
 543 +                       "lvds_gate clock select missing or invalid\n");
 544 +               ret = PTR_ERR(imx6_pcie->lvds_gate);
 545 +               goto err;
 546 +       }
 547 +
 548 +       imx6_pcie->sata_ref_100m = devm_clk_get(&pdev->dev, "sata_ref_100m");
 549 +       if (IS_ERR(imx6_pcie->sata_ref_100m)) {
 550 +               dev_err(&pdev->dev,
 551 +                       "sata_ref_100m clock source missing or invalid\n");
 552 +               ret = PTR_ERR(imx6_pcie->sata_ref_100m);
 553 +               goto err;
 554 +       }
 555 +
 556 +       imx6_pcie->pcie_ref_125m = devm_clk_get(&pdev->dev, "pcie_ref_125m");
 557 +       if (IS_ERR(imx6_pcie->pcie_ref_125m)) {
 558 +               dev_err(&pdev->dev,
 559 +                       "pcie_ref_125m clock source missing or invalid\n");
 560 +               ret = PTR_ERR(imx6_pcie->pcie_ref_125m);
 561 +               goto err;
 562 +       }
 563 +
 564 +       imx6_pcie->pcie_axi = devm_clk_get(&pdev->dev, "pcie_axi");
 565 +       if (IS_ERR(imx6_pcie->pcie_axi)) {
 566 +               dev_err(&pdev->dev,
 567 +                       "pcie_axi clock source missing or invalid\n");
 568 +               ret = PTR_ERR(imx6_pcie->pcie_axi);
 569 +               goto err;
 570 +       }
 571 +
 572 +       /* Grab GPR config register range */
 573 +       imx6_pcie->iomuxc_gpr =
 574 +                syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
 575 +       if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
 576 +               dev_err(&pdev->dev, "unable to find iomuxc registers\n");
 577 +               ret = PTR_ERR(imx6_pcie->iomuxc_gpr);
 578 +               goto err;
 579 +       }
 580 +
 581 +       ret = imx6_add_pcie_port(pp, pdev);
 582 +       if (ret < 0)
 583 +               goto err;
 584 +
 585 +       platform_set_drvdata(pdev, imx6_pcie);
 586 +       return 0;
 587 +
 588 +err:
 589 +       return ret;
 590 +}
 591 +
 592 +static const struct of_device_id imx6_pcie_of_match[] = {
 593 +       { .compatible = "fsl,imx6q-pcie", },
 594 +       {},
 595 +};
 596 +MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);
 597 +
 598 +static struct platform_driver imx6_pcie_driver = {
 599 +       .driver = {
 600 +               .name   = "imx6q-pcie",
 601 +               .owner  = THIS_MODULE,
 602 +               .of_match_table = of_match_ptr(imx6_pcie_of_match),
 603 +       },
 604 +};
 605 +
 606 +/* Freescale PCIe driver does not allow module unload */
 607 +
 608 +static int __init imx6_pcie_init(void)
 609 +{
 610 +       return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
 611 +}
 612 +module_init(imx6_pcie_init);
 613 +
 614 +MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
 615 +MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
 616 +MODULE_LICENSE("GPL v2");