src/patches/suse-2.6.27.31/patches.drivers/r8169-add-8168-8101-registers-description

   1 Commit-Id: f162a5d1b326d54b0be7e3100f69763d8a707721
   2 From: Francois Romieu <romieu@fr.zoreil.com>
   3 Date: Sun, 1 Jun 2008 22:37:49 +0200
   4 Acked-by: Karsten Keil <kkeil@novell.com>
   5 Reference: bnc#448168
   6 Subject: [PATCH] r8169: add 8168/8101 registers description
   7
   8 Signed-off-by: Francois Romieu <romieu@fr.zoreil.com>
   9 Cc: Edward Hsu <edward_hsu@realtek.com.tw>
  10
  11 ---
  12  drivers/net/r8169.c |   47 +++++++++++++++++++++++++++++++++++++++++++----
  13  1 file changed, 43 insertions(+), 4 deletions(-)
  14
  15 --- a/drivers/net/r8169.c
  16 +++ b/drivers/net/r8169.c
  17 @@ -196,9 +196,6 @@ enum rtl_registers {
  18         Config5         = 0x56,
  19         MultiIntr       = 0x5c,
  20         PHYAR           = 0x60,
  21 -       TBICSR          = 0x64,
  22 -       TBI_ANAR        = 0x68,
  23 -       TBI_LPAR        = 0x6a,
  24         PHYstatus       = 0x6c,
  25         RxMaxSize       = 0xda,
  26         CPlusCmd        = 0xe0,
  27 @@ -212,6 +209,32 @@ enum rtl_registers {
  28         FuncForceEvent  = 0xfc,
  29  };
  30
  31 +enum rtl8110_registers {
  32 +       TBICSR                  = 0x64,
  33 +       TBI_ANAR                = 0x68,
  34 +       TBI_LPAR                = 0x6a,
  35 +};
  36 +
  37 +enum rtl8168_8101_registers {
  38 +       CSIDR                   = 0x64,
  39 +       CSIAR                   = 0x68,
  40 +#define        CSIAR_FLAG                      0x80000000
  41 +#define        CSIAR_WRITE_CMD                 0x80000000
  42 +#define        CSIAR_BYTE_ENABLE               0x0f
  43 +#define        CSIAR_BYTE_ENABLE_SHIFT         12
  44 +#define        CSIAR_ADDR_MASK                 0x0fff
  45 +
  46 +       EPHYAR                  = 0x80,
  47 +#define        EPHYAR_FLAG                     0x80000000
  48 +#define        EPHYAR_WRITE_CMD                0x80000000
  49 +#define        EPHYAR_REG_MASK                 0x1f
  50 +#define        EPHYAR_REG_SHIFT                16
  51 +#define        EPHYAR_DATA_MASK                0xffff
  52 +       DBG_REG                 = 0xd1,
  53 +#define        FIX_NAK_1                       (1 << 4)
  54 +#define        FIX_NAK_2                       (1 << 3)
  55 +};
  56 +
  57  enum rtl_register_content {
  58         /* InterruptStatusBits */
  59         SYSErr          = 0x8000,
  60 @@ -265,7 +288,13 @@ enum rtl_register_content {
  61         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
  62
  63         /* Config1 register p.24 */
  64 +       LEDS1           = (1 << 7),
  65 +       LEDS0           = (1 << 6),
  66         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
  67 +       Speed_down      = (1 << 4),
  68 +       MEMMAP          = (1 << 3),
  69 +       IOMAP           = (1 << 2),
  70 +       VPD             = (1 << 1),
  71         PMEnable        = (1 << 0),     /* Power Management Enable */
  72
  73         /* Config2 register p. 25 */
  74 @@ -275,6 +304,7 @@ enum rtl_register_content {
  75         /* Config3 register p.25 */
  76         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
  77         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
  78 +       Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
  79
  80         /* Config5 register p.27 */
  81         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
  82 @@ -292,7 +322,16 @@ enum rtl_register_content {
  83         TBINwComplete   = 0x01000000,
  84
  85         /* CPlusCmd p.31 */
  86 -       PktCntrDisable  = (1 << 7),     // 8168
  87 +       EnableBist      = (1 << 15),    // 8168 8101
  88 +       Mac_dbgo_oe     = (1 << 14),    // 8168 8101
  89 +       Normal_mode     = (1 << 13),    // unused
  90 +       Force_half_dup  = (1 << 12),    // 8168 8101
  91 +       Force_rxflow_en = (1 << 11),    // 8168 8101
  92 +       Force_txflow_en = (1 << 10),    // 8168 8101
  93 +       Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
  94 +       ASF             = (1 << 8),     // 8168 8101
  95 +       PktCntrDisable  = (1 << 7),     // 8168 8101
  96 +       Mac_dbgo_sel    = 0x001c,       // 8168
  97         RxVlan          = (1 << 6),
  98         RxChkSum        = (1 << 5),
  99         PCIDAC          = (1 << 4),