Merge branch 'fifteen' of ssh://git.ipfire.org/pub/git/ipfire-2.x into fifteen

diff --git a/config/firewall/convert-outgoingfw b/config/firewall/convert-outgoingfw
index d7722f421b5e9cad484d445032135b220f168121..d2672cbe0bdc3fed67888481c3aebe910665ad05 100755 (executable)
--- a/config/firewall/convert-outgoingfw
+++ b/config/firewall/convert-outgoingfw
@@ -28,6 +28,7 @@
 ###############################################################################
 
 require '/var/ipfire/general-functions.pl';
+require "${General::swroot}/lang.pl";
 
 use Socket;
 use File::Path;
@@ -66,6 +67,7 @@ my @active= ('Aktiv', 'aktiv', 'Active', 'Activo', 'Actif', 'Actief', 'Aktywne',
 &General::readhash("${General::swroot}/ovpn/settings", \%ovpnSettings);
 &General::readhash($outfwsettings,\%outsettings);
 &General::readhash("${General::swroot}/ethernet/settings", \%ownnet);
+
 #ONLY RUN if /var/ipfire/outgoing exists
 if ( -d "/var/ipfire/outgoing"){
        &process_groups;
@@ -164,6 +166,7 @@ sub new_hostgrp
        my $name; #"converted"
        my $name2;
        my $name3; #custom host/custom net
+       my $mac2;
        foreach my $adr (@hostarray){
                if($run eq 'ip'){
                        my ($ip,$type)                  = split(",",$adr);
@@ -180,17 +183,11 @@ sub new_hostgrp
                                        $hosts{$key}[1] = $type;
                                        $hosts{$key}[2] = $ip;
                                        $hosts{$key}[3] = '';
-                                       $hosts{$key}[4] = 1;
                                        print LOG "->Host (IP) $ip added to custom hosts\n"
                                }else{
                                        print LOG "->Host (IP) $ip already exists in custom hosts\n";
                                        $name="host ";
                                        $name2=$name.$ippart;
-                                       foreach my $key (sort keys %hosts){
-                                               if($hosts{$key}[0] eq $name2){
-                                                       $hosts{$key}[4]++;
-                                               }
-                                       }
                                        $name="host ";
                                        $name2=$name.$ippart;
                                        $name3="Custom Host";
@@ -228,18 +225,12 @@ sub new_hostgrp
                                                $nets{$netkey}[1] = $ippart;
                                                $nets{$netkey}[2] = $subnet;
                                                $nets{$netkey}[3] = '';
-                                               $nets{$netkey}[4] = 1;
                                                print LOG "->Network $ippart/$subnet added to custom networks\n";
                                        }
                                }else{
                                        print LOG "Network $ippart already exists in custom networks\n";
                                        $name="net ";
                                        $name2=$name.$ippart;
-                                       foreach my $key (sort keys %nets){
-                                               if($nets{$key}[0] eq $name2){
-                                                       $nets{$key}[4]++;
-                                               }
-                                       }
                                        $name="net ";
                                        $name2=$name.$ippart;
                                        $name3="Custom Network";
@@ -251,35 +242,29 @@ sub new_hostgrp
                                $groups{$grpkey}[1]     = '';
                                $groups{$grpkey}[2]     = $name2;
                                $groups{$grpkey}[3]     = $name3;
-                               $groups{$grpkey}[4]     = 0;
                                print LOG "->$name2 added to group $grp\n";
                        }
                }elsif($run eq 'mac'){
                        #MACRUN
-                       my ($mac,$type)                         = split(",",$adr);
+                       my ($mac,$type) = split(",",$adr);
                        print LOG "Processing HOST (MAC) $mac\n";
                        if(!&check_host($mac)){
-                               my $key         = &General::findhasharraykey(\%hosts);
+                               my $key = &General::findhasharraykey(\%hosts);
                                $name="host ";
-                               $name2=$name.$mac;
+                               $mac2=$mac;
+                               $mac2 =~ s/:/-/g;
+                               $name2=$name.$mac2;
                                $name3="Custom Host";
                                $hosts{$key}[0] = $name2;
                                $hosts{$key}[1] = $type;
                                $hosts{$key}[2] = $mac;
-                               $hosts{$key}[3] = '';
-                               $hosts{$key}[4] = 1;
                                print LOG "->Host (MAC) $mac added to custom hosts\n";
                        }else{
+                               $mac2=mac;
+                               $mac2 =~ s/:/-/g;
                                print LOG "->Host (MAC) $mac already exists in custom hosts \n";
                                $name="host ";
-                               $name2=$name.$mac;
-                               foreach my $key (sort keys %hosts){
-                                       if($hosts{$key}[0] eq $name2){
-                                               $hosts{$key}[4]++;
-                                       }
-                               }
-                               $name="host ";
-                               $name2=$name.$mac;
+                               $name2=$name.$mac2;
                                $name3="Custom Host";
                        }
                        if($name2 && !&check_grp($grp,$name2)){
@@ -288,7 +273,6 @@ sub new_hostgrp
                                $groups{$grpkey}[1]     = '';
                                $groups{$grpkey}[2]     = $name2;
                                $groups{$grpkey}[3]     = $name3;
-                               $groups{$grpkey}[4]     = 0;
                                print LOG "->$name2 added to group $grp\n";
                        }
                }
@@ -361,6 +345,8 @@ sub process_rules
        my @lines = <DATEI>;
        foreach my $rule (@lines)
        {
+               &General::readhasharray($fwdfwconfig,\%fwconfig);
+               &General::readhasharray($outfwconfig,\%fwconfigout);
                my $now=localtime;
                chomp($rule);
                $port='';
@@ -468,7 +454,7 @@ sub process_rules
                        }
                        ############################################################
                        #destinationpart
-                       if($configline[7] ne ''){
+                       if($configline[7] ne '' && $configline[7] ne '0.0.0.0'){
                                my $address=&check_ip($configline[7]);
                                 if($address){
                                         my ($dip,$dsub) = split("/",$address);
@@ -523,8 +509,6 @@ sub process_rules
                }else{
                        print LOG "-> Rule not converted because not for Firewall mode $outsettings{'POLICY'} (we are only converting for actual mode)\n";
                }
-               &General::readhasharray($fwdfwconfig,\%fwconfig);
-               &General::readhasharray($outfwconfig,\%fwconfigout);
                my $check;
                my $chain;
                foreach my $protocol (@prot){
@@ -535,31 +519,18 @@ sub process_rules
                                $chain='FORWARDFW';
                        }
                        $protocol=uc($protocol);
-                       print LOG "$now -> Converted: $action,$chain,$active,$grp1,$source,$grp2,$target,,,,,$useport,$protocol,,$grp3,$port,$remark,$log,$time,$time_mon,$time_tue,$time_wed,$time_thu,$time_fri,$time_sat,$time_sun,$time_from,$time_to\n";
+                       print LOG "$now -> Converted: $action,$chain,$active,$grp1,$source,$grp2,$target,,$protocol,,,$useport,,,$grp3,$port,$remark,$log,$time,$time_mon,$time_tue,$time_wed,$time_thu,$time_fri,$time_sat,$time_sun,$time_from,$time_to\n";
                        #Put rules into system....
                        ###########################
                        #check for double rules
                        foreach my $key (sort keys %fwconfig){
-                               if("$action,$chain,$active,$grp1,$source,$grp2,$target,,,,,$useport,$protocol,,$grp3,$port,$remark,$log,$time,$time_mon,$time_tue,$time_wed,$time_thu,$time_fri,$time_sat,$time_sun,$time_from,$time_to"
-                                       eq "$fwconfig{$key}[0],$fwconfig{$key}[1],$fwconfig{$key}[2],$fwconfig{$key}[3],$fwconfig{$key}[4],$fwconfig{$key}[5],$fwconfig{$key}[6],,,,,$fwconfig{$key}[11],$fwconfig{$key}[12],,$fwconfig{$key}[14],$fwconfig{$key}[15],$fwconfig{$key}[16],$fwconfig{$key}[17],$fwconfig{$key}[18],$fwconfig{$key}[19],$fwconfig{$key}[20],$fwconfig{$key}[21],$fwconfig{$key}[22],$fwconfig{$key}[23],$fwconfig{$key}[24],$fwconfig{$key}[25],$fwconfig{$key}[26],$fwconfig{$key}[27]"){
+                               if("$action,$chain,$active,$grp1,$source,$grp2,$target,$protocol,$useport,$grp3,$port,$remark,$log,$time,$time_mon,$time_tue,$time_wed,$time_thu,$time_fri,$time_sat,$time_sun,$time_from,$time_to"
+                                       eq "$fwconfig{$key}[0],$fwconfig{$key}[1],$fwconfig{$key}[2],$fwconfig{$key}[3],$fwconfig{$key}[4],$fwconfig{$key}[5],$fwconfig{$key}[6],$fwconfig{$key}[8],$fwconfig{$key}[11],$fwconfig{$key}[14],$fwconfig{$key}[15],$fwconfig{$key}[16],$fwconfig{$key}[17],$fwconfig{$key}[18],$fwconfig{$key}[19],$fwconfig{$key}[20],$fwconfig{$key}[21],$fwconfig{$key}[22],$fwconfig{$key}[23],$fwconfig{$key}[24],$fwconfig{$key}[25],$fwconfig{$key}[26],$fwconfig{$key}[27]"){
                                                $check='on';
                                                next;
                                }
                        }
                        if($check ne 'on'){
-                               #increase groupcounter
-                               my $check1;
-                               if($grp1 eq 'cust_grp_src'){
-                                       foreach my $key (sort keys %groups){
-                                               if($groups{$key}[0] eq $source){
-                                                       $groups{$key}[4]++;
-                                                       $check1='on'; 
-                                               }
-                                       }
-                                       if($check1 eq 'on'){
-                                               &General::writehasharray($configgroups,\%groups);
-                                       }
-                               }
                                if ($chain eq 'FORWARDFW'){
                                        my $key = &General::findhasharraykey(\%fwconfig);
                                        $fwconfig{$key}[0]      = $action;
@@ -569,8 +540,8 @@ sub process_rules
                                        $fwconfig{$key}[4]      = $source;
                                        $fwconfig{$key}[5]      = $grp2;
                                        $fwconfig{$key}[6]      = $target;
+                                       $fwconfig{$key}[8] = $protocol;
                                        $fwconfig{$key}[11] = $useport;
-                                       $fwconfig{$key}[12] = $protocol;
                                        $fwconfig{$key}[14] = $grp3;
                                        $fwconfig{$key}[15] = $port;
                                        $fwconfig{$key}[16] = $remark;
@@ -589,6 +560,7 @@ sub process_rules
                                        $fwconfig{$key}[29] = 'ALL';
                                        $fwconfig{$key}[30] = '';
                                        $fwconfig{$key}[31] = 'dnat';
+                                       &General::writehasharray($fwdfwconfig,\%fwconfig);
                                }else{
                                        my $key = &General::findhasharraykey(\%fwconfigout);
                                        $fwconfigout{$key}[0]   = $action;
@@ -598,8 +570,8 @@ sub process_rules
                                        $fwconfigout{$key}[4]   = $source;
                                        $fwconfigout{$key}[5]   = $grp2;
                                        $fwconfigout{$key}[6]   = $target;
+                                       $fwconfigout{$key}[8]   = $protocol;
                                        $fwconfigout{$key}[11]  = $useport;
-                                       $fwconfigout{$key}[12]  = $protocol;
                                        $fwconfigout{$key}[14]  = $grp3;
                                        $fwconfigout{$key}[15]  = $port;
                                        $fwconfigout{$key}[16]  = $remark;
@@ -618,9 +590,8 @@ sub process_rules
                                        $fwconfigout{$key}[29]  = 'ALL';
                                        $fwconfigout{$key}[30]  = '';
                                        $fwconfigout{$key}[31]  = 'dnat';
+                                       &General::writehasharray($outfwconfig,\%fwconfigout);
                                }
-                               &General::writehasharray($fwdfwconfig,\%fwconfig);
-                               &General::writehasharray($outfwconfig,\%fwconfigout);
                        }
                }
                @prot=();
@@ -681,7 +652,6 @@ sub build_ovpn_grp
                        $nets{$netkey}[1] = $net;
                        $nets{$netkey}[2] = $subnet;
                        $nets{$netkey}[3] = '';
-                       $nets{$netkey}[4] = 1;
                        print LOG "$now ->added $name2 $net/$subnet to customnetworks\n";
                }else{
                        print LOG "-> Custom Network with same IP already exist \"$net/$subnet\" (you can ignore this, if this run was manual from shell)\n"; 
@@ -692,7 +662,6 @@ sub build_ovpn_grp
                        $groups{$grpkey}[1]     = '';
                        $groups{$grpkey}[2]     = $name2;
                        $groups{$grpkey}[3]     = "Custom Network";
-                       $groups{$grpkey}[4]     = 0;
                        print LOG "$now ->added $name2 to customgroup ovpn\n";
                }
                $name2='';

diff --git a/config/kernel/kernel.config.armv5tel-ipfire-multi b/config/kernel/kernel.config.armv5tel-ipfire-multi
index adbc6502e016424d74ca9074391cac388584ae48..bb9f21a6d7783ace727da49ffd55a99cbea5872a 100644 (file)
--- a/config/kernel/kernel.config.armv5tel-ipfire-multi
+++ b/config/kernel/kernel.config.armv5tel-ipfire-multi
@@ -5,7 +5,6 @@
 CONFIG_ARM=y
 CONFIG_MIGHT_HAVE_PCI=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_HAVE_TCM=y
 CONFIG_HAVE_PROC_CPU=y
 CONFIG_NO_IOPORT=y
 CONFIG_STACKTRACE_SUPPORT=y
@@ -15,9 +14,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_ARCH_HAS_CPUFREQ=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ZONE_DMA=y
 CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_FIQ=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_ARM_PATCH_PHYS_VIRT=y
 CONFIG_GENERIC_BUG=y
@@ -104,8 +101,8 @@ CONFIG_RCU_USER_QS=y
 CONFIG_CONTEXT_TRACKING_FORCE=y
 CONFIG_RCU_FANOUT=32
 CONFIG_RCU_FANOUT_LEAF=16
-# CONFIG_RCU_FANOUT_EXACT is not set
-CONFIG_RCU_FAST_NO_HZ=y
+CONFIG_RCU_FANOUT_EXACT=y
+# CONFIG_RCU_FAST_NO_HZ is not set
 # CONFIG_TREE_RCU_TRACE is not set
 CONFIG_RCU_NOCB_CPU=y
 # CONFIG_RCU_NOCB_CPU_NONE is not set
@@ -121,7 +118,10 @@ CONFIG_CPUSETS=y
 CONFIG_PROC_PID_CPUSET=y
 CONFIG_CGROUP_CPUACCT=y
 CONFIG_RESOURCE_COUNTERS=y
-# CONFIG_MEMCG is not set
+CONFIG_MEMCG=y
+CONFIG_MEMCG_SWAP=y
+CONFIG_MEMCG_SWAP_ENABLED=y
+CONFIG_MEMCG_KMEM=y
 CONFIG_CGROUP_PERF=y
 CONFIG_CGROUP_SCHED=y
 CONFIG_FAIR_GROUP_SCHED=y
@@ -135,6 +135,7 @@ CONFIG_IPC_NS=y
 CONFIG_PID_NS=y
 CONFIG_NET_NS=y
 CONFIG_SCHED_AUTOGROUP=y
+CONFIG_MM_OWNER=y
 # CONFIG_SYSFS_DEPRECATED is not set
 CONFIG_RELAY=y
 CONFIG_BLK_DEV_INITRD=y
@@ -176,13 +177,14 @@ CONFIG_PERF_USE_VMALLOC=y
 CONFIG_PERF_EVENTS=y
 # CONFIG_DEBUG_PERF_USE_VMALLOC is not set
 CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLUB_DEBUG=y
+# CONFIG_SLUB_DEBUG is not set
 # CONFIG_COMPAT_BRK is not set
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
+CONFIG_PROFILING=y
 CONFIG_TRACEPOINTS=y
+CONFIG_OPROFILE=m
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
 CONFIG_JUMP_LABEL=y
@@ -202,7 +204,6 @@ CONFIG_HAVE_HW_BREAKPOINT=y
 CONFIG_HAVE_ARCH_JUMP_LABEL=y
 CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
 CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_SECCOMP_FILTER=y
 CONFIG_HAVE_CONTEXT_TRACKING=y
 CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
 CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
@@ -216,7 +217,6 @@ CONFIG_OLD_SIGACTION=y
 #
 # CONFIG_GCOV_KERNEL is not set
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
@@ -328,85 +328,37 @@ CONFIG_ARCH_MULTIPLATFORM=y
 #
 # CPU Core family selection
 #
-CONFIG_ARCH_MULTI_V6=y
+# CONFIG_ARCH_MULTI_V6 is not set
 CONFIG_ARCH_MULTI_V7=y
 CONFIG_ARCH_MULTI_V6_V7=y
 # CONFIG_ARCH_MULTI_CPU_AUTO is not set
-CONFIG_ARCH_MVEBU=y
-
-#
-# Marvell SOC with device tree
-#
-CONFIG_MACH_ARMADA_370_XP=y
-CONFIG_MACH_ARMADA_370=y
-CONFIG_MACH_ARMADA_XP=y
-CONFIG_ARCH_BCM=y
-CONFIG_ARCH_BCM2835=y
-CONFIG_ARCH_CNS3XXX=y
-
-#
-# CNS3XXX platform type
-#
-CONFIG_MACH_CNS3420VB=y
+# CONFIG_ARCH_MVEBU is not set
+# CONFIG_ARCH_BCM is not set
 # CONFIG_GPIO_PCA953X is not set
 CONFIG_KEYBOARD_GPIO_POLLED=m
-CONFIG_ARCH_HIGHBANK=y
+# CONFIG_ARCH_HIGHBANK is not set
 CONFIG_ARCH_MXC=y
 
 #
 # Freescale i.MX support
 #
-CONFIG_MXC_IRQ_PRIOR=y
+# CONFIG_MXC_IRQ_PRIOR is not set
 CONFIG_MXC_TZIC=y
-CONFIG_MXC_AVIC=y
-CONFIG_MXC_DEBUG_BOARD=y
-CONFIG_HAVE_EPIT=y
-# CONFIG_MXC_USE_EPIT is not set
-CONFIG_MXC_ULPI=y
-CONFIG_ARCH_HAS_RNGA=y
+# CONFIG_MXC_DEBUG_BOARD is not set
 CONFIG_HAVE_IMX_ANATOP=y
 CONFIG_HAVE_IMX_GPC=y
 CONFIG_HAVE_IMX_MMDC=y
 CONFIG_HAVE_IMX_SRC=y
 CONFIG_ARCH_MXC_IOMUX_V3=y
-CONFIG_SOC_IMX31=y
-CONFIG_SOC_IMX35=y
 CONFIG_SOC_IMX5=y
 CONFIG_SOC_IMX51=y
 
-#
-# MX31 platforms:
-#
-CONFIG_MACH_MX31ADS=y
-CONFIG_MACH_MX31LILLY=y
-CONFIG_MACH_MX31LITE=y
-CONFIG_MACH_PCM037=y
-CONFIG_MACH_PCM037_EET=y
-CONFIG_MACH_MX31_3DS=y
-CONFIG_MACH_MX31_3DS_MXC_NAND_USE_BBT=y
-CONFIG_MACH_MX31MOBOARD=y
-CONFIG_MACH_QONG=y
-CONFIG_MACH_ARMADILLO5X0=y
-CONFIG_MACH_KZM_ARM11_01=y
-CONFIG_MACH_BUG=y
-CONFIG_MACH_IMX31_DT=y
-
-#
-# MX35 platforms:
-#
-CONFIG_MACH_PCM043=y
-CONFIG_MACH_MX35_3DS=y
-CONFIG_MACH_EUKREA_CPUIMX35SD=y
-CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD=y
-CONFIG_MACH_VPR200=y
-
 #
 # i.MX51 machines:
 #
 CONFIG_MACH_IMX51_DT=y
-CONFIG_MACH_MX51_BABBAGE=y
-CONFIG_MACH_EUKREA_CPUIMX51SD=y
-CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD=y
+# CONFIG_MACH_MX51_BABBAGE is not set
+# CONFIG_MACH_EUKREA_CPUIMX51SD is not set
 
 #
 # Device tree only
@@ -414,154 +366,16 @@ CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD=y
 CONFIG_SOC_IMX53=y
 CONFIG_SOC_IMX6Q=y
 CONFIG_IMX_HAVE_PLATFORM_FEC=y
-CONFIG_IMX_HAVE_PLATFORM_FLEXCAN=y
-CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC=y
 CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS=y
 CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_FB=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y
-CONFIG_IMX_HAVE_PLATFORM_IPU_CORE=y
-CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI=y
-CONFIG_IMX_HAVE_PLATFORM_MXC_MMC=y
-CONFIG_IMX_HAVE_PLATFORM_MXC_NAND=y
-CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA=y
-CONFIG_IMX_HAVE_PLATFORM_MXC_RTC=y
-CONFIG_IMX_HAVE_PLATFORM_MXC_W1=y
-CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX=y
-CONFIG_IMX_HAVE_PLATFORM_SPI_IMX=y
-
-#
-# TI OMAP Common Features
-#
-
-#
-# OMAP Feature Selections
-#
-CONFIG_OMAP_DEBUG_DEVICES=y
-CONFIG_OMAP_DEBUG_LEDS=y
-CONFIG_POWER_AVS_OMAP=y
-CONFIG_POWER_AVS_OMAP_CLASS3=y
-CONFIG_OMAP_RESET_CLOCKS=y
-CONFIG_OMAP_MUX=y
-# CONFIG_OMAP_MUX_DEBUG is not set
-CONFIG_OMAP_MUX_WARNINGS=y
-CONFIG_OMAP_32K_TIMER=y
-# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_OMAP_PM_NOOP=y
-CONFIG_MACH_OMAP_GENERIC=y
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP2PLUS=y
-
-#
-# TI OMAP2/3/4 Specific Features
-#
-CONFIG_ARCH_OMAP2PLUS_TYPICAL=y
-CONFIG_SOC_HAS_OMAP2_SDRC=y
-CONFIG_SOC_HAS_REALTIME_COUNTER=y
-CONFIG_ARCH_OMAP2=y
-CONFIG_ARCH_OMAP3=y
-CONFIG_ARCH_OMAP4=y
-CONFIG_SOC_OMAP5=y
-
-#
-# OMAP Core Type
-#
-CONFIG_SOC_OMAP2420=y
-CONFIG_SOC_OMAP2430=y
-CONFIG_SOC_OMAP3430=y
-CONFIG_SOC_TI81XX=y
-CONFIG_SOC_AM33XX=y
-CONFIG_OMAP_PACKAGE_ZAF=y
-CONFIG_OMAP_PACKAGE_ZAC=y
-CONFIG_OMAP_PACKAGE_CBB=y
-CONFIG_OMAP_PACKAGE_CUS=y
-CONFIG_OMAP_PACKAGE_CBP=y
-CONFIG_OMAP_PACKAGE_CBL=y
-CONFIG_OMAP_PACKAGE_CBS=y
-
-#
-# OMAP Board Type
-#
-CONFIG_MACH_OMAP2_TUSB6010=y
-CONFIG_MACH_OMAP_H4=y
-CONFIG_MACH_OMAP_2430SDP=y
-CONFIG_MACH_OMAP3_BEAGLE=y
-CONFIG_MACH_DEVKIT8000=y
-CONFIG_MACH_OMAP_LDP=y
-CONFIG_MACH_OMAP3530_LV_SOM=y
-CONFIG_MACH_OMAP3_TORPEDO=y
-CONFIG_MACH_OVERO=y
-CONFIG_MACH_OMAP3EVM=y
-CONFIG_MACH_OMAP3517EVM=y
-CONFIG_MACH_CRANEBOARD=y
-CONFIG_MACH_OMAP3_PANDORA=y
-CONFIG_MACH_TOUCHBOOK=y
-CONFIG_MACH_OMAP_3430SDP=y
-CONFIG_MACH_NOKIA_N800=y
-CONFIG_MACH_NOKIA_N810=y
-CONFIG_MACH_NOKIA_N810_WIMAX=y
-CONFIG_MACH_NOKIA_N8X0=y
-CONFIG_MACH_NOKIA_RM680=y
-CONFIG_MACH_NOKIA_RX51=y
-CONFIG_MACH_OMAP_ZOOM2=y
-CONFIG_MACH_OMAP_ZOOM3=y
-CONFIG_MACH_CM_T35=y
-CONFIG_MACH_CM_T3517=y
-CONFIG_MACH_CM_T3730=y
-CONFIG_MACH_IGEP0020=y
-CONFIG_MACH_IGEP0030=y
-CONFIG_MACH_SBC3530=y
-CONFIG_MACH_OMAP_3630SDP=y
-CONFIG_MACH_TI8168EVM=y
-CONFIG_MACH_TI8148EVM=y
-CONFIG_MACH_OMAP_4430SDP=y
-CONFIG_MACH_OMAP4_PANDA=y
-CONFIG_OMAP3_EMU=y
-# CONFIG_OMAP3_SDRC_AC_TIMING is not set
-CONFIG_ARCH_PICOXCELL=y
-CONFIG_ARCH_SOCFPGA=y
-CONFIG_PLAT_SPEAR=y
-CONFIG_ARCH_SPEAR13XX=y
-CONFIG_MACH_SPEAR1310=y
-CONFIG_MACH_SPEAR1340=y
-CONFIG_ARCH_SUNXI=y
-CONFIG_ARCH_SIRF=y
-
-#
-# CSR SiRF atlas6/primaII/Marco/Polo Specific Features
-#
-CONFIG_ARCH_ATLAS6=y
-CONFIG_ARCH_PRIMA2=y
-CONFIG_ARCH_MARCO=y
-CONFIG_SIRF_IRQ=y
-CONFIG_ARCH_TEGRA=y
-
-#
-# NVIDIA Tegra options
-#
-CONFIG_ARCH_TEGRA_2x_SOC=y
-CONFIG_ARCH_TEGRA_3x_SOC=y
-CONFIG_ARCH_TEGRA_114_SOC=y
-CONFIG_TEGRA_PCI=y
-CONFIG_TEGRA_AHB=y
-# CONFIG_TEGRA_EMC_SCALING_ENABLE is not set
-CONFIG_ARCH_U8500=y
-CONFIG_UX500_SOC_COMMON=y
-CONFIG_UX500_SOC_DB8500=y
-
-#
-# Ux500 target platform (boards)
-#
-CONFIG_MACH_MOP500=y
-CONFIG_MACH_HREFV60=y
-CONFIG_MACH_SNOWBALL=y
-CONFIG_UX500_AUTO_PLATFORM=y
-CONFIG_MACH_UX500_DT=y
-CONFIG_UX500_DEBUG_UART=2
+CONFIG_WAND_RFKILL=m
+# CONFIG_ARCH_OMAP2PLUS is not set
+# CONFIG_ARCH_SOCFPGA is not set
+# CONFIG_PLAT_SPEAR is not set
+# CONFIG_ARCH_SUNXI is not set
+# CONFIG_ARCH_SIRF is not set
+# CONFIG_ARCH_TEGRA is not set
+# CONFIG_ARCH_U8500 is not set
 CONFIG_ARCH_VEXPRESS=y
 
 #
@@ -573,32 +387,22 @@ CONFIG_PLAT_VERSATILE_CLCD=y
 CONFIG_PLAT_VERSATILE_SCHED_CLOCK=y
 CONFIG_ARCH_VIRT=y
 CONFIG_ARCH_VT8500=y
-CONFIG_ARCH_WM8750=y
 CONFIG_ARCH_WM8850=y
 CONFIG_ARCH_ZYNQ=y
-CONFIG_PLAT_ORION=y
 CONFIG_PLAT_VERSATILE=y
 CONFIG_ARM_TIMER_SP804=y
 
 #
 # Processor Type
 #
-CONFIG_CPU_PJ4B=y
-CONFIG_CPU_V6=y
-CONFIG_CPU_V6K=y
 CONFIG_CPU_V7=y
-CONFIG_CPU_32v6=y
 CONFIG_CPU_32v6K=y
 CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV6=y
 CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_PABRT_V6=y
 CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_CACHE_V6=y
 CONFIG_CPU_CACHE_V7=y
 CONFIG_CPU_CACHE_VIPT=y
 CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_TLB_V6=y
 CONFIG_CPU_TLB_V7=y
 CONFIG_CPU_HAS_ASID=y
 CONFIG_CPU_CP15=y
@@ -607,9 +411,10 @@ CONFIG_CPU_CP15_MMU=y
 #
 # Processor Features
 #
+# CONFIG_ARM_LPAE is not set
 # CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
 CONFIG_ARM_THUMB=y
-# CONFIG_ARM_THUMBEE is not set
+CONFIG_ARM_THUMBEE=y
 CONFIG_ARM_VIRT_EXT=y
 CONFIG_SWP_EMULATE=y
 # CONFIG_CPU_ICACHE_DISABLE is not set
@@ -621,19 +426,18 @@ CONFIG_OUTER_CACHE=y
 CONFIG_OUTER_CACHE_SYNC=y
 CONFIG_MIGHT_HAVE_CACHE_L2X0=y
 CONFIG_CACHE_L2X0=y
+CONFIG_CACHE_PL310=y
 CONFIG_ARM_L1_CACHE_SHIFT_6=y
 CONFIG_ARM_L1_CACHE_SHIFT=6
 CONFIG_ARM_DMA_MEM_BUFFERABLE=y
 CONFIG_ARM_NR_BANKS=8
 CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_PJ4B_ERRATA_4742=y
-# CONFIG_ARM_ERRATA_326103 is not set
-CONFIG_ARM_ERRATA_411920=y
 CONFIG_ARM_ERRATA_430973=y
 CONFIG_PL310_ERRATA_588369=y
 CONFIG_ARM_ERRATA_643719=y
 CONFIG_ARM_ERRATA_720789=y
 CONFIG_PL310_ERRATA_727915=y
+CONFIG_PL310_ERRATA_753970=y
 CONFIG_ARM_ERRATA_754322=y
 CONFIG_ARM_ERRATA_754327=y
 CONFIG_ARM_ERRATA_764369=y
@@ -647,28 +451,21 @@ CONFIG_ICST=y
 #
 CONFIG_ARM_AMBA=y
 CONFIG_PCI=y
+CONFIG_PCIE_DW=y
 CONFIG_PCI_DOMAINS=y
 CONFIG_PCI_SYSCALL=y
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
-CONFIG_PCI_STUB=y
-CONFIG_PCI_ATS=y
-CONFIG_PCI_IOV=y
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
 # CONFIG_PCI_PRI is not set
 # CONFIG_PCI_PASID is not set
-CONFIG_PCCARD=m
-# CONFIG_PCMCIA is not set
-CONFIG_CARDBUS=y
 
 #
-# PC-card bridges
+# PCI host controller drivers
 #
-CONFIG_YENTA=m
-CONFIG_YENTA_O2=y
-CONFIG_YENTA_RICOH=y
-CONFIG_YENTA_TI=y
-CONFIG_YENTA_ENE_TUNE=y
-CONFIG_YENTA_TOSHIBA=y
+CONFIG_PCI_IMX6=y
+# CONFIG_PCCARD is not set
 
 #
 # Kernel Features
@@ -691,41 +488,43 @@ CONFIG_NR_CPUS=8
 CONFIG_HOTPLUG_CPU=y
 CONFIG_ARM_PSCI=y
 CONFIG_LOCAL_TIMERS=y
-CONFIG_ARCH_NR_GPIO=1024
+CONFIG_ARCH_NR_GPIO=352
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
 CONFIG_HZ=100
 CONFIG_SCHED_HRTICK=y
+# CONFIG_THUMB2_KERNEL is not set
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
-CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
 # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
 # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
 CONFIG_HAVE_ARCH_PFN_VALID=y
 CONFIG_HIGHMEM=y
-# CONFIG_HIGHPTE is not set
+CONFIG_HIGHPTE=y
 CONFIG_HW_PERF_EVENTS=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_HAVE_MEMBLOCK=y
+CONFIG_MEMORY_ISOLATION=y
 # CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 CONFIG_COMPACTION=y
 CONFIG_MIGRATION=y
 # CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
+CONFIG_ZONE_DMA_FLAG=0
 CONFIG_BOUNCE=y
 CONFIG_KSM=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_CROSS_MEMORY_ATTACH=y
 CONFIG_CLEANCACHE=y
 # CONFIG_FRONTSWAP is not set
-CONFIG_FORCE_MAX_ZONEORDER=12
+CONFIG_FORCE_MAX_ZONEORDER=11
 CONFIG_ALIGNMENT_TRAP=y
-CONFIG_SECCOMP=y
+# CONFIG_SECCOMP is not set
 CONFIG_CC_STACKPROTECTOR=y
+# CONFIG_XEN is not set
 
 #
 # Boot options
@@ -752,9 +551,38 @@ CONFIG_AUTO_ZRELADDR=y
 #
 # CPU Frequency scaling
 #
-# CONFIG_CPU_FREQ is not set
-# CONFIG_CPU_IDLE is not set
-CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_GENERIC_CPUFREQ_CPU0=y
+
+#
+# ARM CPU frequency scaling drivers
+#
+# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set
+# CONFIG_ARM_EXYNOS4210_CPUFREQ is not set
+# CONFIG_ARM_EXYNOS4X12_CPUFREQ is not set
+# CONFIG_ARM_EXYNOS5250_CPUFREQ is not set
+# CONFIG_ARM_EXYNOS5440_CPUFREQ is not set
+CONFIG_ARM_IMX6Q_CPUFREQ=m
+# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
 
 #
 # Floating point emulation
@@ -1361,10 +1189,10 @@ CONFIG_MAC80211_LEDS=y
 # CONFIG_MAC80211_MESSAGE_TRACING is not set
 # CONFIG_MAC80211_DEBUG_MENU is not set
 # CONFIG_WIMAX is not set
-CONFIG_RFKILL=m
+CONFIG_RFKILL=y
 CONFIG_RFKILL_LEDS=y
 CONFIG_RFKILL_INPUT=y
-# CONFIG_RFKILL_REGULATOR is not set
+CONFIG_RFKILL_REGULATOR=m
 # CONFIG_RFKILL_GPIO is not set
 # CONFIG_NET_9P is not set
 # CONFIG_CAIF is not set
@@ -1385,31 +1213,39 @@ CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_FIRMWARE_IN_KERNEL=y
 CONFIG_EXTRA_FIRMWARE=""
 CONFIG_FW_LOADER_USER_HELPER=y
 # CONFIG_DEBUG_DRIVER is not set
 # CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_GENERIC_CPU_DEVICES is not set
-CONFIG_SOC_BUS=y
 CONFIG_REGMAP=y
 CONFIG_REGMAP_I2C=y
 CONFIG_REGMAP_MMIO=y
 CONFIG_REGMAP_IRQ=y
 CONFIG_DMA_SHARED_BUFFER=y
-# CONFIG_CMA is not set
+CONFIG_CMA=y
+CONFIG_CMA_DEBUG=y
+
+#
+# Default contiguous memory area size:
+#
+CONFIG_CMA_SIZE_MBYTES=16
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
 
 #
 # Bus devices
 #
-CONFIG_MVEBU_MBUS=y
-CONFIG_OMAP_OCP2SCP=m
-CONFIG_OMAP_INTERCONNECT=y
 CONFIG_CONNECTOR=y
 CONFIG_PROC_EVENTS=y
 CONFIG_MTD=y
-CONFIG_MTD_TESTS=m
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_REDBOOT_PARTS is not set
 CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_AFS_PARTS is not set
@@ -1419,14 +1255,15 @@ CONFIG_MTD_OF_PARTS=y
 #
 # User Modules And Translation Layers
 #
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
+# CONFIG_MTD_BLKDEVS is not set
+# CONFIG_MTD_BLOCK is not set
+# CONFIG_MTD_BLOCK_RO is not set
 # CONFIG_FTL is not set
 # CONFIG_NFTL is not set
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
-CONFIG_SM_FTL=m
+# CONFIG_SM_FTL is not set
 # CONFIG_MTD_OOPS is not set
 # CONFIG_MTD_SWAP is not set
 
@@ -1445,7 +1282,7 @@ CONFIG_MTD_CFI_I1=y
 CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_CFI_I4 is not set
 # CONFIG_MTD_CFI_I8 is not set
-CONFIG_MTD_RAM=m
+# CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
 
@@ -1454,15 +1291,14 @@ CONFIG_MTD_RAM=m
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
 # CONFIG_MTD_INTEL_VR_NOR is not set
-CONFIG_MTD_PLATRAM=m
+# CONFIG_MTD_PLATRAM is not set
 
 #
 # Self-contained MTD device drivers
 #
 # CONFIG_MTD_PMC551 is not set
-CONFIG_MTD_SPEAR_SMI=y
-CONFIG_MTD_SLRAM=m
-CONFIG_MTD_PHRAM=m
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
 # CONFIG_MTD_BLOCK2MTD is not set
 
@@ -1471,37 +1307,33 @@ CONFIG_MTD_PHRAM=m
 #
 # CONFIG_MTD_DOCG3 is not set
 CONFIG_MTD_NAND_ECC=y
-# CONFIG_MTD_NAND_ECC_SMC is not set
+CONFIG_MTD_NAND_ECC_SMC=y
 CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_ECC_BCH is not set
 # CONFIG_MTD_SM_COMMON is not set
 # CONFIG_MTD_NAND_DENALI is not set
 # CONFIG_MTD_NAND_GPIO is not set
-CONFIG_MTD_NAND_OMAP2=y
-# CONFIG_MTD_NAND_OMAP_BCH is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_RICOH is not set
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 # CONFIG_MTD_NAND_DOCG4 is not set
 # CONFIG_MTD_NAND_CAFE is not set
 # CONFIG_MTD_NAND_NANDSIM is not set
-CONFIG_MTD_NAND_PLATFORM=y
+CONFIG_MTD_NAND_GPMI_NAND=m
+# CONFIG_MTD_NAND_PLATFORM is not set
 # CONFIG_MTD_ALAUDA is not set
-CONFIG_MTD_NAND_ORION=m
 CONFIG_MTD_NAND_MXC=m
-# CONFIG_MTD_NAND_FSMC is not set
-CONFIG_MTD_ONENAND=y
-# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
-# CONFIG_MTD_ONENAND_GENERIC is not set
-CONFIG_MTD_ONENAND_OMAP2=y
-# CONFIG_MTD_ONENAND_OTP is not set
-CONFIG_MTD_ONENAND_2X_PROGRAM=y
+# CONFIG_MTD_ONENAND is not set
 
 #
 # LPDDR flash memory drivers
 #
 # CONFIG_MTD_LPDDR is not set
-# CONFIG_MTD_UBI is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_LIMIT=20
+# CONFIG_MTD_UBI_FASTMAP is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
 CONFIG_DTC=y
 CONFIG_OF=y
 
@@ -1521,32 +1353,39 @@ CONFIG_OF_MDIO=y
 CONFIG_OF_PCI=y
 CONFIG_OF_PCI_IRQ=y
 CONFIG_OF_MTD=y
-# CONFIG_PARPORT is not set
+CONFIG_PARPORT=m
+CONFIG_PARPORT_PC=m
+# CONFIG_PARPORT_SERIAL is not set
+# CONFIG_PARPORT_PC_FIFO is not set
+# CONFIG_PARPORT_PC_SUPERIO is not set
+# CONFIG_PARPORT_GSC is not set
+# CONFIG_PARPORT_AX88796 is not set
+CONFIG_PARPORT_1284=y
+CONFIG_PARPORT_NOT_PC=y
 CONFIG_BLK_DEV=y
-CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
-CONFIG_BLK_CPQ_CISS_DA=m
-# CONFIG_CISS_SCSI_TAPE is not set
-CONFIG_BLK_DEV_DAC960=m
-CONFIG_BLK_DEV_UMEM=m
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
 CONFIG_BLK_DEV_CRYPTOLOOP=m
 # CONFIG_BLK_DEV_DRBD is not set
 # CONFIG_BLK_DEV_NBD is not set
-CONFIG_BLK_DEV_NVME=m
+# CONFIG_BLK_DEV_NVME is not set
 # CONFIG_BLK_DEV_OSD is not set
-CONFIG_BLK_DEV_SX8=m
+# CONFIG_BLK_DEV_SX8 is not set
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=65536
+CONFIG_BLK_DEV_RAM_SIZE=16384
 # CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
-CONFIG_MG_DISK=m
-CONFIG_MG_DISK_RES=0
+# CONFIG_MG_DISK is not set
 # CONFIG_BLK_DEV_RBD is not set
-CONFIG_BLK_DEV_RSXX=m
+# CONFIG_BLK_DEV_RSXX is not set
 
 #
 # Misc devices
@@ -1558,12 +1397,11 @@ CONFIG_DUMMY_IRQ=m
 # CONFIG_PHANTOM is not set
 # CONFIG_INTEL_MID_PTI is not set
 # CONFIG_SGI_IOC4 is not set
-CONFIG_TIFM_CORE=m
-CONFIG_TIFM_7XX1=m
+# CONFIG_TIFM_CORE is not set
 CONFIG_ICS932S401=m
 # CONFIG_ATMEL_SSC is not set
 CONFIG_ENCLOSURE_SERVICES=m
-CONFIG_HP_ILO=m
+# CONFIG_HP_ILO is not set
 # CONFIG_APDS9802ALS is not set
 # CONFIG_ISL29003 is not set
 # CONFIG_ISL29020 is not set
@@ -1573,10 +1411,10 @@ CONFIG_HP_ILO=m
 # CONFIG_SENSORS_APDS990X is not set
 # CONFIG_HMC6352 is not set
 CONFIG_DS1682=m
-# CONFIG_ARM_CHARLCD is not set
+CONFIG_ARM_CHARLCD=y
 CONFIG_BMP085=y
 CONFIG_BMP085_I2C=m
-CONFIG_PCH_PHUB=m
+# CONFIG_PCH_PHUB is not set
 CONFIG_USB_SWITCH_FSA9480=m
 # CONFIG_SRAM is not set
 # CONFIG_C2PORT is not set
@@ -1588,9 +1426,7 @@ CONFIG_EEPROM_AT24=m
 CONFIG_EEPROM_LEGACY=m
 CONFIG_EEPROM_MAX6875=m
 CONFIG_EEPROM_93CX6=m
-CONFIG_CB710_CORE=m
-# CONFIG_CB710_DEBUG is not set
-CONFIG_CB710_DEBUG_ASSUMPTIONS=y
+# CONFIG_CB710_CORE is not set
 
 #
 # Texas Instruments shared transport line discipline
@@ -1648,83 +1484,61 @@ CONFIG_SCSI_SRP_TGT_ATTRS=y
 CONFIG_SCSI_LOWLEVEL=y
 CONFIG_ISCSI_TCP=m
 CONFIG_ISCSI_BOOT_SYSFS=m
-CONFIG_SCSI_CXGB3_ISCSI=m
-CONFIG_SCSI_CXGB4_ISCSI=m
-CONFIG_SCSI_BNX2_ISCSI=m
-CONFIG_SCSI_BNX2X_FCOE=m
-CONFIG_BE2ISCSI=m
-CONFIG_BLK_DEV_3W_XXXX_RAID=m
-CONFIG_SCSI_HPSA=m
-CONFIG_SCSI_3W_9XXX=m
-CONFIG_SCSI_3W_SAS=m
+# CONFIG_SCSI_CXGB3_ISCSI is not set
+# CONFIG_SCSI_CXGB4_ISCSI is not set
+# CONFIG_SCSI_BNX2_ISCSI is not set
+# CONFIG_SCSI_BNX2X_FCOE is not set
+# CONFIG_BE2ISCSI is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_HPSA is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_3W_SAS is not set
 # CONFIG_SCSI_ACARD is not set
-CONFIG_SCSI_AACRAID=m
-CONFIG_SCSI_AIC7XXX=m
-CONFIG_AIC7XXX_CMDS_PER_DEVICE=32
-CONFIG_AIC7XXX_RESET_DELAY_MS=5000
-CONFIG_AIC7XXX_DEBUG_ENABLE=y
-CONFIG_AIC7XXX_DEBUG_MASK=0
-CONFIG_AIC7XXX_REG_PRETTY_PRINT=y
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
 # CONFIG_SCSI_AIC7XXX_OLD is not set
-CONFIG_SCSI_AIC79XX=m
-CONFIG_AIC79XX_CMDS_PER_DEVICE=32
-CONFIG_AIC79XX_RESET_DELAY_MS=4000
-# CONFIG_AIC79XX_DEBUG_ENABLE is not set
-CONFIG_AIC79XX_DEBUG_MASK=0
-# CONFIG_AIC79XX_REG_PRETTY_PRINT is not set
-CONFIG_SCSI_AIC94XX=m
-# CONFIG_AIC94XX_DEBUG is not set
-CONFIG_SCSI_MVSAS=m
-# CONFIG_SCSI_MVSAS_DEBUG is not set
-CONFIG_SCSI_MVSAS_TASKLET=y
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_MVSAS is not set
 # CONFIG_SCSI_MVUMI is not set
-CONFIG_SCSI_ARCMSR=m
-CONFIG_MEGARAID_NEWGEN=y
-CONFIG_MEGARAID_MM=m
-CONFIG_MEGARAID_MAILBOX=m
-CONFIG_MEGARAID_LEGACY=m
-CONFIG_MEGARAID_SAS=m
-CONFIG_SCSI_MPT2SAS=m
-CONFIG_SCSI_MPT2SAS_MAX_SGE=128
-# CONFIG_SCSI_MPT2SAS_LOGGING is not set
-CONFIG_SCSI_MPT3SAS=m
-CONFIG_SCSI_MPT3SAS_MAX_SGE=128
-# CONFIG_SCSI_MPT3SAS_LOGGING is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_MPT2SAS is not set
+# CONFIG_SCSI_MPT3SAS is not set
 CONFIG_SCSI_UFSHCD=m
-CONFIG_SCSI_UFSHCD_PCI=m
+# CONFIG_SCSI_UFSHCD_PCI is not set
 CONFIG_SCSI_UFSHCD_PLATFORM=m
-CONFIG_SCSI_HPTIOP=m
+# CONFIG_SCSI_HPTIOP is not set
 CONFIG_LIBFC=m
 CONFIG_LIBFCOE=m
-CONFIG_FCOE=m
-CONFIG_SCSI_DMX3191D=m
-CONFIG_SCSI_FUTURE_DOMAIN=m
-CONFIG_SCSI_IPS=m
-CONFIG_SCSI_INITIO=m
-CONFIG_SCSI_INIA100=m
-CONFIG_SCSI_STEX=m
-CONFIG_SCSI_SYM53C8XX_2=m
-CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
-CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
-CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
-CONFIG_SCSI_SYM53C8XX_MMIO=y
-CONFIG_SCSI_IPR=m
-CONFIG_SCSI_IPR_TRACE=y
-CONFIG_SCSI_IPR_DUMP=y
-CONFIG_SCSI_QLOGIC_1280=m
-CONFIG_SCSI_QLA_FC=m
-CONFIG_SCSI_QLA_ISCSI=m
-CONFIG_SCSI_LPFC=m
-# CONFIG_SCSI_LPFC_DEBUG_FS is not set
-CONFIG_SCSI_DC395x=m
-CONFIG_SCSI_DC390T=m
+# CONFIG_FCOE is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+CONFIG_SCSI_PPA=m
+CONFIG_SCSI_IMM=m
+# CONFIG_SCSI_IZIP_EPP16 is not set
+# CONFIG_SCSI_IZIP_SLOW_CTR is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
 # CONFIG_SCSI_NSP32 is not set
 # CONFIG_SCSI_DEBUG is not set
-CONFIG_SCSI_PMCRAID=m
-CONFIG_SCSI_PM8001=m
+# CONFIG_SCSI_PMCRAID is not set
+# CONFIG_SCSI_PM8001 is not set
 # CONFIG_SCSI_SRP is not set
-CONFIG_SCSI_BFA_FC=m
-CONFIG_SCSI_CHELSIO_FCOE=m
+# CONFIG_SCSI_BFA_FC is not set
+# CONFIG_SCSI_CHELSIO_FCOE is not set
 CONFIG_SCSI_DH=y
 CONFIG_SCSI_DH_RDAC=m
 CONFIG_SCSI_DH_HP_SW=m
@@ -1743,95 +1557,94 @@ CONFIG_SATA_PMP=y
 #
 # Controllers with non-SFF native interface
 #
-CONFIG_SATA_AHCI=y
+# CONFIG_SATA_AHCI is not set
 CONFIG_SATA_AHCI_PLATFORM=m
-CONFIG_SATA_INIC162X=m
-CONFIG_SATA_ACARD_AHCI=m
-CONFIG_SATA_SIL24=m
+CONFIG_AHCI_IMX=m
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_SATA_ACARD_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
 CONFIG_ATA_SFF=y
 
 #
 # SFF controllers with custom DMA interface
 #
-CONFIG_PDC_ADMA=m
-CONFIG_SATA_QSTOR=m
-CONFIG_SATA_SX4=m
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_SX4 is not set
 CONFIG_ATA_BMDMA=y
 
 #
 # SATA SFF controllers with BMDMA
 #
-CONFIG_ATA_PIIX=y
+# CONFIG_ATA_PIIX is not set
 CONFIG_SATA_HIGHBANK=m
 CONFIG_SATA_MV=m
-CONFIG_SATA_NV=m
-CONFIG_SATA_PROMISE=m
-CONFIG_SATA_SIL=m
-CONFIG_SATA_SIS=m
-CONFIG_SATA_SVW=m
-CONFIG_SATA_ULI=m
-CONFIG_SATA_VIA=m
-CONFIG_SATA_VITESSE=m
+# CONFIG_SATA_NV is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_SVW is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
 
 #
 # PATA SFF controllers with BMDMA
 #
-CONFIG_PATA_ALI=m
-CONFIG_PATA_AMD=m
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
 CONFIG_PATA_ARASAN_CF=m
-CONFIG_PATA_ARTOP=m
-CONFIG_PATA_ATIIXP=m
-CONFIG_PATA_ATP867X=m
-CONFIG_PATA_CMD64X=m
-CONFIG_PATA_CS5520=m
-CONFIG_PATA_CS5530=m
-CONFIG_PATA_CS5536=m
-CONFIG_PATA_CYPRESS=m
-CONFIG_PATA_EFAR=m
-CONFIG_PATA_HPT366=m
-CONFIG_PATA_HPT37X=m
-CONFIG_PATA_HPT3X2N=m
-CONFIG_PATA_HPT3X3=m
-# CONFIG_PATA_HPT3X3_DMA is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_ATP867X is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CS5536 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
 CONFIG_PATA_IMX=m
-CONFIG_PATA_IT8213=m
-CONFIG_PATA_IT821X=m
-CONFIG_PATA_JMICRON=m
-CONFIG_PATA_MARVELL=m
-CONFIG_PATA_NETCELL=m
-CONFIG_PATA_NINJA32=m
-CONFIG_PATA_NS87415=m
-CONFIG_PATA_OLDPIIX=m
-CONFIG_PATA_OPTIDMA=m
-CONFIG_PATA_PDC2027X=m
-CONFIG_PATA_PDC_OLD=m
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_PDC_OLD is not set
 # CONFIG_PATA_RADISYS is not set
-CONFIG_PATA_RDC=m
+# CONFIG_PATA_RDC is not set
 # CONFIG_PATA_SC1200 is not set
-CONFIG_PATA_SCH=m
-CONFIG_PATA_SERVERWORKS=m
-CONFIG_PATA_SIL680=m
-CONFIG_PATA_SIS=m
-CONFIG_PATA_TOSHIBA=m
-CONFIG_PATA_TRIFLEX=m
-CONFIG_PATA_VIA=m
-CONFIG_PATA_WINBOND=m
+# CONFIG_PATA_SCH is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_TOSHIBA is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
 
 #
 # PIO-only SFF controllers
 #
-CONFIG_PATA_CMD640_PCI=m
-CONFIG_PATA_MPIIX=m
-CONFIG_PATA_NS87410=m
-CONFIG_PATA_OPTI=m
-CONFIG_PATA_PLATFORM=m
-CONFIG_PATA_OF_PLATFORM=m
-CONFIG_PATA_RZ1000=m
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_RZ1000 is not set
 
 #
 # Generic fallback / legacy drivers
 #
-CONFIG_ATA_GENERIC=m
+# CONFIG_ATA_GENERIC is not set
 # CONFIG_PATA_LEGACY is not set
 CONFIG_MD=y
 CONFIG_BLK_DEV_MD=y
@@ -1870,29 +1683,14 @@ CONFIG_DM_UEVENT=y
 # CONFIG_DM_FLAKEY is not set
 CONFIG_DM_VERITY=m
 # CONFIG_TARGET_CORE is not set
-CONFIG_FUSION=y
-CONFIG_FUSION_SPI=m
-CONFIG_FUSION_FC=m
-CONFIG_FUSION_SAS=m
-CONFIG_FUSION_MAX_SGE=40
-CONFIG_FUSION_CTL=m
-CONFIG_FUSION_LOGGING=y
+# CONFIG_FUSION is not set
 
 #
 # IEEE 1394 (FireWire) support
 #
-CONFIG_FIREWIRE=m
-CONFIG_FIREWIRE_OHCI=m
-CONFIG_FIREWIRE_SBP2=m
-# CONFIG_FIREWIRE_NET is not set
+# CONFIG_FIREWIRE is not set
 # CONFIG_FIREWIRE_NOSY is not set
-CONFIG_I2O=m
-# CONFIG_I2O_LCT_NOTIFY_ON_CHANGES is not set
-CONFIG_I2O_EXT_ADAPTEC=y
-CONFIG_I2O_BUS=m
-CONFIG_I2O_BLOCK=m
-CONFIG_I2O_SCSI=m
-CONFIG_I2O_PROC=m
+# CONFIG_I2O is not set
 CONFIG_NETDEVICES=y
 CONFIG_NET_CORE=y
 CONFIG_BONDING=m
@@ -1918,31 +1716,18 @@ CONFIG_IMQ_BEHAVIOR_AB=y
 CONFIG_IMQ_NUM_DEVS=2
 CONFIG_TUN=m
 CONFIG_VETH=m
-CONFIG_SUNGEM_PHY=m
 # CONFIG_ARCNET is not set
 CONFIG_ATM_DRIVERS=y
 # CONFIG_ATM_DUMMY is not set
 CONFIG_ATM_TCP=m
-CONFIG_ATM_LANAI=m
-CONFIG_ATM_ENI=m
-# CONFIG_ATM_ENI_DEBUG is not set
-# CONFIG_ATM_ENI_TUNE_BURST is not set
-CONFIG_ATM_NICSTAR=m
-# CONFIG_ATM_NICSTAR_USE_SUNI is not set
-# CONFIG_ATM_NICSTAR_USE_IDT77105 is not set
-CONFIG_ATM_IDT77252=m
-# CONFIG_ATM_IDT77252_DEBUG is not set
-# CONFIG_ATM_IDT77252_RCV_ALL is not set
-CONFIG_ATM_IDT77252_USE_SUNI=y
-CONFIG_ATM_IA=m
-# CONFIG_ATM_IA_DEBUG is not set
-CONFIG_ATM_FORE200E=m
-# CONFIG_ATM_FORE200E_USE_TASKLET is not set
-CONFIG_ATM_FORE200E_TX_RETRY=16
-CONFIG_ATM_FORE200E_DEBUG=0
-CONFIG_ATM_HE=m
-# CONFIG_ATM_HE_USE_SUNI is not set
-CONFIG_ATM_SOLOS=m
+# CONFIG_ATM_LANAI is not set
+# CONFIG_ATM_ENI is not set
+# CONFIG_ATM_NICSTAR is not set
+# CONFIG_ATM_IDT77252 is not set
+# CONFIG_ATM_IA is not set
+# CONFIG_ATM_FORE200E is not set
+# CONFIG_ATM_HE is not set
+# CONFIG_ATM_SOLOS is not set
 
 #
 # CAIF transport drivers
@@ -1957,23 +1742,21 @@ CONFIG_NET_DSA_MV88E6XXX_NEED_PPU=y
 CONFIG_NET_DSA_MV88E6131=y
 CONFIG_NET_DSA_MV88E6123_61_65=y
 CONFIG_ETHERNET=y
-CONFIG_MDIO=m
 CONFIG_NET_VENDOR_3COM=y
-CONFIG_TYPHOON=m
+# CONFIG_TYPHOON is not set
 CONFIG_NET_VENDOR_ADAPTEC=y
-CONFIG_ADAPTEC_STARFIRE=m
+# CONFIG_ADAPTEC_STARFIRE is not set
 CONFIG_NET_VENDOR_ALTEON=y
-CONFIG_ACENIC=m
-# CONFIG_ACENIC_OMIT_TIGON_I is not set
+# CONFIG_ACENIC is not set
 CONFIG_NET_VENDOR_AMD=y
-CONFIG_AMD8111_ETH=m
-CONFIG_PCNET32=m
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_PCNET32 is not set
 CONFIG_NET_VENDOR_ATHEROS=y
-CONFIG_ATL2=m
-CONFIG_ATL1=m
-CONFIG_ATL1E=m
-CONFIG_ATL1C=m
-CONFIG_ALX=m
+# CONFIG_ATL2 is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_ATL1C is not set
+# CONFIG_ALX is not set
 CONFIG_NET_CADENCE=y
 CONFIG_ARM_AT91_ETHER=m
 CONFIG_MACB=m
@@ -1982,161 +1765,126 @@ CONFIG_B44=m
 CONFIG_B44_PCI_AUTOSELECT=y
 CONFIG_B44_PCICORE_AUTOSELECT=y
 CONFIG_B44_PCI=y
-CONFIG_BNX2=m
-CONFIG_CNIC=m
-CONFIG_TIGON3=m
-CONFIG_BNX2X=m
-CONFIG_BNX2X_SRIOV=y
+# CONFIG_BNX2 is not set
+# CONFIG_CNIC is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2X is not set
 CONFIG_NET_VENDOR_BROCADE=y
-CONFIG_BNA=m
+# CONFIG_BNA is not set
 CONFIG_NET_CALXEDA_XGMAC=m
 CONFIG_NET_VENDOR_CHELSIO=y
-CONFIG_CHELSIO_T1=m
-CONFIG_CHELSIO_T1_1G=y
-CONFIG_CHELSIO_T3=m
-CONFIG_CHELSIO_T4=m
-CONFIG_CHELSIO_T4VF=m
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_CHELSIO_T3 is not set
+# CONFIG_CHELSIO_T4 is not set
+# CONFIG_CHELSIO_T4VF is not set
 CONFIG_NET_VENDOR_CIRRUS=y
 CONFIG_CS89x0=m
 CONFIG_CS89x0_PLATFORM=y
 CONFIG_NET_VENDOR_CISCO=y
-CONFIG_ENIC=m
+# CONFIG_ENIC is not set
 CONFIG_DM9000=m
 # CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set
 CONFIG_DNET=m
 CONFIG_NET_VENDOR_DEC=y
-CONFIG_NET_TULIP=y
-CONFIG_DE2104X=m
-CONFIG_DE2104X_DSL=0
-CONFIG_TULIP=m
-# CONFIG_TULIP_MWI is not set
-CONFIG_TULIP_MMIO=y
-CONFIG_TULIP_NAPI=y
-CONFIG_TULIP_NAPI_HW_MITIGATION=y
-CONFIG_WINBOND_840=m
-CONFIG_DM9102=m
-CONFIG_ULI526X=m
-# CONFIG_PCMCIA_XIRCOM is not set
+# CONFIG_NET_TULIP is not set
 CONFIG_NET_VENDOR_DLINK=y
-CONFIG_DL2K=m
-CONFIG_SUNDANCE=m
-# CONFIG_SUNDANCE_MMIO is not set
+# CONFIG_DL2K is not set
+# CONFIG_SUNDANCE is not set
 CONFIG_NET_VENDOR_EMULEX=y
-CONFIG_BE2NET=m
+# CONFIG_BE2NET is not set
 CONFIG_NET_VENDOR_EXAR=y
-CONFIG_S2IO=m
-CONFIG_VXGE=m
-# CONFIG_VXGE_DEBUG_TRACE_ALL is not set
+# CONFIG_S2IO is not set
+# CONFIG_VXGE is not set
 CONFIG_NET_VENDOR_FARADAY=y
-CONFIG_FTMAC100=m
-CONFIG_FTGMAC100=m
+# CONFIG_FTMAC100 is not set
+# CONFIG_FTGMAC100 is not set
 CONFIG_NET_VENDOR_FREESCALE=y
 CONFIG_FEC=m
 CONFIG_NET_VENDOR_HP=y
-CONFIG_HP100=m
+# CONFIG_HP100 is not set
 CONFIG_NET_VENDOR_INTEL=y
-CONFIG_E100=m
-CONFIG_E1000=m
-CONFIG_E1000E=m
-CONFIG_IGB=m
-CONFIG_IGB_HWMON=y
-CONFIG_IGBVF=m
-CONFIG_IXGB=m
-CONFIG_IXGBE=m
-CONFIG_IXGBE_HWMON=y
+# CONFIG_E100 is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IGB is not set
+# CONFIG_IGBVF is not set
+# CONFIG_IXGB is not set
+# CONFIG_IXGBE is not set
 CONFIG_NET_VENDOR_I825XX=y
-CONFIG_IP1000=m
-CONFIG_JME=m
+# CONFIG_IP1000 is not set
+# CONFIG_JME is not set
 CONFIG_NET_VENDOR_MARVELL=y
-CONFIG_MV643XX_ETH=m
 CONFIG_MVMDIO=m
-CONFIG_MVNETA=m
-CONFIG_SKGE=m
-# CONFIG_SKGE_DEBUG is not set
-CONFIG_SKGE_GENESIS=y
-CONFIG_SKY2=m
-# CONFIG_SKY2_DEBUG is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
 CONFIG_NET_VENDOR_MELLANOX=y
-CONFIG_MLX4_EN=m
-CONFIG_MLX4_CORE=m
-CONFIG_MLX4_DEBUG=y
+# CONFIG_MLX4_EN is not set
+# CONFIG_MLX4_CORE is not set
 CONFIG_NET_VENDOR_MICREL=y
-CONFIG_KS8842=m
-CONFIG_KS8851_MLL=m
-CONFIG_KSZ884X_PCI=m
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_KSZ884X_PCI is not set
 CONFIG_NET_VENDOR_MYRI=y
-CONFIG_MYRI10GE=m
-CONFIG_FEALNX=m
+# CONFIG_MYRI10GE is not set
+# CONFIG_FEALNX is not set
 CONFIG_NET_VENDOR_NATSEMI=y
-CONFIG_NATSEMI=m
-CONFIG_NS83820=m
+# CONFIG_NATSEMI is not set
+# CONFIG_NS83820 is not set
 CONFIG_NET_VENDOR_8390=y
 CONFIG_AX88796=m
 CONFIG_AX88796_93CX6=y
-CONFIG_NE2K_PCI=m
+# CONFIG_NE2K_PCI is not set
 CONFIG_NET_VENDOR_NVIDIA=y
-CONFIG_FORCEDETH=m
+# CONFIG_FORCEDETH is not set
 CONFIG_NET_VENDOR_OKI=y
-CONFIG_PCH_GBE=m
+# CONFIG_PCH_GBE is not set
 CONFIG_ETHOC=m
-# CONFIG_NET_PACKET_ENGINE is not set
+CONFIG_NET_PACKET_ENGINE=y
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
 CONFIG_NET_VENDOR_QLOGIC=y
-CONFIG_QLA3XXX=m
-CONFIG_QLCNIC=m
-CONFIG_QLCNIC_SRIOV=y
-CONFIG_QLGE=m
-CONFIG_NETXEN_NIC=m
+# CONFIG_QLA3XXX is not set
+# CONFIG_QLCNIC is not set
+# CONFIG_QLGE is not set
+# CONFIG_NETXEN_NIC is not set
 CONFIG_NET_VENDOR_REALTEK=y
-CONFIG_8139CP=m
-CONFIG_8139TOO=m
-# CONFIG_8139TOO_PIO is not set
-# CONFIG_8139TOO_TUNE_TWISTER is not set
-CONFIG_8139TOO_8129=y
-# CONFIG_8139_OLD_RX_RESET is not set
-CONFIG_R8169=m
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_R8169 is not set
 CONFIG_NET_VENDOR_RDC=y
-CONFIG_R6040=m
+# CONFIG_R6040 is not set
 CONFIG_NET_VENDOR_SEEQ=y
 CONFIG_NET_VENDOR_SILAN=y
-CONFIG_SC92031=m
+# CONFIG_SC92031 is not set
 CONFIG_NET_VENDOR_SIS=y
-CONFIG_SIS900=m
-CONFIG_SIS190=m
-CONFIG_SFC=m
-CONFIG_SFC_MTD=y
-CONFIG_SFC_MCDI_MON=y
-CONFIG_SFC_SRIOV=y
+# CONFIG_SIS900 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SFC is not set
 CONFIG_NET_VENDOR_SMSC=y
 CONFIG_SMC91X=m
-CONFIG_EPIC100=m
+# CONFIG_EPIC100 is not set
 CONFIG_SMC911X=m
 CONFIG_SMSC911X=m
 # CONFIG_SMSC911X_ARCH_HOOKS is not set
-CONFIG_SMSC9420=m
+# CONFIG_SMSC9420 is not set
 CONFIG_NET_VENDOR_STMICRO=y
 CONFIG_STMMAC_ETH=m
 CONFIG_STMMAC_PLATFORM=y
-CONFIG_STMMAC_PCI=y
+# CONFIG_STMMAC_PCI is not set
 # CONFIG_STMMAC_DEBUG_FS is not set
 # CONFIG_STMMAC_DA is not set
 CONFIG_NET_VENDOR_SUN=y
-CONFIG_HAPPYMEAL=m
-CONFIG_SUNGEM=m
-CONFIG_CASSINI=m
-CONFIG_NIU=m
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NIU is not set
 CONFIG_NET_VENDOR_TEHUTI=y
-CONFIG_TEHUTI=m
+# CONFIG_TEHUTI is not set
 CONFIG_NET_VENDOR_TI=y
-CONFIG_TI_DAVINCI_EMAC=m
-CONFIG_TI_DAVINCI_MDIO=m
-CONFIG_TI_DAVINCI_CPDMA=m
-CONFIG_TI_CPSW=m
-# CONFIG_TI_CPTS is not set
-CONFIG_TLAN=m
+# CONFIG_TLAN is not set
 CONFIG_NET_VENDOR_VIA=y
-CONFIG_VIA_RHINE=m
-CONFIG_VIA_RHINE_MMIO=y
-CONFIG_VIA_VELOCITY=m
+# CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_VELOCITY is not set
 CONFIG_NET_VENDOR_WIZNET=y
 CONFIG_WIZNET_W5100=m
 CONFIG_WIZNET_W5300=m
@@ -2173,6 +1921,7 @@ CONFIG_MDIO_BITBANG=m
 CONFIG_MDIO_BUS_MUX=m
 CONFIG_MDIO_BUS_MUX_GPIO=m
 CONFIG_MDIO_BUS_MUX_MMIOREG=m
+# CONFIG_PLIP is not set
 CONFIG_PPP=m
 CONFIG_PPP_BSDCOMP=m
 CONFIG_PPP_DEFLATE=m
@@ -2231,25 +1980,22 @@ CONFIG_WLAN=y
 CONFIG_LIBERTAS_THINFIRM=m
 # CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
 CONFIG_LIBERTAS_THINFIRM_USB=m
-CONFIG_ATMEL=m
-CONFIG_PCI_ATMEL=m
+# CONFIG_ATMEL is not set
 CONFIG_AT76C50X_USB=m
 # CONFIG_PRISM54 is not set
 CONFIG_USB_ZD1201=m
 CONFIG_USB_NET_RNDIS_WLAN=m
-CONFIG_RTL8180=m
+# CONFIG_RTL8180 is not set
 CONFIG_RTL8187=m
 CONFIG_RTL8187_LEDS=y
-CONFIG_ADM8211=m
+# CONFIG_ADM8211 is not set
 CONFIG_MAC80211_HWSIM=m
-CONFIG_MWL8K=m
+# CONFIG_MWL8K is not set
 CONFIG_ATH_COMMON=m
 CONFIG_ATH_CARDS=m
 # CONFIG_ATH_DEBUG is not set
-CONFIG_ATH5K=m
-CONFIG_ATH5K_DEBUG=y
-# CONFIG_ATH5K_TRACER is not set
-CONFIG_ATH5K_PCI=y
+# CONFIG_ATH5K is not set
+# CONFIG_ATH5K_PCI is not set
 CONFIG_ATH9K_HW=m
 CONFIG_ATH9K_COMMON=m
 CONFIG_ATH9K_BTCOEX_SUPPORT=y
@@ -2266,8 +2012,7 @@ CONFIG_CARL9170_WPC=y
 # CONFIG_CARL9170_HWRNG is not set
 # CONFIG_ATH6KL is not set
 CONFIG_AR5523=m
-CONFIG_WIL6210=m
-CONFIG_WIL6210_ISR_COR=y
+# CONFIG_WIL6210 is not set
 CONFIG_B43=m
 CONFIG_B43_SSB=y
 CONFIG_B43_PCI_AUTOSELECT=y
@@ -2293,69 +2038,34 @@ CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
 CONFIG_BRCMUTIL=m
 CONFIG_BRCMFMAC=m
 CONFIG_BRCMFMAC_SDIO=y
-CONFIG_BRCMFMAC_USB=y
+# CONFIG_BRCMFMAC_USB is not set
 # CONFIG_BRCM_TRACING is not set
 # CONFIG_BRCMDBG is not set
 CONFIG_HOSTAP=m
 CONFIG_HOSTAP_FIRMWARE=y
 CONFIG_HOSTAP_FIRMWARE_NVRAM=y
-CONFIG_HOSTAP_PLX=m
-CONFIG_HOSTAP_PCI=m
-CONFIG_IPW2100=m
-CONFIG_IPW2100_MONITOR=y
-# CONFIG_IPW2100_DEBUG is not set
-CONFIG_IPW2200=m
-CONFIG_IPW2200_MONITOR=y
-CONFIG_IPW2200_RADIOTAP=y
-CONFIG_IPW2200_PROMISCUOUS=y
-CONFIG_IPW2200_QOS=y
-# CONFIG_IPW2200_DEBUG is not set
-CONFIG_LIBIPW=m
-# CONFIG_LIBIPW_DEBUG is not set
-CONFIG_IWLWIFI=m
-CONFIG_IWLDVM=m
-CONFIG_IWLMVM=m
-CONFIG_IWLWIFI_OPMODE_MODULAR=y
-
-#
-# Debugging Options
-#
-# CONFIG_IWLWIFI_DEBUG is not set
-# CONFIG_IWLWIFI_DEVICE_TRACING is not set
-CONFIG_IWLWIFI_P2P=y
-CONFIG_IWLEGACY=m
-CONFIG_IWL4965=m
-CONFIG_IWL3945=m
-
-#
-# iwl3945 / iwl4965 Debugging Options
-#
-# CONFIG_IWLEGACY_DEBUG is not set
+# CONFIG_HOSTAP_PLX is not set
+# CONFIG_HOSTAP_PCI is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_IWLWIFI is not set
+# CONFIG_IWL4965 is not set
+# CONFIG_IWL3945 is not set
 CONFIG_LIBERTAS=m
 CONFIG_LIBERTAS_USB=m
 CONFIG_LIBERTAS_SDIO=m
 # CONFIG_LIBERTAS_DEBUG is not set
 CONFIG_LIBERTAS_MESH=y
-CONFIG_HERMES=m
-# CONFIG_HERMES_PRISM is not set
-CONFIG_HERMES_CACHE_FW_ON_INIT=y
-CONFIG_PLX_HERMES=m
-CONFIG_TMD_HERMES=m
-CONFIG_NORTEL_HERMES=m
-CONFIG_ORINOCO_USB=m
+# CONFIG_HERMES is not set
 CONFIG_P54_COMMON=m
 CONFIG_P54_USB=m
-CONFIG_P54_PCI=m
+# CONFIG_P54_PCI is not set
 CONFIG_P54_LEDS=y
 CONFIG_RT2X00=m
-CONFIG_RT2400PCI=m
-CONFIG_RT2500PCI=m
-CONFIG_RT61PCI=m
-CONFIG_RT2800PCI=m
-CONFIG_RT2800PCI_RT33XX=y
-CONFIG_RT2800PCI_RT35XX=y
-CONFIG_RT2800PCI_RT53XX=y
-CONFIG_RT2800PCI_RT3290=y
+# CONFIG_RT2400PCI is not set
+# CONFIG_RT2500PCI is not set
+# CONFIG_RT61PCI is not set
+# CONFIG_RT2800PCI is not set
 CONFIG_RT2500USB=m
 CONFIG_RT73USB=m
 CONFIG_RT2800USB=m
@@ -2365,8 +2075,6 @@ CONFIG_RT2800USB_RT53XX=y
 CONFIG_RT2800USB_RT55XX=y
 CONFIG_RT2800USB_UNKNOWN=y
 CONFIG_RT2800_LIB=m
-CONFIG_RT2X00_LIB_MMIO=m
-CONFIG_RT2X00_LIB_PCI=m
 CONFIG_RT2X00_LIB_USB=m
 CONFIG_RT2X00_LIB=m
 CONFIG_RT2X00_LIB_FIRMWARE=y
@@ -2375,11 +2083,11 @@ CONFIG_RT2X00_LIB_LEDS=y
 # CONFIG_RT2X00_DEBUG is not set
 CONFIG_RTLWIFI=m
 # CONFIG_RTLWIFI_DEBUG is not set
-CONFIG_RTL8192CE=m
-CONFIG_RTL8192SE=m
-CONFIG_RTL8192DE=m
-CONFIG_RTL8723AE=m
-CONFIG_RTL8188EE=m
+# CONFIG_RTL8192CE is not set
+# CONFIG_RTL8192SE is not set
+# CONFIG_RTL8192DE is not set
+# CONFIG_RTL8723AE is not set
+# CONFIG_RTL8188EE is not set
 CONFIG_RTL8192CU=m
 CONFIG_RTL8192C_COMMON=m
 CONFIG_WL_TI=y
@@ -2394,7 +2102,7 @@ CONFIG_ZD1211RW=m
 # CONFIG_ZD1211RW_DEBUG is not set
 CONFIG_MWIFIEX=m
 CONFIG_MWIFIEX_SDIO=m
-CONFIG_MWIFIEX_PCIE=m
+# CONFIG_MWIFIEX_PCIE is not set
 CONFIG_MWIFIEX_USB=m
 
 #
@@ -2442,7 +2150,7 @@ CONFIG_HISAX_MAX_CARDS=8
 # HiSax supported cards
 #
 CONFIG_HISAX_16_3=y
-CONFIG_HISAX_TELESPCI=y
+# CONFIG_HISAX_TELESPCI is not set
 CONFIG_HISAX_S0BOX=y
 CONFIG_HISAX_FRITZPCI=y
 CONFIG_HISAX_AVM_A1_PCMCIA=y
@@ -2450,11 +2158,11 @@ CONFIG_HISAX_ELSA=y
 CONFIG_HISAX_DIEHLDIVA=y
 CONFIG_HISAX_SEDLBAUER=y
 CONFIG_HISAX_NICCY=y
-CONFIG_HISAX_BKM_A4T=y
-CONFIG_HISAX_SCT_QUADRO=y
+# CONFIG_HISAX_BKM_A4T is not set
+# CONFIG_HISAX_SCT_QUADRO is not set
 CONFIG_HISAX_GAZEL=y
-CONFIG_HISAX_HFC_PCI=y
-CONFIG_HISAX_W6692=y
+# CONFIG_HISAX_HFC_PCI is not set
+# CONFIG_HISAX_W6692 is not set
 CONFIG_HISAX_HFC_SX=y
 # CONFIG_HISAX_DEBUG is not set
 
@@ -2468,7 +2176,7 @@ CONFIG_HISAX_HFC_SX=y
 CONFIG_HISAX_ST5481=m
 CONFIG_HISAX_HFCUSB=m
 CONFIG_HISAX_HFC4S8S=m
-CONFIG_HISAX_FRITZ_PCIPNP=m
+# CONFIG_HISAX_FRITZ_PCIPNP is not set
 
 #
 # Active cards
@@ -2484,51 +2192,21 @@ CONFIG_ISDN_CAPI_CAPIDRV=m
 # CAPI hardware drivers
 #
 CONFIG_CAPI_AVM=y
-CONFIG_ISDN_DRV_AVMB1_B1PCI=m
-CONFIG_ISDN_DRV_AVMB1_B1PCIV4=y
-CONFIG_ISDN_DRV_AVMB1_T1PCI=m
-CONFIG_ISDN_DRV_AVMB1_C4=m
+# CONFIG_ISDN_DRV_AVMB1_B1PCI is not set
+# CONFIG_ISDN_DRV_AVMB1_T1PCI is not set
+# CONFIG_ISDN_DRV_AVMB1_C4 is not set
 CONFIG_CAPI_EICON=y
-CONFIG_ISDN_DIVAS=m
-CONFIG_ISDN_DIVAS_BRIPCI=y
-CONFIG_ISDN_DIVAS_PRIPCI=y
-CONFIG_ISDN_DIVAS_DIVACAPI=m
-CONFIG_ISDN_DIVAS_USERIDI=m
-CONFIG_ISDN_DIVAS_MAINT=m
-CONFIG_ISDN_DRV_GIGASET=m
-CONFIG_GIGASET_CAPI=y
-# CONFIG_GIGASET_I4L is not set
-# CONFIG_GIGASET_DUMMYLL is not set
-CONFIG_GIGASET_BASE=m
-CONFIG_GIGASET_M105=m
-CONFIG_GIGASET_M101=m
-# CONFIG_GIGASET_DEBUG is not set
-CONFIG_HYSDN=m
-CONFIG_HYSDN_CAPI=y
-CONFIG_MISDN=m
-CONFIG_MISDN_DSP=m
-CONFIG_MISDN_L1OIP=m
-
-#
-# mISDN hardware drivers
-#
-CONFIG_MISDN_HFCPCI=m
-CONFIG_MISDN_HFCMULTI=m
-CONFIG_MISDN_HFCUSB=m
-CONFIG_MISDN_AVMFRITZ=m
-CONFIG_MISDN_SPEEDFAX=m
-CONFIG_MISDN_INFINEON=m
-CONFIG_MISDN_W6692=m
-CONFIG_MISDN_NETJET=m
-CONFIG_MISDN_IPAC=m
-CONFIG_MISDN_ISAR=m
+# CONFIG_ISDN_DIVAS is not set
+# CONFIG_ISDN_DRV_GIGASET is not set
+# CONFIG_HYSDN is not set
+# CONFIG_MISDN is not set
 CONFIG_ISDN_HDLC=m
 
 #
 # Input device support
 #
 CONFIG_INPUT=y
-CONFIG_INPUT_FF_MEMLESS=y
+CONFIG_INPUT_FF_MEMLESS=m
 CONFIG_INPUT_POLLDEV=m
 CONFIG_INPUT_SPARSEKMAP=m
 CONFIG_INPUT_MATRIXKMAP=m
@@ -2549,14 +2227,13 @@ CONFIG_INPUT_EVDEV=y
 # Input Device Drivers
 #
 CONFIG_INPUT_KEYBOARD=y
-# CONFIG_KEYBOARD_ADP5520 is not set
 # CONFIG_KEYBOARD_ADP5588 is not set
 # CONFIG_KEYBOARD_ADP5589 is not set
 CONFIG_KEYBOARD_ATKBD=y
 # CONFIG_KEYBOARD_QT1070 is not set
 # CONFIG_KEYBOARD_QT2160 is not set
 # CONFIG_KEYBOARD_LKKBD is not set
-CONFIG_KEYBOARD_GPIO=m
+CONFIG_KEYBOARD_GPIO=y
 # CONFIG_KEYBOARD_TCA6416 is not set
 # CONFIG_KEYBOARD_TCA8418 is not set
 # CONFIG_KEYBOARD_MATRIX is not set
@@ -2567,16 +2244,10 @@ CONFIG_KEYBOARD_LM8333=m
 # CONFIG_KEYBOARD_MPR121 is not set
 CONFIG_KEYBOARD_IMX=m
 # CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_NOMADIK is not set
-CONFIG_KEYBOARD_TEGRA=m
 # CONFIG_KEYBOARD_OPENCORES is not set
 # CONFIG_KEYBOARD_SAMSUNG is not set
 # CONFIG_KEYBOARD_STOWAWAY is not set
 # CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_STMPE is not set
-CONFIG_KEYBOARD_OMAP4=m
-# CONFIG_KEYBOARD_SPEAR is not set
-# CONFIG_KEYBOARD_TC3589X is not set
 CONFIG_KEYBOARD_TWL4030=m
 # CONFIG_KEYBOARD_XTKBD is not set
 CONFIG_INPUT_MOUSE=y
@@ -2594,7 +2265,7 @@ CONFIG_MOUSE_APPLETOUCH=m
 CONFIG_MOUSE_BCM5974=m
 CONFIG_MOUSE_CYAPA=m
 CONFIG_MOUSE_VSXXXAA=m
-CONFIG_MOUSE_GPIO=m
+# CONFIG_MOUSE_GPIO is not set
 CONFIG_MOUSE_SYNAPTICS_I2C=m
 CONFIG_MOUSE_SYNAPTICS_USB=m
 # CONFIG_INPUT_JOYSTICK is not set
@@ -2603,10 +2274,8 @@ CONFIG_MOUSE_SYNAPTICS_USB=m
 CONFIG_INPUT_MISC=y
 # CONFIG_INPUT_88PM860X_ONKEY is not set
 # CONFIG_INPUT_88PM80X_ONKEY is not set
-# CONFIG_INPUT_AB8500_PONKEY is not set
 # CONFIG_INPUT_AD714X is not set
 # CONFIG_INPUT_BMA150 is not set
-# CONFIG_INPUT_MAX8925_ONKEY is not set
 # CONFIG_INPUT_MMA8450 is not set
 # CONFIG_INPUT_MPU3050 is not set
 # CONFIG_INPUT_GP2A is not set
@@ -2618,16 +2287,12 @@ CONFIG_INPUT_POWERMATE=m
 CONFIG_INPUT_YEALINK=m
 CONFIG_INPUT_CM109=m
 CONFIG_INPUT_RETU_PWRBUTTON=m
-CONFIG_INPUT_TWL4030_PWRBUTTON=y
-CONFIG_INPUT_TWL4030_VIBRA=y
-CONFIG_INPUT_TWL6040_VIBRA=y
+CONFIG_INPUT_TWL4030_PWRBUTTON=m
+CONFIG_INPUT_TWL4030_VIBRA=m
 CONFIG_INPUT_UINPUT=m
 # CONFIG_INPUT_PCF8574 is not set
-# CONFIG_INPUT_PWM_BEEPER is not set
+CONFIG_INPUT_PWM_BEEPER=m
 CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
-# CONFIG_INPUT_DA9052_ONKEY is not set
-# CONFIG_INPUT_DA9055_ONKEY is not set
-# CONFIG_INPUT_WM831X_ON is not set
 # CONFIG_INPUT_ADXL34X is not set
 # CONFIG_INPUT_IMS_PCU is not set
 # CONFIG_INPUT_CMA3000 is not set
@@ -2637,6 +2302,7 @@ CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
 #
 CONFIG_SERIO=y
 CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_PARKBD is not set
 CONFIG_SERIO_AMBAKMI=m
 # CONFIG_SERIO_PCIPS2 is not set
 CONFIG_SERIO_LIBPS2=y
@@ -2661,14 +2327,13 @@ CONFIG_UNIX98_PTYS=y
 CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_NONSTANDARD=y
-CONFIG_ROCKETPORT=m
-CONFIG_CYCLADES=m
-# CONFIG_CYZ_INTR is not set
+# CONFIG_ROCKETPORT is not set
+# CONFIG_CYCLADES is not set
 # CONFIG_MOXA_INTELLIO is not set
 # CONFIG_MOXA_SMARTIO is not set
-CONFIG_SYNCLINKMP=m
-CONFIG_SYNCLINK_GT=m
-CONFIG_NOZOMI=m
+# CONFIG_SYNCLINKMP is not set
+# CONFIG_SYNCLINK_GT is not set
+# CONFIG_NOZOMI is not set
 # CONFIG_ISI is not set
 CONFIG_N_HDLC=m
 CONFIG_N_GSM=m
@@ -2689,7 +2354,7 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4
 CONFIG_SERIAL_8250_EXTENDED=y
 CONFIG_SERIAL_8250_MANY_PORTS=y
 CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
 CONFIG_SERIAL_8250_RSA=y
 # CONFIG_SERIAL_8250_DW is not set
 # CONFIG_SERIAL_8250_EM is not set
@@ -2697,22 +2362,16 @@ CONFIG_SERIAL_8250_RSA=y
 #
 # Non-8250 serial port support
 #
-# CONFIG_SERIAL_AMBA_PL010 is not set
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_SERIAL_SIRFSOC is not set
-# CONFIG_SERIAL_TEGRA is not set
+CONFIG_SERIAL_AMBA_PL010=m
+CONFIG_SERIAL_AMBA_PL011=m
 # CONFIG_SERIAL_MFD_HSU is not set
 CONFIG_SERIAL_IMX=y
 CONFIG_SERIAL_IMX_CONSOLE=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_SERIAL_JSM=m
-CONFIG_SERIAL_VT8500=y
-CONFIG_SERIAL_VT8500_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_VT8500 is not set
 CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_OMAP=y
-CONFIG_SERIAL_OMAP_CONSOLE=y
 CONFIG_SERIAL_SCCNXP=m
 # CONFIG_SERIAL_TIMBERDALE is not set
 # CONFIG_SERIAL_ALTERA_JTAGUART is not set
@@ -2721,9 +2380,11 @@ CONFIG_SERIAL_SCCNXP=m
 # CONFIG_SERIAL_XILINX_PS_UART is not set
 CONFIG_SERIAL_ARC=m
 CONFIG_SERIAL_ARC_NR_PORTS=1
-CONFIG_SERIAL_RP2=m
-CONFIG_SERIAL_RP2_NR_UARTS=32
+# CONFIG_SERIAL_RP2 is not set
 # CONFIG_TTY_PRINTK is not set
+CONFIG_PRINTER=m
+CONFIG_LP_CONSOLE=y
+CONFIG_PPDEV=m
 # CONFIG_HVC_DCC is not set
 CONFIG_IPMI_HANDLER=m
 # CONFIG_IPMI_PANIC_EVENT is not set
@@ -2734,9 +2395,6 @@ CONFIG_IPMI_POWEROFF=m
 CONFIG_HW_RANDOM=y
 CONFIG_HW_RANDOM_TIMERIOMEM=m
 CONFIG_HW_RANDOM_ATMEL=m
-CONFIG_HW_RANDOM_BCM2835=y
-CONFIG_HW_RANDOM_OMAP=y
-# CONFIG_HW_RANDOM_MXC_RNGA is not set
 CONFIG_HW_RANDOM_EXYNOS=m
 CONFIG_NVRAM=y
 CONFIG_R3964=m
@@ -2762,41 +2420,36 @@ CONFIG_I2C_ALGOPCA=m
 #
 # PC SMBus host controller drivers
 #
-CONFIG_I2C_ALI1535=m
-CONFIG_I2C_ALI1563=m
-CONFIG_I2C_ALI15X3=m
-CONFIG_I2C_AMD756=m
-CONFIG_I2C_AMD8111=m
-CONFIG_I2C_I801=m
-CONFIG_I2C_ISCH=m
-CONFIG_I2C_PIIX4=m
-CONFIG_I2C_NFORCE2=m
-CONFIG_I2C_SIS5595=m
-CONFIG_I2C_SIS630=m
-CONFIG_I2C_SIS96X=m
-CONFIG_I2C_VIA=m
-CONFIG_I2C_VIAPRO=m
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
 
 #
 # I2C system bus drivers (mostly embedded / system-on-chip)
 #
-# CONFIG_I2C_BCM2835 is not set
 CONFIG_I2C_CBUS_GPIO=m
 # CONFIG_I2C_DESIGNWARE_PLATFORM is not set
 # CONFIG_I2C_DESIGNWARE_PCI is not set
 # CONFIG_I2C_EG20T is not set
-# CONFIG_I2C_GPIO is not set
+CONFIG_I2C_GPIO=m
 CONFIG_I2C_IMX=m
 # CONFIG_I2C_INTEL_MID is not set
-CONFIG_I2C_MV64XXX=m
 CONFIG_I2C_NOMADIK=y
 # CONFIG_I2C_OCORES is not set
-CONFIG_I2C_OMAP=y
 CONFIG_I2C_PCA_PLATFORM=m
 # CONFIG_I2C_PXA_PCI is not set
 CONFIG_I2C_SIMTEC=m
-CONFIG_I2C_SIRF=y
-CONFIG_I2C_TEGRA=y
 CONFIG_I2C_VERSATILE=m
 # CONFIG_I2C_XILINX is not set
 
@@ -2804,6 +2457,7 @@ CONFIG_I2C_VERSATILE=m
 # External I2C/SMBus adapter drivers
 #
 CONFIG_I2C_DIOLAN_U2C=m
+CONFIG_I2C_PARPORT=m
 CONFIG_I2C_PARPORT_LIGHT=m
 # CONFIG_I2C_TAOS_EVM is not set
 CONFIG_I2C_TINY_USB=m
@@ -2812,7 +2466,7 @@ CONFIG_I2C_VIPERBOARD=m
 #
 # Other I2C/SMBus bus drivers
 #
-# CONFIG_I2C_STUB is not set
+CONFIG_I2C_STUB=m
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
@@ -2841,6 +2495,7 @@ CONFIG_PPS=m
 #
 # CONFIG_PPS_CLIENT_KTIMER is not set
 # CONFIG_PPS_CLIENT_LDISC is not set
+# CONFIG_PPS_CLIENT_PARPORT is not set
 # CONFIG_PPS_CLIENT_GPIO is not set
 
 #
@@ -2865,39 +2520,14 @@ CONFIG_PINMUX=y
 CONFIG_PINCONF=y
 CONFIG_GENERIC_PINCONF=y
 # CONFIG_DEBUG_PINCTRL is not set
-CONFIG_PINCTRL_ABX500=y
-CONFIG_PINCTRL_AB8500=y
-CONFIG_PINCTRL_AB8540=y
-CONFIG_PINCTRL_AB9540=y
-CONFIG_PINCTRL_AB8505=y
-CONFIG_PINCTRL_BCM2835=y
 CONFIG_PINCTRL_IMX=y
-# CONFIG_PINCTRL_IMX35 is not set
 CONFIG_PINCTRL_IMX51=y
 CONFIG_PINCTRL_IMX53=y
 CONFIG_PINCTRL_IMX6Q=y
-CONFIG_PINCTRL_NOMADIK=y
-CONFIG_PINCTRL_DB8500=y
-CONFIG_PINCTRL_DB8540=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PINCTRL_SIRF=y
-CONFIG_PINCTRL_SUNXI=y
-CONFIG_PINCTRL_TEGRA=y
-CONFIG_PINCTRL_TEGRA20=y
-CONFIG_PINCTRL_TEGRA30=y
-CONFIG_PINCTRL_TEGRA114=y
-CONFIG_PINCTRL_SAMSUNG=y
-CONFIG_PINCTRL_EXYNOS=y
-CONFIG_PINCTRL_EXYNOS5440=y
-CONFIG_PINCTRL_MVEBU=y
-CONFIG_PINCTRL_ARMADA_370=y
-CONFIG_PINCTRL_ARMADA_XP=y
-CONFIG_PINCTRL_SPEAR=y
-CONFIG_PINCTRL_SPEAR1310=y
-CONFIG_PINCTRL_SPEAR1340=y
-CONFIG_PINCTRL_SPEAR_PLGPIO=y
+CONFIG_PINCTRL_SINGLE=m
+# CONFIG_PINCTRL_EXYNOS is not set
+# CONFIG_PINCTRL_EXYNOS5440 is not set
 CONFIG_PINCTRL_WMT=y
-# CONFIG_PINCTRL_WM8750 is not set
 CONFIG_PINCTRL_WM8850=y
 CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
 CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
@@ -2908,19 +2538,15 @@ CONFIG_OF_GPIO=y
 # CONFIG_DEBUG_GPIO is not set
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_GENERIC=y
-# CONFIG_GPIO_DA9052 is not set
-# CONFIG_GPIO_DA9055 is not set
 
 #
 # Memory mapped GPIO drivers:
 #
-# CONFIG_GPIO_GENERIC_PLATFORM is not set
+CONFIG_GPIO_GENERIC_PLATFORM=y
 # CONFIG_GPIO_EM is not set
-CONFIG_GPIO_MVEBU=y
 CONFIG_GPIO_MXC=y
 CONFIG_GPIO_PL061=y
 # CONFIG_GPIO_RCAR is not set
-CONFIG_GPIO_SPEAR_SPICS=y
 CONFIG_GPIO_TS5500=m
 # CONFIG_GPIO_VX855 is not set
 # CONFIG_GPIO_GRGPIO is not set
@@ -2930,25 +2556,16 @@ CONFIG_GPIO_TS5500=m
 #
 # CONFIG_GPIO_MAX7300 is not set
 # CONFIG_GPIO_MAX732X is not set
-# CONFIG_GPIO_MC9S08DZ60 is not set
 # CONFIG_GPIO_PCF857X is not set
-# CONFIG_GPIO_RC5T583 is not set
 # CONFIG_GPIO_SX150X is not set
-# CONFIG_GPIO_STMPE is not set
-# CONFIG_GPIO_TC3589X is not set
-# CONFIG_GPIO_TPS65912 is not set
 CONFIG_GPIO_TWL4030=m
-CONFIG_GPIO_TWL6040=m
-# CONFIG_GPIO_WM831X is not set
-# CONFIG_GPIO_WM8350 is not set
-# CONFIG_GPIO_WM8994 is not set
-# CONFIG_GPIO_ADP5520 is not set
 # CONFIG_GPIO_ADP5588 is not set
 CONFIG_GPIO_ADNP=m
 
 #
 # PCI GPIO expanders:
 #
+# CONFIG_GPIO_BT8XX is not set
 # CONFIG_GPIO_AMD8111 is not set
 # CONFIG_GPIO_ML_IOH is not set
 # CONFIG_GPIO_RDC321X is not set
@@ -2956,7 +2573,7 @@ CONFIG_GPIO_ADNP=m
 #
 # SPI GPIO expanders:
 #
-# CONFIG_GPIO_MCP23S08 is not set
+CONFIG_GPIO_MCP23S08=m
 
 #
 # AC97 GPIO expanders:
@@ -2965,9 +2582,6 @@ CONFIG_GPIO_ADNP=m
 #
 # MODULbus GPIO expanders:
 #
-# CONFIG_GPIO_PALMAS is not set
-# CONFIG_GPIO_TPS6586X is not set
-# CONFIG_GPIO_TPS65910 is not set
 
 #
 # USB GPIO expanders:
@@ -2985,7 +2599,6 @@ CONFIG_W1_MASTER_DS2482=m
 CONFIG_W1_MASTER_MXC=m
 CONFIG_W1_MASTER_DS1WM=m
 # CONFIG_W1_MASTER_GPIO is not set
-# CONFIG_HDQ_MASTER_OMAP is not set
 
 #
 # 1-wire Slaves
@@ -3009,39 +2622,29 @@ CONFIG_POWER_SUPPLY=y
 # CONFIG_PDA_POWER is not set
 # CONFIG_APM_POWER is not set
 CONFIG_GENERIC_ADC_BATTERY=m
-# CONFIG_MAX8925_POWER is not set
-# CONFIG_WM831X_BACKUP is not set
-# CONFIG_WM831X_POWER is not set
-# CONFIG_WM8350_POWER is not set
 # CONFIG_TEST_POWER is not set
-# CONFIG_BATTERY_88PM860X is not set
+CONFIG_BATTERY_88PM860X=m
 # CONFIG_BATTERY_DS2760 is not set
 # CONFIG_BATTERY_DS2780 is not set
 # CONFIG_BATTERY_DS2781 is not set
 # CONFIG_BATTERY_DS2782 is not set
 # CONFIG_BATTERY_SBS is not set
 # CONFIG_BATTERY_BQ27x00 is not set
-# CONFIG_BATTERY_DA9030 is not set
-# CONFIG_BATTERY_DA9052 is not set
 # CONFIG_BATTERY_MAX17040 is not set
 # CONFIG_BATTERY_MAX17042 is not set
+CONFIG_CHARGER_88PM860X=m
 # CONFIG_BATTERY_RX51 is not set
 # CONFIG_CHARGER_ISP1704 is not set
 # CONFIG_CHARGER_MAX8903 is not set
-# CONFIG_CHARGER_TWL4030 is not set
+CONFIG_CHARGER_TWL4030=m
 # CONFIG_CHARGER_LP8727 is not set
 # CONFIG_CHARGER_GPIO is not set
 # CONFIG_CHARGER_MANAGER is not set
-# CONFIG_CHARGER_MAX8997 is not set
-# CONFIG_CHARGER_MAX8998 is not set
 # CONFIG_CHARGER_BQ2415X is not set
 # CONFIG_CHARGER_SMB347 is not set
-# CONFIG_CHARGER_TPS65090 is not set
-# CONFIG_AB8500_BM is not set
 # CONFIG_BATTERY_GOLDFISH is not set
 CONFIG_POWER_RESET=y
 CONFIG_POWER_RESET_GPIO=y
-CONFIG_POWER_RESET_QNAP=y
 CONFIG_POWER_RESET_RESTART=y
 CONFIG_POWER_RESET_VEXPRESS=y
 CONFIG_POWER_AVS=y
@@ -3070,9 +2673,7 @@ CONFIG_SENSORS_ASC7621=m
 CONFIG_SENSORS_ATXP1=m
 CONFIG_SENSORS_DS620=m
 CONFIG_SENSORS_DS1621=m
-# CONFIG_SENSORS_DA9052_ADC is not set
-# CONFIG_SENSORS_DA9055 is not set
-CONFIG_SENSORS_I5K_AMB=m
+# CONFIG_SENSORS_I5K_AMB is not set
 CONFIG_SENSORS_F71805F=m
 CONFIG_SENSORS_F71882FG=m
 CONFIG_SENSORS_F75375S=m
@@ -3087,7 +2688,7 @@ CONFIG_SENSORS_IBMPEX=m
 CONFIG_SENSORS_IT87=m
 # CONFIG_SENSORS_JC42 is not set
 CONFIG_SENSORS_LINEAGE=m
-CONFIG_SENSORS_LM63=m
+CONFIG_SENSORS_LM63=y
 CONFIG_SENSORS_LM73=m
 CONFIG_SENSORS_LM75=m
 CONFIG_SENSORS_LM77=m
@@ -3133,7 +2734,7 @@ CONFIG_SENSORS_UCD9200=m
 # CONFIG_SENSORS_ZL6100 is not set
 CONFIG_SENSORS_SHT15=m
 CONFIG_SENSORS_SHT21=m
-CONFIG_SENSORS_SIS5595=m
+# CONFIG_SENSORS_SIS5595 is not set
 # CONFIG_SENSORS_SMM665 is not set
 CONFIG_SENSORS_DME1737=m
 CONFIG_SENSORS_EMC1403=m
@@ -3154,11 +2755,11 @@ CONFIG_SENSORS_THMC50=m
 CONFIG_SENSORS_TMP102=m
 CONFIG_SENSORS_TMP401=m
 CONFIG_SENSORS_TMP421=m
-# CONFIG_SENSORS_TWL4030_MADC is not set
+CONFIG_SENSORS_TWL4030_MADC=m
 CONFIG_SENSORS_VEXPRESS=m
-CONFIG_SENSORS_VIA686A=m
+# CONFIG_SENSORS_VIA686A is not set
 CONFIG_SENSORS_VT1211=m
-CONFIG_SENSORS_VT8231=m
+# CONFIG_SENSORS_VT8231 is not set
 CONFIG_SENSORS_W83781D=m
 CONFIG_SENSORS_W83791D=m
 CONFIG_SENSORS_W83792D=m
@@ -3169,8 +2770,6 @@ CONFIG_SENSORS_W83L785TS=m
 CONFIG_SENSORS_W83L786NG=m
 CONFIG_SENSORS_W83627HF=m
 CONFIG_SENSORS_W83627EHF=m
-# CONFIG_SENSORS_WM831X is not set
-# CONFIG_SENSORS_WM8350 is not set
 CONFIG_THERMAL=y
 CONFIG_THERMAL_HWMON=y
 CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
@@ -3179,10 +2778,9 @@ CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
 CONFIG_THERMAL_GOV_FAIR_SHARE=y
 CONFIG_THERMAL_GOV_STEP_WISE=y
 CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_CPU_THERMAL=y
 CONFIG_THERMAL_EMULATION=y
-# CONFIG_SPEAR_THERMAL is not set
-CONFIG_DB8500_THERMAL=y
-CONFIG_ARMADA_THERMAL=m
+CONFIG_IMX_THERMAL=m
 CONFIG_WATCHDOG=y
 CONFIG_WATCHDOG_CORE=y
 CONFIG_WATCHDOG_NOWAYOUT=y
@@ -3191,27 +2789,21 @@ CONFIG_WATCHDOG_NOWAYOUT=y
 # Watchdog Device Drivers
 #
 CONFIG_SOFT_WATCHDOG=m
-# CONFIG_DA9052_WATCHDOG is not set
-# CONFIG_DA9055_WATCHDOG is not set
-# CONFIG_WM831X_WATCHDOG is not set
-# CONFIG_WM8350_WATCHDOG is not set
-# CONFIG_ARM_SP805_WATCHDOG is not set
+CONFIG_ARM_SP805_WATCHDOG=m
 # CONFIG_DW_WATCHDOG is not set
-# CONFIG_MPCORE_WATCHDOG is not set
-CONFIG_OMAP_WATCHDOG=y
-# CONFIG_TWL4030_WATCHDOG is not set
+CONFIG_MPCORE_WATCHDOG=m
+CONFIG_TWL4030_WATCHDOG=m
 # CONFIG_MAX63XX_WATCHDOG is not set
 CONFIG_IMX2_WDT=m
-CONFIG_UX500_WATCHDOG=y
 CONFIG_RETU_WATCHDOG=m
-CONFIG_ALIM7101_WDT=m
-CONFIG_I6300ESB_WDT=m
+# CONFIG_ALIM7101_WDT is not set
+# CONFIG_I6300ESB_WDT is not set
 
 #
 # PCI-based Watchdog Cards
 #
-CONFIG_PCIPCWATCHDOG=m
-CONFIG_WDTPCI=m
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
 
 #
 # USB-based Watchdog Cards
@@ -3246,93 +2838,78 @@ CONFIG_BCMA_POSSIBLE=y
 # Multifunction device drivers
 #
 CONFIG_MFD_CORE=y
-CONFIG_MFD_AS3711=y
-CONFIG_PMIC_ADP5520=y
-CONFIG_MFD_AAT2870_CORE=y
+# CONFIG_MFD_AS3711 is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_AAT2870_CORE is not set
 # CONFIG_MFD_CROS_EC is not set
 # CONFIG_MFD_ASIC3 is not set
-CONFIG_PMIC_DA903X=y
-CONFIG_PMIC_DA9052=y
-CONFIG_MFD_DA9052_I2C=y
-CONFIG_MFD_DA9055=y
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_DA9052_I2C is not set
+# CONFIG_MFD_DA9055 is not set
 # CONFIG_MFD_MC13XXX_I2C is not set
 # CONFIG_HTC_EGPIO is not set
 # CONFIG_HTC_PASIC3 is not set
-CONFIG_HTC_I2CPLD=y
-CONFIG_LPC_ICH=m
-CONFIG_LPC_SCH=m
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_LPC_ICH is not set
+# CONFIG_LPC_SCH is not set
 # CONFIG_MFD_JANZ_CMODIO is not set
-CONFIG_MFD_88PM800=m
-CONFIG_MFD_88PM805=m
+CONFIG_MFD_88PM800=y
+CONFIG_MFD_88PM805=y
 CONFIG_MFD_88PM860X=y
-CONFIG_MFD_MAX77686=y
-CONFIG_MFD_MAX77693=y
-CONFIG_MFD_MAX8907=m
-CONFIG_MFD_MAX8925=y
-CONFIG_MFD_MAX8997=y
-CONFIG_MFD_MAX8998=y
+# CONFIG_MFD_MAX77686 is not set
+# CONFIG_MFD_MAX77693 is not set
+# CONFIG_MFD_MAX8907 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
 CONFIG_MFD_VIPERBOARD=m
 CONFIG_MFD_RETU=m
 # CONFIG_MFD_PCF50633 is not set
 # CONFIG_UCB1400_CORE is not set
 # CONFIG_MFD_RDC321X is not set
-CONFIG_MFD_RTSX_PCI=m
-CONFIG_MFD_RC5T583=y
-CONFIG_MFD_SEC_CORE=y
+# CONFIG_MFD_RTSX_PCI is not set
+# CONFIG_MFD_RC5T583 is not set
+# CONFIG_MFD_SEC_CORE is not set
 # CONFIG_MFD_SI476X_CORE is not set
 CONFIG_MFD_SM501=m
 CONFIG_MFD_SM501_GPIO=y
-CONFIG_MFD_SMSC=y
+# CONFIG_MFD_SMSC is not set
 CONFIG_ABX500_CORE=y
-CONFIG_AB3100_CORE=y
-CONFIG_AB3100_OTP=y
-CONFIG_AB8500_CORE=y
-# CONFIG_AB8500_DEBUG is not set
-CONFIG_AB8500_GPADC=y
-CONFIG_MFD_DB8500_PRCMU=y
-CONFIG_MFD_STMPE=y
-
-#
-# STMicroelectronics STMPE Interface Drivers
-#
-CONFIG_STMPE_I2C=y
+# CONFIG_AB3100_CORE is not set
+# CONFIG_MFD_STMPE is not set
 CONFIG_MFD_SYSCON=y
 # CONFIG_MFD_TI_AM335X_TSCADC is not set
-CONFIG_MFD_LP8788=y
-CONFIG_MFD_OMAP_USB_HOST=y
-CONFIG_MFD_PALMAS=y
+# CONFIG_MFD_LP8788 is not set
+# CONFIG_MFD_PALMAS is not set
 # CONFIG_TPS6105X is not set
 # CONFIG_TPS65010 is not set
 # CONFIG_TPS6507X is not set
-CONFIG_MFD_TPS65090=y
+# CONFIG_MFD_TPS65090 is not set
 # CONFIG_MFD_TPS65217 is not set
-CONFIG_MFD_TPS6586X=y
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_TPS65912=y
-CONFIG_MFD_TPS65912_I2C=y
-CONFIG_MFD_TPS80031=y
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_TPS65910 is not set
+# CONFIG_MFD_TPS65912 is not set
+# CONFIG_MFD_TPS65912_I2C is not set
+# CONFIG_MFD_TPS80031 is not set
 CONFIG_TWL4030_CORE=y
 CONFIG_TWL4030_MADC=m
 CONFIG_TWL4030_POWER=y
 CONFIG_MFD_TWL4030_AUDIO=y
-CONFIG_TWL6040_CORE=y
-CONFIG_MENELAUS=y
+# CONFIG_TWL6040_CORE is not set
 CONFIG_MFD_WL1273_CORE=m
 CONFIG_MFD_LM3533=m
 # CONFIG_MFD_TIMBERDALE is not set
-CONFIG_MFD_TC3589X=y
+# CONFIG_MFD_TC3589X is not set
 # CONFIG_MFD_TMIO is not set
 # CONFIG_MFD_T7L66XB is not set
 # CONFIG_MFD_TC6387XB is not set
 # CONFIG_MFD_TC6393XB is not set
-CONFIG_MFD_VX855=m
+# CONFIG_MFD_VX855 is not set
 # CONFIG_MFD_ARIZONA_I2C is not set
-CONFIG_MFD_WM8400=y
-CONFIG_MFD_WM831X=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_WM8350=y
-CONFIG_MFD_WM8350_I2C=y
-CONFIG_MFD_WM8994=y
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
 CONFIG_VEXPRESS_CONFIG=y
 CONFIG_REGULATOR=y
 # CONFIG_REGULATOR_DEBUG is not set
@@ -3340,56 +2917,28 @@ CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
 # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-CONFIG_REGULATOR_GPIO=y
-CONFIG_REGULATOR_AD5398=m
-CONFIG_REGULATOR_AAT2870=m
-CONFIG_REGULATOR_DA903X=m
-CONFIG_REGULATOR_DA9052=m
-CONFIG_REGULATOR_DA9055=m
-CONFIG_REGULATOR_FAN53555=m
+# CONFIG_REGULATOR_GPIO is not set
+# CONFIG_REGULATOR_AD5398 is not set
+# CONFIG_REGULATOR_FAN53555 is not set
 CONFIG_REGULATOR_ANATOP=m
-CONFIG_REGULATOR_ISL6271A=m
+# CONFIG_REGULATOR_ISL6271A is not set
 CONFIG_REGULATOR_88PM8607=y
-CONFIG_REGULATOR_MAX1586=m
-CONFIG_REGULATOR_MAX8649=m
-CONFIG_REGULATOR_MAX8660=m
-CONFIG_REGULATOR_MAX8907=m
-CONFIG_REGULATOR_MAX8925=m
-CONFIG_REGULATOR_MAX8952=m
-CONFIG_REGULATOR_MAX8973=m
-CONFIG_REGULATOR_MAX8997=m
-CONFIG_REGULATOR_MAX8998=m
-CONFIG_REGULATOR_MAX77686=m
-CONFIG_REGULATOR_LP3971=m
-CONFIG_REGULATOR_LP3972=m
-CONFIG_REGULATOR_LP872X=y
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+# CONFIG_REGULATOR_MAX8952 is not set
+# CONFIG_REGULATOR_MAX8973 is not set
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_LP3972 is not set
+# CONFIG_REGULATOR_LP872X is not set
 CONFIG_REGULATOR_LP8755=m
-CONFIG_REGULATOR_LP8788=y
-CONFIG_REGULATOR_RC5T583=m
-CONFIG_REGULATOR_S2MPS11=m
-CONFIG_REGULATOR_S5M8767=m
-CONFIG_REGULATOR_AB3100=y
-CONFIG_REGULATOR_AB8500=y
-CONFIG_REGULATOR_DBX500_PRCMU=y
-CONFIG_REGULATOR_DB8500_PRCMU=y
-CONFIG_REGULATOR_PALMAS=m
-CONFIG_REGULATOR_TPS51632=m
-CONFIG_REGULATOR_TPS62360=m
-CONFIG_REGULATOR_TPS65023=m
-CONFIG_REGULATOR_TPS6507X=m
-CONFIG_REGULATOR_TPS65090=m
-CONFIG_REGULATOR_TPS6586X=m
-CONFIG_REGULATOR_TPS65910=m
-CONFIG_REGULATOR_TPS65912=m
-CONFIG_REGULATOR_TPS80031=m
+# CONFIG_REGULATOR_TPS51632 is not set
+# CONFIG_REGULATOR_TPS62360 is not set
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
 CONFIG_REGULATOR_TWL4030=y
 CONFIG_REGULATOR_VEXPRESS=m
-CONFIG_REGULATOR_WM831X=m
-CONFIG_REGULATOR_WM8350=m
-CONFIG_REGULATOR_WM8400=m
-CONFIG_REGULATOR_WM8994=m
-CONFIG_REGULATOR_AS3711=m
-CONFIG_MEDIA_SUPPORT=m
+CONFIG_MEDIA_SUPPORT=y
 
 #
 # Multimedia core support
@@ -3400,15 +2949,14 @@ CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
 # CONFIG_MEDIA_RADIO_SUPPORT is not set
 CONFIG_MEDIA_RC_SUPPORT=y
 CONFIG_MEDIA_CONTROLLER=y
-CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_DEV=y
 CONFIG_VIDEO_V4L2_SUBDEV_API=y
-CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_V4L2=y
 # CONFIG_VIDEO_ADV_DEBUG is not set
 # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
 CONFIG_VIDEO_TUNER=m
 CONFIG_V4L2_MEM2MEM_DEV=m
 CONFIG_VIDEOBUF_GEN=m
-CONFIG_VIDEOBUF_DMA_SG=m
 CONFIG_VIDEOBUF_VMALLOC=m
 CONFIG_VIDEOBUF_DMA_CONTIG=m
 CONFIG_VIDEOBUF_DVB=m
@@ -3416,8 +2964,8 @@ CONFIG_VIDEOBUF2_CORE=m
 CONFIG_VIDEOBUF2_MEMOPS=m
 CONFIG_VIDEOBUF2_DMA_CONTIG=m
 CONFIG_VIDEOBUF2_VMALLOC=m
-# CONFIG_VIDEO_V4L2_INT_DEVICE is not set
-CONFIG_DVB_CORE=m
+CONFIG_VIDEO_V4L2_INT_DEVICE=m
+CONFIG_DVB_CORE=y
 CONFIG_DVB_NET=y
 CONFIG_TTPCI_EEPROM=m
 CONFIG_DVB_MAX_ADAPTERS=8
@@ -3426,7 +2974,7 @@ CONFIG_DVB_DYNAMIC_MINORS=y
 #
 # Media drivers
 #
-CONFIG_RC_CORE=m
+CONFIG_RC_CORE=y
 CONFIG_RC_MAP=m
 CONFIG_RC_DECODERS=y
 CONFIG_LIRC=m
@@ -3440,7 +2988,7 @@ CONFIG_IR_RC5_SZ_DECODER=m
 CONFIG_IR_SANYO_DECODER=m
 CONFIG_IR_MCE_KBD_DECODER=m
 CONFIG_RC_DEVICES=y
-CONFIG_RC_ATI_REMOTE=m
+# CONFIG_RC_ATI_REMOTE is not set
 CONFIG_IR_IMON=m
 CONFIG_IR_MCEUSB=m
 CONFIG_IR_REDRAT3=m
@@ -3497,7 +3045,7 @@ CONFIG_USB_GSPCA_STK014=m
 CONFIG_USB_GSPCA_STV0680=m
 CONFIG_USB_GSPCA_SUNPLUS=m
 CONFIG_USB_GSPCA_T613=m
-CONFIG_USB_GSPCA_TOPRO=m
+# CONFIG_USB_GSPCA_TOPRO is not set
 CONFIG_USB_GSPCA_TV8532=m
 CONFIG_USB_GSPCA_VC032X=m
 CONFIG_USB_GSPCA_VICAM=m
@@ -3523,7 +3071,7 @@ CONFIG_VIDEO_HDPVR=m
 CONFIG_VIDEO_TLG2300=m
 CONFIG_VIDEO_USBVISION=m
 CONFIG_VIDEO_STK1160=m
-CONFIG_VIDEO_STK1160_AC97=y
+# CONFIG_VIDEO_STK1160_AC97 is not set
 
 #
 # Analog/digital TV USB devices
@@ -3582,8 +3130,8 @@ CONFIG_DVB_USB_LME2510=m
 CONFIG_DVB_USB_MXL111SF=m
 CONFIG_DVB_USB_RTL28XXU=m
 CONFIG_DVB_USB_DVBSKY=m
-CONFIG_DVB_TTUSB_BUDGET=m
-CONFIG_DVB_TTUSB_DEC=m
+# CONFIG_DVB_TTUSB_BUDGET is not set
+# CONFIG_DVB_TTUSB_DEC is not set
 CONFIG_SMS_USB_DRV=m
 CONFIG_DVB_B2C2_FLEXCOP_USB=m
 # CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set
@@ -3595,79 +3143,18 @@ CONFIG_VIDEO_EM28XX=m
 CONFIG_VIDEO_EM28XX_ALSA=m
 CONFIG_VIDEO_EM28XX_DVB=m
 CONFIG_VIDEO_EM28XX_RC=m
-CONFIG_MEDIA_PCI_SUPPORT=y
-
-#
-# Media capture support
-#
-
-#
-# Media capture/analog TV support
-#
-CONFIG_VIDEO_IVTV=m
-CONFIG_VIDEO_IVTV_ALSA=m
-CONFIG_VIDEO_FB_IVTV=m
-CONFIG_VIDEO_HEXIUM_GEMINI=m
-CONFIG_VIDEO_HEXIUM_ORION=m
-CONFIG_VIDEO_MXB=m
-
-#
-# Media capture/analog/hybrid TV support
-#
-CONFIG_VIDEO_CX18=m
-CONFIG_VIDEO_CX18_ALSA=m
-CONFIG_VIDEO_CX23885=m
-CONFIG_MEDIA_ALTERA_CI=m
-CONFIG_VIDEO_CX25821=m
-CONFIG_VIDEO_CX25821_ALSA=m
-CONFIG_VIDEO_CX88=m
-CONFIG_VIDEO_CX88_ALSA=m
-CONFIG_VIDEO_CX88_BLACKBIRD=m
-CONFIG_VIDEO_CX88_DVB=m
-CONFIG_VIDEO_CX88_VP3054=m
-CONFIG_VIDEO_CX88_MPEG=m
-CONFIG_VIDEO_BT848=m
-CONFIG_DVB_BT8XX=m
-CONFIG_VIDEO_SAA7134=m
-CONFIG_VIDEO_SAA7134_ALSA=m
-CONFIG_VIDEO_SAA7134_RC=y
-CONFIG_VIDEO_SAA7134_DVB=m
-CONFIG_VIDEO_SAA7164=m
-
-#
-# Media digital TV PCI Adapters
-#
-CONFIG_DVB_AV7110=m
-CONFIG_DVB_AV7110_OSD=y
-CONFIG_DVB_BUDGET_CORE=m
-CONFIG_DVB_BUDGET=m
-CONFIG_DVB_BUDGET_CI=m
-CONFIG_DVB_BUDGET_AV=m
-CONFIG_DVB_BUDGET_PATCH=m
-CONFIG_DVB_B2C2_FLEXCOP_PCI=m
-# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set
-CONFIG_DVB_PLUTO2=m
-CONFIG_DVB_DM1105=m
-CONFIG_DVB_PT1=m
-CONFIG_MANTIS_CORE=m
-CONFIG_DVB_MANTIS=m
-CONFIG_DVB_HOPPER=m
-CONFIG_DVB_NGENE=m
-# CONFIG_DVB_DDBRIDGE is not set
+# CONFIG_MEDIA_PCI_SUPPORT is not set
 CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_VIDEO_CAFE_CCIC=m
-CONFIG_VIDEO_DM6446_CCDC=m
-CONFIG_VIDEO_OMAP2_VOUT_VRFB=y
-CONFIG_VIDEO_OMAP2_VOUT=m
+# CONFIG_VIDEO_CAFE_CCIC is not set
 CONFIG_VIDEO_TIMBERDALE=m
 CONFIG_SOC_CAMERA=m
 CONFIG_SOC_CAMERA_PLATFORM=m
 CONFIG_MX3_VIDEO=y
 CONFIG_VIDEO_MX3=m
-CONFIG_VIDEO_SH_MOBILE_CSI2=m
-CONFIG_VIDEO_SH_MOBILE_CEU=m
+# CONFIG_VIDEO_SH_MOBILE_CSI2 is not set
+# CONFIG_VIDEO_SH_MOBILE_CEU is not set
 CONFIG_V4L_MEM2MEM_DRIVERS=y
-CONFIG_VIDEO_CODA=m
+# CONFIG_VIDEO_CODA is not set
 CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
 CONFIG_VIDEO_SH_VEU=m
 # CONFIG_V4L_TEST_DRIVERS is not set
@@ -3675,24 +3162,17 @@ CONFIG_VIDEO_SH_VEU=m
 #
 # Supported MMC/SDIO adapters
 #
-CONFIG_SMS_SDIO_DRV=m
-
-#
-# Supported FireWire (IEEE 1394) Adapters
-#
-# CONFIG_DVB_FIREDTV is not set
+# CONFIG_SMS_SDIO_DRV is not set
+# CONFIG_MEDIA_PARPORT_SUPPORT is not set
 CONFIG_MEDIA_COMMON_OPTIONS=y
 
 #
 # common driver options
 #
 CONFIG_VIDEO_CX2341X=m
-CONFIG_VIDEO_BTCX=m
 CONFIG_VIDEO_TVEEPROM=m
 CONFIG_CYPRESS_FIRMWARE=m
 CONFIG_DVB_B2C2_FLEXCOP=m
-CONFIG_VIDEO_SAA7146=m
-CONFIG_VIDEO_SAA7146_VV=m
 CONFIG_SMS_SIANO_MDTV=m
 CONFIG_SMS_SIANO_RC=y
 # CONFIG_SMS_SIANO_DEBUGFS is not set
@@ -3702,27 +3182,18 @@ CONFIG_SMS_SIANO_RC=y
 #
 CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
 CONFIG_MEDIA_ATTACH=y
-CONFIG_VIDEO_IR_I2C=m
+CONFIG_VIDEO_IR_I2C=y
 
 #
 # Audio decoders, processors and mixers
 #
-CONFIG_VIDEO_TVAUDIO=m
-CONFIG_VIDEO_TDA7432=m
-CONFIG_VIDEO_TDA9840=m
-CONFIG_VIDEO_TEA6415C=m
-CONFIG_VIDEO_TEA6420=m
 CONFIG_VIDEO_MSP3400=m
-CONFIG_VIDEO_CS5345=m
 CONFIG_VIDEO_CS53L32A=m
 CONFIG_VIDEO_WM8775=m
-CONFIG_VIDEO_WM8739=m
-CONFIG_VIDEO_VP27SMPX=m
 
 #
 # RDS decoders
 #
-CONFIG_VIDEO_SAA6588=m
 
 #
 # Video decoders
@@ -3734,18 +3205,15 @@ CONFIG_VIDEO_TVP5150=m
 #
 # Video and audio decoders
 #
-CONFIG_VIDEO_SAA717X=m
 CONFIG_VIDEO_CX25840=m
 
 #
 # Video encoders
 #
-CONFIG_VIDEO_SAA7127=m
 
 #
 # Camera sensor devices
 #
-CONFIG_VIDEO_OV7670=m
 CONFIG_VIDEO_MT9V011=m
 
 #
@@ -3755,13 +3223,10 @@ CONFIG_VIDEO_MT9V011=m
 #
 # Video improvement chips
 #
-CONFIG_VIDEO_UPD64031A=m
-CONFIG_VIDEO_UPD64083=m
 
 #
 # Miscelaneous helper chips
 #
-CONFIG_VIDEO_M52790=m
 
 #
 # Sensors used on soc_camera driver
@@ -3784,24 +3249,23 @@ CONFIG_SOC_CAMERA_OV9640=m
 CONFIG_SOC_CAMERA_OV9740=m
 CONFIG_SOC_CAMERA_RJ54N1=m
 CONFIG_SOC_CAMERA_TW9910=m
-CONFIG_MEDIA_TUNER=m
-CONFIG_MEDIA_TUNER_SIMPLE=m
-CONFIG_MEDIA_TUNER_TDA8290=m
-CONFIG_MEDIA_TUNER_TDA827X=m
-CONFIG_MEDIA_TUNER_TDA18271=m
-CONFIG_MEDIA_TUNER_TDA9887=m
-CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER=y
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA827X=y
+CONFIG_MEDIA_TUNER_TDA18271=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_MT20XX=y
 CONFIG_MEDIA_TUNER_MT2060=m
 CONFIG_MEDIA_TUNER_MT2063=m
 CONFIG_MEDIA_TUNER_MT2266=m
-CONFIG_MEDIA_TUNER_MT2131=m
 CONFIG_MEDIA_TUNER_QT1010=m
-CONFIG_MEDIA_TUNER_XC2028=m
-CONFIG_MEDIA_TUNER_XC5000=m
-CONFIG_MEDIA_TUNER_XC4000=m
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_XC4000=y
 CONFIG_MEDIA_TUNER_MXL5005S=m
 CONFIG_MEDIA_TUNER_MXL5007T=m
-CONFIG_MEDIA_TUNER_MC44S803=m
+CONFIG_MEDIA_TUNER_MC44S803=y
 CONFIG_MEDIA_TUNER_MAX2165=m
 CONFIG_MEDIA_TUNER_TDA18218=m
 CONFIG_MEDIA_TUNER_FC0011=m
@@ -3831,10 +3295,8 @@ CONFIG_DVB_TDA18271C2DD=m
 #
 # DVB-S (satellite) frontends
 #
-CONFIG_DVB_CX24110=m
 CONFIG_DVB_CX24123=m
 CONFIG_DVB_MT312=m
-CONFIG_DVB_ZL10036=m
 CONFIG_DVB_ZL10039=m
 CONFIG_DVB_S5H1420=m
 CONFIG_DVB_STV0288=m
@@ -3842,32 +3304,22 @@ CONFIG_DVB_STB6000=m
 CONFIG_DVB_STV0299=m
 CONFIG_DVB_STV6110=m
 CONFIG_DVB_STV0900=m
-CONFIG_DVB_TDA8083=m
 CONFIG_DVB_TDA10086=m
-CONFIG_DVB_TDA8261=m
-CONFIG_DVB_VES1X93=m
 CONFIG_DVB_TUNER_ITD1000=m
 CONFIG_DVB_TUNER_CX24113=m
 CONFIG_DVB_TDA826X=m
-CONFIG_DVB_TUA6100=m
 CONFIG_DVB_CX24116=m
 CONFIG_DVB_M88DS3103=m
-CONFIG_DVB_M88DC2800=m
 CONFIG_DVB_SI21XX=m
 CONFIG_DVB_TS2020=m
 CONFIG_DVB_DS3000=m
-CONFIG_DVB_MB86A16=m
 CONFIG_DVB_TDA10071=m
 
 #
 # DVB-T (terrestrial) frontends
 #
-CONFIG_DVB_SP8870=m
-CONFIG_DVB_SP887X=m
-CONFIG_DVB_CX22700=m
 CONFIG_DVB_CX22702=m
 CONFIG_DVB_DRXD=m
-CONFIG_DVB_L64781=m
 CONFIG_DVB_TDA1004X=m
 CONFIG_DVB_NXT6000=m
 CONFIG_DVB_MT352=m
@@ -3879,7 +3331,6 @@ CONFIG_DVB_DIB7000P=m
 CONFIG_DVB_TDA10048=m
 CONFIG_DVB_AF9013=m
 CONFIG_DVB_EC100=m
-CONFIG_DVB_STV0367=m
 CONFIG_DVB_CXD2820R=m
 CONFIG_DVB_RTL2830=m
 CONFIG_DVB_RTL2832=m
@@ -3887,8 +3338,6 @@ CONFIG_DVB_RTL2832=m
 #
 # DVB-C (cable) frontends
 #
-CONFIG_DVB_VES1820=m
-CONFIG_DVB_TDA10021=m
 CONFIG_DVB_TDA10023=m
 CONFIG_DVB_STV0297=m
 
@@ -3896,8 +3345,6 @@ CONFIG_DVB_STV0297=m
 # ATSC (North American/Korean Terrestrial/Cable DTV) frontends
 #
 CONFIG_DVB_NXT200X=m
-CONFIG_DVB_OR51211=m
-CONFIG_DVB_OR51132=m
 CONFIG_DVB_BCM3510=m
 CONFIG_DVB_LGDT330X=m
 CONFIG_DVB_LGDT3305=m
@@ -3927,13 +3374,11 @@ CONFIG_DVB_TUNER_DIB0090=m
 #
 CONFIG_DVB_LNBP21=m
 CONFIG_DVB_LNBP22=m
-CONFIG_DVB_ISL6405=m
 CONFIG_DVB_ISL6421=m
 CONFIG_DVB_ISL6423=m
 CONFIG_DVB_A8293=m
 CONFIG_DVB_LGS8GXX=m
 CONFIG_DVB_ATBM8830=m
-CONFIG_DVB_TDA665x=m
 CONFIG_DVB_IX2505V=m
 CONFIG_DVB_IT913X_FE=m
 CONFIG_DVB_M88RS2000=m
@@ -3953,7 +3398,8 @@ CONFIG_DRM=m
 CONFIG_DRM_USB=m
 CONFIG_DRM_KMS_HELPER=m
 # CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
-CONFIG_DRM_TTM=m
+CONFIG_DRM_GEM_CMA_HELPER=y
+CONFIG_DRM_KMS_CMA_HELPER=y
 
 #
 # I2C encoder or helper chips
@@ -3961,171 +3407,120 @@ CONFIG_DRM_TTM=m
 CONFIG_DRM_I2C_CH7006=m
 CONFIG_DRM_I2C_SIL164=m
 CONFIG_DRM_I2C_NXP_TDA998X=m
-CONFIG_DRM_TDFX=m
-CONFIG_DRM_R128=m
-CONFIG_DRM_RADEON=m
-# CONFIG_DRM_RADEON_UMS is not set
-CONFIG_DRM_NOUVEAU=m
-CONFIG_NOUVEAU_DEBUG=5
-CONFIG_NOUVEAU_DEBUG_DEFAULT=3
-CONFIG_DRM_NOUVEAU_BACKLIGHT=y
-CONFIG_DRM_MGA=m
-CONFIG_DRM_VIA=m
-CONFIG_DRM_SAVAGE=m
+# CONFIG_DRM_TDFX is not set
+# CONFIG_DRM_R128 is not set
+# CONFIG_DRM_RADEON is not set
+# CONFIG_DRM_NOUVEAU is not set
+# CONFIG_DRM_MGA is not set
+# CONFIG_DRM_VIA is not set
+# CONFIG_DRM_SAVAGE is not set
 CONFIG_DRM_EXYNOS=m
 CONFIG_DRM_EXYNOS_DMABUF=y
 CONFIG_DRM_EXYNOS_HDMI=y
 CONFIG_DRM_EXYNOS_VIDI=y
 CONFIG_DRM_EXYNOS_G2D=y
-CONFIG_DRM_VMWGFX=m
-# CONFIG_DRM_VMWGFX_FBCON is not set
+# CONFIG_DRM_VMWGFX is not set
 CONFIG_DRM_UDL=m
-CONFIG_DRM_AST=m
-CONFIG_DRM_MGAG200=m
-CONFIG_DRM_CIRRUS_QEMU=m
-CONFIG_DRM_OMAP=m
-CONFIG_DRM_OMAP_NUM_CRTCS=1
+# CONFIG_DRM_AST is not set
+# CONFIG_DRM_MGAG200 is not set
+# CONFIG_DRM_CIRRUS_QEMU is not set
 # CONFIG_DRM_TILCDC is not set
-CONFIG_DRM_QXL=m
+# CONFIG_DRM_QXL is not set
 # CONFIG_TEGRA_HOST1X is not set
-CONFIG_VGASTATE=m
-CONFIG_VIDEO_OUTPUT_CONTROL=m
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_VIDEOMODE_HELPERS=y
 CONFIG_HDMI=y
-CONFIG_FB=m
+CONFIG_FB=y
 # CONFIG_FIRMWARE_EDID is not set
-CONFIG_FB_DDC=m
+# CONFIG_FB_DDC is not set
 # CONFIG_FB_BOOT_VESA_SUPPORT is not set
 CONFIG_FB_CFB_FILLRECT=m
 CONFIG_FB_CFB_COPYAREA=m
 CONFIG_FB_CFB_IMAGEBLIT=m
 # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-CONFIG_FB_SYS_FILLRECT=m
-CONFIG_FB_SYS_COPYAREA=m
-CONFIG_FB_SYS_IMAGEBLIT=m
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_IMAGEBLIT=y
 # CONFIG_FB_FOREIGN_ENDIAN is not set
 CONFIG_FB_SYS_FOPS=m
 CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_SVGALIB=m
+# CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
-CONFIG_FB_BACKLIGHT=y
+# CONFIG_FB_BACKLIGHT is not set
 CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_TILEBLITTING=y
+# CONFIG_FB_TILEBLITTING is not set
 
 #
 # Frame buffer hardware drivers
 #
-CONFIG_FB_CIRRUS=m
-CONFIG_FB_PM2=m
-# CONFIG_FB_PM2_FIFO_DISCONNECT is not set
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
 CONFIG_FB_ARMCLCD=m
-# CONFIG_FB_IMX is not set
-CONFIG_FB_CYBER2000=m
-CONFIG_FB_CYBER2000_DDC=y
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
 # CONFIG_FB_UVESA is not set
-CONFIG_FB_S1D13XXX=m
+# CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_NVIDIA is not set
-CONFIG_FB_RIVA=m
-# CONFIG_FB_RIVA_I2C is not set
-# CONFIG_FB_RIVA_DEBUG is not set
-CONFIG_FB_RIVA_BACKLIGHT=y
-CONFIG_FB_I740=m
-CONFIG_FB_MATROX=m
-CONFIG_FB_MATROX_MILLENIUM=y
-CONFIG_FB_MATROX_MYSTIQUE=y
-# CONFIG_FB_MATROX_G is not set
-CONFIG_FB_MATROX_I2C=m
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_I740 is not set
+# CONFIG_FB_MATROX is not set
 # CONFIG_FB_RADEON is not set
 # CONFIG_FB_ATY128 is not set
-CONFIG_FB_ATY=m
-CONFIG_FB_ATY_CT=y
-CONFIG_FB_ATY_GENERIC_LCD=y
-CONFIG_FB_ATY_GX=y
-CONFIG_FB_ATY_BACKLIGHT=y
-CONFIG_FB_S3=m
-CONFIG_FB_S3_DDC=y
-CONFIG_FB_SAVAGE=m
-CONFIG_FB_SAVAGE_I2C=y
-CONFIG_FB_SAVAGE_ACCEL=y
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
 # CONFIG_FB_SIS is not set
-CONFIG_FB_NEOMAGIC=m
-CONFIG_FB_KYRO=m
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
 # CONFIG_FB_3DFX is not set
-CONFIG_FB_VOODOO1=m
-CONFIG_FB_VT8623=m
-CONFIG_FB_TRIDENT=m
-CONFIG_FB_ARK=m
-CONFIG_FB_PM3=m
-CONFIG_FB_CARMINE=m
-CONFIG_FB_CARMINE_DRAM_EVAL=y
-# CONFIG_CARMINE_DRAM_CUSTOM is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_VT8500 is not set
+# CONFIG_FB_WM8505 is not set
 # CONFIG_FB_TMIO is not set
 # CONFIG_FB_SM501 is not set
 CONFIG_FB_SMSCUFX=m
-CONFIG_FB_UDL=m
+# CONFIG_FB_UDL is not set
 # CONFIG_FB_GOLDFISH is not set
 # CONFIG_FB_VIRTUAL is not set
-CONFIG_FB_METRONOME=m
-CONFIG_FB_MB862XX=m
-CONFIG_FB_MB862XX_PCI_GDC=y
-CONFIG_FB_MB862XX_I2C=y
-CONFIG_FB_MX3=m
-CONFIG_FB_BROADSHEET=m
-CONFIG_FB_AUO_K190X=m
-CONFIG_FB_AUO_K1900=m
-CONFIG_FB_AUO_K1901=m
-CONFIG_OMAP2_VRFB=y
-CONFIG_OMAP2_DSS=y
-# CONFIG_OMAP2_DSS_DEBUG is not set
-# CONFIG_OMAP2_DSS_DEBUGFS is not set
-CONFIG_OMAP2_DSS_DPI=y
-# CONFIG_OMAP2_DSS_RFBI is not set
-CONFIG_OMAP2_DSS_VENC=y
-CONFIG_OMAP4_DSS_HDMI=y
-CONFIG_OMAP4_DSS_HDMI_AUDIO=y
-# CONFIG_OMAP2_DSS_SDI is not set
-# CONFIG_OMAP2_DSS_DSI is not set
-CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=1
-CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET=y
-# CONFIG_FB_OMAP2 is not set
-
-#
-# OMAP2/3 Display Device Drivers
-#
-CONFIG_PANEL_GENERIC_DPI=y
-CONFIG_PANEL_TFP410=m
-CONFIG_PANEL_SHARP_LS037V7DW01=y
-# CONFIG_PANEL_PICODLP is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_MX3 is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_FB_AUO_K190X is not set
+# CONFIG_FB_SIMPLE is not set
 # CONFIG_EXYNOS_VIDEO is not set
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=m
-# CONFIG_LCD_PLATFORM is not set
+CONFIG_LCD_PLATFORM=m
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 # CONFIG_BACKLIGHT_GENERIC is not set
 # CONFIG_BACKLIGHT_LM3533 is not set
 # CONFIG_BACKLIGHT_PWM is not set
-# CONFIG_BACKLIGHT_DA903X is not set
-# CONFIG_BACKLIGHT_DA9052 is not set
-# CONFIG_BACKLIGHT_MAX8925 is not set
-# CONFIG_BACKLIGHT_WM831X is not set
-# CONFIG_BACKLIGHT_ADP5520 is not set
 # CONFIG_BACKLIGHT_ADP8860 is not set
 # CONFIG_BACKLIGHT_ADP8870 is not set
 # CONFIG_BACKLIGHT_88PM860X is not set
-# CONFIG_BACKLIGHT_AAT2870 is not set
 # CONFIG_BACKLIGHT_LM3630 is not set
 # CONFIG_BACKLIGHT_LM3639 is not set
 # CONFIG_BACKLIGHT_LP855X is not set
-# CONFIG_BACKLIGHT_LP8788 is not set
 # CONFIG_BACKLIGHT_PANDORA is not set
-# CONFIG_BACKLIGHT_AS3711 is not set
 
 #
 # Console display driver support
 #
 CONFIG_DUMMY_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
 CONFIG_FONT_8x16=y
-CONFIG_FONT_AUTOSELECT=y
 CONFIG_LOGO=y
 # CONFIG_LOGO_LINUX_MONO is not set
 # CONFIG_LOGO_LINUX_VGA16 is not set
@@ -4158,118 +3553,88 @@ CONFIG_SND_DEBUG=y
 # CONFIG_SND_DEBUG_VERBOSE is not set
 CONFIG_SND_PCM_XRUN_DEBUG=y
 CONFIG_SND_VMASTER=y
-CONFIG_SND_KCTL_JACK=y
 CONFIG_SND_RAWMIDI_SEQ=m
-CONFIG_SND_OPL3_LIB_SEQ=m
+# CONFIG_SND_OPL3_LIB_SEQ is not set
 # CONFIG_SND_OPL4_LIB_SEQ is not set
 # CONFIG_SND_SBAWE_SEQ is not set
-CONFIG_SND_EMU10K1_SEQ=m
+# CONFIG_SND_EMU10K1_SEQ is not set
 CONFIG_SND_MPU401_UART=m
-CONFIG_SND_OPL3_LIB=m
-CONFIG_SND_VX_LIB=m
 CONFIG_SND_AC97_CODEC=m
 CONFIG_SND_DRIVERS=y
 CONFIG_SND_DUMMY=m
 CONFIG_SND_ALOOP=m
 CONFIG_SND_VIRMIDI=m
 CONFIG_SND_MTPAV=m
+CONFIG_SND_MTS64=m
 CONFIG_SND_SERIAL_U16550=m
 CONFIG_SND_MPU401=m
+CONFIG_SND_PORTMAN2X4=m
 CONFIG_SND_AC97_POWER_SAVE=y
 CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0
-CONFIG_SND_TEA575X=m
 CONFIG_SND_PCI=y
-CONFIG_SND_AD1889=m
-CONFIG_SND_ALS300=m
-CONFIG_SND_ALI5451=m
-CONFIG_SND_ATIIXP=m
-CONFIG_SND_ATIIXP_MODEM=m
-CONFIG_SND_AU8810=m
-CONFIG_SND_AU8820=m
-CONFIG_SND_AU8830=m
-CONFIG_SND_AW2=m
-CONFIG_SND_AZT3328=m
-CONFIG_SND_BT87X=m
-# CONFIG_SND_BT87X_OVERCLOCK is not set
-CONFIG_SND_CA0106=m
-CONFIG_SND_CMIPCI=m
-CONFIG_SND_OXYGEN_LIB=m
-CONFIG_SND_OXYGEN=m
-CONFIG_SND_CS4281=m
-CONFIG_SND_CS46XX=m
-CONFIG_SND_CS46XX_NEW_DSP=y
-CONFIG_SND_CS5535AUDIO=m
-CONFIG_SND_CTXFI=m
-CONFIG_SND_DARLA20=m
-CONFIG_SND_GINA20=m
-CONFIG_SND_LAYLA20=m
-CONFIG_SND_DARLA24=m
-CONFIG_SND_GINA24=m
-CONFIG_SND_LAYLA24=m
-CONFIG_SND_MONA=m
-CONFIG_SND_MIA=m
-CONFIG_SND_ECHO3G=m
-CONFIG_SND_INDIGO=m
-CONFIG_SND_INDIGOIO=m
-CONFIG_SND_INDIGODJ=m
-CONFIG_SND_INDIGOIOX=m
-CONFIG_SND_INDIGODJX=m
-CONFIG_SND_EMU10K1=m
-CONFIG_SND_EMU10K1X=m
-CONFIG_SND_ENS1370=m
-CONFIG_SND_ENS1371=m
-CONFIG_SND_ES1938=m
-CONFIG_SND_ES1968=m
-CONFIG_SND_ES1968_INPUT=y
-CONFIG_SND_ES1968_RADIO=y
-CONFIG_SND_FM801=m
-CONFIG_SND_FM801_TEA575X_BOOL=y
-CONFIG_SND_HDA_INTEL=m
-CONFIG_SND_HDA_PREALLOC_SIZE=64
-CONFIG_SND_HDA_HWDEP=y
-CONFIG_SND_HDA_RECONFIG=y
-CONFIG_SND_HDA_INPUT_BEEP=y
-CONFIG_SND_HDA_INPUT_BEEP_MODE=1
-CONFIG_SND_HDA_INPUT_JACK=y
-# CONFIG_SND_HDA_PATCH_LOADER is not set
-CONFIG_SND_HDA_CODEC_REALTEK=y
-CONFIG_SND_HDA_CODEC_ANALOG=y
-CONFIG_SND_HDA_CODEC_SIGMATEL=y
-CONFIG_SND_HDA_CODEC_VIA=y
-CONFIG_SND_HDA_CODEC_HDMI=y
-CONFIG_SND_HDA_CODEC_CIRRUS=y
-CONFIG_SND_HDA_CODEC_CONEXANT=y
-CONFIG_SND_HDA_CODEC_CA0110=y
-CONFIG_SND_HDA_CODEC_CA0132=y
-# CONFIG_SND_HDA_CODEC_CA0132_DSP is not set
-CONFIG_SND_HDA_CODEC_CMEDIA=y
-CONFIG_SND_HDA_CODEC_SI3054=y
-CONFIG_SND_HDA_GENERIC=y
-CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
-CONFIG_SND_HDSP=m
-CONFIG_SND_HDSPM=m
-CONFIG_SND_ICE1712=m
-CONFIG_SND_ICE1724=m
-CONFIG_SND_INTEL8X0=m
-CONFIG_SND_INTEL8X0M=m
-CONFIG_SND_KORG1212=m
-CONFIG_SND_LOLA=m
-CONFIG_SND_MAESTRO3=m
-CONFIG_SND_MAESTRO3_INPUT=y
-CONFIG_SND_MIXART=m
-CONFIG_SND_NM256=m
-CONFIG_SND_PCXHR=m
-CONFIG_SND_RIPTIDE=m
-CONFIG_SND_RME32=m
-CONFIG_SND_RME96=m
-CONFIG_SND_RME9652=m
-CONFIG_SND_SONICVIBES=m
-CONFIG_SND_TRIDENT=m
-CONFIG_SND_VIA82XX=m
-CONFIG_SND_VIA82XX_MODEM=m
-CONFIG_SND_VIRTUOSO=m
-CONFIG_SND_VX222=m
-CONFIG_SND_YMFPCI=m
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+# CONFIG_SND_CS5535AUDIO is not set
+# CONFIG_SND_CTXFI is not set
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_INDIGOIOX is not set
+# CONFIG_SND_INDIGODJX is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FM801 is not set
+# CONFIG_SND_HDA_INTEL is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_LOLA is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_PCXHR is not set
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_TRIDENT is not set
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_YMFPCI is not set
 CONFIG_SND_ARM=y
 CONFIG_SND_ARMAACI=m
 CONFIG_SND_USB=y
@@ -4278,13 +3643,7 @@ CONFIG_SND_USB_UA101=m
 CONFIG_SND_USB_CAIAQ=m
 CONFIG_SND_USB_CAIAQ_INPUT=y
 CONFIG_SND_USB_6FIRE=m
-CONFIG_SND_FIREWIRE=y
-CONFIG_SND_FIREWIRE_LIB=m
-CONFIG_SND_FIREWIRE_SPEAKERS=m
-# CONFIG_SND_ISIGHT is not set
-# CONFIG_SND_SCS1X is not set
 CONFIG_SND_SOC=m
-CONFIG_SND_SOC_AC97_BUS=y
 CONFIG_SND_SOC_DMAENGINE_PCM=y
 CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
 CONFIG_SND_ATMEL_SOC=m
@@ -4292,56 +3651,13 @@ CONFIG_SND_DESIGNWARE_I2S=m
 CONFIG_SND_SOC_FSL_SSI=m
 CONFIG_SND_SOC_FSL_UTILS=m
 CONFIG_SND_IMX_SOC=m
-CONFIG_SND_SOC_IMX_SSI=m
 CONFIG_SND_SOC_IMX_PCM=m
-CONFIG_SND_SOC_IMX_PCM_FIQ=y
 CONFIG_SND_SOC_IMX_PCM_DMA=y
 CONFIG_SND_SOC_IMX_AUDMUX=m
-# CONFIG_SND_SOC_PHYCORE_AC97 is not set
-CONFIG_SND_SOC_EUKREA_TLV320=m
 CONFIG_SND_SOC_IMX_SGTL5000=m
-CONFIG_SND_OMAP_SOC=m
-CONFIG_SND_OMAP_SOC_DMIC=m
-CONFIG_SND_OMAP_SOC_MCBSP=m
-CONFIG_SND_OMAP_SOC_MCPDM=m
-CONFIG_SND_OMAP_SOC_HDMI=m
-# CONFIG_SND_OMAP_SOC_N810 is not set
-CONFIG_SND_OMAP_SOC_RX51=m
-CONFIG_SND_OMAP_SOC_AM3517EVM=m
-CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m
-CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m
-CONFIG_SND_OMAP_SOC_OMAP_HDMI=m
-CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m
-CONFIG_SND_SOC_TEGRA=m
-CONFIG_SND_SOC_TEGRA20_AC97=m
-CONFIG_SND_SOC_TEGRA20_DAS=m
-CONFIG_SND_SOC_TEGRA20_I2S=m
-CONFIG_SND_SOC_TEGRA20_SPDIF=m
-CONFIG_SND_SOC_TEGRA30_AHUB=m
-CONFIG_SND_SOC_TEGRA30_I2S=m
-# CONFIG_SND_SOC_TEGRA_WM8753 is not set
-CONFIG_SND_SOC_TEGRA_WM8903=m
-CONFIG_SND_SOC_TEGRA_WM9712=m
-CONFIG_SND_SOC_TEGRA_TRIMSLICE=m
-CONFIG_SND_SOC_TEGRA_ALC5632=m
-CONFIG_SND_SOC_UX500=m
-CONFIG_SND_SOC_UX500_PLAT_MSP_I2S=m
-CONFIG_SND_SOC_UX500_PLAT_DMA=m
-CONFIG_SND_SOC_UX500_MACH_MOP500=m
 CONFIG_SND_SOC_I2C_AND_SPI=m
 # CONFIG_SND_SOC_ALL_CODECS is not set
-CONFIG_SND_SOC_AB8500_CODEC=m
-CONFIG_SND_SOC_ALC5632=m
-CONFIG_SND_SOC_DMIC=m
-CONFIG_SND_SOC_OMAP_HDMI_CODEC=m
 CONFIG_SND_SOC_SGTL5000=m
-CONFIG_SND_SOC_TLV320AIC23=m
-CONFIG_SND_SOC_TLV320AIC3X=m
-CONFIG_SND_SOC_TWL4030=m
-CONFIG_SND_SOC_TWL6040=m
-CONFIG_SND_SOC_WM8903=m
-CONFIG_SND_SOC_WM9712=m
-CONFIG_SND_SOC_TPA6130A2=m
 CONFIG_SND_SIMPLE_CARD=m
 # CONFIG_SOUND_PRIME is not set
 CONFIG_AC97_BUS=m
@@ -4461,31 +3777,18 @@ CONFIG_USB_WUSB_CBAF=m
 # USB Host Controller Drivers
 #
 # CONFIG_USB_C67X00_HCD is not set
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_PLATFORM=m
-# CONFIG_USB_XHCI_HCD_DEBUGGING is not set
+# CONFIG_USB_XHCI_HCD is not set
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
 CONFIG_USB_EHCI_TT_NEWSCHED=y
 CONFIG_USB_EHCI_PCI=y
 CONFIG_USB_EHCI_MXC=m
-CONFIG_USB_EHCI_HCD_OMAP=y
-CONFIG_USB_EHCI_HCD_ORION=m
-CONFIG_USB_EHCI_HCD_SPEAR=y
-CONFIG_USB_EHCI_TEGRA=y
-# CONFIG_USB_CNS3XXX_EHCI is not set
 CONFIG_USB_EHCI_HCD_PLATFORM=y
 # CONFIG_USB_OXU210HP_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
 # CONFIG_USB_ISP1760_HCD is not set
 CONFIG_USB_ISP1362_HCD=m
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_OMAP3=y
-# CONFIG_USB_CNS3XXX_OHCI is not set
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_OHCI_HCD is not set
 CONFIG_USB_UHCI_HCD=y
 CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC=y
 CONFIG_USB_UHCI_PLATFORM=y
@@ -4493,7 +3796,7 @@ CONFIG_USB_UHCI_PLATFORM=y
 CONFIG_USB_SL811_HCD=m
 CONFIG_USB_SL811_HCD_ISO=y
 # CONFIG_USB_R8A66597_HCD is not set
-CONFIG_USB_IMX21_HCD=m
+CONFIG_USB_IMX21_HCD=y
 CONFIG_USB_HCD_SSB=m
 
 #
@@ -4537,12 +3840,13 @@ CONFIG_USB_DWC3=m
 CONFIG_USB_DWC3_HOST=y
 # CONFIG_USB_DWC3_DEBUG is not set
 CONFIG_USB_CHIPIDEA=m
-# CONFIG_USB_CHIPIDEA_HOST is not set
+CONFIG_USB_CHIPIDEA_HOST=y
 # CONFIG_USB_CHIPIDEA_DEBUG is not set
 
 #
 # USB port drivers
 #
+CONFIG_USB_USS720=m
 CONFIG_USB_SERIAL=m
 CONFIG_USB_SERIAL_GENERIC=y
 CONFIG_USB_SERIAL_AIRCABLE=m
@@ -4572,6 +3876,7 @@ CONFIG_USB_SERIAL_KLSI=m
 CONFIG_USB_SERIAL_MCT_U232=m
 # CONFIG_USB_SERIAL_METRO is not set
 CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7715_PARPORT=y
 CONFIG_USB_SERIAL_MOS7840=m
 CONFIG_USB_SERIAL_MOTOROLA=m
 # CONFIG_USB_SERIAL_NAVMAN is not set
@@ -4633,20 +3938,17 @@ CONFIG_USB_CXACRU=m
 CONFIG_USB_UEAGLEATM=m
 CONFIG_USB_XUSBATM=m
 CONFIG_USB_PHY=y
-CONFIG_AB8500_USB=m
 CONFIG_NOP_USB_XCEIV=m
 CONFIG_OMAP_CONTROL_USB=m
-CONFIG_OMAP_USB2=m
 CONFIG_OMAP_USB3=m
-CONFIG_SAMSUNG_USBPHY=y
-CONFIG_SAMSUNG_USB2PHY=y
-CONFIG_SAMSUNG_USB3PHY=y
+CONFIG_SAMSUNG_USBPHY=m
+CONFIG_SAMSUNG_USB2PHY=m
+CONFIG_SAMSUNG_USB3PHY=m
 CONFIG_USB_GPIO_VBUS=m
 CONFIG_USB_ISP1301=m
 CONFIG_USB_MXS_PHY=m
 CONFIG_USB_RCAR_PHY=m
 CONFIG_USB_ULPI=y
-CONFIG_USB_ULPI_VIEWPORT=y
 # CONFIG_USB_GADGET is not set
 # CONFIG_UWB is not set
 CONFIG_MMC=y
@@ -4669,33 +3971,23 @@ CONFIG_MMC_BLOCK_BOUNCE=y
 CONFIG_MMC_ARMMMCI=m
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_PCI=m
-CONFIG_MMC_RICOH_MMC=y
-CONFIG_MMC_SDHCI_PLTFM=m
-# CONFIG_MMC_SDHCI_CNS3XXX is not set
-CONFIG_MMC_SDHCI_ESDHC_IMX=m
-CONFIG_MMC_SDHCI_TEGRA=m
-CONFIG_MMC_SDHCI_SIRF=m
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
 CONFIG_MMC_SDHCI_PXAV3=m
 CONFIG_MMC_SDHCI_PXAV2=m
-# CONFIG_MMC_SDHCI_SPEAR is not set
-# CONFIG_MMC_SDHCI_BCM2835 is not set
-CONFIG_MMC_OMAP=y
-CONFIG_MMC_OMAP_HS=y
 CONFIG_MMC_MXC=m
-CONFIG_MMC_TIFM_SD=m
-CONFIG_MMC_MVSDIO=m
-CONFIG_MMC_CB710=m
-CONFIG_MMC_VIA_SDMMC=m
+# CONFIG_MMC_TIFM_SD is not set
+# CONFIG_MMC_CB710 is not set
+# CONFIG_MMC_VIA_SDMMC is not set
 CONFIG_MMC_DW=m
 # CONFIG_MMC_DW_IDMAC is not set
 CONFIG_MMC_DW_PLTFM=m
 CONFIG_MMC_DW_EXYNOS=m
-CONFIG_MMC_DW_PCI=m
+# CONFIG_MMC_DW_PCI is not set
 CONFIG_MMC_VUB300=m
 CONFIG_MMC_USHC=m
 CONFIG_MMC_WMT=m
-CONFIG_MMC_REALTEK_PCI=m
 CONFIG_MEMSTICK=m
 # CONFIG_MEMSTICK_DEBUG is not set
 
@@ -4708,18 +4000,16 @@ CONFIG_MSPRO_BLOCK=m
 #
 # MemoryStick Host Controller Drivers
 #
-CONFIG_MEMSTICK_TIFM_MS=m
-CONFIG_MEMSTICK_JMICRON_38X=m
-CONFIG_MEMSTICK_R592=m
-CONFIG_MEMSTICK_REALTEK_PCI=m
-CONFIG_LEDS_GPIO_REGISTER=y
+# CONFIG_MEMSTICK_TIFM_MS is not set
+# CONFIG_MEMSTICK_JMICRON_38X is not set
+# CONFIG_MEMSTICK_R592 is not set
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 
 #
 # LED drivers
 #
-# CONFIG_LEDS_88PM860X is not set
+CONFIG_LEDS_88PM860X=y
 CONFIG_LEDS_LM3530=m
 CONFIG_LEDS_LM3533=m
 CONFIG_LEDS_LM3642=m
@@ -4730,21 +4020,14 @@ CONFIG_LEDS_LP55XX_COMMON=m
 CONFIG_LEDS_LP5521=m
 CONFIG_LEDS_LP5523=m
 CONFIG_LEDS_LP5562=m
-# CONFIG_LEDS_LP8788 is not set
 # CONFIG_LEDS_PCA955X is not set
 CONFIG_LEDS_PCA9633=m
-# CONFIG_LEDS_WM831X_STATUS is not set
-# CONFIG_LEDS_WM8350 is not set
-# CONFIG_LEDS_DA903X is not set
-# CONFIG_LEDS_DA9052 is not set
-# CONFIG_LEDS_PWM is not set
+CONFIG_LEDS_PWM=m
 CONFIG_LEDS_REGULATOR=m
 # CONFIG_LEDS_BD2802 is not set
 CONFIG_LEDS_LT3593=m
-# CONFIG_LEDS_ADP5520 is not set
 # CONFIG_LEDS_RENESAS_TPU is not set
 CONFIG_LEDS_TCA6507=m
-# CONFIG_LEDS_MAX8997 is not set
 CONFIG_LEDS_LM355x=m
 CONFIG_LEDS_OT200=m
 CONFIG_LEDS_BLINKM=m
@@ -4755,11 +4038,11 @@ CONFIG_LEDS_BLINKM=m
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=m
 CONFIG_LEDS_TRIGGER_ONESHOT=m
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
 CONFIG_LEDS_TRIGGER_BACKLIGHT=m
-# CONFIG_LEDS_TRIGGER_CPU is not set
+CONFIG_LEDS_TRIGGER_CPU=y
 CONFIG_LEDS_TRIGGER_GPIO=m
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
 
 #
 # iptables trigger is under Netfilter config (LED target)
@@ -4783,42 +4066,30 @@ CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
 CONFIG_RTC_INTF_SYSFS=y
 CONFIG_RTC_INTF_PROC=y
 CONFIG_RTC_INTF_DEV=y
-# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
 # CONFIG_RTC_DRV_TEST is not set
 
 #
 # I2C RTC drivers
 #
-# CONFIG_RTC_DRV_88PM860X is not set
-# CONFIG_RTC_DRV_88PM80X is not set
+CONFIG_RTC_DRV_88PM860X=m
+CONFIG_RTC_DRV_88PM80X=m
 CONFIG_RTC_DRV_DS1307=m
 CONFIG_RTC_DRV_DS1374=m
 CONFIG_RTC_DRV_DS1672=m
 CONFIG_RTC_DRV_DS3232=m
-# CONFIG_RTC_DRV_LP8788 is not set
 CONFIG_RTC_DRV_MAX6900=m
-# CONFIG_RTC_DRV_MAX8907 is not set
-# CONFIG_RTC_DRV_MAX8925 is not set
-# CONFIG_RTC_DRV_MAX8998 is not set
-# CONFIG_RTC_DRV_MAX8997 is not set
-# CONFIG_RTC_DRV_MAX77686 is not set
 CONFIG_RTC_DRV_RS5C372=m
 CONFIG_RTC_DRV_ISL1208=m
 CONFIG_RTC_DRV_ISL12022=m
 CONFIG_RTC_DRV_X1205=m
-# CONFIG_RTC_DRV_PALMAS is not set
 CONFIG_RTC_DRV_PCF8523=m
 CONFIG_RTC_DRV_PCF8563=m
 CONFIG_RTC_DRV_PCF8583=m
 CONFIG_RTC_DRV_M41T80=m
 CONFIG_RTC_DRV_M41T80_WDT=y
 CONFIG_RTC_DRV_BQ32K=m
-# CONFIG_RTC_DRV_TWL92330 is not set
-# CONFIG_RTC_DRV_TWL4030 is not set
-# CONFIG_RTC_DRV_TPS6586X is not set
-# CONFIG_RTC_DRV_TPS65910 is not set
-# CONFIG_RTC_DRV_TPS80031 is not set
-# CONFIG_RTC_DRV_RC5T583 is not set
+CONFIG_RTC_DRV_TWL4030=m
 # CONFIG_RTC_DRV_S35390A is not set
 CONFIG_RTC_DRV_FM3130=m
 CONFIG_RTC_DRV_RX8581=m
@@ -4838,8 +4109,6 @@ CONFIG_RTC_DRV_DS1286=m
 CONFIG_RTC_DRV_DS1511=m
 CONFIG_RTC_DRV_DS1553=m
 CONFIG_RTC_DRV_DS1742=m
-# CONFIG_RTC_DRV_DA9052 is not set
-# CONFIG_RTC_DRV_DA9055 is not set
 CONFIG_RTC_DRV_STK17TA8=m
 # CONFIG_RTC_DRV_M48T86 is not set
 CONFIG_RTC_DRV_M48T35=m
@@ -4849,22 +4118,14 @@ CONFIG_RTC_DRV_BQ4802=m
 CONFIG_RTC_DRV_RP5C01=m
 CONFIG_RTC_DRV_V3020=m
 CONFIG_RTC_DRV_DS2404=m
-# CONFIG_RTC_DRV_WM831X is not set
-# CONFIG_RTC_DRV_WM8350 is not set
-CONFIG_RTC_DRV_SPEAR=y
-CONFIG_RTC_DRV_AB3100=y
-# CONFIG_RTC_DRV_AB8500 is not set
 
 #
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_IMXDI=m
-CONFIG_RTC_DRV_OMAP=m
 CONFIG_RTC_DRV_PL030=m
 CONFIG_RTC_DRV_PL031=m
 CONFIG_RTC_DRV_VT8500=m
-CONFIG_RTC_DRV_MV=m
-CONFIG_RTC_DRV_TEGRA=m
 CONFIG_RTC_DRV_MXC=m
 CONFIG_RTC_DRV_SNVS=m
 
@@ -4878,21 +4139,15 @@ CONFIG_DMADEVICES=y
 #
 # DMA Devices
 #
-CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
-# CONFIG_AMBA_PL08X is not set
+CONFIG_AMBA_PL08X=y
 # CONFIG_DW_DMAC is not set
-CONFIG_MV_XOR=y
 CONFIG_MX3_IPU=y
 CONFIG_MX3_IPU_IRQS=4
-CONFIG_TEGRA20_APB_DMA=y
-# CONFIG_STE_DMA40 is not set
 CONFIG_TIMB_DMA=m
-# CONFIG_SIRF_DMA is not set
 CONFIG_PL330_DMA=y
-CONFIG_IMX_SDMA=m
-CONFIG_IMX_DMA=m
-# CONFIG_MXS_DMA is not set
-CONFIG_DMA_OMAP=y
+CONFIG_IMX_SDMA=y
+CONFIG_IMX_DMA=y
+CONFIG_MXS_DMA=y
 CONFIG_DMA_ENGINE=y
 CONFIG_DMA_VIRTUAL_CHANNELS=y
 CONFIG_DMA_OF=y
@@ -4909,11 +4164,11 @@ CONFIG_UIO=m
 # CONFIG_UIO_PDRV is not set
 # CONFIG_UIO_PDRV_GENIRQ is not set
 # CONFIG_UIO_DMEM_GENIRQ is not set
-CONFIG_UIO_AEC=m
-CONFIG_UIO_SERCOS3=m
-CONFIG_UIO_PCI_GENERIC=m
+# CONFIG_UIO_AEC is not set
+# CONFIG_UIO_SERCOS3 is not set
+# CONFIG_UIO_PCI_GENERIC is not set
 # CONFIG_UIO_NETX is not set
-# CONFIG_VIRT_DRIVERS is not set
+CONFIG_VIRT_DRIVERS=y
 
 #
 # Virtio drivers
@@ -4925,16 +4180,17 @@ CONFIG_UIO_PCI_GENERIC=m
 # Microsoft Hyper-V guest support
 #
 CONFIG_STAGING=y
-CONFIG_ET131X=m
+# CONFIG_ET131X is not set
 CONFIG_USBIP_CORE=m
 CONFIG_USBIP_VHCI_HCD=m
 CONFIG_USBIP_HOST=m
 # CONFIG_USBIP_DEBUG is not set
 # CONFIG_W35UND is not set
 # CONFIG_PRISM2_USB is not set
-CONFIG_ECHO=m
+# CONFIG_ECHO is not set
 # CONFIG_COMEDI is not set
 # CONFIG_ASUS_OLED is not set
+# CONFIG_PANEL is not set
 # CONFIG_R8187SE is not set
 # CONFIG_RTL8192U is not set
 # CONFIG_RTLLIB is not set
@@ -4962,7 +4218,6 @@ CONFIG_ECHO=m
 # CONFIG_AD7291 is not set
 # CONFIG_AD7606 is not set
 # CONFIG_AD799X is not set
-# CONFIG_SPEAR_ADC is not set
 
 #
 # Analog digital bi-direction converters
@@ -5032,7 +4287,6 @@ CONFIG_ECHO=m
 # CONFIG_SPEAKUP is not set
 # CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set
 # CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
-# CONFIG_MFD_NVEC is not set
 # CONFIG_STAGING_MEDIA is not set
 
 #
@@ -5043,12 +4297,14 @@ CONFIG_ECHO=m
 # CONFIG_WIMAX_GDM72XX is not set
 # CONFIG_CSR_WIFI is not set
 CONFIG_NET_VENDOR_SILICOM=y
-CONFIG_SBYPASS=m
-CONFIG_BPCTL=m
-# CONFIG_CED1401 is not set
-# CONFIG_DRM_IMX is not set
+# CONFIG_SBYPASS is not set
+# CONFIG_BPCTL is not set
+CONFIG_CED1401=m
+CONFIG_DRM_IMX=m
+# CONFIG_DRM_IMX_FB_HELPER is not set
+CONFIG_DRM_IMX_PARALLEL_DISPLAY=m
+# CONFIG_DRM_IMX_TVE is not set
 # CONFIG_DGRP is not set
-# CONFIG_FIREWIRE_SERIAL is not set
 CONFIG_CLKDEV_LOOKUP=y
 CONFIG_HAVE_CLK_PREPARE=y
 CONFIG_COMMON_CLK=y
@@ -5057,37 +4313,22 @@ CONFIG_COMMON_CLK=y
 # Common Clock Framework
 #
 # CONFIG_COMMON_CLK_DEBUG is not set
-# CONFIG_COMMON_CLK_WM831X is not set
 CONFIG_COMMON_CLK_VERSATILE=y
-# CONFIG_COMMON_CLK_MAX77686 is not set
 CONFIG_COMMON_CLK_SI5351=m
-CONFIG_CLK_TWL6040=m
 CONFIG_COMMON_CLK_AXI_CLKGEN=m
-CONFIG_MVEBU_CLK_CORE=y
-CONFIG_MVEBU_CLK_CPU=y
-CONFIG_MVEBU_CLK_GATING=y
-CONFIG_HWSPINLOCK=m
 
 #
 # Hardware Spinlock drivers
 #
-CONFIG_HWSPINLOCK_OMAP=m
-# CONFIG_HSEM_U8500 is not set
 CONFIG_CLKSRC_OF=y
 CONFIG_CLKSRC_MMIO=y
-CONFIG_DW_APB_TIMER=y
-CONFIG_DW_APB_TIMER_OF=y
-CONFIG_ARMADA_370_XP_TIMER=y
-CONFIG_SUN4I_TIMER=y
 CONFIG_VT8500_TIMER=y
 CONFIG_CADENCE_TTC_TIMER=y
-CONFIG_CLKSRC_NOMADIK_MTU=y
-CONFIG_CLKSRC_DBX500_PRCMU=y
-CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK=y
 CONFIG_ARM_ARCH_TIMER=y
 CONFIG_MAILBOX=y
 CONFIG_PL320_MBOX=y
-# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_OF_IOMMU=y
 
 #
 # Remoteproc drivers
@@ -5100,9 +4341,6 @@ CONFIG_PL320_MBOX=y
 # CONFIG_PM_DEVFREQ is not set
 # CONFIG_EXTCON is not set
 CONFIG_MEMORY=y
-CONFIG_TI_EMIF=m
-CONFIG_TEGRA20_MC=y
-CONFIG_TEGRA30_MC=y
 CONFIG_IIO=m
 CONFIG_IIO_BUFFER=y
 CONFIG_IIO_BUFFER_CB=y
@@ -5120,7 +4358,6 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
 # Analog to digital converters
 #
 # CONFIG_EXYNOS_ADC is not set
-# CONFIG_LP8788_ADC is not set
 # CONFIG_MAX1363 is not set
 # CONFIG_TI_ADC081C is not set
 # CONFIG_VIPERBOARD_ADC is not set
@@ -5186,19 +4423,12 @@ CONFIG_HID_SENSOR_IIO_TRIGGER=m
 # CONFIG_IIO_ST_MAGN_3AXIS is not set
 # CONFIG_VME_BUS is not set
 CONFIG_PWM=y
-# CONFIG_PWM_AB8500 is not set
-# CONFIG_PWM_IMX is not set
-# CONFIG_PWM_SPEAR is not set
-# CONFIG_PWM_TEGRA is not set
-# CONFIG_PWM_TIECAP is not set
-# CONFIG_PWM_TIEHRPWM is not set
-# CONFIG_PWM_TWL is not set
-# CONFIG_PWM_TWL_LED is not set
-# CONFIG_PWM_VT8500 is not set
+CONFIG_PWM_IMX=m
+CONFIG_PWM_TWL=m
+CONFIG_PWM_TWL_LED=m
+CONFIG_PWM_VT8500=m
 CONFIG_IRQCHIP=y
 CONFIG_ARM_GIC=y
-CONFIG_ARM_VIC=y
-CONFIG_ARM_VIC_NR=2
 # CONFIG_IPACK_BUS is not set
 CONFIG_ARCH_HAS_RESET_CONTROLLER=y
 # CONFIG_RESET_CONTROLLER is not set
@@ -5311,6 +4541,7 @@ CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
 # CONFIG_JFFS2_FS is not set
+# CONFIG_UBIFS_FS is not set
 # CONFIG_LOGFS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_SQUASHFS is not set
@@ -5457,7 +4688,6 @@ CONFIG_SCHED_DEBUG=y
 CONFIG_SCHEDSTATS=y
 CONFIG_TIMER_STATS=y
 # CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SLUB_DEBUG_ON is not set
 # CONFIG_SLUB_STATS is not set
 CONFIG_HAVE_DEBUG_KMEMLEAK=y
 # CONFIG_DEBUG_KMEMLEAK is not set
@@ -5489,7 +4719,7 @@ CONFIG_FRAME_POINTER=y
 #
 # CONFIG_SPARSE_RCU_POINTER is not set
 # CONFIG_RCU_TORTURE_TEST is not set
-CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
 # CONFIG_RCU_CPU_STALL_INFO is not set
 # CONFIG_RCU_TRACE is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
@@ -5512,6 +4742,7 @@ CONFIG_TRACE_CLOCK=y
 CONFIG_RING_BUFFER=y
 CONFIG_EVENT_TRACING=y
 CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_RING_BUFFER_ALLOW_SWAP=y
 CONFIG_TRACING=y
 CONFIG_GENERIC_TRACER=y
 CONFIG_TRACING_SUPPORT=y
@@ -5552,26 +4783,11 @@ CONFIG_ARM_UNWIND=y
 CONFIG_OLD_MCOUNT=y
 # CONFIG_DEBUG_USER is not set
 CONFIG_DEBUG_LL=y
-# CONFIG_DEBUG_BCM2835 is not set
-# CONFIG_DEBUG_CNS3XXX is not set
-CONFIG_DEBUG_ZYNQ_UART0=y
+# CONFIG_DEBUG_ZYNQ_UART0 is not set
 # CONFIG_DEBUG_ZYNQ_UART1 is not set
-# CONFIG_DEBUG_HIGHBANK_UART is not set
-# CONFIG_DEBUG_IMX31_UART is not set
-# CONFIG_DEBUG_IMX35_UART is not set
 # CONFIG_DEBUG_IMX51_UART is not set
 # CONFIG_DEBUG_IMX53_UART is not set
-# CONFIG_DEBUG_IMX6Q_UART is not set
-# CONFIG_DEBUG_MVEBU_UART is not set
-# CONFIG_DEBUG_OMAP2PLUS_UART is not set
-# CONFIG_DEBUG_PICOXCELL_UART is not set
-# CONFIG_DEBUG_SOCFPGA_UART is not set
-# CONFIG_DEBUG_SUNXI_UART0 is not set
-# CONFIG_DEBUG_SUNXI_UART1 is not set
-# CONFIG_DEBUG_TEGRA_UART is not set
-# CONFIG_DEBUG_SIRFPRIMA2_UART1 is not set
-# CONFIG_DEBUG_SIRFMARCO_UART1 is not set
-# CONFIG_DEBUG_UX500_UART is not set
+CONFIG_DEBUG_IMX6Q_UART=y
 # CONFIG_DEBUG_VEXPRESS_UART0_DETECT is not set
 # CONFIG_DEBUG_VEXPRESS_UART0_CA9 is not set
 # CONFIG_DEBUG_VEXPRESS_UART0_RS1 is not set
@@ -5579,7 +4795,7 @@ CONFIG_DEBUG_ZYNQ_UART0=y
 # CONFIG_DEBUG_ICEDCC is not set
 # CONFIG_DEBUG_SEMIHOSTING is not set
 CONFIG_DEBUG_IMX_UART_PORT=1
-CONFIG_DEBUG_LL_INCLUDE="debug/zynq.S"
+CONFIG_DEBUG_LL_INCLUDE="debug/imx.S"
 CONFIG_DEBUG_UNCOMPRESS=y
 CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
 CONFIG_EARLY_PRINTK=y
@@ -5708,7 +4924,7 @@ CONFIG_GRKERNSEC_SIGNAL=y
 CONFIG_GRKERNSEC_FORKFAIL=y
 # CONFIG_GRKERNSEC_TIME is not set
 CONFIG_GRKERNSEC_PROC_IPADDR=y
-CONFIG_GRKERNSEC_RWXMAP_LOG=y
+# CONFIG_GRKERNSEC_RWXMAP_LOG is not set
 
 #
 # Executable Protections
@@ -5716,7 +4932,7 @@ CONFIG_GRKERNSEC_RWXMAP_LOG=y
 CONFIG_GRKERNSEC_DMESG=y
 CONFIG_GRKERNSEC_HARDEN_PTRACE=y
 CONFIG_GRKERNSEC_PTRACE_READEXEC=y
-# CONFIG_GRKERNSEC_SETXID is not set
+CONFIG_GRKERNSEC_SETXID=y
 # CONFIG_GRKERNSEC_TPE is not set
 
 #
@@ -5834,8 +5050,8 @@ CONFIG_CRYPTO_RMD128=m
 CONFIG_CRYPTO_RMD160=m
 CONFIG_CRYPTO_RMD256=m
 CONFIG_CRYPTO_RMD320=m
-CONFIG_CRYPTO_SHA1=m
-CONFIG_CRYPTO_SHA1_ARM=m
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA1_ARM=y
 CONFIG_CRYPTO_SHA256=y
 CONFIG_CRYPTO_SHA512=m
 CONFIG_CRYPTO_TGR192=m
@@ -5879,16 +5095,7 @@ CONFIG_CRYPTO_USER_API=y
 CONFIG_CRYPTO_USER_API_HASH=y
 CONFIG_CRYPTO_USER_API_SKCIPHER=y
 CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_DEV_MV_CESA=m
-CONFIG_CRYPTO_DEV_HIFN_795X=m
-CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y
-CONFIG_CRYPTO_DEV_OMAP_SHAM=m
-CONFIG_CRYPTO_DEV_OMAP_AES=m
-# CONFIG_CRYPTO_DEV_PICOXCELL is not set
-CONFIG_CRYPTO_DEV_TEGRA_AES=m
-CONFIG_CRYPTO_DEV_UX500=m
-# CONFIG_CRYPTO_DEV_UX500_CRYP is not set
-# CONFIG_CRYPTO_DEV_UX500_HASH is not set
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
 CONFIG_ASYMMETRIC_KEY_TYPE=m
 CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=m
 CONFIG_PUBLIC_KEY_ALGO_RSA=m
@@ -5945,11 +5152,9 @@ CONFIG_TEXTSEARCH_BM=m
 CONFIG_TEXTSEARCH_FSM=m
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_DMA=y
-CONFIG_CHECK_SIGNATURE=y
 CONFIG_CPU_RMAP=y
 CONFIG_DQL=y
 CONFIG_NLATTR=y
-CONFIG_GENERIC_ATOMIC64=y
 CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
 CONFIG_AVERAGE=y
 CONFIG_CLZ_TAB=y

diff --git a/config/rootfiles/core/fifteen/filelists/files b/config/rootfiles/core/fifteen/filelists/files
index 6a299d4f477ffe17d2d26902bc71554ac5b11372..ac4f298b86d6dfd9334d43bd0ff4b9f6b0b2be45 100644 (file)
--- a/config/rootfiles/core/fifteen/filelists/files
+++ b/config/rootfiles/core/fifteen/filelists/files
@@ -1,12 +1,14 @@
 etc/system-release
 etc/issue
 etc/rc.d/init.d/network
+srv/web/ipfire/cgi-bin/credits.cgi
 srv/web/ipfire/cgi-bin/index.cgi
 srv/web/ipfire/cgi-bin/netinternal.cgi
 srv/web/ipfire/cgi-bin/ovpnmain.cgi
 srv/web/ipfire/cgi-bin/proxy.cgi
 srv/web/ipfire/cgi-bin/upnp.cgi
 srv/web/ipfire/cgi-bin/speed.cgi
+srv/web/ipfire/cgi-bin/url-filter.cgi
 srv/web/ipfire/cgi-bin/vpnmain.cgi
 srv/web/ipfire/html/themes/ipfire/include/functions.pl
 srv/web/ipfire/html/themes/maniac/include/functions.pl

diff --git a/config/rootfiles/core/fifteen/update.sh b/config/rootfiles/core/fifteen/update.sh
index 3ea5ec596b32e3c251c1512367c22fecf3b26002..c2c58f663e2bd96c56b69a97156f777c05032368 100644 (file)
--- a/config/rootfiles/core/fifteen/update.sh
+++ b/config/rootfiles/core/fifteen/update.sh
@@ -52,11 +52,16 @@ rm -f /etc/rc.d/init.d/networking/red.up/26-xtaccess
 # Remove old CGI files
 rm -f /srv/web/ipfire/cgi-bin/{dmzholes,outgoingfw,portfw,xtaccess}.cgi
 
+# Generate chains for new firewall
+/sbin/iptables -N INPUTFW
+/sbin/iptables -N FORWARDFW
+/sbin/iptables -N OUTGOINGFW
+
 # Convert firewall configuration
-/usr/bin/convert-xtaccess
-/usr/bin/convert-outgoingfw
-/usr/bin/convert-portfw
-/usr/bin/convert-dmz
+/usr/sbin/convert-xtaccess
+/usr/sbin/convert-outgoingfw
+/usr/sbin/convert-portfw
+/usr/sbin/convert-dmz
 
 # Remove old firewall configuration files
 rm -rf /var/ipfire/{dmzholes,portfw,outgoing,xtaccess}

diff --git a/html/cgi-bin/credits.cgi b/html/cgi-bin/credits.cgi
index d61019ef1ca9c8d851b993300e434321860d27f9..2d113c4a99892e15675646f064d4f9ca44fdde3a 100644 (file)
--- a/html/cgi-bin/credits.cgi
+++ b/html/cgi-bin/credits.cgi
@@ -68,6 +68,8 @@ Christian Schmidt
 (<a href='mailto:christian.schmidt\@ipfire.org'>christian.schmidt\@ipfire.org</a>) - Vice Project Leader <br />
 Stefan Schantl
 (<a href='mailto:stefan.schantl\@ipfire.org'>stefan.schantl\@ipfire.org</a>)<br />
+Alexander Marx
+(<a href='mailto:alexander.marx\@ipfire.org'>alexander.marx\@ipfire.org</a>)<br />
 Heiner Schmeling
 (<a href='mailto:heiner.schmeling\@ipfire.org'>heiner.schmeling\@ipfire.org</a>)<br />
 Ronald Wiesinger

diff --git a/lfs/linux b/lfs/linux
index 080e8017bfbc6eb0f7ded33f3c903d96d440dca7..a30c46b9c1354caa2c8bdf3926fce6f7db518abd 100644 (file)
--- a/lfs/linux
+++ b/lfs/linux
@@ -165,6 +165,35 @@ ifeq "$(KCFG)" "-multi"
 #      cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/linux-3.2-0002-panda-i2c.patch
 #      cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/linux-3.2-panda-reboot.patch
        cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/linux-3.10-smsc95xx-add_mac_addr_param.patch
+
+       # Patchset for Wandboard.
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/kernel/wandboard/dts/0001-imx6qdl-wandboard-dts-backport.patch
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/kernel/wandboard/dts/0002-ARM-dts-imx6qdl-wandboard-add-gpio-lines-to-wandboar.patch
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/kernel/wandboard/dts/0003-ARM-dts-imx6qdl-wandboard-Add-support-for-i2c1.patch
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/kernel/wandboard/dts/0004-ARM-dts-wandboard-add-binding-for-wand-rfkill-driver.patch
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/kernel/wandboard/dts/0005-ARM-dts-imx6qdl-add-pcie-device-node.patch
+
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/kernel/wandboard/imx/0001-i2c-imx-retry-on-NAK.patch
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/kernel/wandboard/imx/0002-i.MX6-Wandboard-add-CKO1-clock-output.patch
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/kernel/wandboard/imx/0003-thermal-add-imx-thermal-driver-support.patch
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/kernel/wandboard/imx/0004-ARM-i.MX6-Wandboard-add-wifi-bt-rfkill-driver.patch
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/kernel/wandboard/imx/0005-Add-IMX6Q-AHCI-support.patch
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/kernel/wandboard/imx/0006-imx-Add-IMX53-AHCI-support.patch
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/kernel/wandboard/imx/0007-imx6-enable-sata-clk-if-SATA_AHCI_PLATFORM.patch
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/kernel/wandboard/imx/0008-ARM-imx6q-update-the-sata-bits-definitions-of-gpr13.patch
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/kernel/wandboard/imx/0009-ahci_imx-add-ahci-sata-support-on-imx-platforms.patch
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/kernel/wandboard/imx/0010-ahci_imx-depend-on-CONFIG_MFD_SYSCON.patch
+       cd $(DIR_APP) && patch -Np0 < $(DIR_SRC)/src/patches/kernel/wandboard/imx/0011-add-pcie-designware.patch
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/kernel/wandboard/imx/0012-pcie-backport-fixes.patch
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/kernel/wandboard/imx/0013-of-pci-Provide-support-for-parsing-PCI-DT-ranges-pro.patch
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/kernel/wandboard/imx/0014-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/kernel/wandboard/imx/0015-PCI-imx6-Add-support-for-i.MX6-PCIe-controller.patch
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/kernel/wandboard/imx/0016-imx6-pci-tweaks.patch
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/kernel/wandboard/imx/0017-ARM-imx-Add-LVDS-general-purpose-clocks-to-i.MX6Q.patch
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/kernel/wandboard/imx/0018-ARM-imx6q-clock-and-Kconfig-update-for-PCIe-support.patch
+
+       # Patchset for Compulab Utilite.
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/kernel/utilite/linux-3.10-compulab-utilite-support.patch
 endif
 
 ifeq "$(KCFG)" "-rpi"

diff --git a/src/initscripts/init.d/firewall b/src/initscripts/init.d/firewall
index f23f7f4eb485d78d594ef16ba33aecd39d848c48..be0c8b0227a5f22396c7c1522deee0c7d1da014c 100644 (file)
--- a/src/initscripts/init.d/firewall
+++ b/src/initscripts/init.d/firewall
@@ -99,7 +99,7 @@ iptables_init() {
 
        # Block OpenVPN transfer networks
        /sbin/iptables -N OVPNBLOCK
-       for i in INPUT FORWARD OUTPUT; do
+       for i in INPUT FORWARD; do
                /sbin/iptables -A ${i} -j OVPNBLOCK
        done
 

diff --git a/src/patches/kernel/utilite/linux-3.10-compulab-utilite-support.patch b/src/patches/kernel/utilite/linux-3.10-compulab-utilite-support.patch
new file mode 100644 (file)
index 0000000..3d7f676
--- /dev/null
+++ b/src/patches/kernel/utilite/linux-3.10-compulab-utilite-support.patch
@@ -0,0 +1,96 @@
+Add initial support for cm-fx6 module.
+
+cm-fx6 is a module based on mx6q SoC with the following features:
+- Up to 4GB of DDR3
+- 1 LCD/DVI output port
+- 1 HDMI output port
+- 2 LVDS LCD ports
+- Gigabit Ethernet
+- Analog Audio
+- CAN
+- SATA
+- NAND
+- PCIE
+
+This patch allows to boot up the module, configures the serial console,
+the Ethernet adapter and the heartbeat led.
+
+cm-fx6 is embedded inside the Utilite computer.
+
+Signed-off-by: Valentin Raevsky <valentin@compulab.co.il>
+Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
+---
+
+Shawn, can this still be applied for 3.13 ?
+
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index f0895c5..7521a34 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -117,6 +117,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
+       imx6dl-sabresd.dtb \
+       imx6dl-wandboard.dtb \
+       imx6q-arm2.dtb \
++      imx6q-cm-fx6.dtb \
+       imx6q-sabreauto.dtb \
+       imx6q-sabrelite.dtb \
+       imx6q-sabresd.dtb \
+diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts
+new file mode 100644
+index 0000000..2419751
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts
+@@ -0,0 +1,53 @@
++/*
++ * Copyright 2013 CompuLab Ltd.
++ *
++ * Author: Valentin Raevsky <valentin@compulab.co.il>
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/dts-v1/;
++#include "imx6q.dtsi"
++
++/ {
++      model = "CompuLab CM-FX6";
++      compatible = "compulab,cm-fx6", "fsl,imx6q";
++
++      memory {
++              reg = <0x10000000 0x80000000>;
++      };
++
++      leds {
++              compatible = "gpio-leds";
++
++              heartbeat-led {
++                      label = "Heartbeat";
++                      gpios = <&gpio2 31 0>;
++                      linux,default-trigger = "heartbeat";
++              };
++      };
++};
++
++&fec {
++      pinctrl-names = "default";
++      pinctrl-0 = <&pinctrl_enet_1>;
++      phy-mode = "rgmii";
++      status = "okay";
++};
++
++&gpmi {
++      pinctrl-names = "default";
++      pinctrl-0 = <&pinctrl_gpmi_nand_1>;
++      status = "okay";
++};
++
++&uart4 {
++      pinctrl-names = "default";
++      pinctrl-0 = <&pinctrl_uart4_1>;
++      status = "okay";
++};

diff --git a/src/patches/kernel/wandboard/dts/0001-imx6qdl-wandboard-dts-backport.patch b/src/patches/kernel/wandboard/dts/0001-imx6qdl-wandboard-dts-backport.patch
new file mode 100644 (file)
index 0000000..e1c6bea
--- /dev/null
+++ b/src/patches/kernel/wandboard/dts/0001-imx6qdl-wandboard-dts-backport.patch
@@ -0,0 +1,6354 @@
+commit a97d4c27dd2eef64af9e5d778d05a8915cba6822
+Author: Stefan Schantl <stefan.schantl@ipfire.org>
+Date:   Mon Nov 18 21:34:31 2013 +0100
+
+    Backport dts for imx6qdl.
+
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index f0895c5..a3d2869 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -120,7 +120,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
+       imx6q-sabreauto.dtb \
+       imx6q-sabrelite.dtb \
+       imx6q-sabresd.dtb \
+-      imx6q-sbc6x.dtb
++      imx6q-sbc6x.dtb \
++      imx6q-wandboard.dtb
+ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
+       imx23-olinuxino.dtb \
+       imx23-stmp378x_devb.dtb \
+diff --git a/arch/arm/boot/dts/imx6dl-pinfunc.h b/arch/arm/boot/dts/imx6dl-pinfunc.h
+index 9aab950..b81a7a4 100644
+--- a/arch/arm/boot/dts/imx6dl-pinfunc.h
++++ b/arch/arm/boot/dts/imx6dl-pinfunc.h
+@@ -14,1072 +14,1076 @@
+  * The pin function ID is a tuple of
+  * <mux_reg conf_reg input_reg mux_mode input_val>
+  */
+-#define MX6DL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10     0x04c 0x360 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT10__AUD3_RXC             0x04c 0x360 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT10__ECSPI2_MISO          0x04c 0x360 0x7f8 0x2 0x0
+-#define MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA        0x04c 0x360 0x000 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT10__UART1_RX_DATA        0x04c 0x360 0x8fc 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT10__GPIO5_IO28           0x04c 0x360 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT10__ARM_TRACE07          0x04c 0x360 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11     0x050 0x364 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT11__AUD3_RXFS            0x050 0x364 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT11__ECSPI2_SS0           0x050 0x364 0x800 0x2 0x0
+-#define MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA        0x050 0x364 0x8fc 0x3 0x1
+-#define MX6DL_PAD_CSI0_DAT11__UART1_TX_DATA        0x050 0x364 0x000 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT11__GPIO5_IO29           0x050 0x364 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT11__ARM_TRACE08          0x050 0x364 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12     0x054 0x368 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT12__EIM_DATA08           0x054 0x368 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT12__UART4_TX_DATA        0x054 0x368 0x000 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT12__UART4_RX_DATA        0x054 0x368 0x914 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT12__GPIO5_IO30           0x054 0x368 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT12__ARM_TRACE09          0x054 0x368 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13     0x058 0x36c 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT13__EIM_DATA09           0x058 0x36c 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT13__UART4_RX_DATA        0x058 0x36c 0x914 0x3 0x1
+-#define MX6DL_PAD_CSI0_DAT13__UART4_TX_DATA        0x058 0x36c 0x000 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT13__GPIO5_IO31           0x058 0x36c 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT13__ARM_TRACE10          0x058 0x36c 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14     0x05c 0x370 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT14__EIM_DATA10           0x05c 0x370 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT14__UART5_TX_DATA        0x05c 0x370 0x000 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT14__UART5_RX_DATA        0x05c 0x370 0x91c 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT14__GPIO6_IO00           0x05c 0x370 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT14__ARM_TRACE11          0x05c 0x370 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15     0x060 0x374 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT15__EIM_DATA11           0x060 0x374 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT15__UART5_RX_DATA        0x060 0x374 0x91c 0x3 0x1
+-#define MX6DL_PAD_CSI0_DAT15__UART5_TX_DATA        0x060 0x374 0x000 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT15__GPIO6_IO01           0x060 0x374 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT15__ARM_TRACE12          0x060 0x374 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16     0x064 0x378 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT16__EIM_DATA12           0x064 0x378 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT16__UART4_RTS_B          0x064 0x378 0x910 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT16__UART4_CTS_B          0x064 0x378 0x000 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT16__GPIO6_IO02           0x064 0x378 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT16__ARM_TRACE13          0x064 0x378 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17     0x068 0x37c 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT17__EIM_DATA13           0x068 0x37c 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT17__UART4_CTS_B          0x068 0x37c 0x000 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT17__UART4_RTS_B          0x068 0x37c 0x910 0x3 0x1
+-#define MX6DL_PAD_CSI0_DAT17__GPIO6_IO03           0x068 0x37c 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT17__ARM_TRACE14          0x068 0x37c 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18     0x06c 0x380 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT18__EIM_DATA14           0x06c 0x380 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT18__UART5_RTS_B          0x06c 0x380 0x918 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT18__UART5_CTS_B          0x06c 0x380 0x000 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT18__GPIO6_IO04           0x06c 0x380 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT18__ARM_TRACE15          0x06c 0x380 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19     0x070 0x384 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT19__EIM_DATA15           0x070 0x384 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT19__UART5_CTS_B          0x070 0x384 0x000 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT19__UART5_RTS_B          0x070 0x384 0x918 0x3 0x1
+-#define MX6DL_PAD_CSI0_DAT19__GPIO6_IO05           0x070 0x384 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04      0x074 0x388 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT4__EIM_DATA02            0x074 0x388 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT4__ECSPI1_SCLK           0x074 0x388 0x7d8 0x2 0x0
+-#define MX6DL_PAD_CSI0_DAT4__KEY_COL5              0x074 0x388 0x8c0 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT4__AUD3_TXC              0x074 0x388 0x000 0x4 0x0
+-#define MX6DL_PAD_CSI0_DAT4__GPIO5_IO22            0x074 0x388 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT4__ARM_TRACE01           0x074 0x388 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05      0x078 0x38c 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT5__EIM_DATA03            0x078 0x38c 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT5__ECSPI1_MOSI           0x078 0x38c 0x7e0 0x2 0x0
+-#define MX6DL_PAD_CSI0_DAT5__KEY_ROW5              0x078 0x38c 0x8cc 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT5__AUD3_TXD              0x078 0x38c 0x000 0x4 0x0
+-#define MX6DL_PAD_CSI0_DAT5__GPIO5_IO23            0x078 0x38c 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT5__ARM_TRACE02           0x078 0x38c 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06      0x07c 0x390 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT6__EIM_DATA04            0x07c 0x390 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT6__ECSPI1_MISO           0x07c 0x390 0x7dc 0x2 0x0
+-#define MX6DL_PAD_CSI0_DAT6__KEY_COL6              0x07c 0x390 0x8c4 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT6__AUD3_TXFS             0x07c 0x390 0x000 0x4 0x0
+-#define MX6DL_PAD_CSI0_DAT6__GPIO5_IO24            0x07c 0x390 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT6__ARM_TRACE03           0x07c 0x390 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07      0x080 0x394 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT7__EIM_DATA05            0x080 0x394 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT7__ECSPI1_SS0            0x080 0x394 0x7e4 0x2 0x0
+-#define MX6DL_PAD_CSI0_DAT7__KEY_ROW6              0x080 0x394 0x8d0 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT7__AUD3_RXD              0x080 0x394 0x000 0x4 0x0
+-#define MX6DL_PAD_CSI0_DAT7__GPIO5_IO25            0x080 0x394 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT7__ARM_TRACE04           0x080 0x394 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08      0x084 0x398 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT8__EIM_DATA06            0x084 0x398 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT8__ECSPI2_SCLK           0x084 0x398 0x7f4 0x2 0x0
+-#define MX6DL_PAD_CSI0_DAT8__KEY_COL7              0x084 0x398 0x8c8 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT8__I2C1_SDA              0x084 0x398 0x86c 0x4 0x0
+-#define MX6DL_PAD_CSI0_DAT8__GPIO5_IO26            0x084 0x398 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT8__ARM_TRACE05           0x084 0x398 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09      0x088 0x39c 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT9__EIM_DATA07            0x088 0x39c 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT9__ECSPI2_MOSI           0x088 0x39c 0x7fc 0x2 0x0
+-#define MX6DL_PAD_CSI0_DAT9__KEY_ROW7              0x088 0x39c 0x8d4 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT9__I2C1_SCL              0x088 0x39c 0x868 0x4 0x0
+-#define MX6DL_PAD_CSI0_DAT9__GPIO5_IO27            0x088 0x39c 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT9__ARM_TRACE06           0x088 0x39c 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN  0x08c 0x3a0 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DATA_EN__EIM_DATA00         0x08c 0x3a0 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DATA_EN__GPIO5_IO20         0x08c 0x3a0 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK      0x08c 0x3a0 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC       0x090 0x3a4 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_MCLK__CCM_CLKO1             0x090 0x3a4 0x000 0x3 0x0
+-#define MX6DL_PAD_CSI0_MCLK__GPIO5_IO19            0x090 0x3a4 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_MCLK__ARM_TRACE_CTL         0x090 0x3a4 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK    0x094 0x3a8 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_PIXCLK__GPIO5_IO18          0x094 0x3a8 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_PIXCLK__ARM_EVENTO          0x094 0x3a8 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC      0x098 0x3ac 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_VSYNC__EIM_DATA01           0x098 0x3ac 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_VSYNC__GPIO5_IO21           0x098 0x3ac 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_VSYNC__ARM_TRACE00          0x098 0x3ac 0x000 0x7 0x0
+-#define MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK  0x09c 0x3b0 0x000 0x0 0x0
+-#define MX6DL_PAD_DI0_DISP_CLK__LCD_CLK            0x09c 0x3b0 0x000 0x1 0x0
+-#define MX6DL_PAD_DI0_DISP_CLK__GPIO4_IO16         0x09c 0x3b0 0x000 0x5 0x0
+-#define MX6DL_PAD_DI0_DISP_CLK__LCD_WR_RWN         0x09c 0x3b0 0x000 0x8 0x0
+-#define MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15        0x0a0 0x3b4 0x000 0x0 0x0
+-#define MX6DL_PAD_DI0_PIN15__LCD_ENABLE            0x0a0 0x3b4 0x000 0x1 0x0
+-#define MX6DL_PAD_DI0_PIN15__AUD6_TXC              0x0a0 0x3b4 0x000 0x2 0x0
+-#define MX6DL_PAD_DI0_PIN15__GPIO4_IO17            0x0a0 0x3b4 0x000 0x5 0x0
+-#define MX6DL_PAD_DI0_PIN15__LCD_RD_E              0x0a0 0x3b4 0x000 0x8 0x0
+-#define MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN02         0x0a4 0x3b8 0x000 0x0 0x0
+-#define MX6DL_PAD_DI0_PIN2__LCD_HSYNC              0x0a4 0x3b8 0x8d8 0x1 0x0
+-#define MX6DL_PAD_DI0_PIN2__AUD6_TXD               0x0a4 0x3b8 0x000 0x2 0x0
+-#define MX6DL_PAD_DI0_PIN2__GPIO4_IO18             0x0a4 0x3b8 0x000 0x5 0x0
+-#define MX6DL_PAD_DI0_PIN2__LCD_RS                 0x0a4 0x3b8 0x000 0x8 0x0
+-#define MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN03         0x0a8 0x3bc 0x000 0x0 0x0
+-#define MX6DL_PAD_DI0_PIN3__LCD_VSYNC              0x0a8 0x3bc 0x000 0x1 0x0
+-#define MX6DL_PAD_DI0_PIN3__AUD6_TXFS              0x0a8 0x3bc 0x000 0x2 0x0
+-#define MX6DL_PAD_DI0_PIN3__GPIO4_IO19             0x0a8 0x3bc 0x000 0x5 0x0
+-#define MX6DL_PAD_DI0_PIN3__LCD_CS                 0x0a8 0x3bc 0x000 0x8 0x0
+-#define MX6DL_PAD_DI0_PIN4__IPU1_DI0_PIN04         0x0ac 0x3c0 0x000 0x0 0x0
+-#define MX6DL_PAD_DI0_PIN4__LCD_BUSY               0x0ac 0x3c0 0x8d8 0x1 0x1
+-#define MX6DL_PAD_DI0_PIN4__AUD6_RXD               0x0ac 0x3c0 0x000 0x2 0x0
+-#define MX6DL_PAD_DI0_PIN4__SD1_WP                 0x0ac 0x3c0 0x92c 0x3 0x0
+-#define MX6DL_PAD_DI0_PIN4__GPIO4_IO20             0x0ac 0x3c0 0x000 0x5 0x0
+-#define MX6DL_PAD_DI0_PIN4__LCD_RESET              0x0ac 0x3c0 0x000 0x8 0x0
+-#define MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00    0x0b0 0x3c4 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT0__LCD_DATA00           0x0b0 0x3c4 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT0__ECSPI3_SCLK          0x0b0 0x3c4 0x000 0x2 0x0
+-#define MX6DL_PAD_DISP0_DAT0__GPIO4_IO21           0x0b0 0x3c4 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01    0x0b4 0x3c8 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT1__LCD_DATA01           0x0b4 0x3c8 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT1__ECSPI3_MOSI          0x0b4 0x3c8 0x000 0x2 0x0
+-#define MX6DL_PAD_DISP0_DAT1__GPIO4_IO22           0x0b4 0x3c8 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10   0x0b8 0x3cc 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT10__LCD_DATA10          0x0b8 0x3cc 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT10__GPIO4_IO31          0x0b8 0x3cc 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11   0x0bc 0x3d0 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT11__LCD_DATA11          0x0bc 0x3d0 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT11__GPIO5_IO05          0x0bc 0x3d0 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12   0x0c0 0x3d4 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT12__LCD_DATA12          0x0c0 0x3d4 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT12__GPIO5_IO06          0x0c0 0x3d4 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13   0x0c4 0x3d8 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT13__LCD_DATA13          0x0c4 0x3d8 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT13__AUD5_RXFS           0x0c4 0x3d8 0x7bc 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT13__GPIO5_IO07          0x0c4 0x3d8 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14   0x0c8 0x3dc 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT14__LCD_DATA14          0x0c8 0x3dc 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT14__AUD5_RXC            0x0c8 0x3dc 0x7b8 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT14__GPIO5_IO08          0x0c8 0x3dc 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15   0x0cc 0x3e0 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT15__LCD_DATA15          0x0cc 0x3e0 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT15__ECSPI1_SS1          0x0cc 0x3e0 0x7e8 0x2 0x0
+-#define MX6DL_PAD_DISP0_DAT15__ECSPI2_SS1          0x0cc 0x3e0 0x804 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT15__GPIO5_IO09          0x0cc 0x3e0 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16   0x0d0 0x3e4 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT16__LCD_DATA16          0x0d0 0x3e4 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT16__ECSPI2_MOSI         0x0d0 0x3e4 0x7fc 0x2 0x1
+-#define MX6DL_PAD_DISP0_DAT16__AUD5_TXC            0x0d0 0x3e4 0x7c0 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0     0x0d0 0x3e4 0x8e8 0x4 0x0
+-#define MX6DL_PAD_DISP0_DAT16__GPIO5_IO10          0x0d0 0x3e4 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17   0x0d4 0x3e8 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT17__LCD_DATA17          0x0d4 0x3e8 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT17__ECSPI2_MISO         0x0d4 0x3e8 0x7f8 0x2 0x1
+-#define MX6DL_PAD_DISP0_DAT17__AUD5_TXD            0x0d4 0x3e8 0x7b4 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1     0x0d4 0x3e8 0x8ec 0x4 0x0
+-#define MX6DL_PAD_DISP0_DAT17__GPIO5_IO11          0x0d4 0x3e8 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18   0x0d8 0x3ec 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT18__LCD_DATA18          0x0d8 0x3ec 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT18__ECSPI2_SS0          0x0d8 0x3ec 0x800 0x2 0x1
+-#define MX6DL_PAD_DISP0_DAT18__AUD5_TXFS           0x0d8 0x3ec 0x7c4 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT18__AUD4_RXFS           0x0d8 0x3ec 0x7a4 0x4 0x0
+-#define MX6DL_PAD_DISP0_DAT18__GPIO5_IO12          0x0d8 0x3ec 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT18__EIM_CS2_B           0x0d8 0x3ec 0x000 0x7 0x0
+-#define MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19   0x0dc 0x3f0 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT19__LCD_DATA19          0x0dc 0x3f0 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT19__ECSPI2_SCLK         0x0dc 0x3f0 0x7f4 0x2 0x1
+-#define MX6DL_PAD_DISP0_DAT19__AUD5_RXD            0x0dc 0x3f0 0x7b0 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT19__AUD4_RXC            0x0dc 0x3f0 0x7a0 0x4 0x0
+-#define MX6DL_PAD_DISP0_DAT19__GPIO5_IO13          0x0dc 0x3f0 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT19__EIM_CS3_B           0x0dc 0x3f0 0x000 0x7 0x0
+-#define MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02    0x0e0 0x3f4 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT2__LCD_DATA02           0x0e0 0x3f4 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT2__ECSPI3_MISO          0x0e0 0x3f4 0x000 0x2 0x0
+-#define MX6DL_PAD_DISP0_DAT2__GPIO4_IO23           0x0e0 0x3f4 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20   0x0e4 0x3f8 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT20__LCD_DATA20          0x0e4 0x3f8 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT20__ECSPI1_SCLK         0x0e4 0x3f8 0x7d8 0x2 0x1
+-#define MX6DL_PAD_DISP0_DAT20__AUD4_TXC            0x0e4 0x3f8 0x7a8 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT20__GPIO5_IO14          0x0e4 0x3f8 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21   0x0e8 0x3fc 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT21__LCD_DATA21          0x0e8 0x3fc 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT21__ECSPI1_MOSI         0x0e8 0x3fc 0x7e0 0x2 0x1
+-#define MX6DL_PAD_DISP0_DAT21__AUD4_TXD            0x0e8 0x3fc 0x79c 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT21__GPIO5_IO15          0x0e8 0x3fc 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22   0x0ec 0x400 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT22__LCD_DATA22          0x0ec 0x400 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT22__ECSPI1_MISO         0x0ec 0x400 0x7dc 0x2 0x1
+-#define MX6DL_PAD_DISP0_DAT22__AUD4_TXFS           0x0ec 0x400 0x7ac 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT22__GPIO5_IO16          0x0ec 0x400 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23   0x0f0 0x404 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT23__LCD_DATA23          0x0f0 0x404 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT23__ECSPI1_SS0          0x0f0 0x404 0x7e4 0x2 0x1
+-#define MX6DL_PAD_DISP0_DAT23__AUD4_RXD            0x0f0 0x404 0x798 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT23__GPIO5_IO17          0x0f0 0x404 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03    0x0f4 0x408 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT3__LCD_DATA03           0x0f4 0x408 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT3__ECSPI3_SS0           0x0f4 0x408 0x000 0x2 0x0
+-#define MX6DL_PAD_DISP0_DAT3__GPIO4_IO24           0x0f4 0x408 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04    0x0f8 0x40c 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT4__LCD_DATA04           0x0f8 0x40c 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT4__ECSPI3_SS1           0x0f8 0x40c 0x000 0x2 0x0
+-#define MX6DL_PAD_DISP0_DAT4__GPIO4_IO25           0x0f8 0x40c 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05    0x0fc 0x410 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT5__LCD_DATA05           0x0fc 0x410 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT5__ECSPI3_SS2           0x0fc 0x410 0x000 0x2 0x0
+-#define MX6DL_PAD_DISP0_DAT5__AUD6_RXFS            0x0fc 0x410 0x000 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT5__GPIO4_IO26           0x0fc 0x410 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06    0x100 0x414 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT6__LCD_DATA06           0x100 0x414 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT6__ECSPI3_SS3           0x100 0x414 0x000 0x2 0x0
+-#define MX6DL_PAD_DISP0_DAT6__AUD6_RXC             0x100 0x414 0x000 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT6__GPIO4_IO27           0x100 0x414 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07    0x104 0x418 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT7__LCD_DATA07           0x104 0x418 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT7__ECSPI3_RDY           0x104 0x418 0x000 0x2 0x0
+-#define MX6DL_PAD_DISP0_DAT7__GPIO4_IO28           0x104 0x418 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08    0x108 0x41c 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT8__LCD_DATA08           0x108 0x41c 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT8__PWM1_OUT             0x108 0x41c 0x000 0x2 0x0
+-#define MX6DL_PAD_DISP0_DAT8__WDOG1_B              0x108 0x41c 0x000 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT8__GPIO4_IO29           0x108 0x41c 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09    0x10c 0x420 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT9__LCD_DATA09           0x10c 0x420 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT9__PWM2_OUT             0x10c 0x420 0x000 0x2 0x0
+-#define MX6DL_PAD_DISP0_DAT9__WDOG2_B              0x10c 0x420 0x000 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT9__GPIO4_IO30           0x10c 0x420 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_A16__EIM_ADDR16              0x110 0x4e0 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_A16__IPU1_DI1_DISP_CLK       0x110 0x4e0 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_A16__IPU1_CSI1_PIXCLK        0x110 0x4e0 0x8b8 0x2 0x0
+-#define MX6DL_PAD_EIM_A16__GPIO2_IO22              0x110 0x4e0 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_A16__SRC_BOOT_CFG16          0x110 0x4e0 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_A16__EPDC_DATA00             0x110 0x4e0 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_A17__EIM_ADDR17              0x114 0x4e4 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_A17__IPU1_DISP1_DATA12       0x114 0x4e4 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_A17__IPU1_CSI1_DATA12        0x114 0x4e4 0x890 0x2 0x0
+-#define MX6DL_PAD_EIM_A17__GPIO2_IO21              0x114 0x4e4 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_A17__SRC_BOOT_CFG17          0x114 0x4e4 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_A17__EPDC_PWR_STAT           0x114 0x4e4 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_A18__EIM_ADDR18              0x118 0x4e8 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_A18__IPU1_DISP1_DATA13       0x118 0x4e8 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_A18__IPU1_CSI1_DATA13        0x118 0x4e8 0x894 0x2 0x0
+-#define MX6DL_PAD_EIM_A18__GPIO2_IO20              0x118 0x4e8 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_A18__SRC_BOOT_CFG18          0x118 0x4e8 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_A18__EPDC_PWR_CTRL0          0x118 0x4e8 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_A19__EIM_ADDR19              0x11c 0x4ec 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_A19__IPU1_DISP1_DATA14       0x11c 0x4ec 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_A19__IPU1_CSI1_DATA14        0x11c 0x4ec 0x898 0x2 0x0
+-#define MX6DL_PAD_EIM_A19__GPIO2_IO19              0x11c 0x4ec 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_A19__SRC_BOOT_CFG19          0x11c 0x4ec 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_A19__EPDC_PWR_CTRL1          0x11c 0x4ec 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_A20__EIM_ADDR20              0x120 0x4f0 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_A20__IPU1_DISP1_DATA15       0x120 0x4f0 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_A20__IPU1_CSI1_DATA15        0x120 0x4f0 0x89c 0x2 0x0
+-#define MX6DL_PAD_EIM_A20__GPIO2_IO18              0x120 0x4f0 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_A20__SRC_BOOT_CFG20          0x120 0x4f0 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_A20__EPDC_PWR_CTRL2          0x120 0x4f0 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_A21__EIM_ADDR21              0x124 0x4f4 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_A21__IPU1_DISP1_DATA16       0x124 0x4f4 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_A21__IPU1_CSI1_DATA16        0x124 0x4f4 0x8a0 0x2 0x0
+-#define MX6DL_PAD_EIM_A21__GPIO2_IO17              0x124 0x4f4 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_A21__SRC_BOOT_CFG21          0x124 0x4f4 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_A21__EPDC_GDCLK              0x124 0x4f4 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_A22__EIM_ADDR22              0x128 0x4f8 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_A22__IPU1_DISP1_DATA17       0x128 0x4f8 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_A22__IPU1_CSI1_DATA17        0x128 0x4f8 0x8a4 0x2 0x0
+-#define MX6DL_PAD_EIM_A22__GPIO2_IO16              0x128 0x4f8 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_A22__SRC_BOOT_CFG22          0x128 0x4f8 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_A22__EPDC_GDSP               0x128 0x4f8 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_A23__EIM_ADDR23              0x12c 0x4fc 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_A23__IPU1_DISP1_DATA18       0x12c 0x4fc 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_A23__IPU1_CSI1_DATA18        0x12c 0x4fc 0x8a8 0x2 0x0
+-#define MX6DL_PAD_EIM_A23__IPU1_SISG3              0x12c 0x4fc 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_A23__GPIO6_IO06              0x12c 0x4fc 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_A23__SRC_BOOT_CFG23          0x12c 0x4fc 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_A23__EPDC_GDOE               0x12c 0x4fc 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_A24__EIM_ADDR24              0x130 0x500 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_A24__IPU1_DISP1_DATA19       0x130 0x500 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_A24__IPU1_CSI1_DATA19        0x130 0x500 0x8ac 0x2 0x0
+-#define MX6DL_PAD_EIM_A24__IPU1_SISG2              0x130 0x500 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_A24__GPIO5_IO04              0x130 0x500 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_A24__SRC_BOOT_CFG24          0x130 0x500 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_A24__EPDC_GDRL               0x130 0x500 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_A25__EIM_ADDR25              0x134 0x504 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_A25__ECSPI4_SS1              0x134 0x504 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_A25__ECSPI2_RDY              0x134 0x504 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_A25__IPU1_DI1_PIN12          0x134 0x504 0x000 0x3 0x0
+-#define MX6DL_PAD_EIM_A25__IPU1_DI0_D1_CS          0x134 0x504 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_A25__GPIO5_IO02              0x134 0x504 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_A25__HDMI_TX_CEC_LINE        0x134 0x504 0x85c 0x6 0x0
+-#define MX6DL_PAD_EIM_A25__EPDC_DATA15             0x134 0x504 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_A25__EIM_ACLK_FREERUN        0x134 0x504 0x000 0x9 0x0
+-#define MX6DL_PAD_EIM_BCLK__EIM_BCLK               0x138 0x508 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_BCLK__IPU1_DI1_PIN16         0x138 0x508 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_BCLK__GPIO6_IO31             0x138 0x508 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_BCLK__EPDC_SDCE9             0x138 0x508 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_CS0__EIM_CS0_B               0x13c 0x50c 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_CS0__IPU1_DI1_PIN05          0x13c 0x50c 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_CS0__ECSPI2_SCLK             0x13c 0x50c 0x7f4 0x2 0x2
+-#define MX6DL_PAD_EIM_CS0__GPIO2_IO23              0x13c 0x50c 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_CS0__EPDC_DATA06             0x13c 0x50c 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_CS1__EIM_CS1_B               0x140 0x510 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_CS1__IPU1_DI1_PIN06          0x140 0x510 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_CS1__ECSPI2_MOSI             0x140 0x510 0x7fc 0x2 0x2
+-#define MX6DL_PAD_EIM_CS1__GPIO2_IO24              0x140 0x510 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_CS1__EPDC_DATA08             0x140 0x510 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D16__EIM_DATA16              0x144 0x514 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D16__ECSPI1_SCLK             0x144 0x514 0x7d8 0x1 0x2
+-#define MX6DL_PAD_EIM_D16__IPU1_DI0_PIN05          0x144 0x514 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D16__IPU1_CSI1_DATA18        0x144 0x514 0x8a8 0x3 0x1
+-#define MX6DL_PAD_EIM_D16__HDMI_TX_DDC_SDA         0x144 0x514 0x864 0x4 0x0
+-#define MX6DL_PAD_EIM_D16__GPIO3_IO16              0x144 0x514 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D16__I2C2_SDA                0x144 0x514 0x874 0x6 0x0
+-#define MX6DL_PAD_EIM_D16__EPDC_DATA10             0x144 0x514 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D17__EIM_DATA17              0x148 0x518 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D17__ECSPI1_MISO             0x148 0x518 0x7dc 0x1 0x2
+-#define MX6DL_PAD_EIM_D17__IPU1_DI0_PIN06          0x148 0x518 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D17__IPU1_CSI1_PIXCLK        0x148 0x518 0x8b8 0x3 0x1
+-#define MX6DL_PAD_EIM_D17__DCIC1_OUT               0x148 0x518 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D17__GPIO3_IO17              0x148 0x518 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D17__I2C3_SCL                0x148 0x518 0x878 0x6 0x0
+-#define MX6DL_PAD_EIM_D17__EPDC_VCOM0              0x148 0x518 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D18__EIM_DATA18              0x14c 0x51c 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D18__ECSPI1_MOSI             0x14c 0x51c 0x7e0 0x1 0x2
+-#define MX6DL_PAD_EIM_D18__IPU1_DI0_PIN07          0x14c 0x51c 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D18__IPU1_CSI1_DATA17        0x14c 0x51c 0x8a4 0x3 0x1
+-#define MX6DL_PAD_EIM_D18__IPU1_DI1_D0_CS          0x14c 0x51c 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D18__GPIO3_IO18              0x14c 0x51c 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D18__I2C3_SDA                0x14c 0x51c 0x87c 0x6 0x0
+-#define MX6DL_PAD_EIM_D18__EPDC_VCOM1              0x14c 0x51c 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D19__EIM_DATA19              0x150 0x520 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D19__ECSPI1_SS1              0x150 0x520 0x7e8 0x1 0x1
+-#define MX6DL_PAD_EIM_D19__IPU1_DI0_PIN08          0x150 0x520 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D19__IPU1_CSI1_DATA16        0x150 0x520 0x8a0 0x3 0x1
+-#define MX6DL_PAD_EIM_D19__UART1_CTS_B             0x150 0x520 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D19__UART1_RTS_B             0x150 0x520 0x8f8 0x4 0x0
+-#define MX6DL_PAD_EIM_D19__GPIO3_IO19              0x150 0x520 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D19__EPIT1_OUT               0x150 0x520 0x000 0x6 0x0
+-#define MX6DL_PAD_EIM_D19__EPDC_DATA12             0x150 0x520 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D20__EIM_DATA20              0x154 0x524 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D20__ECSPI4_SS0              0x154 0x524 0x808 0x1 0x0
+-#define MX6DL_PAD_EIM_D20__IPU1_DI0_PIN16          0x154 0x524 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D20__IPU1_CSI1_DATA15        0x154 0x524 0x89c 0x3 0x1
+-#define MX6DL_PAD_EIM_D20__UART1_RTS_B             0x154 0x524 0x8f8 0x4 0x1
+-#define MX6DL_PAD_EIM_D20__UART1_CTS_B             0x154 0x524 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D20__GPIO3_IO20              0x154 0x524 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D20__EPIT2_OUT               0x154 0x524 0x000 0x6 0x0
+-#define MX6DL_PAD_EIM_D21__EIM_DATA21              0x158 0x528 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D21__ECSPI4_SCLK             0x158 0x528 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_D21__IPU1_DI0_PIN17          0x158 0x528 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D21__IPU1_CSI1_DATA11        0x158 0x528 0x88c 0x3 0x0
+-#define MX6DL_PAD_EIM_D21__USB_OTG_OC              0x158 0x528 0x920 0x4 0x0
+-#define MX6DL_PAD_EIM_D21__GPIO3_IO21              0x158 0x528 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D21__I2C1_SCL                0x158 0x528 0x868 0x6 0x1
+-#define MX6DL_PAD_EIM_D21__SPDIF_IN                0x158 0x528 0x8f0 0x7 0x0
+-#define MX6DL_PAD_EIM_D22__EIM_DATA22              0x15c 0x52c 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D22__ECSPI4_MISO             0x15c 0x52c 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_D22__IPU1_DI0_PIN01          0x15c 0x52c 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D22__IPU1_CSI1_DATA10        0x15c 0x52c 0x888 0x3 0x0
+-#define MX6DL_PAD_EIM_D22__USB_OTG_PWR             0x15c 0x52c 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D22__GPIO3_IO22              0x15c 0x52c 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D22__SPDIF_OUT               0x15c 0x52c 0x000 0x6 0x0
+-#define MX6DL_PAD_EIM_D22__EPDC_SDCE6              0x15c 0x52c 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D23__EIM_DATA23              0x160 0x530 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D23__IPU1_DI0_D0_CS          0x160 0x530 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_D23__UART3_CTS_B             0x160 0x530 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D23__UART3_RTS_B             0x160 0x530 0x908 0x2 0x0
+-#define MX6DL_PAD_EIM_D23__UART1_DCD_B             0x160 0x530 0x000 0x3 0x0
+-#define MX6DL_PAD_EIM_D23__IPU1_CSI1_DATA_EN       0x160 0x530 0x8b0 0x4 0x0
+-#define MX6DL_PAD_EIM_D23__GPIO3_IO23              0x160 0x530 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D23__IPU1_DI1_PIN02          0x160 0x530 0x000 0x6 0x0
+-#define MX6DL_PAD_EIM_D23__IPU1_DI1_PIN14          0x160 0x530 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_D23__EPDC_DATA11             0x160 0x530 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D24__EIM_DATA24              0x164 0x534 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D24__ECSPI4_SS2              0x164 0x534 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_D24__UART3_TX_DATA           0x164 0x534 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D24__UART3_RX_DATA           0x164 0x534 0x90c 0x2 0x0
+-#define MX6DL_PAD_EIM_D24__ECSPI1_SS2              0x164 0x534 0x7ec 0x3 0x0
+-#define MX6DL_PAD_EIM_D24__ECSPI2_SS2              0x164 0x534 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D24__GPIO3_IO24              0x164 0x534 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D24__AUD5_RXFS               0x164 0x534 0x7bc 0x6 0x1
+-#define MX6DL_PAD_EIM_D24__UART1_DTR_B             0x164 0x534 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_D24__EPDC_SDCE7              0x164 0x534 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D25__EIM_DATA25              0x168 0x538 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D25__ECSPI4_SS3              0x168 0x538 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_D25__UART3_RX_DATA           0x168 0x538 0x90c 0x2 0x1
+-#define MX6DL_PAD_EIM_D25__UART3_TX_DATA           0x168 0x538 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D25__ECSPI1_SS3              0x168 0x538 0x7f0 0x3 0x0
+-#define MX6DL_PAD_EIM_D25__ECSPI2_SS3              0x168 0x538 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D25__GPIO3_IO25              0x168 0x538 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D25__AUD5_RXC                0x168 0x538 0x7b8 0x6 0x1
+-#define MX6DL_PAD_EIM_D25__UART1_DSR_B             0x168 0x538 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_D25__EPDC_SDCE8              0x168 0x538 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D26__EIM_DATA26              0x16c 0x53c 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D26__IPU1_DI1_PIN11          0x16c 0x53c 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_D26__IPU1_CSI0_DATA01        0x16c 0x53c 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D26__IPU1_CSI1_DATA14        0x16c 0x53c 0x898 0x3 0x1
+-#define MX6DL_PAD_EIM_D26__UART2_TX_DATA           0x16c 0x53c 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D26__UART2_RX_DATA           0x16c 0x53c 0x904 0x4 0x0
+-#define MX6DL_PAD_EIM_D26__GPIO3_IO26              0x16c 0x53c 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D26__IPU1_SISG2              0x16c 0x53c 0x000 0x6 0x0
+-#define MX6DL_PAD_EIM_D26__IPU1_DISP1_DATA22       0x16c 0x53c 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_D26__EPDC_SDOED              0x16c 0x53c 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D27__EIM_DATA27              0x170 0x540 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D27__IPU1_DI1_PIN13          0x170 0x540 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_D27__IPU1_CSI0_DATA00        0x170 0x540 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D27__IPU1_CSI1_DATA13        0x170 0x540 0x894 0x3 0x1
+-#define MX6DL_PAD_EIM_D27__UART2_RX_DATA           0x170 0x540 0x904 0x4 0x1
+-#define MX6DL_PAD_EIM_D27__UART2_TX_DATA           0x170 0x540 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D27__GPIO3_IO27              0x170 0x540 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D27__IPU1_SISG3              0x170 0x540 0x000 0x6 0x0
+-#define MX6DL_PAD_EIM_D27__IPU1_DISP1_DATA23       0x170 0x540 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_D27__EPDC_SDOE               0x170 0x540 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D28__EIM_DATA28              0x174 0x544 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D28__I2C1_SDA                0x174 0x544 0x86c 0x1 0x1
+-#define MX6DL_PAD_EIM_D28__ECSPI4_MOSI             0x174 0x544 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D28__IPU1_CSI1_DATA12        0x174 0x544 0x890 0x3 0x1
+-#define MX6DL_PAD_EIM_D28__UART2_CTS_B             0x174 0x544 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D28__UART2_RTS_B             0x174 0x544 0x900 0x4 0x0
+-#define MX6DL_PAD_EIM_D28__GPIO3_IO28              0x174 0x544 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D28__IPU1_EXT_TRIG           0x174 0x544 0x000 0x6 0x0
+-#define MX6DL_PAD_EIM_D28__IPU1_DI0_PIN13          0x174 0x544 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_D28__EPDC_PWR_CTRL3          0x174 0x544 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D29__EIM_DATA29              0x178 0x548 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D29__IPU1_DI1_PIN15          0x178 0x548 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_D29__ECSPI4_SS0              0x178 0x548 0x808 0x2 0x1
+-#define MX6DL_PAD_EIM_D29__UART2_RTS_B             0x178 0x548 0x900 0x4 0x1
+-#define MX6DL_PAD_EIM_D29__UART2_CTS_B             0x178 0x548 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D29__GPIO3_IO29              0x178 0x548 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D29__IPU1_CSI1_VSYNC         0x178 0x548 0x8bc 0x6 0x0
+-#define MX6DL_PAD_EIM_D29__IPU1_DI0_PIN14          0x178 0x548 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_D29__EPDC_PWR_WAKE           0x178 0x548 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D30__EIM_DATA30              0x17c 0x54c 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D30__IPU1_DISP1_DATA21       0x17c 0x54c 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_D30__IPU1_DI0_PIN11          0x17c 0x54c 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D30__IPU1_CSI0_DATA03        0x17c 0x54c 0x000 0x3 0x0
+-#define MX6DL_PAD_EIM_D30__UART3_CTS_B             0x17c 0x54c 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D30__UART3_RTS_B             0x17c 0x54c 0x908 0x4 0x1
+-#define MX6DL_PAD_EIM_D30__GPIO3_IO30              0x17c 0x54c 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D30__USB_H1_OC               0x17c 0x54c 0x924 0x6 0x0
+-#define MX6DL_PAD_EIM_D30__EPDC_SDOEZ              0x17c 0x54c 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D31__EIM_DATA31              0x180 0x550 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D31__IPU1_DISP1_DATA20       0x180 0x550 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_D31__IPU1_DI0_PIN12          0x180 0x550 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D31__IPU1_CSI0_DATA02        0x180 0x550 0x000 0x3 0x0
+-#define MX6DL_PAD_EIM_D31__UART3_RTS_B             0x180 0x550 0x908 0x4 0x2
+-#define MX6DL_PAD_EIM_D31__UART3_CTS_B             0x180 0x550 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D31__GPIO3_IO31              0x180 0x550 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D31__USB_H1_PWR              0x180 0x550 0x000 0x6 0x0
+-#define MX6DL_PAD_EIM_D31__EPDC_SDCLK_P            0x180 0x550 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D31__EIM_ACLK_FREERUN        0x180 0x550 0x000 0x9 0x0
+-#define MX6DL_PAD_EIM_DA0__EIM_AD00                0x184 0x554 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA0__IPU1_DISP1_DATA09       0x184 0x554 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA0__IPU1_CSI1_DATA09        0x184 0x554 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_DA0__GPIO3_IO00              0x184 0x554 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA0__SRC_BOOT_CFG00          0x184 0x554 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA0__EPDC_SDCLK_N            0x184 0x554 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA1__EIM_AD01                0x188 0x558 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA1__IPU1_DISP1_DATA08       0x188 0x558 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA1__IPU1_CSI1_DATA08        0x188 0x558 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_DA1__GPIO3_IO01              0x188 0x558 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA1__SRC_BOOT_CFG01          0x188 0x558 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA1__EPDC_SDLE               0x188 0x558 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA10__EIM_AD10               0x18c 0x55c 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA10__IPU1_DI1_PIN15         0x18c 0x55c 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN      0x18c 0x55c 0x8b0 0x2 0x1
+-#define MX6DL_PAD_EIM_DA10__GPIO3_IO10             0x18c 0x55c 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA10__SRC_BOOT_CFG10         0x18c 0x55c 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA10__EPDC_DATA01            0x18c 0x55c 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA11__EIM_AD11               0x190 0x560 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA11__IPU1_DI1_PIN02         0x190 0x560 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA11__IPU1_CSI1_HSYNC        0x190 0x560 0x8b4 0x2 0x0
+-#define MX6DL_PAD_EIM_DA11__GPIO3_IO11             0x190 0x560 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA11__SRC_BOOT_CFG11         0x190 0x560 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA11__EPDC_DATA03            0x190 0x560 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA12__EIM_AD12               0x194 0x564 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA12__IPU1_DI1_PIN03         0x194 0x564 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA12__IPU1_CSI1_VSYNC        0x194 0x564 0x8bc 0x2 0x1
+-#define MX6DL_PAD_EIM_DA12__GPIO3_IO12             0x194 0x564 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA12__SRC_BOOT_CFG12         0x194 0x564 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA12__EPDC_DATA02            0x194 0x564 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA13__EIM_AD13               0x198 0x568 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA13__IPU1_DI1_D0_CS         0x198 0x568 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA13__GPIO3_IO13             0x198 0x568 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA13__SRC_BOOT_CFG13         0x198 0x568 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA13__EPDC_DATA13            0x198 0x568 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA14__EIM_AD14               0x19c 0x56c 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA14__IPU1_DI1_D1_CS         0x19c 0x56c 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA14__GPIO3_IO14             0x19c 0x56c 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA14__SRC_BOOT_CFG14         0x19c 0x56c 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA14__EPDC_DATA14            0x19c 0x56c 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA15__EIM_AD15               0x1a0 0x570 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA15__IPU1_DI1_PIN01         0x1a0 0x570 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA15__IPU1_DI1_PIN04         0x1a0 0x570 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_DA15__GPIO3_IO15             0x1a0 0x570 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA15__SRC_BOOT_CFG15         0x1a0 0x570 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA15__EPDC_DATA09            0x1a0 0x570 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA2__EIM_AD02                0x1a4 0x574 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA2__IPU1_DISP1_DATA07       0x1a4 0x574 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA2__IPU1_CSI1_DATA07        0x1a4 0x574 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_DA2__GPIO3_IO02              0x1a4 0x574 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA2__SRC_BOOT_CFG02          0x1a4 0x574 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA2__EPDC_BDR0               0x1a4 0x574 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA3__EIM_AD03                0x1a8 0x578 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA3__IPU1_DISP1_DATA06       0x1a8 0x578 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA3__IPU1_CSI1_DATA06        0x1a8 0x578 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_DA3__GPIO3_IO03              0x1a8 0x578 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA3__SRC_BOOT_CFG03          0x1a8 0x578 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA3__EPDC_BDR1               0x1a8 0x578 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA4__EIM_AD04                0x1ac 0x57c 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA4__IPU1_DISP1_DATA05       0x1ac 0x57c 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA4__IPU1_CSI1_DATA05        0x1ac 0x57c 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_DA4__GPIO3_IO04              0x1ac 0x57c 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA4__SRC_BOOT_CFG04          0x1ac 0x57c 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA4__EPDC_SDCE0              0x1ac 0x57c 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA5__EIM_AD05                0x1b0 0x580 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA5__IPU1_DISP1_DATA04       0x1b0 0x580 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA5__IPU1_CSI1_DATA04        0x1b0 0x580 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_DA5__GPIO3_IO05              0x1b0 0x580 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA5__SRC_BOOT_CFG05          0x1b0 0x580 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA5__EPDC_SDCE1              0x1b0 0x580 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA6__EIM_AD06                0x1b4 0x584 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA6__IPU1_DISP1_DATA03       0x1b4 0x584 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA6__IPU1_CSI1_DATA03        0x1b4 0x584 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_DA6__GPIO3_IO06              0x1b4 0x584 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA6__SRC_BOOT_CFG06          0x1b4 0x584 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA6__EPDC_SDCE2              0x1b4 0x584 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA7__EIM_AD07                0x1b8 0x588 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA7__IPU1_DISP1_DATA02       0x1b8 0x588 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA7__IPU1_CSI1_DATA02        0x1b8 0x588 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_DA7__GPIO3_IO07              0x1b8 0x588 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA7__SRC_BOOT_CFG07          0x1b8 0x588 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA7__EPDC_SDCE3              0x1b8 0x588 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA8__EIM_AD08                0x1bc 0x58c 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA8__IPU1_DISP1_DATA01       0x1bc 0x58c 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA8__IPU1_CSI1_DATA01        0x1bc 0x58c 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_DA8__GPIO3_IO08              0x1bc 0x58c 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA8__SRC_BOOT_CFG08          0x1bc 0x58c 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA8__EPDC_SDCE4              0x1bc 0x58c 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA9__EIM_AD09                0x1c0 0x590 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA9__IPU1_DISP1_DATA00       0x1c0 0x590 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA9__IPU1_CSI1_DATA00        0x1c0 0x590 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_DA9__GPIO3_IO09              0x1c0 0x590 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA9__SRC_BOOT_CFG09          0x1c0 0x590 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA9__EPDC_SDCE5              0x1c0 0x590 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_EB0__EIM_EB0_B               0x1c4 0x594 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_EB0__IPU1_DISP1_DATA11       0x1c4 0x594 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_EB0__IPU1_CSI1_DATA11        0x1c4 0x594 0x88c 0x2 0x1
+-#define MX6DL_PAD_EIM_EB0__CCM_PMIC_READY          0x1c4 0x594 0x7d4 0x4 0x0
+-#define MX6DL_PAD_EIM_EB0__GPIO2_IO28              0x1c4 0x594 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_EB0__SRC_BOOT_CFG27          0x1c4 0x594 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_EB0__EPDC_PWR_COM            0x1c4 0x594 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_EB1__EIM_EB1_B               0x1c8 0x598 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_EB1__IPU1_DISP1_DATA10       0x1c8 0x598 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_EB1__IPU1_CSI1_DATA10        0x1c8 0x598 0x888 0x2 0x1
+-#define MX6DL_PAD_EIM_EB1__GPIO2_IO29              0x1c8 0x598 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_EB1__SRC_BOOT_CFG28          0x1c8 0x598 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_EB1__EPDC_SDSHR              0x1c8 0x598 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_EB2__EIM_EB2_B               0x1cc 0x59c 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_EB2__ECSPI1_SS0              0x1cc 0x59c 0x7e4 0x1 0x2
+-#define MX6DL_PAD_EIM_EB2__IPU1_CSI1_DATA19        0x1cc 0x59c 0x8ac 0x3 0x1
+-#define MX6DL_PAD_EIM_EB2__HDMI_TX_DDC_SCL         0x1cc 0x59c 0x860 0x4 0x0
+-#define MX6DL_PAD_EIM_EB2__GPIO2_IO30              0x1cc 0x59c 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_EB2__I2C2_SCL                0x1cc 0x59c 0x870 0x6 0x0
+-#define MX6DL_PAD_EIM_EB2__SRC_BOOT_CFG30          0x1cc 0x59c 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_EB2__EPDC_DATA05             0x1cc 0x59c 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_EB3__EIM_EB3_B               0x1d0 0x5a0 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_EB3__ECSPI4_RDY              0x1d0 0x5a0 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_EB3__UART3_RTS_B             0x1d0 0x5a0 0x908 0x2 0x3
+-#define MX6DL_PAD_EIM_EB3__UART3_CTS_B             0x1d0 0x5a0 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_EB3__UART1_RI_B              0x1d0 0x5a0 0x000 0x3 0x0
+-#define MX6DL_PAD_EIM_EB3__IPU1_CSI1_HSYNC         0x1d0 0x5a0 0x8b4 0x4 0x1
+-#define MX6DL_PAD_EIM_EB3__GPIO2_IO31              0x1d0 0x5a0 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_EB3__IPU1_DI1_PIN03          0x1d0 0x5a0 0x000 0x6 0x0
+-#define MX6DL_PAD_EIM_EB3__SRC_BOOT_CFG31          0x1d0 0x5a0 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_EB3__EPDC_SDCE0              0x1d0 0x5a0 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_EB3__EIM_ACLK_FREERUN        0x1d0 0x5a0 0x000 0x9 0x0
+-#define MX6DL_PAD_EIM_LBA__EIM_LBA_B               0x1d4 0x5a4 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_LBA__IPU1_DI1_PIN17          0x1d4 0x5a4 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_LBA__ECSPI2_SS1              0x1d4 0x5a4 0x804 0x2 0x1
+-#define MX6DL_PAD_EIM_LBA__GPIO2_IO27              0x1d4 0x5a4 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_LBA__SRC_BOOT_CFG26          0x1d4 0x5a4 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_LBA__EPDC_DATA04             0x1d4 0x5a4 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_OE__EIM_OE_B                 0x1d8 0x5a8 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_OE__IPU1_DI1_PIN07           0x1d8 0x5a8 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_OE__ECSPI2_MISO              0x1d8 0x5a8 0x7f8 0x2 0x2
+-#define MX6DL_PAD_EIM_OE__GPIO2_IO25               0x1d8 0x5a8 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_OE__EPDC_PWR_IRQ             0x1d8 0x5a8 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_RW__EIM_RW                   0x1dc 0x5ac 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_RW__IPU1_DI1_PIN08           0x1dc 0x5ac 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_RW__ECSPI2_SS0               0x1dc 0x5ac 0x800 0x2 0x2
+-#define MX6DL_PAD_EIM_RW__GPIO2_IO26               0x1dc 0x5ac 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_RW__SRC_BOOT_CFG29           0x1dc 0x5ac 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_RW__EPDC_DATA07              0x1dc 0x5ac 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_WAIT__EIM_WAIT_B             0x1e0 0x5b0 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_WAIT__EIM_DTACK_B            0x1e0 0x5b0 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_WAIT__GPIO5_IO00             0x1e0 0x5b0 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_WAIT__SRC_BOOT_CFG25         0x1e0 0x5b0 0x000 0x7 0x0
+-#define MX6DL_PAD_ENET_CRS_DV__ENET_RX_EN          0x1e4 0x5b4 0x828 0x1 0x0
+-#define MX6DL_PAD_ENET_CRS_DV__ESAI_TX_CLK         0x1e4 0x5b4 0x840 0x2 0x0
+-#define MX6DL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK       0x1e4 0x5b4 0x8f4 0x3 0x0
+-#define MX6DL_PAD_ENET_CRS_DV__GPIO1_IO25          0x1e4 0x5b4 0x000 0x5 0x0
+-#define MX6DL_PAD_ENET_MDC__MLB_DATA               0x1e8 0x5b8 0x8e0 0x0 0x0
+-#define MX6DL_PAD_ENET_MDC__ENET_MDC               0x1e8 0x5b8 0x000 0x1 0x0
+-#define MX6DL_PAD_ENET_MDC__ESAI_TX5_RX0           0x1e8 0x5b8 0x858 0x2 0x0
+-#define MX6DL_PAD_ENET_MDC__ENET_1588_EVENT1_IN    0x1e8 0x5b8 0x000 0x4 0x0
+-#define MX6DL_PAD_ENET_MDC__GPIO1_IO31             0x1e8 0x5b8 0x000 0x5 0x0
+-#define MX6DL_PAD_ENET_MDIO__ENET_MDIO             0x1ec 0x5bc 0x810 0x1 0x0
+-#define MX6DL_PAD_ENET_MDIO__ESAI_RX_CLK           0x1ec 0x5bc 0x83c 0x2 0x0
+-#define MX6DL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT  0x1ec 0x5bc 0x000 0x4 0x0
+-#define MX6DL_PAD_ENET_MDIO__GPIO1_IO22            0x1ec 0x5bc 0x000 0x5 0x0
+-#define MX6DL_PAD_ENET_MDIO__SPDIF_LOCK            0x1ec 0x5bc 0x000 0x6 0x0
+-#define MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK        0x1f0 0x5c0 0x000 0x1 0x0
+-#define MX6DL_PAD_ENET_REF_CLK__ESAI_RX_FS         0x1f0 0x5c0 0x82c 0x2 0x0
+-#define MX6DL_PAD_ENET_REF_CLK__GPIO1_IO23         0x1f0 0x5c0 0x000 0x5 0x0
+-#define MX6DL_PAD_ENET_REF_CLK__SPDIF_SR_CLK       0x1f0 0x5c0 0x000 0x6 0x0
+-#define MX6DL_PAD_ENET_RX_ER__USB_OTG_ID           0x1f4 0x5c4 0x790 0x0 0x0
+-#define MX6DL_PAD_ENET_RX_ER__ENET_RX_ER           0x1f4 0x5c4 0x000 0x1 0x0
+-#define MX6DL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK       0x1f4 0x5c4 0x834 0x2 0x0
+-#define MX6DL_PAD_ENET_RX_ER__SPDIF_IN             0x1f4 0x5c4 0x8f0 0x3 0x1
+-#define MX6DL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0
+-#define MX6DL_PAD_ENET_RX_ER__GPIO1_IO24           0x1f4 0x5c4 0x000 0x5 0x0
+-#define MX6DL_PAD_ENET_RXD0__ENET_RX_DATA0         0x1f8 0x5c8 0x818 0x1 0x0
+-#define MX6DL_PAD_ENET_RXD0__ESAI_TX_HF_CLK        0x1f8 0x5c8 0x838 0x2 0x0
+-#define MX6DL_PAD_ENET_RXD0__SPDIF_OUT             0x1f8 0x5c8 0x000 0x3 0x0
+-#define MX6DL_PAD_ENET_RXD0__GPIO1_IO27            0x1f8 0x5c8 0x000 0x5 0x0
+-#define MX6DL_PAD_ENET_RXD1__MLB_SIG               0x1fc 0x5cc 0x8e4 0x0 0x0
+-#define MX6DL_PAD_ENET_RXD1__ENET_RX_DATA1         0x1fc 0x5cc 0x81c 0x1 0x0
+-#define MX6DL_PAD_ENET_RXD1__ESAI_TX_FS            0x1fc 0x5cc 0x830 0x2 0x0
+-#define MX6DL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT  0x1fc 0x5cc 0x000 0x4 0x0
+-#define MX6DL_PAD_ENET_RXD1__GPIO1_IO26            0x1fc 0x5cc 0x000 0x5 0x0
+-#define MX6DL_PAD_ENET_TX_EN__ENET_TX_EN           0x200 0x5d0 0x000 0x1 0x0
+-#define MX6DL_PAD_ENET_TX_EN__ESAI_TX3_RX2         0x200 0x5d0 0x850 0x2 0x0
+-#define MX6DL_PAD_ENET_TX_EN__GPIO1_IO28           0x200 0x5d0 0x000 0x5 0x0
+-#define MX6DL_PAD_ENET_TX_EN__I2C4_SCL             0x200 0x5d0 0x880 0x9 0x0
+-#define MX6DL_PAD_ENET_TXD0__ENET_TX_DATA0         0x204 0x5d4 0x000 0x1 0x0
+-#define MX6DL_PAD_ENET_TXD0__ESAI_TX4_RX1          0x204 0x5d4 0x854 0x2 0x0
+-#define MX6DL_PAD_ENET_TXD0__GPIO1_IO30            0x204 0x5d4 0x000 0x5 0x0
+-#define MX6DL_PAD_ENET_TXD1__MLB_CLK               0x208 0x5d8 0x8dc 0x0 0x0
+-#define MX6DL_PAD_ENET_TXD1__ENET_TX_DATA1         0x208 0x5d8 0x000 0x1 0x0
+-#define MX6DL_PAD_ENET_TXD1__ESAI_TX2_RX3          0x208 0x5d8 0x84c 0x2 0x0
+-#define MX6DL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN   0x208 0x5d8 0x000 0x4 0x0
+-#define MX6DL_PAD_ENET_TXD1__GPIO1_IO29            0x208 0x5d8 0x000 0x5 0x0
+-#define MX6DL_PAD_ENET_TXD1__I2C4_SDA              0x208 0x5d8 0x884 0x9 0x0
+-#define MX6DL_PAD_GPIO_0__CCM_CLKO1                0x20c 0x5dc 0x000 0x0 0x0
+-#define MX6DL_PAD_GPIO_0__KEY_COL5                 0x20c 0x5dc 0x8c0 0x2 0x1
+-#define MX6DL_PAD_GPIO_0__ASRC_EXT_CLK             0x20c 0x5dc 0x794 0x3 0x0
+-#define MX6DL_PAD_GPIO_0__EPIT1_OUT                0x20c 0x5dc 0x000 0x4 0x0
+-#define MX6DL_PAD_GPIO_0__GPIO1_IO00               0x20c 0x5dc 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_0__USB_H1_PWR               0x20c 0x5dc 0x000 0x6 0x0
+-#define MX6DL_PAD_GPIO_0__SNVS_VIO_5               0x20c 0x5dc 0x000 0x7 0x0
+-#define MX6DL_PAD_GPIO_1__ESAI_RX_CLK              0x210 0x5e0 0x83c 0x0 0x1
+-#define MX6DL_PAD_GPIO_1__WDOG2_B                  0x210 0x5e0 0x000 0x1 0x0
+-#define MX6DL_PAD_GPIO_1__KEY_ROW5                 0x210 0x5e0 0x8cc 0x2 0x1
+-#define MX6DL_PAD_GPIO_1__USB_OTG_ID               0x210 0x5e0 0x790 0x3 0x1
+-#define MX6DL_PAD_GPIO_1__PWM2_OUT                 0x210 0x5e0 0x000 0x4 0x0
+-#define MX6DL_PAD_GPIO_1__GPIO1_IO01               0x210 0x5e0 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_1__SD1_CD_B                 0x210 0x5e0 0x000 0x6 0x0
+-#define MX6DL_PAD_GPIO_16__ESAI_TX3_RX2            0x214 0x5e4 0x850 0x0 0x1
+-#define MX6DL_PAD_GPIO_16__ENET_1588_EVENT2_IN     0x214 0x5e4 0x000 0x1 0x0
+-#define MX6DL_PAD_GPIO_16__ENET_REF_CLK            0x214 0x5e4 0x80c 0x2 0x0
+-#define MX6DL_PAD_GPIO_16__SD1_LCTL                0x214 0x5e4 0x000 0x3 0x0
+-#define MX6DL_PAD_GPIO_16__SPDIF_IN                0x214 0x5e4 0x8f0 0x4 0x2
+-#define MX6DL_PAD_GPIO_16__GPIO7_IO11              0x214 0x5e4 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_16__I2C3_SDA                0x214 0x5e4 0x87c 0x6 0x1
+-#define MX6DL_PAD_GPIO_16__JTAG_DE_B               0x214 0x5e4 0x000 0x7 0x0
+-#define MX6DL_PAD_GPIO_17__ESAI_TX0                0x218 0x5e8 0x844 0x0 0x0
+-#define MX6DL_PAD_GPIO_17__ENET_1588_EVENT3_IN     0x218 0x5e8 0x000 0x1 0x0
+-#define MX6DL_PAD_GPIO_17__CCM_PMIC_READY          0x218 0x5e8 0x7d4 0x2 0x1
+-#define MX6DL_PAD_GPIO_17__SDMA_EXT_EVENT0         0x218 0x5e8 0x8e8 0x3 0x1
+-#define MX6DL_PAD_GPIO_17__SPDIF_OUT               0x218 0x5e8 0x000 0x4 0x0
+-#define MX6DL_PAD_GPIO_17__GPIO7_IO12              0x218 0x5e8 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_18__ESAI_TX1                0x21c 0x5ec 0x848 0x0 0x0
+-#define MX6DL_PAD_GPIO_18__ENET_RX_CLK             0x21c 0x5ec 0x814 0x1 0x0
+-#define MX6DL_PAD_GPIO_18__SD3_VSELECT             0x21c 0x5ec 0x000 0x2 0x0
+-#define MX6DL_PAD_GPIO_18__SDMA_EXT_EVENT1         0x21c 0x5ec 0x8ec 0x3 0x1
+-#define MX6DL_PAD_GPIO_18__ASRC_EXT_CLK            0x21c 0x5ec 0x794 0x4 0x1
+-#define MX6DL_PAD_GPIO_18__GPIO7_IO13              0x21c 0x5ec 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_18__SNVS_VIO_5_CTL          0x21c 0x5ec 0x000 0x6 0x0
+-#define MX6DL_PAD_GPIO_19__KEY_COL5                0x220 0x5f0 0x8c0 0x0 0x2
+-#define MX6DL_PAD_GPIO_19__ENET_1588_EVENT0_OUT    0x220 0x5f0 0x000 0x1 0x0
+-#define MX6DL_PAD_GPIO_19__SPDIF_OUT               0x220 0x5f0 0x000 0x2 0x0
+-#define MX6DL_PAD_GPIO_19__CCM_CLKO1               0x220 0x5f0 0x000 0x3 0x0
+-#define MX6DL_PAD_GPIO_19__ECSPI1_RDY              0x220 0x5f0 0x000 0x4 0x0
+-#define MX6DL_PAD_GPIO_19__GPIO4_IO05              0x220 0x5f0 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_19__ENET_TX_ER              0x220 0x5f0 0x000 0x6 0x0
+-#define MX6DL_PAD_GPIO_2__ESAI_TX_FS               0x224 0x5f4 0x830 0x0 0x1
+-#define MX6DL_PAD_GPIO_2__KEY_ROW6                 0x224 0x5f4 0x8d0 0x2 0x1
+-#define MX6DL_PAD_GPIO_2__GPIO1_IO02               0x224 0x5f4 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_2__SD2_WP                   0x224 0x5f4 0x000 0x6 0x0
+-#define MX6DL_PAD_GPIO_2__MLB_DATA                 0x224 0x5f4 0x8e0 0x7 0x1
+-#define MX6DL_PAD_GPIO_3__ESAI_RX_HF_CLK           0x228 0x5f8 0x834 0x0 0x1
+-#define MX6DL_PAD_GPIO_3__I2C3_SCL                 0x228 0x5f8 0x878 0x2 0x1
+-#define MX6DL_PAD_GPIO_3__XTALOSC_REF_CLK_24M      0x228 0x5f8 0x000 0x3 0x0
+-#define MX6DL_PAD_GPIO_3__CCM_CLKO2                0x228 0x5f8 0x000 0x4 0x0
+-#define MX6DL_PAD_GPIO_3__GPIO1_IO03               0x228 0x5f8 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_3__USB_H1_OC                0x228 0x5f8 0x924 0x6 0x1
+-#define MX6DL_PAD_GPIO_3__MLB_CLK                  0x228 0x5f8 0x8dc 0x7 0x1
+-#define MX6DL_PAD_GPIO_4__ESAI_TX_HF_CLK           0x22c 0x5fc 0x838 0x0 0x1
+-#define MX6DL_PAD_GPIO_4__KEY_COL7                 0x22c 0x5fc 0x8c8 0x2 0x1
+-#define MX6DL_PAD_GPIO_4__GPIO1_IO04               0x22c 0x5fc 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_4__SD2_CD_B                 0x22c 0x5fc 0x000 0x6 0x0
+-#define MX6DL_PAD_GPIO_5__ESAI_TX2_RX3             0x230 0x600 0x84c 0x0 0x1
+-#define MX6DL_PAD_GPIO_5__KEY_ROW7                 0x230 0x600 0x8d4 0x2 0x1
+-#define MX6DL_PAD_GPIO_5__CCM_CLKO1                0x230 0x600 0x000 0x3 0x0
+-#define MX6DL_PAD_GPIO_5__GPIO1_IO05               0x230 0x600 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_5__I2C3_SCL                 0x230 0x600 0x878 0x6 0x2
+-#define MX6DL_PAD_GPIO_5__ARM_EVENTI               0x230 0x600 0x000 0x7 0x0
+-#define MX6DL_PAD_GPIO_6__ESAI_TX_CLK              0x234 0x604 0x840 0x0 0x1
+-#define MX6DL_PAD_GPIO_6__I2C3_SDA                 0x234 0x604 0x87c 0x2 0x2
+-#define MX6DL_PAD_GPIO_6__GPIO1_IO06               0x234 0x604 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_6__SD2_LCTL                 0x234 0x604 0x000 0x6 0x0
+-#define MX6DL_PAD_GPIO_6__MLB_SIG                  0x234 0x604 0x8e4 0x7 0x1
+-#define MX6DL_PAD_GPIO_7__ESAI_TX4_RX1             0x238 0x608 0x854 0x0 0x1
+-#define MX6DL_PAD_GPIO_7__EPIT1_OUT                0x238 0x608 0x000 0x2 0x0
+-#define MX6DL_PAD_GPIO_7__FLEXCAN1_TX              0x238 0x608 0x000 0x3 0x0
+-#define MX6DL_PAD_GPIO_7__UART2_TX_DATA            0x238 0x608 0x000 0x4 0x0
+-#define MX6DL_PAD_GPIO_7__UART2_RX_DATA            0x238 0x608 0x904 0x4 0x2
+-#define MX6DL_PAD_GPIO_7__GPIO1_IO07               0x238 0x608 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_7__SPDIF_LOCK               0x238 0x608 0x000 0x6 0x0
+-#define MX6DL_PAD_GPIO_7__USB_OTG_HOST_MODE        0x238 0x608 0x000 0x7 0x0
+-#define MX6DL_PAD_GPIO_7__I2C4_SCL                 0x238 0x608 0x880 0x8 0x1
+-#define MX6DL_PAD_GPIO_8__ESAI_TX5_RX0             0x23c 0x60c 0x858 0x0 0x1
+-#define MX6DL_PAD_GPIO_8__XTALOSC_REF_CLK_32K      0x23c 0x60c 0x000 0x1 0x0
+-#define MX6DL_PAD_GPIO_8__EPIT2_OUT                0x23c 0x60c 0x000 0x2 0x0
+-#define MX6DL_PAD_GPIO_8__FLEXCAN1_RX              0x23c 0x60c 0x7c8 0x3 0x0
+-#define MX6DL_PAD_GPIO_8__UART2_RX_DATA            0x23c 0x60c 0x904 0x4 0x3
+-#define MX6DL_PAD_GPIO_8__UART2_TX_DATA            0x23c 0x60c 0x000 0x4 0x0
+-#define MX6DL_PAD_GPIO_8__GPIO1_IO08               0x23c 0x60c 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_8__SPDIF_SR_CLK             0x23c 0x60c 0x000 0x6 0x0
+-#define MX6DL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE     0x23c 0x60c 0x000 0x7 0x0
+-#define MX6DL_PAD_GPIO_8__I2C4_SDA                 0x23c 0x60c 0x884 0x8 0x1
+-#define MX6DL_PAD_GPIO_9__ESAI_RX_FS               0x240 0x610 0x82c 0x0 0x1
+-#define MX6DL_PAD_GPIO_9__WDOG1_B                  0x240 0x610 0x000 0x1 0x0
+-#define MX6DL_PAD_GPIO_9__KEY_COL6                 0x240 0x610 0x8c4 0x2 0x1
+-#define MX6DL_PAD_GPIO_9__CCM_REF_EN_B             0x240 0x610 0x000 0x3 0x0
+-#define MX6DL_PAD_GPIO_9__PWM1_OUT                 0x240 0x610 0x000 0x4 0x0
+-#define MX6DL_PAD_GPIO_9__GPIO1_IO09               0x240 0x610 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_9__SD1_WP                   0x240 0x610 0x92c 0x6 0x1
+-#define MX6DL_PAD_KEY_COL0__ECSPI1_SCLK            0x244 0x62c 0x7d8 0x0 0x3
+-#define MX6DL_PAD_KEY_COL0__ENET_RX_DATA3          0x244 0x62c 0x824 0x1 0x0
+-#define MX6DL_PAD_KEY_COL0__AUD5_TXC               0x244 0x62c 0x7c0 0x2 0x1
+-#define MX6DL_PAD_KEY_COL0__KEY_COL0               0x244 0x62c 0x000 0x3 0x0
+-#define MX6DL_PAD_KEY_COL0__UART4_TX_DATA          0x244 0x62c 0x000 0x4 0x0
+-#define MX6DL_PAD_KEY_COL0__UART4_RX_DATA          0x244 0x62c 0x914 0x4 0x2
+-#define MX6DL_PAD_KEY_COL0__GPIO4_IO06             0x244 0x62c 0x000 0x5 0x0
+-#define MX6DL_PAD_KEY_COL0__DCIC1_OUT              0x244 0x62c 0x000 0x6 0x0
+-#define MX6DL_PAD_KEY_COL1__ECSPI1_MISO            0x248 0x630 0x7dc 0x0 0x3
+-#define MX6DL_PAD_KEY_COL1__ENET_MDIO              0x248 0x630 0x810 0x1 0x1
+-#define MX6DL_PAD_KEY_COL1__AUD5_TXFS              0x248 0x630 0x7c4 0x2 0x1
+-#define MX6DL_PAD_KEY_COL1__KEY_COL1               0x248 0x630 0x000 0x3 0x0
+-#define MX6DL_PAD_KEY_COL1__UART5_TX_DATA          0x248 0x630 0x000 0x4 0x0
+-#define MX6DL_PAD_KEY_COL1__UART5_RX_DATA          0x248 0x630 0x91c 0x4 0x2
+-#define MX6DL_PAD_KEY_COL1__GPIO4_IO08             0x248 0x630 0x000 0x5 0x0
+-#define MX6DL_PAD_KEY_COL1__SD1_VSELECT            0x248 0x630 0x000 0x6 0x0
+-#define MX6DL_PAD_KEY_COL2__ECSPI1_SS1             0x24c 0x634 0x7e8 0x0 0x2
+-#define MX6DL_PAD_KEY_COL2__ENET_RX_DATA2          0x24c 0x634 0x820 0x1 0x0
+-#define MX6DL_PAD_KEY_COL2__FLEXCAN1_TX            0x24c 0x634 0x000 0x2 0x0
+-#define MX6DL_PAD_KEY_COL2__KEY_COL2               0x24c 0x634 0x000 0x3 0x0
+-#define MX6DL_PAD_KEY_COL2__ENET_MDC               0x24c 0x634 0x000 0x4 0x0
+-#define MX6DL_PAD_KEY_COL2__GPIO4_IO10             0x24c 0x634 0x000 0x5 0x0
+-#define MX6DL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE    0x24c 0x634 0x000 0x6 0x0
+-#define MX6DL_PAD_KEY_COL3__ECSPI1_SS3             0x250 0x638 0x7f0 0x0 0x1
+-#define MX6DL_PAD_KEY_COL3__ENET_CRS               0x250 0x638 0x000 0x1 0x0
+-#define MX6DL_PAD_KEY_COL3__HDMI_TX_DDC_SCL        0x250 0x638 0x860 0x2 0x1
+-#define MX6DL_PAD_KEY_COL3__KEY_COL3               0x250 0x638 0x000 0x3 0x0
+-#define MX6DL_PAD_KEY_COL3__I2C2_SCL               0x250 0x638 0x870 0x4 0x1
+-#define MX6DL_PAD_KEY_COL3__GPIO4_IO12             0x250 0x638 0x000 0x5 0x0
+-#define MX6DL_PAD_KEY_COL3__SPDIF_IN               0x250 0x638 0x8f0 0x6 0x3
+-#define MX6DL_PAD_KEY_COL4__FLEXCAN2_TX            0x254 0x63c 0x000 0x0 0x0
+-#define MX6DL_PAD_KEY_COL4__IPU1_SISG4             0x254 0x63c 0x000 0x1 0x0
+-#define MX6DL_PAD_KEY_COL4__USB_OTG_OC             0x254 0x63c 0x920 0x2 0x1
+-#define MX6DL_PAD_KEY_COL4__KEY_COL4               0x254 0x63c 0x000 0x3 0x0
+-#define MX6DL_PAD_KEY_COL4__UART5_RTS_B            0x254 0x63c 0x918 0x4 0x2
+-#define MX6DL_PAD_KEY_COL4__UART5_CTS_B            0x254 0x63c 0x000 0x4 0x0
+-#define MX6DL_PAD_KEY_COL4__GPIO4_IO14             0x254 0x63c 0x000 0x5 0x0
+-#define MX6DL_PAD_KEY_ROW0__ECSPI1_MOSI            0x258 0x640 0x7e0 0x0 0x3
+-#define MX6DL_PAD_KEY_ROW0__ENET_TX_DATA3          0x258 0x640 0x000 0x1 0x0
+-#define MX6DL_PAD_KEY_ROW0__AUD5_TXD               0x258 0x640 0x7b4 0x2 0x1
+-#define MX6DL_PAD_KEY_ROW0__KEY_ROW0               0x258 0x640 0x000 0x3 0x0
+-#define MX6DL_PAD_KEY_ROW0__UART4_RX_DATA          0x258 0x640 0x914 0x4 0x3
+-#define MX6DL_PAD_KEY_ROW0__UART4_TX_DATA          0x258 0x640 0x000 0x4 0x0
+-#define MX6DL_PAD_KEY_ROW0__GPIO4_IO07             0x258 0x640 0x000 0x5 0x0
+-#define MX6DL_PAD_KEY_ROW0__DCIC2_OUT              0x258 0x640 0x000 0x6 0x0
+-#define MX6DL_PAD_KEY_ROW1__ECSPI1_SS0             0x25c 0x644 0x7e4 0x0 0x3
+-#define MX6DL_PAD_KEY_ROW1__ENET_COL               0x25c 0x644 0x000 0x1 0x0
+-#define MX6DL_PAD_KEY_ROW1__AUD5_RXD               0x25c 0x644 0x7b0 0x2 0x1
+-#define MX6DL_PAD_KEY_ROW1__KEY_ROW1               0x25c 0x644 0x000 0x3 0x0
+-#define MX6DL_PAD_KEY_ROW1__UART5_RX_DATA          0x25c 0x644 0x91c 0x4 0x3
+-#define MX6DL_PAD_KEY_ROW1__UART5_TX_DATA          0x25c 0x644 0x000 0x4 0x0
+-#define MX6DL_PAD_KEY_ROW1__GPIO4_IO09             0x25c 0x644 0x000 0x5 0x0
+-#define MX6DL_PAD_KEY_ROW1__SD2_VSELECT            0x25c 0x644 0x000 0x6 0x0
+-#define MX6DL_PAD_KEY_ROW2__ECSPI1_SS2             0x260 0x648 0x7ec 0x0 0x1
+-#define MX6DL_PAD_KEY_ROW2__ENET_TX_DATA2          0x260 0x648 0x000 0x1 0x0
+-#define MX6DL_PAD_KEY_ROW2__FLEXCAN1_RX            0x260 0x648 0x7c8 0x2 0x1
+-#define MX6DL_PAD_KEY_ROW2__KEY_ROW2               0x260 0x648 0x000 0x3 0x0
+-#define MX6DL_PAD_KEY_ROW2__SD2_VSELECT            0x260 0x648 0x000 0x4 0x0
+-#define MX6DL_PAD_KEY_ROW2__GPIO4_IO11             0x260 0x648 0x000 0x5 0x0
+-#define MX6DL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE       0x260 0x648 0x85c 0x6 0x1
+-#define MX6DL_PAD_KEY_ROW3__ASRC_EXT_CLK           0x264 0x64c 0x794 0x1 0x2
+-#define MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA        0x264 0x64c 0x864 0x2 0x1
+-#define MX6DL_PAD_KEY_ROW3__KEY_ROW3               0x264 0x64c 0x000 0x3 0x0
+-#define MX6DL_PAD_KEY_ROW3__I2C2_SDA               0x264 0x64c 0x874 0x4 0x1
+-#define MX6DL_PAD_KEY_ROW3__GPIO4_IO13             0x264 0x64c 0x000 0x5 0x0
+-#define MX6DL_PAD_KEY_ROW3__SD1_VSELECT            0x264 0x64c 0x000 0x6 0x0
+-#define MX6DL_PAD_KEY_ROW4__FLEXCAN2_RX            0x268 0x650 0x7cc 0x0 0x0
+-#define MX6DL_PAD_KEY_ROW4__IPU1_SISG5             0x268 0x650 0x000 0x1 0x0
+-#define MX6DL_PAD_KEY_ROW4__USB_OTG_PWR            0x268 0x650 0x000 0x2 0x0
+-#define MX6DL_PAD_KEY_ROW4__KEY_ROW4               0x268 0x650 0x000 0x3 0x0
+-#define MX6DL_PAD_KEY_ROW4__UART5_CTS_B            0x268 0x650 0x000 0x4 0x0
+-#define MX6DL_PAD_KEY_ROW4__UART5_RTS_B            0x268 0x650 0x918 0x4 0x3
+-#define MX6DL_PAD_KEY_ROW4__GPIO4_IO15             0x268 0x650 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_ALE__NAND_ALE              0x26c 0x654 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_ALE__SD4_RESET             0x26c 0x654 0x000 0x1 0x0
+-#define MX6DL_PAD_NANDF_ALE__GPIO6_IO08            0x26c 0x654 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_CLE__NAND_CLE              0x270 0x658 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_CLE__GPIO6_IO07            0x270 0x658 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_CS0__NAND_CE0_B            0x274 0x65c 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_CS0__GPIO6_IO11            0x274 0x65c 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_CS1__NAND_CE1_B            0x278 0x660 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_CS1__SD4_VSELECT           0x278 0x660 0x000 0x1 0x0
+-#define MX6DL_PAD_NANDF_CS1__SD3_VSELECT           0x278 0x660 0x000 0x2 0x0
+-#define MX6DL_PAD_NANDF_CS1__GPIO6_IO14            0x278 0x660 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_CS2__NAND_CE2_B            0x27c 0x664 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_CS2__IPU1_SISG0            0x27c 0x664 0x000 0x1 0x0
+-#define MX6DL_PAD_NANDF_CS2__ESAI_TX0              0x27c 0x664 0x844 0x2 0x1
+-#define MX6DL_PAD_NANDF_CS2__EIM_CRE               0x27c 0x664 0x000 0x3 0x0
+-#define MX6DL_PAD_NANDF_CS2__CCM_CLKO2             0x27c 0x664 0x000 0x4 0x0
+-#define MX6DL_PAD_NANDF_CS2__GPIO6_IO15            0x27c 0x664 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_CS3__NAND_CE3_B            0x280 0x668 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_CS3__IPU1_SISG1            0x280 0x668 0x000 0x1 0x0
+-#define MX6DL_PAD_NANDF_CS3__ESAI_TX1              0x280 0x668 0x848 0x2 0x1
+-#define MX6DL_PAD_NANDF_CS3__EIM_ADDR26            0x280 0x668 0x000 0x3 0x0
+-#define MX6DL_PAD_NANDF_CS3__GPIO6_IO16            0x280 0x668 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_CS3__I2C4_SDA              0x280 0x668 0x884 0x9 0x2
+-#define MX6DL_PAD_NANDF_D0__NAND_DATA00            0x284 0x66c 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_D0__SD1_DATA4              0x284 0x66c 0x000 0x1 0x0
+-#define MX6DL_PAD_NANDF_D0__GPIO2_IO00             0x284 0x66c 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_D1__NAND_DATA01            0x288 0x670 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_D1__SD1_DATA5              0x288 0x670 0x000 0x1 0x0
+-#define MX6DL_PAD_NANDF_D1__GPIO2_IO01             0x288 0x670 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_D2__NAND_DATA02            0x28c 0x674 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_D2__SD1_DATA6              0x28c 0x674 0x000 0x1 0x0
+-#define MX6DL_PAD_NANDF_D2__GPIO2_IO02             0x28c 0x674 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_D3__NAND_DATA03            0x290 0x678 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_D3__SD1_DATA7              0x290 0x678 0x000 0x1 0x0
+-#define MX6DL_PAD_NANDF_D3__GPIO2_IO03             0x290 0x678 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_D4__NAND_DATA04            0x294 0x67c 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_D4__SD2_DATA4              0x294 0x67c 0x000 0x1 0x0
+-#define MX6DL_PAD_NANDF_D4__GPIO2_IO04             0x294 0x67c 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_D5__NAND_DATA05            0x298 0x680 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_D5__SD2_DATA5              0x298 0x680 0x000 0x1 0x0
+-#define MX6DL_PAD_NANDF_D5__GPIO2_IO05             0x298 0x680 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_D6__NAND_DATA06            0x29c 0x684 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_D6__SD2_DATA6              0x29c 0x684 0x000 0x1 0x0
+-#define MX6DL_PAD_NANDF_D6__GPIO2_IO06             0x29c 0x684 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_D7__NAND_DATA07            0x2a0 0x688 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_D7__SD2_DATA7              0x2a0 0x688 0x000 0x1 0x0
+-#define MX6DL_PAD_NANDF_D7__GPIO2_IO07             0x2a0 0x688 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_RB0__NAND_READY_B          0x2a4 0x68c 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_RB0__GPIO6_IO10            0x2a4 0x68c 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_WP_B__NAND_WP_B            0x2a8 0x690 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_WP_B__GPIO6_IO09           0x2a8 0x690 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_WP_B__I2C4_SCL             0x2a8 0x690 0x880 0x9 0x2
+-#define MX6DL_PAD_RGMII_RD0__HSI_RX_READY          0x2ac 0x694 0x000 0x0 0x0
+-#define MX6DL_PAD_RGMII_RD0__RGMII_RD0             0x2ac 0x694 0x818 0x1 0x1
+-#define MX6DL_PAD_RGMII_RD0__GPIO6_IO25            0x2ac 0x694 0x000 0x5 0x0
+-#define MX6DL_PAD_RGMII_RD1__HSI_TX_FLAG           0x2b0 0x698 0x000 0x0 0x0
+-#define MX6DL_PAD_RGMII_RD1__RGMII_RD1             0x2b0 0x698 0x81c 0x1 0x1
+-#define MX6DL_PAD_RGMII_RD1__GPIO6_IO27            0x2b0 0x698 0x000 0x5 0x0
+-#define MX6DL_PAD_RGMII_RD2__HSI_TX_DATA           0x2b4 0x69c 0x000 0x0 0x0
+-#define MX6DL_PAD_RGMII_RD2__RGMII_RD2             0x2b4 0x69c 0x820 0x1 0x1
+-#define MX6DL_PAD_RGMII_RD2__GPIO6_IO28            0x2b4 0x69c 0x000 0x5 0x0
+-#define MX6DL_PAD_RGMII_RD3__HSI_TX_WAKE           0x2b8 0x6a0 0x000 0x0 0x0
+-#define MX6DL_PAD_RGMII_RD3__RGMII_RD3             0x2b8 0x6a0 0x824 0x1 0x1
+-#define MX6DL_PAD_RGMII_RD3__GPIO6_IO29            0x2b8 0x6a0 0x000 0x5 0x0
+-#define MX6DL_PAD_RGMII_RX_CTL__USB_H3_DATA        0x2bc 0x6a4 0x000 0x0 0x0
+-#define MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL       0x2bc 0x6a4 0x828 0x1 0x1
+-#define MX6DL_PAD_RGMII_RX_CTL__GPIO6_IO24         0x2bc 0x6a4 0x000 0x5 0x0
+-#define MX6DL_PAD_RGMII_RXC__USB_H3_STROBE         0x2c0 0x6a8 0x000 0x0 0x0
+-#define MX6DL_PAD_RGMII_RXC__RGMII_RXC             0x2c0 0x6a8 0x814 0x1 0x1
+-#define MX6DL_PAD_RGMII_RXC__GPIO6_IO30            0x2c0 0x6a8 0x000 0x5 0x0
+-#define MX6DL_PAD_RGMII_TD0__HSI_TX_READY          0x2c4 0x6ac 0x000 0x0 0x0
+-#define MX6DL_PAD_RGMII_TD0__RGMII_TD0             0x2c4 0x6ac 0x000 0x1 0x0
+-#define MX6DL_PAD_RGMII_TD0__GPIO6_IO20            0x2c4 0x6ac 0x000 0x5 0x0
+-#define MX6DL_PAD_RGMII_TD1__HSI_RX_FLAG           0x2c8 0x6b0 0x000 0x0 0x0
+-#define MX6DL_PAD_RGMII_TD1__RGMII_TD1             0x2c8 0x6b0 0x000 0x1 0x0
+-#define MX6DL_PAD_RGMII_TD1__GPIO6_IO21            0x2c8 0x6b0 0x000 0x5 0x0
+-#define MX6DL_PAD_RGMII_TD2__HSI_RX_DATA           0x2cc 0x6b4 0x000 0x0 0x0
+-#define MX6DL_PAD_RGMII_TD2__RGMII_TD2             0x2cc 0x6b4 0x000 0x1 0x0
+-#define MX6DL_PAD_RGMII_TD2__GPIO6_IO22            0x2cc 0x6b4 0x000 0x5 0x0
+-#define MX6DL_PAD_RGMII_TD3__HSI_RX_WAKE           0x2d0 0x6b8 0x000 0x0 0x0
+-#define MX6DL_PAD_RGMII_TD3__RGMII_TD3             0x2d0 0x6b8 0x000 0x1 0x0
+-#define MX6DL_PAD_RGMII_TD3__GPIO6_IO23            0x2d0 0x6b8 0x000 0x5 0x0
+-#define MX6DL_PAD_RGMII_TX_CTL__USB_H2_STROBE      0x2d4 0x6bc 0x000 0x0 0x0
+-#define MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL       0x2d4 0x6bc 0x000 0x1 0x0
+-#define MX6DL_PAD_RGMII_TX_CTL__GPIO6_IO26         0x2d4 0x6bc 0x000 0x5 0x0
+-#define MX6DL_PAD_RGMII_TX_CTL__ENET_REF_CLK       0x2d4 0x6bc 0x80c 0x7 0x1
+-#define MX6DL_PAD_RGMII_TXC__USB_H2_DATA           0x2d8 0x6c0 0x000 0x0 0x0
+-#define MX6DL_PAD_RGMII_TXC__RGMII_TXC             0x2d8 0x6c0 0x000 0x1 0x0
+-#define MX6DL_PAD_RGMII_TXC__SPDIF_EXT_CLK         0x2d8 0x6c0 0x8f4 0x2 0x1
+-#define MX6DL_PAD_RGMII_TXC__GPIO6_IO19            0x2d8 0x6c0 0x000 0x5 0x0
+-#define MX6DL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M   0x2d8 0x6c0 0x000 0x7 0x0
+-#define MX6DL_PAD_SD1_CLK__SD1_CLK                 0x2dc 0x6c4 0x928 0x0 0x1
+-#define MX6DL_PAD_SD1_CLK__GPT_CLKIN               0x2dc 0x6c4 0x000 0x3 0x0
+-#define MX6DL_PAD_SD1_CLK__GPIO1_IO20              0x2dc 0x6c4 0x000 0x5 0x0
+-#define MX6DL_PAD_SD1_CMD__SD1_CMD                 0x2e0 0x6c8 0x000 0x0 0x0
+-#define MX6DL_PAD_SD1_CMD__PWM4_OUT                0x2e0 0x6c8 0x000 0x2 0x0
+-#define MX6DL_PAD_SD1_CMD__GPT_COMPARE1            0x2e0 0x6c8 0x000 0x3 0x0
+-#define MX6DL_PAD_SD1_CMD__GPIO1_IO18              0x2e0 0x6c8 0x000 0x5 0x0
+-#define MX6DL_PAD_SD1_DAT0__SD1_DATA0              0x2e4 0x6cc 0x000 0x0 0x0
+-#define MX6DL_PAD_SD1_DAT0__GPT_CAPTURE1           0x2e4 0x6cc 0x000 0x3 0x0
+-#define MX6DL_PAD_SD1_DAT0__GPIO1_IO16             0x2e4 0x6cc 0x000 0x5 0x0
+-#define MX6DL_PAD_SD1_DAT1__SD1_DATA1              0x2e8 0x6d0 0x000 0x0 0x0
+-#define MX6DL_PAD_SD1_DAT1__PWM3_OUT               0x2e8 0x6d0 0x000 0x2 0x0
+-#define MX6DL_PAD_SD1_DAT1__GPT_CAPTURE2           0x2e8 0x6d0 0x000 0x3 0x0
+-#define MX6DL_PAD_SD1_DAT1__GPIO1_IO17             0x2e8 0x6d0 0x000 0x5 0x0
+-#define MX6DL_PAD_SD1_DAT2__SD1_DATA2              0x2ec 0x6d4 0x000 0x0 0x0
+-#define MX6DL_PAD_SD1_DAT2__GPT_COMPARE2           0x2ec 0x6d4 0x000 0x2 0x0
+-#define MX6DL_PAD_SD1_DAT2__PWM2_OUT               0x2ec 0x6d4 0x000 0x3 0x0
+-#define MX6DL_PAD_SD1_DAT2__WDOG1_B                0x2ec 0x6d4 0x000 0x4 0x0
+-#define MX6DL_PAD_SD1_DAT2__GPIO1_IO19             0x2ec 0x6d4 0x000 0x5 0x0
+-#define MX6DL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB      0x2ec 0x6d4 0x000 0x6 0x0
+-#define MX6DL_PAD_SD1_DAT3__SD1_DATA3              0x2f0 0x6d8 0x000 0x0 0x0
+-#define MX6DL_PAD_SD1_DAT3__GPT_COMPARE3           0x2f0 0x6d8 0x000 0x2 0x0
+-#define MX6DL_PAD_SD1_DAT3__PWM1_OUT               0x2f0 0x6d8 0x000 0x3 0x0
+-#define MX6DL_PAD_SD1_DAT3__WDOG2_B                0x2f0 0x6d8 0x000 0x4 0x0
+-#define MX6DL_PAD_SD1_DAT3__GPIO1_IO21             0x2f0 0x6d8 0x000 0x5 0x0
+-#define MX6DL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB      0x2f0 0x6d8 0x000 0x6 0x0
+-#define MX6DL_PAD_SD2_CLK__SD2_CLK                 0x2f4 0x6dc 0x930 0x0 0x1
+-#define MX6DL_PAD_SD2_CLK__KEY_COL5                0x2f4 0x6dc 0x8c0 0x2 0x3
+-#define MX6DL_PAD_SD2_CLK__AUD4_RXFS               0x2f4 0x6dc 0x7a4 0x3 0x1
+-#define MX6DL_PAD_SD2_CLK__GPIO1_IO10              0x2f4 0x6dc 0x000 0x5 0x0
+-#define MX6DL_PAD_SD2_CMD__SD2_CMD                 0x2f8 0x6e0 0x000 0x0 0x0
+-#define MX6DL_PAD_SD2_CMD__KEY_ROW5                0x2f8 0x6e0 0x8cc 0x2 0x2
+-#define MX6DL_PAD_SD2_CMD__AUD4_RXC                0x2f8 0x6e0 0x7a0 0x3 0x1
+-#define MX6DL_PAD_SD2_CMD__GPIO1_IO11              0x2f8 0x6e0 0x000 0x5 0x0
+-#define MX6DL_PAD_SD2_DAT0__SD2_DATA0              0x2fc 0x6e4 0x000 0x0 0x0
+-#define MX6DL_PAD_SD2_DAT0__AUD4_RXD               0x2fc 0x6e4 0x798 0x3 0x1
+-#define MX6DL_PAD_SD2_DAT0__KEY_ROW7               0x2fc 0x6e4 0x8d4 0x4 0x2
+-#define MX6DL_PAD_SD2_DAT0__GPIO1_IO15             0x2fc 0x6e4 0x000 0x5 0x0
+-#define MX6DL_PAD_SD2_DAT0__DCIC2_OUT              0x2fc 0x6e4 0x000 0x6 0x0
+-#define MX6DL_PAD_SD2_DAT1__SD2_DATA1              0x300 0x6e8 0x000 0x0 0x0
+-#define MX6DL_PAD_SD2_DAT1__EIM_CS2_B              0x300 0x6e8 0x000 0x2 0x0
+-#define MX6DL_PAD_SD2_DAT1__AUD4_TXFS              0x300 0x6e8 0x7ac 0x3 0x1
+-#define MX6DL_PAD_SD2_DAT1__KEY_COL7               0x300 0x6e8 0x8c8 0x4 0x2
+-#define MX6DL_PAD_SD2_DAT1__GPIO1_IO14             0x300 0x6e8 0x000 0x5 0x0
+-#define MX6DL_PAD_SD2_DAT2__SD2_DATA2              0x304 0x6ec 0x000 0x0 0x0
+-#define MX6DL_PAD_SD2_DAT2__EIM_CS3_B              0x304 0x6ec 0x000 0x2 0x0
+-#define MX6DL_PAD_SD2_DAT2__AUD4_TXD               0x304 0x6ec 0x79c 0x3 0x1
+-#define MX6DL_PAD_SD2_DAT2__KEY_ROW6               0x304 0x6ec 0x8d0 0x4 0x2
+-#define MX6DL_PAD_SD2_DAT2__GPIO1_IO13             0x304 0x6ec 0x000 0x5 0x0
+-#define MX6DL_PAD_SD2_DAT3__SD2_DATA3              0x308 0x6f0 0x000 0x0 0x0
+-#define MX6DL_PAD_SD2_DAT3__KEY_COL6               0x308 0x6f0 0x8c4 0x2 0x2
+-#define MX6DL_PAD_SD2_DAT3__AUD4_TXC               0x308 0x6f0 0x7a8 0x3 0x1
+-#define MX6DL_PAD_SD2_DAT3__GPIO1_IO12             0x308 0x6f0 0x000 0x5 0x0
+-#define MX6DL_PAD_SD3_CLK__SD3_CLK                 0x30c 0x6f4 0x934 0x0 0x1
+-#define MX6DL_PAD_SD3_CLK__UART2_RTS_B             0x30c 0x6f4 0x900 0x1 0x2
+-#define MX6DL_PAD_SD3_CLK__UART2_CTS_B             0x30c 0x6f4 0x000 0x1 0x0
+-#define MX6DL_PAD_SD3_CLK__FLEXCAN1_RX             0x30c 0x6f4 0x7c8 0x2 0x2
+-#define MX6DL_PAD_SD3_CLK__GPIO7_IO03              0x30c 0x6f4 0x000 0x5 0x0
+-#define MX6DL_PAD_SD3_CMD__SD3_CMD                 0x310 0x6f8 0x000 0x0 0x0
+-#define MX6DL_PAD_SD3_CMD__UART2_CTS_B             0x310 0x6f8 0x000 0x1 0x0
+-#define MX6DL_PAD_SD3_CMD__UART2_RTS_B             0x310 0x6f8 0x900 0x1 0x3
+-#define MX6DL_PAD_SD3_CMD__FLEXCAN1_TX             0x310 0x6f8 0x000 0x2 0x0
+-#define MX6DL_PAD_SD3_CMD__GPIO7_IO02              0x310 0x6f8 0x000 0x5 0x0
+-#define MX6DL_PAD_SD3_DAT0__SD3_DATA0              0x314 0x6fc 0x000 0x0 0x0
+-#define MX6DL_PAD_SD3_DAT0__UART1_CTS_B            0x314 0x6fc 0x000 0x1 0x0
+-#define MX6DL_PAD_SD3_DAT0__UART1_RTS_B            0x314 0x6fc 0x8f8 0x1 0x2
+-#define MX6DL_PAD_SD3_DAT0__FLEXCAN2_TX            0x314 0x6fc 0x000 0x2 0x0
+-#define MX6DL_PAD_SD3_DAT0__GPIO7_IO04             0x314 0x6fc 0x000 0x5 0x0
+-#define MX6DL_PAD_SD3_DAT1__SD3_DATA1              0x318 0x700 0x000 0x0 0x0
+-#define MX6DL_PAD_SD3_DAT1__UART1_RTS_B            0x318 0x700 0x8f8 0x1 0x3
+-#define MX6DL_PAD_SD3_DAT1__UART1_CTS_B            0x318 0x700 0x000 0x1 0x0
+-#define MX6DL_PAD_SD3_DAT1__FLEXCAN2_RX            0x318 0x700 0x7cc 0x2 0x1
+-#define MX6DL_PAD_SD3_DAT1__GPIO7_IO05             0x318 0x700 0x000 0x5 0x0
+-#define MX6DL_PAD_SD3_DAT2__SD3_DATA2              0x31c 0x704 0x000 0x0 0x0
+-#define MX6DL_PAD_SD3_DAT2__GPIO7_IO06             0x31c 0x704 0x000 0x5 0x0
+-#define MX6DL_PAD_SD3_DAT3__SD3_DATA3              0x320 0x708 0x000 0x0 0x0
+-#define MX6DL_PAD_SD3_DAT3__UART3_CTS_B            0x320 0x708 0x000 0x1 0x0
+-#define MX6DL_PAD_SD3_DAT3__UART3_RTS_B            0x320 0x708 0x908 0x1 0x4
+-#define MX6DL_PAD_SD3_DAT3__GPIO7_IO07             0x320 0x708 0x000 0x5 0x0
+-#define MX6DL_PAD_SD3_DAT4__SD3_DATA4              0x324 0x70c 0x000 0x0 0x0
+-#define MX6DL_PAD_SD3_DAT4__UART2_RX_DATA          0x324 0x70c 0x904 0x1 0x4
+-#define MX6DL_PAD_SD3_DAT4__UART2_TX_DATA          0x324 0x70c 0x000 0x1 0x0
+-#define MX6DL_PAD_SD3_DAT4__GPIO7_IO01             0x324 0x70c 0x000 0x5 0x0
+-#define MX6DL_PAD_SD3_DAT5__SD3_DATA5              0x328 0x710 0x000 0x0 0x0
+-#define MX6DL_PAD_SD3_DAT5__UART2_TX_DATA          0x328 0x710 0x000 0x1 0x0
+-#define MX6DL_PAD_SD3_DAT5__UART2_RX_DATA          0x328 0x710 0x904 0x1 0x5
+-#define MX6DL_PAD_SD3_DAT5__GPIO7_IO00             0x328 0x710 0x000 0x5 0x0
+-#define MX6DL_PAD_SD3_DAT6__SD3_DATA6              0x32c 0x714 0x000 0x0 0x0
+-#define MX6DL_PAD_SD3_DAT6__UART1_RX_DATA          0x32c 0x714 0x8fc 0x1 0x2
+-#define MX6DL_PAD_SD3_DAT6__UART1_TX_DATA          0x32c 0x714 0x000 0x1 0x0
+-#define MX6DL_PAD_SD3_DAT6__GPIO6_IO18             0x32c 0x714 0x000 0x5 0x0
+-#define MX6DL_PAD_SD3_DAT7__SD3_DATA7              0x330 0x718 0x000 0x0 0x0
+-#define MX6DL_PAD_SD3_DAT7__UART1_TX_DATA          0x330 0x718 0x000 0x1 0x0
+-#define MX6DL_PAD_SD3_DAT7__UART1_RX_DATA          0x330 0x718 0x8fc 0x1 0x3
+-#define MX6DL_PAD_SD3_DAT7__GPIO6_IO17             0x330 0x718 0x000 0x5 0x0
+-#define MX6DL_PAD_SD3_RST__SD3_RESET               0x334 0x71c 0x000 0x0 0x0
+-#define MX6DL_PAD_SD3_RST__UART3_RTS_B             0x334 0x71c 0x908 0x1 0x5
+-#define MX6DL_PAD_SD3_RST__UART3_CTS_B             0x334 0x71c 0x000 0x1 0x0
+-#define MX6DL_PAD_SD3_RST__GPIO7_IO08              0x334 0x71c 0x000 0x5 0x0
+-#define MX6DL_PAD_SD4_CLK__SD4_CLK                 0x338 0x720 0x938 0x0 0x1
+-#define MX6DL_PAD_SD4_CLK__NAND_WE_B               0x338 0x720 0x000 0x1 0x0
+-#define MX6DL_PAD_SD4_CLK__UART3_RX_DATA           0x338 0x720 0x90c 0x2 0x2
+-#define MX6DL_PAD_SD4_CLK__UART3_TX_DATA           0x338 0x720 0x000 0x2 0x0
+-#define MX6DL_PAD_SD4_CLK__GPIO7_IO10              0x338 0x720 0x000 0x5 0x0
+-#define MX6DL_PAD_SD4_CMD__SD4_CMD                 0x33c 0x724 0x000 0x0 0x0
+-#define MX6DL_PAD_SD4_CMD__NAND_RE_B               0x33c 0x724 0x000 0x1 0x0
+-#define MX6DL_PAD_SD4_CMD__UART3_TX_DATA           0x33c 0x724 0x000 0x2 0x0
+-#define MX6DL_PAD_SD4_CMD__UART3_RX_DATA           0x33c 0x724 0x90c 0x2 0x3
+-#define MX6DL_PAD_SD4_CMD__GPIO7_IO09              0x33c 0x724 0x000 0x5 0x0
+-#define MX6DL_PAD_SD4_DAT0__SD4_DATA0              0x340 0x728 0x000 0x1 0x0
+-#define MX6DL_PAD_SD4_DAT0__NAND_DQS               0x340 0x728 0x000 0x2 0x0
+-#define MX6DL_PAD_SD4_DAT0__GPIO2_IO08             0x340 0x728 0x000 0x5 0x0
+-#define MX6DL_PAD_SD4_DAT1__SD4_DATA1              0x344 0x72c 0x000 0x1 0x0
+-#define MX6DL_PAD_SD4_DAT1__PWM3_OUT               0x344 0x72c 0x000 0x2 0x0
+-#define MX6DL_PAD_SD4_DAT1__GPIO2_IO09             0x344 0x72c 0x000 0x5 0x0
+-#define MX6DL_PAD_SD4_DAT2__SD4_DATA2              0x348 0x730 0x000 0x1 0x0
+-#define MX6DL_PAD_SD4_DAT2__PWM4_OUT               0x348 0x730 0x000 0x2 0x0
+-#define MX6DL_PAD_SD4_DAT2__GPIO2_IO10             0x348 0x730 0x000 0x5 0x0
+-#define MX6DL_PAD_SD4_DAT3__SD4_DATA3              0x34c 0x734 0x000 0x1 0x0
+-#define MX6DL_PAD_SD4_DAT3__GPIO2_IO11             0x34c 0x734 0x000 0x5 0x0
+-#define MX6DL_PAD_SD4_DAT4__SD4_DATA4              0x350 0x738 0x000 0x1 0x0
+-#define MX6DL_PAD_SD4_DAT4__UART2_RX_DATA          0x350 0x738 0x904 0x2 0x6
+-#define MX6DL_PAD_SD4_DAT4__UART2_TX_DATA          0x350 0x738 0x000 0x2 0x0
+-#define MX6DL_PAD_SD4_DAT4__GPIO2_IO12             0x350 0x738 0x000 0x5 0x0
+-#define MX6DL_PAD_SD4_DAT5__SD4_DATA5              0x354 0x73c 0x000 0x1 0x0
+-#define MX6DL_PAD_SD4_DAT5__UART2_RTS_B            0x354 0x73c 0x900 0x2 0x4
+-#define MX6DL_PAD_SD4_DAT5__UART2_CTS_B            0x354 0x73c 0x000 0x2 0x0
+-#define MX6DL_PAD_SD4_DAT5__GPIO2_IO13             0x354 0x73c 0x000 0x5 0x0
+-#define MX6DL_PAD_SD4_DAT6__SD4_DATA6              0x358 0x740 0x000 0x1 0x0
+-#define MX6DL_PAD_SD4_DAT6__UART2_CTS_B            0x358 0x740 0x000 0x2 0x0
+-#define MX6DL_PAD_SD4_DAT6__UART2_RTS_B            0x358 0x740 0x900 0x2 0x5
+-#define MX6DL_PAD_SD4_DAT6__GPIO2_IO14             0x358 0x740 0x000 0x5 0x0
+-#define MX6DL_PAD_SD4_DAT7__SD4_DATA7              0x35c 0x744 0x000 0x1 0x0
+-#define MX6DL_PAD_SD4_DAT7__UART2_TX_DATA          0x35c 0x744 0x000 0x2 0x0
+-#define MX6DL_PAD_SD4_DAT7__UART2_RX_DATA          0x35c 0x744 0x904 0x2 0x7
+-#define MX6DL_PAD_SD4_DAT7__GPIO2_IO15             0x35c 0x744 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10     0x04c 0x360 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC             0x04c 0x360 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO          0x04c 0x360 0x7f8 0x2 0x0
++#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA        0x04c 0x360 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA        0x04c 0x360 0x8fc 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28           0x04c 0x360 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07          0x04c 0x360 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11     0x050 0x364 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS            0x050 0x364 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0           0x050 0x364 0x800 0x2 0x0
++#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA        0x050 0x364 0x8fc 0x3 0x1
++#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA        0x050 0x364 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29           0x050 0x364 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08          0x050 0x364 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12     0x054 0x368 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08           0x054 0x368 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA        0x054 0x368 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA        0x054 0x368 0x914 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30           0x054 0x368 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09          0x054 0x368 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13     0x058 0x36c 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09           0x058 0x36c 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA        0x058 0x36c 0x914 0x3 0x1
++#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA        0x058 0x36c 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31           0x058 0x36c 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10          0x058 0x36c 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14     0x05c 0x370 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10           0x05c 0x370 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA        0x05c 0x370 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA        0x05c 0x370 0x91c 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00           0x05c 0x370 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11          0x05c 0x370 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15     0x060 0x374 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11           0x060 0x374 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA        0x060 0x374 0x91c 0x3 0x1
++#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA        0x060 0x374 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01           0x060 0x374 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12          0x060 0x374 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16     0x064 0x378 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12           0x064 0x378 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B          0x064 0x378 0x910 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B          0x064 0x378 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02           0x064 0x378 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13          0x064 0x378 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17     0x068 0x37c 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13           0x068 0x37c 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B          0x068 0x37c 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B          0x068 0x37c 0x910 0x3 0x1
++#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03           0x068 0x37c 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14          0x068 0x37c 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18     0x06c 0x380 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14           0x06c 0x380 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B          0x06c 0x380 0x918 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B          0x06c 0x380 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04           0x06c 0x380 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15          0x06c 0x380 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19     0x070 0x384 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15           0x070 0x384 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B          0x070 0x384 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B          0x070 0x384 0x918 0x3 0x1
++#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05           0x070 0x384 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04      0x074 0x388 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02            0x074 0x388 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK           0x074 0x388 0x7d8 0x2 0x0
++#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5              0x074 0x388 0x8c0 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC              0x074 0x388 0x000 0x4 0x0
++#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22            0x074 0x388 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01           0x074 0x388 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05      0x078 0x38c 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03            0x078 0x38c 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI           0x078 0x38c 0x7e0 0x2 0x0
++#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5              0x078 0x38c 0x8cc 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD              0x078 0x38c 0x000 0x4 0x0
++#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23            0x078 0x38c 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02           0x078 0x38c 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06      0x07c 0x390 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04            0x07c 0x390 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO           0x07c 0x390 0x7dc 0x2 0x0
++#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6              0x07c 0x390 0x8c4 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS             0x07c 0x390 0x000 0x4 0x0
++#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24            0x07c 0x390 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03           0x07c 0x390 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07      0x080 0x394 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05            0x080 0x394 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0            0x080 0x394 0x7e4 0x2 0x0
++#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6              0x080 0x394 0x8d0 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD              0x080 0x394 0x000 0x4 0x0
++#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25            0x080 0x394 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04           0x080 0x394 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08      0x084 0x398 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06            0x084 0x398 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK           0x084 0x398 0x7f4 0x2 0x0
++#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7              0x084 0x398 0x8c8 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA              0x084 0x398 0x86c 0x4 0x0
++#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26            0x084 0x398 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05           0x084 0x398 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09      0x088 0x39c 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07            0x088 0x39c 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI           0x088 0x39c 0x7fc 0x2 0x0
++#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7              0x088 0x39c 0x8d4 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL              0x088 0x39c 0x868 0x4 0x0
++#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27            0x088 0x39c 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06           0x088 0x39c 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN  0x08c 0x3a0 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00         0x08c 0x3a0 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20         0x08c 0x3a0 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK      0x08c 0x3a0 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC       0x090 0x3a4 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1             0x090 0x3a4 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19            0x090 0x3a4 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL         0x090 0x3a4 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK    0x094 0x3a8 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18          0x094 0x3a8 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO          0x094 0x3a8 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC      0x098 0x3ac 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01           0x098 0x3ac 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21           0x098 0x3ac 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00          0x098 0x3ac 0x000 0x7 0x0
++#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK  0x09c 0x3b0 0x000 0x0 0x0
++#define MX6QDL_PAD_DI0_DISP_CLK__LCD_CLK            0x09c 0x3b0 0x000 0x1 0x0
++#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16         0x09c 0x3b0 0x000 0x5 0x0
++#define MX6QDL_PAD_DI0_DISP_CLK__LCD_WR_RWN         0x09c 0x3b0 0x000 0x8 0x0
++#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15        0x0a0 0x3b4 0x000 0x0 0x0
++#define MX6QDL_PAD_DI0_PIN15__LCD_ENABLE            0x0a0 0x3b4 0x000 0x1 0x0
++#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC              0x0a0 0x3b4 0x000 0x2 0x0
++#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17            0x0a0 0x3b4 0x000 0x5 0x0
++#define MX6QDL_PAD_DI0_PIN15__LCD_RD_E              0x0a0 0x3b4 0x000 0x8 0x0
++#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02         0x0a4 0x3b8 0x000 0x0 0x0
++#define MX6QDL_PAD_DI0_PIN2__LCD_HSYNC              0x0a4 0x3b8 0x8d8 0x1 0x0
++#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD               0x0a4 0x3b8 0x000 0x2 0x0
++#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18             0x0a4 0x3b8 0x000 0x5 0x0
++#define MX6QDL_PAD_DI0_PIN2__LCD_RS                 0x0a4 0x3b8 0x000 0x8 0x0
++#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03         0x0a8 0x3bc 0x000 0x0 0x0
++#define MX6QDL_PAD_DI0_PIN3__LCD_VSYNC              0x0a8 0x3bc 0x000 0x1 0x0
++#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS              0x0a8 0x3bc 0x000 0x2 0x0
++#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19             0x0a8 0x3bc 0x000 0x5 0x0
++#define MX6QDL_PAD_DI0_PIN3__LCD_CS                 0x0a8 0x3bc 0x000 0x8 0x0
++#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04         0x0ac 0x3c0 0x000 0x0 0x0
++#define MX6QDL_PAD_DI0_PIN4__LCD_BUSY               0x0ac 0x3c0 0x8d8 0x1 0x1
++#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD               0x0ac 0x3c0 0x000 0x2 0x0
++#define MX6QDL_PAD_DI0_PIN4__SD1_WP                 0x0ac 0x3c0 0x92c 0x3 0x0
++#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20             0x0ac 0x3c0 0x000 0x5 0x0
++#define MX6QDL_PAD_DI0_PIN4__LCD_RESET              0x0ac 0x3c0 0x000 0x8 0x0
++#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00    0x0b0 0x3c4 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT0__LCD_DATA00           0x0b0 0x3c4 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK          0x0b0 0x3c4 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21           0x0b0 0x3c4 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01    0x0b4 0x3c8 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT1__LCD_DATA01           0x0b4 0x3c8 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI          0x0b4 0x3c8 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22           0x0b4 0x3c8 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10   0x0b8 0x3cc 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT10__LCD_DATA10          0x0b8 0x3cc 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31          0x0b8 0x3cc 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11   0x0bc 0x3d0 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT11__LCD_DATA11          0x0bc 0x3d0 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05          0x0bc 0x3d0 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12   0x0c0 0x3d4 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT12__LCD_DATA12          0x0c0 0x3d4 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06          0x0c0 0x3d4 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13   0x0c4 0x3d8 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT13__LCD_DATA13          0x0c4 0x3d8 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS           0x0c4 0x3d8 0x7bc 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07          0x0c4 0x3d8 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14   0x0c8 0x3dc 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT14__LCD_DATA14          0x0c8 0x3dc 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC            0x0c8 0x3dc 0x7b8 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08          0x0c8 0x3dc 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15   0x0cc 0x3e0 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT15__LCD_DATA15          0x0cc 0x3e0 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1          0x0cc 0x3e0 0x7e8 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1          0x0cc 0x3e0 0x804 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09          0x0cc 0x3e0 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16   0x0d0 0x3e4 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT16__LCD_DATA16          0x0d0 0x3e4 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI         0x0d0 0x3e4 0x7fc 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC            0x0d0 0x3e4 0x7c0 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0     0x0d0 0x3e4 0x8e8 0x4 0x0
++#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10          0x0d0 0x3e4 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17   0x0d4 0x3e8 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT17__LCD_DATA17          0x0d4 0x3e8 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO         0x0d4 0x3e8 0x7f8 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD            0x0d4 0x3e8 0x7b4 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1     0x0d4 0x3e8 0x8ec 0x4 0x0
++#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11          0x0d4 0x3e8 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18   0x0d8 0x3ec 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT18__LCD_DATA18          0x0d8 0x3ec 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0          0x0d8 0x3ec 0x800 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS           0x0d8 0x3ec 0x7c4 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS           0x0d8 0x3ec 0x7a4 0x4 0x0
++#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12          0x0d8 0x3ec 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B           0x0d8 0x3ec 0x000 0x7 0x0
++#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19   0x0dc 0x3f0 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT19__LCD_DATA19          0x0dc 0x3f0 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK         0x0dc 0x3f0 0x7f4 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD            0x0dc 0x3f0 0x7b0 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC            0x0dc 0x3f0 0x7a0 0x4 0x0
++#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13          0x0dc 0x3f0 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B           0x0dc 0x3f0 0x000 0x7 0x0
++#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02    0x0e0 0x3f4 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT2__LCD_DATA02           0x0e0 0x3f4 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO          0x0e0 0x3f4 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23           0x0e0 0x3f4 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20   0x0e4 0x3f8 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT20__LCD_DATA20          0x0e4 0x3f8 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK         0x0e4 0x3f8 0x7d8 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC            0x0e4 0x3f8 0x7a8 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14          0x0e4 0x3f8 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21   0x0e8 0x3fc 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT21__LCD_DATA21          0x0e8 0x3fc 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI         0x0e8 0x3fc 0x7e0 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD            0x0e8 0x3fc 0x79c 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15          0x0e8 0x3fc 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22   0x0ec 0x400 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT22__LCD_DATA22          0x0ec 0x400 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO         0x0ec 0x400 0x7dc 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS           0x0ec 0x400 0x7ac 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16          0x0ec 0x400 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23   0x0f0 0x404 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT23__LCD_DATA23          0x0f0 0x404 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0          0x0f0 0x404 0x7e4 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD            0x0f0 0x404 0x798 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17          0x0f0 0x404 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03    0x0f4 0x408 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT3__LCD_DATA03           0x0f4 0x408 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0           0x0f4 0x408 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24           0x0f4 0x408 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04    0x0f8 0x40c 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT4__LCD_DATA04           0x0f8 0x40c 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1           0x0f8 0x40c 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25           0x0f8 0x40c 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05    0x0fc 0x410 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT5__LCD_DATA05           0x0fc 0x410 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2           0x0fc 0x410 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS            0x0fc 0x410 0x000 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26           0x0fc 0x410 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06    0x100 0x414 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT6__LCD_DATA06           0x100 0x414 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3           0x100 0x414 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC             0x100 0x414 0x000 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27           0x100 0x414 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07    0x104 0x418 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT7__LCD_DATA07           0x104 0x418 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY           0x104 0x418 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28           0x104 0x418 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08    0x108 0x41c 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT8__LCD_DATA08           0x108 0x41c 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT             0x108 0x41c 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B              0x108 0x41c 0x000 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29           0x108 0x41c 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09    0x10c 0x420 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT9__LCD_DATA09           0x10c 0x420 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT             0x10c 0x420 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B              0x10c 0x420 0x000 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30           0x10c 0x420 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A16__EIM_ADDR16              0x110 0x4e0 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK       0x110 0x4e0 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK        0x110 0x4e0 0x8b8 0x2 0x0
++#define MX6QDL_PAD_EIM_A16__GPIO2_IO22              0x110 0x4e0 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16          0x110 0x4e0 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A16__EPDC_DATA00             0x110 0x4e0 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_A17__EIM_ADDR17              0x114 0x4e4 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12       0x114 0x4e4 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12        0x114 0x4e4 0x890 0x2 0x0
++#define MX6QDL_PAD_EIM_A17__GPIO2_IO21              0x114 0x4e4 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17          0x114 0x4e4 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A17__EPDC_PWR_STAT           0x114 0x4e4 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_A18__EIM_ADDR18              0x118 0x4e8 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13       0x118 0x4e8 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13        0x118 0x4e8 0x894 0x2 0x0
++#define MX6QDL_PAD_EIM_A18__GPIO2_IO20              0x118 0x4e8 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18          0x118 0x4e8 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A18__EPDC_PWR_CTRL0          0x118 0x4e8 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_A19__EIM_ADDR19              0x11c 0x4ec 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14       0x11c 0x4ec 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14        0x11c 0x4ec 0x898 0x2 0x0
++#define MX6QDL_PAD_EIM_A19__GPIO2_IO19              0x11c 0x4ec 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19          0x11c 0x4ec 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A19__EPDC_PWR_CTRL1          0x11c 0x4ec 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_A20__EIM_ADDR20              0x120 0x4f0 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15       0x120 0x4f0 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15        0x120 0x4f0 0x89c 0x2 0x0
++#define MX6QDL_PAD_EIM_A20__GPIO2_IO18              0x120 0x4f0 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20          0x120 0x4f0 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A20__EPDC_PWR_CTRL2          0x120 0x4f0 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_A21__EIM_ADDR21              0x124 0x4f4 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16       0x124 0x4f4 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16        0x124 0x4f4 0x8a0 0x2 0x0
++#define MX6QDL_PAD_EIM_A21__GPIO2_IO17              0x124 0x4f4 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21          0x124 0x4f4 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A21__EPDC_GDCLK              0x124 0x4f4 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_A22__EIM_ADDR22              0x128 0x4f8 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17       0x128 0x4f8 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17        0x128 0x4f8 0x8a4 0x2 0x0
++#define MX6QDL_PAD_EIM_A22__GPIO2_IO16              0x128 0x4f8 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22          0x128 0x4f8 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A22__EPDC_GDSP               0x128 0x4f8 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_A23__EIM_ADDR23              0x12c 0x4fc 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18       0x12c 0x4fc 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18        0x12c 0x4fc 0x8a8 0x2 0x0
++#define MX6QDL_PAD_EIM_A23__IPU1_SISG3              0x12c 0x4fc 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_A23__GPIO6_IO06              0x12c 0x4fc 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23          0x12c 0x4fc 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A23__EPDC_GDOE               0x12c 0x4fc 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_A24__EIM_ADDR24              0x130 0x500 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19       0x130 0x500 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19        0x130 0x500 0x8ac 0x2 0x0
++#define MX6QDL_PAD_EIM_A24__IPU1_SISG2              0x130 0x500 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_A24__GPIO5_IO04              0x130 0x500 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24          0x130 0x500 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A24__EPDC_GDRL               0x130 0x500 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_A25__EIM_ADDR25              0x134 0x504 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1              0x134 0x504 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY              0x134 0x504 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12          0x134 0x504 0x000 0x3 0x0
++#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS          0x134 0x504 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_A25__GPIO5_IO02              0x134 0x504 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE        0x134 0x504 0x85c 0x6 0x0
++#define MX6QDL_PAD_EIM_A25__EPDC_DATA15             0x134 0x504 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_A25__EIM_ACLK_FREERUN        0x134 0x504 0x000 0x9 0x0
++#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK               0x138 0x508 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16         0x138 0x508 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31             0x138 0x508 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_BCLK__EPDC_SDCE9             0x138 0x508 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B               0x13c 0x50c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05          0x13c 0x50c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK             0x13c 0x50c 0x7f4 0x2 0x2
++#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23              0x13c 0x50c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_CS0__EPDC_DATA06             0x13c 0x50c 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B               0x140 0x510 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06          0x140 0x510 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI             0x140 0x510 0x7fc 0x2 0x2
++#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24              0x140 0x510 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_CS1__EPDC_DATA08             0x140 0x510 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D16__EIM_DATA16              0x144 0x514 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK             0x144 0x514 0x7d8 0x1 0x2
++#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05          0x144 0x514 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18        0x144 0x514 0x8a8 0x3 0x1
++#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA         0x144 0x514 0x864 0x4 0x0
++#define MX6QDL_PAD_EIM_D16__GPIO3_IO16              0x144 0x514 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D16__I2C2_SDA                0x144 0x514 0x874 0x6 0x0
++#define MX6QDL_PAD_EIM_D16__EPDC_DATA10             0x144 0x514 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D17__EIM_DATA17              0x148 0x518 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO             0x148 0x518 0x7dc 0x1 0x2
++#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06          0x148 0x518 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK        0x148 0x518 0x8b8 0x3 0x1
++#define MX6QDL_PAD_EIM_D17__DCIC1_OUT               0x148 0x518 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D17__GPIO3_IO17              0x148 0x518 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D17__I2C3_SCL                0x148 0x518 0x878 0x6 0x0
++#define MX6QDL_PAD_EIM_D17__EPDC_VCOM0              0x148 0x518 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D18__EIM_DATA18              0x14c 0x51c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI             0x14c 0x51c 0x7e0 0x1 0x2
++#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07          0x14c 0x51c 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17        0x14c 0x51c 0x8a4 0x3 0x1
++#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS          0x14c 0x51c 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D18__GPIO3_IO18              0x14c 0x51c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D18__I2C3_SDA                0x14c 0x51c 0x87c 0x6 0x0
++#define MX6QDL_PAD_EIM_D18__EPDC_VCOM1              0x14c 0x51c 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D19__EIM_DATA19              0x150 0x520 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1              0x150 0x520 0x7e8 0x1 0x1
++#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08          0x150 0x520 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16        0x150 0x520 0x8a0 0x3 0x1
++#define MX6QDL_PAD_EIM_D19__UART1_CTS_B             0x150 0x520 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D19__UART1_RTS_B             0x150 0x520 0x8f8 0x4 0x0
++#define MX6QDL_PAD_EIM_D19__GPIO3_IO19              0x150 0x520 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D19__EPIT1_OUT               0x150 0x520 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D19__EPDC_DATA12             0x150 0x520 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D20__EIM_DATA20              0x154 0x524 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0              0x154 0x524 0x808 0x1 0x0
++#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16          0x154 0x524 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15        0x154 0x524 0x89c 0x3 0x1
++#define MX6QDL_PAD_EIM_D20__UART1_RTS_B             0x154 0x524 0x8f8 0x4 0x1
++#define MX6QDL_PAD_EIM_D20__UART1_CTS_B             0x154 0x524 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D20__GPIO3_IO20              0x154 0x524 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D20__EPIT2_OUT               0x154 0x524 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D21__EIM_DATA21              0x158 0x528 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK             0x158 0x528 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17          0x158 0x528 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D21__IPU1_CSI1_DATA11        0x158 0x528 0x88c 0x3 0x0
++#define MX6QDL_PAD_EIM_D21__USB_OTG_OC              0x158 0x528 0x920 0x4 0x0
++#define MX6QDL_PAD_EIM_D21__GPIO3_IO21              0x158 0x528 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D21__I2C1_SCL                0x158 0x528 0x868 0x6 0x1
++#define MX6QDL_PAD_EIM_D21__SPDIF_IN                0x158 0x528 0x8f0 0x7 0x0
++#define MX6QDL_PAD_EIM_D22__EIM_DATA22              0x15c 0x52c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO             0x15c 0x52c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01          0x15c 0x52c 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D22__IPU1_CSI1_DATA10        0x15c 0x52c 0x888 0x3 0x0
++#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR             0x15c 0x52c 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D22__GPIO3_IO22              0x15c 0x52c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D22__SPDIF_OUT               0x15c 0x52c 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D22__EPDC_SDCE6              0x15c 0x52c 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D23__EIM_DATA23              0x160 0x530 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS          0x160 0x530 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D23__UART3_CTS_B             0x160 0x530 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D23__UART3_RTS_B             0x160 0x530 0x908 0x2 0x0
++#define MX6QDL_PAD_EIM_D23__UART1_DCD_B             0x160 0x530 0x000 0x3 0x0
++#define MX6QDL_PAD_EIM_D23__IPU1_CSI1_DATA_EN       0x160 0x530 0x8b0 0x4 0x0
++#define MX6QDL_PAD_EIM_D23__GPIO3_IO23              0x160 0x530 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02          0x160 0x530 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14          0x160 0x530 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D23__EPDC_DATA11             0x160 0x530 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D24__EIM_DATA24              0x164 0x534 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2              0x164 0x534 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA           0x164 0x534 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA           0x164 0x534 0x90c 0x2 0x0
++#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2              0x164 0x534 0x7ec 0x3 0x0
++#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2              0x164 0x534 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D24__GPIO3_IO24              0x164 0x534 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D24__AUD5_RXFS               0x164 0x534 0x7bc 0x6 0x1
++#define MX6QDL_PAD_EIM_D24__UART1_DTR_B             0x164 0x534 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D24__EPDC_SDCE7              0x164 0x534 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D25__EIM_DATA25              0x168 0x538 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3              0x168 0x538 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA           0x168 0x538 0x90c 0x2 0x1
++#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA           0x168 0x538 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3              0x168 0x538 0x7f0 0x3 0x0
++#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3              0x168 0x538 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D25__GPIO3_IO25              0x168 0x538 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D25__AUD5_RXC                0x168 0x538 0x7b8 0x6 0x1
++#define MX6QDL_PAD_EIM_D25__UART1_DSR_B             0x168 0x538 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D25__EPDC_SDCE8              0x168 0x538 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D26__EIM_DATA26              0x16c 0x53c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11          0x16c 0x53c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01        0x16c 0x53c 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14        0x16c 0x53c 0x898 0x3 0x1
++#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA           0x16c 0x53c 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA           0x16c 0x53c 0x904 0x4 0x0
++#define MX6QDL_PAD_EIM_D26__GPIO3_IO26              0x16c 0x53c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D26__IPU1_SISG2              0x16c 0x53c 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22       0x16c 0x53c 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D26__EPDC_SDOED              0x16c 0x53c 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D27__EIM_DATA27              0x170 0x540 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13          0x170 0x540 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00        0x170 0x540 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13        0x170 0x540 0x894 0x3 0x1
++#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA           0x170 0x540 0x904 0x4 0x1
++#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA           0x170 0x540 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D27__GPIO3_IO27              0x170 0x540 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D27__IPU1_SISG3              0x170 0x540 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23       0x170 0x540 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D27__EPDC_SDOE               0x170 0x540 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D28__EIM_DATA28              0x174 0x544 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D28__I2C1_SDA                0x174 0x544 0x86c 0x1 0x1
++#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI             0x174 0x544 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D28__IPU1_CSI1_DATA12        0x174 0x544 0x890 0x3 0x1
++#define MX6QDL_PAD_EIM_D28__UART2_CTS_B             0x174 0x544 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D28__UART2_RTS_B             0x174 0x544 0x900 0x4 0x0
++#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B         0x174 0x544 0x900 0x4 0x0
++#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B         0x174 0x544 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D28__GPIO3_IO28              0x174 0x544 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG           0x174 0x544 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13          0x174 0x544 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D28__EPDC_PWR_CTRL3          0x174 0x544 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D29__EIM_DATA29              0x178 0x548 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15          0x178 0x548 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0              0x178 0x548 0x808 0x2 0x1
++#define MX6QDL_PAD_EIM_D29__UART2_RTS_B             0x178 0x548 0x900 0x4 0x1
++#define MX6QDL_PAD_EIM_D29__UART2_CTS_B             0x178 0x548 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B         0x178 0x548 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B         0x178 0x548 0x900 0x4 0x1
++#define MX6QDL_PAD_EIM_D29__GPIO3_IO29              0x178 0x548 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC         0x178 0x548 0x8bc 0x6 0x0
++#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14          0x178 0x548 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D29__EPDC_PWR_WAKE           0x178 0x548 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D30__EIM_DATA30              0x17c 0x54c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21       0x17c 0x54c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11          0x17c 0x54c 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03        0x17c 0x54c 0x000 0x3 0x0
++#define MX6QDL_PAD_EIM_D30__UART3_CTS_B             0x17c 0x54c 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D30__UART3_RTS_B             0x17c 0x54c 0x908 0x4 0x1
++#define MX6QDL_PAD_EIM_D30__GPIO3_IO30              0x17c 0x54c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D30__USB_H1_OC               0x17c 0x54c 0x924 0x6 0x0
++#define MX6QDL_PAD_EIM_D30__EPDC_SDOEZ              0x17c 0x54c 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D31__EIM_DATA31              0x180 0x550 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20       0x180 0x550 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12          0x180 0x550 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02        0x180 0x550 0x000 0x3 0x0
++#define MX6QDL_PAD_EIM_D31__UART3_RTS_B             0x180 0x550 0x908 0x4 0x2
++#define MX6QDL_PAD_EIM_D31__UART3_CTS_B             0x180 0x550 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D31__GPIO3_IO31              0x180 0x550 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D31__USB_H1_PWR              0x180 0x550 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P            0x180 0x550 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D31__EIM_ACLK_FREERUN        0x180 0x550 0x000 0x9 0x0
++#define MX6QDL_PAD_EIM_DA0__EIM_AD00                0x184 0x554 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09       0x184 0x554 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA0__IPU1_CSI1_DATA09        0x184 0x554 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00              0x184 0x554 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00          0x184 0x554 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA0__EPDC_SDCLK_N            0x184 0x554 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA1__EIM_AD01                0x188 0x558 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08       0x188 0x558 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA1__IPU1_CSI1_DATA08        0x188 0x558 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01              0x188 0x558 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01          0x188 0x558 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA1__EPDC_SDLE               0x188 0x558 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA10__EIM_AD10               0x18c 0x55c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15         0x18c 0x55c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN      0x18c 0x55c 0x8b0 0x2 0x1
++#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10             0x18c 0x55c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10         0x18c 0x55c 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA10__EPDC_DATA01            0x18c 0x55c 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA11__EIM_AD11               0x190 0x560 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02         0x190 0x560 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC        0x190 0x560 0x8b4 0x2 0x0
++#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11             0x190 0x560 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11         0x190 0x560 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA11__EPDC_DATA03            0x190 0x560 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA12__EIM_AD12               0x194 0x564 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03         0x194 0x564 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC        0x194 0x564 0x8bc 0x2 0x1
++#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12             0x194 0x564 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12         0x194 0x564 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA12__EPDC_DATA02            0x194 0x564 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA13__EIM_AD13               0x198 0x568 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS         0x198 0x568 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13             0x198 0x568 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13         0x198 0x568 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA13__EPDC_DATA13            0x198 0x568 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA14__EIM_AD14               0x19c 0x56c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS         0x19c 0x56c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14             0x19c 0x56c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14         0x19c 0x56c 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA14__EPDC_DATA14            0x19c 0x56c 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA15__EIM_AD15               0x1a0 0x570 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01         0x1a0 0x570 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04         0x1a0 0x570 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15             0x1a0 0x570 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15         0x1a0 0x570 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA15__EPDC_DATA09            0x1a0 0x570 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA2__EIM_AD02                0x1a4 0x574 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07       0x1a4 0x574 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA2__IPU1_CSI1_DATA07        0x1a4 0x574 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02              0x1a4 0x574 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02          0x1a4 0x574 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA2__EPDC_BDR0               0x1a4 0x574 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA3__EIM_AD03                0x1a8 0x578 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06       0x1a8 0x578 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA3__IPU1_CSI1_DATA06        0x1a8 0x578 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03              0x1a8 0x578 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03          0x1a8 0x578 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA3__EPDC_BDR1               0x1a8 0x578 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA4__EIM_AD04                0x1ac 0x57c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05       0x1ac 0x57c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA4__IPU1_CSI1_DATA05        0x1ac 0x57c 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04              0x1ac 0x57c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04          0x1ac 0x57c 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA4__EPDC_SDCE0              0x1ac 0x57c 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA5__EIM_AD05                0x1b0 0x580 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04       0x1b0 0x580 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA5__IPU1_CSI1_DATA04        0x1b0 0x580 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05              0x1b0 0x580 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05          0x1b0 0x580 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA5__EPDC_SDCE1              0x1b0 0x580 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA6__EIM_AD06                0x1b4 0x584 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03       0x1b4 0x584 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA6__IPU1_CSI1_DATA03        0x1b4 0x584 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06              0x1b4 0x584 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06          0x1b4 0x584 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA6__EPDC_SDCE2              0x1b4 0x584 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA7__EIM_AD07                0x1b8 0x588 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02       0x1b8 0x588 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA7__IPU1_CSI1_DATA02        0x1b8 0x588 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07              0x1b8 0x588 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07          0x1b8 0x588 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA7__EPDC_SDCE3              0x1b8 0x588 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA8__EIM_AD08                0x1bc 0x58c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01       0x1bc 0x58c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA8__IPU1_CSI1_DATA01        0x1bc 0x58c 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08              0x1bc 0x58c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08          0x1bc 0x58c 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA8__EPDC_SDCE4              0x1bc 0x58c 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA9__EIM_AD09                0x1c0 0x590 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00       0x1c0 0x590 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA9__IPU1_CSI1_DATA00        0x1c0 0x590 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09              0x1c0 0x590 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09          0x1c0 0x590 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA9__EPDC_SDCE5              0x1c0 0x590 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B               0x1c4 0x594 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11       0x1c4 0x594 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_EB0__IPU1_CSI1_DATA11        0x1c4 0x594 0x88c 0x2 0x1
++#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY          0x1c4 0x594 0x7d4 0x4 0x0
++#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28              0x1c4 0x594 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27          0x1c4 0x594 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_EB0__EPDC_PWR_COM            0x1c4 0x594 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B               0x1c8 0x598 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10       0x1c8 0x598 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_EB1__IPU1_CSI1_DATA10        0x1c8 0x598 0x888 0x2 0x1
++#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29              0x1c8 0x598 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28          0x1c8 0x598 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_EB1__EPDC_SDSHR              0x1c8 0x598 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B               0x1cc 0x59c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0              0x1cc 0x59c 0x7e4 0x1 0x2
++#define MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19        0x1cc 0x59c 0x8ac 0x3 0x1
++#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL         0x1cc 0x59c 0x860 0x4 0x0
++#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30              0x1cc 0x59c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_EB2__I2C2_SCL                0x1cc 0x59c 0x870 0x6 0x0
++#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30          0x1cc 0x59c 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_EB2__EPDC_DATA05             0x1cc 0x59c 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B               0x1d0 0x5a0 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY              0x1d0 0x5a0 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B             0x1d0 0x5a0 0x908 0x2 0x3
++#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B             0x1d0 0x5a0 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_EB3__UART1_RI_B              0x1d0 0x5a0 0x000 0x3 0x0
++#define MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC         0x1d0 0x5a0 0x8b4 0x4 0x1
++#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31              0x1d0 0x5a0 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03          0x1d0 0x5a0 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31          0x1d0 0x5a0 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_EB3__EPDC_SDCE0              0x1d0 0x5a0 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_EB3__EIM_ACLK_FREERUN        0x1d0 0x5a0 0x000 0x9 0x0
++#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B               0x1d4 0x5a4 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17          0x1d4 0x5a4 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1              0x1d4 0x5a4 0x804 0x2 0x1
++#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27              0x1d4 0x5a4 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26          0x1d4 0x5a4 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_LBA__EPDC_DATA04             0x1d4 0x5a4 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_OE__EIM_OE_B                 0x1d8 0x5a8 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07           0x1d8 0x5a8 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO              0x1d8 0x5a8 0x7f8 0x2 0x2
++#define MX6QDL_PAD_EIM_OE__GPIO2_IO25               0x1d8 0x5a8 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_OE__EPDC_PWR_IRQ             0x1d8 0x5a8 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_RW__EIM_RW                   0x1dc 0x5ac 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08           0x1dc 0x5ac 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0               0x1dc 0x5ac 0x800 0x2 0x2
++#define MX6QDL_PAD_EIM_RW__GPIO2_IO26               0x1dc 0x5ac 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29           0x1dc 0x5ac 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_RW__EPDC_DATA07              0x1dc 0x5ac 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B             0x1e0 0x5b0 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B            0x1e0 0x5b0 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00             0x1e0 0x5b0 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25         0x1e0 0x5b0 0x000 0x7 0x0
++#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN          0x1e4 0x5b4 0x828 0x1 0x0
++#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK         0x1e4 0x5b4 0x840 0x2 0x0
++#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK       0x1e4 0x5b4 0x8f4 0x3 0x0
++#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25          0x1e4 0x5b4 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_MDC__MLB_DATA               0x1e8 0x5b8 0x8e0 0x0 0x0
++#define MX6QDL_PAD_ENET_MDC__ENET_MDC               0x1e8 0x5b8 0x000 0x1 0x0
++#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0           0x1e8 0x5b8 0x858 0x2 0x0
++#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN    0x1e8 0x5b8 0x000 0x4 0x0
++#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31             0x1e8 0x5b8 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO             0x1ec 0x5bc 0x810 0x1 0x0
++#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK           0x1ec 0x5bc 0x83c 0x2 0x0
++#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT  0x1ec 0x5bc 0x000 0x4 0x0
++#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22            0x1ec 0x5bc 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK            0x1ec 0x5bc 0x000 0x6 0x0
++#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK        0x1f0 0x5c0 0x000 0x1 0x0
++#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS         0x1f0 0x5c0 0x82c 0x2 0x0
++#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23         0x1f0 0x5c0 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK       0x1f0 0x5c0 0x000 0x6 0x0
++#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID           0x1f4 0x5c4 0x790 0x0 0x0
++#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER           0x1f4 0x5c4 0x000 0x1 0x0
++#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK       0x1f4 0x5c4 0x834 0x2 0x0
++#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN             0x1f4 0x5c4 0x8f0 0x3 0x1
++#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0
++#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24           0x1f4 0x5c4 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0         0x1f8 0x5c8 0x818 0x1 0x0
++#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK        0x1f8 0x5c8 0x838 0x2 0x0
++#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT             0x1f8 0x5c8 0x000 0x3 0x0
++#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27            0x1f8 0x5c8 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_RXD1__MLB_SIG               0x1fc 0x5cc 0x8e4 0x0 0x0
++#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1         0x1fc 0x5cc 0x81c 0x1 0x0
++#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS            0x1fc 0x5cc 0x830 0x2 0x0
++#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT  0x1fc 0x5cc 0x000 0x4 0x0
++#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26            0x1fc 0x5cc 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN           0x200 0x5d0 0x000 0x1 0x0
++#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2         0x200 0x5d0 0x850 0x2 0x0
++#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28           0x200 0x5d0 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_TX_EN__I2C4_SCL             0x200 0x5d0 0x880 0x9 0x0
++#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0         0x204 0x5d4 0x000 0x1 0x0
++#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1          0x204 0x5d4 0x854 0x2 0x0
++#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30            0x204 0x5d4 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_TXD1__MLB_CLK               0x208 0x5d8 0x8dc 0x0 0x0
++#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1         0x208 0x5d8 0x000 0x1 0x0
++#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3          0x208 0x5d8 0x84c 0x2 0x0
++#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN   0x208 0x5d8 0x000 0x4 0x0
++#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29            0x208 0x5d8 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_TXD1__I2C4_SDA              0x208 0x5d8 0x884 0x9 0x0
++#define MX6QDL_PAD_GPIO_0__CCM_CLKO1                0x20c 0x5dc 0x000 0x0 0x0
++#define MX6QDL_PAD_GPIO_0__KEY_COL5                 0x20c 0x5dc 0x8c0 0x2 0x1
++#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK             0x20c 0x5dc 0x794 0x3 0x0
++#define MX6QDL_PAD_GPIO_0__EPIT1_OUT                0x20c 0x5dc 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_0__GPIO1_IO00               0x20c 0x5dc 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_0__USB_H1_PWR               0x20c 0x5dc 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5               0x20c 0x5dc 0x000 0x7 0x0
++#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK              0x210 0x5e0 0x83c 0x0 0x1
++#define MX6QDL_PAD_GPIO_1__WDOG2_B                  0x210 0x5e0 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_1__KEY_ROW5                 0x210 0x5e0 0x8cc 0x2 0x1
++#define MX6QDL_PAD_GPIO_1__USB_OTG_ID               0x210 0x5e0 0x790 0x3 0x1
++#define MX6QDL_PAD_GPIO_1__PWM2_OUT                 0x210 0x5e0 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_1__GPIO1_IO01               0x210 0x5e0 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_1__SD1_CD_B                 0x210 0x5e0 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2            0x214 0x5e4 0x850 0x0 0x1
++#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN     0x214 0x5e4 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK            0x214 0x5e4 0x80c 0x2 0x0
++#define MX6QDL_PAD_GPIO_16__SD1_LCTL                0x214 0x5e4 0x000 0x3 0x0
++#define MX6QDL_PAD_GPIO_16__SPDIF_IN                0x214 0x5e4 0x8f0 0x4 0x2
++#define MX6QDL_PAD_GPIO_16__GPIO7_IO11              0x214 0x5e4 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_16__I2C3_SDA                0x214 0x5e4 0x87c 0x6 0x1
++#define MX6QDL_PAD_GPIO_16__JTAG_DE_B               0x214 0x5e4 0x000 0x7 0x0
++#define MX6QDL_PAD_GPIO_17__ESAI_TX0                0x218 0x5e8 0x844 0x0 0x0
++#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN     0x218 0x5e8 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY          0x218 0x5e8 0x7d4 0x2 0x1
++#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0         0x218 0x5e8 0x8e8 0x3 0x1
++#define MX6QDL_PAD_GPIO_17__SPDIF_OUT               0x218 0x5e8 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_17__GPIO7_IO12              0x218 0x5e8 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_18__ESAI_TX1                0x21c 0x5ec 0x848 0x0 0x0
++#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK             0x21c 0x5ec 0x814 0x1 0x0
++#define MX6QDL_PAD_GPIO_18__SD3_VSELECT             0x21c 0x5ec 0x000 0x2 0x0
++#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1         0x21c 0x5ec 0x8ec 0x3 0x1
++#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK            0x21c 0x5ec 0x794 0x4 0x1
++#define MX6QDL_PAD_GPIO_18__GPIO7_IO13              0x21c 0x5ec 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL          0x21c 0x5ec 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_19__KEY_COL5                0x220 0x5f0 0x8c0 0x0 0x2
++#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT    0x220 0x5f0 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_19__SPDIF_OUT               0x220 0x5f0 0x000 0x2 0x0
++#define MX6QDL_PAD_GPIO_19__CCM_CLKO1               0x220 0x5f0 0x000 0x3 0x0
++#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY              0x220 0x5f0 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_19__GPIO4_IO05              0x220 0x5f0 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_19__ENET_TX_ER              0x220 0x5f0 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS               0x224 0x5f4 0x830 0x0 0x1
++#define MX6QDL_PAD_GPIO_2__KEY_ROW6                 0x224 0x5f4 0x8d0 0x2 0x1
++#define MX6QDL_PAD_GPIO_2__GPIO1_IO02               0x224 0x5f4 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_2__SD2_WP                   0x224 0x5f4 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_2__MLB_DATA                 0x224 0x5f4 0x8e0 0x7 0x1
++#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK           0x228 0x5f8 0x834 0x0 0x1
++#define MX6QDL_PAD_GPIO_3__I2C3_SCL                 0x228 0x5f8 0x878 0x2 0x1
++#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M      0x228 0x5f8 0x000 0x3 0x0
++#define MX6QDL_PAD_GPIO_3__CCM_CLKO2                0x228 0x5f8 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_3__GPIO1_IO03               0x228 0x5f8 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_3__USB_H1_OC                0x228 0x5f8 0x924 0x6 0x1
++#define MX6QDL_PAD_GPIO_3__MLB_CLK                  0x228 0x5f8 0x8dc 0x7 0x1
++#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK           0x22c 0x5fc 0x838 0x0 0x1
++#define MX6QDL_PAD_GPIO_4__KEY_COL7                 0x22c 0x5fc 0x8c8 0x2 0x1
++#define MX6QDL_PAD_GPIO_4__GPIO1_IO04               0x22c 0x5fc 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_4__SD2_CD_B                 0x22c 0x5fc 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3             0x230 0x600 0x84c 0x0 0x1
++#define MX6QDL_PAD_GPIO_5__KEY_ROW7                 0x230 0x600 0x8d4 0x2 0x1
++#define MX6QDL_PAD_GPIO_5__CCM_CLKO1                0x230 0x600 0x000 0x3 0x0
++#define MX6QDL_PAD_GPIO_5__GPIO1_IO05               0x230 0x600 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_5__I2C3_SCL                 0x230 0x600 0x878 0x6 0x2
++#define MX6QDL_PAD_GPIO_5__ARM_EVENTI               0x230 0x600 0x000 0x7 0x0
++#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK              0x234 0x604 0x840 0x0 0x1
++#define MX6QDL_PAD_GPIO_6__I2C3_SDA                 0x234 0x604 0x87c 0x2 0x2
++#define MX6QDL_PAD_GPIO_6__GPIO1_IO06               0x234 0x604 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_6__SD2_LCTL                 0x234 0x604 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_6__MLB_SIG                  0x234 0x604 0x8e4 0x7 0x1
++#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1             0x238 0x608 0x854 0x0 0x1
++#define MX6QDL_PAD_GPIO_7__EPIT1_OUT                0x238 0x608 0x000 0x2 0x0
++#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX              0x238 0x608 0x000 0x3 0x0
++#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA            0x238 0x608 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA            0x238 0x608 0x904 0x4 0x2
++#define MX6QDL_PAD_GPIO_7__GPIO1_IO07               0x238 0x608 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK               0x238 0x608 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE        0x238 0x608 0x000 0x7 0x0
++#define MX6QDL_PAD_GPIO_7__I2C4_SCL                 0x238 0x608 0x880 0x8 0x1
++#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0             0x23c 0x60c 0x858 0x0 0x1
++#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K      0x23c 0x60c 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_8__EPIT2_OUT                0x23c 0x60c 0x000 0x2 0x0
++#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX              0x23c 0x60c 0x7c8 0x3 0x0
++#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA            0x23c 0x60c 0x904 0x4 0x3
++#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA            0x23c 0x60c 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_8__GPIO1_IO08               0x23c 0x60c 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK             0x23c 0x60c 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE     0x23c 0x60c 0x000 0x7 0x0
++#define MX6QDL_PAD_GPIO_8__I2C4_SDA                 0x23c 0x60c 0x884 0x8 0x1
++#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS               0x240 0x610 0x82c 0x0 0x1
++#define MX6QDL_PAD_GPIO_9__WDOG1_B                  0x240 0x610 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_9__KEY_COL6                 0x240 0x610 0x8c4 0x2 0x1
++#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B             0x240 0x610 0x000 0x3 0x0
++#define MX6QDL_PAD_GPIO_9__PWM1_OUT                 0x240 0x610 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_9__GPIO1_IO09               0x240 0x610 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_9__SD1_WP                   0x240 0x610 0x92c 0x6 0x1
++#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK            0x244 0x62c 0x7d8 0x0 0x3
++#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3          0x244 0x62c 0x824 0x1 0x0
++#define MX6QDL_PAD_KEY_COL0__AUD5_TXC               0x244 0x62c 0x7c0 0x2 0x1
++#define MX6QDL_PAD_KEY_COL0__KEY_COL0               0x244 0x62c 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA          0x244 0x62c 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA          0x244 0x62c 0x914 0x4 0x2
++#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06             0x244 0x62c 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT              0x244 0x62c 0x000 0x6 0x0
++#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO            0x248 0x630 0x7dc 0x0 0x3
++#define MX6QDL_PAD_KEY_COL1__ENET_MDIO              0x248 0x630 0x810 0x1 0x1
++#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS              0x248 0x630 0x7c4 0x2 0x1
++#define MX6QDL_PAD_KEY_COL1__KEY_COL1               0x248 0x630 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA          0x248 0x630 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA          0x248 0x630 0x91c 0x4 0x2
++#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08             0x248 0x630 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT            0x248 0x630 0x000 0x6 0x0
++#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1             0x24c 0x634 0x7e8 0x0 0x2
++#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2          0x24c 0x634 0x820 0x1 0x0
++#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX            0x24c 0x634 0x000 0x2 0x0
++#define MX6QDL_PAD_KEY_COL2__KEY_COL2               0x24c 0x634 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_COL2__ENET_MDC               0x24c 0x634 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10             0x24c 0x634 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE    0x24c 0x634 0x000 0x6 0x0
++#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3             0x250 0x638 0x7f0 0x0 0x1
++#define MX6QDL_PAD_KEY_COL3__ENET_CRS               0x250 0x638 0x000 0x1 0x0
++#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL        0x250 0x638 0x860 0x2 0x1
++#define MX6QDL_PAD_KEY_COL3__KEY_COL3               0x250 0x638 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_COL3__I2C2_SCL               0x250 0x638 0x870 0x4 0x1
++#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12             0x250 0x638 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_COL3__SPDIF_IN               0x250 0x638 0x8f0 0x6 0x3
++#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX            0x254 0x63c 0x000 0x0 0x0
++#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4             0x254 0x63c 0x000 0x1 0x0
++#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC             0x254 0x63c 0x920 0x2 0x1
++#define MX6QDL_PAD_KEY_COL4__KEY_COL4               0x254 0x63c 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B            0x254 0x63c 0x918 0x4 0x2
++#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B            0x254 0x63c 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14             0x254 0x63c 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI            0x258 0x640 0x7e0 0x0 0x3
++#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3          0x258 0x640 0x000 0x1 0x0
++#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD               0x258 0x640 0x7b4 0x2 0x1
++#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0               0x258 0x640 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA          0x258 0x640 0x914 0x4 0x3
++#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA          0x258 0x640 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07             0x258 0x640 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT              0x258 0x640 0x000 0x6 0x0
++#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0             0x25c 0x644 0x7e4 0x0 0x3
++#define MX6QDL_PAD_KEY_ROW1__ENET_COL               0x25c 0x644 0x000 0x1 0x0
++#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD               0x25c 0x644 0x7b0 0x2 0x1
++#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1               0x25c 0x644 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA          0x25c 0x644 0x91c 0x4 0x3
++#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA          0x25c 0x644 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09             0x25c 0x644 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT            0x25c 0x644 0x000 0x6 0x0
++#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2             0x260 0x648 0x7ec 0x0 0x1
++#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2          0x260 0x648 0x000 0x1 0x0
++#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX            0x260 0x648 0x7c8 0x2 0x1
++#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2               0x260 0x648 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT            0x260 0x648 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11             0x260 0x648 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE       0x260 0x648 0x85c 0x6 0x1
++#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK           0x264 0x64c 0x794 0x1 0x2
++#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA        0x264 0x64c 0x864 0x2 0x1
++#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3               0x264 0x64c 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA               0x264 0x64c 0x874 0x4 0x1
++#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13             0x264 0x64c 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT            0x264 0x64c 0x000 0x6 0x0
++#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX            0x268 0x650 0x7cc 0x0 0x0
++#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5             0x268 0x650 0x000 0x1 0x0
++#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR            0x268 0x650 0x000 0x2 0x0
++#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4               0x268 0x650 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B            0x268 0x650 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B            0x268 0x650 0x918 0x4 0x3
++#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15             0x268 0x650 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_ALE__NAND_ALE              0x26c 0x654 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_ALE__SD4_RESET             0x26c 0x654 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08            0x26c 0x654 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_CLE__NAND_CLE              0x270 0x658 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07            0x270 0x658 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B            0x274 0x65c 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11            0x274 0x65c 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B            0x278 0x660 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT           0x278 0x660 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT           0x278 0x660 0x000 0x2 0x0
++#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14            0x278 0x660 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B            0x27c 0x664 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0            0x27c 0x664 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0              0x27c 0x664 0x844 0x2 0x1
++#define MX6QDL_PAD_NANDF_CS2__EIM_CRE               0x27c 0x664 0x000 0x3 0x0
++#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2             0x27c 0x664 0x000 0x4 0x0
++#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15            0x27c 0x664 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B            0x280 0x668 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1            0x280 0x668 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1              0x280 0x668 0x848 0x2 0x1
++#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26            0x280 0x668 0x000 0x3 0x0
++#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16            0x280 0x668 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_CS3__I2C4_SDA              0x280 0x668 0x884 0x9 0x2
++#define MX6QDL_PAD_NANDF_D0__NAND_DATA00            0x284 0x66c 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D0__SD1_DATA4              0x284 0x66c 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00             0x284 0x66c 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D1__NAND_DATA01            0x288 0x670 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D1__SD1_DATA5              0x288 0x670 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01             0x288 0x670 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D2__NAND_DATA02            0x28c 0x674 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D2__SD1_DATA6              0x28c 0x674 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02             0x28c 0x674 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D3__NAND_DATA03            0x290 0x678 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D3__SD1_DATA7              0x290 0x678 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03             0x290 0x678 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D4__NAND_DATA04            0x294 0x67c 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D4__SD2_DATA4              0x294 0x67c 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04             0x294 0x67c 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D5__NAND_DATA05            0x298 0x680 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D5__SD2_DATA5              0x298 0x680 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05             0x298 0x680 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D6__NAND_DATA06            0x29c 0x684 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D6__SD2_DATA6              0x29c 0x684 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06             0x29c 0x684 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D7__NAND_DATA07            0x2a0 0x688 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D7__SD2_DATA7              0x2a0 0x688 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07             0x2a0 0x688 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B          0x2a4 0x68c 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10            0x2a4 0x68c 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B            0x2a8 0x690 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09           0x2a8 0x690 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_WP_B__I2C4_SCL             0x2a8 0x690 0x880 0x9 0x2
++#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY          0x2ac 0x694 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0             0x2ac 0x694 0x818 0x1 0x1
++#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25            0x2ac 0x694 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG           0x2b0 0x698 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1             0x2b0 0x698 0x81c 0x1 0x1
++#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27            0x2b0 0x698 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA           0x2b4 0x69c 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2             0x2b4 0x69c 0x820 0x1 0x1
++#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28            0x2b4 0x69c 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE           0x2b8 0x6a0 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3             0x2b8 0x6a0 0x824 0x1 0x1
++#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29            0x2b8 0x6a0 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA        0x2bc 0x6a4 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL       0x2bc 0x6a4 0x828 0x1 0x1
++#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24         0x2bc 0x6a4 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE         0x2c0 0x6a8 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC             0x2c0 0x6a8 0x814 0x1 0x1
++#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30            0x2c0 0x6a8 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY          0x2c4 0x6ac 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0             0x2c4 0x6ac 0x000 0x1 0x0
++#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20            0x2c4 0x6ac 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG           0x2c8 0x6b0 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1             0x2c8 0x6b0 0x000 0x1 0x0
++#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21            0x2c8 0x6b0 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA           0x2cc 0x6b4 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2             0x2cc 0x6b4 0x000 0x1 0x0
++#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22            0x2cc 0x6b4 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE           0x2d0 0x6b8 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3             0x2d0 0x6b8 0x000 0x1 0x0
++#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23            0x2d0 0x6b8 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE      0x2d4 0x6bc 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL       0x2d4 0x6bc 0x000 0x1 0x0
++#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26         0x2d4 0x6bc 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK       0x2d4 0x6bc 0x80c 0x7 0x1
++#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA           0x2d8 0x6c0 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC             0x2d8 0x6c0 0x000 0x1 0x0
++#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK         0x2d8 0x6c0 0x8f4 0x2 0x1
++#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19            0x2d8 0x6c0 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M   0x2d8 0x6c0 0x000 0x7 0x0
++#define MX6QDL_PAD_SD1_CLK__SD1_CLK                 0x2dc 0x6c4 0x928 0x0 0x1
++#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN               0x2dc 0x6c4 0x000 0x3 0x0
++#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20              0x2dc 0x6c4 0x000 0x5 0x0
++#define MX6QDL_PAD_SD1_CMD__SD1_CMD                 0x2e0 0x6c8 0x000 0x0 0x0
++#define MX6QDL_PAD_SD1_CMD__PWM4_OUT                0x2e0 0x6c8 0x000 0x2 0x0
++#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1            0x2e0 0x6c8 0x000 0x3 0x0
++#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18              0x2e0 0x6c8 0x000 0x5 0x0
++#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0              0x2e4 0x6cc 0x000 0x0 0x0
++#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1           0x2e4 0x6cc 0x000 0x3 0x0
++#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16             0x2e4 0x6cc 0x000 0x5 0x0
++#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1              0x2e8 0x6d0 0x000 0x0 0x0
++#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT               0x2e8 0x6d0 0x000 0x2 0x0
++#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2           0x2e8 0x6d0 0x000 0x3 0x0
++#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17             0x2e8 0x6d0 0x000 0x5 0x0
++#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2              0x2ec 0x6d4 0x000 0x0 0x0
++#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2           0x2ec 0x6d4 0x000 0x2 0x0
++#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT               0x2ec 0x6d4 0x000 0x3 0x0
++#define MX6QDL_PAD_SD1_DAT2__WDOG1_B                0x2ec 0x6d4 0x000 0x4 0x0
++#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19             0x2ec 0x6d4 0x000 0x5 0x0
++#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB      0x2ec 0x6d4 0x000 0x6 0x0
++#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3              0x2f0 0x6d8 0x000 0x0 0x0
++#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3           0x2f0 0x6d8 0x000 0x2 0x0
++#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT               0x2f0 0x6d8 0x000 0x3 0x0
++#define MX6QDL_PAD_SD1_DAT3__WDOG2_B                0x2f0 0x6d8 0x000 0x4 0x0
++#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21             0x2f0 0x6d8 0x000 0x5 0x0
++#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB      0x2f0 0x6d8 0x000 0x6 0x0
++#define MX6QDL_PAD_SD2_CLK__SD2_CLK                 0x2f4 0x6dc 0x930 0x0 0x1
++#define MX6QDL_PAD_SD2_CLK__KEY_COL5                0x2f4 0x6dc 0x8c0 0x2 0x3
++#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS               0x2f4 0x6dc 0x7a4 0x3 0x1
++#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10              0x2f4 0x6dc 0x000 0x5 0x0
++#define MX6QDL_PAD_SD2_CMD__SD2_CMD                 0x2f8 0x6e0 0x000 0x0 0x0
++#define MX6QDL_PAD_SD2_CMD__KEY_ROW5                0x2f8 0x6e0 0x8cc 0x2 0x2
++#define MX6QDL_PAD_SD2_CMD__AUD4_RXC                0x2f8 0x6e0 0x7a0 0x3 0x1
++#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11              0x2f8 0x6e0 0x000 0x5 0x0
++#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0              0x2fc 0x6e4 0x000 0x0 0x0
++#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD               0x2fc 0x6e4 0x798 0x3 0x1
++#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7               0x2fc 0x6e4 0x8d4 0x4 0x2
++#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15             0x2fc 0x6e4 0x000 0x5 0x0
++#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT              0x2fc 0x6e4 0x000 0x6 0x0
++#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1              0x300 0x6e8 0x000 0x0 0x0
++#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B              0x300 0x6e8 0x000 0x2 0x0
++#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS              0x300 0x6e8 0x7ac 0x3 0x1
++#define MX6QDL_PAD_SD2_DAT1__KEY_COL7               0x300 0x6e8 0x8c8 0x4 0x2
++#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14             0x300 0x6e8 0x000 0x5 0x0
++#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2              0x304 0x6ec 0x000 0x0 0x0
++#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B              0x304 0x6ec 0x000 0x2 0x0
++#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD               0x304 0x6ec 0x79c 0x3 0x1
++#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6               0x304 0x6ec 0x8d0 0x4 0x2
++#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13             0x304 0x6ec 0x000 0x5 0x0
++#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3              0x308 0x6f0 0x000 0x0 0x0
++#define MX6QDL_PAD_SD2_DAT3__KEY_COL6               0x308 0x6f0 0x8c4 0x2 0x2
++#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC               0x308 0x6f0 0x7a8 0x3 0x1
++#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12             0x308 0x6f0 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_CLK__SD3_CLK                 0x30c 0x6f4 0x934 0x0 0x1
++#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B             0x30c 0x6f4 0x900 0x1 0x2
++#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B             0x30c 0x6f4 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX             0x30c 0x6f4 0x7c8 0x2 0x2
++#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03              0x30c 0x6f4 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_CMD__SD3_CMD                 0x310 0x6f8 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B             0x310 0x6f8 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B             0x310 0x6f8 0x900 0x1 0x3
++#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX             0x310 0x6f8 0x000 0x2 0x0
++#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02              0x310 0x6f8 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0              0x314 0x6fc 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B            0x314 0x6fc 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B            0x314 0x6fc 0x8f8 0x1 0x2
++#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX            0x314 0x6fc 0x000 0x2 0x0
++#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04             0x314 0x6fc 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1              0x318 0x700 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B            0x318 0x700 0x8f8 0x1 0x3
++#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B            0x318 0x700 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX            0x318 0x700 0x7cc 0x2 0x1
++#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05             0x318 0x700 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2              0x31c 0x704 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06             0x31c 0x704 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3              0x320 0x708 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B            0x320 0x708 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B            0x320 0x708 0x908 0x1 0x4
++#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07             0x320 0x708 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4              0x324 0x70c 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA          0x324 0x70c 0x904 0x1 0x4
++#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA          0x324 0x70c 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01             0x324 0x70c 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5              0x328 0x710 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA          0x328 0x710 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA          0x328 0x710 0x904 0x1 0x5
++#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00             0x328 0x710 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6              0x32c 0x714 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA          0x32c 0x714 0x8fc 0x1 0x2
++#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA          0x32c 0x714 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18             0x32c 0x714 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7              0x330 0x718 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA          0x330 0x718 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA          0x330 0x718 0x8fc 0x1 0x3
++#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17             0x330 0x718 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_RST__SD3_RESET               0x334 0x71c 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_RST__UART3_RTS_B             0x334 0x71c 0x908 0x1 0x5
++#define MX6QDL_PAD_SD3_RST__UART3_CTS_B             0x334 0x71c 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_RST__GPIO7_IO08              0x334 0x71c 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_CLK__SD4_CLK                 0x338 0x720 0x938 0x0 0x1
++#define MX6QDL_PAD_SD4_CLK__NAND_WE_B               0x338 0x720 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA           0x338 0x720 0x90c 0x2 0x2
++#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA           0x338 0x720 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10              0x338 0x720 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_CMD__SD4_CMD                 0x33c 0x724 0x000 0x0 0x0
++#define MX6QDL_PAD_SD4_CMD__NAND_RE_B               0x33c 0x724 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA           0x33c 0x724 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA           0x33c 0x724 0x90c 0x2 0x3
++#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09              0x33c 0x724 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0              0x340 0x728 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT0__NAND_DQS               0x340 0x728 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08             0x340 0x728 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1              0x344 0x72c 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT               0x344 0x72c 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09             0x344 0x72c 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2              0x348 0x730 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT               0x348 0x730 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10             0x348 0x730 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3              0x34c 0x734 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11             0x34c 0x734 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4              0x350 0x738 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA          0x350 0x738 0x904 0x2 0x6
++#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA          0x350 0x738 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12             0x350 0x738 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5              0x354 0x73c 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B            0x354 0x73c 0x900 0x2 0x4
++#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B            0x354 0x73c 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13             0x354 0x73c 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6              0x358 0x740 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B            0x358 0x740 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B            0x358 0x740 0x900 0x2 0x5
++#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14             0x358 0x740 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7              0x35c 0x744 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA          0x35c 0x744 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA          0x35c 0x744 0x904 0x2 0x7
++#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15             0x35c 0x744 0x000 0x5 0x0
+ 
+ #endif /* __DTS_IMX6DL_PINFUNC_H */
+diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts
+index 7adcec3..a6ce7b4 100644
+--- a/arch/arm/boot/dts/imx6dl-sabreauto.dts
++++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts
+@@ -15,17 +15,3 @@
+       model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board";
+       compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
+ };
+-
+-&iomuxc {
+-      pinctrl-names = "default";
+-      pinctrl-0 = <&pinctrl_hog>;
+-
+-      hog {
+-              pinctrl_hog: hoggrp {
+-                      fsl,pins = <
+-                              MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
+-                              MX6DL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
+-                      >;
+-              };
+-      };
+-};
+diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts
+index 7efb05d..1e45f2f 100644
+--- a/arch/arm/boot/dts/imx6dl-sabresd.dts
++++ b/arch/arm/boot/dts/imx6dl-sabresd.dts
+@@ -15,21 +15,3 @@
+       model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
+       compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
+ };
+-
+-&iomuxc {
+-      pinctrl-names = "default";
+-      pinctrl-0 = <&pinctrl_hog>;
+-
+-      hog {
+-              pinctrl_hog: hoggrp {
+-                      fsl,pins = <
+-                              MX6DL_PAD_GPIO_4__GPIO1_IO04   0x80000000
+-                              MX6DL_PAD_GPIO_5__GPIO1_IO05   0x80000000
+-                              MX6DL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
+-                              MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
+-                              MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
+-                              MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
+-                      >;
+-              };
+-      };
+-};
+diff --git a/arch/arm/boot/dts/imx6dl-wandboard.dts b/arch/arm/boot/dts/imx6dl-wandboard.dts
+index bfc59c3..e672891 100644
+--- a/arch/arm/boot/dts/imx6dl-wandboard.dts
++++ b/arch/arm/boot/dts/imx6dl-wandboard.dts
+@@ -10,6 +10,7 @@
+  */
+ /dts-v1/;
+ #include "imx6dl.dtsi"
++#include "imx6qdl-wandboard.dtsi"
+ 
+ / {
+       model = "Wandboard i.MX6 Dual Lite Board";
+@@ -19,26 +20,3 @@
+               reg = <0x10000000 0x40000000>;
+       };
+ };
+-
+-&fec {
+-      pinctrl-names = "default";
+-      pinctrl-0 = <&pinctrl_enet_1>;
+-      phy-mode = "rgmii";
+-      status = "okay";
+-};
+-
+-&uart1 {
+-      pinctrl-names = "default";
+-      pinctrl-0 = <&pinctrl_uart1_1>;
+-      status = "okay";
+-};
+-
+-&usbh1 {
+-      status = "okay";
+-};
+-
+-&usdhc3 {
+-      pinctrl-names = "default";
+-      pinctrl-0 = <&pinctrl_usdhc3_2>;
+-      status = "okay";
+-};
+diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
+index 62dc781..9e8ae11 100644
+--- a/arch/arm/boot/dts/imx6dl.dtsi
++++ b/arch/arm/boot/dts/imx6dl.dtsi
+@@ -8,8 +8,8 @@
+  *
+  */
+ 
+-#include "imx6qdl.dtsi"
+ #include "imx6dl-pinfunc.h"
++#include "imx6qdl.dtsi"
+ 
+ / {
+       cpus {
+@@ -32,126 +32,15 @@
+       };
+ 
+       soc {
++              ocram: sram@00900000 {
++                      compatible = "mmio-sram";
++                      reg = <0x00900000 0x20000>;
++                      clocks = <&clks 142>;
++              };
++
+               aips1: aips-bus@02000000 {
+                       iomuxc: iomuxc@020e0000 {
+                               compatible = "fsl,imx6dl-iomuxc";
+-                              reg = <0x020e0000 0x4000>;
+-
+-                              enet {
+-                                      pinctrl_enet_1: enetgrp-1 {
+-                                              fsl,pins = <
+-                                                      MX6DL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
+-                                                      MX6DL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
+-                                                      MX6DL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+-                                                      MX6DL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+-                                                      MX6DL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+-                                                      MX6DL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+-                                                      MX6DL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+-                                                      MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+-                                                      MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+-                                                      MX6DL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+-                                                      MX6DL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+-                                                      MX6DL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+-                                                      MX6DL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+-                                                      MX6DL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+-                                                      MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+-                                                      MX6DL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
+-                                              >;
+-                                      };
+-
+-                                      pinctrl_enet_2: enetgrp-2 {
+-                                              fsl,pins = <
+-                                                      MX6DL_PAD_KEY_COL1__ENET_MDIO        0x1b0b0
+-                                                      MX6DL_PAD_KEY_COL2__ENET_MDC         0x1b0b0
+-                                                      MX6DL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+-                                                      MX6DL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+-                                                      MX6DL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+-                                                      MX6DL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+-                                                      MX6DL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+-                                                      MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+-                                                      MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+-                                                      MX6DL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+-                                                      MX6DL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+-                                                      MX6DL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+-                                                      MX6DL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+-                                                      MX6DL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+-                                                      MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+-                                              >;
+-                                      };
+-                              };
+-
+-                              uart1 {
+-                                      pinctrl_uart1_1: uart1grp-1 {
+-                                              fsl,pins = <
+-                                                      MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+-                                                      MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+-                                              >;
+-                                      };
+-                              };
+-
+-                              uart4 {
+-                                      pinctrl_uart4_1: uart4grp-1 {
+-                                              fsl,pins = <
+-                                                      MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+-                                                      MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+-                                              >;
+-                                      };
+-                              };
+-
+-                              usbotg {
+-                                      pinctrl_usbotg_2: usbotggrp-2 {
+-                                              fsl,pins = <
+-                                                      MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+-                                              >;
+-                                      };
+-                              };
+-
+-                              usdhc2 {
+-                                      pinctrl_usdhc2_1: usdhc2grp-1 {
+-                                              fsl,pins = <
+-                                                      MX6DL_PAD_SD2_CMD__SD2_CMD    0x17059
+-                                                      MX6DL_PAD_SD2_CLK__SD2_CLK    0x10059
+-                                                      MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+-                                                      MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+-                                                      MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+-                                                      MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+-                                                      MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
+-                                                      MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
+-                                                      MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
+-                                                      MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
+-                                              >;
+-                                      };
+-                              };
+-
+-                              usdhc3 {
+-                                      pinctrl_usdhc3_1: usdhc3grp-1 {
+-                                              fsl,pins = <
+-                                                      MX6DL_PAD_SD3_CMD__SD3_CMD    0x17059
+-                                                      MX6DL_PAD_SD3_CLK__SD3_CLK    0x10059
+-                                                      MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+-                                                      MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+-                                                      MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+-                                                      MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+-                                                      MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+-                                                      MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+-                                                      MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+-                                                      MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+-                                              >;
+-                                      };
+-
+-                                      pinctrl_usdhc3_2: usdhc3grp_2 {
+-                                              fsl,pins = <
+-                                                      MX6DL_PAD_SD3_CMD__SD3_CMD    0x17059
+-                                                      MX6DL_PAD_SD3_CLK__SD3_CLK    0x10059
+-                                                      MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+-                                                      MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+-                                                      MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+-                                                      MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+-                                              >;
+-                                      };
+-                              };
+-
+-
+                       };
+ 
+                       pxp: pxp@020f0000 {
+@@ -182,3 +71,20 @@
+               };
+       };
+ };
++
++&ldb {
++      clocks = <&clks 33>, <&clks 34>,
++               <&clks 39>, <&clks 40>,
++               <&clks 135>, <&clks 136>;
++      clock-names = "di0_pll", "di1_pll",
++                    "di0_sel", "di1_sel",
++                    "di0", "di1";
++
++      lvds-channel@0 {
++              crtcs = <&ipu1 0>, <&ipu1 1>;
++      };
++
++      lvds-channel@1 {
++              crtcs = <&ipu1 0>, <&ipu1 1>;
++      };
++};
+diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
+index 4e54fde..edf1bd9 100644
+--- a/arch/arm/boot/dts/imx6q-arm2.dts
++++ b/arch/arm/boot/dts/imx6q-arm2.dts
+@@ -57,7 +57,7 @@
+       hog {
+               pinctrl_hog: hoggrp {
+                       fsl,pins = <
+-                              MX6Q_PAD_EIM_D25__GPIO3_IO25 0x80000000
++                              MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000
+                       >;
+               };
+       };
+@@ -65,8 +65,8 @@
+       arm2 {
+               pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
+                       fsl,pins = <
+-                              MX6Q_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
+-                              MX6Q_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
++                              MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
++                              MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
+                       >;
+               };
+       };
+@@ -97,6 +97,14 @@
+       status = "okay";
+ };
+ 
++&uart2 {
++      pinctrl-names = "default";
++      pinctrl-0 = <&pinctrl_uart2_2>;
++      fsl,dte-mode;
++      fsl,uart-has-rtscts;
++      status = "okay";
++};
++
+ &uart4 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart4_1>;
+diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h b/arch/arm/boot/dts/imx6q-pinfunc.h
+index faea6e1..9bbe82b 100644
+--- a/arch/arm/boot/dts/imx6q-pinfunc.h
++++ b/arch/arm/boot/dts/imx6q-pinfunc.h
+@@ -14,1028 +14,1032 @@
+  * The pin function ID is a tuple of
+  * <mux_reg conf_reg input_reg mux_mode input_val>
+  */
+-#define MX6Q_PAD_SD2_DAT1__SD2_DATA1              0x04c 0x360 0x000 0x0 0x0
+-#define MX6Q_PAD_SD2_DAT1__ECSPI5_SS0             0x04c 0x360 0x834 0x1 0x0
+-#define MX6Q_PAD_SD2_DAT1__EIM_CS2_B              0x04c 0x360 0x000 0x2 0x0
+-#define MX6Q_PAD_SD2_DAT1__AUD4_TXFS              0x04c 0x360 0x7c8 0x3 0x0
+-#define MX6Q_PAD_SD2_DAT1__KEY_COL7               0x04c 0x360 0x8f0 0x4 0x0
+-#define MX6Q_PAD_SD2_DAT1__GPIO1_IO14             0x04c 0x360 0x000 0x5 0x0
+-#define MX6Q_PAD_SD2_DAT2__SD2_DATA2              0x050 0x364 0x000 0x0 0x0
+-#define MX6Q_PAD_SD2_DAT2__ECSPI5_SS1             0x050 0x364 0x838 0x1 0x0
+-#define MX6Q_PAD_SD2_DAT2__EIM_CS3_B              0x050 0x364 0x000 0x2 0x0
+-#define MX6Q_PAD_SD2_DAT2__AUD4_TXD               0x050 0x364 0x7b8 0x3 0x0
+-#define MX6Q_PAD_SD2_DAT2__KEY_ROW6               0x050 0x364 0x8f8 0x4 0x0
+-#define MX6Q_PAD_SD2_DAT2__GPIO1_IO13             0x050 0x364 0x000 0x5 0x0
+-#define MX6Q_PAD_SD2_DAT0__SD2_DATA0              0x054 0x368 0x000 0x0 0x0
+-#define MX6Q_PAD_SD2_DAT0__ECSPI5_MISO            0x054 0x368 0x82c 0x1 0x0
+-#define MX6Q_PAD_SD2_DAT0__AUD4_RXD               0x054 0x368 0x7b4 0x3 0x0
+-#define MX6Q_PAD_SD2_DAT0__KEY_ROW7               0x054 0x368 0x8fc 0x4 0x0
+-#define MX6Q_PAD_SD2_DAT0__GPIO1_IO15             0x054 0x368 0x000 0x5 0x0
+-#define MX6Q_PAD_SD2_DAT0__DCIC2_OUT              0x054 0x368 0x000 0x6 0x0
+-#define MX6Q_PAD_RGMII_TXC__USB_H2_DATA           0x058 0x36c 0x000 0x0 0x0
+-#define MX6Q_PAD_RGMII_TXC__RGMII_TXC             0x058 0x36c 0x000 0x1 0x0
+-#define MX6Q_PAD_RGMII_TXC__SPDIF_EXT_CLK         0x058 0x36c 0x918 0x2 0x0
+-#define MX6Q_PAD_RGMII_TXC__GPIO6_IO19            0x058 0x36c 0x000 0x5 0x0
+-#define MX6Q_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M   0x058 0x36c 0x000 0x7 0x0
+-#define MX6Q_PAD_RGMII_TD0__HSI_TX_READY          0x05c 0x370 0x000 0x0 0x0
+-#define MX6Q_PAD_RGMII_TD0__RGMII_TD0             0x05c 0x370 0x000 0x1 0x0
+-#define MX6Q_PAD_RGMII_TD0__GPIO6_IO20            0x05c 0x370 0x000 0x5 0x0
+-#define MX6Q_PAD_RGMII_TD1__HSI_RX_FLAG           0x060 0x374 0x000 0x0 0x0
+-#define MX6Q_PAD_RGMII_TD1__RGMII_TD1             0x060 0x374 0x000 0x1 0x0
+-#define MX6Q_PAD_RGMII_TD1__GPIO6_IO21            0x060 0x374 0x000 0x5 0x0
+-#define MX6Q_PAD_RGMII_TD2__HSI_RX_DATA           0x064 0x378 0x000 0x0 0x0
+-#define MX6Q_PAD_RGMII_TD2__RGMII_TD2             0x064 0x378 0x000 0x1 0x0
+-#define MX6Q_PAD_RGMII_TD2__GPIO6_IO22            0x064 0x378 0x000 0x5 0x0
+-#define MX6Q_PAD_RGMII_TD3__HSI_RX_WAKE           0x068 0x37c 0x000 0x0 0x0
+-#define MX6Q_PAD_RGMII_TD3__RGMII_TD3             0x068 0x37c 0x000 0x1 0x0
+-#define MX6Q_PAD_RGMII_TD3__GPIO6_IO23            0x068 0x37c 0x000 0x5 0x0
+-#define MX6Q_PAD_RGMII_RX_CTL__USB_H3_DATA        0x06c 0x380 0x000 0x0 0x0
+-#define MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL       0x06c 0x380 0x858 0x1 0x0
+-#define MX6Q_PAD_RGMII_RX_CTL__GPIO6_IO24         0x06c 0x380 0x000 0x5 0x0
+-#define MX6Q_PAD_RGMII_RD0__HSI_RX_READY          0x070 0x384 0x000 0x0 0x0
+-#define MX6Q_PAD_RGMII_RD0__RGMII_RD0             0x070 0x384 0x848 0x1 0x0
+-#define MX6Q_PAD_RGMII_RD0__GPIO6_IO25            0x070 0x384 0x000 0x5 0x0
+-#define MX6Q_PAD_RGMII_TX_CTL__USB_H2_STROBE      0x074 0x388 0x000 0x0 0x0
+-#define MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL       0x074 0x388 0x000 0x1 0x0
+-#define MX6Q_PAD_RGMII_TX_CTL__GPIO6_IO26         0x074 0x388 0x000 0x5 0x0
+-#define MX6Q_PAD_RGMII_TX_CTL__ENET_REF_CLK       0x074 0x388 0x83c 0x7 0x0
+-#define MX6Q_PAD_RGMII_RD1__HSI_TX_FLAG           0x078 0x38c 0x000 0x0 0x0
+-#define MX6Q_PAD_RGMII_RD1__RGMII_RD1             0x078 0x38c 0x84c 0x1 0x0
+-#define MX6Q_PAD_RGMII_RD1__GPIO6_IO27            0x078 0x38c 0x000 0x5 0x0
+-#define MX6Q_PAD_RGMII_RD2__HSI_TX_DATA           0x07c 0x390 0x000 0x0 0x0
+-#define MX6Q_PAD_RGMII_RD2__RGMII_RD2             0x07c 0x390 0x850 0x1 0x0
+-#define MX6Q_PAD_RGMII_RD2__GPIO6_IO28            0x07c 0x390 0x000 0x5 0x0
+-#define MX6Q_PAD_RGMII_RD3__HSI_TX_WAKE           0x080 0x394 0x000 0x0 0x0
+-#define MX6Q_PAD_RGMII_RD3__RGMII_RD3             0x080 0x394 0x854 0x1 0x0
+-#define MX6Q_PAD_RGMII_RD3__GPIO6_IO29            0x080 0x394 0x000 0x5 0x0
+-#define MX6Q_PAD_RGMII_RXC__USB_H3_STROBE         0x084 0x398 0x000 0x0 0x0
+-#define MX6Q_PAD_RGMII_RXC__RGMII_RXC             0x084 0x398 0x844 0x1 0x0
+-#define MX6Q_PAD_RGMII_RXC__GPIO6_IO30            0x084 0x398 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_A25__EIM_ADDR25              0x088 0x39c 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_A25__ECSPI4_SS1              0x088 0x39c 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_A25__ECSPI2_RDY              0x088 0x39c 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12          0x088 0x39c 0x000 0x3 0x0
+-#define MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS          0x088 0x39c 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_A25__GPIO5_IO02              0x088 0x39c 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE        0x088 0x39c 0x88c 0x6 0x0
+-#define MX6Q_PAD_EIM_EB2__EIM_EB2_B               0x08c 0x3a0 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_EB2__ECSPI1_SS0              0x08c 0x3a0 0x800 0x1 0x0
+-#define MX6Q_PAD_EIM_EB2__IPU2_CSI1_DATA19        0x08c 0x3a0 0x8d4 0x3 0x0
+-#define MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL         0x08c 0x3a0 0x890 0x4 0x0
+-#define MX6Q_PAD_EIM_EB2__GPIO2_IO30              0x08c 0x3a0 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_EB2__I2C2_SCL                0x08c 0x3a0 0x8a0 0x6 0x0
+-#define MX6Q_PAD_EIM_EB2__SRC_BOOT_CFG30          0x08c 0x3a0 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_D16__EIM_DATA16              0x090 0x3a4 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D16__ECSPI1_SCLK             0x090 0x3a4 0x7f4 0x1 0x0
+-#define MX6Q_PAD_EIM_D16__IPU1_DI0_PIN05          0x090 0x3a4 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D16__IPU2_CSI1_DATA18        0x090 0x3a4 0x8d0 0x3 0x0
+-#define MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA         0x090 0x3a4 0x894 0x4 0x0
+-#define MX6Q_PAD_EIM_D16__GPIO3_IO16              0x090 0x3a4 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D16__I2C2_SDA                0x090 0x3a4 0x8a4 0x6 0x0
+-#define MX6Q_PAD_EIM_D17__EIM_DATA17              0x094 0x3a8 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D17__ECSPI1_MISO             0x094 0x3a8 0x7f8 0x1 0x0
+-#define MX6Q_PAD_EIM_D17__IPU1_DI0_PIN06          0x094 0x3a8 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK        0x094 0x3a8 0x8e0 0x3 0x0
+-#define MX6Q_PAD_EIM_D17__DCIC1_OUT               0x094 0x3a8 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D17__GPIO3_IO17              0x094 0x3a8 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D17__I2C3_SCL                0x094 0x3a8 0x8a8 0x6 0x0
+-#define MX6Q_PAD_EIM_D18__EIM_DATA18              0x098 0x3ac 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D18__ECSPI1_MOSI             0x098 0x3ac 0x7fc 0x1 0x0
+-#define MX6Q_PAD_EIM_D18__IPU1_DI0_PIN07          0x098 0x3ac 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D18__IPU2_CSI1_DATA17        0x098 0x3ac 0x8cc 0x3 0x0
+-#define MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS          0x098 0x3ac 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D18__GPIO3_IO18              0x098 0x3ac 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D18__I2C3_SDA                0x098 0x3ac 0x8ac 0x6 0x0
+-#define MX6Q_PAD_EIM_D19__EIM_DATA19              0x09c 0x3b0 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D19__ECSPI1_SS1              0x09c 0x3b0 0x804 0x1 0x0
+-#define MX6Q_PAD_EIM_D19__IPU1_DI0_PIN08          0x09c 0x3b0 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D19__IPU2_CSI1_DATA16        0x09c 0x3b0 0x8c8 0x3 0x0
+-#define MX6Q_PAD_EIM_D19__UART1_CTS_B             0x09c 0x3b0 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D19__UART1_RTS_B             0x09c 0x3b0 0x91c 0x4 0x0
+-#define MX6Q_PAD_EIM_D19__GPIO3_IO19              0x09c 0x3b0 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D19__EPIT1_OUT               0x09c 0x3b0 0x000 0x6 0x0
+-#define MX6Q_PAD_EIM_D20__EIM_DATA20              0x0a0 0x3b4 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D20__ECSPI4_SS0              0x0a0 0x3b4 0x824 0x1 0x0
+-#define MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16          0x0a0 0x3b4 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D20__IPU2_CSI1_DATA15        0x0a0 0x3b4 0x8c4 0x3 0x0
+-#define MX6Q_PAD_EIM_D20__UART1_RTS_B             0x0a0 0x3b4 0x91c 0x4 0x1
+-#define MX6Q_PAD_EIM_D20__UART1_CTS_B             0x0a0 0x3b4 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D20__GPIO3_IO20              0x0a0 0x3b4 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D20__EPIT2_OUT               0x0a0 0x3b4 0x000 0x6 0x0
+-#define MX6Q_PAD_EIM_D21__EIM_DATA21              0x0a4 0x3b8 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D21__ECSPI4_SCLK             0x0a4 0x3b8 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17          0x0a4 0x3b8 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D21__IPU2_CSI1_DATA11        0x0a4 0x3b8 0x8b4 0x3 0x0
+-#define MX6Q_PAD_EIM_D21__USB_OTG_OC              0x0a4 0x3b8 0x944 0x4 0x0
+-#define MX6Q_PAD_EIM_D21__GPIO3_IO21              0x0a4 0x3b8 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D21__I2C1_SCL                0x0a4 0x3b8 0x898 0x6 0x0
+-#define MX6Q_PAD_EIM_D21__SPDIF_IN                0x0a4 0x3b8 0x914 0x7 0x0
+-#define MX6Q_PAD_EIM_D22__EIM_DATA22              0x0a8 0x3bc 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D22__ECSPI4_MISO             0x0a8 0x3bc 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_D22__IPU1_DI0_PIN01          0x0a8 0x3bc 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D22__IPU2_CSI1_DATA10        0x0a8 0x3bc 0x8b0 0x3 0x0
+-#define MX6Q_PAD_EIM_D22__USB_OTG_PWR             0x0a8 0x3bc 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D22__GPIO3_IO22              0x0a8 0x3bc 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D22__SPDIF_OUT               0x0a8 0x3bc 0x000 0x6 0x0
+-#define MX6Q_PAD_EIM_D23__EIM_DATA23              0x0ac 0x3c0 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS          0x0ac 0x3c0 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_D23__UART3_CTS_B             0x0ac 0x3c0 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D23__UART3_RTS_B             0x0ac 0x3c0 0x92c 0x2 0x0
+-#define MX6Q_PAD_EIM_D23__UART1_DCD_B             0x0ac 0x3c0 0x000 0x3 0x0
+-#define MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN       0x0ac 0x3c0 0x8d8 0x4 0x0
+-#define MX6Q_PAD_EIM_D23__GPIO3_IO23              0x0ac 0x3c0 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN02          0x0ac 0x3c0 0x000 0x6 0x0
+-#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14          0x0ac 0x3c0 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_EB3__EIM_EB3_B               0x0b0 0x3c4 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_EB3__ECSPI4_RDY              0x0b0 0x3c4 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_EB3__UART3_RTS_B             0x0b0 0x3c4 0x92c 0x2 0x1
+-#define MX6Q_PAD_EIM_EB3__UART3_CTS_B             0x0b0 0x3c4 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_EB3__UART1_RI_B              0x0b0 0x3c4 0x000 0x3 0x0
+-#define MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC         0x0b0 0x3c4 0x8dc 0x4 0x0
+-#define MX6Q_PAD_EIM_EB3__GPIO2_IO31              0x0b0 0x3c4 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN03          0x0b0 0x3c4 0x000 0x6 0x0
+-#define MX6Q_PAD_EIM_EB3__SRC_BOOT_CFG31          0x0b0 0x3c4 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_D24__EIM_DATA24              0x0b4 0x3c8 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D24__ECSPI4_SS2              0x0b4 0x3c8 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_D24__UART3_TX_DATA           0x0b4 0x3c8 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D24__UART3_RX_DATA           0x0b4 0x3c8 0x930 0x2 0x0
+-#define MX6Q_PAD_EIM_D24__ECSPI1_SS2              0x0b4 0x3c8 0x808 0x3 0x0
+-#define MX6Q_PAD_EIM_D24__ECSPI2_SS2              0x0b4 0x3c8 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D24__GPIO3_IO24              0x0b4 0x3c8 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D24__AUD5_RXFS               0x0b4 0x3c8 0x7d8 0x6 0x0
+-#define MX6Q_PAD_EIM_D24__UART1_DTR_B             0x0b4 0x3c8 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_D25__EIM_DATA25              0x0b8 0x3cc 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D25__ECSPI4_SS3              0x0b8 0x3cc 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_D25__UART3_RX_DATA           0x0b8 0x3cc 0x930 0x2 0x1
+-#define MX6Q_PAD_EIM_D25__UART3_TX_DATA           0x0b8 0x3cc 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D25__ECSPI1_SS3              0x0b8 0x3cc 0x80c 0x3 0x0
+-#define MX6Q_PAD_EIM_D25__ECSPI2_SS3              0x0b8 0x3cc 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D25__GPIO3_IO25              0x0b8 0x3cc 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D25__AUD5_RXC                0x0b8 0x3cc 0x7d4 0x6 0x0
+-#define MX6Q_PAD_EIM_D25__UART1_DSR_B             0x0b8 0x3cc 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_D26__EIM_DATA26              0x0bc 0x3d0 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11          0x0bc 0x3d0 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_D26__IPU1_CSI0_DATA01        0x0bc 0x3d0 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D26__IPU2_CSI1_DATA14        0x0bc 0x3d0 0x8c0 0x3 0x0
+-#define MX6Q_PAD_EIM_D26__UART2_TX_DATA           0x0bc 0x3d0 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D26__UART2_RX_DATA           0x0bc 0x3d0 0x928 0x4 0x0
+-#define MX6Q_PAD_EIM_D26__GPIO3_IO26              0x0bc 0x3d0 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D26__IPU1_SISG2              0x0bc 0x3d0 0x000 0x6 0x0
+-#define MX6Q_PAD_EIM_D26__IPU1_DISP1_DATA22       0x0bc 0x3d0 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_D27__EIM_DATA27              0x0c0 0x3d4 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13          0x0c0 0x3d4 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_D27__IPU1_CSI0_DATA00        0x0c0 0x3d4 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D27__IPU2_CSI1_DATA13        0x0c0 0x3d4 0x8bc 0x3 0x0
+-#define MX6Q_PAD_EIM_D27__UART2_RX_DATA           0x0c0 0x3d4 0x928 0x4 0x1
+-#define MX6Q_PAD_EIM_D27__UART2_TX_DATA           0x0c0 0x3d4 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D27__GPIO3_IO27              0x0c0 0x3d4 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D27__IPU1_SISG3              0x0c0 0x3d4 0x000 0x6 0x0
+-#define MX6Q_PAD_EIM_D27__IPU1_DISP1_DATA23       0x0c0 0x3d4 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_D28__EIM_DATA28              0x0c4 0x3d8 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D28__I2C1_SDA                0x0c4 0x3d8 0x89c 0x1 0x0
+-#define MX6Q_PAD_EIM_D28__ECSPI4_MOSI             0x0c4 0x3d8 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D28__IPU2_CSI1_DATA12        0x0c4 0x3d8 0x8b8 0x3 0x0
+-#define MX6Q_PAD_EIM_D28__UART2_CTS_B             0x0c4 0x3d8 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D28__UART2_RTS_B             0x0c4 0x3d8 0x924 0x4 0x0
+-#define MX6Q_PAD_EIM_D28__GPIO3_IO28              0x0c4 0x3d8 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG           0x0c4 0x3d8 0x000 0x6 0x0
+-#define MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13          0x0c4 0x3d8 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_D29__EIM_DATA29              0x0c8 0x3dc 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15          0x0c8 0x3dc 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_D29__ECSPI4_SS0              0x0c8 0x3dc 0x824 0x2 0x1
+-#define MX6Q_PAD_EIM_D29__UART2_RTS_B             0x0c8 0x3dc 0x924 0x4 0x1
+-#define MX6Q_PAD_EIM_D29__UART2_CTS_B             0x0c8 0x3dc 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D29__GPIO3_IO29              0x0c8 0x3dc 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC         0x0c8 0x3dc 0x8e4 0x6 0x0
+-#define MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14          0x0c8 0x3dc 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_D30__EIM_DATA30              0x0cc 0x3e0 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D30__IPU1_DISP1_DATA21       0x0cc 0x3e0 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11          0x0cc 0x3e0 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D30__IPU1_CSI0_DATA03        0x0cc 0x3e0 0x000 0x3 0x0
+-#define MX6Q_PAD_EIM_D30__UART3_CTS_B             0x0cc 0x3e0 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D30__UART3_RTS_B             0x0cc 0x3e0 0x92c 0x4 0x2
+-#define MX6Q_PAD_EIM_D30__GPIO3_IO30              0x0cc 0x3e0 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D30__USB_H1_OC               0x0cc 0x3e0 0x948 0x6 0x0
+-#define MX6Q_PAD_EIM_D31__EIM_DATA31              0x0d0 0x3e4 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D31__IPU1_DISP1_DATA20       0x0d0 0x3e4 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12          0x0d0 0x3e4 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D31__IPU1_CSI0_DATA02        0x0d0 0x3e4 0x000 0x3 0x0
+-#define MX6Q_PAD_EIM_D31__UART3_RTS_B             0x0d0 0x3e4 0x92c 0x4 0x3
+-#define MX6Q_PAD_EIM_D31__UART3_CTS_B             0x0d0 0x3e4 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D31__GPIO3_IO31              0x0d0 0x3e4 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D31__USB_H1_PWR              0x0d0 0x3e4 0x000 0x6 0x0
+-#define MX6Q_PAD_EIM_A24__EIM_ADDR24              0x0d4 0x3e8 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_A24__IPU1_DISP1_DATA19       0x0d4 0x3e8 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_A24__IPU2_CSI1_DATA19        0x0d4 0x3e8 0x8d4 0x2 0x1
+-#define MX6Q_PAD_EIM_A24__IPU2_SISG2              0x0d4 0x3e8 0x000 0x3 0x0
+-#define MX6Q_PAD_EIM_A24__IPU1_SISG2              0x0d4 0x3e8 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_A24__GPIO5_IO04              0x0d4 0x3e8 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_A24__SRC_BOOT_CFG24          0x0d4 0x3e8 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_A23__EIM_ADDR23              0x0d8 0x3ec 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_A23__IPU1_DISP1_DATA18       0x0d8 0x3ec 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_A23__IPU2_CSI1_DATA18        0x0d8 0x3ec 0x8d0 0x2 0x1
+-#define MX6Q_PAD_EIM_A23__IPU2_SISG3              0x0d8 0x3ec 0x000 0x3 0x0
+-#define MX6Q_PAD_EIM_A23__IPU1_SISG3              0x0d8 0x3ec 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_A23__GPIO6_IO06              0x0d8 0x3ec 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_A23__SRC_BOOT_CFG23          0x0d8 0x3ec 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_A22__EIM_ADDR22              0x0dc 0x3f0 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_A22__IPU1_DISP1_DATA17       0x0dc 0x3f0 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_A22__IPU2_CSI1_DATA17        0x0dc 0x3f0 0x8cc 0x2 0x1
+-#define MX6Q_PAD_EIM_A22__GPIO2_IO16              0x0dc 0x3f0 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_A22__SRC_BOOT_CFG22          0x0dc 0x3f0 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_A21__EIM_ADDR21              0x0e0 0x3f4 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_A21__IPU1_DISP1_DATA16       0x0e0 0x3f4 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_A21__IPU2_CSI1_DATA16        0x0e0 0x3f4 0x8c8 0x2 0x1
+-#define MX6Q_PAD_EIM_A21__GPIO2_IO17              0x0e0 0x3f4 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_A21__SRC_BOOT_CFG21          0x0e0 0x3f4 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_A20__EIM_ADDR20              0x0e4 0x3f8 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_A20__IPU1_DISP1_DATA15       0x0e4 0x3f8 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_A20__IPU2_CSI1_DATA15        0x0e4 0x3f8 0x8c4 0x2 0x1
+-#define MX6Q_PAD_EIM_A20__GPIO2_IO18              0x0e4 0x3f8 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_A20__SRC_BOOT_CFG20          0x0e4 0x3f8 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_A19__EIM_ADDR19              0x0e8 0x3fc 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_A19__IPU1_DISP1_DATA14       0x0e8 0x3fc 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_A19__IPU2_CSI1_DATA14        0x0e8 0x3fc 0x8c0 0x2 0x1
+-#define MX6Q_PAD_EIM_A19__GPIO2_IO19              0x0e8 0x3fc 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_A19__SRC_BOOT_CFG19          0x0e8 0x3fc 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_A18__EIM_ADDR18              0x0ec 0x400 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_A18__IPU1_DISP1_DATA13       0x0ec 0x400 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_A18__IPU2_CSI1_DATA13        0x0ec 0x400 0x8bc 0x2 0x1
+-#define MX6Q_PAD_EIM_A18__GPIO2_IO20              0x0ec 0x400 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_A18__SRC_BOOT_CFG18          0x0ec 0x400 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_A17__EIM_ADDR17              0x0f0 0x404 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_A17__IPU1_DISP1_DATA12       0x0f0 0x404 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_A17__IPU2_CSI1_DATA12        0x0f0 0x404 0x8b8 0x2 0x1
+-#define MX6Q_PAD_EIM_A17__GPIO2_IO21              0x0f0 0x404 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_A17__SRC_BOOT_CFG17          0x0f0 0x404 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_A16__EIM_ADDR16              0x0f4 0x408 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK       0x0f4 0x408 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK        0x0f4 0x408 0x8e0 0x2 0x1
+-#define MX6Q_PAD_EIM_A16__GPIO2_IO22              0x0f4 0x408 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_A16__SRC_BOOT_CFG16          0x0f4 0x408 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_CS0__EIM_CS0_B               0x0f8 0x40c 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN05          0x0f8 0x40c 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_CS0__ECSPI2_SCLK             0x0f8 0x40c 0x810 0x2 0x0
+-#define MX6Q_PAD_EIM_CS0__GPIO2_IO23              0x0f8 0x40c 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_CS1__EIM_CS1_B               0x0fc 0x410 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN06          0x0fc 0x410 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_CS1__ECSPI2_MOSI             0x0fc 0x410 0x818 0x2 0x0
+-#define MX6Q_PAD_EIM_CS1__GPIO2_IO24              0x0fc 0x410 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_OE__EIM_OE_B                 0x100 0x414 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_OE__IPU1_DI1_PIN07           0x100 0x414 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_OE__ECSPI2_MISO              0x100 0x414 0x814 0x2 0x0
+-#define MX6Q_PAD_EIM_OE__GPIO2_IO25               0x100 0x414 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_RW__EIM_RW                   0x104 0x418 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_RW__IPU1_DI1_PIN08           0x104 0x418 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_RW__ECSPI2_SS0               0x104 0x418 0x81c 0x2 0x0
+-#define MX6Q_PAD_EIM_RW__GPIO2_IO26               0x104 0x418 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_RW__SRC_BOOT_CFG29           0x104 0x418 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_LBA__EIM_LBA_B               0x108 0x41c 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17          0x108 0x41c 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_LBA__ECSPI2_SS1              0x108 0x41c 0x820 0x2 0x0
+-#define MX6Q_PAD_EIM_LBA__GPIO2_IO27              0x108 0x41c 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_LBA__SRC_BOOT_CFG26          0x108 0x41c 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_EB0__EIM_EB0_B               0x10c 0x420 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_EB0__IPU1_DISP1_DATA11       0x10c 0x420 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_EB0__IPU2_CSI1_DATA11        0x10c 0x420 0x8b4 0x2 0x1
+-#define MX6Q_PAD_EIM_EB0__CCM_PMIC_READY          0x10c 0x420 0x7f0 0x4 0x0
+-#define MX6Q_PAD_EIM_EB0__GPIO2_IO28              0x10c 0x420 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_EB0__SRC_BOOT_CFG27          0x10c 0x420 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_EB1__EIM_EB1_B               0x110 0x424 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_EB1__IPU1_DISP1_DATA10       0x110 0x424 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_EB1__IPU2_CSI1_DATA10        0x110 0x424 0x8b0 0x2 0x1
+-#define MX6Q_PAD_EIM_EB1__GPIO2_IO29              0x110 0x424 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_EB1__SRC_BOOT_CFG28          0x110 0x424 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA0__EIM_AD00                0x114 0x428 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA0__IPU1_DISP1_DATA09       0x114 0x428 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA0__IPU2_CSI1_DATA09        0x114 0x428 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_DA0__GPIO3_IO00              0x114 0x428 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA0__SRC_BOOT_CFG00          0x114 0x428 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA1__EIM_AD01                0x118 0x42c 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA1__IPU1_DISP1_DATA08       0x118 0x42c 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA1__IPU2_CSI1_DATA08        0x118 0x42c 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_DA1__GPIO3_IO01              0x118 0x42c 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA1__SRC_BOOT_CFG01          0x118 0x42c 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA2__EIM_AD02                0x11c 0x430 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA2__IPU1_DISP1_DATA07       0x11c 0x430 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA2__IPU2_CSI1_DATA07        0x11c 0x430 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_DA2__GPIO3_IO02              0x11c 0x430 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA2__SRC_BOOT_CFG02          0x11c 0x430 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA3__EIM_AD03                0x120 0x434 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA3__IPU1_DISP1_DATA06       0x120 0x434 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA3__IPU2_CSI1_DATA06        0x120 0x434 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_DA3__GPIO3_IO03              0x120 0x434 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA3__SRC_BOOT_CFG03          0x120 0x434 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA4__EIM_AD04                0x124 0x438 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA4__IPU1_DISP1_DATA05       0x124 0x438 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA4__IPU2_CSI1_DATA05        0x124 0x438 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_DA4__GPIO3_IO04              0x124 0x438 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA4__SRC_BOOT_CFG04          0x124 0x438 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA5__EIM_AD05                0x128 0x43c 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA5__IPU1_DISP1_DATA04       0x128 0x43c 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA5__IPU2_CSI1_DATA04        0x128 0x43c 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_DA5__GPIO3_IO05              0x128 0x43c 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA5__SRC_BOOT_CFG05          0x128 0x43c 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA6__EIM_AD06                0x12c 0x440 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA6__IPU1_DISP1_DATA03       0x12c 0x440 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA6__IPU2_CSI1_DATA03        0x12c 0x440 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_DA6__GPIO3_IO06              0x12c 0x440 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA6__SRC_BOOT_CFG06          0x12c 0x440 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA7__EIM_AD07                0x130 0x444 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA7__IPU1_DISP1_DATA02       0x130 0x444 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA7__IPU2_CSI1_DATA02        0x130 0x444 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_DA7__GPIO3_IO07              0x130 0x444 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA7__SRC_BOOT_CFG07          0x130 0x444 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA8__EIM_AD08                0x134 0x448 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA8__IPU1_DISP1_DATA01       0x134 0x448 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA8__IPU2_CSI1_DATA01        0x134 0x448 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_DA8__GPIO3_IO08              0x134 0x448 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA8__SRC_BOOT_CFG08          0x134 0x448 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA9__EIM_AD09                0x138 0x44c 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA9__IPU1_DISP1_DATA00       0x138 0x44c 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA9__IPU2_CSI1_DATA00        0x138 0x44c 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_DA9__GPIO3_IO09              0x138 0x44c 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA9__SRC_BOOT_CFG09          0x138 0x44c 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA10__EIM_AD10               0x13c 0x450 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15         0x13c 0x450 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN      0x13c 0x450 0x8d8 0x2 0x1
+-#define MX6Q_PAD_EIM_DA10__GPIO3_IO10             0x13c 0x450 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA10__SRC_BOOT_CFG10         0x13c 0x450 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA11__EIM_AD11               0x140 0x454 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN02         0x140 0x454 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC        0x140 0x454 0x8dc 0x2 0x1
+-#define MX6Q_PAD_EIM_DA11__GPIO3_IO11             0x140 0x454 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA11__SRC_BOOT_CFG11         0x140 0x454 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA12__EIM_AD12               0x144 0x458 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN03         0x144 0x458 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC        0x144 0x458 0x8e4 0x2 0x1
+-#define MX6Q_PAD_EIM_DA12__GPIO3_IO12             0x144 0x458 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA12__SRC_BOOT_CFG12         0x144 0x458 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA13__EIM_AD13               0x148 0x45c 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS         0x148 0x45c 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA13__GPIO3_IO13             0x148 0x45c 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA13__SRC_BOOT_CFG13         0x148 0x45c 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA14__EIM_AD14               0x14c 0x460 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS         0x14c 0x460 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA14__GPIO3_IO14             0x14c 0x460 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA14__SRC_BOOT_CFG14         0x14c 0x460 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA15__EIM_AD15               0x150 0x464 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN01         0x150 0x464 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN04         0x150 0x464 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_DA15__GPIO3_IO15             0x150 0x464 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA15__SRC_BOOT_CFG15         0x150 0x464 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_WAIT__EIM_WAIT_B             0x154 0x468 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_WAIT__EIM_DTACK_B            0x154 0x468 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_WAIT__GPIO5_IO00             0x154 0x468 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_WAIT__SRC_BOOT_CFG25         0x154 0x468 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_BCLK__EIM_BCLK               0x158 0x46c 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16         0x158 0x46c 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_BCLK__GPIO6_IO31             0x158 0x46c 0x000 0x5 0x0
+-#define MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK  0x15c 0x470 0x000 0x0 0x0
+-#define MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK  0x15c 0x470 0x000 0x1 0x0
+-#define MX6Q_PAD_DI0_DISP_CLK__GPIO4_IO16         0x15c 0x470 0x000 0x5 0x0
+-#define MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15        0x160 0x474 0x000 0x0 0x0
+-#define MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15        0x160 0x474 0x000 0x1 0x0
+-#define MX6Q_PAD_DI0_PIN15__AUD6_TXC              0x160 0x474 0x000 0x2 0x0
+-#define MX6Q_PAD_DI0_PIN15__GPIO4_IO17            0x160 0x474 0x000 0x5 0x0
+-#define MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN02         0x164 0x478 0x000 0x0 0x0
+-#define MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN02         0x164 0x478 0x000 0x1 0x0
+-#define MX6Q_PAD_DI0_PIN2__AUD6_TXD               0x164 0x478 0x000 0x2 0x0
+-#define MX6Q_PAD_DI0_PIN2__GPIO4_IO18             0x164 0x478 0x000 0x5 0x0
+-#define MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN03         0x168 0x47c 0x000 0x0 0x0
+-#define MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN03         0x168 0x47c 0x000 0x1 0x0
+-#define MX6Q_PAD_DI0_PIN3__AUD6_TXFS              0x168 0x47c 0x000 0x2 0x0
+-#define MX6Q_PAD_DI0_PIN3__GPIO4_IO19             0x168 0x47c 0x000 0x5 0x0
+-#define MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN04         0x16c 0x480 0x000 0x0 0x0
+-#define MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN04         0x16c 0x480 0x000 0x1 0x0
+-#define MX6Q_PAD_DI0_PIN4__AUD6_RXD               0x16c 0x480 0x000 0x2 0x0
+-#define MX6Q_PAD_DI0_PIN4__SD1_WP                 0x16c 0x480 0x94c 0x3 0x0
+-#define MX6Q_PAD_DI0_PIN4__GPIO4_IO20             0x16c 0x480 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DATA00    0x170 0x484 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DATA00    0x170 0x484 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK          0x170 0x484 0x000 0x2 0x0
+-#define MX6Q_PAD_DISP0_DAT0__GPIO4_IO21           0x170 0x484 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DATA01    0x174 0x488 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DATA01    0x174 0x488 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI          0x174 0x488 0x000 0x2 0x0
+-#define MX6Q_PAD_DISP0_DAT1__GPIO4_IO22           0x174 0x488 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DATA02    0x178 0x48c 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DATA02    0x178 0x48c 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO          0x178 0x48c 0x000 0x2 0x0
+-#define MX6Q_PAD_DISP0_DAT2__GPIO4_IO23           0x178 0x48c 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DATA03    0x17c 0x490 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DATA03    0x17c 0x490 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0           0x17c 0x490 0x000 0x2 0x0
+-#define MX6Q_PAD_DISP0_DAT3__GPIO4_IO24           0x17c 0x490 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DATA04    0x180 0x494 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DATA04    0x180 0x494 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1           0x180 0x494 0x000 0x2 0x0
+-#define MX6Q_PAD_DISP0_DAT4__GPIO4_IO25           0x180 0x494 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DATA05    0x184 0x498 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DATA05    0x184 0x498 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2           0x184 0x498 0x000 0x2 0x0
+-#define MX6Q_PAD_DISP0_DAT5__AUD6_RXFS            0x184 0x498 0x000 0x3 0x0
+-#define MX6Q_PAD_DISP0_DAT5__GPIO4_IO26           0x184 0x498 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DATA06    0x188 0x49c 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DATA06    0x188 0x49c 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3           0x188 0x49c 0x000 0x2 0x0
+-#define MX6Q_PAD_DISP0_DAT6__AUD6_RXC             0x188 0x49c 0x000 0x3 0x0
+-#define MX6Q_PAD_DISP0_DAT6__GPIO4_IO27           0x188 0x49c 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DATA07    0x18c 0x4a0 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DATA07    0x18c 0x4a0 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY           0x18c 0x4a0 0x000 0x2 0x0
+-#define MX6Q_PAD_DISP0_DAT7__GPIO4_IO28           0x18c 0x4a0 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DATA08    0x190 0x4a4 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DATA08    0x190 0x4a4 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT8__PWM1_OUT             0x190 0x4a4 0x000 0x2 0x0
+-#define MX6Q_PAD_DISP0_DAT8__WDOG1_B              0x190 0x4a4 0x000 0x3 0x0
+-#define MX6Q_PAD_DISP0_DAT8__GPIO4_IO29           0x190 0x4a4 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DATA09    0x194 0x4a8 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DATA09    0x194 0x4a8 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT9__PWM2_OUT             0x194 0x4a8 0x000 0x2 0x0
+-#define MX6Q_PAD_DISP0_DAT9__WDOG2_B              0x194 0x4a8 0x000 0x3 0x0
+-#define MX6Q_PAD_DISP0_DAT9__GPIO4_IO30           0x194 0x4a8 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DATA10   0x198 0x4ac 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DATA10   0x198 0x4ac 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT10__GPIO4_IO31          0x198 0x4ac 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DATA11   0x19c 0x4b0 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DATA11   0x19c 0x4b0 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT11__GPIO5_IO05          0x19c 0x4b0 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DATA12   0x1a0 0x4b4 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DATA12   0x1a0 0x4b4 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT12__GPIO5_IO06          0x1a0 0x4b4 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DATA13   0x1a4 0x4b8 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DATA13   0x1a4 0x4b8 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT13__AUD5_RXFS           0x1a4 0x4b8 0x7d8 0x3 0x1
+-#define MX6Q_PAD_DISP0_DAT13__GPIO5_IO07          0x1a4 0x4b8 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DATA14   0x1a8 0x4bc 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DATA14   0x1a8 0x4bc 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT14__AUD5_RXC            0x1a8 0x4bc 0x7d4 0x3 0x1
+-#define MX6Q_PAD_DISP0_DAT14__GPIO5_IO08          0x1a8 0x4bc 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DATA15   0x1ac 0x4c0 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DATA15   0x1ac 0x4c0 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1          0x1ac 0x4c0 0x804 0x2 0x1
+-#define MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1          0x1ac 0x4c0 0x820 0x3 0x1
+-#define MX6Q_PAD_DISP0_DAT15__GPIO5_IO09          0x1ac 0x4c0 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DATA16   0x1b0 0x4c4 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DATA16   0x1b0 0x4c4 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI         0x1b0 0x4c4 0x818 0x2 0x1
+-#define MX6Q_PAD_DISP0_DAT16__AUD5_TXC            0x1b0 0x4c4 0x7dc 0x3 0x0
+-#define MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT0     0x1b0 0x4c4 0x90c 0x4 0x0
+-#define MX6Q_PAD_DISP0_DAT16__GPIO5_IO10          0x1b0 0x4c4 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DATA17   0x1b4 0x4c8 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DATA17   0x1b4 0x4c8 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO         0x1b4 0x4c8 0x814 0x2 0x1
+-#define MX6Q_PAD_DISP0_DAT17__AUD5_TXD            0x1b4 0x4c8 0x7d0 0x3 0x0
+-#define MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT1     0x1b4 0x4c8 0x910 0x4 0x0
+-#define MX6Q_PAD_DISP0_DAT17__GPIO5_IO11          0x1b4 0x4c8 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DATA18   0x1b8 0x4cc 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DATA18   0x1b8 0x4cc 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0          0x1b8 0x4cc 0x81c 0x2 0x1
+-#define MX6Q_PAD_DISP0_DAT18__AUD5_TXFS           0x1b8 0x4cc 0x7e0 0x3 0x0
+-#define MX6Q_PAD_DISP0_DAT18__AUD4_RXFS           0x1b8 0x4cc 0x7c0 0x4 0x0
+-#define MX6Q_PAD_DISP0_DAT18__GPIO5_IO12          0x1b8 0x4cc 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT18__EIM_CS2_B           0x1b8 0x4cc 0x000 0x7 0x0
+-#define MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DATA19   0x1bc 0x4d0 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DATA19   0x1bc 0x4d0 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK         0x1bc 0x4d0 0x810 0x2 0x1
+-#define MX6Q_PAD_DISP0_DAT19__AUD5_RXD            0x1bc 0x4d0 0x7cc 0x3 0x0
+-#define MX6Q_PAD_DISP0_DAT19__AUD4_RXC            0x1bc 0x4d0 0x7bc 0x4 0x0
+-#define MX6Q_PAD_DISP0_DAT19__GPIO5_IO13          0x1bc 0x4d0 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT19__EIM_CS3_B           0x1bc 0x4d0 0x000 0x7 0x0
+-#define MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DATA20   0x1c0 0x4d4 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DATA20   0x1c0 0x4d4 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK         0x1c0 0x4d4 0x7f4 0x2 0x1
+-#define MX6Q_PAD_DISP0_DAT20__AUD4_TXC            0x1c0 0x4d4 0x7c4 0x3 0x0
+-#define MX6Q_PAD_DISP0_DAT20__GPIO5_IO14          0x1c0 0x4d4 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DATA21   0x1c4 0x4d8 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DATA21   0x1c4 0x4d8 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI         0x1c4 0x4d8 0x7fc 0x2 0x1
+-#define MX6Q_PAD_DISP0_DAT21__AUD4_TXD            0x1c4 0x4d8 0x7b8 0x3 0x1
+-#define MX6Q_PAD_DISP0_DAT21__GPIO5_IO15          0x1c4 0x4d8 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DATA22   0x1c8 0x4dc 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DATA22   0x1c8 0x4dc 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO         0x1c8 0x4dc 0x7f8 0x2 0x1
+-#define MX6Q_PAD_DISP0_DAT22__AUD4_TXFS           0x1c8 0x4dc 0x7c8 0x3 0x1
+-#define MX6Q_PAD_DISP0_DAT22__GPIO5_IO16          0x1c8 0x4dc 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DATA23   0x1cc 0x4e0 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DATA23   0x1cc 0x4e0 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0          0x1cc 0x4e0 0x800 0x2 0x1
+-#define MX6Q_PAD_DISP0_DAT23__AUD4_RXD            0x1cc 0x4e0 0x7b4 0x3 0x1
+-#define MX6Q_PAD_DISP0_DAT23__GPIO5_IO17          0x1cc 0x4e0 0x000 0x5 0x0
+-#define MX6Q_PAD_ENET_MDIO__ENET_MDIO             0x1d0 0x4e4 0x840 0x1 0x0
+-#define MX6Q_PAD_ENET_MDIO__ESAI_RX_CLK           0x1d0 0x4e4 0x86c 0x2 0x0
+-#define MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT  0x1d0 0x4e4 0x000 0x4 0x0
+-#define MX6Q_PAD_ENET_MDIO__GPIO1_IO22            0x1d0 0x4e4 0x000 0x5 0x0
+-#define MX6Q_PAD_ENET_MDIO__SPDIF_LOCK            0x1d0 0x4e4 0x000 0x6 0x0
+-#define MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK        0x1d4 0x4e8 0x000 0x1 0x0
+-#define MX6Q_PAD_ENET_REF_CLK__ESAI_RX_FS         0x1d4 0x4e8 0x85c 0x2 0x0
+-#define MX6Q_PAD_ENET_REF_CLK__GPIO1_IO23         0x1d4 0x4e8 0x000 0x5 0x0
+-#define MX6Q_PAD_ENET_REF_CLK__SPDIF_SR_CLK       0x1d4 0x4e8 0x000 0x6 0x0
+-#define MX6Q_PAD_ENET_RX_ER__USB_OTG_ID           0x1d8 0x4ec 0x000 0x0 0x0
+-#define MX6Q_PAD_ENET_RX_ER__ENET_RX_ER           0x1d8 0x4ec 0x000 0x1 0x0
+-#define MX6Q_PAD_ENET_RX_ER__ESAI_RX_HF_CLK       0x1d8 0x4ec 0x864 0x2 0x0
+-#define MX6Q_PAD_ENET_RX_ER__SPDIF_IN             0x1d8 0x4ec 0x914 0x3 0x1
+-#define MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0
+-#define MX6Q_PAD_ENET_RX_ER__GPIO1_IO24           0x1d8 0x4ec 0x000 0x5 0x0
+-#define MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN          0x1dc 0x4f0 0x858 0x1 0x1
+-#define MX6Q_PAD_ENET_CRS_DV__ESAI_TX_CLK         0x1dc 0x4f0 0x870 0x2 0x0
+-#define MX6Q_PAD_ENET_CRS_DV__SPDIF_EXT_CLK       0x1dc 0x4f0 0x918 0x3 0x1
+-#define MX6Q_PAD_ENET_CRS_DV__GPIO1_IO25          0x1dc 0x4f0 0x000 0x5 0x0
+-#define MX6Q_PAD_ENET_RXD1__MLB_SIG               0x1e0 0x4f4 0x908 0x0 0x0
+-#define MX6Q_PAD_ENET_RXD1__ENET_RX_DATA1         0x1e0 0x4f4 0x84c 0x1 0x1
+-#define MX6Q_PAD_ENET_RXD1__ESAI_TX_FS            0x1e0 0x4f4 0x860 0x2 0x0
+-#define MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT  0x1e0 0x4f4 0x000 0x4 0x0
+-#define MX6Q_PAD_ENET_RXD1__GPIO1_IO26            0x1e0 0x4f4 0x000 0x5 0x0
+-#define MX6Q_PAD_ENET_RXD0__ENET_RX_DATA0         0x1e4 0x4f8 0x848 0x1 0x1
+-#define MX6Q_PAD_ENET_RXD0__ESAI_TX_HF_CLK        0x1e4 0x4f8 0x868 0x2 0x0
+-#define MX6Q_PAD_ENET_RXD0__SPDIF_OUT             0x1e4 0x4f8 0x000 0x3 0x0
+-#define MX6Q_PAD_ENET_RXD0__GPIO1_IO27            0x1e4 0x4f8 0x000 0x5 0x0
+-#define MX6Q_PAD_ENET_TX_EN__ENET_TX_EN           0x1e8 0x4fc 0x000 0x1 0x0
+-#define MX6Q_PAD_ENET_TX_EN__ESAI_TX3_RX2         0x1e8 0x4fc 0x880 0x2 0x0
+-#define MX6Q_PAD_ENET_TX_EN__GPIO1_IO28           0x1e8 0x4fc 0x000 0x5 0x0
+-#define MX6Q_PAD_ENET_TXD1__MLB_CLK               0x1ec 0x500 0x900 0x0 0x0
+-#define MX6Q_PAD_ENET_TXD1__ENET_TX_DATA1         0x1ec 0x500 0x000 0x1 0x0
+-#define MX6Q_PAD_ENET_TXD1__ESAI_TX2_RX3          0x1ec 0x500 0x87c 0x2 0x0
+-#define MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN   0x1ec 0x500 0x000 0x4 0x0
+-#define MX6Q_PAD_ENET_TXD1__GPIO1_IO29            0x1ec 0x500 0x000 0x5 0x0
+-#define MX6Q_PAD_ENET_TXD0__ENET_TX_DATA0         0x1f0 0x504 0x000 0x1 0x0
+-#define MX6Q_PAD_ENET_TXD0__ESAI_TX4_RX1          0x1f0 0x504 0x884 0x2 0x0
+-#define MX6Q_PAD_ENET_TXD0__GPIO1_IO30            0x1f0 0x504 0x000 0x5 0x0
+-#define MX6Q_PAD_ENET_MDC__MLB_DATA               0x1f4 0x508 0x904 0x0 0x0
+-#define MX6Q_PAD_ENET_MDC__ENET_MDC               0x1f4 0x508 0x000 0x1 0x0
+-#define MX6Q_PAD_ENET_MDC__ESAI_TX5_RX0           0x1f4 0x508 0x888 0x2 0x0
+-#define MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN    0x1f4 0x508 0x000 0x4 0x0
+-#define MX6Q_PAD_ENET_MDC__GPIO1_IO31             0x1f4 0x508 0x000 0x5 0x0
+-#define MX6Q_PAD_KEY_COL0__ECSPI1_SCLK            0x1f8 0x5c8 0x7f4 0x0 0x2
+-#define MX6Q_PAD_KEY_COL0__ENET_RX_DATA3          0x1f8 0x5c8 0x854 0x1 0x1
+-#define MX6Q_PAD_KEY_COL0__AUD5_TXC               0x1f8 0x5c8 0x7dc 0x2 0x1
+-#define MX6Q_PAD_KEY_COL0__KEY_COL0               0x1f8 0x5c8 0x000 0x3 0x0
+-#define MX6Q_PAD_KEY_COL0__UART4_TX_DATA          0x1f8 0x5c8 0x000 0x4 0x0
+-#define MX6Q_PAD_KEY_COL0__UART4_RX_DATA          0x1f8 0x5c8 0x938 0x4 0x0
+-#define MX6Q_PAD_KEY_COL0__GPIO4_IO06             0x1f8 0x5c8 0x000 0x5 0x0
+-#define MX6Q_PAD_KEY_COL0__DCIC1_OUT              0x1f8 0x5c8 0x000 0x6 0x0
+-#define MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI            0x1fc 0x5cc 0x7fc 0x0 0x2
+-#define MX6Q_PAD_KEY_ROW0__ENET_TX_DATA3          0x1fc 0x5cc 0x000 0x1 0x0
+-#define MX6Q_PAD_KEY_ROW0__AUD5_TXD               0x1fc 0x5cc 0x7d0 0x2 0x1
+-#define MX6Q_PAD_KEY_ROW0__KEY_ROW0               0x1fc 0x5cc 0x000 0x3 0x0
+-#define MX6Q_PAD_KEY_ROW0__UART4_RX_DATA          0x1fc 0x5cc 0x938 0x4 0x1
+-#define MX6Q_PAD_KEY_ROW0__UART4_TX_DATA          0x1fc 0x5cc 0x000 0x4 0x0
+-#define MX6Q_PAD_KEY_ROW0__GPIO4_IO07             0x1fc 0x5cc 0x000 0x5 0x0
+-#define MX6Q_PAD_KEY_ROW0__DCIC2_OUT              0x1fc 0x5cc 0x000 0x6 0x0
+-#define MX6Q_PAD_KEY_COL1__ECSPI1_MISO            0x200 0x5d0 0x7f8 0x0 0x2
+-#define MX6Q_PAD_KEY_COL1__ENET_MDIO              0x200 0x5d0 0x840 0x1 0x1
+-#define MX6Q_PAD_KEY_COL1__AUD5_TXFS              0x200 0x5d0 0x7e0 0x2 0x1
+-#define MX6Q_PAD_KEY_COL1__KEY_COL1               0x200 0x5d0 0x000 0x3 0x0
+-#define MX6Q_PAD_KEY_COL1__UART5_TX_DATA          0x200 0x5d0 0x000 0x4 0x0
+-#define MX6Q_PAD_KEY_COL1__UART5_RX_DATA          0x200 0x5d0 0x940 0x4 0x0
+-#define MX6Q_PAD_KEY_COL1__GPIO4_IO08             0x200 0x5d0 0x000 0x5 0x0
+-#define MX6Q_PAD_KEY_COL1__SD1_VSELECT            0x200 0x5d0 0x000 0x6 0x0
+-#define MX6Q_PAD_KEY_ROW1__ECSPI1_SS0             0x204 0x5d4 0x800 0x0 0x2
+-#define MX6Q_PAD_KEY_ROW1__ENET_COL               0x204 0x5d4 0x000 0x1 0x0
+-#define MX6Q_PAD_KEY_ROW1__AUD5_RXD               0x204 0x5d4 0x7cc 0x2 0x1
+-#define MX6Q_PAD_KEY_ROW1__KEY_ROW1               0x204 0x5d4 0x000 0x3 0x0
+-#define MX6Q_PAD_KEY_ROW1__UART5_RX_DATA          0x204 0x5d4 0x940 0x4 0x1
+-#define MX6Q_PAD_KEY_ROW1__UART5_TX_DATA          0x204 0x5d4 0x000 0x4 0x0
+-#define MX6Q_PAD_KEY_ROW1__GPIO4_IO09             0x204 0x5d4 0x000 0x5 0x0
+-#define MX6Q_PAD_KEY_ROW1__SD2_VSELECT            0x204 0x5d4 0x000 0x6 0x0
+-#define MX6Q_PAD_KEY_COL2__ECSPI1_SS1             0x208 0x5d8 0x804 0x0 0x2
+-#define MX6Q_PAD_KEY_COL2__ENET_RX_DATA2          0x208 0x5d8 0x850 0x1 0x1
+-#define MX6Q_PAD_KEY_COL2__FLEXCAN1_TX            0x208 0x5d8 0x000 0x2 0x0
+-#define MX6Q_PAD_KEY_COL2__KEY_COL2               0x208 0x5d8 0x000 0x3 0x0
+-#define MX6Q_PAD_KEY_COL2__ENET_MDC               0x208 0x5d8 0x000 0x4 0x0
+-#define MX6Q_PAD_KEY_COL2__GPIO4_IO10             0x208 0x5d8 0x000 0x5 0x0
+-#define MX6Q_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE    0x208 0x5d8 0x000 0x6 0x0
+-#define MX6Q_PAD_KEY_ROW2__ECSPI1_SS2             0x20c 0x5dc 0x808 0x0 0x1
+-#define MX6Q_PAD_KEY_ROW2__ENET_TX_DATA2          0x20c 0x5dc 0x000 0x1 0x0
+-#define MX6Q_PAD_KEY_ROW2__FLEXCAN1_RX            0x20c 0x5dc 0x7e4 0x2 0x0
+-#define MX6Q_PAD_KEY_ROW2__KEY_ROW2               0x20c 0x5dc 0x000 0x3 0x0
+-#define MX6Q_PAD_KEY_ROW2__SD2_VSELECT            0x20c 0x5dc 0x000 0x4 0x0
+-#define MX6Q_PAD_KEY_ROW2__GPIO4_IO11             0x20c 0x5dc 0x000 0x5 0x0
+-#define MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE       0x20c 0x5dc 0x88c 0x6 0x1
+-#define MX6Q_PAD_KEY_COL3__ECSPI1_SS3             0x210 0x5e0 0x80c 0x0 0x1
+-#define MX6Q_PAD_KEY_COL3__ENET_CRS               0x210 0x5e0 0x000 0x1 0x0
+-#define MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL        0x210 0x5e0 0x890 0x2 0x1
+-#define MX6Q_PAD_KEY_COL3__KEY_COL3               0x210 0x5e0 0x000 0x3 0x0
+-#define MX6Q_PAD_KEY_COL3__I2C2_SCL               0x210 0x5e0 0x8a0 0x4 0x1
+-#define MX6Q_PAD_KEY_COL3__GPIO4_IO12             0x210 0x5e0 0x000 0x5 0x0
+-#define MX6Q_PAD_KEY_COL3__SPDIF_IN               0x210 0x5e0 0x914 0x6 0x2
+-#define MX6Q_PAD_KEY_ROW3__ASRC_EXT_CLK           0x214 0x5e4 0x7b0 0x1 0x0
+-#define MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA        0x214 0x5e4 0x894 0x2 0x1
+-#define MX6Q_PAD_KEY_ROW3__KEY_ROW3               0x214 0x5e4 0x000 0x3 0x0
+-#define MX6Q_PAD_KEY_ROW3__I2C2_SDA               0x214 0x5e4 0x8a4 0x4 0x1
+-#define MX6Q_PAD_KEY_ROW3__GPIO4_IO13             0x214 0x5e4 0x000 0x5 0x0
+-#define MX6Q_PAD_KEY_ROW3__SD1_VSELECT            0x214 0x5e4 0x000 0x6 0x0
+-#define MX6Q_PAD_KEY_COL4__FLEXCAN2_TX            0x218 0x5e8 0x000 0x0 0x0
+-#define MX6Q_PAD_KEY_COL4__IPU1_SISG4             0x218 0x5e8 0x000 0x1 0x0
+-#define MX6Q_PAD_KEY_COL4__USB_OTG_OC             0x218 0x5e8 0x944 0x2 0x1
+-#define MX6Q_PAD_KEY_COL4__KEY_COL4               0x218 0x5e8 0x000 0x3 0x0
+-#define MX6Q_PAD_KEY_COL4__UART5_RTS_B            0x218 0x5e8 0x93c 0x4 0x0
+-#define MX6Q_PAD_KEY_COL4__UART5_CTS_B            0x218 0x5e8 0x000 0x4 0x0
+-#define MX6Q_PAD_KEY_COL4__GPIO4_IO14             0x218 0x5e8 0x000 0x5 0x0
+-#define MX6Q_PAD_KEY_ROW4__FLEXCAN2_RX            0x21c 0x5ec 0x7e8 0x0 0x0
+-#define MX6Q_PAD_KEY_ROW4__IPU1_SISG5             0x21c 0x5ec 0x000 0x1 0x0
+-#define MX6Q_PAD_KEY_ROW4__USB_OTG_PWR            0x21c 0x5ec 0x000 0x2 0x0
+-#define MX6Q_PAD_KEY_ROW4__KEY_ROW4               0x21c 0x5ec 0x000 0x3 0x0
+-#define MX6Q_PAD_KEY_ROW4__UART5_CTS_B            0x21c 0x5ec 0x000 0x4 0x0
+-#define MX6Q_PAD_KEY_ROW4__UART5_RTS_B            0x21c 0x5ec 0x93c 0x4 0x1
+-#define MX6Q_PAD_KEY_ROW4__GPIO4_IO15             0x21c 0x5ec 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_0__CCM_CLKO1                0x220 0x5f0 0x000 0x0 0x0
+-#define MX6Q_PAD_GPIO_0__KEY_COL5                 0x220 0x5f0 0x8e8 0x2 0x0
+-#define MX6Q_PAD_GPIO_0__ASRC_EXT_CLK             0x220 0x5f0 0x7b0 0x3 0x1
+-#define MX6Q_PAD_GPIO_0__EPIT1_OUT                0x220 0x5f0 0x000 0x4 0x0
+-#define MX6Q_PAD_GPIO_0__GPIO1_IO00               0x220 0x5f0 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_0__USB_H1_PWR               0x220 0x5f0 0x000 0x6 0x0
+-#define MX6Q_PAD_GPIO_0__SNVS_VIO_5               0x220 0x5f0 0x000 0x7 0x0
+-#define MX6Q_PAD_GPIO_1__ESAI_RX_CLK              0x224 0x5f4 0x86c 0x0 0x1
+-#define MX6Q_PAD_GPIO_1__WDOG2_B                  0x224 0x5f4 0x000 0x1 0x0
+-#define MX6Q_PAD_GPIO_1__KEY_ROW5                 0x224 0x5f4 0x8f4 0x2 0x0
+-#define MX6Q_PAD_GPIO_1__USB_OTG_ID               0x224 0x5f4 0x000 0x3 0x0
+-#define MX6Q_PAD_GPIO_1__PWM2_OUT                 0x224 0x5f4 0x000 0x4 0x0
+-#define MX6Q_PAD_GPIO_1__GPIO1_IO01               0x224 0x5f4 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_1__SD1_CD_B                 0x224 0x5f4 0x000 0x6 0x0
+-#define MX6Q_PAD_GPIO_9__ESAI_RX_FS               0x228 0x5f8 0x85c 0x0 0x1
+-#define MX6Q_PAD_GPIO_9__WDOG1_B                  0x228 0x5f8 0x000 0x1 0x0
+-#define MX6Q_PAD_GPIO_9__KEY_COL6                 0x228 0x5f8 0x8ec 0x2 0x0
+-#define MX6Q_PAD_GPIO_9__CCM_REF_EN_B             0x228 0x5f8 0x000 0x3 0x0
+-#define MX6Q_PAD_GPIO_9__PWM1_OUT                 0x228 0x5f8 0x000 0x4 0x0
+-#define MX6Q_PAD_GPIO_9__GPIO1_IO09               0x228 0x5f8 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_9__SD1_WP                   0x228 0x5f8 0x94c 0x6 0x1
+-#define MX6Q_PAD_GPIO_3__ESAI_RX_HF_CLK           0x22c 0x5fc 0x864 0x0 0x1
+-#define MX6Q_PAD_GPIO_3__I2C3_SCL                 0x22c 0x5fc 0x8a8 0x2 0x1
+-#define MX6Q_PAD_GPIO_3__XTALOSC_REF_CLK_24M      0x22c 0x5fc 0x000 0x3 0x0
+-#define MX6Q_PAD_GPIO_3__CCM_CLKO2                0x22c 0x5fc 0x000 0x4 0x0
+-#define MX6Q_PAD_GPIO_3__GPIO1_IO03               0x22c 0x5fc 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_3__USB_H1_OC                0x22c 0x5fc 0x948 0x6 0x1
+-#define MX6Q_PAD_GPIO_3__MLB_CLK                  0x22c 0x5fc 0x900 0x7 0x1
+-#define MX6Q_PAD_GPIO_6__ESAI_TX_CLK              0x230 0x600 0x870 0x0 0x1
+-#define MX6Q_PAD_GPIO_6__I2C3_SDA                 0x230 0x600 0x8ac 0x2 0x1
+-#define MX6Q_PAD_GPIO_6__GPIO1_IO06               0x230 0x600 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_6__SD2_LCTL                 0x230 0x600 0x000 0x6 0x0
+-#define MX6Q_PAD_GPIO_6__MLB_SIG                  0x230 0x600 0x908 0x7 0x1
+-#define MX6Q_PAD_GPIO_2__ESAI_TX_FS               0x234 0x604 0x860 0x0 0x1
+-#define MX6Q_PAD_GPIO_2__KEY_ROW6                 0x234 0x604 0x8f8 0x2 0x1
+-#define MX6Q_PAD_GPIO_2__GPIO1_IO02               0x234 0x604 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_2__SD2_WP                   0x234 0x604 0x000 0x6 0x0
+-#define MX6Q_PAD_GPIO_2__MLB_DATA                 0x234 0x604 0x904 0x7 0x1
+-#define MX6Q_PAD_GPIO_4__ESAI_TX_HF_CLK           0x238 0x608 0x868 0x0 0x1
+-#define MX6Q_PAD_GPIO_4__KEY_COL7                 0x238 0x608 0x8f0 0x2 0x1
+-#define MX6Q_PAD_GPIO_4__GPIO1_IO04               0x238 0x608 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_4__SD2_CD_B                 0x238 0x608 0x000 0x6 0x0
+-#define MX6Q_PAD_GPIO_5__ESAI_TX2_RX3             0x23c 0x60c 0x87c 0x0 0x1
+-#define MX6Q_PAD_GPIO_5__KEY_ROW7                 0x23c 0x60c 0x8fc 0x2 0x1
+-#define MX6Q_PAD_GPIO_5__CCM_CLKO1                0x23c 0x60c 0x000 0x3 0x0
+-#define MX6Q_PAD_GPIO_5__GPIO1_IO05               0x23c 0x60c 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_5__I2C3_SCL                 0x23c 0x60c 0x8a8 0x6 0x2
+-#define MX6Q_PAD_GPIO_5__ARM_EVENTI               0x23c 0x60c 0x000 0x7 0x0
+-#define MX6Q_PAD_GPIO_7__ESAI_TX4_RX1             0x240 0x610 0x884 0x0 0x1
+-#define MX6Q_PAD_GPIO_7__ECSPI5_RDY               0x240 0x610 0x000 0x1 0x0
+-#define MX6Q_PAD_GPIO_7__EPIT1_OUT                0x240 0x610 0x000 0x2 0x0
+-#define MX6Q_PAD_GPIO_7__FLEXCAN1_TX              0x240 0x610 0x000 0x3 0x0
+-#define MX6Q_PAD_GPIO_7__UART2_TX_DATA            0x240 0x610 0x000 0x4 0x0
+-#define MX6Q_PAD_GPIO_7__UART2_RX_DATA            0x240 0x610 0x928 0x4 0x2
+-#define MX6Q_PAD_GPIO_7__GPIO1_IO07               0x240 0x610 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_7__SPDIF_LOCK               0x240 0x610 0x000 0x6 0x0
+-#define MX6Q_PAD_GPIO_7__USB_OTG_HOST_MODE        0x240 0x610 0x000 0x7 0x0
+-#define MX6Q_PAD_GPIO_8__ESAI_TX5_RX0             0x244 0x614 0x888 0x0 0x1
+-#define MX6Q_PAD_GPIO_8__XTALOSC_REF_CLK_32K      0x244 0x614 0x000 0x1 0x0
+-#define MX6Q_PAD_GPIO_8__EPIT2_OUT                0x244 0x614 0x000 0x2 0x0
+-#define MX6Q_PAD_GPIO_8__FLEXCAN1_RX              0x244 0x614 0x7e4 0x3 0x1
+-#define MX6Q_PAD_GPIO_8__UART2_RX_DATA            0x244 0x614 0x928 0x4 0x3
+-#define MX6Q_PAD_GPIO_8__UART2_TX_DATA            0x244 0x614 0x000 0x4 0x0
+-#define MX6Q_PAD_GPIO_8__GPIO1_IO08               0x244 0x614 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_8__SPDIF_SR_CLK             0x244 0x614 0x000 0x6 0x0
+-#define MX6Q_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE     0x244 0x614 0x000 0x7 0x0
+-#define MX6Q_PAD_GPIO_16__ESAI_TX3_RX2            0x248 0x618 0x880 0x0 0x1
+-#define MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN     0x248 0x618 0x000 0x1 0x0
+-#define MX6Q_PAD_GPIO_16__ENET_REF_CLK            0x248 0x618 0x83c 0x2 0x1
+-#define MX6Q_PAD_GPIO_16__SD1_LCTL                0x248 0x618 0x000 0x3 0x0
+-#define MX6Q_PAD_GPIO_16__SPDIF_IN                0x248 0x618 0x914 0x4 0x3
+-#define MX6Q_PAD_GPIO_16__GPIO7_IO11              0x248 0x618 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_16__I2C3_SDA                0x248 0x618 0x8ac 0x6 0x2
+-#define MX6Q_PAD_GPIO_16__JTAG_DE_B               0x248 0x618 0x000 0x7 0x0
+-#define MX6Q_PAD_GPIO_17__ESAI_TX0                0x24c 0x61c 0x874 0x0 0x0
+-#define MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN     0x24c 0x61c 0x000 0x1 0x0
+-#define MX6Q_PAD_GPIO_17__CCM_PMIC_READY          0x24c 0x61c 0x7f0 0x2 0x1
+-#define MX6Q_PAD_GPIO_17__SDMA_EXT_EVENT0         0x24c 0x61c 0x90c 0x3 0x1
+-#define MX6Q_PAD_GPIO_17__SPDIF_OUT               0x24c 0x61c 0x000 0x4 0x0
+-#define MX6Q_PAD_GPIO_17__GPIO7_IO12              0x24c 0x61c 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_18__ESAI_TX1                0x250 0x620 0x878 0x0 0x0
+-#define MX6Q_PAD_GPIO_18__ENET_RX_CLK             0x250 0x620 0x844 0x1 0x1
+-#define MX6Q_PAD_GPIO_18__SD3_VSELECT             0x250 0x620 0x000 0x2 0x0
+-#define MX6Q_PAD_GPIO_18__SDMA_EXT_EVENT1         0x250 0x620 0x910 0x3 0x1
+-#define MX6Q_PAD_GPIO_18__ASRC_EXT_CLK            0x250 0x620 0x7b0 0x4 0x2
+-#define MX6Q_PAD_GPIO_18__GPIO7_IO13              0x250 0x620 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_18__SNVS_VIO_5_CTL          0x250 0x620 0x000 0x6 0x0
+-#define MX6Q_PAD_GPIO_19__KEY_COL5                0x254 0x624 0x8e8 0x0 0x1
+-#define MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT    0x254 0x624 0x000 0x1 0x0
+-#define MX6Q_PAD_GPIO_19__SPDIF_OUT               0x254 0x624 0x000 0x2 0x0
+-#define MX6Q_PAD_GPIO_19__CCM_CLKO1               0x254 0x624 0x000 0x3 0x0
+-#define MX6Q_PAD_GPIO_19__ECSPI1_RDY              0x254 0x624 0x000 0x4 0x0
+-#define MX6Q_PAD_GPIO_19__GPIO4_IO05              0x254 0x624 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_19__ENET_TX_ER              0x254 0x624 0x000 0x6 0x0
+-#define MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK    0x258 0x628 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_PIXCLK__GPIO5_IO18          0x258 0x628 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_PIXCLK__ARM_EVENTO          0x258 0x628 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC       0x25c 0x62c 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_MCLK__CCM_CLKO1             0x25c 0x62c 0x000 0x3 0x0
+-#define MX6Q_PAD_CSI0_MCLK__GPIO5_IO19            0x25c 0x62c 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_MCLK__ARM_TRACE_CTL         0x25c 0x62c 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN  0x260 0x630 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DATA_EN__EIM_DATA00         0x260 0x630 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DATA_EN__GPIO5_IO20         0x260 0x630 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DATA_EN__ARM_TRACE_CLK      0x260 0x630 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC      0x264 0x634 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_VSYNC__EIM_DATA01           0x264 0x634 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_VSYNC__GPIO5_IO21           0x264 0x634 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_VSYNC__ARM_TRACE00          0x264 0x634 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_DATA04      0x268 0x638 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT4__EIM_DATA02            0x268 0x638 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK           0x268 0x638 0x7f4 0x2 0x3
+-#define MX6Q_PAD_CSI0_DAT4__KEY_COL5              0x268 0x638 0x8e8 0x3 0x2
+-#define MX6Q_PAD_CSI0_DAT4__AUD3_TXC              0x268 0x638 0x000 0x4 0x0
+-#define MX6Q_PAD_CSI0_DAT4__GPIO5_IO22            0x268 0x638 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT4__ARM_TRACE01           0x268 0x638 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_DATA05      0x26c 0x63c 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT5__EIM_DATA03            0x26c 0x63c 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI           0x26c 0x63c 0x7fc 0x2 0x3
+-#define MX6Q_PAD_CSI0_DAT5__KEY_ROW5              0x26c 0x63c 0x8f4 0x3 0x1
+-#define MX6Q_PAD_CSI0_DAT5__AUD3_TXD              0x26c 0x63c 0x000 0x4 0x0
+-#define MX6Q_PAD_CSI0_DAT5__GPIO5_IO23            0x26c 0x63c 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT5__ARM_TRACE02           0x26c 0x63c 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_DATA06      0x270 0x640 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT6__EIM_DATA04            0x270 0x640 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO           0x270 0x640 0x7f8 0x2 0x3
+-#define MX6Q_PAD_CSI0_DAT6__KEY_COL6              0x270 0x640 0x8ec 0x3 0x1
+-#define MX6Q_PAD_CSI0_DAT6__AUD3_TXFS             0x270 0x640 0x000 0x4 0x0
+-#define MX6Q_PAD_CSI0_DAT6__GPIO5_IO24            0x270 0x640 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT6__ARM_TRACE03           0x270 0x640 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_DATA07      0x274 0x644 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT7__EIM_DATA05            0x274 0x644 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0            0x274 0x644 0x800 0x2 0x3
+-#define MX6Q_PAD_CSI0_DAT7__KEY_ROW6              0x274 0x644 0x8f8 0x3 0x2
+-#define MX6Q_PAD_CSI0_DAT7__AUD3_RXD              0x274 0x644 0x000 0x4 0x0
+-#define MX6Q_PAD_CSI0_DAT7__GPIO5_IO25            0x274 0x644 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT7__ARM_TRACE04           0x274 0x644 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_DATA08      0x278 0x648 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT8__EIM_DATA06            0x278 0x648 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK           0x278 0x648 0x810 0x2 0x2
+-#define MX6Q_PAD_CSI0_DAT8__KEY_COL7              0x278 0x648 0x8f0 0x3 0x2
+-#define MX6Q_PAD_CSI0_DAT8__I2C1_SDA              0x278 0x648 0x89c 0x4 0x1
+-#define MX6Q_PAD_CSI0_DAT8__GPIO5_IO26            0x278 0x648 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT8__ARM_TRACE05           0x278 0x648 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_DATA09      0x27c 0x64c 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT9__EIM_DATA07            0x27c 0x64c 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI           0x27c 0x64c 0x818 0x2 0x2
+-#define MX6Q_PAD_CSI0_DAT9__KEY_ROW7              0x27c 0x64c 0x8fc 0x3 0x2
+-#define MX6Q_PAD_CSI0_DAT9__I2C1_SCL              0x27c 0x64c 0x898 0x4 0x1
+-#define MX6Q_PAD_CSI0_DAT9__GPIO5_IO27            0x27c 0x64c 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT9__ARM_TRACE06           0x27c 0x64c 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_DATA10     0x280 0x650 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT10__AUD3_RXC             0x280 0x650 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO          0x280 0x650 0x814 0x2 0x2
+-#define MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA        0x280 0x650 0x000 0x3 0x0
+-#define MX6Q_PAD_CSI0_DAT10__UART1_RX_DATA        0x280 0x650 0x920 0x3 0x0
+-#define MX6Q_PAD_CSI0_DAT10__GPIO5_IO28           0x280 0x650 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT10__ARM_TRACE07          0x280 0x650 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_DATA11     0x284 0x654 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT11__AUD3_RXFS            0x284 0x654 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0           0x284 0x654 0x81c 0x2 0x2
+-#define MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA        0x284 0x654 0x920 0x3 0x1
+-#define MX6Q_PAD_CSI0_DAT11__UART1_TX_DATA        0x284 0x654 0x000 0x3 0x0
+-#define MX6Q_PAD_CSI0_DAT11__GPIO5_IO29           0x284 0x654 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT11__ARM_TRACE08          0x284 0x654 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_DATA12     0x288 0x658 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT12__EIM_DATA08           0x288 0x658 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT12__UART4_TX_DATA        0x288 0x658 0x000 0x3 0x0
+-#define MX6Q_PAD_CSI0_DAT12__UART4_RX_DATA        0x288 0x658 0x938 0x3 0x2
+-#define MX6Q_PAD_CSI0_DAT12__GPIO5_IO30           0x288 0x658 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT12__ARM_TRACE09          0x288 0x658 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_DATA13     0x28c 0x65c 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT13__EIM_DATA09           0x28c 0x65c 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT13__UART4_RX_DATA        0x28c 0x65c 0x938 0x3 0x3
+-#define MX6Q_PAD_CSI0_DAT13__UART4_TX_DATA        0x28c 0x65c 0x000 0x3 0x0
+-#define MX6Q_PAD_CSI0_DAT13__GPIO5_IO31           0x28c 0x65c 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT13__ARM_TRACE10          0x28c 0x65c 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_DATA14     0x290 0x660 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT14__EIM_DATA10           0x290 0x660 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT14__UART5_TX_DATA        0x290 0x660 0x000 0x3 0x0
+-#define MX6Q_PAD_CSI0_DAT14__UART5_RX_DATA        0x290 0x660 0x940 0x3 0x2
+-#define MX6Q_PAD_CSI0_DAT14__GPIO6_IO00           0x290 0x660 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT14__ARM_TRACE11          0x290 0x660 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_DATA15     0x294 0x664 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT15__EIM_DATA11           0x294 0x664 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT15__UART5_RX_DATA        0x294 0x664 0x940 0x3 0x3
+-#define MX6Q_PAD_CSI0_DAT15__UART5_TX_DATA        0x294 0x664 0x000 0x3 0x0
+-#define MX6Q_PAD_CSI0_DAT15__GPIO6_IO01           0x294 0x664 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT15__ARM_TRACE12          0x294 0x664 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_DATA16     0x298 0x668 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT16__EIM_DATA12           0x298 0x668 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT16__UART4_RTS_B          0x298 0x668 0x934 0x3 0x0
+-#define MX6Q_PAD_CSI0_DAT16__UART4_CTS_B          0x298 0x668 0x000 0x3 0x0
+-#define MX6Q_PAD_CSI0_DAT16__GPIO6_IO02           0x298 0x668 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT16__ARM_TRACE13          0x298 0x668 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_DATA17     0x29c 0x66c 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT17__EIM_DATA13           0x29c 0x66c 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT17__UART4_CTS_B          0x29c 0x66c 0x000 0x3 0x0
+-#define MX6Q_PAD_CSI0_DAT17__UART4_RTS_B          0x29c 0x66c 0x934 0x3 0x1
+-#define MX6Q_PAD_CSI0_DAT17__GPIO6_IO03           0x29c 0x66c 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT17__ARM_TRACE14          0x29c 0x66c 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_DATA18     0x2a0 0x670 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT18__EIM_DATA14           0x2a0 0x670 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT18__UART5_RTS_B          0x2a0 0x670 0x93c 0x3 0x2
+-#define MX6Q_PAD_CSI0_DAT18__UART5_CTS_B          0x2a0 0x670 0x000 0x3 0x0
+-#define MX6Q_PAD_CSI0_DAT18__GPIO6_IO04           0x2a0 0x670 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT18__ARM_TRACE15          0x2a0 0x670 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_DATA19     0x2a4 0x674 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT19__EIM_DATA15           0x2a4 0x674 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT19__UART5_CTS_B          0x2a4 0x674 0x000 0x3 0x0
+-#define MX6Q_PAD_CSI0_DAT19__UART5_RTS_B          0x2a4 0x674 0x93c 0x3 0x3
+-#define MX6Q_PAD_CSI0_DAT19__GPIO6_IO05           0x2a4 0x674 0x000 0x5 0x0
+-#define MX6Q_PAD_SD3_DAT7__SD3_DATA7              0x2a8 0x690 0x000 0x0 0x0
+-#define MX6Q_PAD_SD3_DAT7__UART1_TX_DATA          0x2a8 0x690 0x000 0x1 0x0
+-#define MX6Q_PAD_SD3_DAT7__UART1_RX_DATA          0x2a8 0x690 0x920 0x1 0x2
+-#define MX6Q_PAD_SD3_DAT7__GPIO6_IO17             0x2a8 0x690 0x000 0x5 0x0
+-#define MX6Q_PAD_SD3_DAT6__SD3_DATA6              0x2ac 0x694 0x000 0x0 0x0
+-#define MX6Q_PAD_SD3_DAT6__UART1_RX_DATA          0x2ac 0x694 0x920 0x1 0x3
+-#define MX6Q_PAD_SD3_DAT6__UART1_TX_DATA          0x2ac 0x694 0x000 0x1 0x0
+-#define MX6Q_PAD_SD3_DAT6__GPIO6_IO18             0x2ac 0x694 0x000 0x5 0x0
+-#define MX6Q_PAD_SD3_DAT5__SD3_DATA5              0x2b0 0x698 0x000 0x0 0x0
+-#define MX6Q_PAD_SD3_DAT5__UART2_TX_DATA          0x2b0 0x698 0x000 0x1 0x0
+-#define MX6Q_PAD_SD3_DAT5__UART2_RX_DATA          0x2b0 0x698 0x928 0x1 0x4
+-#define MX6Q_PAD_SD3_DAT5__GPIO7_IO00             0x2b0 0x698 0x000 0x5 0x0
+-#define MX6Q_PAD_SD3_DAT4__SD3_DATA4              0x2b4 0x69c 0x000 0x0 0x0
+-#define MX6Q_PAD_SD3_DAT4__UART2_RX_DATA          0x2b4 0x69c 0x928 0x1 0x5
+-#define MX6Q_PAD_SD3_DAT4__UART2_TX_DATA          0x2b4 0x69c 0x000 0x1 0x0
+-#define MX6Q_PAD_SD3_DAT4__GPIO7_IO01             0x2b4 0x69c 0x000 0x5 0x0
+-#define MX6Q_PAD_SD3_CMD__SD3_CMD                 0x2b8 0x6a0 0x000 0x0 0x0
+-#define MX6Q_PAD_SD3_CMD__UART2_CTS_B             0x2b8 0x6a0 0x000 0x1 0x0
+-#define MX6Q_PAD_SD3_CMD__UART2_RTS_B             0x2b8 0x6a0 0x924 0x1 0x2
+-#define MX6Q_PAD_SD3_CMD__FLEXCAN1_TX             0x2b8 0x6a0 0x000 0x2 0x0
+-#define MX6Q_PAD_SD3_CMD__GPIO7_IO02              0x2b8 0x6a0 0x000 0x5 0x0
+-#define MX6Q_PAD_SD3_CLK__SD3_CLK                 0x2bc 0x6a4 0x000 0x0 0x0
+-#define MX6Q_PAD_SD3_CLK__UART2_RTS_B             0x2bc 0x6a4 0x924 0x1 0x3
+-#define MX6Q_PAD_SD3_CLK__UART2_CTS_B             0x2bc 0x6a4 0x000 0x1 0x0
+-#define MX6Q_PAD_SD3_CLK__FLEXCAN1_RX             0x2bc 0x6a4 0x7e4 0x2 0x2
+-#define MX6Q_PAD_SD3_CLK__GPIO7_IO03              0x2bc 0x6a4 0x000 0x5 0x0
+-#define MX6Q_PAD_SD3_DAT0__SD3_DATA0              0x2c0 0x6a8 0x000 0x0 0x0
+-#define MX6Q_PAD_SD3_DAT0__UART1_CTS_B            0x2c0 0x6a8 0x000 0x1 0x0
+-#define MX6Q_PAD_SD3_DAT0__UART1_RTS_B            0x2c0 0x6a8 0x91c 0x1 0x2
+-#define MX6Q_PAD_SD3_DAT0__FLEXCAN2_TX            0x2c0 0x6a8 0x000 0x2 0x0
+-#define MX6Q_PAD_SD3_DAT0__GPIO7_IO04             0x2c0 0x6a8 0x000 0x5 0x0
+-#define MX6Q_PAD_SD3_DAT1__SD3_DATA1              0x2c4 0x6ac 0x000 0x0 0x0
+-#define MX6Q_PAD_SD3_DAT1__UART1_RTS_B            0x2c4 0x6ac 0x91c 0x1 0x3
+-#define MX6Q_PAD_SD3_DAT1__UART1_CTS_B            0x2c4 0x6ac 0x000 0x1 0x0
+-#define MX6Q_PAD_SD3_DAT1__FLEXCAN2_RX            0x2c4 0x6ac 0x7e8 0x2 0x1
+-#define MX6Q_PAD_SD3_DAT1__GPIO7_IO05             0x2c4 0x6ac 0x000 0x5 0x0
+-#define MX6Q_PAD_SD3_DAT2__SD3_DATA2              0x2c8 0x6b0 0x000 0x0 0x0
+-#define MX6Q_PAD_SD3_DAT2__GPIO7_IO06             0x2c8 0x6b0 0x000 0x5 0x0
+-#define MX6Q_PAD_SD3_DAT3__SD3_DATA3              0x2cc 0x6b4 0x000 0x0 0x0
+-#define MX6Q_PAD_SD3_DAT3__UART3_CTS_B            0x2cc 0x6b4 0x000 0x1 0x0
+-#define MX6Q_PAD_SD3_DAT3__UART3_RTS_B            0x2cc 0x6b4 0x92c 0x1 0x4
+-#define MX6Q_PAD_SD3_DAT3__GPIO7_IO07             0x2cc 0x6b4 0x000 0x5 0x0
+-#define MX6Q_PAD_SD3_RST__SD3_RESET               0x2d0 0x6b8 0x000 0x0 0x0
+-#define MX6Q_PAD_SD3_RST__UART3_RTS_B             0x2d0 0x6b8 0x92c 0x1 0x5
+-#define MX6Q_PAD_SD3_RST__UART3_CTS_B             0x2d0 0x6b8 0x000 0x1 0x0
+-#define MX6Q_PAD_SD3_RST__GPIO7_IO08              0x2d0 0x6b8 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_CLE__NAND_CLE              0x2d4 0x6bc 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_CLE__IPU2_SISG4            0x2d4 0x6bc 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_CLE__GPIO6_IO07            0x2d4 0x6bc 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_ALE__NAND_ALE              0x2d8 0x6c0 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_ALE__SD4_RESET             0x2d8 0x6c0 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_ALE__GPIO6_IO08            0x2d8 0x6c0 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_WP_B__NAND_WP_B            0x2dc 0x6c4 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_WP_B__IPU2_SISG5           0x2dc 0x6c4 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_WP_B__GPIO6_IO09           0x2dc 0x6c4 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_RB0__NAND_READY_B          0x2e0 0x6c8 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN01        0x2e0 0x6c8 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_RB0__GPIO6_IO10            0x2e0 0x6c8 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_CS0__NAND_CE0_B            0x2e4 0x6cc 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_CS0__GPIO6_IO11            0x2e4 0x6cc 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_CS1__NAND_CE1_B            0x2e8 0x6d0 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_CS1__SD4_VSELECT           0x2e8 0x6d0 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_CS1__SD3_VSELECT           0x2e8 0x6d0 0x000 0x2 0x0
+-#define MX6Q_PAD_NANDF_CS1__GPIO6_IO14            0x2e8 0x6d0 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_CS2__NAND_CE2_B            0x2ec 0x6d4 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_CS2__IPU1_SISG0            0x2ec 0x6d4 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_CS2__ESAI_TX0              0x2ec 0x6d4 0x874 0x2 0x1
+-#define MX6Q_PAD_NANDF_CS2__EIM_CRE               0x2ec 0x6d4 0x000 0x3 0x0
+-#define MX6Q_PAD_NANDF_CS2__CCM_CLKO2             0x2ec 0x6d4 0x000 0x4 0x0
+-#define MX6Q_PAD_NANDF_CS2__GPIO6_IO15            0x2ec 0x6d4 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_CS2__IPU2_SISG0            0x2ec 0x6d4 0x000 0x6 0x0
+-#define MX6Q_PAD_NANDF_CS3__NAND_CE3_B            0x2f0 0x6d8 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_CS3__IPU1_SISG1            0x2f0 0x6d8 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_CS3__ESAI_TX1              0x2f0 0x6d8 0x878 0x2 0x1
+-#define MX6Q_PAD_NANDF_CS3__EIM_ADDR26            0x2f0 0x6d8 0x000 0x3 0x0
+-#define MX6Q_PAD_NANDF_CS3__GPIO6_IO16            0x2f0 0x6d8 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_CS3__IPU2_SISG1            0x2f0 0x6d8 0x000 0x6 0x0
+-#define MX6Q_PAD_SD4_CMD__SD4_CMD                 0x2f4 0x6dc 0x000 0x0 0x0
+-#define MX6Q_PAD_SD4_CMD__NAND_RE_B               0x2f4 0x6dc 0x000 0x1 0x0
+-#define MX6Q_PAD_SD4_CMD__UART3_TX_DATA           0x2f4 0x6dc 0x000 0x2 0x0
+-#define MX6Q_PAD_SD4_CMD__UART3_RX_DATA           0x2f4 0x6dc 0x930 0x2 0x2
+-#define MX6Q_PAD_SD4_CMD__GPIO7_IO09              0x2f4 0x6dc 0x000 0x5 0x0
+-#define MX6Q_PAD_SD4_CLK__SD4_CLK                 0x2f8 0x6e0 0x000 0x0 0x0
+-#define MX6Q_PAD_SD4_CLK__NAND_WE_B               0x2f8 0x6e0 0x000 0x1 0x0
+-#define MX6Q_PAD_SD4_CLK__UART3_RX_DATA           0x2f8 0x6e0 0x930 0x2 0x3
+-#define MX6Q_PAD_SD4_CLK__UART3_TX_DATA           0x2f8 0x6e0 0x000 0x2 0x0
+-#define MX6Q_PAD_SD4_CLK__GPIO7_IO10              0x2f8 0x6e0 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_D0__NAND_DATA00            0x2fc 0x6e4 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_D0__SD1_DATA4              0x2fc 0x6e4 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_D0__GPIO2_IO00             0x2fc 0x6e4 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_D1__NAND_DATA01            0x300 0x6e8 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_D1__SD1_DATA5              0x300 0x6e8 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_D1__GPIO2_IO01             0x300 0x6e8 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_D2__NAND_DATA02            0x304 0x6ec 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_D2__SD1_DATA6              0x304 0x6ec 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_D2__GPIO2_IO02             0x304 0x6ec 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_D3__NAND_DATA03            0x308 0x6f0 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_D3__SD1_DATA7              0x308 0x6f0 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_D3__GPIO2_IO03             0x308 0x6f0 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_D4__NAND_DATA04            0x30c 0x6f4 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_D4__SD2_DATA4              0x30c 0x6f4 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_D4__GPIO2_IO04             0x30c 0x6f4 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_D5__NAND_DATA05            0x310 0x6f8 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_D5__SD2_DATA5              0x310 0x6f8 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_D5__GPIO2_IO05             0x310 0x6f8 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_D6__NAND_DATA06            0x314 0x6fc 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_D6__SD2_DATA6              0x314 0x6fc 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_D6__GPIO2_IO06             0x314 0x6fc 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_D7__NAND_DATA07            0x318 0x700 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_D7__SD2_DATA7              0x318 0x700 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_D7__GPIO2_IO07             0x318 0x700 0x000 0x5 0x0
+-#define MX6Q_PAD_SD4_DAT0__SD4_DATA0              0x31c 0x704 0x000 0x1 0x0
+-#define MX6Q_PAD_SD4_DAT0__NAND_DQS               0x31c 0x704 0x000 0x2 0x0
+-#define MX6Q_PAD_SD4_DAT0__GPIO2_IO08             0x31c 0x704 0x000 0x5 0x0
+-#define MX6Q_PAD_SD4_DAT1__SD4_DATA1              0x320 0x708 0x000 0x1 0x0
+-#define MX6Q_PAD_SD4_DAT1__PWM3_OUT               0x320 0x708 0x000 0x2 0x0
+-#define MX6Q_PAD_SD4_DAT1__GPIO2_IO09             0x320 0x708 0x000 0x5 0x0
+-#define MX6Q_PAD_SD4_DAT2__SD4_DATA2              0x324 0x70c 0x000 0x1 0x0
+-#define MX6Q_PAD_SD4_DAT2__PWM4_OUT               0x324 0x70c 0x000 0x2 0x0
+-#define MX6Q_PAD_SD4_DAT2__GPIO2_IO10             0x324 0x70c 0x000 0x5 0x0
+-#define MX6Q_PAD_SD4_DAT3__SD4_DATA3              0x328 0x710 0x000 0x1 0x0
+-#define MX6Q_PAD_SD4_DAT3__GPIO2_IO11             0x328 0x710 0x000 0x5 0x0
+-#define MX6Q_PAD_SD4_DAT4__SD4_DATA4              0x32c 0x714 0x000 0x1 0x0
+-#define MX6Q_PAD_SD4_DAT4__UART2_RX_DATA          0x32c 0x714 0x928 0x2 0x6
+-#define MX6Q_PAD_SD4_DAT4__UART2_TX_DATA          0x32c 0x714 0x000 0x2 0x0
+-#define MX6Q_PAD_SD4_DAT4__GPIO2_IO12             0x32c 0x714 0x000 0x5 0x0
+-#define MX6Q_PAD_SD4_DAT5__SD4_DATA5              0x330 0x718 0x000 0x1 0x0
+-#define MX6Q_PAD_SD4_DAT5__UART2_RTS_B            0x330 0x718 0x924 0x2 0x4
+-#define MX6Q_PAD_SD4_DAT5__UART2_CTS_B            0x330 0x718 0x000 0x2 0x0
+-#define MX6Q_PAD_SD4_DAT5__GPIO2_IO13             0x330 0x718 0x000 0x5 0x0
+-#define MX6Q_PAD_SD4_DAT6__SD4_DATA6              0x334 0x71c 0x000 0x1 0x0
+-#define MX6Q_PAD_SD4_DAT6__UART2_CTS_B            0x334 0x71c 0x000 0x2 0x0
+-#define MX6Q_PAD_SD4_DAT6__UART2_RTS_B            0x334 0x71c 0x924 0x2 0x5
+-#define MX6Q_PAD_SD4_DAT6__GPIO2_IO14             0x334 0x71c 0x000 0x5 0x0
+-#define MX6Q_PAD_SD4_DAT7__SD4_DATA7              0x338 0x720 0x000 0x1 0x0
+-#define MX6Q_PAD_SD4_DAT7__UART2_TX_DATA          0x338 0x720 0x000 0x2 0x0
+-#define MX6Q_PAD_SD4_DAT7__UART2_RX_DATA          0x338 0x720 0x928 0x2 0x7
+-#define MX6Q_PAD_SD4_DAT7__GPIO2_IO15             0x338 0x720 0x000 0x5 0x0
+-#define MX6Q_PAD_SD1_DAT1__SD1_DATA1              0x33c 0x724 0x000 0x0 0x0
+-#define MX6Q_PAD_SD1_DAT1__ECSPI5_SS0             0x33c 0x724 0x834 0x1 0x1
+-#define MX6Q_PAD_SD1_DAT1__PWM3_OUT               0x33c 0x724 0x000 0x2 0x0
+-#define MX6Q_PAD_SD1_DAT1__GPT_CAPTURE2           0x33c 0x724 0x000 0x3 0x0
+-#define MX6Q_PAD_SD1_DAT1__GPIO1_IO17             0x33c 0x724 0x000 0x5 0x0
+-#define MX6Q_PAD_SD1_DAT0__SD1_DATA0              0x340 0x728 0x000 0x0 0x0
+-#define MX6Q_PAD_SD1_DAT0__ECSPI5_MISO            0x340 0x728 0x82c 0x1 0x1
+-#define MX6Q_PAD_SD1_DAT0__GPT_CAPTURE1           0x340 0x728 0x000 0x3 0x0
+-#define MX6Q_PAD_SD1_DAT0__GPIO1_IO16             0x340 0x728 0x000 0x5 0x0
+-#define MX6Q_PAD_SD1_DAT3__SD1_DATA3              0x344 0x72c 0x000 0x0 0x0
+-#define MX6Q_PAD_SD1_DAT3__ECSPI5_SS2             0x344 0x72c 0x000 0x1 0x0
+-#define MX6Q_PAD_SD1_DAT3__GPT_COMPARE3           0x344 0x72c 0x000 0x2 0x0
+-#define MX6Q_PAD_SD1_DAT3__PWM1_OUT               0x344 0x72c 0x000 0x3 0x0
+-#define MX6Q_PAD_SD1_DAT3__WDOG2_B                0x344 0x72c 0x000 0x4 0x0
+-#define MX6Q_PAD_SD1_DAT3__GPIO1_IO21             0x344 0x72c 0x000 0x5 0x0
+-#define MX6Q_PAD_SD1_DAT3__WDOG2_RESET_B_DEB      0x344 0x72c 0x000 0x6 0x0
+-#define MX6Q_PAD_SD1_CMD__SD1_CMD                 0x348 0x730 0x000 0x0 0x0
+-#define MX6Q_PAD_SD1_CMD__ECSPI5_MOSI             0x348 0x730 0x830 0x1 0x0
+-#define MX6Q_PAD_SD1_CMD__PWM4_OUT                0x348 0x730 0x000 0x2 0x0
+-#define MX6Q_PAD_SD1_CMD__GPT_COMPARE1            0x348 0x730 0x000 0x3 0x0
+-#define MX6Q_PAD_SD1_CMD__GPIO1_IO18              0x348 0x730 0x000 0x5 0x0
+-#define MX6Q_PAD_SD1_DAT2__SD1_DATA2              0x34c 0x734 0x000 0x0 0x0
+-#define MX6Q_PAD_SD1_DAT2__ECSPI5_SS1             0x34c 0x734 0x838 0x1 0x1
+-#define MX6Q_PAD_SD1_DAT2__GPT_COMPARE2           0x34c 0x734 0x000 0x2 0x0
+-#define MX6Q_PAD_SD1_DAT2__PWM2_OUT               0x34c 0x734 0x000 0x3 0x0
+-#define MX6Q_PAD_SD1_DAT2__WDOG1_B                0x34c 0x734 0x000 0x4 0x0
+-#define MX6Q_PAD_SD1_DAT2__GPIO1_IO19             0x34c 0x734 0x000 0x5 0x0
+-#define MX6Q_PAD_SD1_DAT2__WDOG1_RESET_B_DEB      0x34c 0x734 0x000 0x6 0x0
+-#define MX6Q_PAD_SD1_CLK__SD1_CLK                 0x350 0x738 0x000 0x0 0x0
+-#define MX6Q_PAD_SD1_CLK__ECSPI5_SCLK             0x350 0x738 0x828 0x1 0x0
+-#define MX6Q_PAD_SD1_CLK__GPT_CLKIN               0x350 0x738 0x000 0x3 0x0
+-#define MX6Q_PAD_SD1_CLK__GPIO1_IO20              0x350 0x738 0x000 0x5 0x0
+-#define MX6Q_PAD_SD2_CLK__SD2_CLK                 0x354 0x73c 0x000 0x0 0x0
+-#define MX6Q_PAD_SD2_CLK__ECSPI5_SCLK             0x354 0x73c 0x828 0x1 0x1
+-#define MX6Q_PAD_SD2_CLK__KEY_COL5                0x354 0x73c 0x8e8 0x2 0x3
+-#define MX6Q_PAD_SD2_CLK__AUD4_RXFS               0x354 0x73c 0x7c0 0x3 0x1
+-#define MX6Q_PAD_SD2_CLK__GPIO1_IO10              0x354 0x73c 0x000 0x5 0x0
+-#define MX6Q_PAD_SD2_CMD__SD2_CMD                 0x358 0x740 0x000 0x0 0x0
+-#define MX6Q_PAD_SD2_CMD__ECSPI5_MOSI             0x358 0x740 0x830 0x1 0x1
+-#define MX6Q_PAD_SD2_CMD__KEY_ROW5                0x358 0x740 0x8f4 0x2 0x2
+-#define MX6Q_PAD_SD2_CMD__AUD4_RXC                0x358 0x740 0x7bc 0x3 0x1
+-#define MX6Q_PAD_SD2_CMD__GPIO1_IO11              0x358 0x740 0x000 0x5 0x0
+-#define MX6Q_PAD_SD2_DAT3__SD2_DATA3              0x35c 0x744 0x000 0x0 0x0
+-#define MX6Q_PAD_SD2_DAT3__ECSPI5_SS3             0x35c 0x744 0x000 0x1 0x0
+-#define MX6Q_PAD_SD2_DAT3__KEY_COL6               0x35c 0x744 0x8ec 0x2 0x2
+-#define MX6Q_PAD_SD2_DAT3__AUD4_TXC               0x35c 0x744 0x7c4 0x3 0x1
+-#define MX6Q_PAD_SD2_DAT3__GPIO1_IO12             0x35c 0x744 0x000 0x5 0x0
++#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1              0x04c 0x360 0x000 0x0 0x0
++#define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0             0x04c 0x360 0x834 0x1 0x0
++#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B              0x04c 0x360 0x000 0x2 0x0
++#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS              0x04c 0x360 0x7c8 0x3 0x0
++#define MX6QDL_PAD_SD2_DAT1__KEY_COL7               0x04c 0x360 0x8f0 0x4 0x0
++#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14             0x04c 0x360 0x000 0x5 0x0
++#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2              0x050 0x364 0x000 0x0 0x0
++#define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1             0x050 0x364 0x838 0x1 0x0
++#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B              0x050 0x364 0x000 0x2 0x0
++#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD               0x050 0x364 0x7b8 0x3 0x0
++#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6               0x050 0x364 0x8f8 0x4 0x0
++#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13             0x050 0x364 0x000 0x5 0x0
++#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0              0x054 0x368 0x000 0x0 0x0
++#define MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO            0x054 0x368 0x82c 0x1 0x0
++#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD               0x054 0x368 0x7b4 0x3 0x0
++#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7               0x054 0x368 0x8fc 0x4 0x0
++#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15             0x054 0x368 0x000 0x5 0x0
++#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT              0x054 0x368 0x000 0x6 0x0
++#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA           0x058 0x36c 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC             0x058 0x36c 0x000 0x1 0x0
++#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK         0x058 0x36c 0x918 0x2 0x0
++#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19            0x058 0x36c 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M   0x058 0x36c 0x000 0x7 0x0
++#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY          0x05c 0x370 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0             0x05c 0x370 0x000 0x1 0x0
++#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20            0x05c 0x370 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG           0x060 0x374 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1             0x060 0x374 0x000 0x1 0x0
++#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21            0x060 0x374 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA           0x064 0x378 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2             0x064 0x378 0x000 0x1 0x0
++#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22            0x064 0x378 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE           0x068 0x37c 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3             0x068 0x37c 0x000 0x1 0x0
++#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23            0x068 0x37c 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA        0x06c 0x380 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL       0x06c 0x380 0x858 0x1 0x0
++#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24         0x06c 0x380 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY          0x070 0x384 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0             0x070 0x384 0x848 0x1 0x0
++#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25            0x070 0x384 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE      0x074 0x388 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL       0x074 0x388 0x000 0x1 0x0
++#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26         0x074 0x388 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK       0x074 0x388 0x83c 0x7 0x0
++#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG           0x078 0x38c 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1             0x078 0x38c 0x84c 0x1 0x0
++#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27            0x078 0x38c 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA           0x07c 0x390 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2             0x07c 0x390 0x850 0x1 0x0
++#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28            0x07c 0x390 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE           0x080 0x394 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3             0x080 0x394 0x854 0x1 0x0
++#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29            0x080 0x394 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE         0x084 0x398 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC             0x084 0x398 0x844 0x1 0x0
++#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30            0x084 0x398 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A25__EIM_ADDR25              0x088 0x39c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1              0x088 0x39c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY              0x088 0x39c 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12          0x088 0x39c 0x000 0x3 0x0
++#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS          0x088 0x39c 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_A25__GPIO5_IO02              0x088 0x39c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE        0x088 0x39c 0x88c 0x6 0x0
++#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B               0x08c 0x3a0 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0              0x08c 0x3a0 0x800 0x1 0x0
++#define MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19        0x08c 0x3a0 0x8d4 0x3 0x0
++#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL         0x08c 0x3a0 0x890 0x4 0x0
++#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30              0x08c 0x3a0 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_EB2__I2C2_SCL                0x08c 0x3a0 0x8a0 0x6 0x0
++#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30          0x08c 0x3a0 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D16__EIM_DATA16              0x090 0x3a4 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK             0x090 0x3a4 0x7f4 0x1 0x0
++#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05          0x090 0x3a4 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18        0x090 0x3a4 0x8d0 0x3 0x0
++#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA         0x090 0x3a4 0x894 0x4 0x0
++#define MX6QDL_PAD_EIM_D16__GPIO3_IO16              0x090 0x3a4 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D16__I2C2_SDA                0x090 0x3a4 0x8a4 0x6 0x0
++#define MX6QDL_PAD_EIM_D17__EIM_DATA17              0x094 0x3a8 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO             0x094 0x3a8 0x7f8 0x1 0x0
++#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06          0x094 0x3a8 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK        0x094 0x3a8 0x8e0 0x3 0x0
++#define MX6QDL_PAD_EIM_D17__DCIC1_OUT               0x094 0x3a8 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D17__GPIO3_IO17              0x094 0x3a8 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D17__I2C3_SCL                0x094 0x3a8 0x8a8 0x6 0x0
++#define MX6QDL_PAD_EIM_D18__EIM_DATA18              0x098 0x3ac 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI             0x098 0x3ac 0x7fc 0x1 0x0
++#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07          0x098 0x3ac 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17        0x098 0x3ac 0x8cc 0x3 0x0
++#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS          0x098 0x3ac 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D18__GPIO3_IO18              0x098 0x3ac 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D18__I2C3_SDA                0x098 0x3ac 0x8ac 0x6 0x0
++#define MX6QDL_PAD_EIM_D19__EIM_DATA19              0x09c 0x3b0 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1              0x09c 0x3b0 0x804 0x1 0x0
++#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08          0x09c 0x3b0 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16        0x09c 0x3b0 0x8c8 0x3 0x0
++#define MX6QDL_PAD_EIM_D19__UART1_CTS_B             0x09c 0x3b0 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D19__UART1_RTS_B             0x09c 0x3b0 0x91c 0x4 0x0
++#define MX6QDL_PAD_EIM_D19__GPIO3_IO19              0x09c 0x3b0 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D19__EPIT1_OUT               0x09c 0x3b0 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D20__EIM_DATA20              0x0a0 0x3b4 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0              0x0a0 0x3b4 0x824 0x1 0x0
++#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16          0x0a0 0x3b4 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15        0x0a0 0x3b4 0x8c4 0x3 0x0
++#define MX6QDL_PAD_EIM_D20__UART1_RTS_B             0x0a0 0x3b4 0x91c 0x4 0x1
++#define MX6QDL_PAD_EIM_D20__UART1_CTS_B             0x0a0 0x3b4 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D20__GPIO3_IO20              0x0a0 0x3b4 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D20__EPIT2_OUT               0x0a0 0x3b4 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D21__EIM_DATA21              0x0a4 0x3b8 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK             0x0a4 0x3b8 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17          0x0a4 0x3b8 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D21__IPU2_CSI1_DATA11        0x0a4 0x3b8 0x8b4 0x3 0x0
++#define MX6QDL_PAD_EIM_D21__USB_OTG_OC              0x0a4 0x3b8 0x944 0x4 0x0
++#define MX6QDL_PAD_EIM_D21__GPIO3_IO21              0x0a4 0x3b8 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D21__I2C1_SCL                0x0a4 0x3b8 0x898 0x6 0x0
++#define MX6QDL_PAD_EIM_D21__SPDIF_IN                0x0a4 0x3b8 0x914 0x7 0x0
++#define MX6QDL_PAD_EIM_D22__EIM_DATA22              0x0a8 0x3bc 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO             0x0a8 0x3bc 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01          0x0a8 0x3bc 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D22__IPU2_CSI1_DATA10        0x0a8 0x3bc 0x8b0 0x3 0x0
++#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR             0x0a8 0x3bc 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D22__GPIO3_IO22              0x0a8 0x3bc 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D22__SPDIF_OUT               0x0a8 0x3bc 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D23__EIM_DATA23              0x0ac 0x3c0 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS          0x0ac 0x3c0 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D23__UART3_CTS_B             0x0ac 0x3c0 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D23__UART3_RTS_B             0x0ac 0x3c0 0x92c 0x2 0x0
++#define MX6QDL_PAD_EIM_D23__UART1_DCD_B             0x0ac 0x3c0 0x000 0x3 0x0
++#define MX6QDL_PAD_EIM_D23__IPU2_CSI1_DATA_EN       0x0ac 0x3c0 0x8d8 0x4 0x0
++#define MX6QDL_PAD_EIM_D23__GPIO3_IO23              0x0ac 0x3c0 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02          0x0ac 0x3c0 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14          0x0ac 0x3c0 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B               0x0b0 0x3c4 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY              0x0b0 0x3c4 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B             0x0b0 0x3c4 0x92c 0x2 0x1
++#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B             0x0b0 0x3c4 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_EB3__UART1_RI_B              0x0b0 0x3c4 0x000 0x3 0x0
++#define MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC         0x0b0 0x3c4 0x8dc 0x4 0x0
++#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31              0x0b0 0x3c4 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03          0x0b0 0x3c4 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31          0x0b0 0x3c4 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D24__EIM_DATA24              0x0b4 0x3c8 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2              0x0b4 0x3c8 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA           0x0b4 0x3c8 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA           0x0b4 0x3c8 0x930 0x2 0x0
++#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2              0x0b4 0x3c8 0x808 0x3 0x0
++#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2              0x0b4 0x3c8 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D24__GPIO3_IO24              0x0b4 0x3c8 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D24__AUD5_RXFS               0x0b4 0x3c8 0x7d8 0x6 0x0
++#define MX6QDL_PAD_EIM_D24__UART1_DTR_B             0x0b4 0x3c8 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D25__EIM_DATA25              0x0b8 0x3cc 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3              0x0b8 0x3cc 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA           0x0b8 0x3cc 0x930 0x2 0x1
++#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA           0x0b8 0x3cc 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3              0x0b8 0x3cc 0x80c 0x3 0x0
++#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3              0x0b8 0x3cc 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D25__GPIO3_IO25              0x0b8 0x3cc 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D25__AUD5_RXC                0x0b8 0x3cc 0x7d4 0x6 0x0
++#define MX6QDL_PAD_EIM_D25__UART1_DSR_B             0x0b8 0x3cc 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D26__EIM_DATA26              0x0bc 0x3d0 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11          0x0bc 0x3d0 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01        0x0bc 0x3d0 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14        0x0bc 0x3d0 0x8c0 0x3 0x0
++#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA           0x0bc 0x3d0 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA           0x0bc 0x3d0 0x928 0x4 0x0
++#define MX6QDL_PAD_EIM_D26__GPIO3_IO26              0x0bc 0x3d0 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D26__IPU1_SISG2              0x0bc 0x3d0 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22       0x0bc 0x3d0 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D27__EIM_DATA27              0x0c0 0x3d4 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13          0x0c0 0x3d4 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00        0x0c0 0x3d4 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13        0x0c0 0x3d4 0x8bc 0x3 0x0
++#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA           0x0c0 0x3d4 0x928 0x4 0x1
++#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA           0x0c0 0x3d4 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D27__GPIO3_IO27              0x0c0 0x3d4 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D27__IPU1_SISG3              0x0c0 0x3d4 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23       0x0c0 0x3d4 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D28__EIM_DATA28              0x0c4 0x3d8 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D28__I2C1_SDA                0x0c4 0x3d8 0x89c 0x1 0x0
++#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI             0x0c4 0x3d8 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D28__IPU2_CSI1_DATA12        0x0c4 0x3d8 0x8b8 0x3 0x0
++#define MX6QDL_PAD_EIM_D28__UART2_CTS_B             0x0c4 0x3d8 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D28__UART2_RTS_B             0x0c4 0x3d8 0x924 0x4 0x0
++#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B         0x0c4 0x3d8 0x924 0x4 0x0
++#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B         0x0c4 0x3d8 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D28__GPIO3_IO28              0x0c4 0x3d8 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG           0x0c4 0x3d8 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13          0x0c4 0x3d8 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D29__EIM_DATA29              0x0c8 0x3dc 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15          0x0c8 0x3dc 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0              0x0c8 0x3dc 0x824 0x2 0x1
++#define MX6QDL_PAD_EIM_D29__UART2_RTS_B             0x0c8 0x3dc 0x924 0x4 0x1
++#define MX6QDL_PAD_EIM_D29__UART2_CTS_B             0x0c8 0x3dc 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B         0x0c8 0x3dc 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B         0x0c8 0x3dc 0x924 0x4 0x1
++#define MX6QDL_PAD_EIM_D29__GPIO3_IO29              0x0c8 0x3dc 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC         0x0c8 0x3dc 0x8e4 0x6 0x0
++#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14          0x0c8 0x3dc 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D30__EIM_DATA30              0x0cc 0x3e0 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21       0x0cc 0x3e0 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11          0x0cc 0x3e0 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03        0x0cc 0x3e0 0x000 0x3 0x0
++#define MX6QDL_PAD_EIM_D30__UART3_CTS_B             0x0cc 0x3e0 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D30__UART3_RTS_B             0x0cc 0x3e0 0x92c 0x4 0x2
++#define MX6QDL_PAD_EIM_D30__GPIO3_IO30              0x0cc 0x3e0 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D30__USB_H1_OC               0x0cc 0x3e0 0x948 0x6 0x0
++#define MX6QDL_PAD_EIM_D31__EIM_DATA31              0x0d0 0x3e4 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20       0x0d0 0x3e4 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12          0x0d0 0x3e4 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02        0x0d0 0x3e4 0x000 0x3 0x0
++#define MX6QDL_PAD_EIM_D31__UART3_RTS_B             0x0d0 0x3e4 0x92c 0x4 0x3
++#define MX6QDL_PAD_EIM_D31__UART3_CTS_B             0x0d0 0x3e4 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D31__GPIO3_IO31              0x0d0 0x3e4 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D31__USB_H1_PWR              0x0d0 0x3e4 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_A24__EIM_ADDR24              0x0d4 0x3e8 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19       0x0d4 0x3e8 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19        0x0d4 0x3e8 0x8d4 0x2 0x1
++#define MX6QDL_PAD_EIM_A24__IPU2_SISG2              0x0d4 0x3e8 0x000 0x3 0x0
++#define MX6QDL_PAD_EIM_A24__IPU1_SISG2              0x0d4 0x3e8 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_A24__GPIO5_IO04              0x0d4 0x3e8 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24          0x0d4 0x3e8 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A23__EIM_ADDR23              0x0d8 0x3ec 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18       0x0d8 0x3ec 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18        0x0d8 0x3ec 0x8d0 0x2 0x1
++#define MX6QDL_PAD_EIM_A23__IPU2_SISG3              0x0d8 0x3ec 0x000 0x3 0x0
++#define MX6QDL_PAD_EIM_A23__IPU1_SISG3              0x0d8 0x3ec 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_A23__GPIO6_IO06              0x0d8 0x3ec 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23          0x0d8 0x3ec 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A22__EIM_ADDR22              0x0dc 0x3f0 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17       0x0dc 0x3f0 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17        0x0dc 0x3f0 0x8cc 0x2 0x1
++#define MX6QDL_PAD_EIM_A22__GPIO2_IO16              0x0dc 0x3f0 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22          0x0dc 0x3f0 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A21__EIM_ADDR21              0x0e0 0x3f4 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16       0x0e0 0x3f4 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16        0x0e0 0x3f4 0x8c8 0x2 0x1
++#define MX6QDL_PAD_EIM_A21__GPIO2_IO17              0x0e0 0x3f4 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21          0x0e0 0x3f4 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A20__EIM_ADDR20              0x0e4 0x3f8 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15       0x0e4 0x3f8 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15        0x0e4 0x3f8 0x8c4 0x2 0x1
++#define MX6QDL_PAD_EIM_A20__GPIO2_IO18              0x0e4 0x3f8 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20          0x0e4 0x3f8 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A19__EIM_ADDR19              0x0e8 0x3fc 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14       0x0e8 0x3fc 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14        0x0e8 0x3fc 0x8c0 0x2 0x1
++#define MX6QDL_PAD_EIM_A19__GPIO2_IO19              0x0e8 0x3fc 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19          0x0e8 0x3fc 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A18__EIM_ADDR18              0x0ec 0x400 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13       0x0ec 0x400 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13        0x0ec 0x400 0x8bc 0x2 0x1
++#define MX6QDL_PAD_EIM_A18__GPIO2_IO20              0x0ec 0x400 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18          0x0ec 0x400 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A17__EIM_ADDR17              0x0f0 0x404 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12       0x0f0 0x404 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12        0x0f0 0x404 0x8b8 0x2 0x1
++#define MX6QDL_PAD_EIM_A17__GPIO2_IO21              0x0f0 0x404 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17          0x0f0 0x404 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A16__EIM_ADDR16              0x0f4 0x408 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK       0x0f4 0x408 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK        0x0f4 0x408 0x8e0 0x2 0x1
++#define MX6QDL_PAD_EIM_A16__GPIO2_IO22              0x0f4 0x408 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16          0x0f4 0x408 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B               0x0f8 0x40c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05          0x0f8 0x40c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK             0x0f8 0x40c 0x810 0x2 0x0
++#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23              0x0f8 0x40c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B               0x0fc 0x410 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06          0x0fc 0x410 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI             0x0fc 0x410 0x818 0x2 0x0
++#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24              0x0fc 0x410 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_OE__EIM_OE_B                 0x100 0x414 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07           0x100 0x414 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO              0x100 0x414 0x814 0x2 0x0
++#define MX6QDL_PAD_EIM_OE__GPIO2_IO25               0x100 0x414 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_RW__EIM_RW                   0x104 0x418 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08           0x104 0x418 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0               0x104 0x418 0x81c 0x2 0x0
++#define MX6QDL_PAD_EIM_RW__GPIO2_IO26               0x104 0x418 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29           0x104 0x418 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B               0x108 0x41c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17          0x108 0x41c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1              0x108 0x41c 0x820 0x2 0x0
++#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27              0x108 0x41c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26          0x108 0x41c 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B               0x10c 0x420 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11       0x10c 0x420 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_EB0__IPU2_CSI1_DATA11        0x10c 0x420 0x8b4 0x2 0x1
++#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY          0x10c 0x420 0x7f0 0x4 0x0
++#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28              0x10c 0x420 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27          0x10c 0x420 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B               0x110 0x424 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10       0x110 0x424 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_EB1__IPU2_CSI1_DATA10        0x110 0x424 0x8b0 0x2 0x1
++#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29              0x110 0x424 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28          0x110 0x424 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA0__EIM_AD00                0x114 0x428 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09       0x114 0x428 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA0__IPU2_CSI1_DATA09        0x114 0x428 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00              0x114 0x428 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00          0x114 0x428 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA1__EIM_AD01                0x118 0x42c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08       0x118 0x42c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA1__IPU2_CSI1_DATA08        0x118 0x42c 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01              0x118 0x42c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01          0x118 0x42c 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA2__EIM_AD02                0x11c 0x430 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07       0x11c 0x430 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA2__IPU2_CSI1_DATA07        0x11c 0x430 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02              0x11c 0x430 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02          0x11c 0x430 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA3__EIM_AD03                0x120 0x434 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06       0x120 0x434 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA3__IPU2_CSI1_DATA06        0x120 0x434 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03              0x120 0x434 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03          0x120 0x434 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA4__EIM_AD04                0x124 0x438 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05       0x124 0x438 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA4__IPU2_CSI1_DATA05        0x124 0x438 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04              0x124 0x438 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04          0x124 0x438 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA5__EIM_AD05                0x128 0x43c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04       0x128 0x43c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04        0x128 0x43c 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05              0x128 0x43c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05          0x128 0x43c 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA6__EIM_AD06                0x12c 0x440 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03       0x12c 0x440 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA6__IPU2_CSI1_DATA03        0x12c 0x440 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06              0x12c 0x440 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06          0x12c 0x440 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA7__EIM_AD07                0x130 0x444 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02       0x130 0x444 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA7__IPU2_CSI1_DATA02        0x130 0x444 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07              0x130 0x444 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07          0x130 0x444 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA8__EIM_AD08                0x134 0x448 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01       0x134 0x448 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA8__IPU2_CSI1_DATA01        0x134 0x448 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08              0x134 0x448 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08          0x134 0x448 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA9__EIM_AD09                0x138 0x44c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00       0x138 0x44c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA9__IPU2_CSI1_DATA00        0x138 0x44c 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09              0x138 0x44c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09          0x138 0x44c 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA10__EIM_AD10               0x13c 0x450 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15         0x13c 0x450 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN      0x13c 0x450 0x8d8 0x2 0x1
++#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10             0x13c 0x450 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10         0x13c 0x450 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA11__EIM_AD11               0x140 0x454 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02         0x140 0x454 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC        0x140 0x454 0x8dc 0x2 0x1
++#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11             0x140 0x454 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11         0x140 0x454 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA12__EIM_AD12               0x144 0x458 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03         0x144 0x458 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC        0x144 0x458 0x8e4 0x2 0x1
++#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12             0x144 0x458 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12         0x144 0x458 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA13__EIM_AD13               0x148 0x45c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS         0x148 0x45c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13             0x148 0x45c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13         0x148 0x45c 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA14__EIM_AD14               0x14c 0x460 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS         0x14c 0x460 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14             0x14c 0x460 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14         0x14c 0x460 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA15__EIM_AD15               0x150 0x464 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01         0x150 0x464 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04         0x150 0x464 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15             0x150 0x464 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15         0x150 0x464 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B             0x154 0x468 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B            0x154 0x468 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00             0x154 0x468 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25         0x154 0x468 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK               0x158 0x46c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16         0x158 0x46c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31             0x158 0x46c 0x000 0x5 0x0
++#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK  0x15c 0x470 0x000 0x0 0x0
++#define MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK  0x15c 0x470 0x000 0x1 0x0
++#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16         0x15c 0x470 0x000 0x5 0x0
++#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15        0x160 0x474 0x000 0x0 0x0
++#define MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15        0x160 0x474 0x000 0x1 0x0
++#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC              0x160 0x474 0x000 0x2 0x0
++#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17            0x160 0x474 0x000 0x5 0x0
++#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02         0x164 0x478 0x000 0x0 0x0
++#define MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02         0x164 0x478 0x000 0x1 0x0
++#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD               0x164 0x478 0x000 0x2 0x0
++#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18             0x164 0x478 0x000 0x5 0x0
++#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03         0x168 0x47c 0x000 0x0 0x0
++#define MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03         0x168 0x47c 0x000 0x1 0x0
++#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS              0x168 0x47c 0x000 0x2 0x0
++#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19             0x168 0x47c 0x000 0x5 0x0
++#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04         0x16c 0x480 0x000 0x0 0x0
++#define MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04         0x16c 0x480 0x000 0x1 0x0
++#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD               0x16c 0x480 0x000 0x2 0x0
++#define MX6QDL_PAD_DI0_PIN4__SD1_WP                 0x16c 0x480 0x94c 0x3 0x0
++#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20             0x16c 0x480 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00    0x170 0x484 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00    0x170 0x484 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK          0x170 0x484 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21           0x170 0x484 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01    0x174 0x488 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01    0x174 0x488 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI          0x174 0x488 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22           0x174 0x488 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02    0x178 0x48c 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02    0x178 0x48c 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO          0x178 0x48c 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23           0x178 0x48c 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03    0x17c 0x490 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03    0x17c 0x490 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0           0x17c 0x490 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24           0x17c 0x490 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04    0x180 0x494 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04    0x180 0x494 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1           0x180 0x494 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25           0x180 0x494 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05    0x184 0x498 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05    0x184 0x498 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2           0x184 0x498 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS            0x184 0x498 0x000 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26           0x184 0x498 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06    0x188 0x49c 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06    0x188 0x49c 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3           0x188 0x49c 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC             0x188 0x49c 0x000 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27           0x188 0x49c 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07    0x18c 0x4a0 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07    0x18c 0x4a0 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY           0x18c 0x4a0 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28           0x18c 0x4a0 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08    0x190 0x4a4 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08    0x190 0x4a4 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT             0x190 0x4a4 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B              0x190 0x4a4 0x000 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29           0x190 0x4a4 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09    0x194 0x4a8 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09    0x194 0x4a8 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT             0x194 0x4a8 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B              0x194 0x4a8 0x000 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30           0x194 0x4a8 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10   0x198 0x4ac 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10   0x198 0x4ac 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31          0x198 0x4ac 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11   0x19c 0x4b0 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11   0x19c 0x4b0 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05          0x19c 0x4b0 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12   0x1a0 0x4b4 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12   0x1a0 0x4b4 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06          0x1a0 0x4b4 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13   0x1a4 0x4b8 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13   0x1a4 0x4b8 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS           0x1a4 0x4b8 0x7d8 0x3 0x1
++#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07          0x1a4 0x4b8 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14   0x1a8 0x4bc 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14   0x1a8 0x4bc 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC            0x1a8 0x4bc 0x7d4 0x3 0x1
++#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08          0x1a8 0x4bc 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15   0x1ac 0x4c0 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15   0x1ac 0x4c0 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1          0x1ac 0x4c0 0x804 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1          0x1ac 0x4c0 0x820 0x3 0x1
++#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09          0x1ac 0x4c0 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16   0x1b0 0x4c4 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16   0x1b0 0x4c4 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI         0x1b0 0x4c4 0x818 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC            0x1b0 0x4c4 0x7dc 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0     0x1b0 0x4c4 0x90c 0x4 0x0
++#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10          0x1b0 0x4c4 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17   0x1b4 0x4c8 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17   0x1b4 0x4c8 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO         0x1b4 0x4c8 0x814 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD            0x1b4 0x4c8 0x7d0 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1     0x1b4 0x4c8 0x910 0x4 0x0
++#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11          0x1b4 0x4c8 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18   0x1b8 0x4cc 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18   0x1b8 0x4cc 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0          0x1b8 0x4cc 0x81c 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS           0x1b8 0x4cc 0x7e0 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS           0x1b8 0x4cc 0x7c0 0x4 0x0
++#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12          0x1b8 0x4cc 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B           0x1b8 0x4cc 0x000 0x7 0x0
++#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19   0x1bc 0x4d0 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19   0x1bc 0x4d0 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK         0x1bc 0x4d0 0x810 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD            0x1bc 0x4d0 0x7cc 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC            0x1bc 0x4d0 0x7bc 0x4 0x0
++#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13          0x1bc 0x4d0 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B           0x1bc 0x4d0 0x000 0x7 0x0
++#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20   0x1c0 0x4d4 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20   0x1c0 0x4d4 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK         0x1c0 0x4d4 0x7f4 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC            0x1c0 0x4d4 0x7c4 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14          0x1c0 0x4d4 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21   0x1c4 0x4d8 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21   0x1c4 0x4d8 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI         0x1c4 0x4d8 0x7fc 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD            0x1c4 0x4d8 0x7b8 0x3 0x1
++#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15          0x1c4 0x4d8 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22   0x1c8 0x4dc 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22   0x1c8 0x4dc 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO         0x1c8 0x4dc 0x7f8 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS           0x1c8 0x4dc 0x7c8 0x3 0x1
++#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16          0x1c8 0x4dc 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23   0x1cc 0x4e0 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23   0x1cc 0x4e0 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0          0x1cc 0x4e0 0x800 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD            0x1cc 0x4e0 0x7b4 0x3 0x1
++#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17          0x1cc 0x4e0 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO             0x1d0 0x4e4 0x840 0x1 0x0
++#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK           0x1d0 0x4e4 0x86c 0x2 0x0
++#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT  0x1d0 0x4e4 0x000 0x4 0x0
++#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22            0x1d0 0x4e4 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK            0x1d0 0x4e4 0x000 0x6 0x0
++#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK        0x1d4 0x4e8 0x000 0x1 0x0
++#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS         0x1d4 0x4e8 0x85c 0x2 0x0
++#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23         0x1d4 0x4e8 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK       0x1d4 0x4e8 0x000 0x6 0x0
++#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID           0x1d8 0x4ec 0x000 0x0 0x0
++#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER           0x1d8 0x4ec 0x000 0x1 0x0
++#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK       0x1d8 0x4ec 0x864 0x2 0x0
++#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN             0x1d8 0x4ec 0x914 0x3 0x1
++#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0
++#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24           0x1d8 0x4ec 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN          0x1dc 0x4f0 0x858 0x1 0x1
++#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK         0x1dc 0x4f0 0x870 0x2 0x0
++#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK       0x1dc 0x4f0 0x918 0x3 0x1
++#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25          0x1dc 0x4f0 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_RXD1__MLB_SIG               0x1e0 0x4f4 0x908 0x0 0x0
++#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1         0x1e0 0x4f4 0x84c 0x1 0x1
++#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS            0x1e0 0x4f4 0x860 0x2 0x0
++#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT  0x1e0 0x4f4 0x000 0x4 0x0
++#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26            0x1e0 0x4f4 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0         0x1e4 0x4f8 0x848 0x1 0x1
++#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK        0x1e4 0x4f8 0x868 0x2 0x0
++#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT             0x1e4 0x4f8 0x000 0x3 0x0
++#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27            0x1e4 0x4f8 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN           0x1e8 0x4fc 0x000 0x1 0x0
++#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2         0x1e8 0x4fc 0x880 0x2 0x0
++#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28           0x1e8 0x4fc 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_TXD1__MLB_CLK               0x1ec 0x500 0x900 0x0 0x0
++#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1         0x1ec 0x500 0x000 0x1 0x0
++#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3          0x1ec 0x500 0x87c 0x2 0x0
++#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN   0x1ec 0x500 0x000 0x4 0x0
++#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29            0x1ec 0x500 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0         0x1f0 0x504 0x000 0x1 0x0
++#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1          0x1f0 0x504 0x884 0x2 0x0
++#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30            0x1f0 0x504 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_MDC__MLB_DATA               0x1f4 0x508 0x904 0x0 0x0
++#define MX6QDL_PAD_ENET_MDC__ENET_MDC               0x1f4 0x508 0x000 0x1 0x0
++#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0           0x1f4 0x508 0x888 0x2 0x0
++#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN    0x1f4 0x508 0x000 0x4 0x0
++#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31             0x1f4 0x508 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK            0x1f8 0x5c8 0x7f4 0x0 0x2
++#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3          0x1f8 0x5c8 0x854 0x1 0x1
++#define MX6QDL_PAD_KEY_COL0__AUD5_TXC               0x1f8 0x5c8 0x7dc 0x2 0x1
++#define MX6QDL_PAD_KEY_COL0__KEY_COL0               0x1f8 0x5c8 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA          0x1f8 0x5c8 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA          0x1f8 0x5c8 0x938 0x4 0x0
++#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06             0x1f8 0x5c8 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT              0x1f8 0x5c8 0x000 0x6 0x0
++#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI            0x1fc 0x5cc 0x7fc 0x0 0x2
++#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3          0x1fc 0x5cc 0x000 0x1 0x0
++#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD               0x1fc 0x5cc 0x7d0 0x2 0x1
++#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0               0x1fc 0x5cc 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA          0x1fc 0x5cc 0x938 0x4 0x1
++#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA          0x1fc 0x5cc 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07             0x1fc 0x5cc 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT              0x1fc 0x5cc 0x000 0x6 0x0
++#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO            0x200 0x5d0 0x7f8 0x0 0x2
++#define MX6QDL_PAD_KEY_COL1__ENET_MDIO              0x200 0x5d0 0x840 0x1 0x1
++#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS              0x200 0x5d0 0x7e0 0x2 0x1
++#define MX6QDL_PAD_KEY_COL1__KEY_COL1               0x200 0x5d0 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA          0x200 0x5d0 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA          0x200 0x5d0 0x940 0x4 0x0
++#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08             0x200 0x5d0 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT            0x200 0x5d0 0x000 0x6 0x0
++#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0             0x204 0x5d4 0x800 0x0 0x2
++#define MX6QDL_PAD_KEY_ROW1__ENET_COL               0x204 0x5d4 0x000 0x1 0x0
++#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD               0x204 0x5d4 0x7cc 0x2 0x1
++#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1               0x204 0x5d4 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA          0x204 0x5d4 0x940 0x4 0x1
++#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA          0x204 0x5d4 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09             0x204 0x5d4 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT            0x204 0x5d4 0x000 0x6 0x0
++#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1             0x208 0x5d8 0x804 0x0 0x2
++#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2          0x208 0x5d8 0x850 0x1 0x1
++#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX            0x208 0x5d8 0x000 0x2 0x0
++#define MX6QDL_PAD_KEY_COL2__KEY_COL2               0x208 0x5d8 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_COL2__ENET_MDC               0x208 0x5d8 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10             0x208 0x5d8 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE    0x208 0x5d8 0x000 0x6 0x0
++#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2             0x20c 0x5dc 0x808 0x0 0x1
++#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2          0x20c 0x5dc 0x000 0x1 0x0
++#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX            0x20c 0x5dc 0x7e4 0x2 0x0
++#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2               0x20c 0x5dc 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT            0x20c 0x5dc 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11             0x20c 0x5dc 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE       0x20c 0x5dc 0x88c 0x6 0x1
++#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3             0x210 0x5e0 0x80c 0x0 0x1
++#define MX6QDL_PAD_KEY_COL3__ENET_CRS               0x210 0x5e0 0x000 0x1 0x0
++#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL        0x210 0x5e0 0x890 0x2 0x1
++#define MX6QDL_PAD_KEY_COL3__KEY_COL3               0x210 0x5e0 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_COL3__I2C2_SCL               0x210 0x5e0 0x8a0 0x4 0x1
++#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12             0x210 0x5e0 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_COL3__SPDIF_IN               0x210 0x5e0 0x914 0x6 0x2
++#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK           0x214 0x5e4 0x7b0 0x1 0x0
++#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA        0x214 0x5e4 0x894 0x2 0x1
++#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3               0x214 0x5e4 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA               0x214 0x5e4 0x8a4 0x4 0x1
++#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13             0x214 0x5e4 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT            0x214 0x5e4 0x000 0x6 0x0
++#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX            0x218 0x5e8 0x000 0x0 0x0
++#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4             0x218 0x5e8 0x000 0x1 0x0
++#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC             0x218 0x5e8 0x944 0x2 0x1
++#define MX6QDL_PAD_KEY_COL4__KEY_COL4               0x218 0x5e8 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B            0x218 0x5e8 0x93c 0x4 0x0
++#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B            0x218 0x5e8 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14             0x218 0x5e8 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX            0x21c 0x5ec 0x7e8 0x0 0x0
++#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5             0x21c 0x5ec 0x000 0x1 0x0
++#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR            0x21c 0x5ec 0x000 0x2 0x0
++#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4               0x21c 0x5ec 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B            0x21c 0x5ec 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B            0x21c 0x5ec 0x93c 0x4 0x1
++#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15             0x21c 0x5ec 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_0__CCM_CLKO1                0x220 0x5f0 0x000 0x0 0x0
++#define MX6QDL_PAD_GPIO_0__KEY_COL5                 0x220 0x5f0 0x8e8 0x2 0x0
++#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK             0x220 0x5f0 0x7b0 0x3 0x1
++#define MX6QDL_PAD_GPIO_0__EPIT1_OUT                0x220 0x5f0 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_0__GPIO1_IO00               0x220 0x5f0 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_0__USB_H1_PWR               0x220 0x5f0 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5               0x220 0x5f0 0x000 0x7 0x0
++#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK              0x224 0x5f4 0x86c 0x0 0x1
++#define MX6QDL_PAD_GPIO_1__WDOG2_B                  0x224 0x5f4 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_1__KEY_ROW5                 0x224 0x5f4 0x8f4 0x2 0x0
++#define MX6QDL_PAD_GPIO_1__USB_OTG_ID               0x224 0x5f4 0x000 0x3 0x0
++#define MX6QDL_PAD_GPIO_1__PWM2_OUT                 0x224 0x5f4 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_1__GPIO1_IO01               0x224 0x5f4 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_1__SD1_CD_B                 0x224 0x5f4 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS               0x228 0x5f8 0x85c 0x0 0x1
++#define MX6QDL_PAD_GPIO_9__WDOG1_B                  0x228 0x5f8 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_9__KEY_COL6                 0x228 0x5f8 0x8ec 0x2 0x0
++#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B             0x228 0x5f8 0x000 0x3 0x0
++#define MX6QDL_PAD_GPIO_9__PWM1_OUT                 0x228 0x5f8 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_9__GPIO1_IO09               0x228 0x5f8 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_9__SD1_WP                   0x228 0x5f8 0x94c 0x6 0x1
++#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK           0x22c 0x5fc 0x864 0x0 0x1
++#define MX6QDL_PAD_GPIO_3__I2C3_SCL                 0x22c 0x5fc 0x8a8 0x2 0x1
++#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M      0x22c 0x5fc 0x000 0x3 0x0
++#define MX6QDL_PAD_GPIO_3__CCM_CLKO2                0x22c 0x5fc 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_3__GPIO1_IO03               0x22c 0x5fc 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_3__USB_H1_OC                0x22c 0x5fc 0x948 0x6 0x1
++#define MX6QDL_PAD_GPIO_3__MLB_CLK                  0x22c 0x5fc 0x900 0x7 0x1
++#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK              0x230 0x600 0x870 0x0 0x1
++#define MX6QDL_PAD_GPIO_6__I2C3_SDA                 0x230 0x600 0x8ac 0x2 0x1
++#define MX6QDL_PAD_GPIO_6__GPIO1_IO06               0x230 0x600 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_6__SD2_LCTL                 0x230 0x600 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_6__MLB_SIG                  0x230 0x600 0x908 0x7 0x1
++#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS               0x234 0x604 0x860 0x0 0x1
++#define MX6QDL_PAD_GPIO_2__KEY_ROW6                 0x234 0x604 0x8f8 0x2 0x1
++#define MX6QDL_PAD_GPIO_2__GPIO1_IO02               0x234 0x604 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_2__SD2_WP                   0x234 0x604 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_2__MLB_DATA                 0x234 0x604 0x904 0x7 0x1
++#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK           0x238 0x608 0x868 0x0 0x1
++#define MX6QDL_PAD_GPIO_4__KEY_COL7                 0x238 0x608 0x8f0 0x2 0x1
++#define MX6QDL_PAD_GPIO_4__GPIO1_IO04               0x238 0x608 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_4__SD2_CD_B                 0x238 0x608 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3             0x23c 0x60c 0x87c 0x0 0x1
++#define MX6QDL_PAD_GPIO_5__KEY_ROW7                 0x23c 0x60c 0x8fc 0x2 0x1
++#define MX6QDL_PAD_GPIO_5__CCM_CLKO1                0x23c 0x60c 0x000 0x3 0x0
++#define MX6QDL_PAD_GPIO_5__GPIO1_IO05               0x23c 0x60c 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_5__I2C3_SCL                 0x23c 0x60c 0x8a8 0x6 0x2
++#define MX6QDL_PAD_GPIO_5__ARM_EVENTI               0x23c 0x60c 0x000 0x7 0x0
++#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1             0x240 0x610 0x884 0x0 0x1
++#define MX6QDL_PAD_GPIO_7__ECSPI5_RDY               0x240 0x610 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_7__EPIT1_OUT                0x240 0x610 0x000 0x2 0x0
++#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX              0x240 0x610 0x000 0x3 0x0
++#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA            0x240 0x610 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA            0x240 0x610 0x928 0x4 0x2
++#define MX6QDL_PAD_GPIO_7__GPIO1_IO07               0x240 0x610 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK               0x240 0x610 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE        0x240 0x610 0x000 0x7 0x0
++#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0             0x244 0x614 0x888 0x0 0x1
++#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K      0x244 0x614 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_8__EPIT2_OUT                0x244 0x614 0x000 0x2 0x0
++#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX              0x244 0x614 0x7e4 0x3 0x1
++#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA            0x244 0x614 0x928 0x4 0x3
++#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA            0x244 0x614 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_8__GPIO1_IO08               0x244 0x614 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK             0x244 0x614 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE     0x244 0x614 0x000 0x7 0x0
++#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2            0x248 0x618 0x880 0x0 0x1
++#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN     0x248 0x618 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK            0x248 0x618 0x83c 0x2 0x1
++#define MX6QDL_PAD_GPIO_16__SD1_LCTL                0x248 0x618 0x000 0x3 0x0
++#define MX6QDL_PAD_GPIO_16__SPDIF_IN                0x248 0x618 0x914 0x4 0x3
++#define MX6QDL_PAD_GPIO_16__GPIO7_IO11              0x248 0x618 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_16__I2C3_SDA                0x248 0x618 0x8ac 0x6 0x2
++#define MX6QDL_PAD_GPIO_16__JTAG_DE_B               0x248 0x618 0x000 0x7 0x0
++#define MX6QDL_PAD_GPIO_17__ESAI_TX0                0x24c 0x61c 0x874 0x0 0x0
++#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN     0x24c 0x61c 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY          0x24c 0x61c 0x7f0 0x2 0x1
++#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0         0x24c 0x61c 0x90c 0x3 0x1
++#define MX6QDL_PAD_GPIO_17__SPDIF_OUT               0x24c 0x61c 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_17__GPIO7_IO12              0x24c 0x61c 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_18__ESAI_TX1                0x250 0x620 0x878 0x0 0x0
++#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK             0x250 0x620 0x844 0x1 0x1
++#define MX6QDL_PAD_GPIO_18__SD3_VSELECT             0x250 0x620 0x000 0x2 0x0
++#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1         0x250 0x620 0x910 0x3 0x1
++#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK            0x250 0x620 0x7b0 0x4 0x2
++#define MX6QDL_PAD_GPIO_18__GPIO7_IO13              0x250 0x620 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL          0x250 0x620 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_19__KEY_COL5                0x254 0x624 0x8e8 0x0 0x1
++#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT    0x254 0x624 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_19__SPDIF_OUT               0x254 0x624 0x000 0x2 0x0
++#define MX6QDL_PAD_GPIO_19__CCM_CLKO1               0x254 0x624 0x000 0x3 0x0
++#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY              0x254 0x624 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_19__GPIO4_IO05              0x254 0x624 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_19__ENET_TX_ER              0x254 0x624 0x000 0x6 0x0
++#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK    0x258 0x628 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18          0x258 0x628 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO          0x258 0x628 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC       0x25c 0x62c 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1             0x25c 0x62c 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19            0x25c 0x62c 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL         0x25c 0x62c 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN  0x260 0x630 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00         0x260 0x630 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20         0x260 0x630 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK      0x260 0x630 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC      0x264 0x634 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01           0x264 0x634 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21           0x264 0x634 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00          0x264 0x634 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04      0x268 0x638 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02            0x268 0x638 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK           0x268 0x638 0x7f4 0x2 0x3
++#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5              0x268 0x638 0x8e8 0x3 0x2
++#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC              0x268 0x638 0x000 0x4 0x0
++#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22            0x268 0x638 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01           0x268 0x638 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05      0x26c 0x63c 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03            0x26c 0x63c 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI           0x26c 0x63c 0x7fc 0x2 0x3
++#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5              0x26c 0x63c 0x8f4 0x3 0x1
++#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD              0x26c 0x63c 0x000 0x4 0x0
++#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23            0x26c 0x63c 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02           0x26c 0x63c 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06      0x270 0x640 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04            0x270 0x640 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO           0x270 0x640 0x7f8 0x2 0x3
++#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6              0x270 0x640 0x8ec 0x3 0x1
++#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS             0x270 0x640 0x000 0x4 0x0
++#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24            0x270 0x640 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03           0x270 0x640 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07      0x274 0x644 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05            0x274 0x644 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0            0x274 0x644 0x800 0x2 0x3
++#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6              0x274 0x644 0x8f8 0x3 0x2
++#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD              0x274 0x644 0x000 0x4 0x0
++#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25            0x274 0x644 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04           0x274 0x644 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08      0x278 0x648 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06            0x278 0x648 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK           0x278 0x648 0x810 0x2 0x2
++#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7              0x278 0x648 0x8f0 0x3 0x2
++#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA              0x278 0x648 0x89c 0x4 0x1
++#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26            0x278 0x648 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05           0x278 0x648 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09      0x27c 0x64c 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07            0x27c 0x64c 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI           0x27c 0x64c 0x818 0x2 0x2
++#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7              0x27c 0x64c 0x8fc 0x3 0x2
++#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL              0x27c 0x64c 0x898 0x4 0x1
++#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27            0x27c 0x64c 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06           0x27c 0x64c 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10     0x280 0x650 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC             0x280 0x650 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO          0x280 0x650 0x814 0x2 0x2
++#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA        0x280 0x650 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA        0x280 0x650 0x920 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28           0x280 0x650 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07          0x280 0x650 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11     0x284 0x654 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS            0x284 0x654 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0           0x284 0x654 0x81c 0x2 0x2
++#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA        0x284 0x654 0x920 0x3 0x1
++#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA        0x284 0x654 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29           0x284 0x654 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08          0x284 0x654 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12     0x288 0x658 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08           0x288 0x658 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA        0x288 0x658 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA        0x288 0x658 0x938 0x3 0x2
++#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30           0x288 0x658 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09          0x288 0x658 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13     0x28c 0x65c 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09           0x28c 0x65c 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA        0x28c 0x65c 0x938 0x3 0x3
++#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA        0x28c 0x65c 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31           0x28c 0x65c 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10          0x28c 0x65c 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14     0x290 0x660 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10           0x290 0x660 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA        0x290 0x660 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA        0x290 0x660 0x940 0x3 0x2
++#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00           0x290 0x660 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11          0x290 0x660 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15     0x294 0x664 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11           0x294 0x664 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA        0x294 0x664 0x940 0x3 0x3
++#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA        0x294 0x664 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01           0x294 0x664 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12          0x294 0x664 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16     0x298 0x668 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12           0x298 0x668 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B          0x298 0x668 0x934 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B          0x298 0x668 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02           0x298 0x668 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13          0x298 0x668 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17     0x29c 0x66c 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13           0x29c 0x66c 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B          0x29c 0x66c 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B          0x29c 0x66c 0x934 0x3 0x1
++#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03           0x29c 0x66c 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14          0x29c 0x66c 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18     0x2a0 0x670 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14           0x2a0 0x670 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B          0x2a0 0x670 0x93c 0x3 0x2
++#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B          0x2a0 0x670 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04           0x2a0 0x670 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15          0x2a0 0x670 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19     0x2a4 0x674 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15           0x2a4 0x674 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B          0x2a4 0x674 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B          0x2a4 0x674 0x93c 0x3 0x3
++#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05           0x2a4 0x674 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7              0x2a8 0x690 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA          0x2a8 0x690 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA          0x2a8 0x690 0x920 0x1 0x2
++#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17             0x2a8 0x690 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6              0x2ac 0x694 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA          0x2ac 0x694 0x920 0x1 0x3
++#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA          0x2ac 0x694 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18             0x2ac 0x694 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5              0x2b0 0x698 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA          0x2b0 0x698 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA          0x2b0 0x698 0x928 0x1 0x4
++#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00             0x2b0 0x698 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4              0x2b4 0x69c 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA          0x2b4 0x69c 0x928 0x1 0x5
++#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA          0x2b4 0x69c 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01             0x2b4 0x69c 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_CMD__SD3_CMD                 0x2b8 0x6a0 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B             0x2b8 0x6a0 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B             0x2b8 0x6a0 0x924 0x1 0x2
++#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX             0x2b8 0x6a0 0x000 0x2 0x0
++#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02              0x2b8 0x6a0 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_CLK__SD3_CLK                 0x2bc 0x6a4 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B             0x2bc 0x6a4 0x924 0x1 0x3
++#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B             0x2bc 0x6a4 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX             0x2bc 0x6a4 0x7e4 0x2 0x2
++#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03              0x2bc 0x6a4 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0              0x2c0 0x6a8 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B            0x2c0 0x6a8 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B            0x2c0 0x6a8 0x91c 0x1 0x2
++#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX            0x2c0 0x6a8 0x000 0x2 0x0
++#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04             0x2c0 0x6a8 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1              0x2c4 0x6ac 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B            0x2c4 0x6ac 0x91c 0x1 0x3
++#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B            0x2c4 0x6ac 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX            0x2c4 0x6ac 0x7e8 0x2 0x1
++#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05             0x2c4 0x6ac 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2              0x2c8 0x6b0 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06             0x2c8 0x6b0 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3              0x2cc 0x6b4 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B            0x2cc 0x6b4 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B            0x2cc 0x6b4 0x92c 0x1 0x4
++#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07             0x2cc 0x6b4 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_RST__SD3_RESET               0x2d0 0x6b8 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_RST__UART3_RTS_B             0x2d0 0x6b8 0x92c 0x1 0x5
++#define MX6QDL_PAD_SD3_RST__UART3_CTS_B             0x2d0 0x6b8 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_RST__GPIO7_IO08              0x2d0 0x6b8 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_CLE__NAND_CLE              0x2d4 0x6bc 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_CLE__IPU2_SISG4            0x2d4 0x6bc 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07            0x2d4 0x6bc 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_ALE__NAND_ALE              0x2d8 0x6c0 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_ALE__SD4_RESET             0x2d8 0x6c0 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08            0x2d8 0x6c0 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B            0x2dc 0x6c4 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_WP_B__IPU2_SISG5           0x2dc 0x6c4 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09           0x2dc 0x6c4 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B          0x2e0 0x6c8 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_RB0__IPU2_DI0_PIN01        0x2e0 0x6c8 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10            0x2e0 0x6c8 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B            0x2e4 0x6cc 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11            0x2e4 0x6cc 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B            0x2e8 0x6d0 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT           0x2e8 0x6d0 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT           0x2e8 0x6d0 0x000 0x2 0x0
++#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14            0x2e8 0x6d0 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B            0x2ec 0x6d4 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0            0x2ec 0x6d4 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0              0x2ec 0x6d4 0x874 0x2 0x1
++#define MX6QDL_PAD_NANDF_CS2__EIM_CRE               0x2ec 0x6d4 0x000 0x3 0x0
++#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2             0x2ec 0x6d4 0x000 0x4 0x0
++#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15            0x2ec 0x6d4 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_CS2__IPU2_SISG0            0x2ec 0x6d4 0x000 0x6 0x0
++#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B            0x2f0 0x6d8 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1            0x2f0 0x6d8 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1              0x2f0 0x6d8 0x878 0x2 0x1
++#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26            0x2f0 0x6d8 0x000 0x3 0x0
++#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16            0x2f0 0x6d8 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_CS3__IPU2_SISG1            0x2f0 0x6d8 0x000 0x6 0x0
++#define MX6QDL_PAD_SD4_CMD__SD4_CMD                 0x2f4 0x6dc 0x000 0x0 0x0
++#define MX6QDL_PAD_SD4_CMD__NAND_RE_B               0x2f4 0x6dc 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA           0x2f4 0x6dc 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA           0x2f4 0x6dc 0x930 0x2 0x2
++#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09              0x2f4 0x6dc 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_CLK__SD4_CLK                 0x2f8 0x6e0 0x000 0x0 0x0
++#define MX6QDL_PAD_SD4_CLK__NAND_WE_B               0x2f8 0x6e0 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA           0x2f8 0x6e0 0x930 0x2 0x3
++#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA           0x2f8 0x6e0 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10              0x2f8 0x6e0 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D0__NAND_DATA00            0x2fc 0x6e4 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D0__SD1_DATA4              0x2fc 0x6e4 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00             0x2fc 0x6e4 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D1__NAND_DATA01            0x300 0x6e8 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D1__SD1_DATA5              0x300 0x6e8 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01             0x300 0x6e8 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D2__NAND_DATA02            0x304 0x6ec 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D2__SD1_DATA6              0x304 0x6ec 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02             0x304 0x6ec 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D3__NAND_DATA03            0x308 0x6f0 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D3__SD1_DATA7              0x308 0x6f0 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03             0x308 0x6f0 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D4__NAND_DATA04            0x30c 0x6f4 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D4__SD2_DATA4              0x30c 0x6f4 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04             0x30c 0x6f4 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D5__NAND_DATA05            0x310 0x6f8 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D5__SD2_DATA5              0x310 0x6f8 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05             0x310 0x6f8 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D6__NAND_DATA06            0x314 0x6fc 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D6__SD2_DATA6              0x314 0x6fc 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06             0x314 0x6fc 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D7__NAND_DATA07            0x318 0x700 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D7__SD2_DATA7              0x318 0x700 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07             0x318 0x700 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0              0x31c 0x704 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT0__NAND_DQS               0x31c 0x704 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08             0x31c 0x704 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1              0x320 0x708 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT               0x320 0x708 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09             0x320 0x708 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2              0x324 0x70c 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT               0x324 0x70c 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10             0x324 0x70c 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3              0x328 0x710 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11             0x328 0x710 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4              0x32c 0x714 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA          0x32c 0x714 0x928 0x2 0x6
++#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA          0x32c 0x714 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12             0x32c 0x714 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5              0x330 0x718 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B            0x330 0x718 0x924 0x2 0x4
++#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B            0x330 0x718 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13             0x330 0x718 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6              0x334 0x71c 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B            0x334 0x71c 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B            0x334 0x71c 0x924 0x2 0x5
++#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14             0x334 0x71c 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7              0x338 0x720 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA          0x338 0x720 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA          0x338 0x720 0x928 0x2 0x7
++#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15             0x338 0x720 0x000 0x5 0x0
++#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1              0x33c 0x724 0x000 0x0 0x0
++#define MX6QDL_PAD_SD1_DAT1__ECSPI5_SS0             0x33c 0x724 0x834 0x1 0x1
++#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT               0x33c 0x724 0x000 0x2 0x0
++#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2           0x33c 0x724 0x000 0x3 0x0
++#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17             0x33c 0x724 0x000 0x5 0x0
++#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0              0x340 0x728 0x000 0x0 0x0
++#define MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO            0x340 0x728 0x82c 0x1 0x1
++#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1           0x340 0x728 0x000 0x3 0x0
++#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16             0x340 0x728 0x000 0x5 0x0
++#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3              0x344 0x72c 0x000 0x0 0x0
++#define MX6QDL_PAD_SD1_DAT3__ECSPI5_SS2             0x344 0x72c 0x000 0x1 0x0
++#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3           0x344 0x72c 0x000 0x2 0x0
++#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT               0x344 0x72c 0x000 0x3 0x0
++#define MX6QDL_PAD_SD1_DAT3__WDOG2_B                0x344 0x72c 0x000 0x4 0x0
++#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21             0x344 0x72c 0x000 0x5 0x0
++#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB      0x344 0x72c 0x000 0x6 0x0
++#define MX6QDL_PAD_SD1_CMD__SD1_CMD                 0x348 0x730 0x000 0x0 0x0
++#define MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI             0x348 0x730 0x830 0x1 0x0
++#define MX6QDL_PAD_SD1_CMD__PWM4_OUT                0x348 0x730 0x000 0x2 0x0
++#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1            0x348 0x730 0x000 0x3 0x0
++#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18              0x348 0x730 0x000 0x5 0x0
++#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2              0x34c 0x734 0x000 0x0 0x0
++#define MX6QDL_PAD_SD1_DAT2__ECSPI5_SS1             0x34c 0x734 0x838 0x1 0x1
++#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2           0x34c 0x734 0x000 0x2 0x0
++#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT               0x34c 0x734 0x000 0x3 0x0
++#define MX6QDL_PAD_SD1_DAT2__WDOG1_B                0x34c 0x734 0x000 0x4 0x0
++#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19             0x34c 0x734 0x000 0x5 0x0
++#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB      0x34c 0x734 0x000 0x6 0x0
++#define MX6QDL_PAD_SD1_CLK__SD1_CLK                 0x350 0x738 0x000 0x0 0x0
++#define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK             0x350 0x738 0x828 0x1 0x0
++#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN               0x350 0x738 0x000 0x3 0x0
++#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20              0x350 0x738 0x000 0x5 0x0
++#define MX6QDL_PAD_SD2_CLK__SD2_CLK                 0x354 0x73c 0x000 0x0 0x0
++#define MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK             0x354 0x73c 0x828 0x1 0x1
++#define MX6QDL_PAD_SD2_CLK__KEY_COL5                0x354 0x73c 0x8e8 0x2 0x3
++#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS               0x354 0x73c 0x7c0 0x3 0x1
++#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10              0x354 0x73c 0x000 0x5 0x0
++#define MX6QDL_PAD_SD2_CMD__SD2_CMD                 0x358 0x740 0x000 0x0 0x0
++#define MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI             0x358 0x740 0x830 0x1 0x1
++#define MX6QDL_PAD_SD2_CMD__KEY_ROW5                0x358 0x740 0x8f4 0x2 0x2
++#define MX6QDL_PAD_SD2_CMD__AUD4_RXC                0x358 0x740 0x7bc 0x3 0x1
++#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11              0x358 0x740 0x000 0x5 0x0
++#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3              0x35c 0x744 0x000 0x0 0x0
++#define MX6QDL_PAD_SD2_DAT3__ECSPI5_SS3             0x35c 0x744 0x000 0x1 0x0
++#define MX6QDL_PAD_SD2_DAT3__KEY_COL6               0x35c 0x744 0x8ec 0x2 0x2
++#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC               0x35c 0x744 0x7c4 0x3 0x1
++#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12             0x35c 0x744 0x000 0x5 0x0
+ 
+ #endif /* __DTS_IMX6Q_PINFUNC_H */
+diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
+index 49d6f28..334b924 100644
+--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
++++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
+@@ -20,16 +20,6 @@
+       compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
+ };
+ 
+-&iomuxc {
+-      pinctrl-names = "default";
+-      pinctrl-0 = <&pinctrl_hog>;
+-
+-      hog {
+-              pinctrl_hog: hoggrp {
+-                      fsl,pins = <
+-                              MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
+-                              MX6Q_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
+-                      >;
+-              };
+-      };
++&sata {
++      status = "okay";
+ };
+diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
+index 6a00066..3530280 100644
+--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
++++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
+@@ -65,6 +65,10 @@
+       };
+ };
+ 
++&sata {
++      status = "okay";
++};
++
+ &ecspi1 {
+       fsl,spi-num-chipselects = <1>;
+       cs-gpios = <&gpio3 19 0>;
+@@ -91,14 +95,14 @@
+       hog {
+               pinctrl_hog: hoggrp {
+                       fsl,pins = <
+-                              MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x80000000
+-                              MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x80000000
+-                              MX6Q_PAD_EIM_D19__GPIO3_IO19  0x80000000
+-                              MX6Q_PAD_EIM_D22__GPIO3_IO22  0x80000000
+-                              MX6Q_PAD_EIM_D23__GPIO3_IO23  0x80000000
+-                              MX6Q_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
+-                              MX6Q_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
+-                              MX6Q_PAD_GPIO_0__CCM_CLKO1    0x80000000
++                              MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000
++                              MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000
++                              MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x80000000
++                              MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x80000000
++                              MX6QDL_PAD_EIM_D23__GPIO3_IO23  0x80000000
++                              MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
++                              MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
++                              MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x80000000
+                       >;
+               };
+       };
+@@ -163,7 +167,7 @@
+       codec: sgtl5000@0a {
+               compatible = "fsl,sgtl5000";
+               reg = <0x0a>;
+-              clocks = <&clks 169>;
++              clocks = <&clks 201>;
+               VDDA-supply = <&reg_2p5v>;
+               VDDIO-supply = <&reg_3p3v>;
+       };
+diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
+index 4420513..9cbdfe7 100644
+--- a/arch/arm/boot/dts/imx6q-sabresd.dts
++++ b/arch/arm/boot/dts/imx6q-sabresd.dts
+@@ -20,20 +20,6 @@
+       compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
+ };
+ 
+-&iomuxc {
+-      pinctrl-names = "default";
+-      pinctrl-0 = <&pinctrl_hog>;
+-
+-      hog {
+-              pinctrl_hog: hoggrp {
+-                      fsl,pins = <
+-                              MX6Q_PAD_GPIO_4__GPIO1_IO04   0x80000000
+-                              MX6Q_PAD_GPIO_5__GPIO1_IO05   0x80000000
+-                              MX6Q_PAD_NANDF_D0__GPIO2_IO00 0x80000000
+-                              MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x80000000
+-                              MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x80000000
+-                              MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x80000000
+-                      >;
+-              };
+-      };
++&sata {
++      status = "okay";
+ };
+diff --git a/arch/arm/boot/dts/imx6q-wandboard.dts b/arch/arm/boot/dts/imx6q-wandboard.dts
+new file mode 100644
+index 0000000..36be17f
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6q-wandboard.dts
+@@ -0,0 +1,26 @@
++/*
++ * Copyright 2013 Freescale Semiconductor, Inc.
++ *
++ * Author: Fabio Estevam <fabio.estevam@freescale.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++/dts-v1/;
++#include "imx6q.dtsi"
++#include "imx6qdl-wandboard.dtsi"
++
++/ {
++      model = "Wandboard i.MX6 Quad Board";
++      compatible = "wand,imx6q-wandboard", "fsl,imx6q";
++
++      memory {
++              reg = <0x10000000 0x80000000>;
++      };
++};
++
++&sata {
++      status = "okay";
++};
+diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
+index dc54a72..f024ef2 100644
+--- a/arch/arm/boot/dts/imx6q.dtsi
++++ b/arch/arm/boot/dts/imx6q.dtsi
+@@ -8,8 +8,8 @@
+  *
+  */
+ 
+-#include "imx6qdl.dtsi"
+ #include "imx6q-pinfunc.h"
++#include "imx6qdl.dtsi"
+ 
+ / {
+       cpus {
+@@ -61,6 +61,12 @@
+       };
+ 
+       soc {
++              ocram: sram@00900000 {
++                      compatible = "mmio-sram";
++                      reg = <0x00900000 0x40000>;
++                      clocks = <&clks 142>;
++              };
++
+               aips-bus@02000000 { /* AIPS1 */
+                       spba-bus@02000000 {
+                               ecspi5: ecspi@02018000 {
+@@ -77,261 +83,54 @@
+ 
+                       iomuxc: iomuxc@020e0000 {
+                               compatible = "fsl,imx6q-iomuxc";
+-                              reg = <0x020e0000 0x4000>;
+ 
+-                              /* shared pinctrl settings */
+-                              audmux {
+-                                      pinctrl_audmux_1: audmux-1 {
+-                                              fsl,pins = <
+-                                                      MX6Q_PAD_SD2_DAT0__AUD4_RXD  0x80000000
+-                                                      MX6Q_PAD_SD2_DAT3__AUD4_TXC  0x80000000
+-                                                      MX6Q_PAD_SD2_DAT2__AUD4_TXD  0x80000000
+-                                                      MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
+-                                              >;
+-                                      };
+-
+-                                      pinctrl_audmux_2: audmux-2 {
+-                                              fsl,pins = <
+-                                                      MX6Q_PAD_CSI0_DAT7__AUD3_RXD  0x80000000
+-                                                      MX6Q_PAD_CSI0_DAT4__AUD3_TXC  0x80000000
+-                                                      MX6Q_PAD_CSI0_DAT5__AUD3_TXD  0x80000000
+-                                                      MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
+-                                              >;
+-                                      };
+-                              };
+-
+-                              ecspi1 {
+-                                      pinctrl_ecspi1_1: ecspi1grp-1 {
+-                                              fsl,pins = <
+-                                                      MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+-                                                      MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+-                                                      MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+-                                              >;
+-                                      };
+-                              };
+-
+-                              ecspi3 {
+-                                      pinctrl_ecspi3_1: ecspi3grp-1 {
+-                                              fsl,pins = <
+-                                                      MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
+-                                                      MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
+-                                                      MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
+-                                              >;
+-                                      };
+-                              };
+-
+-                              enet {
+-                                      pinctrl_enet_1: enetgrp-1 {
+-                                              fsl,pins = <
+-                                                      MX6Q_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
+-                                                      MX6Q_PAD_ENET_MDC__ENET_MDC         0x1b0b0
+-                                                      MX6Q_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+-                                                      MX6Q_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+-                                                      MX6Q_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+-                                                      MX6Q_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+-                                                      MX6Q_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+-                                                      MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+-                                                      MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+-                                                      MX6Q_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+-                                                      MX6Q_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+-                                                      MX6Q_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+-                                                      MX6Q_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+-                                                      MX6Q_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+-                                                      MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+-                                                      MX6Q_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
+-                                              >;
+-                                      };
+-
+-                                      pinctrl_enet_2: enetgrp-2 {
+-                                              fsl,pins = <
+-                                                      MX6Q_PAD_KEY_COL1__ENET_MDIO        0x1b0b0
+-                                                      MX6Q_PAD_KEY_COL2__ENET_MDC         0x1b0b0
+-                                                      MX6Q_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+-                                                      MX6Q_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+-                                                      MX6Q_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+-                                                      MX6Q_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+-                                                      MX6Q_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+-                                                      MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+-                                                      MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+-                                                      MX6Q_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+-                                                      MX6Q_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+-                                                      MX6Q_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+-                                                      MX6Q_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+-                                                      MX6Q_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+-                                                      MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+-                                              >;
+-                                      };
+-                              };
+-
+-                              gpmi-nand {
+-                                      pinctrl_gpmi_nand_1: gpmi-nand-1 {
+-                                              fsl,pins = <
+-                                                      MX6Q_PAD_NANDF_CLE__NAND_CLE     0xb0b1
+-                                                      MX6Q_PAD_NANDF_ALE__NAND_ALE     0xb0b1
+-                                                      MX6Q_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
+-                                                      MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
+-                                                      MX6Q_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
+-                                                      MX6Q_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
+-                                                      MX6Q_PAD_NANDF_CS2__NAND_CE2_B   0xb0b1
+-                                                      MX6Q_PAD_NANDF_CS3__NAND_CE3_B   0xb0b1
+-                                                      MX6Q_PAD_SD4_CMD__NAND_RE_B      0xb0b1
+-                                                      MX6Q_PAD_SD4_CLK__NAND_WE_B      0xb0b1
+-                                                      MX6Q_PAD_NANDF_D0__NAND_DATA00   0xb0b1
+-                                                      MX6Q_PAD_NANDF_D1__NAND_DATA01   0xb0b1
+-                                                      MX6Q_PAD_NANDF_D2__NAND_DATA02   0xb0b1
+-                                                      MX6Q_PAD_NANDF_D3__NAND_DATA03   0xb0b1
+-                                                      MX6Q_PAD_NANDF_D4__NAND_DATA04   0xb0b1
+-                                                      MX6Q_PAD_NANDF_D5__NAND_DATA05   0xb0b1
+-                                                      MX6Q_PAD_NANDF_D6__NAND_DATA06   0xb0b1
+-                                                      MX6Q_PAD_NANDF_D7__NAND_DATA07   0xb0b1
+-                                                      MX6Q_PAD_SD4_DAT0__NAND_DQS      0x00b1
+-                                              >;
+-                                      };
+-                              };
+-
+-                              i2c1 {
+-                                      pinctrl_i2c1_1: i2c1grp-1 {
+-                                              fsl,pins = <
+-                                                      MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+-                                                      MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+-                                              >;
+-                                      };
+-                              };
+-
+-                              i2c2 {
+-                                      pinctrl_i2c2_1: i2c2grp-1 {
+-                                              fsl,pins = <
+-                                                      MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
+-                                                      MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
+-                                              >;
+-                                      };
+-                              };
+-
+-                              i2c3 {
+-                                      pinctrl_i2c3_1: i2c3grp-1 {
+-                                              fsl,pins = <
+-                                                      MX6Q_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
+-                                                      MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+-                                              >;
+-                                      };
+-                              };
+-
+-                              uart1 {
+-                                      pinctrl_uart1_1: uart1grp-1 {
+-                                              fsl,pins = <
+-                                                      MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+-                                                      MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+-                                              >;
+-                                      };
+-                              };
+-
+-                              uart2 {
+-                                      pinctrl_uart2_1: uart2grp-1 {
+-                                              fsl,pins = <
+-                                                      MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
+-                                                      MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
+-                                              >;
+-                                      };
+-                              };
+-
+-                              uart4 {
+-                                      pinctrl_uart4_1: uart4grp-1 {
+-                                              fsl,pins = <
+-                                                      MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+-                                                      MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+-                                              >;
+-                                      };
+-                              };
+-
+-                              usbotg {
+-                                      pinctrl_usbotg_1: usbotggrp-1 {
+-                                              fsl,pins = <
+-                                                      MX6Q_PAD_GPIO_1__USB_OTG_ID 0x17059
+-                                              >;
+-                                      };
+-
+-                                      pinctrl_usbotg_2: usbotggrp-2 {
+-                                              fsl,pins = <
+-                                                      MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+-                                              >;
+-                                      };
+-                              };
+-
+-                              usdhc2 {
+-                                      pinctrl_usdhc2_1: usdhc2grp-1 {
+-                                              fsl,pins = <
+-                                                      MX6Q_PAD_SD2_CMD__SD2_CMD    0x17059
+-                                                      MX6Q_PAD_SD2_CLK__SD2_CLK    0x10059
+-                                                      MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
+-                                                      MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
+-                                                      MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
+-                                                      MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
+-                                                      MX6Q_PAD_NANDF_D4__SD2_DATA4 0x17059
+-                                                      MX6Q_PAD_NANDF_D5__SD2_DATA5 0x17059
+-                                                      MX6Q_PAD_NANDF_D6__SD2_DATA6 0x17059
+-                                                      MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
+-                                              >;
+-                                      };
+-                              };
+-
+-                              usdhc3 {
+-                                      pinctrl_usdhc3_1: usdhc3grp-1 {
+-                                              fsl,pins = <
+-                                                      MX6Q_PAD_SD3_CMD__SD3_CMD    0x17059
+-                                                      MX6Q_PAD_SD3_CLK__SD3_CLK    0x10059
+-                                                      MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
+-                                                      MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
+-                                                      MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
+-                                                      MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
+-                                                      MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x17059
+-                                                      MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x17059
+-                                                      MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x17059
+-                                                      MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x17059
+-                                              >;
+-                                      };
+-
+-                                      pinctrl_usdhc3_2: usdhc3grp-2 {
+-                                              fsl,pins = <
+-                                                      MX6Q_PAD_SD3_CMD__SD3_CMD    0x17059
+-                                                      MX6Q_PAD_SD3_CLK__SD3_CLK    0x10059
+-                                                      MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
+-                                                      MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
+-                                                      MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
+-                                                      MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
+-                                              >;
+-                                      };
+-                              };
+-
+-                              usdhc4 {
+-                                      pinctrl_usdhc4_1: usdhc4grp-1 {
+-                                              fsl,pins = <
+-                                                      MX6Q_PAD_SD4_CMD__SD4_CMD    0x17059
+-                                                      MX6Q_PAD_SD4_CLK__SD4_CLK    0x10059
+-                                                      MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
+-                                                      MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
+-                                                      MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
+-                                                      MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
+-                                                      MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x17059
+-                                                      MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x17059
+-                                                      MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x17059
+-                                                      MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x17059
+-                                              >;
+-                                      };
+-
+-                                      pinctrl_usdhc4_2: usdhc4grp-2 {
+-                                              fsl,pins = <
+-                                                      MX6Q_PAD_SD4_CMD__SD4_CMD    0x17059
+-                                                      MX6Q_PAD_SD4_CLK__SD4_CLK    0x10059
+-                                                      MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
+-                                                      MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
+-                                                      MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
+-                                                      MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
++                              ipu2 {
++                                      pinctrl_ipu2_1: ipu2grp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
++                                                      MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15       0x10
++                                                      MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02        0x10
++                                                      MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03        0x10
++                                                      MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04        0x80000000
++                                                      MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00   0x10
++                                                      MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01   0x10
++                                                      MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02   0x10
++                                                      MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03   0x10
++                                                      MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04   0x10
++                                                      MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05   0x10
++                                                      MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06   0x10
++                                                      MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07   0x10
++                                                      MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08   0x10
++                                                      MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09   0x10
++                                                      MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10  0x10
++                                                      MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11  0x10
++                                                      MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12  0x10
++                                                      MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13  0x10
++                                                      MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14  0x10
++                                                      MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15  0x10
++                                                      MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16  0x10
++                                                      MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17  0x10
++                                                      MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18  0x10
++                                                      MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19  0x10
++                                                      MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20  0x10
++                                                      MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21  0x10
++                                                      MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22  0x10
++                                                      MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23  0x10
+                                               >;
+                                       };
+                               };
+                       };
+               };
+ 
++              sata: sata@02200000 {
++                      compatible = "fsl,imx6q-ahci";
++                      reg = <0x02200000 0x4000>;
++                      interrupts = <0 39 0x04>;
++                      clocks =  <&clks 154>, <&clks 187>, <&clks 105>;
++                      clock-names = "sata", "sata_ref", "ahb";
++                      status = "disabled";
++              };
++
+               ipu2: ipu@02800000 {
+                       #crtc-cells = <1>;
+                       compatible = "fsl,imx6q-ipu";
+diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+index 4d237cf..1cbbc51 100644
+--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+@@ -16,6 +16,22 @@
+       };
+ };
+ 
++&ecspi1 {
++      fsl,spi-num-chipselects = <1>;
++      cs-gpios = <&gpio3 19 0>;
++      pinctrl-names = "default";
++      pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_sabreauto>;
++      status = "disabled"; /* pin conflict with WEIM NOR */
++
++      flash: m25p80@0 {
++              #address-cells = <1>;
++              #size-cells = <1>;
++              compatible = "st,m25p32";
++              spi-max-frequency = <20000000>;
++              reg = <0>;
++      };
++};
++
+ &fec {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_enet_2>;
+@@ -23,6 +39,34 @@
+       status = "okay";
+ };
+ 
++&gpmi {
++      pinctrl-names = "default";
++      pinctrl-0 = <&pinctrl_gpmi_nand_1>;
++      status = "okay";
++};
++
++&iomuxc {
++      pinctrl-names = "default";
++      pinctrl-0 = <&pinctrl_hog>;
++
++      hog {
++              pinctrl_hog: hoggrp {
++                      fsl,pins = <
++                              MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
++                              MX6QDL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
++                      >;
++              };
++      };
++
++      ecspi1 {
++              pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
++                      fsl,pins = <
++                              MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
++                      >;
++              };
++      };
++};
++
+ &uart4 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart4_1>;
+@@ -36,3 +80,22 @@
+       wp-gpios = <&gpio1 13 0>;
+       status = "okay";
+ };
++
++&weim {
++      pinctrl-names = "default";
++      pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>;
++      #address-cells = <2>;
++      #size-cells = <1>;
++      ranges = <0 0 0x08000000 0x08000000>;
++      status = "disabled"; /* pin conflict with SPI NOR */
++
++      nor@0,0 {
++              compatible = "cfi-flash";
++              reg = <0 0 0x02000000>;
++              #address-cells = <1>;
++              #size-cells = <1>;
++              bank-width = <2>;
++              fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
++                              0x0000c000 0x1404a38e 0x00000000>;
++      };
++};
+diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+index e21f6a8..39eafc2 100644
+--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+@@ -26,6 +26,22 @@
+                       gpio = <&gpio3 22 0>;
+                       enable-active-high;
+               };
++
++              reg_usb_h1_vbus: usb_h1_vbus {
++                      compatible = "regulator-fixed";
++                      regulator-name = "usb_h1_vbus";
++                      regulator-min-microvolt = <5000000>;
++                      regulator-max-microvolt = <5000000>;
++                      gpio = <&gpio1 29 0>;
++                      enable-active-high;
++              };
++
++              reg_audio: wm8962_supply {
++                      compatible = "regulator-fixed";
++                      regulator-name = "wm8962-supply";
++                      gpio = <&gpio4 10 0>;
++                      enable-active-high;
++              };
+       };
+ 
+       gpio-keys {
+@@ -34,15 +50,58 @@
+               volume-up {
+                       label = "Volume Up";
+                       gpios = <&gpio1 4 0>;
++                      gpio-key,wakeup;
+                       linux,code = <115>; /* KEY_VOLUMEUP */
+               };
+ 
+               volume-down {
+                       label = "Volume Down";
+                       gpios = <&gpio1 5 0>;
++                      gpio-key,wakeup;
+                       linux,code = <114>; /* KEY_VOLUMEDOWN */
+               };
+       };
++
++      sound {
++              compatible = "fsl,imx6q-sabresd-wm8962",
++                         "fsl,imx-audio-wm8962";
++              model = "wm8962-audio";
++              ssi-controller = <&ssi2>;
++              audio-codec = <&codec>;
++              audio-routing =
++                      "Headphone Jack", "HPOUTL",
++                      "Headphone Jack", "HPOUTR",
++                      "Ext Spk", "SPKOUTL",
++                      "Ext Spk", "SPKOUTR",
++                      "MICBIAS", "AMIC",
++                      "IN3R", "MICBIAS",
++                      "DMIC", "MICBIAS",
++                      "DMICDAT", "DMIC";
++              mux-int-port = <2>;
++              mux-ext-port = <3>;
++      };
++};
++
++&audmux {
++      pinctrl-names = "default";
++      pinctrl-0 = <&pinctrl_audmux_2>;
++      status = "okay";
++};
++
++&ecspi1 {
++      fsl,spi-num-chipselects = <1>;
++      cs-gpios = <&gpio4 9 0>;
++      pinctrl-names = "default";
++      pinctrl-0 = <&pinctrl_ecspi1_2>;
++      status = "okay";
++
++      flash: m25p80@0 {
++              #address-cells = <1>;
++              #size-cells = <1>;
++              compatible = "st,m25p32";
++              spi-max-frequency = <20000000>;
++              reg = <0>;
++      };
+ };
+ 
+ &fec {
+@@ -52,6 +111,102 @@
+       status = "okay";
+ };
+ 
++&i2c1 {
++      clock-frequency = <100000>;
++      pinctrl-names = "default";
++      pinctrl-0 = <&pinctrl_i2c1_2>;
++      status = "okay";
++
++      codec: wm8962@1a {
++              compatible = "wlf,wm8962";
++              reg = <0x1a>;
++              clocks = <&clks 201>;
++              DCVDD-supply = <&reg_audio>;
++              DBVDD-supply = <&reg_audio>;
++              AVDD-supply = <&reg_audio>;
++              CPVDD-supply = <&reg_audio>;
++              MICVDD-supply = <&reg_audio>;
++              PLLVDD-supply = <&reg_audio>;
++              SPKVDD1-supply = <&reg_audio>;
++              SPKVDD2-supply = <&reg_audio>;
++              gpio-cfg = <
++                      0x0000 /* 0:Default */
++                      0x0000 /* 1:Default */
++                      0x0013 /* 2:FN_DMICCLK */
++                      0x0000 /* 3:Default */
++                      0x8014 /* 4:FN_DMICCDAT */
++                      0x0000 /* 5:Default */
++              >;
++       };
++};
++
++&i2c3 {
++      clock-frequency = <100000>;
++      pinctrl-names = "default";
++      pinctrl-0 = <&pinctrl_i2c3_2>;
++      status = "okay";
++
++      egalax_ts@04 {
++              compatible = "eeti,egalax_ts";
++              reg = <0x04>;
++              interrupt-parent = <&gpio6>;
++              interrupts = <7 2>;
++              wakeup-gpios = <&gpio6 7 0>;
++      };
++};
++
++&iomuxc {
++      pinctrl-names = "default";
++      pinctrl-0 = <&pinctrl_hog>;
++
++      hog {
++              pinctrl_hog: hoggrp {
++                      fsl,pins = <
++                              MX6QDL_PAD_GPIO_4__GPIO1_IO04   0x80000000
++                              MX6QDL_PAD_GPIO_5__GPIO1_IO05   0x80000000
++                              MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
++                              MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
++                              MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
++                              MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
++                              MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
++                              MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
++                              MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
++                              MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x80000000
++                      >;
++              };
++      };
++};
++
++&ldb {
++      status = "okay";
++
++      lvds-channel@1 {
++              fsl,data-mapping = "spwg";
++              fsl,data-width = <18>;
++              status = "okay";
++
++              display-timings {
++                      native-mode = <&timing0>;
++                      timing0: hsd100pxn1 {
++                              clock-frequency = <65000000>;
++                              hactive = <1024>;
++                              vactive = <768>;
++                              hback-porch = <220>;
++                              hfront-porch = <40>;
++                              vback-porch = <21>;
++                              vfront-porch = <7>;
++                              hsync-len = <60>;
++                              vsync-len = <10>;
++                      };
++              };
++      };
++};
++
++&ssi2 {
++      fsl,mode = "i2s-slave";
++      status = "okay";
++};
++
+ &uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1_1>;
+@@ -59,6 +214,7 @@
+ };
+ 
+ &usbh1 {
++      vbus-supply = <&reg_usb_h1_vbus>;
+       status = "okay";
+ };
+ 
+diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+new file mode 100644
+index 0000000..a55113e
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+@@ -0,0 +1,137 @@
++/*
++ * Copyright 2013 Freescale Semiconductor, Inc.
++ *
++ * Author: Fabio Estevam <fabio.estevam@freescale.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++/ {
++      regulators {
++              compatible = "simple-bus";
++
++              reg_2p5v: 2p5v {
++                      compatible = "regulator-fixed";
++                      regulator-name = "2P5V";
++                      regulator-min-microvolt = <2500000>;
++                      regulator-max-microvolt = <2500000>;
++                      regulator-always-on;
++              };
++
++              reg_3p3v: 3p3v {
++                      compatible = "regulator-fixed";
++                      regulator-name = "3P3V";
++                      regulator-min-microvolt = <3300000>;
++                      regulator-max-microvolt = <3300000>;
++                      regulator-always-on;
++              };
++      };
++
++      sound {
++              compatible = "fsl,imx6-wandboard-sgtl5000",
++                           "fsl,imx-audio-sgtl5000";
++              model = "imx6-wandboard-sgtl5000";
++              ssi-controller = <&ssi1>;
++              audio-codec = <&codec>;
++              audio-routing =
++                      "MIC_IN", "Mic Jack",
++                      "Mic Jack", "Mic Bias",
++                      "Headphone Jack", "HP_OUT";
++              mux-int-port = <1>;
++              mux-ext-port = <3>;
++      };
++};
++
++&audmux {
++      pinctrl-names = "default";
++      pinctrl-0 = <&pinctrl_audmux_2>;
++      status = "okay";
++};
++
++&i2c2 {
++      clock-frequency = <100000>;
++      pinctrl-names = "default";
++      pinctrl-0 = <&pinctrl_i2c2_2>;
++      status = "okay";
++
++      codec: sgtl5000@0a {
++              compatible = "fsl,sgtl5000";
++              reg = <0x0a>;
++              clocks = <&clks 201>;
++              VDDA-supply = <&reg_2p5v>;
++              VDDIO-supply = <&reg_3p3v>;
++      };
++};
++
++&iomuxc {
++      pinctrl-names = "default";
++      pinctrl-0 = <&pinctrl_hog>;
++
++      hog {
++              pinctrl_hog: hoggrp {
++                      fsl,pins = <
++                              MX6QDL_PAD_GPIO_0__CCM_CLKO1     0x130b0
++                              MX6QDL_PAD_GPIO_2__GPIO1_IO02    0x80000000
++                              MX6QDL_PAD_EIM_DA9__GPIO3_IO09   0x80000000
++                              MX6QDL_PAD_EIM_EB1__GPIO2_IO29   0x80000000 /* WL_REF_ON */
++                              MX6QDL_PAD_EIM_A25__GPIO5_IO02   0x80000000 /* WL_RST_N */
++                              MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* WL_REG_ON */
++                              MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */
++                              MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */
++                      >;
++              };
++      };
++};
++
++&fec {
++      pinctrl-names = "default";
++      pinctrl-0 = <&pinctrl_enet_1>;
++      phy-mode = "rgmii";
++      status = "okay";
++};
++
++&ssi1 {
++      fsl,mode = "i2s-slave";
++      status = "okay";
++};
++
++&uart1 {
++      pinctrl-names = "default";
++      pinctrl-0 = <&pinctrl_uart1_1>;
++      status = "okay";
++};
++
++&uart3 {
++      pinctrl-names = "default";
++      pinctrl-0 = <&pinctrl_uart3_2>;
++      fsl,uart-has-rtscts;
++      status = "okay";
++};
++
++&usbh1 {
++      status = "okay";
++};
++
++&usdhc1 {
++      pinctrl-names = "default";
++      pinctrl-0 = <&pinctrl_usdhc1_2>;
++      cd-gpios = <&gpio1 2 0>;
++      status = "okay";
++};
++
++&usdhc2 {
++      pinctrl-names = "default";
++      pinctrl-0 = <&pinctrl_usdhc2_2>;
++      non-removable;
++      status = "okay";
++};
++
++&usdhc3 {
++      pinctrl-names = "default";
++      pinctrl-0 = <&pinctrl_usdhc3_2>;
++      cd-gpios = <&gpio3 9 0>;
++      status = "okay";
++};
+diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
+index 9e8296e..ccd55c2 100644
+--- a/arch/arm/boot/dts/imx6qdl.dtsi
++++ b/arch/arm/boot/dts/imx6qdl.dtsi
+@@ -14,11 +14,6 @@
+ 
+ / {
+       aliases {
+-              serial0 = &uart1;
+-              serial1 = &uart2;
+-              serial2 = &uart3;
+-              serial3 = &uart4;
+-              serial4 = &uart5;
+               gpio0 = &gpio1;
+               gpio1 = &gpio2;
+               gpio2 = &gpio3;
+@@ -26,6 +21,18 @@
+               gpio4 = &gpio5;
+               gpio5 = &gpio6;
+               gpio6 = &gpio7;
++              i2c0 = &i2c1;
++              i2c1 = &i2c2;
++              i2c2 = &i2c3;
++              serial0 = &uart1;
++              serial1 = &uart2;
++              serial2 = &uart3;
++              serial3 = &uart4;
++              serial4 = &uart5;
++              spi0 = &ecspi1;
++              spi1 = &ecspi2;
++              spi2 = &ecspi3;
++              spi3 = &ecspi4;
+       };
+ 
+       intc: interrupt-controller@00a01000 {
+@@ -81,15 +88,14 @@
+                       #size-cells = <1>;
+                       reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
+                       reg-names = "gpmi-nand", "bch";
+-                      interrupts = <0 13 0x04>, <0 15 0x04>;
+-                      interrupt-names = "gpmi-dma", "bch";
++                      interrupts = <0 15 0x04>;
++                      interrupt-names = "bch";
+                       clocks = <&clks 152>, <&clks 153>, <&clks 151>,
+                                <&clks 150>, <&clks 149>;
+                       clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
+                                     "gpmi_bch_apb", "per1_bch";
+                       dmas = <&dma_apbh 0>;
+                       dma-names = "rx-tx";
+-                      fsl,gpmi-dma-channel = <0>;
+                       status = "disabled";
+               };
+ 
+@@ -106,6 +112,8 @@
+                       interrupts = <0 92 0x04>;
+                       cache-unified;
+                       cache-level = <2>;
++                      arm,tag-latency = <4 2 3>;
++                      arm,data-latency = <4 2 3>;
+               };
+ 
+               pmu {
+@@ -182,6 +190,8 @@
+                                       interrupts = <0 26 0x04>;
+                                       clocks = <&clks 160>, <&clks 161>;
+                                       clock-names = "ipg", "per";
++                                      dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
++                                      dma-names = "rx", "tx";
+                                       status = "disabled";
+                               };
+ 
+@@ -195,6 +205,9 @@
+                                       reg = <0x02028000 0x4000>;
+                                       interrupts = <0 46 0x04>;
+                                       clocks = <&clks 178>;
++                                      dmas = <&sdma 37 1 0>,
++                                             <&sdma 38 1 0>;
++                                      dma-names = "rx", "tx";
+                                       fsl,fifo-depth = <15>;
+                                       fsl,ssi-dma-events = <38 37>;
+                                       status = "disabled";
+@@ -205,6 +218,9 @@
+                                       reg = <0x0202c000 0x4000>;
+                                       interrupts = <0 47 0x04>;
+                                       clocks = <&clks 179>;
++                                      dmas = <&sdma 41 1 0>,
++                                             <&sdma 42 1 0>;
++                                      dma-names = "rx", "tx";
+                                       fsl,fifo-depth = <15>;
+                                       fsl,ssi-dma-events = <42 41>;
+                                       status = "disabled";
+@@ -215,6 +231,9 @@
+                                       reg = <0x02030000 0x4000>;
+                                       interrupts = <0 48 0x04>;
+                                       clocks = <&clks 180>;
++                                      dmas = <&sdma 45 1 0>,
++                                             <&sdma 46 1 0>;
++                                      dma-names = "rx", "tx";
+                                       fsl,fifo-depth = <15>;
+                                       fsl,ssi-dma-events = <46 45>;
+                                       status = "disabled";
+@@ -276,17 +295,23 @@
+                       };
+ 
+                       can1: flexcan@02090000 {
++                              compatible = "fsl,imx6q-flexcan";
+                               reg = <0x02090000 0x4000>;
+                               interrupts = <0 110 0x04>;
++                              clocks = <&clks 108>, <&clks 109>;
++                              clock-names = "ipg", "per";
+                       };
+ 
+                       can2: flexcan@02094000 {
++                              compatible = "fsl,imx6q-flexcan";
+                               reg = <0x02094000 0x4000>;
+                               interrupts = <0 111 0x04>;
++                              clocks = <&clks 110>, <&clks 111>;
++                              clock-names = "ipg", "per";
+                       };
+ 
+                       gpt: gpt@02098000 {
+-                              compatible = "fsl,imx6q-gpt";
++                              compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
+                               reg = <0x02098000 0x4000>;
+                               interrupts = <0 55 0x04>;
+                               clocks = <&clks 119>, <&clks 120>;
+@@ -489,6 +514,13 @@
+                               };
+                       };
+ 
++                      tempmon: tempmon {
++                              compatible = "fsl,imx6q-tempmon";
++                              interrupts = <0 49 0x04>;
++                              fsl,tempmon = <&anatop>;
++                              fsl,tempmon-data = <&ocotp>;
++                      };
++
+                       usbphy1: usbphy@020c9000 {
+                               compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
+                               reg = <0x020c9000 0x1000>;
+@@ -544,6 +576,713 @@
+                               reg = <0x020e0000 0x38>;
+                       };
+ 
++                      iomuxc: iomuxc@020e0000 {
++                              compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
++                              reg = <0x020e0000 0x4000>;
++
++                              audmux {
++                                      pinctrl_audmux_1: audmux-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_SD2_DAT0__AUD4_RXD  0x80000000
++                                                      MX6QDL_PAD_SD2_DAT3__AUD4_TXC  0x80000000
++                                                      MX6QDL_PAD_SD2_DAT2__AUD4_TXD  0x80000000
++                                                      MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
++                                              >;
++                                      };
++
++                                      pinctrl_audmux_2: audmux-2 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_CSI0_DAT7__AUD3_RXD  0x80000000
++                                                      MX6QDL_PAD_CSI0_DAT4__AUD3_TXC  0x80000000
++                                                      MX6QDL_PAD_CSI0_DAT5__AUD3_TXD  0x80000000
++                                                      MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
++                                              >;
++                                      };
++
++                                      pinctrl_audmux_3: audmux-3 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_DISP0_DAT16__AUD5_TXC  0x80000000
++                                                      MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000
++                                                      MX6QDL_PAD_DISP0_DAT19__AUD5_RXD  0x80000000
++                                              >;
++                                      };
++                              };
++
++                              ecspi1 {
++                                      pinctrl_ecspi1_1: ecspi1grp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
++                                                      MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
++                                                      MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
++                                              >;
++                                      };
++
++                                      pinctrl_ecspi1_2: ecspi1grp-2 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
++                                                      MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
++                                                      MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
++                                              >;
++                                      };
++                              };
++
++                              ecspi3 {
++                                      pinctrl_ecspi3_1: ecspi3grp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
++                                                      MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
++                                                      MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
++                                              >;
++                                      };
++                              };
++
++                              enet {
++                                      pinctrl_enet_1: enetgrp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
++                                                      MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
++                                                      MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
++                                                      MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
++                                                      MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
++                                                      MX6QDL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
++                                              >;
++                                      };
++
++                                      pinctrl_enet_2: enetgrp-2 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_KEY_COL1__ENET_MDIO        0x1b0b0
++                                                      MX6QDL_PAD_KEY_COL2__ENET_MDC         0x1b0b0
++                                                      MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
++                                                      MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
++                                                      MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
++                                              >;
++                                      };
++
++                                      pinctrl_enet_3: enetgrp-3 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
++                                                      MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
++                                                      MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
++                                                      MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
++                                                      MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
++                                                      MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
++                                                      MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
++                                              >;
++                                      };
++                              };
++
++                              esai {
++                                      pinctrl_esai_1: esaigrp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030
++                                                      MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK  0x1b030
++                                                      MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS     0x1b030
++                                                      MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2  0x1b030
++                                                      MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3   0x1b030
++                                                      MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1   0x1b030
++                                                      MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0    0x1b030
++                                                      MX6QDL_PAD_NANDF_CS2__ESAI_TX0       0x1b030
++                                                      MX6QDL_PAD_NANDF_CS3__ESAI_TX1       0x1b030
++                                              >;
++                                      };
++
++                                      pinctrl_esai_2: esaigrp-2 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
++                                                      MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS    0x1b030
++                                                      MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
++                                                      MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3     0x1b030
++                                                      MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1  0x1b030
++                                                      MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0   0x1b030
++                                                      MX6QDL_PAD_GPIO_17__ESAI_TX0        0x1b030
++                                                      MX6QDL_PAD_NANDF_CS3__ESAI_TX1      0x1b030
++                                                      MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK   0x1b030
++                                                      MX6QDL_PAD_GPIO_9__ESAI_RX_FS       0x1b030
++                                              >;
++                                      };
++                              };
++
++                              flexcan1 {
++                                      pinctrl_flexcan1_1: flexcan1grp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
++                                                      MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
++                                              >;
++                                      };
++
++                                      pinctrl_flexcan1_2: flexcan1grp-2 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_GPIO_7__FLEXCAN1_TX   0x80000000
++                                                      MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
++                                              >;
++                                      };
++                              };
++
++                              flexcan2 {
++                                      pinctrl_flexcan2_1: flexcan2grp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
++                                                      MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
++                                              >;
++                                      };
++                              };
++
++                              gpmi-nand {
++                                      pinctrl_gpmi_nand_1: gpmi-nand-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
++                                                      MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
++                                                      MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
++                                                      MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
++                                                      MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
++                                                      MX6QDL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
++                                                      MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
++                                                      MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
++                                                      MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
++                                                      MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
++                                                      MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
++                                                      MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
++                                                      MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
++                                                      MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
++                                                      MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
++                                                      MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
++                                                      MX6QDL_PAD_SD4_DAT0__NAND_DQS      0x00b1
++                                              >;
++                                      };
++                              };
++
++                              hdmi_hdcp {
++                                      pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
++                                                      MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
++                                              >;
++                                      };
++
++                                      pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
++                                                      MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
++                                              >;
++                                      };
++
++                                      pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL  0x4001b8b1
++                                                      MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
++                                              >;
++                                      };
++                              };
++
++                              hdmi_cec {
++                                      pinctrl_hdmi_cec_1: hdmicecgrp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
++                                              >;
++                                      };
++
++                                      pinctrl_hdmi_cec_2: hdmicecgrp-2 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
++                                              >;
++                                      };
++                              };
++
++                              i2c1 {
++                                      pinctrl_i2c1_1: i2c1grp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
++                                                      MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
++                                              >;
++                                      };
++
++                                      pinctrl_i2c1_2: i2c1grp-2 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
++                                                      MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
++                                              >;
++                                      };
++                              };
++
++                              i2c2 {
++                                      pinctrl_i2c2_1: i2c2grp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
++                                                      MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
++                                              >;
++                                      };
++
++                                      pinctrl_i2c2_2: i2c2grp-2 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
++                                                      MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
++                                              >;
++                                      };
++
++                                      pinctrl_i2c2_3: i2c2grp-3 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_EIM_EB2__I2C2_SCL  0x4001b8b1
++                                                      MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
++                                              >;
++                                      };
++                              };
++
++                              i2c3 {
++                                      pinctrl_i2c3_1: i2c3grp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
++                                                      MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
++                                              >;
++                                      };
++
++                                      pinctrl_i2c3_2: i2c3grp-2 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
++                                                      MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
++                                              >;
++                                      };
++
++                                      pinctrl_i2c3_3: i2c3grp-3 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_GPIO_5__I2C3_SCL  0x4001b8b1
++                                                      MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
++                                              >;
++                                      };
++
++                                      pinctrl_i2c3_4: i2c3grp-4 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_GPIO_3__I2C3_SCL  0x4001b8b1
++                                                      MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
++                                              >;
++                                      };
++                              };
++
++                              ipu1 {
++                                      pinctrl_ipu1_1: ipu1grp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
++                                                      MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
++                                                      MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
++                                                      MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
++                                                      MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04        0x80000000
++                                                      MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
++                                                      MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
++                                                      MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
++                                                      MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
++                                                      MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
++                                                      MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
++                                                      MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
++                                                      MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
++                                                      MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
++                                                      MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
++                                                      MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
++                                                      MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
++                                                      MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
++                                                      MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
++                                                      MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
++                                                      MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
++                                                      MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
++                                                      MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
++                                                      MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
++                                                      MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
++                                                      MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
++                                                      MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
++                                                      MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
++                                                      MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
++                                              >;
++                                      };
++
++                                      pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x80000000
++                                                      MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x80000000
++                                                      MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x80000000
++                                                      MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x80000000
++                                                      MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x80000000
++                                                      MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x80000000
++                                                      MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x80000000
++                                                      MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x80000000
++                                                      MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
++                                                      MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x80000000
++                                                      MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x80000000
++                                                      MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x80000000
++                                              >;
++                                      };
++
++                                      pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04   0x80000000
++                                                      MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05   0x80000000
++                                                      MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06   0x80000000
++                                                      MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07   0x80000000
++                                                      MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08   0x80000000
++                                                      MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09   0x80000000
++                                                      MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10  0x80000000
++                                                      MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11  0x80000000
++                                                      MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12  0x80000000
++                                                      MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13  0x80000000
++                                                      MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14  0x80000000
++                                                      MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15  0x80000000
++                                                      MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16  0x80000000
++                                                      MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17  0x80000000
++                                                      MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18  0x80000000
++                                                      MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19  0x80000000
++                                                      MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
++                                                      MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC    0x80000000
++                                                      MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC   0x80000000
++                                              >;
++                                      };
++                              };
++
++                              mlb {
++                                      pinctrl_mlb_1: mlbgrp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_GPIO_3__MLB_CLK  0x71
++                                                      MX6QDL_PAD_GPIO_6__MLB_SIG  0x71
++                                                      MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
++                                              >;
++                                      };
++
++                                      pinctrl_mlb_2: mlbgrp-2 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71
++                                                      MX6QDL_PAD_GPIO_6__MLB_SIG    0x71
++                                                      MX6QDL_PAD_GPIO_2__MLB_DATA   0x71
++                                              >;
++                                      };
++                              };
++
++                              pwm0 {
++                                      pinctrl_pwm0_1: pwm0grp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
++                                              >;
++                                      };
++                              };
++
++                              pwm3 {
++                                      pinctrl_pwm3_1: pwm3grp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
++                                              >;
++                                      };
++                              };
++
++                              spdif {
++                                      pinctrl_spdif_1: spdifgrp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
++                                              >;
++                                      };
++
++                                      pinctrl_spdif_2: spdifgrp-2 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_GPIO_16__SPDIF_IN  0x1b0b0
++                                                      MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
++                                              >;
++                                      };
++                              };
++
++                              uart1 {
++                                      pinctrl_uart1_1: uart1grp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
++                                                      MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
++                                              >;
++                                      };
++                              };
++
++                              uart2 {
++                                      pinctrl_uart2_1: uart2grp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
++                                                      MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
++                                              >;
++                                      };
++
++                                      pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_EIM_D26__UART2_RX_DATA   0x1b0b1
++                                                      MX6QDL_PAD_EIM_D27__UART2_TX_DATA   0x1b0b1
++                                                      MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
++                                                      MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
++                                              >;
++                                      };
++                              };
++
++                              uart3 {
++                                      pinctrl_uart3_1: uart3grp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
++                                                      MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
++                                                      MX6QDL_PAD_EIM_D30__UART3_CTS_B   0x1b0b1
++                                                      MX6QDL_PAD_EIM_EB3__UART3_RTS_B   0x1b0b1
++                                              >;
++                                      };
++
++                                      pinctrl_uart3_2: uart3grp-2 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
++                                                      MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
++                                                      MX6QDL_PAD_EIM_D23__UART3_CTS_B   0x1b0b1
++                                                      MX6QDL_PAD_EIM_EB3__UART3_RTS_B   0x1b0b1
++                                              >;
++                                      };
++                              };
++
++                              uart4 {
++                                      pinctrl_uart4_1: uart4grp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
++                                                      MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
++                                              >;
++                                      };
++                              };
++
++                              usbotg {
++                                      pinctrl_usbotg_1: usbotggrp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
++                                              >;
++                                      };
++
++                                      pinctrl_usbotg_2: usbotggrp-2 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
++                                              >;
++                                      };
++                              };
++
++                              usbh2 {
++                                      pinctrl_usbh2_1: usbh2grp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_RGMII_TXC__USB_H2_DATA      0x40013030
++                                                      MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
++                                              >;
++                                      };
++
++                                      pinctrl_usbh2_2: usbh2grp-2 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
++                                              >;
++                                      };
++                              };
++
++                              usbh3 {
++                                      pinctrl_usbh3_1: usbh3grp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030
++                                                      MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE  0x40013030
++                                              >;
++                                      };
++
++                                      pinctrl_usbh3_2: usbh3grp-2 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
++                                              >;
++                                      };
++                              };
++
++                              usdhc1 {
++                                      pinctrl_usdhc1_1: usdhc1grp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17059
++                                                      MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10059
++                                                      MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
++                                                      MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
++                                                      MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
++                                                      MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
++                                                      MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
++                                                      MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
++                                                      MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
++                                                      MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
++                                              >;
++                                      };
++
++                                      pinctrl_usdhc1_2: usdhc1grp-2 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17059
++                                                      MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10059
++                                                      MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
++                                                      MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
++                                                      MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
++                                                      MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
++                                              >;
++                                      };
++                              };
++
++                              usdhc2 {
++                                      pinctrl_usdhc2_1: usdhc2grp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17059
++                                                      MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10059
++                                                      MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
++                                                      MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
++                                                      MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
++                                                      MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
++                                                      MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
++                                                      MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
++                                                      MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
++                                                      MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
++                                              >;
++                                      };
++
++                                      pinctrl_usdhc2_2: usdhc2grp-2 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17059
++                                                      MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10059
++                                                      MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
++                                                      MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
++                                                      MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
++                                                      MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
++                                              >;
++                                      };
++                              };
++
++                              usdhc3 {
++                                      pinctrl_usdhc3_1: usdhc3grp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
++                                                      MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
++                                                      MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
++                                                      MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
++                                                      MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
++                                                      MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
++                                                      MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
++                                                      MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
++                                                      MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
++                                                      MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
++                                              >;
++                                      };
++
++                                      pinctrl_usdhc3_2: usdhc3grp-2 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
++                                                      MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
++                                                      MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
++                                                      MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
++                                                      MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
++                                                      MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
++                                              >;
++                                      };
++                              };
++
++                              usdhc4 {
++                                      pinctrl_usdhc4_1: usdhc4grp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17059
++                                                      MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10059
++                                                      MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
++                                                      MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
++                                                      MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
++                                                      MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
++                                                      MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
++                                                      MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
++                                                      MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
++                                                      MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
++                                              >;
++                                      };
++
++                                      pinctrl_usdhc4_2: usdhc4grp-2 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17059
++                                                      MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10059
++                                                      MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
++                                                      MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
++                                                      MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
++                                                      MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
++                                              >;
++                                      };
++                              };
++
++                              weim {
++                                      pinctrl_weim_cs0_1: weim_cs0grp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
++                                              >;
++                                      };
++
++                                      pinctrl_weim_nor_1: weim_norgrp-1 {
++                                              fsl,pins = <
++                                                      MX6QDL_PAD_EIM_OE__EIM_OE_B     0xb0b1
++                                                      MX6QDL_PAD_EIM_RW__EIM_RW       0xb0b1
++                                                      MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
++                                                      /* data */
++                                                      MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
++                                                      MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
++                                                      MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
++                                                      MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
++                                                      MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
++                                                      MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
++                                                      MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
++                                                      MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
++                                                      MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
++                                                      MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
++                                                      MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
++                                                      MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
++                                                      MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
++                                                      MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
++                                                      MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
++                                                      MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
++                                                      /* address */
++                                                      MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
++                                                      MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
++                                                      MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
++                                                      MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
++                                                      MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
++                                                      MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
++                                                      MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
++                                                      MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
++                                                      MX6QDL_PAD_EIM_DA15__EIM_AD15  0xb0b1
++                                                      MX6QDL_PAD_EIM_DA14__EIM_AD14  0xb0b1
++                                                      MX6QDL_PAD_EIM_DA13__EIM_AD13  0xb0b1
++                                                      MX6QDL_PAD_EIM_DA12__EIM_AD12  0xb0b1
++                                                      MX6QDL_PAD_EIM_DA11__EIM_AD11  0xb0b1
++                                                      MX6QDL_PAD_EIM_DA10__EIM_AD10  0xb0b1
++                                                      MX6QDL_PAD_EIM_DA9__EIM_AD09   0xb0b1
++                                                      MX6QDL_PAD_EIM_DA8__EIM_AD08   0xb0b1
++                                                      MX6QDL_PAD_EIM_DA7__EIM_AD07   0xb0b1
++                                                      MX6QDL_PAD_EIM_DA6__EIM_AD06   0xb0b1
++                                                      MX6QDL_PAD_EIM_DA5__EIM_AD05   0xb0b1
++                                                      MX6QDL_PAD_EIM_DA4__EIM_AD04   0xb0b1
++                                                      MX6QDL_PAD_EIM_DA3__EIM_AD03   0xb0b1
++                                                      MX6QDL_PAD_EIM_DA2__EIM_AD02   0xb0b1
++                                                      MX6QDL_PAD_EIM_DA1__EIM_AD01   0xb0b1
++                                                      MX6QDL_PAD_EIM_DA0__EIM_AD00   0xb0b1
++                                              >;
++                                      };
++                              };
++                      };
++
+                       ldb: ldb@020e0008 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+@@ -553,13 +1292,11 @@
+ 
+                               lvds-channel@0 {
+                                       reg = <0>;
+-                                      crtcs = <&ipu1 0>;
+                                       status = "disabled";
+                               };
+ 
+                               lvds-channel@1 {
+                                       reg = <1>;
+-                                      crtcs = <&ipu1 1>;
+                                       status = "disabled";
+                               };
+                       };
+@@ -580,6 +1317,7 @@
+                               interrupts = <0 2 0x04>;
+                               clocks = <&clks 155>, <&clks 155>;
+                               clock-names = "ipg", "ahb";
++                              #dma-cells = <3>;
+                               fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
+                       };
+               };
+@@ -638,7 +1376,7 @@
+                               status = "disabled";
+                       };
+ 
+-                      usbmisc: usbmisc: usbmisc@02184800 {
++                      usbmisc: usbmisc@02184800 {
+                               #index-cells = <1>;
+                               compatible = "fsl,imx6q-usbmisc";
+                               reg = <0x02184800 0x200>;
+@@ -742,21 +1480,18 @@
+                               reg = <0x021b4000 0x4000>;
+                       };
+ 
+-                      weim@021b8000 {
++                      weim: weim@021b8000 {
++                              compatible = "fsl,imx6q-weim";
+                               reg = <0x021b8000 0x4000>;
+                               interrupts = <0 14 0x04>;
++                              clocks = <&clks 196>;
+                       };
+ 
+-                      ocotp@021bc000 {
+-                              compatible = "fsl,imx6q-ocotp";
++                      ocotp: ocotp@021bc000 {
++                              compatible = "fsl,imx6q-ocotp", "syscon";
+                               reg = <0x021bc000 0x4000>;
+                       };
+ 
+-                      ocotp@021c0000 {
+-                              reg = <0x021c0000 0x4000>;
+-                              interrupts = <0 21 0x04>;
+-                      };
+-
+                       tzasc@021d0000 { /* TZASC1 */
+                               reg = <0x021d0000 0x4000>;
+                               interrupts = <0 108 0x04>;
+@@ -792,6 +1527,8 @@
+                               interrupts = <0 27 0x04>;
+                               clocks = <&clks 160>, <&clks 161>;
+                               clock-names = "ipg", "per";
++                              dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
++                              dma-names = "rx", "tx";
+                               status = "disabled";
+                       };
+ 
+@@ -801,6 +1538,8 @@
+                               interrupts = <0 28 0x04>;
+                               clocks = <&clks 160>, <&clks 161>;
+                               clock-names = "ipg", "per";
++                              dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
++                              dma-names = "rx", "tx";
+                               status = "disabled";
+                       };
+ 
+@@ -810,6 +1549,8 @@
+                               interrupts = <0 29 0x04>;
+                               clocks = <&clks 160>, <&clks 161>;
+                               clock-names = "ipg", "per";
++                              dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
++                              dma-names = "rx", "tx";
+                               status = "disabled";
+                       };
+ 
+@@ -819,6 +1560,8 @@
+                               interrupts = <0 30 0x04>;
+                               clocks = <&clks 160>, <&clks 161>;
+                               clock-names = "ipg", "per";
++                              dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
++                              dma-names = "rx", "tx";
+                               status = "disabled";
+                       };
+               };

diff --git a/src/patches/kernel/wandboard/dts/0002-ARM-dts-imx6qdl-wandboard-add-gpio-lines-to-wandboar.patch b/src/patches/kernel/wandboard/dts/0002-ARM-dts-imx6qdl-wandboard-add-gpio-lines-to-wandboar.patch
new file mode 100644 (file)
index 0000000..009db26
--- /dev/null
+++ b/src/patches/kernel/wandboard/dts/0002-ARM-dts-imx6qdl-wandboard-add-gpio-lines-to-wandboar.patch
@@ -0,0 +1,41 @@
+From df41a18b5ac1401c96dcbce99baa50e339494eba Mon Sep 17 00:00:00 2001
+From: Mike Panetta <panetta.mike@gmail.com>
+Date: Tue, 30 Jul 2013 20:33:26 -0400
+Subject: [PATCH 2/5] ARM: dts: imx6qdl-wandboard: add gpio lines to wandboard
+
+Signed-off-by: Mike Panetta <panetta.mike@gmail.com>
+---
+ arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+index 35f5479..a302e95 100644
+--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+@@ -92,6 +92,23 @@
+                       >;
+               };
+       };
++
++      gpio {
++              pinctrl_gpio: gpiogrp {
++                      fsl,pins = <
++                              MX6QDL_PAD_EIM_DA12__GPIO3_IO12   0x80000000 /* GPIO3_12 EDM pin 255 */
++                              MX6QDL_PAD_EIM_DA11__GPIO3_IO11   0x80000000 /* GPIO3_11 EDM pin 256 */
++                              MX6QDL_PAD_EIM_DA10__GPIO3_IO10   0x80000000 /* GPIO3_10 EDM pin 257 */
++                              MX6QDL_PAD_EIM_D27__GPIO3_IO27    0x80000000 /* GPIO3_27 EDM pin 258 */
++                              MX6QDL_PAD_EIM_D26__GPIO3_IO26    0x80000000 /* GPIO3_26 EDM pin 259 */
++                              MX6QDL_PAD_EIM_BCLK__GPIO6_IO31   0x80000000 /* GPIO6_31 EDM pin 260 */
++                              MX6QDL_PAD_EIM_DA8__GPIO3_IO08    0x80000000 /* GPIO3_8  EDM pin 261 */
++                              MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x80000000 /* GPIO1_24 EDM pin 262 */
++                              MX6QDL_PAD_GPIO_19__GPIO4_IO05    0x80000000 /* GPIO4_5  EDM pin 263 */
++                              MX6QDL_PAD_SD3_RST__GPIO7_IO08    0x80000000 /* GPIO7_8  EDM pin 264 */
++                      >;
++              };
++      };
+ };
+ 
+ &fec {
+-- 
+1.8.4.rc3
+

diff --git a/src/patches/kernel/wandboard/dts/0003-ARM-dts-imx6qdl-wandboard-Add-support-for-i2c1.patch b/src/patches/kernel/wandboard/dts/0003-ARM-dts-imx6qdl-wandboard-Add-support-for-i2c1.patch
new file mode 100644 (file)
index 0000000..7c4e5dd
--- /dev/null
+++ b/src/patches/kernel/wandboard/dts/0003-ARM-dts-imx6qdl-wandboard-Add-support-for-i2c1.patch
@@ -0,0 +1,33 @@
+From aefbac1e9377311240656ae5061346acb8612e1b Mon Sep 17 00:00:00 2001
+From: Michael Panetta <panetta.mike@gmail.com>
+Date: Tue, 6 Aug 2013 21:32:50 -0400
+Subject: [PATCH 3/5] ARM: dts: imx6qdl-wandboard: Add support for i2c1.
+
+This patch adds support for i2c1 to the wandboard common dtsi file.
+
+Signed-off-by: Michael Panetta <panetta.mike@gmail.com>
+---
+ arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+index a302e95..d429c0b 100644
+--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+@@ -58,6 +58,13 @@
+       status = "okay";
+ };
+ 
++&i2c1 {
++      clock-frequency = <100000>;
++      pinctrl-names = "default";
++      pinctrl-0 = <&pinctrl_i2c1_1>;
++      status = "okay";
++};
++
+ &i2c2 {
+       clock-frequency = <100000>;
+       pinctrl-names = "default";
+-- 
+1.8.4.rc3
+

diff --git a/src/patches/kernel/wandboard/dts/0004-ARM-dts-wandboard-add-binding-for-wand-rfkill-driver.patch b/src/patches/kernel/wandboard/dts/0004-ARM-dts-wandboard-add-binding-for-wand-rfkill-driver.patch
new file mode 100644 (file)
index 0000000..54bb388
--- /dev/null
+++ b/src/patches/kernel/wandboard/dts/0004-ARM-dts-wandboard-add-binding-for-wand-rfkill-driver.patch
@@ -0,0 +1,52 @@
+From 1305ac7e9308dcd59c3acc205bc95097cad87ed5 Mon Sep 17 00:00:00 2001
+From: Vladimir Ermakov <vooon341@gmail.com>
+Date: Fri, 16 Aug 2013 06:52:26 +0400
+Subject: [PATCH 5/5] ARM: dts: wandboard: add binding for wand-rfkill driver
+
+Required gpios pincontrol selected in hog. Add binding only.
+Disabled non-removable, because after unblocking need to redetect SDIO device.
+
+Signed-off-by: Vladimir Ermakov <vooon341@gmail.com>
+---
+ arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 18 +++++++++++++++++-
+ 1 file changed, 17 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+index 737805b..c1ef3bd 100644
+--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+@@ -50,6 +50,22 @@
+               spdif-controller = <&spdif>;
+               spdif-out;
+       };
++
++      rfkill {
++              compatible = "wand,imx6qdl-wandboard-rfkill";
++              pinctrl-names = "default";
++              pinctrl-0 = <>;
++
++              bluetooth-on = <&gpio3 13 0>;
++              bluetooth-wake = <&gpio3 14 0>;
++              bluetooth-host-wake = <&gpio3 15 0>;
++
++              wifi-ref-on = <&gpio2 29 0>;
++              wifi-rst-n = <&gpio5 2 0>;
++              wifi-reg-on = <&gpio1 26 0>;
++              wifi-host-wake = <&gpio1 29 0>;
++              wifi-wake = <&gpio1 30 0>;
++      };
+ };
+ 
+ &audmux {
+@@ -175,7 +191,7 @@
+ &usdhc2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usdhc2_2>;
+-      non-removable;
++      //non-removable;
+       status = "okay";
+ };
+ 
+-- 
+1.8.4.rc3
+

diff --git a/src/patches/kernel/wandboard/dts/0005-ARM-dts-imx6qdl-add-pcie-device-node.patch b/src/patches/kernel/wandboard/dts/0005-ARM-dts-imx6qdl-add-pcie-device-node.patch
new file mode 100644 (file)
index 0000000..e78d9ba
--- /dev/null
+++ b/src/patches/kernel/wandboard/dts/0005-ARM-dts-imx6qdl-add-pcie-device-node.patch
@@ -0,0 +1,38 @@
+From 3a57291fa4ca7f7647d826f5b47082ef306d839f Mon Sep 17 00:00:00 2001
+From: Sean Cross <xobs@kosagi.com>
+Date: Thu, 26 Sep 2013 10:51:09 +0800
+Subject: [PATCH] ARM: dts: imx6qdl: add pcie device node
+
+Add pcie device node for imx6qdl.
+
+Signed-off-by: Sean Cross <xobs@kosagi.com>
+Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
+---
+ arch/arm/boot/dts/imx6qdl.dtsi | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+--- a/arch/arm/boot/dts/imx6qdl.dtsi
++++ b/arch/arm/boot/dts/imx6qdl.dtsi
+@@ -108,6 +108,22 @@
+                       cache-level = <2>;
+               };
+ 
++              pcie: pcie@0x01000000 {
++                      compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
++                      reg = <0x01ffc000 0x4000>; /* DBI */
++                      #address-cells = <3>;
++                      #size-cells = <2>;
++                      device_type = "pci";
++                      ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
++                                0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
++                                0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
++                      num-lanes = <1>;
++                      interrupts = <0 123 0x04>;
++                      clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
++                      clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
++                      status = "disabled";
++              };
++
+               pmu {
+                       compatible = "arm,cortex-a9-pmu";
+                       interrupts = <0 94 0x04>;

diff --git a/src/patches/kernel/wandboard/imx/0001-i2c-imx-retry-on-NAK.patch b/src/patches/kernel/wandboard/imx/0001-i2c-imx-retry-on-NAK.patch
new file mode 100644 (file)
index 0000000..e876c6e
--- /dev/null
+++ b/src/patches/kernel/wandboard/imx/0001-i2c-imx-retry-on-NAK.patch
@@ -0,0 +1,38 @@
+From: Tim Harvey <tharvey@gateworks.com>
+Subject: [PATCH] i2c: imx: retry on NAK
+
+In case of busy i2c try again to get ACK.
+
+Signed-off-by: Tim Harvey <tharvey@gateworks.com>
+Tested-by: Luka Perkov <luka@openwrt.org>
+---
+ drivers/i2c/busses/i2c-imx.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/drivers/i2c/busses/i2c-imx.c
++++ b/drivers/i2c/busses/i2c-imx.c
+@@ -62,6 +62,7 @@
+ 
+ /* Default value */
+ #define IMX_I2C_BIT_RATE      100000  /* 100kHz */
++#define IMX_I2C_MAX_RETRIES   3       /* number of retries to attempt */
+ 
+ /* IMX I2C registers */
+ #define IMX_I2C_IADR  0x00    /* i2c slave address */
+@@ -198,7 +199,7 @@ static int i2c_imx_acked(struct imx_i2c_
+ {
+       if (readb(i2c_imx->base + IMX_I2C_I2SR) & I2SR_RXAK) {
+               dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
+-              return -EIO;  /* No ACK */
++              return -EAGAIN; /* try again */
+       }
+ 
+       dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
+@@ -533,6 +534,7 @@ static int __init i2c_imx_probe(struct p
+       i2c_imx->adapter.dev.parent     = &pdev->dev;
+       i2c_imx->adapter.nr             = pdev->id;
+       i2c_imx->adapter.dev.of_node    = pdev->dev.of_node;
++      i2c_imx->adapter.retries        = IMX_I2C_MAX_RETRIES;
+       i2c_imx->base                   = base;
+ 
+       pinctrl = devm_pinctrl_get_select_default(&pdev->dev);

diff --git a/src/patches/kernel/wandboard/imx/0002-i.MX6-Wandboard-add-CKO1-clock-output.patch b/src/patches/kernel/wandboard/imx/0002-i.MX6-Wandboard-add-CKO1-clock-output.patch
new file mode 100644 (file)
index 0000000..b24c7ad
--- /dev/null
+++ b/src/patches/kernel/wandboard/imx/0002-i.MX6-Wandboard-add-CKO1-clock-output.patch
@@ -0,0 +1,29 @@
+From fc69065e84165aef5ba7a837d9d2e668bd03b146 Mon Sep 17 00:00:00 2001
+From: Vladimir Ermakov <vooon341@gmail.com>
+Date: Wed, 10 Jul 2013 03:03:51 +0400
+Subject: [PATCH 7/8] i.MX6 Wandboard add CKO1 clock output
+
+stgl5000 uses clock from imx CKO1 pad.
+
+Signed-off-by: Vladimir Ermakov <vooon341@gmail.com>
+---
+ arch/arm/mach-imx/mach-imx6q.c |    3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
+index 5536fd8..bf9a30b 100644
+--- a/arch/arm/mach-imx/mach-imx6q.c
++++ b/arch/arm/mach-imx/mach-imx6q.c
+@@ -166,6 +166,9 @@ static void __init imx6q_init_machine(void)
+       if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
+               imx6q_sabrelite_init();
+ 
++      if (of_machine_is_compatible("wand,imx6q-wandboard"))
++              imx6q_sabrelite_cko1_setup();
++
+       of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+ 
+       imx_anatop_init();
+-- 
+1.7.10.4
+

diff --git a/src/patches/kernel/wandboard/imx/0003-thermal-add-imx-thermal-driver-support.patch b/src/patches/kernel/wandboard/imx/0003-thermal-add-imx-thermal-driver-support.patch
new file mode 100644 (file)
index 0000000..a0a7cec
--- /dev/null
+++ b/src/patches/kernel/wandboard/imx/0003-thermal-add-imx-thermal-driver-support.patch
@@ -0,0 +1,489 @@
+From 744af645bfdb0bfe73fa28df06da48783f85e6a9 Mon Sep 17 00:00:00 2001
+From: Shawn Guo <shawn.guo@linaro.org>
+Date: Mon, 24 Jun 2013 14:30:44 +0800
+Subject: [PATCH 5/5] thermal: add imx thermal driver support
+
+This is based on the initial imx thermal work done by
+Rob Lee <rob.lee@linaro.org> (Not sure if the email address is still
+valid).  Since he is no longer interested in the work and I have
+rewritten a significant amount of the code, I just took the authorship
+over from him.
+
+It adds the imx thermal support using Temperature Monitor (TEMPMON)
+block found on some Freescale i.MX SoCs.  The driver uses syscon regmap
+interface to access TEMPMON control registers and calibration data, and
+supports cpufreq as the cooling device.
+
+Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
+---
+ .../devicetree/bindings/thermal/imx-thermal.txt    |   17 +
+ drivers/thermal/Kconfig                            |   11 +
+ drivers/thermal/Makefile                           |    1 +
+ drivers/thermal/imx_thermal.c                      |  397 ++++++++++++++++++++
+ 4 files changed, 426 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/thermal/imx-thermal.txt
+ create mode 100644 drivers/thermal/imx_thermal.c
+
+diff --git a/Documentation/devicetree/bindings/thermal/imx-thermal.txt b/Documentation/devicetree/bindings/thermal/imx-thermal.txt
+new file mode 100644
+index 0000000..541c25e
+--- /dev/null
++++ b/Documentation/devicetree/bindings/thermal/imx-thermal.txt
+@@ -0,0 +1,17 @@
++* Temperature Monitor (TEMPMON) on Freescale i.MX SoCs
++
++Required properties:
++- compatible : "fsl,imx6q-thermal"
++- fsl,tempmon : phandle pointer to system controller that contains TEMPMON
++  control registers, e.g. ANATOP on imx6q.
++- fsl,tempmon-data : phandle pointer to fuse controller that contains TEMPMON
++  calibration data, e.g. OCOTP on imx6q.  The details about calibration data
++  can be found in SoC Reference Manual.
++
++Example:
++
++tempmon {
++      compatible = "fsl,imx6q-tempmon";
++      fsl,tempmon = <&anatop>;
++      fsl,tempmon-data = <&ocotp>;
++};
+diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
+index 5e3c025..e91d78f 100644
+--- a/drivers/thermal/Kconfig
++++ b/drivers/thermal/Kconfig
+@@ -91,6 +91,17 @@ config THERMAL_EMULATION
+         because userland can easily disable the thermal policy by simply
+         flooding this sysfs node with low temperature values.
+ 
++config IMX_THERMAL
++      tristate "Temperature sensor driver for Freescale i.MX SoCs"
++      depends on CPU_THERMAL
++      depends on MFD_SYSCON
++      depends on OF
++      help
++        Support for Temperature Monitor (TEMPMON) found on Freescale i.MX SoCs.
++        It supports one critical trip point and one passive trip point.  The
++        cpufreq is used as the cooling device to throttle CPUs when the
++        passive trip is crossed.
++
+ config SPEAR_THERMAL
+       bool "SPEAr thermal sensor driver"
+       depends on PLAT_SPEAR
+diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
+index c054d41..6910b2d 100644
+--- a/drivers/thermal/Makefile
++++ b/drivers/thermal/Makefile
+@@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_THERMAL) += exynos_thermal.o
+ obj-$(CONFIG_DOVE_THERMAL)    += dove_thermal.o
+ obj-$(CONFIG_DB8500_THERMAL)  += db8500_thermal.o
+ obj-$(CONFIG_ARMADA_THERMAL)  += armada_thermal.o
++obj-$(CONFIG_IMX_THERMAL)     += imx_thermal.o
+ obj-$(CONFIG_DB8500_CPUFREQ_COOLING)  += db8500_cpufreq_cooling.o
+ obj-$(CONFIG_INTEL_POWERCLAMP)        += intel_powerclamp.o
+ 
+diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
+new file mode 100644
+index 0000000..d16c33c
+--- /dev/null
++++ b/drivers/thermal/imx_thermal.c
+@@ -0,0 +1,397 @@
++/*
++ * Copyright 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/cpu_cooling.h>
++#include <linux/cpufreq.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/mfd/syscon.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++#include <linux/slab.h>
++#include <linux/thermal.h>
++#include <linux/types.h>
++
++#define REG_SET               0x4
++#define REG_CLR               0x8
++#define REG_TOG               0xc
++
++#define MISC0                         0x0150
++#define MISC0_REFTOP_SELBIASOFF               (1 << 3)
++
++#define TEMPSENSE0                    0x0180
++#define TEMPSENSE0_TEMP_CNT_SHIFT     8
++#define TEMPSENSE0_TEMP_CNT_MASK      (0xfff << TEMPSENSE0_TEMP_CNT_SHIFT)
++#define TEMPSENSE0_FINISHED           (1 << 2)
++#define TEMPSENSE0_MEASURE_TEMP               (1 << 1)
++#define TEMPSENSE0_POWER_DOWN         (1 << 0)
++
++#define TEMPSENSE1                    0x0190
++#define TEMPSENSE1_MEASURE_FREQ               0xffff
++
++#define OCOTP_ANA1                    0x04e0
++
++/* The driver supports 1 passive trip point and 1 critical trip point */
++enum imx_thermal_trip {
++      IMX_TRIP_PASSIVE,
++      IMX_TRIP_CRITICAL,
++      IMX_TRIP_NUM,
++};
++
++/*
++ * It defines the temperature in millicelsius for passive trip point
++ * that will trigger cooling action when crossed.
++ */
++#define IMX_TEMP_PASSIVE              85000
++
++/*
++ * The maximum die temperature on imx parts is 105C, let's give some cushion
++ * for noise and possible temperature rise between measurements.
++ */
++#define IMX_TEMP_CRITICAL             100000
++
++#define IMX_POLLING_DELAY             2000 /* millisecond */
++#define IMX_PASSIVE_DELAY             1000
++
++struct imx_thermal_data {
++      struct thermal_zone_device *tz;
++      struct thermal_cooling_device *cdev;
++      enum thermal_device_mode mode;
++      struct regmap *tempmon;
++      int c1, c2; /* See formula in imx_get_sensor_data() */
++};
++
++static int imx_get_temp(struct thermal_zone_device *tz, unsigned long *temp)
++{
++      struct imx_thermal_data *data = tz->devdata;
++      struct regmap *map = data->tempmon;
++      static unsigned long last_temp;
++      unsigned int n_meas;
++      u32 val;
++
++      /*
++       * Every time we measure the temperature, we will power on the
++       * temperature sensor, enable measurements, take a reading,
++       * disable measurements, power off the temperature sensor.
++       */
++      regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_POWER_DOWN);
++      regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_MEASURE_TEMP);
++
++      /*
++       * According to the temp sensor designers, it may require up to ~17us
++       * to complete a measurement.
++       */
++      usleep_range(20, 50);
++
++      regmap_read(map, TEMPSENSE0, &val);
++      regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_MEASURE_TEMP);
++      regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_POWER_DOWN);
++
++      if ((val & TEMPSENSE0_FINISHED) == 0) {
++              dev_dbg(&tz->device, "temp measurement never finished\n");
++              return -EAGAIN;
++      }
++
++      n_meas = (val & TEMPSENSE0_TEMP_CNT_MASK) >> TEMPSENSE0_TEMP_CNT_SHIFT;
++
++      /* See imx_get_sensor_data() for formula derivation */
++      *temp = data->c2 + data->c1 * n_meas;
++
++      if (*temp != last_temp) {
++              dev_dbg(&tz->device, "millicelsius: %ld\n", *temp);
++              last_temp = *temp;
++      }
++
++      return 0;
++}
++
++static int imx_get_mode(struct thermal_zone_device *tz,
++                      enum thermal_device_mode *mode)
++{
++      struct imx_thermal_data *data = tz->devdata;
++
++      *mode = data->mode;
++
++      return 0;
++}
++
++static int imx_set_mode(struct thermal_zone_device *tz,
++                      enum thermal_device_mode mode)
++{
++      struct imx_thermal_data *data = tz->devdata;
++
++      if (mode == THERMAL_DEVICE_ENABLED) {
++              tz->polling_delay = IMX_POLLING_DELAY;
++              tz->passive_delay = IMX_PASSIVE_DELAY;
++      } else {
++              tz->polling_delay = 0;
++              tz->passive_delay = 0;
++      }
++
++      data->mode = mode;
++      thermal_zone_device_update(tz);
++
++      return 0;
++}
++
++static int imx_get_trip_type(struct thermal_zone_device *tz, int trip,
++                           enum thermal_trip_type *type)
++{
++      *type = (trip == IMX_TRIP_PASSIVE) ? THERMAL_TRIP_PASSIVE :
++                                           THERMAL_TRIP_CRITICAL;
++      return 0;
++}
++
++static int imx_get_crit_temp(struct thermal_zone_device *tz,
++                           unsigned long *temp)
++{
++      *temp = IMX_TEMP_CRITICAL;
++      return 0;
++}
++
++static int imx_get_trip_temp(struct thermal_zone_device *tz, int trip,
++                           unsigned long *temp)
++{
++      *temp = (trip == IMX_TRIP_PASSIVE) ? IMX_TEMP_PASSIVE :
++                                           IMX_TEMP_CRITICAL;
++      return 0;
++}
++
++static int imx_bind(struct thermal_zone_device *tz,
++                  struct thermal_cooling_device *cdev)
++{
++      int ret;
++
++      ret = thermal_zone_bind_cooling_device(tz, IMX_TRIP_PASSIVE, cdev,
++                                             THERMAL_NO_LIMIT,
++                                             THERMAL_NO_LIMIT);
++      if (ret) {
++              dev_err(&tz->device,
++                      "binding zone %s with cdev %s failed:%d\n",
++                      tz->type, cdev->type, ret);
++              return ret;
++      }
++
++      return 0;
++}
++
++static int imx_unbind(struct thermal_zone_device *tz,
++                    struct thermal_cooling_device *cdev)
++{
++      int ret;
++
++      ret = thermal_zone_unbind_cooling_device(tz, IMX_TRIP_PASSIVE, cdev);
++      if (ret) {
++              dev_err(&tz->device,
++                      "unbinding zone %s with cdev %s failed:%d\n",
++                      tz->type, cdev->type, ret);
++              return ret;
++      }
++
++      return 0;
++}
++
++static const struct thermal_zone_device_ops imx_tz_ops = {
++      .bind = imx_bind,
++      .unbind = imx_unbind,
++      .get_temp = imx_get_temp,
++      .get_mode = imx_get_mode,
++      .set_mode = imx_set_mode,
++      .get_trip_type = imx_get_trip_type,
++      .get_trip_temp = imx_get_trip_temp,
++      .get_crit_temp = imx_get_crit_temp,
++};
++
++static int imx_get_sensor_data(struct platform_device *pdev)
++{
++      struct imx_thermal_data *data = platform_get_drvdata(pdev);
++      struct regmap *map;
++      int t1, t2, n1, n2;
++      int ret;
++      u32 val;
++
++      map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
++                                            "fsl,tempmon-data");
++      if (IS_ERR(map)) {
++              ret = PTR_ERR(map);
++              dev_err(&pdev->dev, "failed to get sensor regmap: %d\n", ret);
++              return ret;
++      }
++
++      ret = regmap_read(map, OCOTP_ANA1, &val);
++      if (ret) {
++              dev_err(&pdev->dev, "failed to read sensor data: %d\n", ret);
++              return ret;
++      }
++
++      if (val == 0 || val == ~0) {
++              dev_err(&pdev->dev, "invalid sensor calibration data\n");
++              return -EINVAL;
++      }
++
++      /*
++       * Sensor data layout:
++       *   [31:20] - sensor value @ 25C
++       *    [19:8] - sensor value of hot
++       *     [7:0] - hot temperature value
++       */
++      n1 = val >> 20;
++      n2 = (val & 0xfff00) >> 8;
++      t2 = val & 0xff;
++      t1 = 25; /* t1 always 25C */
++
++      /*
++       * Derived from linear interpolation,
++       * Tmeas = T2 + (Nmeas - N2) * (T1 - T2) / (N1 - N2)
++       * We want to reduce this down to the minimum computation necessary
++       * for each temperature read.  Also, we want Tmeas in millicelsius
++       * and we don't want to lose precision from integer division. So...
++       * milli_Tmeas = 1000 * T2 + 1000 * (Nmeas - N2) * (T1 - T2) / (N1 - N2)
++       * Let constant c1 = 1000 * (T1 - T2) / (N1 - N2)
++       * milli_Tmeas = (1000 * T2) + c1 * (Nmeas - N2)
++       * milli_Tmeas = (1000 * T2) + (c1 * Nmeas) - (c1 * N2)
++       * Let constant c2 = (1000 * T2) - (c1 * N2)
++       * milli_Tmeas = c2 + (c1 * Nmeas)
++       */
++      data->c1 = 1000 * (t1 - t2) / (n1 - n2);
++      data->c2 = 1000 * t2 - data->c1 * n2;
++
++      return 0;
++}
++
++static int imx_thermal_probe(struct platform_device *pdev)
++{
++      struct imx_thermal_data *data;
++      struct cpumask clip_cpus;
++      struct regmap *map;
++      int ret;
++
++      data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
++      if (!data)
++              return -ENOMEM;
++
++      map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "fsl,tempmon");
++      if (IS_ERR(map)) {
++              ret = PTR_ERR(map);
++              dev_err(&pdev->dev, "failed to get tempmon regmap: %d\n", ret);
++              return ret;
++      }
++      data->tempmon = map;
++
++      platform_set_drvdata(pdev, data);
++
++      ret = imx_get_sensor_data(pdev);
++      if (ret) {
++              dev_err(&pdev->dev, "failed to get sensor data\n");
++              return ret;
++      }
++
++      /* Make sure sensor is in known good state for measurements */
++      regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_POWER_DOWN);
++      regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_MEASURE_TEMP);
++      regmap_write(map, TEMPSENSE1 + REG_CLR, TEMPSENSE1_MEASURE_FREQ);
++      regmap_write(map, MISC0 + REG_SET, MISC0_REFTOP_SELBIASOFF);
++      regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_POWER_DOWN);
++
++      cpumask_set_cpu(0, &clip_cpus);
++      data->cdev = cpufreq_cooling_register(&clip_cpus);
++      if (IS_ERR(data->cdev)) {
++              ret = PTR_ERR(data->cdev);
++              dev_err(&pdev->dev,
++                      "failed to register cpufreq cooling device: %d\n", ret);
++              return ret;
++      }
++
++      data->tz = thermal_zone_device_register("imx_thermal_zone",
++                                              IMX_TRIP_NUM, 0, data,
++                                              &imx_tz_ops, NULL,
++                                              IMX_PASSIVE_DELAY,
++                                              IMX_POLLING_DELAY);
++      if (IS_ERR(data->tz)) {
++              ret = PTR_ERR(data->tz);
++              dev_err(&pdev->dev,
++                      "failed to register thermal zone device %d\n", ret);
++              cpufreq_cooling_unregister(data->cdev);
++              return ret;
++      }
++
++      data->mode = THERMAL_DEVICE_ENABLED;
++
++      return 0;
++}
++
++static int imx_thermal_remove(struct platform_device *pdev)
++{
++      struct imx_thermal_data *data = platform_get_drvdata(pdev);
++
++      thermal_zone_device_unregister(data->tz);
++      cpufreq_cooling_unregister(data->cdev);
++
++      return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int imx_thermal_suspend(struct device *dev)
++{
++      struct imx_thermal_data *data = dev_get_drvdata(dev);
++      struct regmap *map = data->tempmon;
++      u32 val;
++
++      regmap_read(map, TEMPSENSE0, &val);
++      if ((val & TEMPSENSE0_POWER_DOWN) == 0) {
++              /*
++               * If a measurement is taking place, wait for a long enough
++               * time for it to finish, and then check again.  If it still
++               * does not finish, something must go wrong.
++               */
++              udelay(50);
++              regmap_read(map, TEMPSENSE0, &val);
++              if ((val & TEMPSENSE0_POWER_DOWN) == 0)
++                      return -ETIMEDOUT;
++      }
++
++      return 0;
++}
++
++static int imx_thermal_resume(struct device *dev)
++{
++      /* Nothing to do for now */
++      return 0;
++}
++#endif
++
++static SIMPLE_DEV_PM_OPS(imx_thermal_pm_ops,
++                       imx_thermal_suspend, imx_thermal_resume);
++
++static const struct of_device_id of_imx_thermal_match[] = {
++      { .compatible = "fsl,imx6q-tempmon", },
++      { /* end */ }
++};
++
++static struct platform_driver imx_thermal = {
++      .driver = {
++              .name   = "imx_thermal",
++              .owner  = THIS_MODULE,
++              .pm     = &imx_thermal_pm_ops,
++              .of_match_table = of_imx_thermal_match,
++      },
++      .probe          = imx_thermal_probe,
++      .remove         = imx_thermal_remove,
++};
++module_platform_driver(imx_thermal);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("Thermal driver for Freescale i.MX SoCs");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("platform:imx-thermal");
+-- 
+1.7.10.4
+

diff --git a/src/patches/kernel/wandboard/imx/0004-ARM-i.MX6-Wandboard-add-wifi-bt-rfkill-driver.patch b/src/patches/kernel/wandboard/imx/0004-ARM-i.MX6-Wandboard-add-wifi-bt-rfkill-driver.patch
new file mode 100644 (file)
index 0000000..993b1d7
--- /dev/null
+++ b/src/patches/kernel/wandboard/imx/0004-ARM-i.MX6-Wandboard-add-wifi-bt-rfkill-driver.patch
@@ -0,0 +1,341 @@
+From adf0f7b7d7c0083dd936fe46423b89e974f8df12 Mon Sep 17 00:00:00 2001
+From: Vladimir Ermakov <vooon341@gmail.com>
+Date: Wed, 10 Jul 2013 03:06:54 +0400
+Subject: [PATCH] ARM i.MX6 Wandboard add wifi+bt rfkill driver
+
+BRCM WiFi module requires initialization for control gpio;
+Additional provides rfkill funcs.
+
+v2: fix wrong probe func in driver struct
+v3: add imx6qdl compatible
+
+Signed-off-by: Vladimir Ermakov <vooon341@gmail.com>
+---
+ arch/arm/mach-imx/devices/Kconfig       |   6 +
+ arch/arm/mach-imx/devices/Makefile      |   1 +
+ arch/arm/mach-imx/devices/wand-rfkill.c | 290 ++++++++++++++++++++++++++++++++
+ 3 files changed, 297 insertions(+)
+ create mode 100644 arch/arm/mach-imx/devices/wand-rfkill.c
+
+diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig
+index 68c74fb..a0adf75 100644
+--- a/arch/arm/mach-imx/devices/Kconfig
++++ b/arch/arm/mach-imx/devices/Kconfig
+@@ -85,3 +85,9 @@ config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+ 
+ config IMX_HAVE_PLATFORM_SPI_IMX
+       bool
++
++config WAND_RFKILL
++      tristate "Wandboard RF Kill support"
++      depends on SOC_IMX6Q
++      default m
++      select RFKILL
+diff --git a/arch/arm/mach-imx/devices/Makefile b/arch/arm/mach-imx/devices/Makefile
+index 67416fb..b2aded5 100644
+--- a/arch/arm/mach-imx/devices/Makefile
++++ b/arch/arm/mach-imx/devices/Makefile
+@@ -30,3 +30,4 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
+ obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o
+ obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) +=  platform-spi_imx.o
+ obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_EMMA) += platform-mx2-emma.o
++obj-$(CONFIG_WAND_RFKILL) += wand-rfkill.o
+diff --git a/arch/arm/mach-imx/devices/wand-rfkill.c b/arch/arm/mach-imx/devices/wand-rfkill.c
+new file mode 100644
+index 0000000..da7ef9f
+--- /dev/null
++++ b/arch/arm/mach-imx/devices/wand-rfkill.c
+@@ -0,0 +1,290 @@
++/*
++ * arch/arm/mach-imx/devices/wand-rfkill.c
++ *
++ * Copyright (C) 2013 Vladimir Ermakov <vooon341@gmail.com>
++ *
++ * based on net/rfkill/rfkill-gpio.c
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++
++#include <linux/of.h>
++#include <linux/of_gpio.h>
++#include <linux/of_device.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/platform_device.h>
++#include <linux/rfkill.h>
++#include <linux/delay.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++
++
++struct wand_rfkill_data {
++      struct rfkill *rfkill_dev;
++      int shutdown_gpio;
++      const char *shutdown_name;
++};
++
++static int wand_rfkill_set_block(void *data, bool blocked)
++{
++      struct wand_rfkill_data *rfkill = data;
++
++      pr_debug("wandboard-rfkill: set block %d\n", blocked);
++
++      if (blocked) {
++              if (gpio_is_valid(rfkill->shutdown_gpio))
++                      gpio_direction_output(rfkill->shutdown_gpio, 0);
++      } else {
++              if (gpio_is_valid(rfkill->shutdown_gpio))
++                      gpio_direction_output(rfkill->shutdown_gpio, 1);
++      }
++
++      return 0;
++}
++
++static const struct rfkill_ops wand_rfkill_ops = {
++      .set_block = wand_rfkill_set_block,
++};
++
++static int wand_rfkill_wifi_probe(struct device *dev,
++              struct device_node *np,
++              struct wand_rfkill_data *rfkill)
++{
++      int ret;
++      int wl_ref_on, wl_rst_n, wl_reg_on, wl_wake, wl_host_wake;
++
++      wl_ref_on = of_get_named_gpio(np, "wifi-ref-on", 0);
++      wl_rst_n = of_get_named_gpio(np, "wifi-rst-n", 0);
++      wl_reg_on = of_get_named_gpio(np, "wifi-reg-on", 0);
++      wl_wake = of_get_named_gpio(np, "wifi-wake", 0);
++      wl_host_wake = of_get_named_gpio(np, "wifi-host-wake", 0);
++
++      if (!gpio_is_valid(wl_rst_n) || !gpio_is_valid(wl_ref_on) ||
++                      !gpio_is_valid(wl_reg_on) || !gpio_is_valid(wl_wake) ||
++                      !gpio_is_valid(wl_host_wake)) {
++
++              dev_err(dev, "incorrect wifi gpios (%d %d %d %d %d)\n",
++                              wl_rst_n, wl_ref_on, wl_reg_on, wl_wake, wl_host_wake);
++              return -EINVAL;
++      }
++
++      dev_info(dev, "initialize wifi chip\n");
++
++      gpio_request(wl_rst_n, "wl_rst_n");
++      gpio_direction_output(wl_rst_n, 0);
++      msleep(11);
++      gpio_set_value(wl_rst_n, 1);
++
++      gpio_request(wl_ref_on, "wl_ref_on");
++      gpio_direction_output(wl_ref_on, 1);
++
++      gpio_request(wl_reg_on, "wl_reg_on");
++      gpio_direction_output(wl_reg_on, 1);
++
++      gpio_request(wl_wake, "wl_wake");
++      gpio_direction_output(wl_wake, 1);
++
++      gpio_request(wl_host_wake, "wl_host_wake");
++      gpio_direction_input(wl_host_wake);
++
++      rfkill->shutdown_name = "wifi_shutdown";
++      rfkill->shutdown_gpio = wl_wake;
++
++      rfkill->rfkill_dev = rfkill_alloc("wifi-rfkill", dev, RFKILL_TYPE_WLAN,
++                      &wand_rfkill_ops, rfkill);
++      if (!rfkill->rfkill_dev) {
++              ret = -ENOMEM;
++              goto wifi_fail_free_gpio;
++      }
++
++      ret = rfkill_register(rfkill->rfkill_dev);
++      if (ret < 0)
++              goto wifi_fail_unregister;
++
++      dev_info(dev, "wifi-rfkill registered.\n");
++
++      return 0;
++
++wifi_fail_unregister:
++      rfkill_destroy(rfkill->rfkill_dev);
++wifi_fail_free_gpio:
++      if (gpio_is_valid(wl_rst_n))     gpio_free(wl_rst_n);
++      if (gpio_is_valid(wl_ref_on))    gpio_free(wl_ref_on);
++      if (gpio_is_valid(wl_reg_on))    gpio_free(wl_reg_on);
++      if (gpio_is_valid(wl_wake))      gpio_free(wl_wake);
++      if (gpio_is_valid(wl_host_wake)) gpio_free(wl_host_wake);
++
++      return ret;
++}
++
++static int wand_rfkill_bt_probe(struct device *dev,
++              struct device_node *np,
++              struct wand_rfkill_data *rfkill)
++{
++      int ret;
++      int bt_on, bt_wake, bt_host_wake;
++
++      bt_on = of_get_named_gpio(np, "bluetooth-on", 0);
++      bt_wake = of_get_named_gpio(np, "bluetooth-wake", 0);
++      bt_host_wake = of_get_named_gpio(np, "bluetooth-host-wake", 0);
++
++      if (!gpio_is_valid(bt_on) || !gpio_is_valid(bt_wake) ||
++                      !gpio_is_valid(bt_host_wake)) {
++
++              dev_err(dev, "incorrect bt gpios (%d %d %d)\n",
++                              bt_on, bt_wake, bt_host_wake);
++              return -EINVAL;
++      }
++
++      dev_info(dev, "initialize bluetooth chip\n");
++
++      gpio_request(bt_on, "bt_on");
++      gpio_direction_output(bt_on, 0);
++      msleep(11);
++      gpio_set_value(bt_on, 1);
++
++      gpio_request(bt_wake, "bt_wake");
++      gpio_direction_output(bt_wake, 1);
++
++      gpio_request(bt_host_wake, "bt_host_wake");
++      gpio_direction_input(bt_host_wake);
++
++      rfkill->shutdown_name = "bluetooth_shutdown";
++      rfkill->shutdown_gpio = bt_wake;
++
++      rfkill->rfkill_dev = rfkill_alloc("bluetooth-rfkill", dev, RFKILL_TYPE_BLUETOOTH,
++                      &wand_rfkill_ops, rfkill);
++      if (!rfkill->rfkill_dev) {
++              ret = -ENOMEM;
++              goto bt_fail_free_gpio;
++      }
++
++      ret = rfkill_register(rfkill->rfkill_dev);
++      if (ret < 0)
++              goto bt_fail_unregister;
++
++      dev_info(dev, "bluetooth-rfkill registered.\n");
++
++      return 0;
++
++bt_fail_unregister:
++      rfkill_destroy(rfkill->rfkill_dev);
++bt_fail_free_gpio:
++      if (gpio_is_valid(bt_on))        gpio_free(bt_on);
++      if (gpio_is_valid(bt_wake))      gpio_free(bt_wake);
++      if (gpio_is_valid(bt_host_wake)) gpio_free(bt_host_wake);
++
++      return ret;
++}
++
++static int wand_rfkill_probe(struct platform_device *pdev)
++{
++      struct wand_rfkill_data *rfkill;
++      struct pinctrl *pinctrl;
++      int ret;
++
++      dev_info(&pdev->dev, "Wandboard rfkill initialization\n");
++
++      if (!pdev->dev.of_node) {
++              dev_err(&pdev->dev, "no device tree node\n");
++              return -ENODEV;
++      }
++
++      rfkill = kzalloc(sizeof(*rfkill) * 2, GFP_KERNEL);
++      if (!rfkill)
++              return -ENOMEM;
++
++      pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
++      if (IS_ERR(pinctrl)) {
++              int ret = PTR_ERR(pinctrl);
++              dev_err(&pdev->dev, "failed to get default pinctrl: %d\n", ret);
++              return ret;
++      }
++
++      /* setup WiFi */
++      ret = wand_rfkill_wifi_probe(&pdev->dev, pdev->dev.of_node, &rfkill[0]);
++      if (ret < 0)
++              goto fail_free_rfkill;
++
++      /* setup bluetooth */
++      ret = wand_rfkill_bt_probe(&pdev->dev, pdev->dev.of_node, &rfkill[1]);
++      if (ret < 0)
++              goto fail_unregister_wifi;
++
++      platform_set_drvdata(pdev, rfkill);
++
++      return 0;
++
++fail_unregister_wifi:
++      if (rfkill[1].rfkill_dev) {
++              rfkill_unregister(rfkill[1].rfkill_dev);
++              rfkill_destroy(rfkill[1].rfkill_dev);
++      }
++
++      /* TODO free gpio */
++
++fail_free_rfkill:
++      kfree(rfkill);
++
++      return ret;
++}
++
++static int wand_rfkill_remove(struct platform_device *pdev)
++{
++      struct wand_rfkill_data *rfkill = platform_get_drvdata(pdev);
++
++      dev_info(&pdev->dev, "Module unloading\n");
++
++      if (!rfkill)
++              return 0;
++
++      /* WiFi */
++      if (gpio_is_valid(rfkill[0].shutdown_gpio))
++              gpio_free(rfkill[0].shutdown_gpio);
++
++      rfkill_unregister(rfkill[0].rfkill_dev);
++      rfkill_destroy(rfkill[0].rfkill_dev);
++
++      /* Bt */
++      if (gpio_is_valid(rfkill[1].shutdown_gpio))
++              gpio_free(rfkill[1].shutdown_gpio);
++
++      rfkill_unregister(rfkill[1].rfkill_dev);
++      rfkill_destroy(rfkill[1].rfkill_dev);
++
++      kfree(rfkill);
++
++      return 0;
++}
++
++static struct of_device_id wand_rfkill_match[] = {
++      { .compatible = "wand,imx6q-wandboard-rfkill", },
++      { .compatible = "wand,imx6dl-wandboard-rfkill", },
++      { .compatible = "wand,imx6qdl-wandboard-rfkill", },
++      {}
++};
++
++static struct platform_driver wand_rfkill_driver = {
++      .driver = {
++              .name = "wandboard-rfkill",
++              .owner = THIS_MODULE,
++              .of_match_table = of_match_ptr(wand_rfkill_match),
++      },
++      .probe = wand_rfkill_probe,
++      .remove = wand_rfkill_remove
++};
++
++module_platform_driver(wand_rfkill_driver);
++
++MODULE_AUTHOR("Vladimir Ermakov <vooon341@gmail.com>");
++MODULE_DESCRIPTION("Wandboard rfkill driver");
++MODULE_LICENSE("GPL v2");
+-- 
+1.8.4.rc3
+

diff --git a/src/patches/kernel/wandboard/imx/0005-Add-IMX6Q-AHCI-support.patch b/src/patches/kernel/wandboard/imx/0005-Add-IMX6Q-AHCI-support.patch
new file mode 100644 (file)
index 0000000..912b3be
--- /dev/null
+++ b/src/patches/kernel/wandboard/imx/0005-Add-IMX6Q-AHCI-support.patch
@@ -0,0 +1,85 @@
+From 8e890a259208dbe3aba6f46f7c3a213269d8f123 Mon Sep 17 00:00:00 2001
+From: Allen Ibara <allen@zee.aero>
+Date: Tue, 4 Dec 2012 20:44:26 -0800
+Subject: [PATCH 2/5] Add IMX6Q AHCI support
+
+Adds ahci_platform bits to make AHCI work on sabrelite IMX6Q board.
+
+Signed-off-by: Allen Ibara <allen@zee.aero>
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+---
+ 
+diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
+index 7a8a284..d324cdf 100644
+--- a/drivers/ata/ahci_platform.c
++++ b/drivers/ata/ahci_platform.c
+@@ -23,6 +23,9 @@
+ #include <linux/platform_device.h>
+ #include <linux/libata.h>
+ #include <linux/ahci_platform.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_gpio.h>
+ #include "ahci.h"
+ 
+ static void ahci_host_stop(struct ata_host *host);
+@@ -30,6 +33,7 @@ static void ahci_host_stop(struct ata_host *host);
+ enum ahci_type {
+       AHCI,           /* standard platform ahci */
+       IMX53_AHCI,     /* ahci on i.mx53 */
++      IMX6Q_AHCI,     /* ahci on i.mx6q */
+       STRICT_AHCI,    /* delayed DMA engine start */
+ };
+ 
+@@ -41,6 +45,9 @@ static struct platform_device_id ahci_devtype[] = {
+               .name = "imx53-ahci",
+               .driver_data = IMX53_AHCI,
+       }, {
++              .name = "imx6q-ahci",
++              .driver_data = IMX53_AHCI,
++      }, {
+               .name = "strict-ahci",
+               .driver_data = STRICT_AHCI,
+       }, {
+@@ -86,12 +93,24 @@ static struct scsi_host_template ahci_platform_sht = {
+       AHCI_SHT("ahci_platform"),
+ };
+ 
++static const struct of_device_id ahci_of_match[] = {
++      { .compatible = "calxeda,hb-ahci",  .data = &ahci_devtype[AHCI],},
++      { .compatible = "fsl,imx6q-ahci",   .data = &ahci_devtype[IMX6Q_AHCI],},
++      { .compatible = "snps,spear-ahci", },
++      {},
++};
++MODULE_DEVICE_TABLE(of, ahci_of_match);
++
+ static int ahci_probe(struct platform_device *pdev)
+ {
+       struct device *dev = &pdev->dev;
+       struct ahci_platform_data *pdata = dev_get_platdata(dev);
++      const struct of_device_id *of_id =
++                      of_match_device(ahci_of_match, &pdev->dev);
++      const struct platform_device_id *id_entry = of_id->data;
+       const struct platform_device_id *id = platform_get_device_id(pdev);
+-      struct ata_port_info pi = ahci_port_info[id ? id->driver_data : 0];
++      struct ata_port_info pi = ahci_port_info[id ? id->driver_data : \
++              id_entry->driver_data];
+       const struct ata_port_info *ppi[] = { &pi, NULL };
+       struct ahci_host_priv *hpriv;
+       struct ata_host *host;
+@@ -325,12 +344,6 @@ disable_unprepare_clk:
+ 
+ static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_suspend, ahci_resume);
+ 
+-static const struct of_device_id ahci_of_match[] = {
+-      { .compatible = "snps,spear-ahci", },
+-      {},
+-};
+-MODULE_DEVICE_TABLE(of, ahci_of_match);
+-
+ static struct platform_driver ahci_driver = {
+       .probe = ahci_probe,
+       .remove = ata_platform_remove_one,
+-- 
+1.7.10.4
+

diff --git a/src/patches/kernel/wandboard/imx/0006-imx-Add-IMX53-AHCI-support.patch b/src/patches/kernel/wandboard/imx/0006-imx-Add-IMX53-AHCI-support.patch
new file mode 100644 (file)
index 0000000..1b96d8c
--- /dev/null
+++ b/src/patches/kernel/wandboard/imx/0006-imx-Add-IMX53-AHCI-support.patch
@@ -0,0 +1,25 @@
+From 41cc1967181a833c3c5af30682ea85dd01c28ff4 Mon Sep 17 00:00:00 2001
+From: Robert Nelson <robertcnelson@gmail.com>
+Date: Tue, 22 Jan 2013 22:21:03 -0600
+Subject: [PATCH 3/5] imx: Add IMX53 AHCI support
+
+Adds ahci_platform bits to make AHCI work on mx53 qsb board.
+
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+---
+
+diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
+index d324cdf..b01eeca 100644
+--- a/drivers/ata/ahci_platform.c
++++ b/drivers/ata/ahci_platform.c
+@@ -95,6 +95,7 @@ static struct scsi_host_template ahci_platform_sht = {
+ 
+ static const struct of_device_id ahci_of_match[] = {
+       { .compatible = "calxeda,hb-ahci",  .data = &ahci_devtype[AHCI],},
++      { .compatible = "fsl,imx53-ahci",   .data = &ahci_devtype[IMX53_AHCI],},
+       { .compatible = "fsl,imx6q-ahci",   .data = &ahci_devtype[IMX6Q_AHCI],},
+       { .compatible = "snps,spear-ahci", },
+       {},
+-- 
+1.7.10.4
+

diff --git a/src/patches/kernel/wandboard/imx/0007-imx6-enable-sata-clk-if-SATA_AHCI_PLATFORM.patch b/src/patches/kernel/wandboard/imx/0007-imx6-enable-sata-clk-if-SATA_AHCI_PLATFORM.patch
new file mode 100644 (file)
index 0000000..d85e3ff
--- /dev/null
+++ b/src/patches/kernel/wandboard/imx/0007-imx6-enable-sata-clk-if-SATA_AHCI_PLATFORM.patch
@@ -0,0 +1,33 @@
+From 765561c8c72a46c2177b20d730e061ab2ff8f970 Mon Sep 17 00:00:00 2001
+From: Paolo Pisati <paolo.pisati@canonical.com>
+Date: Thu, 31 Jan 2013 18:33:46 +0100
+Subject: [PATCH 4/5] SAUCE: imx6: enable sata clk if SATA_AHCI_PLATFORM
+
+Clock modifications in 24d340ac "ARM i.MX6: Fix ethernet PLL clocks" broke the
+SATA clk, fix it.
+
+More info: http://www.spinics.net/lists/arm-kernel/msg221503.html
+
+Original-code-from: Shawn Guo <shawn.guo@linaro.org>
+Signed-off-by: Paolo Pisati <paolo.pisati@canonical.com>
+---
+ arch/arm/mach-imx/clk-imx6q.c |    3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
+index 4e3148c..38d707a 100644
+--- a/arch/arm/mach-imx/clk-imx6q.c
++++ b/arch/arm/mach-imx/clk-imx6q.c
+@@ -568,6 +568,9 @@ int __init mx6q_clocks_init(void)
+               clk_prepare_enable(clk[usbphy2_gate]);
+       }
+ 
++      if (IS_ENABLED(CONFIG_SATA_AHCI_PLATFORM))
++              clk_prepare_enable(clk[sata_ref_100m]);
++
+       /* Set initial power mode */
+       imx6q_set_lpm(WAIT_CLOCKED);
+ 
+-- 
+1.7.10.4
+

diff --git a/src/patches/kernel/wandboard/imx/0008-ARM-imx6q-update-the-sata-bits-definitions-of-gpr13.patch b/src/patches/kernel/wandboard/imx/0008-ARM-imx6q-update-the-sata-bits-definitions-of-gpr13.patch
new file mode 100644 (file)
index 0000000..6f6ea69
--- /dev/null
+++ b/src/patches/kernel/wandboard/imx/0008-ARM-imx6q-update-the-sata-bits-definitions-of-gpr13.patch
@@ -0,0 +1,150 @@
+From 371863a788db77e6092d69df17d8884cb0d94270 Mon Sep 17 00:00:00 2001
+From: Richard Zhu <r65037@freescale.com>
+Date: Wed, 24 Jul 2013 06:15:28 +0000
+Subject: [PATCH 1/2] ARM: imx6q: update the sata bits definitions of gpr13
+
+Replace the SATA_PHY_# by the more readable definitons.
+
+tj: Being routed through libata branch to enable implementation of
+    ahci_imx.
+
+Signed-off-by: Richard Zhu <r65037@freescale.com>
+Acked-by: Shawn Guo <shawn.guo@linaro.org>
+Signed-off-by: Tejun Heo <tj@kernel.org>
+---
+ include/linux/mfd/syscon/imx6q-iomuxc-gpr.h |  121 +++++++++++++++++++--------
+ 1 file changed, 84 insertions(+), 37 deletions(-)
+
+diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+index b1521e8..b6bdcd6 100644
+--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
++++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+@@ -279,41 +279,88 @@
+ #define IMX6Q_GPR13_CAN2_STOP_REQ             BIT(29)
+ #define IMX6Q_GPR13_CAN1_STOP_REQ             BIT(28)
+ #define IMX6Q_GPR13_ENET_STOP_REQ             BIT(27)
+-#define IMX6Q_GPR13_SATA_PHY_8_MASK           (0x7 << 24)
+-#define IMX6Q_GPR13_SATA_PHY_8_0_5_DB         (0x0 << 24)
+-#define IMX6Q_GPR13_SATA_PHY_8_1_0_DB         (0x1 << 24)
+-#define IMX6Q_GPR13_SATA_PHY_8_1_5_DB         (0x2 << 24)
+-#define IMX6Q_GPR13_SATA_PHY_8_2_0_DB         (0x3 << 24)
+-#define IMX6Q_GPR13_SATA_PHY_8_2_5_DB         (0x4 << 24)
+-#define IMX6Q_GPR13_SATA_PHY_8_3_0_DB         (0x5 << 24)
+-#define IMX6Q_GPR13_SATA_PHY_8_3_5_DB         (0x6 << 24)
+-#define IMX6Q_GPR13_SATA_PHY_8_4_0_DB         (0x7 << 24)
+-#define IMX6Q_GPR13_SATA_PHY_7_MASK           (0x1f << 19)
+-#define IMX6Q_GPR13_SATA_PHY_7_SATA1I         (0x10 << 19)
+-#define IMX6Q_GPR13_SATA_PHY_7_SATA1M         (0x10 << 19)
+-#define IMX6Q_GPR13_SATA_PHY_7_SATA1X         (0x1a << 19)
+-#define IMX6Q_GPR13_SATA_PHY_7_SATA2I         (0x12 << 19)
+-#define IMX6Q_GPR13_SATA_PHY_7_SATA2M         (0x12 << 19)
+-#define IMX6Q_GPR13_SATA_PHY_7_SATA2X         (0x1a << 19)
+-#define IMX6Q_GPR13_SATA_PHY_6_MASK           (0x7 << 16)
+-#define IMX6Q_GPR13_SATA_SPEED_MASK           BIT(15)
+-#define IMX6Q_GPR13_SATA_SPEED_1P5G           0x0
+-#define IMX6Q_GPR13_SATA_SPEED_3P0G           BIT(15)
+-#define IMX6Q_GPR13_SATA_PHY_5                        BIT(14)
+-#define IMX6Q_GPR13_SATA_PHY_4_MASK           (0x7 << 11)
+-#define IMX6Q_GPR13_SATA_PHY_4_16_16          (0x0 << 11)
+-#define IMX6Q_GPR13_SATA_PHY_4_14_16          (0x1 << 11)
+-#define IMX6Q_GPR13_SATA_PHY_4_12_16          (0x2 << 11)
+-#define IMX6Q_GPR13_SATA_PHY_4_10_16          (0x3 << 11)
+-#define IMX6Q_GPR13_SATA_PHY_4_9_16           (0x4 << 11)
+-#define IMX6Q_GPR13_SATA_PHY_4_8_16           (0x5 << 11)
+-#define IMX6Q_GPR13_SATA_PHY_3_MASK           (0xf << 7)
+-#define IMX6Q_GPR13_SATA_PHY_3_OFF            0x7
+-#define IMX6Q_GPR13_SATA_PHY_2_MASK           (0x1f << 2)
+-#define IMX6Q_GPR13_SATA_PHY_2_OFF            0x2
+-#define IMX6Q_GPR13_SATA_PHY_1_MASK           (0x3 << 0)
+-#define IMX6Q_GPR13_SATA_PHY_1_FAST           (0x0 << 0)
+-#define IMX6Q_GPR13_SATA_PHY_1_MED            (0x1 << 0)
+-#define IMX6Q_GPR13_SATA_PHY_1_SLOW           (0x2 << 0)
+-
++#define IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK               (0x7 << 24)
++#define IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB     (0x0 << 24)
++#define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB     (0x1 << 24)
++#define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB     (0x2 << 24)
++#define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB     (0x3 << 24)
++#define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB     (0x4 << 24)
++#define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB     (0x5 << 24)
++#define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB     (0x6 << 24)
++#define IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB     (0x7 << 24)
++#define IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK      (0x1f << 19)
++#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1I    (0x10 << 19)
++#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1M    (0x10 << 19)
++#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1X    (0x1a << 19)
++#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2I    (0x12 << 19)
++#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M    (0x12 << 19)
++#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2X    (0x1a << 19)
++#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK    (0x7 << 16)
++#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_1F   (0x0 << 16)
++#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_2F   (0x1 << 16)
++#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_4F   (0x2 << 16)
++#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F   (0x3 << 16)
++#define IMX6Q_GPR13_SATA_SPD_MODE_MASK                BIT(15)
++#define IMX6Q_GPR13_SATA_SPD_MODE_1P5G                0x0
++#define IMX6Q_GPR13_SATA_SPD_MODE_3P0G                BIT(15)
++#define IMX6Q_GPR13_SATA_MPLL_SS_EN           BIT(14)
++#define IMX6Q_GPR13_SATA_TX_ATTEN_MASK                (0x7 << 11)
++#define IMX6Q_GPR13_SATA_TX_ATTEN_16_16               (0x0 << 11)
++#define IMX6Q_GPR13_SATA_TX_ATTEN_14_16               (0x1 << 11)
++#define IMX6Q_GPR13_SATA_TX_ATTEN_12_16               (0x2 << 11)
++#define IMX6Q_GPR13_SATA_TX_ATTEN_10_16               (0x3 << 11)
++#define IMX6Q_GPR13_SATA_TX_ATTEN_9_16                (0x4 << 11)
++#define IMX6Q_GPR13_SATA_TX_ATTEN_8_16                (0x5 << 11)
++#define IMX6Q_GPR13_SATA_TX_BOOST_MASK                (0xf << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB     (0x0 << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB     (0x1 << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB     (0x2 << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB     (0x3 << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB     (0x4 << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB     (0x5 << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB     (0x6 << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB     (0x7 << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB     (0x8 << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB     (0x9 << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB     (0xa << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB     (0xb << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB     (0xc << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB     (0xd << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB     (0xe << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB     (0xf << 7)
++#define IMX6Q_GPR13_SATA_TX_LVL_MASK          (0x1f << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_0_937_V               (0x00 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_0_947_V               (0x01 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_0_957_V               (0x02 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_0_966_V               (0x03 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_0_976_V               (0x04 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_0_986_V               (0x05 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_0_996_V               (0x06 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_005_V               (0x07 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_015_V               (0x08 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_025_V               (0x09 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_035_V               (0x0a << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_045_V               (0x0b << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_054_V               (0x0c << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_064_V               (0x0d << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_074_V               (0x0e << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_084_V               (0x0f << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_094_V               (0x10 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_104_V               (0x11 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_113_V               (0x12 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_123_V               (0x13 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_133_V               (0x14 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_143_V               (0x15 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_152_V               (0x16 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_162_V               (0x17 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_172_V               (0x18 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_182_V               (0x19 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_191_V               (0x1a << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_201_V               (0x1b << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_211_V               (0x1c << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_221_V               (0x1d << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_230_V               (0x1e << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_240_V               (0x1f << 2)
++#define IMX6Q_GPR13_SATA_MPLL_CLK_EN          BIT(1)
++#define IMX6Q_GPR13_SATA_TX_EDGE_RATE         BIT(0)
+ #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
+-- 
+1.7.10.4
+

diff --git a/src/patches/kernel/wandboard/imx/0009-ahci_imx-add-ahci-sata-support-on-imx-platforms.patch b/src/patches/kernel/wandboard/imx/0009-ahci_imx-add-ahci-sata-support-on-imx-platforms.patch
new file mode 100644 (file)
index 0000000..758476a
--- /dev/null
+++ b/src/patches/kernel/wandboard/imx/0009-ahci_imx-add-ahci-sata-support-on-imx-platforms.patch
@@ -0,0 +1,316 @@
+From 093f4fdd74f29031d79be747c65b95fb16601a92 Mon Sep 17 00:00:00 2001
+From: Richard Zhu <r65037@freescale.com>
+Date: Wed, 24 Jul 2013 06:15:29 +0000
+Subject: [PATCH 2/2] ahci_imx: add ahci sata support on imx platforms
+
+imx6q contains one Synopsys AHCI SATA controller, But it can't share
+ahci_platform driver with other controllers because there are some
+misalignments of the generic AHCI controller - the bits definitions of
+the HBA registers, the Vendor Specific registers, the AHCI PHY clock
+and the AHCI signals adjustment window(GPR13 register).
+
+ - CAP_SSS(bit20) of the HOST_CAP is writable, default value is '0',
+   should be configured to be '1'
+
+ - bit0 (only one AHCI SATA port on imx6q) of the HOST_PORTS_IMPL
+   should be set to be '1'.(default 0)
+
+ - One Vendor Specific register HOST_TIMER1MS(offset:0xe0) should be
+   configured regarding to the frequency of AHB bus clock.
+
+ - Configurations of the AHCI PHY clock, and the signal parameters of
+   the GPR13
+
+Setup its own ahci sata driver, contained the imx6q specific
+initialized codes, re-use the generic ahci_platform driver, and keep
+the generic ahci_platform driver clean as much as possible.
+
+tj: patch description reformatted
+
+Signed-off-by: Richard Zhu <r65037@freescale.com>
+Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
+Signed-off-by: Tejun Heo <tj@kernel.org>
+---
+ drivers/ata/Kconfig    |    9 ++
+ drivers/ata/Makefile   |    1 +
+ drivers/ata/ahci_imx.c |  236 ++++++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 246 insertions(+)
+ create mode 100644 drivers/ata/ahci_imx.c
+
+diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
+index 80dc988..cbf7a16 100644
+--- a/drivers/ata/Kconfig
++++ b/drivers/ata/Kconfig
+@@ -97,6 +97,15 @@ config SATA_AHCI_PLATFORM
+ 
+         If unsure, say N.
+ 
++config AHCI_IMX
++      tristate "Freescale i.MX AHCI SATA support"
++      depends on SATA_AHCI_PLATFORM
++      help
++        This option enables support for the Freescale i.MX SoC's
++        onboard AHCI SATA.
++
++        If unsure, say N.
++
+ config SATA_FSL
+       tristate "Freescale 3.0Gbps SATA support"
+       depends on FSL_SOC
+diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
+index c04d0fd..46518c6 100644
+--- a/drivers/ata/Makefile
++++ b/drivers/ata/Makefile
+@@ -10,6 +10,7 @@ obj-$(CONFIG_SATA_INIC162X)  += sata_inic162x.o
+ obj-$(CONFIG_SATA_SIL24)      += sata_sil24.o
+ obj-$(CONFIG_SATA_DWC)                += sata_dwc_460ex.o
+ obj-$(CONFIG_SATA_HIGHBANK)   += sata_highbank.o libahci.o
++obj-$(CONFIG_AHCI_IMX)                += ahci_imx.o
+ 
+ # SFF w/ custom DMA
+ obj-$(CONFIG_PDC_ADMA)                += pdc_adma.o
+diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c
+new file mode 100644
+index 0000000..58debb0
+--- /dev/null
++++ b/drivers/ata/ahci_imx.c
+@@ -0,0 +1,236 @@
++/*
++ * Freescale IMX AHCI SATA platform driver
++ * Copyright 2013 Freescale Semiconductor, Inc.
++ *
++ * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++#include <linux/ahci_platform.h>
++#include <linux/of_device.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
++#include "ahci.h"
++
++enum {
++      HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
++};
++
++struct imx_ahci_priv {
++      struct platform_device *ahci_pdev;
++      struct clk *sata_ref_clk;
++      struct clk *ahb_clk;
++      struct regmap *gpr;
++};
++
++static int imx6q_sata_init(struct device *dev, void __iomem *mmio)
++{
++      int ret = 0;
++      unsigned int reg_val;
++      struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
++
++      imxpriv->gpr =
++              syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
++      if (IS_ERR(imxpriv->gpr)) {
++              dev_err(dev, "failed to find fsl,imx6q-iomux-gpr regmap\n");
++              return PTR_ERR(imxpriv->gpr);
++      }
++
++      ret = clk_prepare_enable(imxpriv->sata_ref_clk);
++      if (ret < 0) {
++              dev_err(dev, "prepare-enable sata_ref clock err:%d\n", ret);
++              return ret;
++      }
++
++      /*
++       * set PHY Paremeters, two steps to configure the GPR13,
++       * one write for rest of parameters, mask of first write
++       * is 0x07fffffd, and the other one write for setting
++       * the mpll_clk_en.
++       */
++      regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK
++                      | IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK
++                      | IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK
++                      | IMX6Q_GPR13_SATA_SPD_MODE_MASK
++                      | IMX6Q_GPR13_SATA_MPLL_SS_EN
++                      | IMX6Q_GPR13_SATA_TX_ATTEN_MASK
++                      | IMX6Q_GPR13_SATA_TX_BOOST_MASK
++                      | IMX6Q_GPR13_SATA_TX_LVL_MASK
++                      | IMX6Q_GPR13_SATA_TX_EDGE_RATE
++                      , IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB
++                      | IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M
++                      | IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F
++                      | IMX6Q_GPR13_SATA_SPD_MODE_3P0G
++                      | IMX6Q_GPR13_SATA_MPLL_SS_EN
++                      | IMX6Q_GPR13_SATA_TX_ATTEN_9_16
++                      | IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB
++                      | IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
++      regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
++                      IMX6Q_GPR13_SATA_MPLL_CLK_EN);
++      usleep_range(100, 200);
++
++      /*
++       * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
++       * and IP vendor specific register HOST_TIMER1MS.
++       * Configure CAP_SSS (support stagered spin up).
++       * Implement the port0.
++       * Get the ahb clock rate, and configure the TIMER1MS register.
++       */
++      reg_val = readl(mmio + HOST_CAP);
++      if (!(reg_val & HOST_CAP_SSS)) {
++              reg_val |= HOST_CAP_SSS;
++              writel(reg_val, mmio + HOST_CAP);
++      }
++      reg_val = readl(mmio + HOST_PORTS_IMPL);
++      if (!(reg_val & 0x1)) {
++              reg_val |= 0x1;
++              writel(reg_val, mmio + HOST_PORTS_IMPL);
++      }
++
++      reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
++      writel(reg_val, mmio + HOST_TIMER1MS);
++
++      return 0;
++}
++
++static void imx6q_sata_exit(struct device *dev)
++{
++      struct imx_ahci_priv *imxpriv =  dev_get_drvdata(dev->parent);
++
++      regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
++                      !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
++      clk_disable_unprepare(imxpriv->sata_ref_clk);
++}
++
++static struct ahci_platform_data imx6q_sata_pdata = {
++      .init = imx6q_sata_init,
++      .exit = imx6q_sata_exit,
++};
++
++static const struct of_device_id imx_ahci_of_match[] = {
++      { .compatible = "fsl,imx6q-ahci", .data = &imx6q_sata_pdata},
++      {},
++};
++MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
++
++static int imx_ahci_probe(struct platform_device *pdev)
++{
++      struct device *dev = &pdev->dev;
++      struct resource *mem, *irq, res[2];
++      const struct of_device_id *of_id;
++      const struct ahci_platform_data *pdata = NULL;
++      struct imx_ahci_priv *imxpriv;
++      struct device *ahci_dev;
++      struct platform_device *ahci_pdev;
++      int ret;
++
++      imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
++      if (!imxpriv) {
++              dev_err(dev, "can't alloc ahci_host_priv\n");
++              return -ENOMEM;
++      }
++
++      ahci_pdev = platform_device_alloc("ahci", -1);
++      if (!ahci_pdev)
++              return -ENODEV;
++
++      ahci_dev = &ahci_pdev->dev;
++      ahci_dev->parent = dev;
++
++      imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
++      if (IS_ERR(imxpriv->ahb_clk)) {
++              dev_err(dev, "can't get ahb clock.\n");
++              ret = PTR_ERR(imxpriv->ahb_clk);
++              goto err_out;
++      }
++
++      imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
++      if (IS_ERR(imxpriv->sata_ref_clk)) {
++              dev_err(dev, "can't get sata_ref clock.\n");
++              ret = PTR_ERR(imxpriv->sata_ref_clk);
++              goto err_out;
++      }
++
++      imxpriv->ahci_pdev = ahci_pdev;
++      platform_set_drvdata(pdev, imxpriv);
++
++      of_id = of_match_device(imx_ahci_of_match, dev);
++      if (of_id) {
++              pdata = of_id->data;
++      } else {
++              ret = -EINVAL;
++              goto err_out;
++      }
++
++      mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++      irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
++      if (!mem || !irq) {
++              dev_err(dev, "no mmio/irq resource\n");
++              ret = -ENOMEM;
++              goto err_out;
++      }
++
++      res[0] = *mem;
++      res[1] = *irq;
++
++      ahci_dev->coherent_dma_mask = DMA_BIT_MASK(32);
++      ahci_dev->dma_mask = &ahci_dev->coherent_dma_mask;
++      ahci_dev->of_node = dev->of_node;
++
++      ret = platform_device_add_resources(ahci_pdev, res, 2);
++      if (ret)
++              goto err_out;
++
++      ret = platform_device_add_data(ahci_pdev, pdata, sizeof(*pdata));
++      if (ret)
++              goto err_out;
++
++      ret = platform_device_add(ahci_pdev);
++      if (ret) {
++err_out:
++              platform_device_put(ahci_pdev);
++              return ret;
++      }
++
++      return 0;
++}
++
++static int imx_ahci_remove(struct platform_device *pdev)
++{
++      struct imx_ahci_priv *imxpriv = platform_get_drvdata(pdev);
++      struct platform_device *ahci_pdev = imxpriv->ahci_pdev;
++
++      platform_device_unregister(ahci_pdev);
++      return 0;
++}
++
++static struct platform_driver imx_ahci_driver = {
++      .probe = imx_ahci_probe,
++      .remove = imx_ahci_remove,
++      .driver = {
++              .name = "ahci-imx",
++              .owner = THIS_MODULE,
++              .of_match_table = imx_ahci_of_match,
++      },
++};
++module_platform_driver(imx_ahci_driver);
++
++MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
++MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("ahci:imx");
+-- 
+1.7.10.4
+

diff --git a/src/patches/kernel/wandboard/imx/0010-ahci_imx-depend-on-CONFIG_MFD_SYSCON.patch b/src/patches/kernel/wandboard/imx/0010-ahci_imx-depend-on-CONFIG_MFD_SYSCON.patch
new file mode 100644 (file)
index 0000000..86e7d8f
--- /dev/null
+++ b/src/patches/kernel/wandboard/imx/0010-ahci_imx-depend-on-CONFIG_MFD_SYSCON.patch
@@ -0,0 +1,24 @@
+From: Tejun Heo <tj@kernel.org>
+Subject: [PATCH] ahci_imx: depend on CONFIG_MFD_SYSCON
+
+ahci_imx makes use of regmap but the dependency wasn't specified in
+Kconfig leading build failures if CONFIG_AHCI_IMX is enabled but
+CONFIG_MFD_SYSCON is not.  Add the Kconfig dependency.
+
+Signed-off-by: Tejun Heo <tj@kernel.org>
+Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
+---
+ drivers/ata/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/ata/Kconfig
++++ b/drivers/ata/Kconfig
+@@ -99,7 +99,7 @@ config SATA_AHCI_PLATFORM
+ 
+ config AHCI_IMX
+       tristate "Freescale i.MX AHCI SATA support"
+-      depends on SATA_AHCI_PLATFORM
++      depends on SATA_AHCI_PLATFORM && MFD_SYSCON
+       help
+         This option enables support for the Freescale i.MX SoC's
+         onboard AHCI SATA.

diff --git a/src/patches/kernel/wandboard/imx/0011-add-pcie-designware.patch b/src/patches/kernel/wandboard/imx/0011-add-pcie-designware.patch
new file mode 100644 (file)
index 0000000..3d865d3
--- /dev/null
+++ b/src/patches/kernel/wandboard/imx/0011-add-pcie-designware.patch
@@ -0,0 +1,636 @@
+--- /dev/null  2013-12-09 21:30:35.000000000 +0000
++++ drivers/pci/host/pcie-designware.h 2013-09-20 01:59:32.000000000 +0000
+@@ -0,0 +1,65 @@
++/*
++ * Synopsys Designware PCIe host controller driver
++ *
++ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
++ *            http://www.samsung.com
++ *
++ * Author: Jingoo Han <jg1.han@samsung.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++struct pcie_port_info {
++      u32             cfg0_size;
++      u32             cfg1_size;
++      u32             io_size;
++      u32             mem_size;
++      phys_addr_t     io_bus_addr;
++      phys_addr_t     mem_bus_addr;
++};
++
++struct pcie_port {
++      struct device           *dev;
++      u8                      root_bus_nr;
++      void __iomem            *dbi_base;
++      u64                     cfg0_base;
++      void __iomem            *va_cfg0_base;
++      u64                     cfg1_base;
++      void __iomem            *va_cfg1_base;
++      u64                     io_base;
++      u64                     mem_base;
++      spinlock_t              conf_lock;
++      struct resource         cfg;
++      struct resource         io;
++      struct resource         mem;
++      struct pcie_port_info   config;
++      int                     irq;
++      u32                     lanes;
++      struct pcie_host_ops    *ops;
++};
++
++struct pcie_host_ops {
++      void (*readl_rc)(struct pcie_port *pp,
++                      void __iomem *dbi_base, u32 *val);
++      void (*writel_rc)(struct pcie_port *pp,
++                      u32 val, void __iomem *dbi_base);
++      int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
++      int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
++      int (*link_up)(struct pcie_port *pp);
++      void (*host_init)(struct pcie_port *pp);
++};
++
++extern unsigned long global_io_offset;
++
++int cfg_read(void __iomem *addr, int where, int size, u32 *val);
++int cfg_write(void __iomem *addr, int where, int size, u32 val);
++int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, u32 val);
++int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, u32 *val);
++int dw_pcie_link_up(struct pcie_port *pp);
++void dw_pcie_setup_rc(struct pcie_port *pp);
++int dw_pcie_host_init(struct pcie_port *pp);
++int dw_pcie_setup(int nr, struct pci_sys_data *sys);
++struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys);
++int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
+--- /dev/null  2013-12-09 21:30:35.000000000 +0000
++++ drivers/pci/host/pcie-designware.c 2013-09-20 01:59:32.000000000 +0000
+@@ -0,0 +1,565 @@
++/*
++ * Synopsys Designware PCIe host controller driver
++ *
++ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
++ *            http://www.samsung.com
++ *
++ * Author: Jingoo Han <jg1.han@samsung.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of_address.h>
++#include <linux/pci.h>
++#include <linux/pci_regs.h>
++#include <linux/types.h>
++
++#include "pcie-designware.h"
++
++/* Synopsis specific PCIE configuration registers */
++#define PCIE_PORT_LINK_CONTROL                0x710
++#define PORT_LINK_MODE_MASK           (0x3f << 16)
++#define PORT_LINK_MODE_1_LANES                (0x1 << 16)
++#define PORT_LINK_MODE_2_LANES                (0x3 << 16)
++#define PORT_LINK_MODE_4_LANES                (0x7 << 16)
++
++#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
++#define PORT_LOGIC_SPEED_CHANGE               (0x1 << 17)
++#define PORT_LOGIC_LINK_WIDTH_MASK    (0x1ff << 8)
++#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
++#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
++#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
++
++#define PCIE_MSI_ADDR_LO              0x820
++#define PCIE_MSI_ADDR_HI              0x824
++#define PCIE_MSI_INTR0_ENABLE         0x828
++#define PCIE_MSI_INTR0_MASK           0x82C
++#define PCIE_MSI_INTR0_STATUS         0x830
++
++#define PCIE_ATU_VIEWPORT             0x900
++#define PCIE_ATU_REGION_INBOUND               (0x1 << 31)
++#define PCIE_ATU_REGION_OUTBOUND      (0x0 << 31)
++#define PCIE_ATU_REGION_INDEX1                (0x1 << 0)
++#define PCIE_ATU_REGION_INDEX0                (0x0 << 0)
++#define PCIE_ATU_CR1                  0x904
++#define PCIE_ATU_TYPE_MEM             (0x0 << 0)
++#define PCIE_ATU_TYPE_IO              (0x2 << 0)
++#define PCIE_ATU_TYPE_CFG0            (0x4 << 0)
++#define PCIE_ATU_TYPE_CFG1            (0x5 << 0)
++#define PCIE_ATU_CR2                  0x908
++#define PCIE_ATU_ENABLE                       (0x1 << 31)
++#define PCIE_ATU_BAR_MODE_ENABLE      (0x1 << 30)
++#define PCIE_ATU_LOWER_BASE           0x90C
++#define PCIE_ATU_UPPER_BASE           0x910
++#define PCIE_ATU_LIMIT                        0x914
++#define PCIE_ATU_LOWER_TARGET         0x918
++#define PCIE_ATU_BUS(x)                       (((x) & 0xff) << 24)
++#define PCIE_ATU_DEV(x)                       (((x) & 0x1f) << 19)
++#define PCIE_ATU_FUNC(x)              (((x) & 0x7) << 16)
++#define PCIE_ATU_UPPER_TARGET         0x91C
++
++static struct hw_pci dw_pci;
++
++unsigned long global_io_offset;
++
++static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
++{
++      return sys->private_data;
++}
++
++int cfg_read(void __iomem *addr, int where, int size, u32 *val)
++{
++      *val = readl(addr);
++
++      if (size == 1)
++              *val = (*val >> (8 * (where & 3))) & 0xff;
++      else if (size == 2)
++              *val = (*val >> (8 * (where & 3))) & 0xffff;
++      else if (size != 4)
++              return PCIBIOS_BAD_REGISTER_NUMBER;
++
++      return PCIBIOS_SUCCESSFUL;
++}
++
++int cfg_write(void __iomem *addr, int where, int size, u32 val)
++{
++      if (size == 4)
++              writel(val, addr);
++      else if (size == 2)
++              writew(val, addr + (where & 2));
++      else if (size == 1)
++              writeb(val, addr + (where & 3));
++      else
++              return PCIBIOS_BAD_REGISTER_NUMBER;
++
++      return PCIBIOS_SUCCESSFUL;
++}
++
++static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
++{
++      if (pp->ops->readl_rc)
++              pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
++      else
++              *val = readl(pp->dbi_base + reg);
++}
++
++static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
++{
++      if (pp->ops->writel_rc)
++              pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
++      else
++              writel(val, pp->dbi_base + reg);
++}
++
++int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
++                              u32 *val)
++{
++      int ret;
++
++      if (pp->ops->rd_own_conf)
++              ret = pp->ops->rd_own_conf(pp, where, size, val);
++      else
++              ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
++
++      return ret;
++}
++
++int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
++                              u32 val)
++{
++      int ret;
++
++      if (pp->ops->wr_own_conf)
++              ret = pp->ops->wr_own_conf(pp, where, size, val);
++      else
++              ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size,
++                              val);
++
++      return ret;
++}
++
++int dw_pcie_link_up(struct pcie_port *pp)
++{
++      if (pp->ops->link_up)
++              return pp->ops->link_up(pp);
++      else
++              return 0;
++}
++
++int __init dw_pcie_host_init(struct pcie_port *pp)
++{
++      struct device_node *np = pp->dev->of_node;
++      struct of_pci_range range;
++      struct of_pci_range_parser parser;
++      u32 val;
++
++      if (of_pci_range_parser_init(&parser, np)) {
++              dev_err(pp->dev, "missing ranges property\n");
++              return -EINVAL;
++      }
++
++      /* Get the I/O and memory ranges from DT */
++      for_each_of_pci_range(&parser, &range) {
++              unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
++              if (restype == IORESOURCE_IO) {
++                      of_pci_range_to_resource(&range, np, &pp->io);
++                      pp->io.name = "I/O";
++                      pp->io.start = max_t(resource_size_t,
++                                           PCIBIOS_MIN_IO,
++                                           range.pci_addr + global_io_offset);
++                      pp->io.end = min_t(resource_size_t,
++                                         IO_SPACE_LIMIT,
++                                         range.pci_addr + range.size
++                                         + global_io_offset);
++                      pp->config.io_size = resource_size(&pp->io);
++                      pp->config.io_bus_addr = range.pci_addr;
++              }
++              if (restype == IORESOURCE_MEM) {
++                      of_pci_range_to_resource(&range, np, &pp->mem);
++                      pp->mem.name = "MEM";
++                      pp->config.mem_size = resource_size(&pp->mem);
++                      pp->config.mem_bus_addr = range.pci_addr;
++              }
++              if (restype == 0) {
++                      of_pci_range_to_resource(&range, np, &pp->cfg);
++                      pp->config.cfg0_size = resource_size(&pp->cfg)/2;
++                      pp->config.cfg1_size = resource_size(&pp->cfg)/2;
++              }
++      }
++
++      if (!pp->dbi_base) {
++              pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
++                                      resource_size(&pp->cfg));
++              if (!pp->dbi_base) {
++                      dev_err(pp->dev, "error with ioremap\n");
++                      return -ENOMEM;
++              }
++      }
++
++      pp->cfg0_base = pp->cfg.start;
++      pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
++      pp->io_base = pp->io.start;
++      pp->mem_base = pp->mem.start;
++
++      pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
++                                      pp->config.cfg0_size);
++      if (!pp->va_cfg0_base) {
++              dev_err(pp->dev, "error with ioremap in function\n");
++              return -ENOMEM;
++      }
++      pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
++                                      pp->config.cfg1_size);
++      if (!pp->va_cfg1_base) {
++              dev_err(pp->dev, "error with ioremap\n");
++              return -ENOMEM;
++      }
++
++      if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {
++              dev_err(pp->dev, "Failed to parse the number of lanes\n");
++              return -EINVAL;
++      }
++
++      if (pp->ops->host_init)
++              pp->ops->host_init(pp);
++
++      dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
++
++      /* program correct class for RC */
++      dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
++
++      dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
++      val |= PORT_LOGIC_SPEED_CHANGE;
++      dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
++
++      dw_pci.nr_controllers = 1;
++      dw_pci.private_data = (void **)&pp;
++
++      pci_common_init(&dw_pci);
++      pci_assign_unassigned_resources();
++#ifdef CONFIG_PCI_DOMAINS
++      dw_pci.domain++;
++#endif
++
++      return 0;
++}
++
++static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
++{
++      /* Program viewport 0 : OUTBOUND : CFG0 */
++      dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
++                        PCIE_ATU_VIEWPORT);
++      dw_pcie_writel_rc(pp, pp->cfg0_base, PCIE_ATU_LOWER_BASE);
++      dw_pcie_writel_rc(pp, (pp->cfg0_base >> 32), PCIE_ATU_UPPER_BASE);
++      dw_pcie_writel_rc(pp, pp->cfg0_base + pp->config.cfg0_size - 1,
++                        PCIE_ATU_LIMIT);
++      dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
++      dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
++      dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1);
++      dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
++}
++
++static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
++{
++      /* Program viewport 1 : OUTBOUND : CFG1 */
++      dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
++                        PCIE_ATU_VIEWPORT);
++      dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
++      dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
++      dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);
++      dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
++      dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
++                        PCIE_ATU_LIMIT);
++      dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
++      dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
++}
++
++static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
++{
++      /* Program viewport 0 : OUTBOUND : MEM */
++      dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
++                        PCIE_ATU_VIEWPORT);
++      dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
++      dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
++      dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
++      dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
++      dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,
++                        PCIE_ATU_LIMIT);
++      dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
++      dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
++                        PCIE_ATU_UPPER_TARGET);
++}
++
++static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
++{
++      /* Program viewport 1 : OUTBOUND : IO */
++      dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
++                        PCIE_ATU_VIEWPORT);
++      dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
++      dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
++      dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);
++      dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);
++      dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,
++                        PCIE_ATU_LIMIT);
++      dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
++      dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
++                        PCIE_ATU_UPPER_TARGET);
++}
++
++static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
++              u32 devfn, int where, int size, u32 *val)
++{
++      int ret = PCIBIOS_SUCCESSFUL;
++      u32 address, busdev;
++
++      busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
++               PCIE_ATU_FUNC(PCI_FUNC(devfn));
++      address = where & ~0x3;
++
++      if (bus->parent->number == pp->root_bus_nr) {
++              dw_pcie_prog_viewport_cfg0(pp, busdev);
++              ret = cfg_read(pp->va_cfg0_base + address, where, size, val);
++              dw_pcie_prog_viewport_mem_outbound(pp);
++      } else {
++              dw_pcie_prog_viewport_cfg1(pp, busdev);
++              ret = cfg_read(pp->va_cfg1_base + address, where, size, val);
++              dw_pcie_prog_viewport_io_outbound(pp);
++      }
++
++      return ret;
++}
++
++static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
++              u32 devfn, int where, int size, u32 val)
++{
++      int ret = PCIBIOS_SUCCESSFUL;
++      u32 address, busdev;
++
++      busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
++               PCIE_ATU_FUNC(PCI_FUNC(devfn));
++      address = where & ~0x3;
++
++      if (bus->parent->number == pp->root_bus_nr) {
++              dw_pcie_prog_viewport_cfg0(pp, busdev);
++              ret = cfg_write(pp->va_cfg0_base + address, where, size, val);
++              dw_pcie_prog_viewport_mem_outbound(pp);
++      } else {
++              dw_pcie_prog_viewport_cfg1(pp, busdev);
++              ret = cfg_write(pp->va_cfg1_base + address, where, size, val);
++              dw_pcie_prog_viewport_io_outbound(pp);
++      }
++
++      return ret;
++}
++
++
++static int dw_pcie_valid_config(struct pcie_port *pp,
++                              struct pci_bus *bus, int dev)
++{
++      /* If there is no link, then there is no device */
++      if (bus->number != pp->root_bus_nr) {
++              if (!dw_pcie_link_up(pp))
++                      return 0;
++      }
++
++      /* access only one slot on each root port */
++      if (bus->number == pp->root_bus_nr && dev > 0)
++              return 0;
++
++      /*
++       * do not read more than one device on the bus directly attached
++       * to RC's (Virtual Bridge's) DS side.
++       */
++      if (bus->primary == pp->root_bus_nr && dev > 0)
++              return 0;
++
++      return 1;
++}
++
++static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
++                      int size, u32 *val)
++{
++      struct pcie_port *pp = sys_to_pcie(bus->sysdata);
++      unsigned long flags;
++      int ret;
++
++      if (!pp) {
++              BUG();
++              return -EINVAL;
++      }
++
++      if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
++              *val = 0xffffffff;
++              return PCIBIOS_DEVICE_NOT_FOUND;
++      }
++
++      spin_lock_irqsave(&pp->conf_lock, flags);
++      if (bus->number != pp->root_bus_nr)
++              ret = dw_pcie_rd_other_conf(pp, bus, devfn,
++                                              where, size, val);
++      else
++              ret = dw_pcie_rd_own_conf(pp, where, size, val);
++      spin_unlock_irqrestore(&pp->conf_lock, flags);
++
++      return ret;
++}
++
++static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
++                      int where, int size, u32 val)
++{
++      struct pcie_port *pp = sys_to_pcie(bus->sysdata);
++      unsigned long flags;
++      int ret;
++
++      if (!pp) {
++              BUG();
++              return -EINVAL;
++      }
++
++      if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
++              return PCIBIOS_DEVICE_NOT_FOUND;
++
++      spin_lock_irqsave(&pp->conf_lock, flags);
++      if (bus->number != pp->root_bus_nr)
++              ret = dw_pcie_wr_other_conf(pp, bus, devfn,
++                                              where, size, val);
++      else
++              ret = dw_pcie_wr_own_conf(pp, where, size, val);
++      spin_unlock_irqrestore(&pp->conf_lock, flags);
++
++      return ret;
++}
++
++static struct pci_ops dw_pcie_ops = {
++      .read = dw_pcie_rd_conf,
++      .write = dw_pcie_wr_conf,
++};
++
++int dw_pcie_setup(int nr, struct pci_sys_data *sys)
++{
++      struct pcie_port *pp;
++
++      pp = sys_to_pcie(sys);
++
++      if (!pp)
++              return 0;
++
++      if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
++              sys->io_offset = global_io_offset - pp->config.io_bus_addr;
++              pci_ioremap_io(sys->io_offset, pp->io.start);
++              global_io_offset += SZ_64K;
++              pci_add_resource_offset(&sys->resources, &pp->io,
++                                      sys->io_offset);
++      }
++
++      sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr;
++      pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
++
++      return 1;
++}
++
++struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
++{
++      struct pci_bus *bus;
++      struct pcie_port *pp = sys_to_pcie(sys);
++
++      if (pp) {
++              pp->root_bus_nr = sys->busnr;
++              bus = pci_scan_root_bus(NULL, sys->busnr, &dw_pcie_ops,
++                                      sys, &sys->resources);
++      } else {
++              bus = NULL;
++              BUG();
++      }
++
++      return bus;
++}
++
++int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
++{
++      struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
++
++      return pp->irq;
++}
++
++static struct hw_pci dw_pci = {
++      .setup          = dw_pcie_setup,
++      .scan           = dw_pcie_scan_bus,
++      .map_irq        = dw_pcie_map_irq,
++};
++
++void dw_pcie_setup_rc(struct pcie_port *pp)
++{
++      struct pcie_port_info *config = &pp->config;
++      u32 val;
++      u32 membase;
++      u32 memlimit;
++
++      /* set the number of lines as 4 */
++      dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
++      val &= ~PORT_LINK_MODE_MASK;
++      switch (pp->lanes) {
++      case 1:
++              val |= PORT_LINK_MODE_1_LANES;
++              break;
++      case 2:
++              val |= PORT_LINK_MODE_2_LANES;
++              break;
++      case 4:
++              val |= PORT_LINK_MODE_4_LANES;
++              break;
++      }
++      dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
++
++      /* set link width speed control register */
++      dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
++      val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
++      switch (pp->lanes) {
++      case 1:
++              val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
++              break;
++      case 2:
++              val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
++              break;
++      case 4:
++              val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
++              break;
++      }
++      dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
++
++      /* setup RC BARs */
++      dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
++      dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_1);
++
++      /* setup interrupt pins */
++      dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
++      val &= 0xffff00ff;
++      val |= 0x00000100;
++      dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
++
++      /* setup bus numbers */
++      dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
++      val &= 0xff000000;
++      val |= 0x00010100;
++      dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
++
++      /* setup memory base, memory limit */
++      membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
++      memlimit = (config->mem_size + (u32)pp->mem_base) & 0xfff00000;
++      val = memlimit | membase;
++      dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
++
++      /* setup command register */
++      dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
++      val &= 0xffff0000;
++      val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
++              PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
++      dw_pcie_writel_rc(pp, val, PCI_COMMAND);
++}
++
++MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
++MODULE_DESCRIPTION("Designware PCIe host controller driver");
++MODULE_LICENSE("GPL v2");

diff --git a/src/patches/kernel/wandboard/imx/0012-pcie-backport-fixes.patch b/src/patches/kernel/wandboard/imx/0012-pcie-backport-fixes.patch
new file mode 100644 (file)
index 0000000..aef6b05
--- /dev/null
+++ b/src/patches/kernel/wandboard/imx/0012-pcie-backport-fixes.patch
@@ -0,0 +1,17 @@
+--- a/drivers/pci/Kconfig
++++ b/drivers/pci/Kconfig
+@@ -125,3 +125,5 @@ config PCI_IOAPIC
+ config PCI_LABEL
+       def_bool y if (DMI || ACPI)
+       select NLS
++
++source "drivers/pci/host/Kconfig"
+--- a/drivers/pci/Makefile
++++ b/drivers/pci/Makefile
+@@ -67,3 +67,6 @@ obj-$(CONFIG_XEN_PCIDEV_FRONTEND) += xen
+ obj-$(CONFIG_OF) += of.o
+ 
+ ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG
++
++# PCI host controller drivers
++obj-y += host/

diff --git a/src/patches/kernel/wandboard/imx/0013-of-pci-Provide-support-for-parsing-PCI-DT-ranges-pro.patch b/src/patches/kernel/wandboard/imx/0013-of-pci-Provide-support-for-parsing-PCI-DT-ranges-pro.patch
new file mode 100644 (file)
index 0000000..ab20f7f
--- /dev/null
+++ b/src/patches/kernel/wandboard/imx/0013-of-pci-Provide-support-for-parsing-PCI-DT-ranges-pro.patch
@@ -0,0 +1,194 @@
+From: Andrew Murray <Andrew.Murray@arm.com>
+Subject: [PATCH] of/pci: Provide support for parsing PCI DT ranges property
+
+This patch factors out common implementation patterns to reduce overall kernel
+code and provide a means for host bridge drivers to directly obtain struct
+resources from the DT's ranges property without relying on architecture specific
+DT handling. This will make it easier to write archiecture independent host bridge
+drivers and mitigate against further duplication of DT parsing code.
+
+This patch can be used in the following way:
+
+       struct of_pci_range_parser parser;
+       struct of_pci_range range;
+
+       if (of_pci_range_parser_init(&parser, np))
+               ; //no ranges property
+
+       for_each_of_pci_range(&parser, &range) {
+
+               /*
+                       directly access properties of the address range, e.g.:
+                       range.pci_space, range.pci_addr, range.cpu_addr,
+                       range.size, range.flags
+
+                       alternatively obtain a struct resource, e.g.:
+                       struct resource res;
+                       of_pci_range_to_resource(&range, np, &res);
+               */
+       }
+
+Additionally the implementation takes care of adjacent ranges and merges them
+into a single range (as was the case with powerpc and microblaze).
+
+Signed-off-by: Andrew Murray <Andrew.Murray@arm.com>
+Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Reviewed-by: Rob Herring <rob.herring@calxeda.com>
+Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Tested-by: Linus Walleij <linus.walleij@linaro.org>
+Tested-by: Jingoo Han <jg1.han@samsung.com>
+Acked-by: Grant Likely <grant.likely@secretlab.ca>
+Signed-off-by: Jason Cooper <jason@lakedaemon.net>
+---
+ drivers/of/address.c       | 67 ++++++++++++++++++++++++++++++++++++++++++++++
+ include/linux/of_address.h | 48 +++++++++++++++++++++++++++++++++
+ 2 files changed, 115 insertions(+)
+
+--- a/drivers/of/address.c
++++ b/drivers/of/address.c
+@@ -231,6 +231,73 @@ int of_pci_address_to_resource(struct de
+       return __of_address_to_resource(dev, addrp, size, flags, NULL, r);
+ }
+ EXPORT_SYMBOL_GPL(of_pci_address_to_resource);
++
++int of_pci_range_parser_init(struct of_pci_range_parser *parser,
++                              struct device_node *node)
++{
++      const int na = 3, ns = 2;
++      int rlen;
++
++      parser->node = node;
++      parser->pna = of_n_addr_cells(node);
++      parser->np = parser->pna + na + ns;
++
++      parser->range = of_get_property(node, "ranges", &rlen);
++      if (parser->range == NULL)
++              return -ENOENT;
++
++      parser->end = parser->range + rlen / sizeof(__be32);
++
++      return 0;
++}
++EXPORT_SYMBOL_GPL(of_pci_range_parser_init);
++
++struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser,
++                                              struct of_pci_range *range)
++{
++      const int na = 3, ns = 2;
++
++      if (!range)
++              return NULL;
++
++      if (!parser->range || parser->range + parser->np > parser->end)
++              return NULL;
++
++      range->pci_space = parser->range[0];
++      range->flags = of_bus_pci_get_flags(parser->range);
++      range->pci_addr = of_read_number(parser->range + 1, ns);
++      range->cpu_addr = of_translate_address(parser->node,
++                              parser->range + na);
++      range->size = of_read_number(parser->range + parser->pna + na, ns);
++
++      parser->range += parser->np;
++
++      /* Now consume following elements while they are contiguous */
++      while (parser->range + parser->np <= parser->end) {
++              u32 flags, pci_space;
++              u64 pci_addr, cpu_addr, size;
++
++              pci_space = be32_to_cpup(parser->range);
++              flags = of_bus_pci_get_flags(parser->range);
++              pci_addr = of_read_number(parser->range + 1, ns);
++              cpu_addr = of_translate_address(parser->node,
++                              parser->range + na);
++              size = of_read_number(parser->range + parser->pna + na, ns);
++
++              if (flags != range->flags)
++                      break;
++              if (pci_addr != range->pci_addr + range->size ||
++                  cpu_addr != range->cpu_addr + range->size)
++                      break;
++
++              range->size += size;
++              parser->range += parser->np;
++      }
++
++      return range;
++}
++EXPORT_SYMBOL_GPL(of_pci_range_parser_one);
++
+ #endif /* CONFIG_PCI */
+ 
+ /*
+--- a/include/linux/of_address.h
++++ b/include/linux/of_address.h
+@@ -4,6 +4,36 @@
+ #include <linux/errno.h>
+ #include <linux/of.h>
+ 
++struct of_pci_range_parser {
++      struct device_node *node;
++      const __be32 *range;
++      const __be32 *end;
++      int np;
++      int pna;
++};
++
++struct of_pci_range {
++      u32 pci_space;
++      u64 pci_addr;
++      u64 cpu_addr;
++      u64 size;
++      u32 flags;
++};
++
++#define for_each_of_pci_range(parser, range) \
++      for (; of_pci_range_parser_one(parser, range);)
++
++static inline void of_pci_range_to_resource(struct of_pci_range *range,
++                                          struct device_node *np,
++                                          struct resource *res)
++{
++      res->flags = range->flags;
++      res->start = range->cpu_addr;
++      res->end = range->cpu_addr + range->size - 1;
++      res->parent = res->child = res->sibling = NULL;
++      res->name = np->full_name;
++}
++
+ #ifdef CONFIG_OF_ADDRESS
+ extern u64 of_translate_address(struct device_node *np, const __be32 *addr);
+ extern bool of_can_translate_address(struct device_node *dev);
+@@ -27,6 +57,11 @@ static inline unsigned long pci_address_
+ #define pci_address_to_pio pci_address_to_pio
+ #endif
+ 
++extern int of_pci_range_parser_init(struct of_pci_range_parser *parser,
++                      struct device_node *node);
++extern struct of_pci_range *of_pci_range_parser_one(
++                                      struct of_pci_range_parser *parser,
++                                      struct of_pci_range *range);
+ #else /* CONFIG_OF_ADDRESS */
+ #ifndef of_address_to_resource
+ static inline int of_address_to_resource(struct device_node *dev, int index,
+@@ -53,6 +88,19 @@ static inline const __be32 *of_get_addre
+ {
+       return NULL;
+ }
++
++static inline int of_pci_range_parser_init(struct of_pci_range_parser *parser,
++                      struct device_node *node)
++{
++      return -1;
++}
++
++static inline struct of_pci_range *of_pci_range_parser_one(
++                                      struct of_pci_range_parser *parser,
++                                      struct of_pci_range *range)
++{
++      return NULL;
++}
+ #endif /* CONFIG_OF_ADDRESS */
+ 
+ 

diff --git a/src/patches/kernel/wandboard/imx/0014-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch b/src/patches/kernel/wandboard/imx/0014-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch
new file mode 100644 (file)
index 0000000..19ca079
--- /dev/null
+++ b/src/patches/kernel/wandboard/imx/0014-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch
@@ -0,0 +1,37 @@
+From: Sean Cross <xobs@kosagi.com>
+Subject: [PATCH 1/2] ARM: imx6q: Add PCIe bits to GPR syscon definition
+
+PCIe requires additional bits be defined for GPR8 and GPR12.
+
+Signed-off-by: Sean Cross <xobs@kosagi.com>
+Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+---
+ include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
++++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+@@ -241,6 +241,12 @@
+ 
+ #define IMX6Q_GPR5_L2_CLK_STOP                        BIT(8)
+ 
++#define IMX6Q_GPR8_TX_SWING_LOW                       (0x7f << 25)
++#define IMX6Q_GPR8_TX_SWING_FULL              (0x7f << 18)
++#define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB         (0x3f << 12)
++#define IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB               (0x3f << 6)
++#define IMX6Q_GPR8_TX_DEEMPH_GEN1             (0x3f << 0)
++
+ #define IMX6Q_GPR9_TZASC2_BYP                 BIT(1)
+ #define IMX6Q_GPR9_TZASC1_BYP                 BIT(0)
+ 
+@@ -273,7 +279,9 @@
+ #define IMX6Q_GPR12_ARMP_AHB_CLK_EN           BIT(26)
+ #define IMX6Q_GPR12_ARMP_ATB_CLK_EN           BIT(25)
+ #define IMX6Q_GPR12_ARMP_APB_CLK_EN           BIT(24)
++#define IMX6Q_GPR12_DEVICE_TYPE                       (0xf << 12)
+ #define IMX6Q_GPR12_PCIE_CTL_2                        BIT(10)
++#define IMX6Q_GPR12_LOS_LEVEL                 (0x1f << 4)
+ 
+ #define IMX6Q_GPR13_SDMA_STOP_REQ             BIT(30)
+ #define IMX6Q_GPR13_CAN2_STOP_REQ             BIT(29)

diff --git a/src/patches/kernel/wandboard/imx/0015-PCI-imx6-Add-support-for-i.MX6-PCIe-controller.patch b/src/patches/kernel/wandboard/imx/0015-PCI-imx6-Add-support-for-i.MX6-PCIe-controller.patch
new file mode 100644 (file)
index 0000000..599cd0e
--- /dev/null
+++ b/src/patches/kernel/wandboard/imx/0015-PCI-imx6-Add-support-for-i.MX6-PCIe-controller.patch
@@ -0,0 +1,616 @@
+Subject: [PATCH 2/2] PCI: imx6: Add support for i.MX6 PCIe controller
+From: Sean Cross <xobs@kosagi.com>
+
+Add support for the PCIe port present on the i.MX6 family of controllers.
+These use the Synopsis Designware core tied to their own PHY.
+
+Signed-off-by: Sean Cross <xobs@kosagi.com>
+Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
+---
+ drivers/pci/host/Kconfig                           |   6 +
+ drivers/pci/host/Makefile                          |   1 +
+ drivers/pci/host/pci-imx6.c                        | 575 +++++++++++++++++++++
+ 4 files changed, 588 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/pci/host/pci-imx6.c
+
+--- /dev/null
++++ b/drivers/pci/host/Kconfig
+@@ -0,0 +1,13 @@
++menu "PCI host controller drivers"
++      depends on PCI
++
++config PCIE_DW
++      bool
++
++config PCI_IMX6
++      bool "Freescale i.MX6 PCIe controller"
++      depends on SOC_IMX6Q
++      select PCIEPORTBUS
++      select PCIE_DW
++
++endmenu
+--- /dev/null
++++ b/drivers/pci/host/Makefile
+@@ -0,0 +1,2 @@
++obj-$(CONFIG_PCIE_DW) += pcie-designware.o
++obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
+--- /dev/null
++++ b/drivers/pci/host/pci-imx6.c
+@@ -0,0 +1,575 @@
++/*
++ * PCIe host controller driver for Freescale i.MX6 SoCs
++ *
++ * Copyright (C) 2013 Kosagi
++ *            http://www.kosagi.com
++ *
++ * Author: Sean Cross <xobs@kosagi.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/kernel.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
++#include <linux/module.h>
++#include <linux/of_gpio.h>
++#include <linux/pci.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++#include <linux/resource.h>
++#include <linux/signal.h>
++#include <linux/types.h>
++
++#include "pcie-designware.h"
++
++#define to_imx6_pcie(x)       container_of(x, struct imx6_pcie, pp)
++
++struct imx6_pcie {
++      int                     reset_gpio;
++      int                     power_on_gpio;
++      int                     wake_up_gpio;
++      int                     disable_gpio;
++      struct clk              *lvds_gate;
++      struct clk              *sata_ref_100m;
++      struct clk              *pcie_ref_125m;
++      struct clk              *pcie_axi;
++      struct pcie_port        pp;
++      struct regmap           *iomuxc_gpr;
++      void __iomem            *mem_base;
++};
++
++/* PCIe Port Logic registers (memory-mapped) */
++#define PL_OFFSET 0x700
++#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
++#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
++
++#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
++#define PCIE_PHY_CTRL_DATA_LOC 0
++#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
++#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
++#define PCIE_PHY_CTRL_WR_LOC 18
++#define PCIE_PHY_CTRL_RD_LOC 19
++
++#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
++#define PCIE_PHY_STAT_ACK_LOC 16
++
++/* PHY registers (not memory-mapped) */
++#define PCIE_PHY_RX_ASIC_OUT 0x100D
++
++#define PHY_RX_OVRD_IN_LO 0x1005
++#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
++#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
++
++static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
++{
++      u32 val;
++      u32 max_iterations = 10;
++      u32 wait_counter = 0;
++
++      do {
++              val = readl(dbi_base + PCIE_PHY_STAT);
++              val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
++              wait_counter++;
++
++              if (val == exp_val)
++                      return 0;
++
++              udelay(1);
++      } while (wait_counter < max_iterations);
++
++      return -ETIMEDOUT;
++}
++
++static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
++{
++      u32 val;
++      int ret;
++
++      val = addr << PCIE_PHY_CTRL_DATA_LOC;
++      writel(val, dbi_base + PCIE_PHY_CTRL);
++
++      val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
++      writel(val, dbi_base + PCIE_PHY_CTRL);
++
++      ret = pcie_phy_poll_ack(dbi_base, 1);
++      if (ret)
++              return ret;
++
++      val = addr << PCIE_PHY_CTRL_DATA_LOC;
++      writel(val, dbi_base + PCIE_PHY_CTRL);
++
++      ret = pcie_phy_poll_ack(dbi_base, 0);
++      if (ret)
++              return ret;
++
++      return 0;
++}
++
++/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
++static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
++{
++      u32 val, phy_ctl;
++      int ret;
++
++      ret = pcie_phy_wait_ack(dbi_base, addr);
++      if (ret)
++              return ret;
++
++      /* assert Read signal */
++      phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
++      writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
++
++      ret = pcie_phy_poll_ack(dbi_base, 1);
++      if (ret)
++              return ret;
++
++      val = readl(dbi_base + PCIE_PHY_STAT);
++      *data = val & 0xffff;
++
++      /* deassert Read signal */
++      writel(0x00, dbi_base + PCIE_PHY_CTRL);
++
++      ret = pcie_phy_poll_ack(dbi_base, 0);
++      if (ret)
++              return ret;
++
++      return 0;
++}
++
++static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
++{
++      u32 var;
++      int ret;
++
++      /* write addr */
++      /* cap addr */
++      ret = pcie_phy_wait_ack(dbi_base, addr);
++      if (ret)
++              return ret;
++
++      var = data << PCIE_PHY_CTRL_DATA_LOC;
++      writel(var, dbi_base + PCIE_PHY_CTRL);
++
++      /* capture data */
++      var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
++      writel(var, dbi_base + PCIE_PHY_CTRL);
++
++      ret = pcie_phy_poll_ack(dbi_base, 1);
++      if (ret)
++              return ret;
++
++      /* deassert cap data */
++      var = data << PCIE_PHY_CTRL_DATA_LOC;
++      writel(var, dbi_base + PCIE_PHY_CTRL);
++
++      /* wait for ack de-assertion */
++      ret = pcie_phy_poll_ack(dbi_base, 0);
++      if (ret)
++              return ret;
++
++      /* assert wr signal */
++      var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
++      writel(var, dbi_base + PCIE_PHY_CTRL);
++
++      /* wait for ack */
++      ret = pcie_phy_poll_ack(dbi_base, 1);
++      if (ret)
++              return ret;
++
++      /* deassert wr signal */
++      var = data << PCIE_PHY_CTRL_DATA_LOC;
++      writel(var, dbi_base + PCIE_PHY_CTRL);
++
++      /* wait for ack de-assertion */
++      ret = pcie_phy_poll_ack(dbi_base, 0);
++      if (ret)
++              return ret;
++
++      writel(0x0, dbi_base + PCIE_PHY_CTRL);
++
++      return 0;
++}
++
++/*  Added for PCI abort handling */
++static int imx6q_pcie_abort_handler(unsigned long addr,
++              unsigned int fsr, struct pt_regs *regs)
++{
++      /*
++       * If it was an imprecise abort, then we need to correct the
++       * return address to be _after_ the instruction.
++       */
++      if (fsr & (1 << 10))
++              regs->ARM_pc += 4;
++      return 0;
++}
++
++static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
++{
++      struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
++
++      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
++                      IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
++      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
++                      IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
++      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
++                      IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
++
++      gpio_set_value(imx6_pcie->reset_gpio, 0);
++      msleep(100);
++      gpio_set_value(imx6_pcie->reset_gpio, 1);
++
++      return 0;
++}
++
++static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
++{
++      struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
++      int ret;
++
++      if (gpio_is_valid(imx6_pcie->power_on_gpio))
++              gpio_set_value(imx6_pcie->power_on_gpio, 1);
++
++      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
++                      IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
++      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
++                      IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
++
++      ret = clk_prepare_enable(imx6_pcie->sata_ref_100m);
++      if (ret) {
++              dev_err(pp->dev, "unable to enable sata_ref_100m\n");
++              goto err_sata_ref;
++      }
++
++      ret = clk_prepare_enable(imx6_pcie->pcie_ref_125m);
++      if (ret) {
++              dev_err(pp->dev, "unable to enable pcie_ref_125m\n");
++              goto err_pcie_ref;
++      }
++
++      ret = clk_prepare_enable(imx6_pcie->lvds_gate);
++      if (ret) {
++              dev_err(pp->dev, "unable to enable lvds_gate\n");
++              goto err_lvds_gate;
++      }
++
++      ret = clk_prepare_enable(imx6_pcie->pcie_axi);
++      if (ret) {
++              dev_err(pp->dev, "unable to enable pcie_axi\n");
++              goto err_pcie_axi;
++      }
++
++      /* allow the clocks to stabilize */
++      usleep_range(200, 500);
++
++      return 0;
++
++err_pcie_axi:
++      clk_disable_unprepare(imx6_pcie->lvds_gate);
++err_lvds_gate:
++      clk_disable_unprepare(imx6_pcie->pcie_ref_125m);
++err_pcie_ref:
++      clk_disable_unprepare(imx6_pcie->sata_ref_100m);
++err_sata_ref:
++      return ret;
++
++}
++
++static void imx6_pcie_init_phy(struct pcie_port *pp)
++{
++      struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
++
++      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
++                      IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
++
++      /* configure constant input signal to the pcie ctrl and phy */
++      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
++                      IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
++      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
++                      IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
++
++      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
++                      IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0);
++      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
++                      IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6);
++      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
++                      IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12);
++      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
++                      IMX6Q_GPR8_TX_SWING_FULL, 127 << 18);
++      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
++                      IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
++}
++
++static void imx6_pcie_host_init(struct pcie_port *pp)
++{
++      int count = 0;
++      struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
++
++      imx6_pcie_assert_core_reset(pp);
++
++      imx6_pcie_init_phy(pp);
++
++      imx6_pcie_deassert_core_reset(pp);
++
++      dw_pcie_setup_rc(pp);
++
++      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
++                      IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
++
++      while (!dw_pcie_link_up(pp)) {
++              usleep_range(100, 1000);
++              count++;
++              if (count >= 10) {
++                      dev_err(pp->dev, "phy link never came up\n");
++                      dev_dbg(pp->dev,
++                              "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
++                              readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
++                              readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
++                      break;
++              }
++      }
++
++      return;
++}
++
++static int imx6_pcie_link_up(struct pcie_port *pp)
++{
++      u32 rc, ltssm, rx_valid, temp;
++
++      /* link is debug bit 36, debug register 1 starts at bit 32 */
++      rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & (0x1 << (36 - 32));
++      if (rc)
++              return -EAGAIN;
++
++      /*
++       * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
++       * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
++       * If (MAC/LTSSM.state == Recovery.RcvrLock)
++       * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
++       * to gen2 is stuck
++       */
++      pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
++      ltssm = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;
++
++      if (rx_valid & 0x01)
++              return 0;
++
++      if (ltssm != 0x0d)
++              return 0;
++
++      dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
++
++      pcie_phy_read(pp->dbi_base,
++              PHY_RX_OVRD_IN_LO, &temp);
++      temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN
++              | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
++      pcie_phy_write(pp->dbi_base,
++              PHY_RX_OVRD_IN_LO, temp);
++
++      usleep_range(2000, 3000);
++
++      pcie_phy_read(pp->dbi_base,
++              PHY_RX_OVRD_IN_LO, &temp);
++      temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN
++              | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
++      pcie_phy_write(pp->dbi_base,
++              PHY_RX_OVRD_IN_LO, temp);
++
++      return 0;
++}
++
++static struct pcie_host_ops imx6_pcie_host_ops = {
++      .link_up = imx6_pcie_link_up,
++      .host_init = imx6_pcie_host_init,
++};
++
++static int imx6_add_pcie_port(struct pcie_port *pp,
++                      struct platform_device *pdev)
++{
++      int ret;
++
++      pp->irq = platform_get_irq(pdev, 0);
++      if (!pp->irq) {
++              dev_err(&pdev->dev, "failed to get irq\n");
++              return -ENODEV;
++      }
++
++      pp->root_bus_nr = -1;
++      pp->ops = &imx6_pcie_host_ops;
++
++      spin_lock_init(&pp->conf_lock);
++      ret = dw_pcie_host_init(pp);
++      if (ret) {
++              dev_err(&pdev->dev, "failed to initialize host\n");
++              return ret;
++      }
++
++      return 0;
++}
++
++static int __init imx6_pcie_probe(struct platform_device *pdev)
++{
++      struct imx6_pcie *imx6_pcie;
++      struct pcie_port *pp;
++      struct device_node *np = pdev->dev.of_node;
++      struct resource *dbi_base;
++      int ret;
++
++      imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL);
++      if (!imx6_pcie)
++              return -ENOMEM;
++
++      pp = &imx6_pcie->pp;
++      pp->dev = &pdev->dev;
++
++      /* Added for PCI abort handling */
++      hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
++              "imprecise external abort");
++
++      dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++      if (!dbi_base) {
++              dev_err(&pdev->dev, "dbi_base memory resource not found\n");
++              return -ENODEV;
++      }
++
++      pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
++      if (IS_ERR(pp->dbi_base)) {
++              dev_err(&pdev->dev, "unable to remap dbi_base\n");
++              ret = PTR_ERR(pp->dbi_base);
++              goto err;
++      }
++
++      /* Fetch GPIOs */
++      imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
++      if (!gpio_is_valid(imx6_pcie->reset_gpio)) {
++              dev_err(&pdev->dev, "no reset-gpio defined\n");
++              ret = -ENODEV;
++      }
++      ret = devm_gpio_request_one(&pdev->dev,
++                              imx6_pcie->reset_gpio,
++                              GPIOF_OUT_INIT_LOW,
++                              "PCIe reset");
++      if (ret) {
++              dev_err(&pdev->dev, "unable to get reset gpio\n");
++              goto err;
++      }
++
++      imx6_pcie->power_on_gpio = of_get_named_gpio(np, "power-on-gpio", 0);
++      if (gpio_is_valid(imx6_pcie->power_on_gpio)) {
++              ret = devm_gpio_request_one(&pdev->dev,
++                                      imx6_pcie->power_on_gpio,
++                                      GPIOF_OUT_INIT_LOW,
++                                      "PCIe power enable");
++              if (ret) {
++                      dev_err(&pdev->dev, "unable to get power-on gpio\n");
++                      goto err;
++              }
++      }
++
++      imx6_pcie->wake_up_gpio = of_get_named_gpio(np, "wake-up-gpio", 0);
++      if (gpio_is_valid(imx6_pcie->wake_up_gpio)) {
++              ret = devm_gpio_request_one(&pdev->dev,
++                                      imx6_pcie->wake_up_gpio,
++                                      GPIOF_IN,
++                                      "PCIe wake up");
++              if (ret) {
++                      dev_err(&pdev->dev, "unable to get wake-up gpio\n");
++                      goto err;
++              }
++      }
++
++      imx6_pcie->disable_gpio = of_get_named_gpio(np, "disable-gpio", 0);
++      if (gpio_is_valid(imx6_pcie->disable_gpio)) {
++              ret = devm_gpio_request_one(&pdev->dev,
++                                      imx6_pcie->disable_gpio,
++                                      GPIOF_OUT_INIT_HIGH,
++                                      "PCIe disable endpoint");
++              if (ret) {
++                      dev_err(&pdev->dev, "unable to get disable-ep gpio\n");
++                      goto err;
++              }
++      }
++
++      /* Fetch clocks */
++      imx6_pcie->lvds_gate = devm_clk_get(&pdev->dev, "lvds_gate");
++      if (IS_ERR(imx6_pcie->lvds_gate)) {
++              dev_err(&pdev->dev,
++                      "lvds_gate clock select missing or invalid\n");
++              ret = PTR_ERR(imx6_pcie->lvds_gate);
++              goto err;
++      }
++
++      imx6_pcie->sata_ref_100m = devm_clk_get(&pdev->dev, "sata_ref_100m");
++      if (IS_ERR(imx6_pcie->sata_ref_100m)) {
++              dev_err(&pdev->dev,
++                      "sata_ref_100m clock source missing or invalid\n");
++              ret = PTR_ERR(imx6_pcie->sata_ref_100m);
++              goto err;
++      }
++
++      imx6_pcie->pcie_ref_125m = devm_clk_get(&pdev->dev, "pcie_ref_125m");
++      if (IS_ERR(imx6_pcie->pcie_ref_125m)) {
++              dev_err(&pdev->dev,
++                      "pcie_ref_125m clock source missing or invalid\n");
++              ret = PTR_ERR(imx6_pcie->pcie_ref_125m);
++              goto err;
++      }
++
++      imx6_pcie->pcie_axi = devm_clk_get(&pdev->dev, "pcie_axi");
++      if (IS_ERR(imx6_pcie->pcie_axi)) {
++              dev_err(&pdev->dev,
++                      "pcie_axi clock source missing or invalid\n");
++              ret = PTR_ERR(imx6_pcie->pcie_axi);
++              goto err;
++      }
++
++      /* Grab GPR config register range */
++      imx6_pcie->iomuxc_gpr =
++               syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
++      if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
++              dev_err(&pdev->dev, "unable to find iomuxc registers\n");
++              ret = PTR_ERR(imx6_pcie->iomuxc_gpr);
++              goto err;
++      }
++
++      ret = imx6_add_pcie_port(pp, pdev);
++      if (ret < 0)
++              goto err;
++
++      platform_set_drvdata(pdev, imx6_pcie);
++      return 0;
++
++err:
++      return ret;
++}
++
++static const struct of_device_id imx6_pcie_of_match[] = {
++      { .compatible = "fsl,imx6q-pcie", },
++      {},
++};
++MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);
++
++static struct platform_driver imx6_pcie_driver = {
++      .driver = {
++              .name   = "imx6q-pcie",
++              .owner  = THIS_MODULE,
++              .of_match_table = of_match_ptr(imx6_pcie_of_match),
++      },
++};
++
++/* Freescale PCIe driver does not allow module unload */
++
++static int __init imx6_pcie_init(void)
++{
++      return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
++}
++module_init(imx6_pcie_init);
++
++MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
++MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
++MODULE_LICENSE("GPL v2");

diff --git a/src/patches/kernel/wandboard/imx/0016-imx6-pci-tweaks.patch b/src/patches/kernel/wandboard/imx/0016-imx6-pci-tweaks.patch
new file mode 100644 (file)
index 0000000..eda007e
--- /dev/null
+++ b/src/patches/kernel/wandboard/imx/0016-imx6-pci-tweaks.patch
@@ -0,0 +1,24 @@
+--- a/drivers/pci/host/pci-imx6.c
++++ b/drivers/pci/host/pci-imx6.c
+@@ -200,12 +200,6 @@ static int pcie_phy_write(void __iomem *
+ static int imx6q_pcie_abort_handler(unsigned long addr,
+               unsigned int fsr, struct pt_regs *regs)
+ {
+-      /*
+-       * If it was an imprecise abort, then we need to correct the
+-       * return address to be _after_ the instruction.
+-       */
+-      if (fsr & (1 << 10))
+-              regs->ARM_pc += 4;
+       return 0;
+ }
+ 
+@@ -322,7 +316,7 @@ static void imx6_pcie_host_init(struct p
+                       IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
+ 
+       while (!dw_pcie_link_up(pp)) {
+-              usleep_range(100, 1000);
++              usleep_range(2000, 3000);
+               count++;
+               if (count >= 10) {
+                       dev_err(pp->dev, "phy link never came up\n");

diff --git a/src/patches/kernel/wandboard/imx/0017-ARM-imx-Add-LVDS-general-purpose-clocks-to-i.MX6Q.patch b/src/patches/kernel/wandboard/imx/0017-ARM-imx-Add-LVDS-general-purpose-clocks-to-i.MX6Q.patch
new file mode 100644 (file)
index 0000000..3f1b6eb
--- /dev/null
+++ b/src/patches/kernel/wandboard/imx/0017-ARM-imx-Add-LVDS-general-purpose-clocks-to-i.MX6Q.patch
@@ -0,0 +1,70 @@
+From: Sean Cross <xobs@kosagi.com>
+Subject: [PATCH 1/3] ARM: imx: Add LVDS general-purpose clocks to i.MX6Q
+
+The i.MX6 has two general-purpose LVDS clocks that can be driven
+from a variety of sources.  This patch adds a mux and a gate for
+both of these clocks.
+
+Signed-off-by: Sean Cross <xobs@kosagi.com>
+Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
+---
+ .../devicetree/bindings/clock/imx6q-clock.txt        |  4 ++++
+ arch/arm/mach-imx/clk-imx6q.c                        | 20 +++++++++++++++++++-
+ 2 files changed, 23 insertions(+), 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
++++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+@@ -208,6 +208,10 @@ clocks and IDs.
+       pll4_post_div           193
+       pll5_post_div           194
+       pll5_video_div          195
++      lvds1_sel               204
++      lvds2_sel               205
++      lvds1_gate              206
++      lvds2_gate              207
+ 
+ Examples:
+ 
+--- a/arch/arm/mach-imx/clk-imx6q.c
++++ b/arch/arm/mach-imx/clk-imx6q.c
+@@ -205,6 +205,11 @@ static const char *vpu_axi_sels[] = { "a
+ static const char *cko1_sels[]        = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
+                                   "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
+                                   "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", };
++static const char *lvds_sels[] = {
++      "dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
++      "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",
++      "pcie_ref", "sata_ref",
++};
+ 
+ enum mx6q_clks {
+       dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
+@@ -238,7 +243,8 @@ enum mx6q_clks {
+       pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
+       ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
+       sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
+-      usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, clk_max
++      usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div,
++      lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, clk_max
+ };
+ 
+ static struct clk *clk[clk_max];
+@@ -340,6 +346,18 @@ int __init mx6q_clocks_init(void)
+                       base + 0xe0, 0, 2, 0, clk_enet_ref_table,
+                       &imx_ccm_lock);
+ 
++      clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
++      clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
++
++      /*
++       * lvds1_gate and lvds2_gate are pseudo-gates.  Both can be
++       * independently configured as clock inputs or outputs.  We treat
++       * the "output_enable" bit as a gate, even though it's really just
++       * enabling clock output.
++       */
++      clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "dummy", base + 0x160, 10);
++      clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "dummy", base + 0x160, 11);
++
+       /*                                name              parent_name        reg       idx */
+       clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus",     base + 0x100, 0);
+       clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus",     base + 0x100, 1);

diff --git a/src/patches/kernel/wandboard/imx/0018-ARM-imx6q-clock-and-Kconfig-update-for-PCIe-support.patch b/src/patches/kernel/wandboard/imx/0018-ARM-imx6q-clock-and-Kconfig-update-for-PCIe-support.patch
new file mode 100644 (file)
index 0000000..25f207a
--- /dev/null
+++ b/src/patches/kernel/wandboard/imx/0018-ARM-imx6q-clock-and-Kconfig-update-for-PCIe-support.patch
@@ -0,0 +1,38 @@
+From 4f6723e8ff497e35c8f2fb20886fccc533c58cdb Mon Sep 17 00:00:00 2001
+From: Sean Cross <xobs@kosagi.com>
+Date: Thu, 26 Sep 2013 10:45:35 +0800
+Subject: [PATCH] ARM: imx6q: clock and Kconfig update for PCIe support
+
+Update imx6q clock initialization and Kconfig for PCIe support.
+
+Signed-off-by: Sean Cross <xobs@kosagi.com>
+Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
+---
+ arch/arm/mach-imx/Kconfig     | 2 ++
+ arch/arm/mach-imx/clk-imx6q.c | 4 ++++
+ 2 files changed, 6 insertions(+)
+
+--- a/arch/arm/mach-imx/Kconfig
++++ b/arch/arm/mach-imx/Kconfig
+@@ -806,6 +806,8 @@ config SOC_IMX6Q
+       select HAVE_IMX_SRC
+       select HAVE_SMP
+       select MFD_SYSCON
++      select MIGHT_HAVE_PCI
++      select PCI_DOMAINS if PCI
+       select PINCTRL
+       select PINCTRL_IMX6Q
+       select PL310_ERRATA_588369 if CACHE_PL310
+--- a/arch/arm/mach-imx/clk-imx6q.c
++++ b/arch/arm/mach-imx/clk-imx6q.c
+@@ -586,6 +586,10 @@ int __init mx6q_clocks_init(void)
+               clk_prepare_enable(clk[usbphy2_gate]);
+       }
+ 
++      /* All existing boards with PCIe use LVDS1 */
++      if (IS_ENABLED(CONFIG_PCI_IMX6))
++              clk_set_parent(clk[lvds1_sel], clk[sata_ref]);
++
+       /* Set initial power mode */
+       imx6q_set_lpm(WAIT_CLOCKED);
+