Tamar Christina [Tue, 21 Apr 2020 14:16:21 +0000 (15:16 +0100)]
BFD: Exclude sections with no content from compress check.
The check in bfd_get_full_section_contents is trying to check that we don't
allocate more space for a section than the size of the section is on disk.
Previously we excluded linker created sections since they didn't have a size on
disk. However we also need to exclude sections with no content as well such as
the BSS section. Space for these would not have been allocated by the assembler
and so the check would incorrectly fail.
bfd/ChangeLog:
PR binutils/24753
* compress.c (bfd_get_full_section_contents): Exclude sections with no
content.
gas/ChangeLog:
PR binutils/24753
* testsuite/gas/arm/pr24753.d: New test.
* testsuite/gas/arm/pr24753.s: New test.
Tamar Christina [Wed, 1 Apr 2020 09:47:18 +0000 (10:47 +0100)]
Arm: Fix LSB of GOT for Thumb2 only PLT.
When you have a Thumb only PLT then the address in the GOT for PLT0 needs to
have the Thumb bit set since the instruction used in PLTn to get there is
`ldr.w pc` which is an inter-working instruction:
Tamar Christina [Wed, 1 Apr 2020 09:40:07 +0000 (10:40 +0100)]
Arm: Fix thumb2 PLT branch offsets.
When I previously changed these offsets I had incorrectly used an offset of -2
for this Thumb2 PLT. Unfortunately because we had no tests for this PLT I had
missed that the result was incorrect.
This patch fixes the offset to PC .-4 so that it correctly addresses the
previous instruction and adds a test for this PLT stub.
H.J. Lu [Wed, 25 Mar 2020 13:54:20 +0000 (06:54 -0700)]
plugin: Use LDPT_ADD_SYMBOLS_V2 to get symbol type
Since LTO plugin may generate more than one ltrans.o file from one input
IR object as LTO wrapper ignores -flto-partition=none:
lto-wrapper.c:608:
604 /* Drop arguments that we want to take from the link line. */
605 case OPT_flto_:
606 case OPT_flto:
607 case OPT_flto_partition_:
608 continue;
the LTO wrapper approach is not only slow but also unreliable. Since
the LTO plugin API has been extended to add LDPT_ADD_SYMBOLS_V2 with
symbol type and section kind, we can use LDPT_ADD_SYMBOLS_V2 to get
symbol type, instead of invoking the LTO wrapper.
PR binutils/25640
* plugin.c (plugin_list_entry): Add has_symbol_type.
(add_symbols_v2): New function.
(bfd_plugin_open_input): Don't invoke LTO wrapper if LTO plugin
provides symbol type.
(try_load_plugin): Add LDPT_ADD_SYMBOLS_V2.
(bfd_plugin_canonicalize_symtab): Use LTO plugin symbol type if
available.
PR lto/94249
* plugin-api.h: Add more robust endianess detection.
binutils-gdb/bfd/elf.c: In function ‘setup_group’:
binutils-gdb/bfd/elf.c:740:35: error: overflow in conversion from ‘unsigned int’ to ‘int’ changes value from ‘num_group = 4294967295’ to ‘-1’ [-Werror=overflow]
740 | elf_tdata (abfd)->num_group = num_group = -1;
| ^~~~~~~~~
cc1: all warnings being treated as errors
make[2]: *** [Makefile:1608: elf.lo] Error 1
Change num_group in elf_obj_tdata to unsigned int to compile with GCC 10.
PR binutils/25717
* elf-bfd.h (elf_obj_tdata): Change num_group to unsigned int.
Andre Vieira [Fri, 13 Mar 2020 13:31:56 +0000 (13:31 +0000)]
gas, arm: PR25660L Fix vadd/vsub with lt and le condition codes for MVE
As explained in the PR, the addition of MVE makes the parser strip 't' and 'e'
as suffixes when MVE is enabled. This leads to vadd and vsub in it blocks with
lt and le conditions to be initially parsed as vaddl and vsubl. This means the
operand parsing for these must allow for the same operands as the scalar vadd
and vsub. I had forgotten to do this and this patch remedies that oversight.
gas/ChangeLog:
2020-03-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
Backport from mainline.
2020-03-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 25660
* config/tc-arm.c (operand_parse_code): Add OP_RNSDMQR and OP_oRNSDMQ.
(parse_operands): Handle new operand codes.
(do_neon_dyadic_long): Make shape check accept the scalar variants.
(asm_opcode_insns): Fix operand codes for vaddl and vsubl.
* testsuite/gas/arm/mve-vaddsub-it.s: New test.
* testsuite/gas/arm/mve-vaddsub-it.d: New test.
* testsuite/gas/arm/mve-vaddsub-it-bad.s: New test.
* testsuite/gas/arm/mve-vaddsub-it-bad.l: New test.
* testsuite/gas/arm/mve-vaddsub-it-bad.d: New test.
* testsuite/gas/arm/nomve-vaddsub-it.d: New test.
Alan Modra [Wed, 11 Mar 2020 04:13:16 +0000 (14:43 +1030)]
powerpc64-ld infinite loop
If this code dealing with possible conversion of inline plt sequences
is ever executed, ld will hang. A binary with such sequences and of
code size larger than approximately 90% the reach of an unconditional
branch is the trigger. Oops.
* elf64-ppc.c (ppc64_elf_inline_plt): Do increment rel in for loop.
H.J. Lu [Tue, 25 Feb 2020 11:30:33 +0000 (03:30 -0800)]
Don't call lto-wrapper for ar and ranlib
Since ar and ranlib don't need to know symbol types to work properly,
we should avoid calling lto-wrapper for them to speed them up.
bfd/
PR binutils/25584
* plugin.c (need_lto_wrapper_p): New.
(bfd_plugin_set_program_name): Add an int argument to set
need_lto_wrapper_p.
(get_lto_wrapper): Return FALSE if need_lto_wrapper_p isn't
set.
* plugin.h (bfd_plugin_set_program_name): Add an int argument.
binutils/
PR binutils/25584
* ar.c (main): Pass 0 to bfd_plugin_set_program_name.
* nm.c (main): Pass 1 to bfd_plugin_set_program_name.
Alan Modra [Sat, 22 Feb 2020 02:16:33 +0000 (12:46 +1030)]
PR25585, PHDR segment not covered by LOAD segment
I closed this bug as invalid, but I think it is worth mentioning in NEWS
that older linkers didn't check PT_PHDR very well. The patch also allows
people to force an output file with --noinhibit-exec after the error.
bfd/
PR 25585
* elf.c (assign_file_positions_for_load_sections): Continue linking
on "PHDR segment not covered by LOAD segment" errors.
ld/
PR 25585
* NEWS: Mention better "PHDR segment not covered by LOAD segment"
checking.
Nick Clifton [Sun, 16 Feb 2020 11:33:15 +0000 (11:33 +0000)]
Import fixes for using the LTO plugin with nm.
PR 25355
bfd:
2020-02-13 H.J. Lu <hongjiu.lu@intel.com>
* plugin.c (try_load_plugin): Make plugin_list_iter an argument
and use it if it isn't NULL. Remove has_plugin_p argument. Add
a build_list_p argument. Don't search plugin_list. Short circuit
when building the plugin list.
(has_plugin): Renamed to has_plugin_list.
(bfd_plugin_set_plugin): Don't set has_plugin.
(bfd_plugin_specified_p): Check plugin_list instead.
(build_plugin_list): New function.
(load_plugin): Call build_plugin_list and use plugin_list.
2020-02-11 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/25355
* plugin.c (try_claim): Always clean up for LTO wrapper.
(try_load_plugin): Treat each object as independent. Create a
copy for plugin name.
Nick Clifton [Tue, 11 Feb 2020 15:55:25 +0000 (15:55 +0000)]
Import a fix from the mainline sources that prevents a potential illegal memory access when parsing PE binaries.
PR 25447
* coffgen.c (_bfd_coff_close_and_cleanup): Do not clear the keep
syms and keep strings flags as these may have been set in order to
prevent a bogus call to free.
MSP430: Enable relaxation of jump instructions to hard-coded pcrel offsets
This patch fixes execution failures which occur when the BR in a
sequence such as:
J<cond> 1f
BR
1:
is relaxed to a JMP, and the pc-relative offset for the destination of
the J<cond> instruction is hard-coded to be 2 words ahead of the
instruction.
The hard-coded offset will cause execution to jump 1 word ahead of where
it should actually go.
Instead we now detect the hard-coded offset is one we inserted earlier,
and invert the condition, allowing us to remove the BR entirely.
bfd/ChangeLog:
2020-02-10 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* elf32-msp430.c (msp430_elf_relax_section): Before relaxing a branch,
check if previous instruction matches a conditional jump inserted
earlier. Invert conditional jump and delete branch in this case.
MSP430: Enable relaxation of relocs in JMP instructions
This patch fixes relocation overflows caused by an inability to relax
unconditional JMP instructions to BR instructions.
bfd/ChangeLog:
2020-02-10 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* elf32-msp430.c (msp430_elf_relax_add_two_words): Rename to
msp430_elf_relax_add_words. Support insertion of either one or two
words.
(msp430_elf_relax_section): Catch opcode of 0x3c00 when relocation
needs to be grown. Handle insertion of branch instruction to replace
jump.
H.J. Lu [Mon, 10 Feb 2020 16:37:22 +0000 (08:37 -0800)]
x86: Accept Intel64 only instruction by default
Commit d835a58baae720 disabled sysenter/sysenter in 64-bit mode by
default. By default, assembler should accept common, Intel64 only
and AMD64 ISAs since there are no conflicts.
gas/
PR gas/25516
* config/tc-i386.c (intel64): Renamed to ...
(isa64): This.
(match_template): Accept Intel64 only instruction by default.
(i386_displacement): Updated.
(md_parse_option): Updated.
* c-i386.texi: Update -mamd64/-mintel64 documentation.
* testsuite/gas/i386/i386.exp: Run x86-64-sysenter. Pass
-mamd64 to x86-64-sysenter-amd.
* testsuite/gas/i386/x86-64-sysenter.d: New file.
opcodes/
PR gas/25516
* i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
with ISA64.
* i386-opc.h (AMD64): Removed.
(Intel64): Likewose.
(AMD64): New.
(INTEL64): Likewise.
(INTEL64ONLY): Likewise.
(i386_opcode_modifier): Replace amd64 and intel64 with isa64.
* i386-opc.tbl (Amd64): New.
(Intel64): Likewise.
(Intel64Only): Likewise.
Replace AMD64 with Amd64. Update sysenter/sysenter with
Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
* i386-tbl.h: Regenerated.
bfcvt converts a .S input to a .H output, so any predicated movprfx
needs to operate on .S rather than .H. In common with SVE2 narrowing
top operations, bfcvtnt doesn't accept movprfx.
2020-02-10 Richard Sandiford <richard.sandiford@arm.com>
opcodes/
* aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
gas/
* testsuite/gas/aarch64/sve-bfloat-movprfx.s: Use .h rather than
.s for the movprfx.
* testsuite/gas/aarch64/sve-bfloat-movprfx.d: Update accordingly.
* testsuite/gas/aarch64/sve-movprfx_28.d,
* testsuite/gas/aarch64/sve-movprfx_28.l,
* testsuite/gas/aarch64/sve-movprfx_28.s: New test.