Alan Modra [Wed, 11 Mar 2020 04:13:16 +0000 (14:43 +1030)]
powerpc64-ld infinite loop
If this code dealing with possible conversion of inline plt sequences
is ever executed, ld will hang. A binary with such sequences and of
code size larger than approximately 90% the reach of an unconditional
branch is the trigger. Oops.
* elf64-ppc.c (ppc64_elf_inline_plt): Do increment rel in for loop.
Alan Modra [Wed, 15 Jan 2020 05:45:43 +0000 (16:15 +1030)]
Reinstate gas em=freebsd for sparc-freebsd
In commit c9098af41e3 I over-simplified the sparc target decoding,
missing the fact that prior to that patch sparc-*-freebsd fell through
to the generic *-*-freebsd match.
Alan Modra [Tue, 14 Jan 2020 10:15:53 +0000 (20:45 +1030)]
PR25384, PowerPC64 ELFv1 copy relocs against function symbols
Function symbols of course don't normally want .dynbss copies but
with some old versions of gcc they are needed to copy the function
descriptor. This patch restricts the cases where they are useful to
compilers using dot-symbols, and enables the warning regardless of
whether a PLT entry is emitted in the executable. PLTs in shared
libraries are affected by a .dynbss copy in the executable.
bfd/
PR 25384
* elf64-ppc.c (ELIMINATE_COPY_RELOCS): Update comment.
(ppc64_elf_adjust_dynamic_symbol): Don't allow .dynbss copies
of function symbols unless dot symbols are present. Do warn
whenever one is created, regardles of whether a PLT entry is
also emitted for the function symbol.
ld/
* testsuite/ld-powerpc/ambiguousv1b.d: Adjust expected output.
* testsuite/ld-powerpc/funref.s: Align func_tab.
* testsuite/ld-powerpc/funref2.s: Likewise.
* testsuite/ld-powerpc/funv1.s: Add dot symbols.
Eric Botcazou [Thu, 5 Sep 2019 16:23:37 +0000 (18:23 +0200)]
Fix PR ld/24574
This restores a line that has been dropped when the auto-import feature
of the PE-COFF linker was overhauled about one year. It is necessary
for GDB to properly resolve extern symbol in DLLs.
ld/ChangeLog
* pe-dll.c (pe_find_data_imports): Replace again the original name
of the undefined symbol with the __imp_ prefixed one after it is
resolved.
Tamar Christina [Tue, 20 Aug 2019 15:34:26 +0000 (16:34 +0100)]
Arm: Fix performance issue with thumb-2 tailcalls
We currently use a padding NOP after a Thumb to Arm interworking veneer (BX pc).
The NOP is never executed but may result in a performance penalty on some cores.
For this reason this patch changes the NOPs after Thumb to Arm veneers into B .-2
and adds a note to this in the source code for future reference.
bfd/ChangeLog:
* elf32-arm.c (elf32_thumb2_plt_entry, elf32_arm_plt_thumb_stub,
elf32_arm_stub_long_branch_v4t_thumb_thumb,
elf32_arm_stub_long_branch_v4t_thumb_arm,
elf32_arm_stub_short_branch_v4t_thumb_arm,
elf32_arm_stub_long_branch_v4t_thumb_arm_pic,
elf32_arm_stub_long_branch_v4t_thumb_thumb_pic,
elf32_arm_stub_long_branch_v4t_thumb_tls_pic): Change nop to branch to
previous instruction.
Tamar Christina [Thu, 22 Aug 2019 10:35:35 +0000 (11:35 +0100)]
AArch64: Fix LD crash on weak and undefined TLS symbols. (PR/24602).
This patch fixes a few linker crashes due to TLS code reaching an assert when it
shouldn't.
The first scenario is with weak TLS symbols that remain weak during linking. In
this case the mid-end would not have seen a TLS symbol and so wouldn't have
allocated the TLS section. We currently assert here and the linker crashes with
a not very useful message.
This patch changes this to return the value 0 for the TLS symbol in question
emulating what lld and gold and other BFD targets do. However because weak TLS
is implementation defined and we don't define any behavior for it I also emit a
warning to the user to inform them of such.
Secondly when a strong TLS reference is undefined. The linker crashes even after
it correctly reported that there is an undefined reference. This changes it so
that it gracefully exits and reports a useful error.
bfd/ChangeLog:
PR ld/24601
* elfnn-aarch64.c (aarch64_relocate): Handle weak TLS and undefined TLS.
Also Pass input_bfd to _bfd_aarch64_elf_resolve_relocation.
* elfxx-aarch64.c (_bfd_aarch64_elf_resolve_relocation): Use it.
* elfxx-aarch64.h (_bfd_aarch64_elf_resolve_relocation): Emit warning
for weak TLS.
ld/ChangeLog:
PR ld/24601
* testsuite/ld-aarch64/aarch64-elf.exp (undef-tls, weak-tls): New.
* testsuite/ld-aarch64/undef-tls.d: New test.
* testsuite/ld-aarch64/undef-tls.s: New test.
* testsuite/ld-aarch64/weak-tls.d: New test.
* testsuite/ld-aarch64/weak-tls.s: New test.
Alan Modra [Fri, 16 Aug 2019 03:50:28 +0000 (13:20 +0930)]
PowerPC gcc bootstrap fail with bss-plt
git commit 3e04d7655b introduced a bug by sizing output sections
earlier in ppc_before_allocation. That meant PLT (and GOT) sizes were
not included when calculating total executable section sizes.
* emultempl/ppc32elf.em (ppc_before_allocation): Force running
prelim_size_sections before deciding whether branch trampolines
might be needed.
[ARM]: Correct the regular expressions in cmse_main_sec_debug.d file.
Fixes the linker testcase "Secure gateway veneers:cmse functions debug
information missing" which was failing due to output regular expression
mismatch on arm-none-linux-gnueabihf targets.
* ld/testsuite/ld-arm/cmse_main_sec_debug.d: Modify regexps to
allow for output from a arm-none-linux-gnueabihf target.
[AArch64] Add support for GMID_EL1 register for +memtag
We're missing support for the GMID_EL1 system register from the Memory Tagging Extension in binutils.
This is specified at:
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/gmid_el1
This simple patch adds the support for this read-only register.
Tested make check on gas.
Backport from mainline
2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* testsuite/ld-aarch64/aarch64-elf.exp: Add new tests.
* testsuite/ld-aarch64/variant_pcs-1.s: New asm for tests.
* testsuite/ld-aarch64/variant_pcs-2.s: New asm for tests.
* testsuite/ld-aarch64/variant_pcs-now.d: New test.
* testsuite/ld-aarch64/variant_pcs-r.d: New test.
* testsuite/ld-aarch64/variant_pcs-shared.d: New test.
* testsuite/ld-aarch64/variant_pcs.ld: New linker script for tests.
ld/ChangeLog:
* testsuite/ld-aarch64/variant_pcs-now.d: Use --hash-style=sysv.
* testsuite/ld-aarch64/variant_pcs-shared.d: Likewise.
Allow st_other values such as STO_AARCH64_VARIANT_PCS to be set for alias
symbols independently. This is needed for ifunc symbols which are
aliased to the resolver using .set and don't expect resolver attributes
to override the ifunc symbol attributes. This means .variant_pcs must be
added explicitly to aliases.
gas/ChangeLog:
* config/tc-aarch64.c (aarch64_elf_copy_symbol_attributes): Define.
* config/tc-aarch64.h (aarch64_elf_copy_symbol_attributes): Declare.
(OBJ_COPY_SYMBOL_ATTRIBUTES): Define.
* testsuite/gas/aarch64/symbol-variant_pcs-3.d: New test.
* testsuite/gas/aarch64/symbol-variant_pcs-3.s: New test.
In ELF objects the specified symbol is marked with STO_AARCH64_VARIANT_PCS.
gas/ChangeLog:
* config/tc-aarch64.c (s_variant_pcs): New function.
* doc/c-aarch64.texi: Document .variant_pcs.
* testsuite/gas/aarch64/symbol-variant_pcs-1.d: New test.
* testsuite/gas/aarch64/symbol-variant_pcs-1.s: New test.
* testsuite/gas/aarch64/symbol-variant_pcs-2.d: New test.
* testsuite/gas/aarch64/symbol-variant_pcs-2.s: New test.
The bottom 2 bits of st_other are used for visibility, the top 6 bits are
de facto reserved for processor specific use. This patch defines a
bits to mark function symbols that follow a variant procedure call standard
with different register usage convention.
A dynamic tag is also defined that marks modules with R_<CLS>_JUMP_SLOT
relocations referencing symbols marked with STO_AARCH64_VARIANT_PCS.
This can be used by dynamic linkers that support lazy binding to decide
what registers need to be preserved during symbol resolution.
Ensure that debug information for ARM security functions is not dropped by the linker when performing garbage collection.
onsider a file containing only Armv8-M secure entry functions.
This file is compiled and linked with "-march=armv8-m.main -mfloat-abi=hard
-mfpu=fpv5-sp-d16 -mcmse -static --specs=rdimon.specs
-Wl,--section-start,.gnu.sgstubs=0x190000 -ffunction-sections
-fdata-sections
-Wl,--gc-sections -g" options to generate an executable.
The executable generated does not contain any debug information of these
secure entry
functions even though it contains secure entry functions in the .text
section.
Example:
$ cat main.c
int main (void)
{
return 0;
}
[AArch64] Add missing C_MAX_ELEM flags for SVE conversions
SVE FCVTZS, FCVTZU, SCVTF and UCVTF need the same treatment as FCVT:
the register size used in a predicated MOVPRFX must be the wider of
the destination and source sizes.
Since I was adding a (supposedly) complete set of tests for converts,
it seemed more consistent to add a complete set of tests for shifts
as well, even though there's no bug to fix there.
2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
opcodes/
* aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
gas/
* testsuite/gas/aarch64/sve-movprfx_26.s: Also test FCVTZS, FCVTZU,
SCVTF, UCVTF, LSR and ASR.
* testsuite/gas/aarch64/sve-movprfx_26.d: Update accordingly.
* testsuite/gas/aarch64/sve-movprfx_26.l: Likewise.
projects / thirdparty / binutils-gdb.git / log
