| 2024-03-28 |
 Nelson Chu | RISC-V: Removed privileged spec 1.9.1 support in assembler.
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commit | commitdiff | tree |
| 2024-03-18 |
Nelson Chu | RISC-V: Tidy smstateen and ssstateen testcases.
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commit | commitdiff | tree |
| 2024-02-21 |
Nelson Chu | RISC-V: Don't generate branch/jump relocation if symbol...
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commit | commitdiff | tree |
| 2023-12-28 |
Nelson Chu | RISC-V: PR31179, The SET/ADD/SUB fix breaks ABI compatibilit...
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commit | commitdiff | tree |
| 2023-12-11 |
Nelson Chu | RISC-V/gas: Clarify the definition of `relaxable' in...
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commit | commitdiff | tree |
| 2023-12-01 |
Nelson Chu | RISC-V: Update gas/NEWS for RISC-V vendor extension...
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commit | commitdiff | tree |
| 2023-12-01 |
 Nelson Chu | RISC-V: Add SiFive custom vector coprocessor interface...
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commit | commitdiff | tree |
| 2023-11-06 |
Nelson Chu | RISC-V: Make sure rv32q conflict won't affect the fp...
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commit | commitdiff | tree |
| 2023-11-06 |
Nelson Chu | RISC-V: Moved out linker internal relocations after...
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commit | commitdiff | tree |
| 2023-10-27 |
Nelson Chu | RISC-V: Clarify the behaviors of SET/ADD/SUB relocations.
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commit | commitdiff | tree |
| 2023-10-19 |
Nelson Chu | RISC-V: Don't do undefweak relaxations for the linker_def...
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commit | commitdiff | tree |
| 2023-10-18 |
Nelson Chu | RISC-V: Make sure rv32q conflict won't affect the zfa...
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commit | commitdiff | tree |
| 2023-09-07 |
Nelson Chu | RISC-V: Clarify the naming rules of vendor operands.
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commit | commitdiff | tree |
| 2023-09-01 |
Nelson Chu | RISC-V: Fixed the wrong expansion for pseudo vmsge...
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commit | commitdiff | tree |
| 2023-08-18 |
Nelson Chu | RISC-V: Report "c or zca" for INSN_CLASS_C when error...
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commit | commitdiff | tree |
| 2023-06-01 |
Nelson Chu | [PR ld/22263][PR ld/24676] RISC-V: Avoid spurious R_RISCV_NO...
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commit | commitdiff | tree |
| 2023-05-27 |
 Nelson Chu | [PR ld/22263][PR ld/25694] RISC-V: Avoid dynamic TLS...
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commit | commitdiff | tree |
| 2023-05-19 |
Nelson Chu | RISC-V: Minor improvements for dis-assembler.
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commit | commitdiff | tree |
| 2023-04-28 |
Nelson Chu | RISC-V: Enable x0 base relaxation for relax_pc even...
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commit | commitdiff | tree |
| 2023-04-28 |
Nelson Chu | RISC-V: Relax R_RISCV_[PCREL_]LO12_I/S to R_RISCV_GPREL_I...
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commit | commitdiff | tree |
| 2023-03-29 |
Nelson Chu | RISC-V: Clarify link behaviors of R_RISCV_32/64 relocations...
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commit | commitdiff | tree |
| 2023-03-29 |
Nelson Chu | RISC-V: Extract the ld code which are too complicated...
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commit | commitdiff | tree |
| 2022-12-23 |
Nelson Chu | RISC-V: Relax the order checking for the architecture...
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commit | commitdiff | tree |
| 2022-11-02 |
Nelson Chu | RISC-V: Fixed the missing $x+arch when adding odd paddings...
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commit | commitdiff | tree |
| 2022-10-29 |
Nelson Chu | RISC-V: Always generate mapping symbols at the start...
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commit | commitdiff | tree |
| 2022-10-28 |
Nelson Chu | RISC-V: Output mapping symbols with ISA string.
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commit | commitdiff | tree |
| 2022-10-27 |
Nelson Chu | RISC-V: Fix build failures for -Werror=sign-compare.
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commit | commitdiff | tree |
| 2022-10-25 |
Nelson Chu | RISC-V: Should reset `again' flag for _bfd_riscv_relax_pc.
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commit | commitdiff | tree |
| 2022-10-04 |
Nelson Chu | RISC-V: Renamed INSN_CLASS for floating point in integer...
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commit | commitdiff | tree |
| 2022-09-21 |
Nelson Chu | RISC-V: Always generate R_RISCV_CALL_PLT reloc for...
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commit | commitdiff | tree |
| 2022-09-16 |
Nelson Chu | RISC-V: Make g imply zmmul extension.
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commit | commitdiff | tree |
| 2022-09-12 |
Nelson Chu | RISC-V: PR28509, the default visibility symbol cannot...
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commit | commitdiff | tree |
| 2022-08-23 |
Nelson Chu | binutils: Updated my email address.
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commit | commitdiff | tree |
| 2022-06-22 |
Nelson Chu | RISC-V: Reorder the prefixed extensions which are out...
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commit | commitdiff | tree |
| 2022-06-22 |
Nelson Chu | RISC-V: Use single h extension to control hypervisor...
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commit | commitdiff | tree |
| 2022-05-17 |
Nelson Chu | RISC-V: Added half-precision floating-point v1.0 instructions.
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commit | commitdiff | tree |
| 2022-02-23 |
Nelson Chu | RISC-V: Updated CSRs to privileged spec v1.12 and debug...
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commit | commitdiff | tree |
| 2022-01-07 |
Nelson Chu | RISC-V: Updated the default ISA spec to 20191213.
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commit | commitdiff | tree |
| 2021-12-24 |
Nelson Chu | RISC-V: Rewrite the csr testcases.
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commit | commitdiff | tree |
| 2021-12-16 |
Nelson Chu | RISC-V: Support svinval extension with frozen version...
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commit | commitdiff | tree |
| 2021-12-14 |
Nelson Chu | RISC-V: Added ld testcases for the medlow and medany...
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commit | commitdiff | tree |
| 2021-12-09 |
Nelson Chu | RISC-V: Clarify the behavior of .option arch directive.
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commit | commitdiff | tree |
| 2021-11-30 |
Nelson Chu | RISC-V: The vtype immediate with more than the defined...
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commit | commitdiff | tree |
| 2021-11-30 |
Nelson Chu | RISC-V: Dump vset[i]vli immediate as numbers once vsew...
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commit | commitdiff | tree |
| 2021-11-22 |
Nelson Chu | RISC-V: Removed the redundant NULL pointer check in...
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commit | commitdiff | tree |
| 2021-11-22 |
Nelson Chu | RISC-V: Replace .option rvc/norvc with .option arch...
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commit | commitdiff | tree |
| 2021-11-22 |
Nelson Chu | RISC-V: PR28610, Fix ASAN heap-buffer-overflow error...
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commit | commitdiff | tree |
| 2021-11-19 |
Nelson Chu | RISC-V: Support new .option arch directive.
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commit | commitdiff | tree |
| 2021-11-19 |
Nelson Chu | RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC.
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commit | commitdiff | tree |
| 2021-11-17 |
Nelson Chu | RISC-V: Support rvv extension with released version...
Nelson Chu <nelson.chu@sifive.com>
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commit | commitdiff | tree |
| 2021-11-11 |
Nelson Chu | RISC-V: Dump objects according to the elf architecture...
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commit | commitdiff | tree |
| 2021-11-04 |
Nelson Chu | RISC-V: Clarify the behavior of .option rvc or norvc.
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commit | commitdiff | tree |
| 2021-10-27 |
Nelson Chu | RISC-V: Tidy riscv assembler and disassembler.
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commit | commitdiff | tree |
| 2021-09-28 |
Nelson Chu | RISC-V: Allow to add numbers in the prefixed extension...
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commit | commitdiff | tree |
| 2021-09-17 |
Nelson Chu | RISC-V: Merged extension string tables and their version...
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commit | commitdiff | tree |
| 2021-09-13 |
Nelson Chu | RISC-V: Update the assembler insn testcase.
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commit | commitdiff | tree |
| 2021-08-31 |
Nelson Chu | RISC-V: Extend .insn directive to support hardcode...
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commit | commitdiff | tree |
| 2021-08-30 |
Nelson Chu | RISC-V: PR28291, Fix the gdb fails that PR27916 caused.
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commit | commitdiff | tree |
| 2021-08-30 |
Nelson Chu | RISC-V: PR27916, Support mapping symbols.
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commit | commitdiff | tree |
| 2021-07-20 |
Nelson Chu | RISC-V: Minor updates for architecture parser.
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commit | commitdiff | tree |
| 2021-07-13 |
Nelson Chu | RISC-V: Enable elf attributes when default configure...
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commit | commitdiff | tree |
| 2021-07-06 |
Nelson Chu | RISC-V: Fix the build broken with -Werror.
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commit | commitdiff | tree |
| 2021-06-22 |
Nelson Chu | RISC-V: Clarify the addends of pc-relative access.
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commit | commitdiff | tree |
| 2021-06-11 |
Nelson Chu | RISC-V: Update the riscv_opts.[rvc|rve] in the riscv_set_arch.
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commit | commitdiff | tree |
| 2021-05-31 |
Nelson Chu | RISC-V: PR27566, Do not relax when data segment phase...
2021-05-31 Nelson Chu <nelson.chu@sifive.com>
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commit | commitdiff | tree |
| 2021-05-26 |
Nelson Chu | RISC-V: Allow to link the objects with unknown prefixed...
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commit | commitdiff | tree |
| 2021-05-24 |
Nelson Chu | RISC-V: PR25212, Report errors for invalid march and...
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commit | commitdiff | tree |
| 2021-05-14 |
Nelson Chu | RISC-V: Check the overflow for %pcrel_lo addend more...
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commit | commitdiff | tree |
| 2021-05-13 |
Nelson Chu | RISC-V: Record implicit subsets in a table, to avoid...
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commit | commitdiff | tree |
| 2021-04-16 |
Nelson Chu | RISC-V: PR27436, make operand C> work the same as >.
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commit | commitdiff | tree |
| 2021-04-16 |
Nelson Chu | Update the ChangeLog, and add the missing entries.
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commit | commitdiff | tree |
| 2021-04-15 |
Nelson Chu | RISC-V: PR27584, surpress local and empty name symbols...
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commit | commitdiff | tree |
| 2021-04-13 |
Nelson Chu | RISC-V: Don't report the mismatched version warning...
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commit | commitdiff | tree |
| 2021-04-12 |
Nelson Chu | RISC-V: The version of i-ext should be RISCV_UNKNOWN_VERSION...
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commit | commitdiff | tree |
| 2021-04-12 |
Nelson Chu | RISC-V: Add i-ext as the implicit extension when e...
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commit | commitdiff | tree |
| 2021-04-12 |
Nelson Chu | RISC-V: Support to parse the multi-letter prefix in...
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commit | commitdiff | tree |
| 2021-03-11 |
Nelson Chu | RISC-V: Improve multiple relax passes problem.
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commit | commitdiff | tree |
| 2021-02-19 |
Nelson Chu | RISC-V: PR27158, fixed UJ/SB types and added CSS/CL...
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commit | commitdiff | tree |
| 2021-02-18 |
Nelson Chu | RISC-V: Add bfd/cpu-riscv.h to support all spec versions...
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commit | commitdiff | tree |
| 2021-02-17 |
Nelson Chu | RISC-V: PR27200, allow the first input non-ABI binary...
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commit | commitdiff | tree |
| 2021-02-05 |
Nelson Chu | RISC-V: PR27348, Remove the obsolete OP_*CUSTOM_IMM.
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commit | commitdiff | tree |
| 2021-02-05 |
Nelson Chu | RISC-V: PR27348, Remove obsolete Xcustom support.
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commit | commitdiff | tree |
| 2021-02-04 |
Nelson Chu | RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions.
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commit | commitdiff | tree |
| 2021-01-19 |
Nelson Chu | ld: Just xfail riscv little endian targets for compressed1d...
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commit | commitdiff | tree |
| 2021-01-15 |
Nelson Chu | RISC-V: Fixed the indent that caused by the previous...
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commit | commitdiff | tree |
| 2021-01-15 |
Nelson Chu | RISC-V: Indent and GNU coding standards tidy, also...
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commit | commitdiff | tree |
| 2021-01-15 |
Nelson Chu | RISC-V: Error and warning messages tidy.
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commit | commitdiff | tree |
| 2021-01-15 |
Nelson Chu | RISC-V: Comments tidy and improvement.
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commit | commitdiff | tree |
| 2021-01-05 |
Nelson Chu | RISC-V: Ouput __global_pointer$ as dynamic symbol when...
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commit | commitdiff | tree |
| 2021-01-04 |
Nelson Chu | RISC-V: Fix the merged orders of Z* extension for linker.
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commit | commitdiff | tree |
| 2020-12-10 |
Nelson Chu | RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.
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commit | commitdiff | tree |
| 2020-12-10 |
Nelson Chu | RISC-V: Dump CSR according to the elf privileged spec...
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commit | commitdiff | tree |
| 2020-12-10 |
Nelson Chu | RISC-V: Control fence.i and csr instructions by zifencei...
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commit | commitdiff | tree |
| 2020-12-01 |
Nelson Chu | RISC-V: Fix the order checking for Z* extension.
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commit | commitdiff | tree |
| 2020-12-01 |
Nelson Chu | RISC-V: Support to add implicit extensions for G.
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commit | commitdiff | tree |
| 2020-12-01 |
Nelson Chu | RISC-V: Support to add implicit extensions.
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commit | commitdiff | tree |
| 2020-12-01 |
Nelson Chu | RISC-V: Improve the version parsing for arch string.
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commit | commitdiff | tree |
| 2020-12-01 |
Nelson Chu | RISC-V: Remove the unimplemented extensions.
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commit | commitdiff | tree |
| 2020-12-01 |
Nelson Chu | RISC-V: Add zifencei and prefixed h class extensions.
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commit | commitdiff | tree |
| 2020-12-01 |
Nelson Chu | RISC-V: Don't allow any uppercase letter in the arch...
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commit | commitdiff | tree |
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