fix(Makefile): reduce the number of shell invocations

fix(Makefile): reduce the number of shell invocations

Makefile uses recursively expanded macros and as can be seen by simply
adding $(warning Call to shell) in front of $(shell ...) Foo's in the
Makefile, we are calling out to shell 9 times just to get the working
directory, a working directory which doesn't change during Make!

Let's save few pony's and reduce it to 2...