RISC-V: Fix --enable-checking=rtl ICE on rv32gc bootstrap

RISC-V: Fix --enable-checking=rtl ICE on rv32gc bootstrap

Resolves PR 111461.

during RTL pass: expand
offtime.c: In function '__offtime':
offtime.c:79:6: internal compiler error: RTL check: expected elt 0 type 'e' or 'u', have 'w' (rtx const_int) in riscv_legitimize_const_move, at config/riscv/riscv.cc:2176
   79 |   ip = __mon_yday[__isleap(y)];

Tested on rv32gc glibc with --enable-checking=rtl.

2023-09-19 Juzhe Zhong <juzhe.zhong@rivai.ai>

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_legitimize_const_move): Eliminate
	src_op_0 var to avoid rtl check error.

Tested-by: Patrick O'Neill <patrick@rivosinc.com>